Upgrade to valgrind 3.12.0.
Release 3.12.0 (20 October 2016)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3.12.0 is a feature release with many improvements and the usual
collection of bug fixes.
This release supports X86/Linux, AMD64/Linux, ARM32/Linux,
ARM64/Linux, PPC32/Linux, PPC64BE/Linux, PPC64LE/Linux, S390X/Linux,
MIPS32/Linux, MIPS64/Linux, ARM/Android, ARM64/Android,
MIPS32/Android, X86/Android, X86/Solaris, AMD64/Solaris, X86/MacOSX
10.10 and AMD64/MacOSX 10.10. There is also preliminary support for
X86/MacOSX 10.11/12, AMD64/MacOSX 10.11/12 and TILEGX/Linux.
* ================== PLATFORM CHANGES =================
* POWER: Support for ISA 3.0 has been added
* mips: support for O32 FPXX ABI has been added.
* mips: improved recognition of different processors
* mips: determination of page size now done at run time
* amd64: Partial support for AMD FMA4 instructions.
* arm, arm64: Support for v8 crypto and CRC instructions.
* Improvements and robustification of the Solaris port.
* Preliminary support for MacOS 10.12 (Sierra) has been added.
Whilst 3.12.0 continues to support the 32-bit x86 instruction set, we
would prefer users to migrate to 64-bit x86 (a.k.a amd64 or x86_64)
where possible. Valgrind's support for 32-bit x86 has stagnated in
recent years and has fallen far behind that for 64-bit x86
instructions. By contrast 64-bit x86 is well supported, up to and
including AVX2.
* ==================== TOOL CHANGES ====================
* Memcheck:
- Added meta mempool support for describing a custom allocator which:
- Auto-frees all chunks assuming that destroying a pool destroys all
objects in the pool
- Uses itself to allocate other memory blocks
- New flag --ignore-range-below-sp to ignore memory accesses below
the stack pointer, if you really have to. The related flag
--workaround-gcc296-bugs=yes is now deprecated. Use
--ignore-range-below-sp=1024-1 as a replacement.
* DRD:
- Improved thread startup time significantly on non-Linux platforms.
* DHAT
- Added collection of the metric "tot-blocks-allocd"
* ==================== OTHER CHANGES ====================
* Replacement/wrapping of malloc/new related functions is now done not just
for system libraries by default, but for any globally defined malloc/new
related function (both in shared libraries and statically linked alternative
malloc implementations). The dynamic (runtime) linker is excluded, though.
To only intercept malloc/new related functions in
system libraries use --soname-synonyms=somalloc=nouserintercepts (where
"nouserintercepts" can be any non-existing library name).
This new functionality is not implemented for MacOS X.
* The maximum number of callers in a suppression entry is now equal to
the maximum size for --num-callers (500).
Note that --gen-suppressions=yes|all similarly generates suppressions
containing up to --num-callers frames.
* New and modified GDB server monitor features:
- Valgrind's gdbserver now accepts the command 'catch syscall'.
Note that you must have GDB >= 7.11 to use 'catch syscall' with
gdbserver.
* New option --run-cxx-freeres=<yes|no> can be used to change whether
__gnu_cxx::__freeres() cleanup function is called or not. Default is
'yes'.
* Valgrind is able to read compressed debuginfo sections in two formats:
- zlib ELF gABI format with SHF_COMPRESSED flag (gcc option -gz=zlib)
- zlib GNU format with .zdebug sections (gcc option -gz=zlib-gnu)
* Modest JIT-cost improvements: the cost of instrumenting code blocks
for the most common use case (x86_64-linux, Memcheck) has been
reduced by 10%-15%.
* Improved performance for programs that do a lot of discarding of
instruction address ranges of 8KB or less.
* The C++ symbol demangler has been updated.
* More robustness against invalid syscall parameters on Linux.
* ==================== FIXED BUGS ====================
The following bugs have been fixed or resolved. Note that "n-i-bz"
stands for "not in bugzilla" -- that is, a bug that was reported to us
but never got a bugzilla entry. We encourage you to file bugs in
bugzilla (https://bugs.kde.org/enter_bug.cgi?product=valgrind) rather
than mailing the developers (or mailing lists) directly -- bugs that
are not entered into bugzilla tend to get forgotten about or ignored.
To see details of a given bug, visit
https://bugs.kde.org/show_bug.cgi?id=XXXXXX
where XXXXXX is the bug number as listed below.
191069 Exiting due to signal not reported in XML output
199468 Suppressions: stack size limited to 25
while --num-callers allows more frames
212352 vex amd64 unhandled opc_aux = 0x 2, first_opcode == 0xDC (FCOM)
278744 cvtps2pd with redundant RexW
303877 valgrind doesn't support compressed debuginfo sections.
345307 Warning about "still reachable" memory when using libstdc++ from gcc 5
348345 Assertion fails for negative lineno
351282 V 3.10.1 MIPS softfloat build broken with GCC 4.9.3 / binutils 2.25.1
351692 Dumps created by valgrind are not readable by gdb (mips32 specific)
351804 Crash on generating suppressions for "printf" call on OS X 10.10
352197 mips: mmap2() not wrapped correctly for page size > 4096
353083 arm64 doesn't implement various xattr system calls
353084 arm64 doesn't support sigpending system call
353137 www: update info for Supported Platforms
353138 www: update "The Valgrind Developers" page
353370 don't advertise RDRAND in cpuid for Core-i7-4910-like avx2 machine
== 365325
== 357873
353384 amd64->IR: 0x66 0xF 0x3A 0x62 0xD1 0x62 (pcmpXstrX $0x62)
353398 WARNING: unhandled amd64-solaris syscall: 207
353660 XML in auxwhat tag not escaping reserved symbols properly
353680 s390x: Crash with certain glibc versions due to non-implemented TBEGIN
353727 amd64->IR: 0x66 0xF 0x3A 0x62 0xD1 0x72 (pcmpXstrX $0x72)
353802 ELF debug info reader confused with multiple .rodata sections
353891 Assert 'bad_scanned_addr < VG_ROUNDDN(start+len, sizeof(Addr))' failed
353917 unhandled amd64-solaris syscall fchdir(120)
353920 unhandled amd64-solaris syscall: 170
354274 arm: unhandled instruction: 0xEBAD 0x0AC1 (sub.w sl, sp, r1, lsl #3)
354392 unhandled amd64-solaris syscall: 171
354797 Vbit test does not include Iops for Power 8 instruction support
354883 tst->os_state.pthread - magic_delta assertion failure on OSX 10.11
== 361351
== 362920
== 366222
354933 Fix documentation of --kernel-variant=android-no-hw-tls option
355188 valgrind should intercept all malloc related global functions
355454 do not intercept malloc related symbols from the runtime linker
355455 stderr.exp of test cases wrapmalloc and wrapmallocstatic overconstrained
356044 Dwarf line info reader misinterprets is_stmt register
356112 mips: replace addi with addiu
356393 valgrind (vex) crashes because isZeroU happened
== 363497
== 364497
356676 arm64-linux: unhandled syscalls 125, 126 (sched_get_priority_max/min)
356678 arm64-linux: unhandled syscall 232 (mincore)
356817 valgrind.h triggers compiler errors on MSVC when defining NVALGRIND
356823 Unsupported ARM instruction: stlex
357059 x86/amd64: SSE cvtpi2ps with memory source does transition to MMX state
357338 Unhandled instruction for SHA instructions libcrypto Boring SSL
357673 crash if I try to run valgrind with a binary link with libcurl
357833 Setting RLIMIT_DATA to zero breaks with linux 4.5+
357871 pthread_spin_destroy not properly wrapped
357887 Calls to VG_(fclose) do not close the file descriptor
357932 amd64->IR: accept redundant REX prefixes for {minsd,maxsd} m128, xmm.
358030 support direct socket calls on x86 32bit (new in linux 4.3)
358478 drd/tests/std_thread.cpp doesn't build with GCC6
359133 Assertion 'eltSzB <= ddpa->poolSzB' failed
359181 Buffer Overflow during Demangling
359201 futex syscall "skips" argument 5 if op is FUTEX_WAIT_BITSET
359289 s390x: popcnt (B9E1) not implemented
359472 The Power PC vsubuqm instruction doesn't always give the correct result
359503 Add missing syscalls for aarch64 (arm64)
359645 "You need libc6-dbg" help message could be more helpful
359703 s390: wire up separate socketcalls system calls
359724 getsockname might crash - deref_UInt should call safe_to_deref
359733 amd64 implement ld.so strchr/index override like x86
359767 Valgrind does not support the IBM POWER ISA 3.0 instructions, part 1/5
359829 Power PC test suite none/tests/ppc64/test_isa_2_07.c uses
uninitialized data
359838 arm64: Unhandled instruction 0xD5033F5F (clrex)
359871 Incorrect mask handling in ppoll
359952 Unrecognised PCMPESTRM variants (0x70, 0x19)
360008 Contents of Power vr registers contents is not printed correctly when
the --vgdb-shadow-registers=yes option is used
360035 POWER PC instruction bcdadd and bcdsubtract generate result with
non-zero shadow bits
360378 arm64: Unhandled instruction 0x5E280844 (sha1h s4, s2)
360425 arm64 unsupported instruction ldpsw
== 364435
360519 none/tests/arm64/memory.vgtest might fail with newer gcc
360571 Error about the Android Runtime reading below the stack pointer on ARM
360574 Wrong parameter type for an ashmem ioctl() call on Android and ARM64
360749 kludge for multiple .rodata sections on Solaris no longer needed
360752 raise the number of reserved fds in m_main.c from 10 to 12
361207 Valgrind does not support the IBM POWER ISA 3.0 instructions, part 2/5
361226 s390x: risbgn (EC59) not implemented
361253 [s390x] ex_clone.c:42: undefined reference to `pthread_create'
361354 ppc64[le]: wire up separate socketcalls system calls
361615 Inconsistent termination for multithreaded process terminated by signal
361926 Unhandled Solaris syscall: sysfs(84)
362009 V dumps core on unimplemented functionality before threads are created
362329 Valgrind does not support the IBM POWER ISA 3.0 instructions, part 3/5
362894 missing (broken) support for wbit field on mtfsfi instruction (ppc64)
362935 [AsusWRT] Assertion 'sizeof(TTEntryC) <= 88' failed
362953 Request for an update to the Valgrind Developers page
363680 add renameat2() support
363705 arm64 missing syscall name_to_handle_at and open_by_handle_at
363714 ppc64 missing syscalls sync, waitid and name_to/open_by_handle_at
363858 Valgrind does not support the IBM POWER ISA 3.0 instructions, part 4/5
364058 clarify in manual limitations of array overruns detections
364413 pselect sycallwrapper mishandles NULL sigmask
364728 Power PC, missing support for several HW registers in
get_otrack_shadow_offset_wrk()
364948 Valgrind does not support the IBM POWER ISA 3.0 instructions, part 5/5
365273 Invalid write to stack location reported after signal handler runs
365912 ppc64BE segfault during jm-insns test (RELRO)
366079 FPXX Support for MIPS32 Valgrind
366138 Fix configure errors out when using Xcode 8 (clang 8.0.0)
366344 Multiple unhandled instruction for Aarch64
(0x0EE0E020, 0x1AC15800, 0x4E284801, 0x5E040023, 0x5E056060)
367995 Integration of memcheck with custom memory allocator
368120 x86_linux asm _start functions do not keep 16-byte aligned stack pointer
368412 False positive result for altivec capability check
368416 Add tc06_two_races_xml.exp output for ppc64
368419 Perf Events ioctls not implemented
368461 mmapunmap test fails on ppc64
368823 run_a_thread_NORETURN assembly code typo for VGP_arm64_linux target
369000 AMD64 fma4 instructions unsupported.
369169 ppc64 fails jm_int_isa_2_07 test
369175 jm_vec_isa_2_07 test crashes on ppc64
369209 valgrind loops and eats up all memory if cwd doesn't exist.
369356 pre_mem_read_sockaddr syscall wrapper can crash with bad sockaddr
369359 msghdr_foreachfield can crash when handling bad iovec
369360 Bad sigprocmask old or new sets can crash valgrind
369361 vmsplice syscall wrapper crashes on bad iovec
369362 Bad sigaction arguments crash valgrind
369383 x86 sys_modify_ldt wrapper crashes on bad ptr
369402 Bad set/get_thread_area pointer crashes valgrind
369441 bad lvec argument crashes process_vm_readv/writev syscall wrappers
369446 valgrind crashes on unknown fcntl command
369439 S390x: Unhandled insns RISBLG/RISBHG and LDE/LDER
369468 Remove quadratic metapool algorithm using VG_(HT_remove_at_Iter)
370265 ISA 3.0 HW cap stuff needs updating
371128 BCD add and subtract instructions on Power BE in 32-bit mode do not work
n-i-bz Fix incorrect (or infinite loop) unwind on RHEL7 x86 and amd64
n-i-bz massif --pages-as-heap=yes does not report peak caused by mmap+munmap
n-i-bz false positive leaks due to aspacemgr merging heap & non heap segments
n-i-bz Fix ppoll_alarm exclusion on OS X
n-i-bz Document brk segment limitation, reference manual in limit reached msg.
n-i-bz Fix clobber list in none/tests/amd64/xacq_xrel.c [valgrind r15737]
n-i-bz Bump allowed shift value for "add.w reg, sp, reg, lsl #N" [vex r3206]
n-i-bz amd64: memcheck false positive with shr %edx
n-i-bz arm3: Allow early writeback of SP base register in "strd rD, [sp, #-16]"
n-i-bz ppc: Fix two cases of PPCAvFpOp vs PPCFpOp enum confusion
n-i-bz arm: Fix incorrect register-number constraint check for LDAEX{,B,H,D}
n-i-bz DHAT: added collection of the metric "tot-blocks-allocd"
(3.12.0.RC1: 20 October 2016, vex r3282, valgrind r16094)
(3.12.0.RC2: 20 October 2016, vex r3282, valgrind r16096)
(3.12.0: 21 October 2016, vex r3282, valgrind r16098)
Bug: http://b/37470713
Bug: http://b/29251682
Test: ran runtests-arm(64)?.sh and the bug reporter's specific binary (32- and 64-bit)
Change-Id: I43ccbea946d89fc4ae9f355181ac5061d6ce4453
diff --git a/none/tests/Makefile.am b/none/tests/Makefile.am
index a4204d5..ffe55d4 100644
--- a/none/tests/Makefile.am
+++ b/none/tests/Makefile.am
@@ -140,14 +140,19 @@
mq.stderr.exp mq.vgtest \
munmap_exe.stderr.exp munmap_exe.vgtest \
nestedfns.stderr.exp nestedfns.stdout.exp nestedfns.vgtest \
+ nocwd.stdout.exp nocwd.stderr.exp nocwd.vgtest \
nodir.stderr.exp nodir.vgtest \
pending.stdout.exp pending.stderr.exp pending.vgtest \
+ ppoll_alarm.stdout.exp ppoll_alarm.stderr.exp ppoll_alarm.vgtest \
procfs-linux.stderr.exp-with-readlinkat \
procfs-linux.stderr.exp-without-readlinkat \
procfs-linux.vgtest \
procfs-non-linux.vgtest \
procfs-non-linux.stderr.exp-with-readlinkat \
procfs-non-linux.stderr.exp-without-readlinkat \
+ pselect_alarm.stdout.exp pselect_alarm.stderr.exp pselect_alarm.vgtest \
+ pselect_sigmask_null.vgtest \
+ pselect_sigmask_null.stdout.exp pselect_sigmask_null.stderr.exp \
pth_atfork1.stderr.exp pth_atfork1.stdout.exp pth_atfork1.vgtest \
pth_blockedsig.stderr.exp \
pth_blockedsig.stdout.exp pth_blockedsig.vgtest \
@@ -163,6 +168,7 @@
pth_rwlock.stderr.exp pth_rwlock.vgtest \
pth_stackalign.stderr.exp \
pth_stackalign.stdout.exp pth_stackalign.vgtest \
+ pth_term_signal.stderr.exp pth_term_signal.vgtest \
rcrl.stderr.exp rcrl.stdout.exp rcrl.vgtest \
readline1.stderr.exp readline1.stdout.exp \
readline1.vgtest \
@@ -214,11 +220,14 @@
manythreads \
mmap_fcntl_bug \
munmap_exe map_unaligned map_unmap mq \
+ nocwd \
pending \
procfs-cmdline-exe \
+ pselect_alarm \
+ pselect_sigmask_null \
pth_atfork1 pth_blockedsig pth_cancel1 pth_cancel2 pth_cvsimple \
pth_empty pth_exit pth_exit2 pth_mutexspeed pth_once pth_rwlock \
- pth_stackalign \
+ pth_stackalign pth_term_signal\
rcrl readline1 \
require-text-symbol \
res_search resolv \
@@ -247,7 +256,8 @@
# This doesn't appear to be compilable on Darwin.
if ! VGCONF_OS_IS_DARWIN
- check_PROGRAMS += rlimit64_nofile
+ check_PROGRAMS += rlimit64_nofile \
+ ppoll_alarm
endif
# clang does not know -ansi
@@ -267,7 +277,7 @@
execve_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
if VGCONF_OS_IS_SOLARIS
fcntl_setown_LDADD = -lsocket -lnsl
-fdleak_cmsg_CFLAGS = $(AM_CFLAGS) -D_XOPEN_SOURCE=500
+fdleak_cmsg_CFLAGS = $(AM_CFLAGS) -std=c99 -D_XOPEN_SOURCE=600
fdleak_cmsg_LDADD = -lsocket -lnsl
fdleak_ipv4_LDADD = -lsocket -lnsl
fdleak_creat_LDADD = -lsocket -lnsl
@@ -289,6 +299,8 @@
../../VEX/libvexmultiarch-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
../../VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a @LIB_UBSAN@
libvexmultiarch_test_SOURCES = libvex_test.c
+ppoll_alarm_LDADD = -lpthread
+pselect_alarm_LDADD = -lpthread
pth_atfork1_LDADD = -lpthread
pth_blockedsig_LDADD = -lpthread
pth_cancel1_CFLAGS = $(AM_CFLAGS) -Wno-shadow
@@ -306,6 +318,7 @@
pth_rwlock_CFLAGS += --std=c99
endif
pth_stackalign_LDADD = -lpthread
+pth_term_signal_LDADD = -lpthread
res_search_LDADD = -lresolv -lpthread
resolv_CFLAGS = $(AM_CFLAGS)
resolv_LDADD = -lresolv -lpthread
diff --git a/none/tests/Makefile.in b/none/tests/Makefile.in
new file mode 100644
index 0000000..d9ffe8d
--- /dev/null
+++ b/none/tests/Makefile.in
@@ -0,0 +1,2287 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+VPATH = @srcdir@
+am__is_gnu_make = { \
+ if test -z '$(MAKELEVEL)'; then \
+ false; \
+ elif test -n '$(MAKE_HOST)'; then \
+ true; \
+ elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
+ true; \
+ else \
+ false; \
+ fi; \
+}
+am__make_running_with_option = \
+ case $${target_option-} in \
+ ?) ;; \
+ *) echo "am__make_running_with_option: internal error: invalid" \
+ "target option '$${target_option-}' specified" >&2; \
+ exit 1;; \
+ esac; \
+ has_opt=no; \
+ sane_makeflags=$$MAKEFLAGS; \
+ if $(am__is_gnu_make); then \
+ sane_makeflags=$$MFLAGS; \
+ else \
+ case $$MAKEFLAGS in \
+ *\\[\ \ ]*) \
+ bs=\\; \
+ sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
+ | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \
+ esac; \
+ fi; \
+ skip_next=no; \
+ strip_trailopt () \
+ { \
+ flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
+ }; \
+ for flg in $$sane_makeflags; do \
+ test $$skip_next = yes && { skip_next=no; continue; }; \
+ case $$flg in \
+ *=*|--*) continue;; \
+ -*I) strip_trailopt 'I'; skip_next=yes;; \
+ -*I?*) strip_trailopt 'I';; \
+ -*O) strip_trailopt 'O'; skip_next=yes;; \
+ -*O?*) strip_trailopt 'O';; \
+ -*l) strip_trailopt 'l'; skip_next=yes;; \
+ -*l?*) strip_trailopt 'l';; \
+ -[dEDm]) skip_next=yes;; \
+ -[JT]) skip_next=yes;; \
+ esac; \
+ case $$flg in \
+ *$$target_option*) has_opt=yes; break;; \
+ esac; \
+ done; \
+ test $$has_opt = yes
+am__make_dryrun = (target_option=n; $(am__make_running_with_option))
+am__make_keepgoing = (target_option=k; $(am__make_running_with_option))
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+@COMPILER_IS_CLANG_TRUE@am__append_1 = -Wno-cast-align -Wno-self-assign \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-compare
+
+@SOLARIS_XPG_SYMBOLS_PRESENT_TRUE@am__append_2 = -Wl,-M,$(top_srcdir)/solaris/vgpreload-solaris.mapfile
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_3 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+
+# Make sure that all test programs have threaded errno.
+# Disable largefile support as there are test cases explictly enabling it.
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
+@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
+@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-constant-out-of-range-compare \
+@COMPILER_IS_CLANG_TRUE@ -Wno-self-assign -Wno-string-plus-int \
+@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
+@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
+@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
+
+# Arch-specific tests.
+@VGCONF_ARCHS_INCLUDE_X86_TRUE@am__append_8 = x86
+@VGCONF_ARCHS_INCLUDE_AMD64_TRUE@am__append_9 = amd64
+@VGCONF_ARCHS_INCLUDE_PPC32_TRUE@am__append_10 = ppc32
+@VGCONF_ARCHS_INCLUDE_PPC64_TRUE@am__append_11 = ppc64
+@VGCONF_ARCHS_INCLUDE_ARM_TRUE@am__append_12 = arm
+@VGCONF_ARCHS_INCLUDE_ARM64_TRUE@am__append_13 = arm64
+@VGCONF_ARCHS_INCLUDE_S390X_TRUE@am__append_14 = s390x
+@VGCONF_ARCHS_INCLUDE_MIPS32_TRUE@am__append_15 = mips32
+@VGCONF_ARCHS_INCLUDE_MIPS64_TRUE@am__append_16 = mips64
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@am__append_17 = tilegx
+
+# OS-specific tests
+@VGCONF_OS_IS_LINUX_TRUE@am__append_18 = linux
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_19 = darwin
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_20 = solaris
+
+# Platform-specific tests
+@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_21 = amd64-linux
+@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_22 = x86-linux
+@VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_TRUE@am__append_23 = amd64-darwin
+@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE@am__append_24 = x86-darwin
+@VGCONF_PLATFORMS_INCLUDE_AMD64_SOLARIS_TRUE@am__append_25 = amd64-solaris
+@VGCONF_PLATFORMS_INCLUDE_X86_SOLARIS_TRUE@am__append_26 = x86-solaris
+check_PROGRAMS = args$(EXEEXT) async-sigs$(EXEEXT) bitfield1$(EXEEXT) \
+ bug129866$(EXEEXT) bug234814$(EXEEXT) closeall$(EXEEXT) \
+ coolo_strlen$(EXEEXT) discard$(EXEEXT) exec-sigmask$(EXEEXT) \
+ execve$(EXEEXT) faultstatus$(EXEEXT) fcntl_setown$(EXEEXT) \
+ fdleak_cmsg$(EXEEXT) fdleak_creat$(EXEEXT) fdleak_dup$(EXEEXT) \
+ fdleak_dup2$(EXEEXT) fdleak_fcntl$(EXEEXT) \
+ fdleak_ipv4$(EXEEXT) fdleak_open$(EXEEXT) fdleak_pipe$(EXEEXT) \
+ fdleak_socketpair$(EXEEXT) floored$(EXEEXT) fork$(EXEEXT) \
+ fucomip$(EXEEXT) ioctl_moans$(EXEEXT) libvex_test$(EXEEXT) \
+ libvexmultiarch_test$(EXEEXT) manythreads$(EXEEXT) \
+ mmap_fcntl_bug$(EXEEXT) munmap_exe$(EXEEXT) \
+ map_unaligned$(EXEEXT) map_unmap$(EXEEXT) mq$(EXEEXT) \
+ nocwd$(EXEEXT) pending$(EXEEXT) procfs-cmdline-exe$(EXEEXT) \
+ pselect_alarm$(EXEEXT) pselect_sigmask_null$(EXEEXT) \
+ pth_atfork1$(EXEEXT) pth_blockedsig$(EXEEXT) \
+ pth_cancel1$(EXEEXT) pth_cancel2$(EXEEXT) \
+ pth_cvsimple$(EXEEXT) pth_empty$(EXEEXT) pth_exit$(EXEEXT) \
+ pth_exit2$(EXEEXT) pth_mutexspeed$(EXEEXT) pth_once$(EXEEXT) \
+ pth_rwlock$(EXEEXT) pth_stackalign$(EXEEXT) \
+ pth_term_signal$(EXEEXT) rcrl$(EXEEXT) readline1$(EXEEXT) \
+ require-text-symbol$(EXEEXT) res_search$(EXEEXT) \
+ resolv$(EXEEXT) rlimit_nofile$(EXEEXT) selfrun$(EXEEXT) \
+ sem$(EXEEXT) semlimit$(EXEEXT) sha1_test$(EXEEXT) \
+ shortpush$(EXEEXT) shorts$(EXEEXT) stackgrowth$(EXEEXT) \
+ sigstackgrowth$(EXEEXT) syscall-restart1$(EXEEXT) \
+ syscall-restart2$(EXEEXT) syslog$(EXEEXT) system$(EXEEXT) \
+ thread-exits$(EXEEXT) threaded-fork$(EXEEXT) \
+ threadederrno$(EXEEXT) timestamp$(EXEEXT) tls$(EXEEXT) \
+ tls.so$(EXEEXT) tls2.so$(EXEEXT) unit_debuglog$(EXEEXT) \
+ valgrind_cpp_test$(EXEEXT) vgprintf$(EXEEXT) \
+ coolo_sigaction$(EXEEXT) gxx304$(EXEEXT) \
+ process_vm_readv_writev$(EXEEXT) $(am__EXEEXT_1) \
+ $(am__EXEEXT_2) $(am__EXEEXT_3) $(am__EXEEXT_4)
+@HAVE_NESTED_FUNCTIONS_TRUE@am__append_27 = nestedfns
+
+# This doesn't appear to be compilable on Darwin.
+@VGCONF_OS_IS_DARWIN_FALSE@am__append_28 = rlimit64_nofile \
+@VGCONF_OS_IS_DARWIN_FALSE@ ppoll_alarm
+
+
+# clang does not know -ansi
+@COMPILER_IS_CLANG_FALSE@am__append_29 = ansi
+@BUILD_IFUNC_TESTS_TRUE@am__append_30 = ifunc
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_31 = --std=c99
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_32 = -U_REENTRANT
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_33 = -Du_int32_t=uint32_t
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_34 = --std=c99
+subdir = none/tests
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.ac
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+DIST_COMMON = $(srcdir)/Makefile.am $(dist_noinst_SCRIPTS) \
+ $(noinst_HEADERS) $(am__DIST_COMMON)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+@HAVE_NESTED_FUNCTIONS_TRUE@am__EXEEXT_1 = nestedfns$(EXEEXT)
+@VGCONF_OS_IS_DARWIN_FALSE@am__EXEEXT_2 = rlimit64_nofile$(EXEEXT) \
+@VGCONF_OS_IS_DARWIN_FALSE@ ppoll_alarm$(EXEEXT)
+@COMPILER_IS_CLANG_FALSE@am__EXEEXT_3 = ansi$(EXEEXT)
+@BUILD_IFUNC_TESTS_TRUE@am__EXEEXT_4 = ifunc$(EXEEXT)
+ansi_SOURCES = ansi.c
+ansi_OBJECTS = ansi-ansi.$(OBJEXT)
+ansi_LDADD = $(LDADD)
+ansi_LINK = $(CCLD) $(ansi_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) \
+ -o $@
+args_SOURCES = args.c
+args_OBJECTS = args.$(OBJEXT)
+args_LDADD = $(LDADD)
+async_sigs_SOURCES = async-sigs.c
+async_sigs_OBJECTS = async-sigs.$(OBJEXT)
+async_sigs_LDADD = $(LDADD)
+bitfield1_SOURCES = bitfield1.c
+bitfield1_OBJECTS = bitfield1.$(OBJEXT)
+bitfield1_LDADD = $(LDADD)
+bug129866_SOURCES = bug129866.c
+bug129866_OBJECTS = bug129866.$(OBJEXT)
+bug129866_LDADD = $(LDADD)
+bug234814_SOURCES = bug234814.c
+bug234814_OBJECTS = bug234814.$(OBJEXT)
+bug234814_LDADD = $(LDADD)
+closeall_SOURCES = closeall.c
+closeall_OBJECTS = closeall.$(OBJEXT)
+closeall_LDADD = $(LDADD)
+am_coolo_sigaction_OBJECTS = coolo_sigaction.$(OBJEXT)
+coolo_sigaction_OBJECTS = $(am_coolo_sigaction_OBJECTS)
+coolo_sigaction_LDADD = $(LDADD)
+coolo_strlen_SOURCES = coolo_strlen.c
+coolo_strlen_OBJECTS = coolo_strlen.$(OBJEXT)
+coolo_strlen_LDADD = $(LDADD)
+discard_SOURCES = discard.c
+discard_OBJECTS = discard.$(OBJEXT)
+discard_LDADD = $(LDADD)
+exec_sigmask_SOURCES = exec-sigmask.c
+exec_sigmask_OBJECTS = exec-sigmask.$(OBJEXT)
+exec_sigmask_LDADD = $(LDADD)
+execve_SOURCES = execve.c
+execve_OBJECTS = execve-execve.$(OBJEXT)
+execve_LDADD = $(LDADD)
+execve_LINK = $(CCLD) $(execve_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+faultstatus_SOURCES = faultstatus.c
+faultstatus_OBJECTS = faultstatus.$(OBJEXT)
+faultstatus_LDADD = $(LDADD)
+fcntl_setown_SOURCES = fcntl_setown.c
+fcntl_setown_OBJECTS = fcntl_setown.$(OBJEXT)
+fcntl_setown_DEPENDENCIES =
+fdleak_cmsg_SOURCES = fdleak_cmsg.c
+fdleak_cmsg_OBJECTS = fdleak_cmsg-fdleak_cmsg.$(OBJEXT)
+fdleak_cmsg_DEPENDENCIES =
+fdleak_cmsg_LINK = $(CCLD) $(fdleak_cmsg_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+fdleak_creat_SOURCES = fdleak_creat.c
+fdleak_creat_OBJECTS = fdleak_creat.$(OBJEXT)
+fdleak_creat_DEPENDENCIES =
+fdleak_dup_SOURCES = fdleak_dup.c
+fdleak_dup_OBJECTS = fdleak_dup.$(OBJEXT)
+fdleak_dup_LDADD = $(LDADD)
+fdleak_dup2_SOURCES = fdleak_dup2.c
+fdleak_dup2_OBJECTS = fdleak_dup2.$(OBJEXT)
+fdleak_dup2_LDADD = $(LDADD)
+fdleak_fcntl_SOURCES = fdleak_fcntl.c
+fdleak_fcntl_OBJECTS = fdleak_fcntl.$(OBJEXT)
+fdleak_fcntl_LDADD = $(LDADD)
+fdleak_ipv4_SOURCES = fdleak_ipv4.c
+fdleak_ipv4_OBJECTS = fdleak_ipv4.$(OBJEXT)
+fdleak_ipv4_DEPENDENCIES =
+fdleak_open_SOURCES = fdleak_open.c
+fdleak_open_OBJECTS = fdleak_open.$(OBJEXT)
+fdleak_open_LDADD = $(LDADD)
+fdleak_pipe_SOURCES = fdleak_pipe.c
+fdleak_pipe_OBJECTS = fdleak_pipe.$(OBJEXT)
+fdleak_pipe_LDADD = $(LDADD)
+fdleak_socketpair_SOURCES = fdleak_socketpair.c
+fdleak_socketpair_OBJECTS = fdleak_socketpair.$(OBJEXT)
+fdleak_socketpair_DEPENDENCIES =
+floored_SOURCES = floored.c
+floored_OBJECTS = floored.$(OBJEXT)
+floored_DEPENDENCIES =
+fork_SOURCES = fork.c
+fork_OBJECTS = fork.$(OBJEXT)
+fork_LDADD = $(LDADD)
+fucomip_SOURCES = fucomip.c
+fucomip_OBJECTS = fucomip.$(OBJEXT)
+fucomip_LDADD = $(LDADD)
+am_gxx304_OBJECTS = gxx304.$(OBJEXT)
+gxx304_OBJECTS = $(am_gxx304_OBJECTS)
+gxx304_LDADD = $(LDADD)
+ifunc_SOURCES = ifunc.c
+ifunc_OBJECTS = ifunc.$(OBJEXT)
+ifunc_LDADD = $(LDADD)
+ioctl_moans_SOURCES = ioctl_moans.c
+ioctl_moans_OBJECTS = ioctl_moans.$(OBJEXT)
+ioctl_moans_LDADD = $(LDADD)
+libvex_test_SOURCES = libvex_test.c
+libvex_test_OBJECTS = libvex_test-libvex_test.$(OBJEXT)
+libvex_test_DEPENDENCIES = \
+ ../../VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+libvex_test_LINK = $(CCLD) $(libvex_test_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+am_libvexmultiarch_test_OBJECTS = \
+ libvexmultiarch_test-libvex_test.$(OBJEXT)
+libvexmultiarch_test_OBJECTS = $(am_libvexmultiarch_test_OBJECTS)
+libvexmultiarch_test_DEPENDENCIES = \
+ ../../VEX/libvexmultiarch-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
+ ../../VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
+libvexmultiarch_test_LINK = $(CCLD) $(libvexmultiarch_test_CFLAGS) \
+ $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+manythreads_SOURCES = manythreads.c
+manythreads_OBJECTS = manythreads.$(OBJEXT)
+manythreads_DEPENDENCIES =
+map_unaligned_SOURCES = map_unaligned.c
+map_unaligned_OBJECTS = map_unaligned.$(OBJEXT)
+map_unaligned_LDADD = $(LDADD)
+map_unmap_SOURCES = map_unmap.c
+map_unmap_OBJECTS = map_unmap.$(OBJEXT)
+map_unmap_LDADD = $(LDADD)
+mmap_fcntl_bug_SOURCES = mmap_fcntl_bug.c
+mmap_fcntl_bug_OBJECTS = mmap_fcntl_bug.$(OBJEXT)
+mmap_fcntl_bug_LDADD = $(LDADD)
+mq_SOURCES = mq.c
+mq_OBJECTS = mq.$(OBJEXT)
+mq_DEPENDENCIES =
+munmap_exe_SOURCES = munmap_exe.c
+munmap_exe_OBJECTS = munmap_exe.$(OBJEXT)
+munmap_exe_LDADD = $(LDADD)
+nestedfns_SOURCES = nestedfns.c
+nestedfns_OBJECTS = nestedfns-nestedfns.$(OBJEXT)
+nestedfns_LDADD = $(LDADD)
+nestedfns_LINK = $(CCLD) $(nestedfns_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+nocwd_SOURCES = nocwd.c
+nocwd_OBJECTS = nocwd.$(OBJEXT)
+nocwd_LDADD = $(LDADD)
+pending_SOURCES = pending.c
+pending_OBJECTS = pending.$(OBJEXT)
+pending_LDADD = $(LDADD)
+ppoll_alarm_SOURCES = ppoll_alarm.c
+ppoll_alarm_OBJECTS = ppoll_alarm.$(OBJEXT)
+ppoll_alarm_DEPENDENCIES =
+process_vm_readv_writev_SOURCES = process_vm_readv_writev.c
+process_vm_readv_writev_OBJECTS = process_vm_readv_writev.$(OBJEXT)
+process_vm_readv_writev_LDADD = $(LDADD)
+procfs_cmdline_exe_SOURCES = procfs-cmdline-exe.c
+procfs_cmdline_exe_OBJECTS = procfs-cmdline-exe.$(OBJEXT)
+procfs_cmdline_exe_LDADD = $(LDADD)
+pselect_alarm_SOURCES = pselect_alarm.c
+pselect_alarm_OBJECTS = pselect_alarm.$(OBJEXT)
+pselect_alarm_DEPENDENCIES =
+pselect_sigmask_null_SOURCES = pselect_sigmask_null.c
+pselect_sigmask_null_OBJECTS = pselect_sigmask_null.$(OBJEXT)
+pselect_sigmask_null_LDADD = $(LDADD)
+pth_atfork1_SOURCES = pth_atfork1.c
+pth_atfork1_OBJECTS = pth_atfork1.$(OBJEXT)
+pth_atfork1_DEPENDENCIES =
+pth_blockedsig_SOURCES = pth_blockedsig.c
+pth_blockedsig_OBJECTS = pth_blockedsig.$(OBJEXT)
+pth_blockedsig_DEPENDENCIES =
+pth_cancel1_SOURCES = pth_cancel1.c
+pth_cancel1_OBJECTS = pth_cancel1-pth_cancel1.$(OBJEXT)
+pth_cancel1_DEPENDENCIES =
+pth_cancel1_LINK = $(CCLD) $(pth_cancel1_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+pth_cancel2_SOURCES = pth_cancel2.c
+pth_cancel2_OBJECTS = pth_cancel2.$(OBJEXT)
+pth_cancel2_DEPENDENCIES =
+pth_cvsimple_SOURCES = pth_cvsimple.c
+pth_cvsimple_OBJECTS = pth_cvsimple.$(OBJEXT)
+pth_cvsimple_DEPENDENCIES =
+pth_empty_SOURCES = pth_empty.c
+pth_empty_OBJECTS = pth_empty.$(OBJEXT)
+pth_empty_DEPENDENCIES =
+pth_exit_SOURCES = pth_exit.c
+pth_exit_OBJECTS = pth_exit.$(OBJEXT)
+pth_exit_DEPENDENCIES =
+pth_exit2_SOURCES = pth_exit2.c
+pth_exit2_OBJECTS = pth_exit2.$(OBJEXT)
+pth_exit2_DEPENDENCIES =
+pth_mutexspeed_SOURCES = pth_mutexspeed.c
+pth_mutexspeed_OBJECTS = pth_mutexspeed.$(OBJEXT)
+pth_mutexspeed_DEPENDENCIES =
+pth_once_SOURCES = pth_once.c
+pth_once_OBJECTS = pth_once.$(OBJEXT)
+pth_once_DEPENDENCIES =
+pth_rwlock_SOURCES = pth_rwlock.c
+pth_rwlock_OBJECTS = pth_rwlock-pth_rwlock.$(OBJEXT)
+pth_rwlock_DEPENDENCIES =
+pth_rwlock_LINK = $(CCLD) $(pth_rwlock_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+pth_stackalign_SOURCES = pth_stackalign.c
+pth_stackalign_OBJECTS = pth_stackalign.$(OBJEXT)
+pth_stackalign_DEPENDENCIES =
+pth_term_signal_SOURCES = pth_term_signal.c
+pth_term_signal_OBJECTS = pth_term_signal.$(OBJEXT)
+pth_term_signal_DEPENDENCIES =
+rcrl_SOURCES = rcrl.c
+rcrl_OBJECTS = rcrl.$(OBJEXT)
+rcrl_LDADD = $(LDADD)
+readline1_SOURCES = readline1.c
+readline1_OBJECTS = readline1.$(OBJEXT)
+readline1_LDADD = $(LDADD)
+require_text_symbol_SOURCES = require-text-symbol.c
+require_text_symbol_OBJECTS = require-text-symbol.$(OBJEXT)
+require_text_symbol_LDADD = $(LDADD)
+res_search_SOURCES = res_search.c
+res_search_OBJECTS = res_search.$(OBJEXT)
+res_search_DEPENDENCIES =
+resolv_SOURCES = resolv.c
+resolv_OBJECTS = resolv-resolv.$(OBJEXT)
+resolv_DEPENDENCIES =
+resolv_LINK = $(CCLD) $(resolv_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+rlimit64_nofile_SOURCES = rlimit64_nofile.c
+rlimit64_nofile_OBJECTS = rlimit64_nofile.$(OBJEXT)
+rlimit64_nofile_LDADD = $(LDADD)
+rlimit_nofile_SOURCES = rlimit_nofile.c
+rlimit_nofile_OBJECTS = rlimit_nofile.$(OBJEXT)
+rlimit_nofile_LDADD = $(LDADD)
+selfrun_SOURCES = selfrun.c
+selfrun_OBJECTS = selfrun.$(OBJEXT)
+selfrun_LDADD = $(LDADD)
+sem_SOURCES = sem.c
+sem_OBJECTS = sem.$(OBJEXT)
+sem_LDADD = $(LDADD)
+semlimit_SOURCES = semlimit.c
+semlimit_OBJECTS = semlimit.$(OBJEXT)
+semlimit_DEPENDENCIES =
+sha1_test_SOURCES = sha1_test.c
+sha1_test_OBJECTS = sha1_test-sha1_test.$(OBJEXT)
+sha1_test_LDADD = $(LDADD)
+sha1_test_LINK = $(CCLD) $(sha1_test_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+shortpush_SOURCES = shortpush.c
+shortpush_OBJECTS = shortpush.$(OBJEXT)
+shortpush_LDADD = $(LDADD)
+shorts_SOURCES = shorts.c
+shorts_OBJECTS = shorts.$(OBJEXT)
+shorts_LDADD = $(LDADD)
+sigstackgrowth_SOURCES = sigstackgrowth.c
+sigstackgrowth_OBJECTS = sigstackgrowth.$(OBJEXT)
+sigstackgrowth_LDADD = $(LDADD)
+stackgrowth_SOURCES = stackgrowth.c
+stackgrowth_OBJECTS = stackgrowth.$(OBJEXT)
+stackgrowth_LDADD = $(LDADD)
+syscall_restart1_SOURCES = syscall-restart1.c
+syscall_restart1_OBJECTS = syscall-restart1.$(OBJEXT)
+syscall_restart1_LDADD = $(LDADD)
+syscall_restart2_SOURCES = syscall-restart2.c
+syscall_restart2_OBJECTS = syscall-restart2.$(OBJEXT)
+syscall_restart2_LDADD = $(LDADD)
+syslog_SOURCES = syslog.c
+syslog_OBJECTS = syslog.$(OBJEXT)
+syslog_LDADD = $(LDADD)
+system_SOURCES = system.c
+system_OBJECTS = system.$(OBJEXT)
+system_LDADD = $(LDADD)
+thread_exits_SOURCES = thread-exits.c
+thread_exits_OBJECTS = thread-exits.$(OBJEXT)
+thread_exits_DEPENDENCIES =
+threaded_fork_SOURCES = threaded-fork.c
+threaded_fork_OBJECTS = threaded-fork.$(OBJEXT)
+threaded_fork_DEPENDENCIES =
+threadederrno_SOURCES = threadederrno.c
+threadederrno_OBJECTS = threadederrno-threadederrno.$(OBJEXT)
+threadederrno_DEPENDENCIES =
+threadederrno_LINK = $(CCLD) $(threadederrno_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+timestamp_SOURCES = timestamp.c
+timestamp_OBJECTS = timestamp.$(OBJEXT)
+timestamp_LDADD = $(LDADD)
+am_tls_OBJECTS = tls.$(OBJEXT) tls2.$(OBJEXT)
+tls_OBJECTS = $(am_tls_OBJECTS)
+tls_LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(tls_LDFLAGS) $(LDFLAGS) -o \
+ $@
+am_tls_so_OBJECTS = tls_so-tls_so.$(OBJEXT)
+tls_so_OBJECTS = $(am_tls_so_OBJECTS)
+tls_so_LINK = $(CCLD) $(tls_so_CFLAGS) $(CFLAGS) $(tls_so_LDFLAGS) \
+ $(LDFLAGS) -o $@
+am_tls2_so_OBJECTS = tls2_so.$(OBJEXT)
+tls2_so_OBJECTS = $(am_tls2_so_OBJECTS)
+tls2_so_LDADD = $(LDADD)
+tls2_so_LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(tls2_so_LDFLAGS) \
+ $(LDFLAGS) -o $@
+unit_debuglog_SOURCES = unit_debuglog.c
+unit_debuglog_OBJECTS = unit_debuglog.$(OBJEXT)
+unit_debuglog_LDADD = $(LDADD)
+am_valgrind_cpp_test_OBJECTS = valgrind_cpp_test.$(OBJEXT)
+valgrind_cpp_test_OBJECTS = $(am_valgrind_cpp_test_OBJECTS)
+valgrind_cpp_test_DEPENDENCIES =
+vgprintf_SOURCES = vgprintf.c
+vgprintf_OBJECTS = vgprintf.$(OBJEXT)
+vgprintf_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+AM_V_P = $(am__v_P_@AM_V@)
+am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
+am__v_P_0 = false
+am__v_P_1 = :
+AM_V_GEN = $(am__v_GEN_@AM_V@)
+am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@)
+am__v_GEN_0 = @echo " GEN " $@;
+am__v_GEN_1 =
+AM_V_at = $(am__v_at_@AM_V@)
+am__v_at_ = $(am__v_at_@AM_DEFAULT_V@)
+am__v_at_0 = @
+am__v_at_1 =
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+AM_V_lt = $(am__v_lt_@AM_V@)
+am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)
+am__v_lt_0 = --silent
+am__v_lt_1 =
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+AM_V_CC = $(am__v_CC_@AM_V@)
+am__v_CC_ = $(am__v_CC_@AM_DEFAULT_V@)
+am__v_CC_0 = @echo " CC " $@;
+am__v_CC_1 =
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+AM_V_CCLD = $(am__v_CCLD_@AM_V@)
+am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
+am__v_CCLD_0 = @echo " CCLD " $@;
+am__v_CCLD_1 =
+CXXCOMPILE = $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
+ $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS)
+AM_V_CXX = $(am__v_CXX_@AM_V@)
+am__v_CXX_ = $(am__v_CXX_@AM_DEFAULT_V@)
+am__v_CXX_0 = @echo " CXX " $@;
+am__v_CXX_1 =
+CXXLD = $(CXX)
+CXXLINK = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) $(AM_LDFLAGS) $(LDFLAGS) \
+ -o $@
+AM_V_CXXLD = $(am__v_CXXLD_@AM_V@)
+am__v_CXXLD_ = $(am__v_CXXLD_@AM_DEFAULT_V@)
+am__v_CXXLD_0 = @echo " CXXLD " $@;
+am__v_CXXLD_1 =
+SOURCES = ansi.c args.c async-sigs.c bitfield1.c bug129866.c \
+ bug234814.c closeall.c $(coolo_sigaction_SOURCES) \
+ coolo_strlen.c discard.c exec-sigmask.c execve.c faultstatus.c \
+ fcntl_setown.c fdleak_cmsg.c fdleak_creat.c fdleak_dup.c \
+ fdleak_dup2.c fdleak_fcntl.c fdleak_ipv4.c fdleak_open.c \
+ fdleak_pipe.c fdleak_socketpair.c floored.c fork.c fucomip.c \
+ $(gxx304_SOURCES) ifunc.c ioctl_moans.c libvex_test.c \
+ $(libvexmultiarch_test_SOURCES) manythreads.c map_unaligned.c \
+ map_unmap.c mmap_fcntl_bug.c mq.c munmap_exe.c nestedfns.c \
+ nocwd.c pending.c ppoll_alarm.c process_vm_readv_writev.c \
+ procfs-cmdline-exe.c pselect_alarm.c pselect_sigmask_null.c \
+ pth_atfork1.c pth_blockedsig.c pth_cancel1.c pth_cancel2.c \
+ pth_cvsimple.c pth_empty.c pth_exit.c pth_exit2.c \
+ pth_mutexspeed.c pth_once.c pth_rwlock.c pth_stackalign.c \
+ pth_term_signal.c rcrl.c readline1.c require-text-symbol.c \
+ res_search.c resolv.c rlimit64_nofile.c rlimit_nofile.c \
+ selfrun.c sem.c semlimit.c sha1_test.c shortpush.c shorts.c \
+ sigstackgrowth.c stackgrowth.c syscall-restart1.c \
+ syscall-restart2.c syslog.c system.c thread-exits.c \
+ threaded-fork.c threadederrno.c timestamp.c $(tls_SOURCES) \
+ $(tls_so_SOURCES) $(tls2_so_SOURCES) unit_debuglog.c \
+ $(valgrind_cpp_test_SOURCES) vgprintf.c
+DIST_SOURCES = ansi.c args.c async-sigs.c bitfield1.c bug129866.c \
+ bug234814.c closeall.c $(coolo_sigaction_SOURCES) \
+ coolo_strlen.c discard.c exec-sigmask.c execve.c faultstatus.c \
+ fcntl_setown.c fdleak_cmsg.c fdleak_creat.c fdleak_dup.c \
+ fdleak_dup2.c fdleak_fcntl.c fdleak_ipv4.c fdleak_open.c \
+ fdleak_pipe.c fdleak_socketpair.c floored.c fork.c fucomip.c \
+ $(gxx304_SOURCES) ifunc.c ioctl_moans.c libvex_test.c \
+ $(libvexmultiarch_test_SOURCES) manythreads.c map_unaligned.c \
+ map_unmap.c mmap_fcntl_bug.c mq.c munmap_exe.c nestedfns.c \
+ nocwd.c pending.c ppoll_alarm.c process_vm_readv_writev.c \
+ procfs-cmdline-exe.c pselect_alarm.c pselect_sigmask_null.c \
+ pth_atfork1.c pth_blockedsig.c pth_cancel1.c pth_cancel2.c \
+ pth_cvsimple.c pth_empty.c pth_exit.c pth_exit2.c \
+ pth_mutexspeed.c pth_once.c pth_rwlock.c pth_stackalign.c \
+ pth_term_signal.c rcrl.c readline1.c require-text-symbol.c \
+ res_search.c resolv.c rlimit64_nofile.c rlimit_nofile.c \
+ selfrun.c sem.c semlimit.c sha1_test.c shortpush.c shorts.c \
+ sigstackgrowth.c stackgrowth.c syscall-restart1.c \
+ syscall-restart2.c syslog.c system.c thread-exits.c \
+ threaded-fork.c threadederrno.c timestamp.c $(tls_SOURCES) \
+ $(tls_so_SOURCES) $(tls2_so_SOURCES) unit_debuglog.c \
+ $(valgrind_cpp_test_SOURCES) vgprintf.c
+RECURSIVE_TARGETS = all-recursive check-recursive cscopelist-recursive \
+ ctags-recursive dvi-recursive html-recursive info-recursive \
+ install-data-recursive install-dvi-recursive \
+ install-exec-recursive install-html-recursive \
+ install-info-recursive install-pdf-recursive \
+ install-ps-recursive install-recursive installcheck-recursive \
+ installdirs-recursive pdf-recursive ps-recursive \
+ tags-recursive uninstall-recursive
+am__can_run_installinfo = \
+ case $$AM_UPDATE_INFO_DIR in \
+ n|no|NO) false;; \
+ *) (install-info --version) >/dev/null 2>&1;; \
+ esac
+HEADERS = $(noinst_HEADERS)
+RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \
+ distclean-recursive maintainer-clean-recursive
+am__recursive_targets = \
+ $(RECURSIVE_TARGETS) \
+ $(RECURSIVE_CLEAN_TARGETS) \
+ $(am__extra_recursive_targets)
+AM_RECURSIVE_TARGETS = $(am__recursive_targets:-recursive=) TAGS CTAGS \
+ distdir
+am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) $(LISP)
+# Read a list of newline-separated strings from the standard input,
+# and print each of them once, without duplicates. Input order is
+# *not* preserved.
+am__uniquify_input = $(AWK) '\
+ BEGIN { nonempty = 0; } \
+ { items[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in items) print i; }; } \
+'
+# Make sure the list of sources is unique. This is necessary because,
+# e.g., the same source file might be shared among _SOURCES variables
+# for different programs/libraries.
+am__define_uniq_tagged_files = \
+ list='$(am__tagged_files)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | $(am__uniquify_input)`
+ETAGS = etags
+CTAGS = ctags
+am__DIST_COMMON = $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/depcomp
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+am__relativize = \
+ dir0=`pwd`; \
+ sed_first='s,^\([^/]*\)/.*$$,\1,'; \
+ sed_rest='s,^[^/]*/*,,'; \
+ sed_last='s,^.*/\([^/]*\)$$,\1,'; \
+ sed_butlast='s,/*[^/]*$$,,'; \
+ while test -n "$$dir1"; do \
+ first=`echo "$$dir1" | sed -e "$$sed_first"`; \
+ if test "$$first" != "."; then \
+ if test "$$first" = ".."; then \
+ dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \
+ dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \
+ else \
+ first2=`echo "$$dir2" | sed -e "$$sed_first"`; \
+ if test "$$first2" = "$$first"; then \
+ dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \
+ else \
+ dir2="../$$dir2"; \
+ fi; \
+ dir0="$$dir0"/"$$first"; \
+ fi; \
+ fi; \
+ dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \
+ done; \
+ reldir="$$dir2"
+ACLOCAL = @ACLOCAL@
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+AM_DEFAULT_VERBOSITY = @AM_DEFAULT_VERBOSITY@
+AR = @AR@
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+FLAG_OCTEON = @FLAG_OCTEON@
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+FLAG_T_TEXT = @FLAG_T_TEXT@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_CAST_ALIGN = @FLAG_W_CAST_ALIGN@
+FLAG_W_CAST_QUAL = @FLAG_W_CAST_QUAL@
+FLAG_W_EMPTY_BODY = @FLAG_W_EMPTY_BODY@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_FORMAT = @FLAG_W_FORMAT@
+FLAG_W_FORMAT_SECURITY = @FLAG_W_FORMAT_SECURITY@
+FLAG_W_FORMAT_SIGNEDNESS = @FLAG_W_FORMAT_SIGNEDNESS@
+FLAG_W_IGNORED_QUALIFIERS = @FLAG_W_IGNORED_QUALIFIERS@
+FLAG_W_MISSING_PARAMETER_TYPE = @FLAG_W_MISSING_PARAMETER_TYPE@
+FLAG_W_NO_INFINITE_RECURSION = @FLAG_W_NO_INFINITE_RECURSION@
+FLAG_W_NO_MEMSET_TRANSPOSED_ARGS = @FLAG_W_NO_MEMSET_TRANSPOSED_ARGS@
+FLAG_W_NO_MISMATCHED_NEW_DELETE = @FLAG_W_NO_MISMATCHED_NEW_DELETE@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_POINTER_SIGN = @FLAG_W_NO_POINTER_SIGN@
+FLAG_W_NO_STATIC_LOCAL_IN_INLINE = @FLAG_W_NO_STATIC_LOCAL_IN_INLINE@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+FLAG_W_NO_UNUSED_FUNCTION = @FLAG_W_NO_UNUSED_FUNCTION@
+FLAG_W_OLD_STYLE_DECLARATION = @FLAG_W_OLD_STYLE_DECLARATION@
+FLAG_W_WRITE_STRINGS = @FLAG_W_WRITE_STRINGS@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+HWCAP_HAS_ALTIVEC = @HWCAP_HAS_ALTIVEC@
+HWCAP_HAS_DFP = @HWCAP_HAS_DFP@
+HWCAP_HAS_HTM = @HWCAP_HAS_HTM@
+HWCAP_HAS_ISA_2_05 = @HWCAP_HAS_ISA_2_05@
+HWCAP_HAS_ISA_2_06 = @HWCAP_HAS_ISA_2_06@
+HWCAP_HAS_ISA_2_07 = @HWCAP_HAS_ISA_2_07@
+HWCAP_HAS_ISA_3_00 = @HWCAP_HAS_ISA_3_00@
+HWCAP_HAS_VSX = @HWCAP_HAS_VSX@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
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+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
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+LTLIBOBJS = @LTLIBOBJS@
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+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY_2 = @PREFERRED_STACK_BOUNDARY_2@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+SOLARIS_UNDEF_LARGESOURCE = @SOLARIS_UNDEF_LARGESOURCE@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+VG_TMPDIR = @VG_TMPDIR@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
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+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = -O2 -g -std=gnu99 -Wall -Wmissing-prototypes -Wshadow \
+ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \
+ @FLAG_W_CAST_ALIGN@ @FLAG_W_CAST_QUAL@ @FLAG_W_WRITE_STRINGS@ \
+ @FLAG_W_EMPTY_BODY@ @FLAG_W_FORMAT@ @FLAG_W_FORMAT_SIGNEDNESS@ \
+ @FLAG_W_FORMAT_SECURITY@ @FLAG_W_IGNORED_QUALIFIERS@ \
+ @FLAG_W_MISSING_PARAMETER_TYPE@ @FLAG_W_OLD_STYLE_DECLARATION@ \
+ @FLAG_FNO_STACK_PROTECTOR@ @FLAG_FSANITIZE@ \
+ -fno-strict-aliasing -fno-builtin $(am__append_1)
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fpic -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# These flags are used for building the preload shared objects (PSOs).
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads. Also, we must use any
+# -mpreferred-stack-boundary flag to build the preload shared
+# objects, since that risks misaligning the client's stack and
+# results in segfaults like (eg) #324050.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \
+@VGCONF_OS_IS_DARWIN_TRUE@ -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
+ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
+AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
+AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ $(AM_FLAG_M3264_PRI)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) \
+ $(AM_FLAG_M3264_PRI)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+SUBDIRS = . scripts $(am__append_8) $(am__append_9) $(am__append_10) \
+ $(am__append_11) $(am__append_12) $(am__append_13) \
+ $(am__append_14) $(am__append_15) $(am__append_16) \
+ $(am__append_17) $(am__append_18) $(am__append_19) \
+ $(am__append_20) $(am__append_21) $(am__append_22) \
+ $(am__append_23) $(am__append_24) $(am__append_25) \
+ $(am__append_26)
+DIST_SUBDIRS = x86 amd64 ppc32 ppc64 arm arm64 s390x mips32 mips64 tilegx \
+ linux darwin solaris amd64-linux x86-linux amd64-darwin \
+ x86-darwin amd64-solaris x86-solaris scripts .
+
+dist_noinst_SCRIPTS = \
+ filter_cmdline0 \
+ filter_cmdline1 \
+ filter_fdleak \
+ filter_ioctl_moans \
+ filter_none_discards \
+ filter_stderr \
+ filter_timestamp \
+ allexec_prepare_prereq
+
+noinst_HEADERS = fdleak.h
+EXTRA_DIST = \
+ allexec32.stdout.exp allexec32.stderr.exp allexec32.vgtest\
+ allexec64.stdout.exp allexec64.stderr.exp allexec64.vgtest\
+ ansi.stderr.exp ansi.vgtest \
+ args.stderr.exp args.stdout.exp args.vgtest \
+ async-sigs.stderr.exp async-sigs.stderr.exp-mips32 \
+ async-sigs.vgtest \
+ bigcode.vgtest bigcode.stderr.exp bigcode.stdout.exp \
+ bitfield1.stderr.exp bitfield1.vgtest \
+ bug129866.vgtest bug129866.stderr.exp bug129866.stdout.exp \
+ bug234814.vgtest bug234814.stderr.exp bug234814.stdout.exp \
+ closeall.stderr.exp closeall.vgtest \
+ cmdline0.stderr.exp cmdline0.stdout.exp cmdline0.vgtest \
+ cmdline1.stderr.exp cmdline1.stdout.exp cmdline1.vgtest \
+ cmdline2.stderr.exp cmdline2.stdout.exp cmdline2.vgtest \
+ cmdline3.stderr.exp cmdline3.vgtest \
+ cmdline4.stderr.exp cmdline4.vgtest \
+ cmdline5.stderr.exp cmdline5.vgtest \
+ cmdline6.stderr.exp cmdline6.vgtest \
+ cmd-with-special.stderr.exp cmd-with-special.vgtest \
+ coolo_sigaction.stderr.exp \
+ coolo_sigaction.stdout.exp coolo_sigaction.vgtest \
+ coolo_strlen.stderr.exp coolo_strlen.vgtest \
+ discard.stderr.exp discard.stdout.exp \
+ discard.vgtest \
+ empty-exe.vgtest empty-exe.stderr.exp \
+ exec-sigmask.vgtest exec-sigmask.stdout.exp \
+ exec-sigmask.stdout.exp2 exec-sigmask.stdout.exp3 \
+ exec-sigmask.stdout.exp-solaris exec-sigmask.stderr.exp \
+ execve.vgtest execve.stdout.exp execve.stderr.exp \
+ faultstatus.vgtest faultstatus.stderr.exp faultstatus.stderr.exp-s390x \
+ fcntl_setown.vgtest fcntl_setown.stdout.exp fcntl_setown.stderr.exp \
+ fdleak_cmsg.stderr.exp fdleak_cmsg.vgtest \
+ fdleak_creat.stderr.exp fdleak_creat.vgtest \
+ fdleak_dup.stderr.exp fdleak_dup.vgtest \
+ fdleak_dup2.stderr.exp fdleak_dup2.vgtest \
+ fdleak_fcntl.stderr.exp fdleak_fcntl.vgtest \
+ fdleak_ipv4.stderr.exp fdleak_ipv4.stdout.exp fdleak_ipv4.vgtest \
+ fdleak_open.stderr.exp fdleak_open.vgtest \
+ fdleak_pipe.stderr.exp fdleak_pipe.vgtest \
+ fdleak_socketpair.stderr.exp fdleak_socketpair.vgtest \
+ floored.stderr.exp floored.stdout.exp floored.vgtest \
+ fork.stderr.exp fork.stdout.exp fork.vgtest \
+ fucomip.stderr.exp fucomip.vgtest \
+ gxx304.stderr.exp gxx304.vgtest \
+ ifunc.stderr.exp ifunc.stdout.exp ifunc.vgtest \
+ ioctl_moans.stderr.exp ioctl_moans.vgtest \
+ libvex_test.stderr.exp libvex_test.vgtest \
+ libvexmultiarch_test.stderr.exp libvexmultiarch_test.vgtest \
+ manythreads.stdout.exp manythreads.stderr.exp manythreads.vgtest \
+ map_unaligned.stderr.exp map_unaligned.vgtest \
+ map_unmap.stderr.exp map_unmap.stdout.exp map_unmap.vgtest \
+ mmap_fcntl_bug.vgtest mmap_fcntl_bug.stdout.exp \
+ mmap_fcntl_bug.stderr.exp \
+ mq.stderr.exp mq.vgtest \
+ munmap_exe.stderr.exp munmap_exe.vgtest \
+ nestedfns.stderr.exp nestedfns.stdout.exp nestedfns.vgtest \
+ nocwd.stdout.exp nocwd.stderr.exp nocwd.vgtest \
+ nodir.stderr.exp nodir.vgtest \
+ pending.stdout.exp pending.stderr.exp pending.vgtest \
+ ppoll_alarm.stdout.exp ppoll_alarm.stderr.exp ppoll_alarm.vgtest \
+ procfs-linux.stderr.exp-with-readlinkat \
+ procfs-linux.stderr.exp-without-readlinkat \
+ procfs-linux.vgtest \
+ procfs-non-linux.vgtest \
+ procfs-non-linux.stderr.exp-with-readlinkat \
+ procfs-non-linux.stderr.exp-without-readlinkat \
+ pselect_alarm.stdout.exp pselect_alarm.stderr.exp pselect_alarm.vgtest \
+ pselect_sigmask_null.vgtest \
+ pselect_sigmask_null.stdout.exp pselect_sigmask_null.stderr.exp \
+ pth_atfork1.stderr.exp pth_atfork1.stdout.exp pth_atfork1.vgtest \
+ pth_blockedsig.stderr.exp \
+ pth_blockedsig.stdout.exp pth_blockedsig.vgtest \
+ pth_cancel1.stderr.exp pth_cancel1.stdout.exp pth_cancel1.vgtest \
+ pth_cancel2.stderr.exp pth_cancel2.vgtest \
+ pth_cvsimple.stderr.exp pth_cvsimple.stdout.exp pth_cvsimple.vgtest \
+ pth_empty.stderr.exp pth_empty.vgtest \
+ pth_exit.stderr.exp pth_exit.vgtest \
+ pth_exit2.stderr.exp pth_exit2.vgtest \
+ pth_mutexspeed.stderr.exp \
+ pth_mutexspeed.stdout.exp pth_mutexspeed.vgtest \
+ pth_once.stderr.exp pth_once.stdout.exp pth_once.vgtest \
+ pth_rwlock.stderr.exp pth_rwlock.vgtest \
+ pth_stackalign.stderr.exp \
+ pth_stackalign.stdout.exp pth_stackalign.vgtest \
+ pth_term_signal.stderr.exp pth_term_signal.vgtest \
+ rcrl.stderr.exp rcrl.stdout.exp rcrl.vgtest \
+ readline1.stderr.exp readline1.stdout.exp \
+ readline1.vgtest \
+ require-text-symbol-1.vgtest \
+ require-text-symbol-1.stderr.exp \
+ require-text-symbol-2.vgtest \
+ require-text-symbol-2.stderr.exp-libcso1 \
+ require-text-symbol-2.stderr.exp-libcso6 \
+ res_search.stderr.exp res_search.stdout.exp res_search.vgtest \
+ resolv.stderr.exp resolv.stdout.exp resolv.vgtest \
+ rlimit_nofile.stderr.exp rlimit_nofile.stdout.exp rlimit_nofile.vgtest \
+ rlimit64_nofile.stderr.exp rlimit64_nofile.stdout.exp rlimit64_nofile.vgtest \
+ selfrun.stderr.exp selfrun.stdout.exp selfrun.vgtest \
+ sem.stderr.exp sem.stdout.exp sem.vgtest \
+ semlimit.stderr.exp semlimit.stdout.exp semlimit.vgtest \
+ sha1_test.stderr.exp sha1_test.vgtest \
+ shortpush.stderr.exp shortpush.vgtest \
+ shorts.stderr.exp shorts.vgtest \
+ sigstackgrowth.stdout.exp sigstackgrowth.stderr.exp sigstackgrowth.vgtest \
+ stackgrowth.stdout.exp stackgrowth.stderr.exp stackgrowth.vgtest \
+ syscall-restart1.vgtest syscall-restart1.stdout.exp syscall-restart1.stderr.exp \
+ syscall-restart2.vgtest syscall-restart2.stdout.exp syscall-restart2.stderr.exp \
+ syslog.vgtest syslog.stderr.exp \
+ system.stderr.exp system.vgtest \
+ thread-exits.stderr.exp thread-exits.stdout.exp thread-exits.vgtest \
+ threaded-fork.stderr.exp threaded-fork.stdout.exp threaded-fork.vgtest \
+ threadederrno.stderr.exp threadederrno.stdout.exp \
+ threadederrno.vgtest \
+ timestamp.stderr.exp timestamp.vgtest \
+ tls.vgtest tls.stderr.exp tls.stdout.exp \
+ unit_debuglog.stderr.exp unit_debuglog.vgtest \
+ vgprintf.stderr.exp vgprintf.vgtest \
+ process_vm_readv_writev.stderr.exp process_vm_readv_writev.vgtest
+
+
+# Extra stuff for C tests
+ansi_CFLAGS = $(AM_CFLAGS) -ansi
+execve_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+@VGCONF_OS_IS_SOLARIS_TRUE@fcntl_setown_LDADD = -lsocket -lnsl
+@VGCONF_OS_IS_SOLARIS_TRUE@fdleak_cmsg_CFLAGS = $(AM_CFLAGS) -std=c99 -D_XOPEN_SOURCE=600
+@VGCONF_OS_IS_SOLARIS_TRUE@fdleak_cmsg_LDADD = -lsocket -lnsl
+@VGCONF_OS_IS_SOLARIS_TRUE@fdleak_ipv4_LDADD = -lsocket -lnsl
+@VGCONF_OS_IS_SOLARIS_TRUE@fdleak_creat_LDADD = -lsocket -lnsl
+@VGCONF_OS_IS_SOLARIS_TRUE@fdleak_socketpair_LDADD = -lsocket -lnsl
+floored_LDADD = -lm
+manythreads_LDADD = -lpthread
+@VGCONF_OS_IS_DARWIN_FALSE@nestedfns_CFLAGS = $(AM_CFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@nestedfns_CFLAGS = $(AM_CFLAGS) -fnested-functions
+@VGCONF_OS_IS_DARWIN_FALSE@mq_LDADD = -lrt
+libvex_test_CFLAGS = $(AM_CFLAGS) @FLAG_FSANITIZE@
+libvex_test_LDADD = ../../VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
+ @LIB_UBSAN@
+
+libvexmultiarch_test_CFLAGS = $(AM_CFLAGS) @FLAG_FSANITIZE@
+libvexmultiarch_test_LDADD = \
+ ../../VEX/libvexmultiarch-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
+ ../../VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a @LIB_UBSAN@
+
+libvexmultiarch_test_SOURCES = libvex_test.c
+ppoll_alarm_LDADD = -lpthread
+pselect_alarm_LDADD = -lpthread
+pth_atfork1_LDADD = -lpthread
+pth_blockedsig_LDADD = -lpthread
+pth_cancel1_CFLAGS = $(AM_CFLAGS) -Wno-shadow
+pth_cancel1_LDADD = -lpthread
+pth_cancel2_LDADD = -lpthread
+pth_cvsimple_LDADD = -lpthread
+pth_empty_LDADD = -lpthread
+pth_exit_LDADD = -lpthread
+pth_exit2_LDADD = -lpthread
+pth_mutexspeed_LDADD = -lpthread
+pth_once_LDADD = -lpthread
+pth_rwlock_LDADD = -lpthread
+pth_rwlock_CFLAGS = $(AM_CFLAGS) $(am__append_31)
+pth_stackalign_LDADD = -lpthread
+pth_term_signal_LDADD = -lpthread
+res_search_LDADD = -lresolv -lpthread
+resolv_CFLAGS = $(AM_CFLAGS) $(am__append_32)
+resolv_LDADD = -lresolv -lpthread
+semlimit_LDADD = -lpthread
+sha1_test_CFLAGS = $(AM_CFLAGS) $(am__append_33)
+thread_exits_LDADD = -lpthread
+threaded_fork_LDADD = -lpthread
+threadederrno_CFLAGS = $(AM_CFLAGS) $(am__append_34)
+threadederrno_LDADD = -lpthread
+tls_SOURCES = tls.c tls2.c
+tls_DEPENDENCIES = tls.so tls2.so
+tls_LDFLAGS = -Wl,-rpath,$(abs_top_builddir)/none/tests
+tls_LDADD = tls.so tls2.so -lpthread
+tls_so_SOURCES = tls_so.c
+tls_so_DEPENDENCIES = tls2.so
+@VGCONF_OS_IS_DARWIN_FALSE@tls_so_LDFLAGS = -Wl,-rpath,$(abs_top_builddir)/none/tests -shared -fPIC
+@VGCONF_OS_IS_DARWIN_TRUE@tls_so_LDFLAGS = -dynamic -dynamiclib -all_load -fpic
+@VGCONF_OS_IS_DARWIN_FALSE@tls_so_LDADD = tls2.so
+@VGCONF_OS_IS_DARWIN_TRUE@tls_so_LDADD = `pwd`/tls2.so
+tls_so_CFLAGS = $(AM_CFLAGS) -fPIC
+tls2_so_SOURCES = tls2_so.c
+@VGCONF_OS_IS_DARWIN_FALSE@tls2_so_LDFLAGS = -shared
+@VGCONF_OS_IS_DARWIN_TRUE@tls2_so_LDFLAGS = -dynamic -dynamiclib -all_load
+valgrind_cpp_test_SOURCES = valgrind_cpp_test.cpp
+valgrind_cpp_test_LDADD = -lstdc++
+
+# C++ tests
+coolo_sigaction_SOURCES = coolo_sigaction.cpp
+gxx304_SOURCES = gxx304.cpp
+all: all-recursive
+
+.SUFFIXES:
+.SUFFIXES: .c .cpp .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+$(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__empty):
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+
+ansi$(EXEEXT): $(ansi_OBJECTS) $(ansi_DEPENDENCIES) $(EXTRA_ansi_DEPENDENCIES)
+ @rm -f ansi$(EXEEXT)
+ $(AM_V_CCLD)$(ansi_LINK) $(ansi_OBJECTS) $(ansi_LDADD) $(LIBS)
+
+args$(EXEEXT): $(args_OBJECTS) $(args_DEPENDENCIES) $(EXTRA_args_DEPENDENCIES)
+ @rm -f args$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(args_OBJECTS) $(args_LDADD) $(LIBS)
+
+async-sigs$(EXEEXT): $(async_sigs_OBJECTS) $(async_sigs_DEPENDENCIES) $(EXTRA_async_sigs_DEPENDENCIES)
+ @rm -f async-sigs$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(async_sigs_OBJECTS) $(async_sigs_LDADD) $(LIBS)
+
+bitfield1$(EXEEXT): $(bitfield1_OBJECTS) $(bitfield1_DEPENDENCIES) $(EXTRA_bitfield1_DEPENDENCIES)
+ @rm -f bitfield1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bitfield1_OBJECTS) $(bitfield1_LDADD) $(LIBS)
+
+bug129866$(EXEEXT): $(bug129866_OBJECTS) $(bug129866_DEPENDENCIES) $(EXTRA_bug129866_DEPENDENCIES)
+ @rm -f bug129866$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug129866_OBJECTS) $(bug129866_LDADD) $(LIBS)
+
+bug234814$(EXEEXT): $(bug234814_OBJECTS) $(bug234814_DEPENDENCIES) $(EXTRA_bug234814_DEPENDENCIES)
+ @rm -f bug234814$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug234814_OBJECTS) $(bug234814_LDADD) $(LIBS)
+
+closeall$(EXEEXT): $(closeall_OBJECTS) $(closeall_DEPENDENCIES) $(EXTRA_closeall_DEPENDENCIES)
+ @rm -f closeall$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(closeall_OBJECTS) $(closeall_LDADD) $(LIBS)
+
+coolo_sigaction$(EXEEXT): $(coolo_sigaction_OBJECTS) $(coolo_sigaction_DEPENDENCIES) $(EXTRA_coolo_sigaction_DEPENDENCIES)
+ @rm -f coolo_sigaction$(EXEEXT)
+ $(AM_V_CXXLD)$(CXXLINK) $(coolo_sigaction_OBJECTS) $(coolo_sigaction_LDADD) $(LIBS)
+
+coolo_strlen$(EXEEXT): $(coolo_strlen_OBJECTS) $(coolo_strlen_DEPENDENCIES) $(EXTRA_coolo_strlen_DEPENDENCIES)
+ @rm -f coolo_strlen$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(coolo_strlen_OBJECTS) $(coolo_strlen_LDADD) $(LIBS)
+
+discard$(EXEEXT): $(discard_OBJECTS) $(discard_DEPENDENCIES) $(EXTRA_discard_DEPENDENCIES)
+ @rm -f discard$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(discard_OBJECTS) $(discard_LDADD) $(LIBS)
+
+exec-sigmask$(EXEEXT): $(exec_sigmask_OBJECTS) $(exec_sigmask_DEPENDENCIES) $(EXTRA_exec_sigmask_DEPENDENCIES)
+ @rm -f exec-sigmask$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(exec_sigmask_OBJECTS) $(exec_sigmask_LDADD) $(LIBS)
+
+execve$(EXEEXT): $(execve_OBJECTS) $(execve_DEPENDENCIES) $(EXTRA_execve_DEPENDENCIES)
+ @rm -f execve$(EXEEXT)
+ $(AM_V_CCLD)$(execve_LINK) $(execve_OBJECTS) $(execve_LDADD) $(LIBS)
+
+faultstatus$(EXEEXT): $(faultstatus_OBJECTS) $(faultstatus_DEPENDENCIES) $(EXTRA_faultstatus_DEPENDENCIES)
+ @rm -f faultstatus$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(faultstatus_OBJECTS) $(faultstatus_LDADD) $(LIBS)
+
+fcntl_setown$(EXEEXT): $(fcntl_setown_OBJECTS) $(fcntl_setown_DEPENDENCIES) $(EXTRA_fcntl_setown_DEPENDENCIES)
+ @rm -f fcntl_setown$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(fcntl_setown_OBJECTS) $(fcntl_setown_LDADD) $(LIBS)
+
+fdleak_cmsg$(EXEEXT): $(fdleak_cmsg_OBJECTS) $(fdleak_cmsg_DEPENDENCIES) $(EXTRA_fdleak_cmsg_DEPENDENCIES)
+ @rm -f fdleak_cmsg$(EXEEXT)
+ $(AM_V_CCLD)$(fdleak_cmsg_LINK) $(fdleak_cmsg_OBJECTS) $(fdleak_cmsg_LDADD) $(LIBS)
+
+fdleak_creat$(EXEEXT): $(fdleak_creat_OBJECTS) $(fdleak_creat_DEPENDENCIES) $(EXTRA_fdleak_creat_DEPENDENCIES)
+ @rm -f fdleak_creat$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(fdleak_creat_OBJECTS) $(fdleak_creat_LDADD) $(LIBS)
+
+fdleak_dup$(EXEEXT): $(fdleak_dup_OBJECTS) $(fdleak_dup_DEPENDENCIES) $(EXTRA_fdleak_dup_DEPENDENCIES)
+ @rm -f fdleak_dup$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(fdleak_dup_OBJECTS) $(fdleak_dup_LDADD) $(LIBS)
+
+fdleak_dup2$(EXEEXT): $(fdleak_dup2_OBJECTS) $(fdleak_dup2_DEPENDENCIES) $(EXTRA_fdleak_dup2_DEPENDENCIES)
+ @rm -f fdleak_dup2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(fdleak_dup2_OBJECTS) $(fdleak_dup2_LDADD) $(LIBS)
+
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+EXTRA_DIST = \
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+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = -O2 -g -std=gnu99 -Wall -Wmissing-prototypes -Wshadow \
+ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \
+ @FLAG_W_CAST_ALIGN@ @FLAG_W_CAST_QUAL@ @FLAG_W_WRITE_STRINGS@ \
+ @FLAG_W_EMPTY_BODY@ @FLAG_W_FORMAT@ @FLAG_W_FORMAT_SIGNEDNESS@ \
+ @FLAG_W_FORMAT_SECURITY@ @FLAG_W_IGNORED_QUALIFIERS@ \
+ @FLAG_W_MISSING_PARAMETER_TYPE@ @FLAG_W_OLD_STYLE_DECLARATION@ \
+ @FLAG_FNO_STACK_PROTECTOR@ @FLAG_FSANITIZE@ \
+ -fno-strict-aliasing -fno-builtin $(am__append_1)
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fpic -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# These flags are used for building the preload shared objects (PSOs).
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads. Also, we must use any
+# -mpreferred-stack-boundary flag to build the preload shared
+# objects, since that risks misaligning the client's stack and
+# results in segfaults like (eg) #324050.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \
+@VGCONF_OS_IS_DARWIN_TRUE@ -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
+ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
+AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
+AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ @FLAG_M64@ $(am__empty)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) @FLAG_M64@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = \
+ filter_stderr
+
+EXTRA_DIST = \
+ bug345887.stderr.exp bug345887.vgtest \
+ map_32bits.stderr.exp map_32bits.vgtest
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/amd64-linux/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/amd64-linux/Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+$(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__empty):
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+
+bug345887$(EXEEXT): $(bug345887_OBJECTS) $(bug345887_DEPENDENCIES) $(EXTRA_bug345887_DEPENDENCIES)
+ @rm -f bug345887$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug345887_OBJECTS) $(bug345887_LDADD) $(LIBS)
+
+map_32bits$(EXEEXT): $(map_32bits_OBJECTS) $(map_32bits_DEPENDENCIES) $(EXTRA_map_32bits_DEPENDENCIES)
+ @rm -f map_32bits$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(map_32bits_OBJECTS) $(map_32bits_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug345887.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/map_32bits.Po@am__quote@
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+.c.o:
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+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ $< &&\
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+ID: $(am__tagged_files)
+ $(am__define_uniq_tagged_files); mkid -fID $$unique
+tags: tags-am
+TAGS: tags
+
+tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+ set x; \
+ here=`pwd`; \
+ $(am__define_uniq_tagged_files); \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: ctags-am
+
+CTAGS: ctags
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+ test -z "$(CTAGS_ARGS)$$unique" \
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+GTAGS:
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+ fi
+mostlyclean-generic:
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+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = -O2 -g -std=gnu99 -Wall -Wmissing-prototypes -Wshadow \
+ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \
+ @FLAG_W_CAST_ALIGN@ @FLAG_W_CAST_QUAL@ @FLAG_W_WRITE_STRINGS@ \
+ @FLAG_W_EMPTY_BODY@ @FLAG_W_FORMAT@ @FLAG_W_FORMAT_SIGNEDNESS@ \
+ @FLAG_W_FORMAT_SECURITY@ @FLAG_W_IGNORED_QUALIFIERS@ \
+ @FLAG_W_MISSING_PARAMETER_TYPE@ @FLAG_W_OLD_STYLE_DECLARATION@ \
+ @FLAG_FNO_STACK_PROTECTOR@ @FLAG_FSANITIZE@ \
+ -fno-strict-aliasing -fno-builtin $(am__append_1)
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fpic -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# These flags are used for building the preload shared objects (PSOs).
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads. Also, we must use any
+# -mpreferred-stack-boundary flag to build the preload shared
+# objects, since that risks misaligning the client's stack and
+# results in segfaults like (eg) #324050.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \
+@VGCONF_OS_IS_DARWIN_TRUE@ -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
+ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
+AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
+AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ @FLAG_M64@ $(am__empty)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) @FLAG_M64@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = \
+ coredump_single_thread_mdb \
+ coredump_single_thread_sse_mdb \
+ filter_stderr
+
+EXTRA_DIST = \
+ coredump_single_thread.post.exp coredump_single_thread.stderr.exp \
+ coredump_single_thread.stdout.exp coredump_single_thread.vgtest \
+ coredump_single_thread_sse.post.exp coredump_single_thread_sse.stderr.exp \
+ coredump_single_thread_sse.stdout.exp coredump_single_thread_sse.vgtest \
+ syscall_return_args.stderr.exp syscall_return_args.vgtest
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/amd64-solaris/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/amd64-solaris/Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+$(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__empty):
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+
+coredump_single_thread$(EXEEXT): $(coredump_single_thread_OBJECTS) $(coredump_single_thread_DEPENDENCIES) $(EXTRA_coredump_single_thread_DEPENDENCIES)
+ @rm -f coredump_single_thread$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(coredump_single_thread_OBJECTS) $(coredump_single_thread_LDADD) $(LIBS)
+
+coredump_single_thread_sse$(EXEEXT): $(coredump_single_thread_sse_OBJECTS) $(coredump_single_thread_sse_DEPENDENCIES) $(EXTRA_coredump_single_thread_sse_DEPENDENCIES)
+ @rm -f coredump_single_thread_sse$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(coredump_single_thread_sse_OBJECTS) $(coredump_single_thread_sse_LDADD) $(LIBS)
+
+syscall_return_args$(EXEEXT): $(syscall_return_args_OBJECTS) $(syscall_return_args_DEPENDENCIES) $(EXTRA_syscall_return_args_DEPENDENCIES)
+ @rm -f syscall_return_args$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(syscall_return_args_OBJECTS) $(syscall_return_args_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coredump_single_thread.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coredump_single_thread_sse.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/syscall_return_args.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.o$$||'`;\
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ $< &&\
+@am__fastdepCC_TRUE@ $(am__mv) $$depbase.Tpo $$depbase.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
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+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.obj$$||'`;\
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ `$(CYGPATH_W) '$<'` &&\
+@am__fastdepCC_TRUE@ $(am__mv) $$depbase.Tpo $$depbase.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
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+ID: $(am__tagged_files)
+ $(am__define_uniq_tagged_files); mkid -fID $$unique
+tags: tags-am
+TAGS: tags
+
+tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+ set x; \
+ here=`pwd`; \
+ $(am__define_uniq_tagged_files); \
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+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
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+ if test $$# -gt 0; then \
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+ fi; \
+ fi
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+ for i in $$list; do \
+ if test -f "$$i"; then \
+ echo "$(subdir)/$$i"; \
+ else \
+ echo "$$sdir/$$i"; \
+ fi; \
+ done >> $(top_builddir)/cscope.files
+
+distclean-tags:
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+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
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+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
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+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
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+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
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+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
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+ "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \
+ fi
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS TAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local cscopelist-am \
+ ctags ctags-am distclean distclean-compile distclean-generic \
+ distclean-tags distdir dvi dvi-am html html-am info info-am \
+ install install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-html \
+ install-html-am install-info install-info-am install-man \
+ install-pdf install-pdf-am install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ maintainer-clean maintainer-clean-generic mostlyclean \
+ mostlyclean-compile mostlyclean-generic pdf pdf-am ps ps-am \
+ tags tags-am uninstall uninstall-am
+
+.PRECIOUS: Makefile
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
+# It needs to be depended on by an 'uninstall-local' rule.
+uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
+uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/none/tests/amd64-solaris/coredump_single_thread.post.exp b/none/tests/amd64-solaris/coredump_single_thread.post.exp
index a5aa542..34bd669 100644
--- a/none/tests/amd64-solaris/coredump_single_thread.post.exp
+++ b/none/tests/amd64-solaris/coredump_single_thread.post.exp
@@ -1,7 +1,6 @@
---Status---
debugging core file of coredump_single (64-bit) from ...
initial argv: ./coredump_single_thread
-threading model: native threads
status: process terminated by SIGSEGV (Segmentation Fault), addr=........
---Registers---
@@ -15,7 +14,7 @@
%r15 = 0x000000000000010e
-%rip = 0x........ coredump_single_thread`inner+0x........
+%rip = 0x........ inner+0x........
%rsp = 0x000000000000010f
@@ -23,7 +22,7 @@
%err = 0x0
---Stack trace---
-coredump_single_thread`inner
-coredump_single_thread`outer
-coredump_single_thread`main
-coredump_single_thread`_start
+inner
+outer
+main
+_start
diff --git a/none/tests/amd64-solaris/coredump_single_thread_mdb b/none/tests/amd64-solaris/coredump_single_thread_mdb
index 00b864f..082d78a 100755
--- a/none/tests/amd64-solaris/coredump_single_thread_mdb
+++ b/none/tests/amd64-solaris/coredump_single_thread_mdb
@@ -7,6 +7,7 @@
echo "::status" | /usr/bin/mdb vgcore.* | \
perl -p -e 's/from \S*$/from .../' | \
perl -0 -p -e 's/^file: .+?^(initial argv:)/$1/ms' | \
+sed '/^threading model:/ d' | \
perl -p -e 's/addr=[0-9A-Fa-f]+/addr=......../g'
echo "\n---Registers---"
diff --git a/none/tests/amd64-solaris/coredump_single_thread_sse.post.exp b/none/tests/amd64-solaris/coredump_single_thread_sse.post.exp
index 9840da5..01acc71 100644
--- a/none/tests/amd64-solaris/coredump_single_thread_sse.post.exp
+++ b/none/tests/amd64-solaris/coredump_single_thread_sse.post.exp
@@ -1,7 +1,6 @@
---Status---
debugging core file of coredump_single (64-bit) from ...
initial argv: ./coredump_single_thread_sse
-threading model: native threads
status: process terminated by SIGSEGV (Segmentation Fault), addr=........
---SSE Registers---
diff --git a/none/tests/amd64-solaris/coredump_single_thread_sse_mdb b/none/tests/amd64-solaris/coredump_single_thread_sse_mdb
index 3cc5413..8d8f550 100755
--- a/none/tests/amd64-solaris/coredump_single_thread_sse_mdb
+++ b/none/tests/amd64-solaris/coredump_single_thread_sse_mdb
@@ -7,6 +7,7 @@
echo "::status" | /usr/bin/mdb vgcore.* | \
perl -p -e 's/from \S*$/from .../' | \
perl -0 -p -e 's/^file: .+?^(initial argv:)/$1/ms' | \
+sed '/^threading model:/ d' | \
perl -p -e 's/addr=[0-9A-Fa-f]+/addr=......../g'
echo "\n---SSE Registers---"
diff --git a/none/tests/amd64/Makefile.am b/none/tests/amd64/Makefile.am
index be4113b..f0cd081 100644
--- a/none/tests/amd64/Makefile.am
+++ b/none/tests/amd64/Makefile.am
@@ -42,6 +42,7 @@
cmpxchg.vgtest cmpxchg.stdout.exp cmpxchg.stderr.exp \
faultstatus.disabled faultstatus.stderr.exp \
fcmovnu.vgtest fcmovnu.stderr.exp fcmovnu.stdout.exp \
+ fma4.vgtest fma4.stdout.exp fma4.stderr.exp \
fxtract.vgtest fxtract.stderr.exp fxtract.stdout.exp \
fxtract.stdout.exp-older-glibc \
getseg.stdout.exp getseg.stderr.exp getseg.vgtest \
@@ -109,6 +110,9 @@
if BUILD_VPCLMULQDQ_TESTS
check_PROGRAMS += avx-1
endif
+if BUILD_FMA4_TESTS
+ check_PROGRAMS += fma4
+endif
endif
if BUILD_AVX2_TESTS
if !COMPILER_IS_ICC
@@ -185,6 +189,11 @@
insn_fpu_LDADD = -lm
insn_pclmulqdq_SOURCES = insn_pclmulqdq.def
fxtract_LDADD = -lm
+fma4_CFLAGS = $(AM_CFLAGS) -std=c99
+if VGCONF_OS_IS_SOLARIS
+fma4_CFLAGS += -D__EXTENSIONS__
+endif
+fma4_LDADD = -lm
.def.c: $(srcdir)/gen_insn_test.pl
$(PERL) $(srcdir)/gen_insn_test.pl < $< > $@
diff --git a/none/tests/amd64/Makefile.in b/none/tests/amd64/Makefile.in
new file mode 100644
index 0000000..7ebb77f
--- /dev/null
+++ b/none/tests/amd64/Makefile.in
@@ -0,0 +1,1602 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+am__is_gnu_make = { \
+ if test -z '$(MAKELEVEL)'; then \
+ false; \
+ elif test -n '$(MAKE_HOST)'; then \
+ true; \
+ elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
+ true; \
+ else \
+ false; \
+ fi; \
+}
+am__make_running_with_option = \
+ case $${target_option-} in \
+ ?) ;; \
+ *) echo "am__make_running_with_option: internal error: invalid" \
+ "target option '$${target_option-}' specified" >&2; \
+ exit 1;; \
+ esac; \
+ has_opt=no; \
+ sane_makeflags=$$MAKEFLAGS; \
+ if $(am__is_gnu_make); then \
+ sane_makeflags=$$MFLAGS; \
+ else \
+ case $$MAKEFLAGS in \
+ *\\[\ \ ]*) \
+ bs=\\; \
+ sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
+ | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \
+ esac; \
+ fi; \
+ skip_next=no; \
+ strip_trailopt () \
+ { \
+ flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
+ }; \
+ for flg in $$sane_makeflags; do \
+ test $$skip_next = yes && { skip_next=no; continue; }; \
+ case $$flg in \
+ *=*|--*) continue;; \
+ -*I) strip_trailopt 'I'; skip_next=yes;; \
+ -*I?*) strip_trailopt 'I';; \
+ -*O) strip_trailopt 'O'; skip_next=yes;; \
+ -*O?*) strip_trailopt 'O';; \
+ -*l) strip_trailopt 'l'; skip_next=yes;; \
+ -*l?*) strip_trailopt 'l';; \
+ -[dEDm]) skip_next=yes;; \
+ -[JT]) skip_next=yes;; \
+ esac; \
+ case $$flg in \
+ *$$target_option*) has_opt=yes; break;; \
+ esac; \
+ done; \
+ test $$has_opt = yes
+am__make_dryrun = (target_option=n; $(am__make_running_with_option))
+am__make_keepgoing = (target_option=k; $(am__make_running_with_option))
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+@COMPILER_IS_CLANG_TRUE@am__append_1 = -Wno-cast-align -Wno-self-assign \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-compare
+
+@SOLARIS_XPG_SYMBOLS_PRESENT_TRUE@am__append_2 = -Wl,-M,$(top_srcdir)/solaris/vgpreload-solaris.mapfile
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_3 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+
+# Make sure that all test programs have threaded errno.
+# Disable largefile support as there are test cases explictly enabling it.
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
+@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
+@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-constant-out-of-range-compare \
+@COMPILER_IS_CLANG_TRUE@ -Wno-self-assign -Wno-string-plus-int \
+@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
+@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
+@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
+@BUILD_SSE3_TESTS_TRUE@am__append_8 = insn_sse3
+@BUILD_SSSE3_TESTS_TRUE@am__append_9 = insn_ssse3
+@BUILD_PCLMULQDQ_TESTS_TRUE@am__append_10 = insn_pclmulqdq
+check_PROGRAMS = allexec$(EXEEXT) amd64locked$(EXEEXT) \
+ bug127521-64$(EXEEXT) bug132813-amd64$(EXEEXT) \
+ bug132918$(EXEEXT) bug137714-amd64$(EXEEXT) clc$(EXEEXT) \
+ cmpxchg$(EXEEXT) getseg$(EXEEXT) $(am__EXEEXT_4) \
+ nan80and64$(EXEEXT) rcl-amd64$(EXEEXT) redundantRexW$(EXEEXT) \
+ smc1$(EXEEXT) sbbmisc$(EXEEXT) nibz_bennee_mmap$(EXEEXT) \
+ x87trigOOR$(EXEEXT) xadd$(EXEEXT) $(am__EXEEXT_5) \
+ $(am__EXEEXT_6) $(am__EXEEXT_7) $(am__EXEEXT_8) \
+ $(am__EXEEXT_9) $(am__EXEEXT_10) $(am__EXEEXT_11) \
+ $(am__EXEEXT_12) $(am__EXEEXT_13) $(am__EXEEXT_14) \
+ $(am__EXEEXT_15) $(am__EXEEXT_16) $(am__EXEEXT_17) \
+ $(am__EXEEXT_18)
+@BUILD_ADDR32_TESTS_TRUE@am__append_11 = asorep
+@BUILD_AVX_TESTS_TRUE@@BUILD_VPCLMULQDQ_TESTS_TRUE@am__append_12 = avx-1
+@BUILD_AVX_TESTS_TRUE@@BUILD_FMA4_TESTS_TRUE@am__append_13 = fma4
+@BUILD_AVX2_TESTS_TRUE@@COMPILER_IS_ICC_FALSE@am__append_14 = avx2-1
+@BUILD_SSSE3_TESTS_TRUE@am__append_15 = ssse3_misaligned
+@BUILD_LZCNT_TESTS_TRUE@am__append_16 = lzcnt64
+@BUILD_MOVBE_TESTS_TRUE@am__append_17 = movbe
+@BUILD_SSE42_TESTS_TRUE@am__append_18 = \
+@BUILD_SSE42_TESTS_TRUE@ pcmpstr64 pcmpxstrx64 sse4-64 crc32 aes \
+@BUILD_SSE42_TESTS_TRUE@ pcmpstr64w pcmpxstrx64w
+
+@BUILD_TSX_TESTS_TRUE@am__append_19 = tm1 xacq_xrel
+@BUILD_BMI_TESTS_TRUE@am__append_20 = bmi
+@BUILD_FMA_TESTS_TRUE@am__append_21 = fma
+@BUILD_MPX_TESTS_TRUE@am__append_22 = mpx
+
+# DDD: these need to be made to work on Darwin like the x86/ ones were.
+@VGCONF_OS_IS_DARWIN_FALSE@am__append_23 = \
+@VGCONF_OS_IS_DARWIN_FALSE@ bug156404-amd64 \
+@VGCONF_OS_IS_DARWIN_FALSE@ faultstatus \
+@VGCONF_OS_IS_DARWIN_FALSE@ fcmovnu \
+@VGCONF_OS_IS_DARWIN_FALSE@ fxtract \
+@VGCONF_OS_IS_DARWIN_FALSE@ looper \
+@VGCONF_OS_IS_DARWIN_FALSE@ jrcxz \
+@VGCONF_OS_IS_DARWIN_FALSE@ shrld \
+@VGCONF_OS_IS_DARWIN_FALSE@ slahf-amd64
+
+@BUILD_LOOPNEL_TESTS_TRUE@@VGCONF_OS_IS_DARWIN_FALSE@am__append_24 = loopnel
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_25 = -D__EXTENSIONS__
+subdir = none/tests/amd64
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.ac
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+DIST_COMMON = $(srcdir)/Makefile.am $(dist_noinst_SCRIPTS) \
+ $(am__DIST_COMMON)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+@BUILD_SSE3_TESTS_TRUE@am__EXEEXT_1 = insn_sse3$(EXEEXT)
+@BUILD_SSSE3_TESTS_TRUE@am__EXEEXT_2 = insn_ssse3$(EXEEXT)
+@BUILD_PCLMULQDQ_TESTS_TRUE@am__EXEEXT_3 = insn_pclmulqdq$(EXEEXT)
+am__EXEEXT_4 = insn_basic$(EXEEXT) insn_mmx$(EXEEXT) insn_sse$(EXEEXT) \
+ insn_sse2$(EXEEXT) insn_fpu$(EXEEXT) $(am__EXEEXT_1) \
+ $(am__EXEEXT_2) $(am__EXEEXT_3)
+@BUILD_ADDR32_TESTS_TRUE@am__EXEEXT_5 = asorep$(EXEEXT)
+@BUILD_AVX_TESTS_TRUE@@BUILD_VPCLMULQDQ_TESTS_TRUE@am__EXEEXT_6 = avx-1$(EXEEXT)
+@BUILD_AVX_TESTS_TRUE@@BUILD_FMA4_TESTS_TRUE@am__EXEEXT_7 = \
+@BUILD_AVX_TESTS_TRUE@@BUILD_FMA4_TESTS_TRUE@ fma4$(EXEEXT)
+@BUILD_AVX2_TESTS_TRUE@@COMPILER_IS_ICC_FALSE@am__EXEEXT_8 = \
+@BUILD_AVX2_TESTS_TRUE@@COMPILER_IS_ICC_FALSE@ avx2-1$(EXEEXT)
+@BUILD_SSSE3_TESTS_TRUE@am__EXEEXT_9 = ssse3_misaligned$(EXEEXT)
+@BUILD_LZCNT_TESTS_TRUE@am__EXEEXT_10 = lzcnt64$(EXEEXT)
+@BUILD_MOVBE_TESTS_TRUE@am__EXEEXT_11 = movbe$(EXEEXT)
+@BUILD_SSE42_TESTS_TRUE@am__EXEEXT_12 = pcmpstr64$(EXEEXT) \
+@BUILD_SSE42_TESTS_TRUE@ pcmpxstrx64$(EXEEXT) sse4-64$(EXEEXT) \
+@BUILD_SSE42_TESTS_TRUE@ crc32$(EXEEXT) aes$(EXEEXT) \
+@BUILD_SSE42_TESTS_TRUE@ pcmpstr64w$(EXEEXT) \
+@BUILD_SSE42_TESTS_TRUE@ pcmpxstrx64w$(EXEEXT)
+@BUILD_TSX_TESTS_TRUE@am__EXEEXT_13 = tm1$(EXEEXT) xacq_xrel$(EXEEXT)
+@BUILD_BMI_TESTS_TRUE@am__EXEEXT_14 = bmi$(EXEEXT)
+@BUILD_FMA_TESTS_TRUE@am__EXEEXT_15 = fma$(EXEEXT)
+@BUILD_MPX_TESTS_TRUE@am__EXEEXT_16 = mpx$(EXEEXT)
+@VGCONF_OS_IS_DARWIN_FALSE@am__EXEEXT_17 = bug156404-amd64$(EXEEXT) \
+@VGCONF_OS_IS_DARWIN_FALSE@ faultstatus$(EXEEXT) \
+@VGCONF_OS_IS_DARWIN_FALSE@ fcmovnu$(EXEEXT) fxtract$(EXEEXT) \
+@VGCONF_OS_IS_DARWIN_FALSE@ looper$(EXEEXT) jrcxz$(EXEEXT) \
+@VGCONF_OS_IS_DARWIN_FALSE@ shrld$(EXEEXT) slahf-amd64$(EXEEXT)
+@BUILD_LOOPNEL_TESTS_TRUE@@VGCONF_OS_IS_DARWIN_FALSE@am__EXEEXT_18 = loopnel$(EXEEXT)
+aes_SOURCES = aes.c
+aes_OBJECTS = aes.$(OBJEXT)
+aes_LDADD = $(LDADD)
+allexec_SOURCES = allexec.c
+allexec_OBJECTS = allexec-allexec.$(OBJEXT)
+allexec_LDADD = $(LDADD)
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+#----------------------------------------------------------------------------
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+# Baseline flags for all compilations. Aim here is to maximise
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+
+# These flags are used for building the preload shared objects (PSOs).
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+# objects, since that risks misaligning the client's stack and
+# results in segfaults like (eg) #324050.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \
+@VGCONF_OS_IS_DARWIN_TRUE@ -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
+ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
+AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
+AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ @FLAG_M64@ $(am__empty)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) @FLAG_M64@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_cpuid filter_inf_nan filter_stderr gen_insn_test.pl
+CLEANFILES = $(addsuffix .c,$(INSN_TESTS))
+INSN_TESTS = insn_basic insn_mmx insn_sse insn_sse2 insn_fpu \
+ $(am__append_8) $(am__append_9) $(am__append_10)
+
+# Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS,
+# to avoid packaging screwups if 'make dist' is run on a machine
+# which failed the BUILD_SSE3_TESTS test in configure.in.
+EXTRA_DIST = \
+ aes.vgtest aes.stdout.exp aes.stderr.exp \
+ amd64locked.vgtest amd64locked.stdout.exp amd64locked.stderr.exp \
+ avx-1.vgtest avx-1.stdout.exp avx-1.stderr.exp \
+ avx2-1.vgtest avx2-1.stdout.exp avx2-1.stderr.exp \
+ asorep.stderr.exp asorep.stdout.exp asorep.vgtest \
+ bmi.stderr.exp bmi.stdout.exp bmi.vgtest \
+ fma.stderr.exp fma.stdout.exp fma.vgtest \
+ bug127521-64.vgtest bug127521-64.stdout.exp bug127521-64.stderr.exp \
+ bug132813-amd64.vgtest bug132813-amd64.stdout.exp \
+ bug132813-amd64.stderr.exp \
+ bug137714-amd64.vgtest bug137714-amd64.stdout.exp \
+ bug137714-amd64.stderr.exp \
+ bug132918.vgtest bug132918.stderr.exp bug132918.stdout.exp \
+ bug132918.stdout.exp-older-glibc \
+ bug156404-amd64.vgtest bug156404-amd64.stdout.exp \
+ bug156404-amd64.stderr.exp \
+ clc.vgtest clc.stdout.exp clc.stderr.exp \
+ crc32.vgtest crc32.stdout.exp crc32.stderr.exp \
+ cmpxchg.vgtest cmpxchg.stdout.exp cmpxchg.stderr.exp \
+ faultstatus.disabled faultstatus.stderr.exp \
+ fcmovnu.vgtest fcmovnu.stderr.exp fcmovnu.stdout.exp \
+ fma4.vgtest fma4.stdout.exp fma4.stderr.exp \
+ fxtract.vgtest fxtract.stderr.exp fxtract.stdout.exp \
+ fxtract.stdout.exp-older-glibc \
+ getseg.stdout.exp getseg.stderr.exp getseg.vgtest \
+ $(addsuffix .stderr.exp,$(INSN_TESTS)) \
+ $(addsuffix .stdout.exp,$(INSN_TESTS)) \
+ $(addsuffix .vgtest,$(INSN_TESTS)) \
+ insn_pclmulqdq.vgtest insn_pclmulqdq.stdout.exp \
+ insn_pclmulqdq.stderr.exp \
+ insn_sse3.stdout.exp insn_sse3.stderr.exp insn_sse3.vgtest \
+ insn_ssse3.stdout.exp insn_ssse3.stderr.exp insn_ssse3.vgtest \
+ jrcxz.stderr.exp jrcxz.stdout.exp jrcxz.vgtest \
+ looper.stderr.exp looper.stdout.exp looper.vgtest \
+ loopnel.stderr.exp loopnel.stdout.exp loopnel.vgtest \
+ lzcnt64.stderr.exp lzcnt64.stdout.exp lzcnt64.vgtest \
+ movbe.stderr.exp movbe.stdout.exp movbe.vgtest \
+ mpx.stderr.exp mpx.stdout.exp mpx.vgtest \
+ nan80and64.stderr.exp nan80and64.stdout.exp nan80and64.vgtest \
+ nibz_bennee_mmap.stderr.exp nibz_bennee_mmap.stdout.exp \
+ nibz_bennee_mmap.vgtest \
+ pcmpstr64.stderr.exp pcmpstr64.stdout.exp \
+ pcmpstr64.vgtest \
+ pcmpstr64w.stderr.exp pcmpstr64w.stdout.exp \
+ pcmpstr64w.vgtest \
+ pcmpxstrx64.stderr.exp pcmpxstrx64.stdout.exp \
+ pcmpxstrx64.vgtest \
+ pcmpxstrx64w.stderr.exp pcmpxstrx64w.stdout.exp \
+ pcmpxstrx64w.vgtest \
+ rcl-amd64.vgtest rcl-amd64.stdout.exp rcl-amd64.stderr.exp \
+ redundantRexW.vgtest redundantRexW.stdout.exp \
+ redundantRexW.stderr.exp \
+ smc1.stderr.exp smc1.stdout.exp smc1.vgtest \
+ sbbmisc.stderr.exp sbbmisc.stdout.exp sbbmisc.vgtest \
+ shrld.stderr.exp shrld.stdout.exp shrld.vgtest \
+ ssse3_misaligned.stderr.exp ssse3_misaligned.stdout.exp \
+ ssse3_misaligned.vgtest \
+ sse4-64.stderr.exp sse4-64.stdout.exp sse4-64.vgtest \
+ sse4-64.stdout.exp-older-glibc \
+ slahf-amd64.stderr.exp slahf-amd64.stdout.exp \
+ slahf-amd64.vgtest \
+ tm1.vgtest tm1.stderr.exp tm1.stdout.exp \
+ x87trigOOR.vgtest x87trigOOR.stderr.exp x87trigOOR.stdout.exp \
+ xacq_xrel.stderr.exp xacq_xrel.stdout.exp xacq_xrel.vgtest \
+ xadd.stderr.exp xadd.stdout.exp xadd.vgtest
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+
+# generic C ones
+amd64locked_CFLAGS = $(AM_CFLAGS) -O
+bug132918_LDADD = -lm
+fxtract_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_OVERFLOW@
+insn_basic_SOURCES = insn_basic.def
+insn_basic_LDADD = -lm
+insn_mmx_SOURCES = insn_mmx.def
+insn_mmx_LDADD = -lm
+insn_sse_SOURCES = insn_sse.def
+insn_sse_LDADD = -lm
+insn_sse2_SOURCES = insn_sse2.def
+insn_sse2_LDADD = -lm
+insn_sse3_SOURCES = insn_sse3.def
+insn_sse3_LDADD = -lm
+insn_ssse3_SOURCES = insn_ssse3.def
+insn_ssse3_LDADD = -lm
+insn_fpu_SOURCES = insn_fpu.def
+insn_fpu_LDADD = -lm
+insn_pclmulqdq_SOURCES = insn_pclmulqdq.def
+fxtract_LDADD = -lm
+fma4_CFLAGS = $(AM_CFLAGS) -std=c99 $(am__append_25)
+fma4_LDADD = -lm
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .def .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/amd64/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/amd64/Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+$(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__empty):
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+
+aes$(EXEEXT): $(aes_OBJECTS) $(aes_DEPENDENCIES) $(EXTRA_aes_DEPENDENCIES)
+ @rm -f aes$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(aes_OBJECTS) $(aes_LDADD) $(LIBS)
+
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES) $(EXTRA_allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(AM_V_CCLD)$(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+
+amd64locked$(EXEEXT): $(amd64locked_OBJECTS) $(amd64locked_DEPENDENCIES) $(EXTRA_amd64locked_DEPENDENCIES)
+ @rm -f amd64locked$(EXEEXT)
+ $(AM_V_CCLD)$(amd64locked_LINK) $(amd64locked_OBJECTS) $(amd64locked_LDADD) $(LIBS)
+
+asorep$(EXEEXT): $(asorep_OBJECTS) $(asorep_DEPENDENCIES) $(EXTRA_asorep_DEPENDENCIES)
+ @rm -f asorep$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(asorep_OBJECTS) $(asorep_LDADD) $(LIBS)
+
+avx-1$(EXEEXT): $(avx_1_OBJECTS) $(avx_1_DEPENDENCIES) $(EXTRA_avx_1_DEPENDENCIES)
+ @rm -f avx-1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(avx_1_OBJECTS) $(avx_1_LDADD) $(LIBS)
+
+avx2-1$(EXEEXT): $(avx2_1_OBJECTS) $(avx2_1_DEPENDENCIES) $(EXTRA_avx2_1_DEPENDENCIES)
+ @rm -f avx2-1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(avx2_1_OBJECTS) $(avx2_1_LDADD) $(LIBS)
+
+bmi$(EXEEXT): $(bmi_OBJECTS) $(bmi_DEPENDENCIES) $(EXTRA_bmi_DEPENDENCIES)
+ @rm -f bmi$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bmi_OBJECTS) $(bmi_LDADD) $(LIBS)
+
+bug127521-64$(EXEEXT): $(bug127521_64_OBJECTS) $(bug127521_64_DEPENDENCIES) $(EXTRA_bug127521_64_DEPENDENCIES)
+ @rm -f bug127521-64$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug127521_64_OBJECTS) $(bug127521_64_LDADD) $(LIBS)
+
+bug132813-amd64$(EXEEXT): $(bug132813_amd64_OBJECTS) $(bug132813_amd64_DEPENDENCIES) $(EXTRA_bug132813_amd64_DEPENDENCIES)
+ @rm -f bug132813-amd64$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug132813_amd64_OBJECTS) $(bug132813_amd64_LDADD) $(LIBS)
+
+bug132918$(EXEEXT): $(bug132918_OBJECTS) $(bug132918_DEPENDENCIES) $(EXTRA_bug132918_DEPENDENCIES)
+ @rm -f bug132918$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug132918_OBJECTS) $(bug132918_LDADD) $(LIBS)
+
+bug137714-amd64$(EXEEXT): $(bug137714_amd64_OBJECTS) $(bug137714_amd64_DEPENDENCIES) $(EXTRA_bug137714_amd64_DEPENDENCIES)
+ @rm -f bug137714-amd64$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug137714_amd64_OBJECTS) $(bug137714_amd64_LDADD) $(LIBS)
+
+bug156404-amd64$(EXEEXT): $(bug156404_amd64_OBJECTS) $(bug156404_amd64_DEPENDENCIES) $(EXTRA_bug156404_amd64_DEPENDENCIES)
+ @rm -f bug156404-amd64$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug156404_amd64_OBJECTS) $(bug156404_amd64_LDADD) $(LIBS)
+
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+fma4-fma4.obj: fma4.c
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+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/fma4-fma4.Tpo $(DEPDIR)/fma4-fma4.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='fma4.c' object='fma4-fma4.obj' libtool=no @AMDEPBACKSLASH@
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+
+fxtract-fxtract.o: fxtract.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fxtract_CFLAGS) $(CFLAGS) -MT fxtract-fxtract.o -MD -MP -MF $(DEPDIR)/fxtract-fxtract.Tpo -c -o fxtract-fxtract.o `test -f 'fxtract.c' || echo '$(srcdir)/'`fxtract.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/fxtract-fxtract.Tpo $(DEPDIR)/fxtract-fxtract.Po
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+fxtract-fxtract.obj: fxtract.c
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+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/fxtract-fxtract.Tpo $(DEPDIR)/fxtract-fxtract.Po
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+
+ID: $(am__tagged_files)
+ $(am__define_uniq_tagged_files); mkid -fID $$unique
+tags: tags-am
+TAGS: tags
+
+tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+ set x; \
+ here=`pwd`; \
+ $(am__define_uniq_tagged_files); \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: ctags-am
+
+CTAGS: ctags
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+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+cscopelist: cscopelist-am
+
+cscopelist-am: $(am__tagged_files)
+ list='$(am__tagged_files)'; \
+ case "$(srcdir)" in \
+ [\\/]* | ?:[\\/]*) sdir="$(srcdir)" ;; \
+ *) sdir=$(subdir)/$(srcdir) ;; \
+ esac; \
+ for i in $$list; do \
+ if test -f "$$i"; then \
+ echo "$(subdir)/$$i"; \
+ else \
+ echo "$$sdir/$$i"; \
+ fi; \
+ done >> $(top_builddir)/cscope.files
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
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+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ install; \
+ else \
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \
+ fi
+mostlyclean-generic:
+
+clean-generic:
+ -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
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+info: info-am
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+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
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+ clean-checkPROGRAMS clean-generic clean-local cscopelist-am \
+ ctags ctags-am distclean distclean-compile distclean-generic \
+ distclean-tags distdir dvi dvi-am html html-am info info-am \
+ install install-am install-data install-data-am install-dvi \
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+ install-html-am install-info install-info-am install-man \
+ install-pdf install-pdf-am install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ maintainer-clean maintainer-clean-generic mostlyclean \
+ mostlyclean-compile mostlyclean-generic pdf pdf-am ps ps-am \
+ tags tags-am uninstall uninstall-am
+
+.PRECIOUS: Makefile
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
+# It needs to be depended on by an 'uninstall-local' rule.
+uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
+uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+.def.c: $(srcdir)/gen_insn_test.pl
+ $(PERL) $(srcdir)/gen_insn_test.pl < $< > $@
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/none/tests/amd64/allexec.c b/none/tests/amd64/allexec.c
deleted file mode 120000
index 6d6a9cf..0000000
--- a/none/tests/amd64/allexec.c
+++ /dev/null
@@ -1 +0,0 @@
-../allexec.c
\ No newline at end of file
diff --git a/none/tests/allexec.c b/none/tests/amd64/allexec.c
similarity index 100%
copy from none/tests/allexec.c
copy to none/tests/amd64/allexec.c
diff --git a/none/tests/amd64/fma4.c b/none/tests/amd64/fma4.c
new file mode 100644
index 0000000..d9ca3c8
--- /dev/null
+++ b/none/tests/amd64/fma4.c
@@ -0,0 +1,659 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+#include <math.h>
+#include "tests/malloc.h"
+
+typedef unsigned char UChar;
+typedef unsigned int UInt;
+typedef unsigned long int UWord;
+typedef unsigned long long int ULong;
+typedef double Double;
+typedef float Float;
+
+#define IS_32_ALIGNED(_ptr) (0 == (0x1F & (UWord)(_ptr)))
+
+typedef union { UChar u8[16]; UInt u32[4]; Float f32[4]; Double f64[2]; } XMM;
+typedef union { UChar u8[32]; UInt u32[8]; XMM xmm[2]; } YMM;
+typedef struct { YMM r1; YMM r2; YMM r3; YMM r4; YMM m; } Block;
+
+void showFloat ( XMM* vec, int idx )
+{
+ Float f = vec->f32[idx];
+ int neg = signbit (f);
+ char sign = neg != 0 ? '-' : ' ';
+ switch (fpclassify (f)) {
+ case FP_NORMAL: {
+ for (int i = idx * 4 + 3; i >= idx * 4; i--)
+ printf("%02x", (UInt)vec->u8[i]);
+ break;
+ }
+ case FP_INFINITE: {
+ printf ("[ %cINF ]", sign);
+ break;
+ }
+ case FP_ZERO: {
+ printf ("[%cZERO ]", sign);
+ break;
+ }
+ case FP_NAN: {
+ printf ("[ NAN ]");
+ break;
+ }
+ default: {
+ printf ("[%cSUBNR]", sign);
+ break;
+ }
+ }
+}
+
+void showDouble ( XMM* vec, int idx )
+{
+ Double d = vec->f64[idx];
+ int neg = signbit (d);
+ char sign = neg != 0 ? '-' : ' ';
+ switch (fpclassify (d)) {
+ case FP_NORMAL: {
+ for (int i = idx * 8 + 7; i >= idx * 8; i--)
+ printf("%02x", (UInt)vec->u8[i]);
+ break;
+ }
+ case FP_INFINITE: {
+ printf ("[ %cINF ]", sign);
+ break;
+ }
+ case FP_ZERO: {
+ printf ("[ %cZERO ]", sign);
+ break;
+ }
+ case FP_NAN: {
+ printf ("[ NAN ]");
+ break;
+ }
+ default: {
+ printf ("[ %cSUBNORMAL ]", sign);
+ break;
+ }
+ }
+}
+
+void showXMM ( XMM* vec, int isDouble )
+{
+ if (isDouble) {
+ showDouble ( vec, 1 );
+ printf (".");
+ showDouble ( vec, 0 );
+ } else {
+ showFloat ( vec, 3 );
+ printf (".");
+ showFloat ( vec, 2 );
+ printf (".");
+ showFloat ( vec, 1 );
+ printf (".");
+ showFloat ( vec, 0 );
+ }
+}
+
+void showYMM ( YMM* vec, int isDouble )
+{
+ assert(IS_32_ALIGNED(vec));
+ showXMM ( &vec->xmm[1], isDouble );
+ printf(".");
+ showXMM ( &vec->xmm[0], isDouble );
+}
+
+void showBlock ( char* msg, Block* block, int isDouble )
+{
+ printf(" %s\n", msg);
+ printf("r1: "); showYMM(&block->r1, isDouble); printf("\n");
+ printf("r2: "); showYMM(&block->r2, isDouble); printf("\n");
+ printf("r3: "); showYMM(&block->r3, isDouble); printf("\n");
+ printf("r4: "); showYMM(&block->r4, isDouble); printf("\n");
+ printf(" m: "); showYMM(&block->m, isDouble); printf("\n");
+}
+
+static Double special_values[10];
+
+static __attribute__((noinline))
+Double negate ( Double d ) { return -d; }
+static __attribute__((noinline))
+Double divf64 ( Double x, Double y ) { return x/y; }
+
+static __attribute__((noinline))
+Double plusZero ( void ) { return 0.0; }
+static __attribute__((noinline))
+Double minusZero ( void ) { return negate(plusZero()); }
+
+static __attribute__((noinline))
+Double plusOne ( void ) { return 1.0; }
+static __attribute__((noinline))
+Double minusOne ( void ) { return negate(plusOne()); }
+
+static __attribute__((noinline))
+Double plusInf ( void ) { return 1.0 / 0.0; }
+static __attribute__((noinline))
+Double minusInf ( void ) { return negate(plusInf()); }
+
+static __attribute__((noinline))
+Double plusNaN ( void ) { return divf64(plusInf(),plusInf()); }
+static __attribute__((noinline))
+Double minusNaN ( void ) { return negate(plusNaN()); }
+
+static __attribute__((noinline))
+Double plusDenorm ( void ) { return 1.23e-315 / 1e3; }
+static __attribute__((noinline))
+Double minusDenorm ( void ) { return negate(plusDenorm()); }
+
+static void init_special_values ( void )
+{
+ special_values[0] = plusZero();
+ special_values[1] = minusZero();
+ special_values[2] = plusOne();
+ special_values[3] = minusOne();
+ special_values[4] = plusInf();
+ special_values[5] = minusInf();
+ special_values[6] = plusNaN();
+ special_values[7] = minusNaN();
+ special_values[8] = plusDenorm();
+ special_values[9] = minusDenorm();
+}
+
+void specialFBlock ( Block* b )
+{
+ int i;
+ Float* p = (Float*)b;
+ for (i = 0; i < sizeof(Block) / sizeof(Float); i++)
+ p[i] = (Float) special_values[i % 10];
+}
+
+void specialDBlock ( Block* b )
+{
+ int i;
+ Double* p = (Double*)b;
+ for (i = 0; i < sizeof(Block) / sizeof(Double); i++)
+ p[i] = special_values[i % 10];
+}
+
+UChar randUChar ( void )
+{
+ static UInt seed = 80021;
+ seed = 1103515245 * seed + 12345;
+ return (seed >> 17) & 0xFF;
+}
+
+void randBlock ( Block* b )
+{
+ int i;
+ UChar* p = (UChar*)b;
+ for (i = 0; i < sizeof(Block); i++)
+ p[i] = randUChar();
+}
+
+void oneBlock ( Block* b )
+{
+ int i;
+ UChar* p = (UChar*)b;
+ for (i = 0; i < sizeof(Block); i++)
+ p[i] = 1;
+}
+
+#define GEN_test(_name, _instr, _isD) \
+ __attribute__ ((noinline)) void \
+ test_##_name ( const char *n, Block* b) \
+ { \
+ printf("%s %s\n", #_name, n); \
+ showBlock("before", b, _isD); \
+ __asm__ __volatile__( \
+ "vmovdqa 0(%0),%%ymm7" "\n\t" \
+ "vmovdqa 32(%0),%%ymm8" "\n\t" \
+ "vmovdqa 64(%0),%%ymm6" "\n\t" \
+ "vmovdqa 96(%0),%%ymm9" "\n\t" \
+ "leaq 128(%0),%%r14" "\n\t" \
+ _instr "\n\t" \
+ "vmovdqa %%ymm7, 0(%0)" "\n\t" \
+ "vmovdqa %%ymm8, 32(%0)" "\n\t" \
+ "vmovdqa %%ymm6, 64(%0)" "\n\t" \
+ "vmovdqa %%ymm9, 96(%0)" "\n\t" \
+ : /*OUT*/ \
+ : /*IN*/"r"(b) \
+ : /*TRASH*/"xmm7","xmm8","xmm6","xmm9","r14","memory","cc" \
+ ); \
+ showBlock("after", b, _isD); \
+ printf("\n"); \
+ }
+
+/* All these defines do the same thing (and someone with stronger
+ preprocessor foo could probably express things much smaller).
+ They generate 4 different functions to test 4 variants of an
+ fma4 instruction. One with as input 4 registers, one where
+ the output register is also one of the input registers and
+ two versions where different inputs are a memory location.
+ The xmm variants create 128 versions, the ymm variants 256. */
+
+#define GEN_test_VFMADDPD_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfmaddpd %%xmm7,%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfmaddpd %%xmm7,%%xmm8,%%xmm9,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfmaddpd (%%r14),%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfmaddpd %%xmm8,(%%r14),%%xmm6,%%xmm9", 1);
+GEN_test_VFMADDPD_xmm(VFMADDPD)
+
+#define GEN_test_VFMADDPD_ymm(_name) \
+ GEN_test(_name##_ymm, \
+ "vfmaddpd %%ymm7,%%ymm8,%%ymm6,%%ymm9", 1); \
+ GEN_test(_name##_ymm_src_dst, \
+ "vfmaddpd %%ymm7,%%ymm8,%%ymm9,%%ymm9", 1); \
+ GEN_test(_name##_ymm_mem1, \
+ "vfmaddpd (%%r14),%%ymm8,%%ymm6,%%ymm9", 1); \
+ GEN_test(_name##_ymm_mem2, \
+ "vfmaddpd %%ymm8,(%%r14),%%ymm6,%%ymm9", 1);
+GEN_test_VFMADDPD_ymm(VFMADDPD)
+
+#define GEN_test_VFMADDPS_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfmaddps %%xmm7,%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfmaddps %%xmm7,%%xmm8,%%xmm9,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfmaddps (%%r14),%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfmaddps %%xmm8,(%%r14),%%xmm6,%%xmm9", 0);
+GEN_test_VFMADDPS_xmm(VFMADDPS)
+
+#define GEN_test_VFMADDPS_ymm(_name) \
+ GEN_test(_name##_ymm, \
+ "vfmaddps %%ymm7,%%ymm8,%%ymm6,%%ymm9", 0); \
+ GEN_test(_name##_ymm_src_dst, \
+ "vfmaddps %%ymm7,%%ymm8,%%ymm9,%%ymm9", 0); \
+ GEN_test(_name##_ymm_mem1, \
+ "vfmaddps (%%r14),%%ymm8,%%ymm6,%%ymm9", 0); \
+ GEN_test(_name##_ymm_mem2, \
+ "vfmaddps %%ymm8,(%%r14),%%ymm6,%%ymm9", 0);
+GEN_test_VFMADDPS_ymm(VFMADDPS)
+
+#define GEN_test_VFMADDSD_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfmaddsd %%xmm7,%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfmaddsd %%xmm7,%%xmm8,%%xmm9,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfmaddsd (%%r14),%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfmaddsd %%xmm8,(%%r14),%%xmm6,%%xmm9", 1);
+GEN_test_VFMADDSD_xmm(VFMADDSD)
+
+#define GEN_test_VFMADDSS_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfmaddss %%xmm7,%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfmaddss %%xmm7,%%xmm8,%%xmm9,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfmaddss (%%r14),%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfmaddss %%xmm8,(%%r14),%%xmm6,%%xmm9", 0);
+GEN_test_VFMADDSS_xmm(VFMADDSS)
+
+#define GEN_test_VFMADDSUBPD_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfmaddsubpd %%xmm7,%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfmaddsubpd %%xmm7,%%xmm8,%%xmm9,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfmaddsubpd (%%r14),%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfmaddsubpd %%xmm8,(%%r14),%%xmm6,%%xmm9", 1);
+GEN_test_VFMADDSUBPD_xmm(VFMADDSUBPD)
+
+#define GEN_test_VFMADDSUBPD_ymm(_name) \
+ GEN_test(_name##_ymm, \
+ "vfmaddsubpd %%ymm7,%%ymm8,%%ymm6,%%ymm9", 1); \
+ GEN_test(_name##_ymm_src_dst, \
+ "vfmaddsubpd %%ymm7,%%ymm8,%%ymm9,%%ymm9", 1); \
+ GEN_test(_name##_ymm_mem1, \
+ "vfmaddsubpd (%%r14),%%ymm8,%%ymm6,%%ymm9", 1); \
+ GEN_test(_name##_ymm_mem2, \
+ "vfmaddsubpd %%ymm8,(%%r14),%%ymm6,%%ymm9", 1);
+GEN_test_VFMADDSUBPD_ymm(VFMADDSUBPD)
+
+#define GEN_test_VFMADDSUBPS_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfmaddsubps %%xmm7,%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfmaddsubps %%xmm7,%%xmm8,%%xmm9,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfmaddsubps (%%r14),%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfmaddsubps %%xmm8,(%%r14),%%xmm6,%%xmm9", 0);
+GEN_test_VFMADDSUBPS_xmm(VFMADDSUBPS)
+
+#define GEN_test_VFMADDSUBPS_ymm(_name) \
+ GEN_test(_name##_ymm, \
+ "vfmaddsubps %%ymm7,%%ymm8,%%ymm6,%%ymm9", 0); \
+ GEN_test(_name##_ymm_src_dst, \
+ "vfmaddsubps %%ymm7,%%ymm8,%%ymm9,%%ymm9", 0); \
+ GEN_test(_name##_ymm_mem1, \
+ "vfmaddsubps (%%r14),%%ymm8,%%ymm6,%%ymm9", 0); \
+ GEN_test(_name##_ymm_mem2, \
+ "vfmaddsubps %%ymm8,(%%r14),%%ymm6,%%ymm9", 0);
+GEN_test_VFMADDSUBPS_ymm(VFMADDSUBPS)
+
+#define GEN_test_VFMSUBADDPD_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfmsubaddpd %%xmm7,%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfmsubaddpd %%xmm7,%%xmm8,%%xmm9,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfmsubaddpd (%%r14),%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfmsubaddpd %%xmm8,(%%r14),%%xmm6,%%xmm9", 1);
+GEN_test_VFMSUBADDPD_xmm(VFMSUBADDPD)
+
+#define GEN_test_VFMSUBADDPD_ymm(_name) \
+ GEN_test(_name##_ymm, \
+ "vfmsubaddpd %%ymm7,%%ymm8,%%ymm6,%%ymm9", 1); \
+ GEN_test(_name##_ymm_src_dst, \
+ "vfmsubaddpd %%ymm7,%%ymm8,%%ymm9,%%ymm9", 1); \
+ GEN_test(_name##_ymm_mem1, \
+ "vfmsubaddpd (%%r14),%%ymm8,%%ymm6,%%ymm9", 1); \
+ GEN_test(_name##_ymm_mem2, \
+ "vfmsubaddpd %%ymm8,(%%r14),%%ymm6,%%ymm9", 1);
+GEN_test_VFMSUBADDPD_ymm(VFMSUBADDPD)
+
+#define GEN_test_VFMSUBADDPS_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfmsubaddps %%xmm7,%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfmsubaddps %%xmm7,%%xmm8,%%xmm9,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfmsubaddps (%%r14),%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfmsubaddps %%xmm8,(%%r14),%%xmm6,%%xmm9", 0);
+GEN_test_VFMSUBADDPS_xmm(VFMSUBADDPS)
+
+#define GEN_test_VFMSUBADDPS_ymm(_name) \
+ GEN_test(_name##_ymm, \
+ "vfmsubaddps %%ymm7,%%ymm8,%%ymm6,%%ymm9", 0); \
+ GEN_test(_name##_ymm_src_dst, \
+ "vfmsubaddps %%ymm7,%%ymm8,%%ymm9,%%ymm9", 0); \
+ GEN_test(_name##_ymm_mem1, \
+ "vfmsubaddps (%%r14),%%ymm8,%%ymm6,%%ymm9", 0); \
+ GEN_test(_name##_ymm_mem2, \
+ "vfmsubaddps %%ymm8,(%%r14),%%ymm6,%%ymm9", 0);
+GEN_test_VFMSUBADDPS_ymm(VFMSUBADDPS)
+
+#define GEN_test_VFMSUBPD_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfmsubpd %%xmm7,%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfmsubpd %%xmm7,%%xmm8,%%xmm9,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfmsubpd (%%r14),%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfmsubpd %%xmm8,(%%r14),%%xmm6,%%xmm9", 1);
+GEN_test_VFMSUBPD_xmm(VFMSUBPD)
+
+#define GEN_test_VFMSUBPD_ymm(_name) \
+ GEN_test(_name##_ymm, \
+ "vfmsubpd %%ymm7,%%ymm8,%%ymm6,%%ymm9", 1); \
+ GEN_test(_name##_ymm_src_dst, \
+ "vfmsubpd %%ymm7,%%ymm8,%%ymm9,%%ymm9", 1); \
+ GEN_test(_name##_ymm_mem1, \
+ "vfmsubpd (%%r14),%%ymm8,%%ymm6,%%ymm9", 1); \
+ GEN_test(_name##_ymm_mem2, \
+ "vfmsubpd %%ymm8,(%%r14),%%ymm6,%%ymm9", 1);
+GEN_test_VFMSUBPD_ymm(VFMSUBPD)
+
+#define GEN_test_VFMSUBPS_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfmsubps %%xmm7,%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfmsubps %%xmm7,%%xmm8,%%xmm9,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfmsubps (%%r14),%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfmsubps %%xmm8,(%%r14),%%xmm6,%%xmm9", 0);
+GEN_test_VFMSUBPS_xmm(VFMSUBPS)
+
+#define GEN_test_VFMSUBPS_ymm(_name) \
+ GEN_test(_name##_ymm, \
+ "vfmsubps %%ymm7,%%ymm8,%%ymm6,%%ymm9", 0); \
+ GEN_test(_name##_ymm_src_dst, \
+ "vfmsubps %%ymm7,%%ymm8,%%ymm9,%%ymm9", 0); \
+ GEN_test(_name##_ymm_mem1, \
+ "vfmsubps (%%r14),%%ymm8,%%ymm6,%%ymm9", 0); \
+ GEN_test(_name##_ymm_mem2, \
+ "vfmsubps %%ymm8,(%%r14),%%ymm6,%%ymm9", 0);
+GEN_test_VFMSUBPS_ymm(VFMSUBPS)
+
+#define GEN_test_VFMSUBSD_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfmsubsd %%xmm7,%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfmsubsd %%xmm7,%%xmm8,%%xmm9,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfmsubsd (%%r14),%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfmsubsd %%xmm8,(%%r14),%%xmm6,%%xmm9", 1);
+GEN_test_VFMSUBSD_xmm(VFMSUBSD)
+
+#define GEN_test_VFMSUBSS_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfmsubss %%xmm7,%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfmsubss %%xmm7,%%xmm8,%%xmm9,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfmsubss (%%r14),%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfmsubss %%xmm8,(%%r14),%%xmm6,%%xmm9", 0);
+GEN_test_VFMSUBSS_xmm(VFMSUBSS)
+
+#define GEN_test_VFNMADDPD_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfnmaddpd %%xmm7,%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfnmaddpd %%xmm7,%%xmm8,%%xmm9,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfnmaddpd (%%r14),%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfnmaddpd %%xmm8,(%%r14),%%xmm6,%%xmm9", 1);
+GEN_test_VFNMADDPD_xmm(VFNMADDPD)
+
+#define GEN_test_VFNMADDPD_ymm(_name) \
+ GEN_test(_name##_ymm, \
+ "vfnmaddpd %%ymm7,%%ymm8,%%ymm6,%%ymm9", 1); \
+ GEN_test(_name##_ymm_src_dst, \
+ "vfnmaddpd %%ymm7,%%ymm8,%%ymm9,%%ymm9", 1); \
+ GEN_test(_name##_ymm_mem1, \
+ "vfnmaddpd (%%r14),%%ymm8,%%ymm6,%%ymm9", 1); \
+ GEN_test(_name##_ymm_mem2, \
+ "vfnmaddpd %%ymm8,(%%r14),%%ymm6,%%ymm9", 1);
+GEN_test_VFNMADDPD_ymm(VFNMADDPD)
+
+#define GEN_test_VFNMADDPS_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfnmaddps %%xmm7,%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfnmaddps %%xmm7,%%xmm8,%%xmm9,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfnmaddps (%%r14),%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfnmaddps %%xmm8,(%%r14),%%xmm6,%%xmm9", 0);
+GEN_test_VFNMADDPS_xmm(VFNMADDPS)
+
+#define GEN_test_VFNMADDPS_ymm(_name) \
+ GEN_test(_name##_ymm, \
+ "vfnmaddps %%ymm7,%%ymm8,%%ymm6,%%ymm9", 0); \
+ GEN_test(_name##_ymm_src_dst, \
+ "vfnmaddps %%ymm7,%%ymm8,%%ymm9,%%ymm9", 0); \
+ GEN_test(_name##_ymm_mem1, \
+ "vfnmaddps (%%r14),%%ymm8,%%ymm6,%%ymm9", 0); \
+ GEN_test(_name##_ymm_mem2, \
+ "vfnmaddps %%ymm8,(%%r14),%%ymm6,%%ymm9", 0);
+GEN_test_VFNMADDPS_ymm(VFNMADDPS)
+
+#define GEN_test_VFNMADDSD_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfnmaddsd %%xmm7,%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfnmaddsd %%xmm7,%%xmm8,%%xmm9,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfnmaddsd (%%r14),%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfnmaddsd %%xmm8,(%%r14),%%xmm6,%%xmm9", 1);
+GEN_test_VFNMADDSD_xmm(VFNMADDSD)
+
+#define GEN_test_VFNMADDSS_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfnmaddss %%xmm7,%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfnmaddss %%xmm7,%%xmm8,%%xmm9,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfnmaddss (%%r14),%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfnmaddss %%xmm8,(%%r14),%%xmm6,%%xmm9", 0);
+GEN_test_VFNMADDSS_xmm(VFNMADDSS)
+
+#define GEN_test_VFNMSUBPD_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfnmsubpd %%xmm7,%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfnmsubpd %%xmm7,%%xmm8,%%xmm9,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfnmsubpd (%%r14),%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfnmsubpd %%xmm8,(%%r14),%%xmm6,%%xmm9", 1);
+GEN_test_VFNMSUBPD_xmm(VFNMSUBPD)
+
+#define GEN_test_VFNMSUBPD_ymm(_name) \
+ GEN_test(_name##_ymm, \
+ "vfnmsubpd %%ymm7,%%ymm8,%%ymm6,%%ymm9", 1); \
+ GEN_test(_name##_ymm_src_dst, \
+ "vfnmsubpd %%ymm7,%%ymm8,%%ymm9,%%ymm9", 1); \
+ GEN_test(_name##_ymm_mem1, \
+ "vfnmsubpd (%%r14),%%ymm8,%%ymm6,%%ymm9", 1); \
+ GEN_test(_name##_ymm_mem2, \
+ "vfnmsubpd %%ymm8,(%%r14),%%ymm6,%%ymm9", 1);
+GEN_test_VFNMSUBPD_ymm(VFNMSUBPD)
+
+#define GEN_test_VFNMSUBPS_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfnmsubps %%xmm7,%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfnmsubps %%xmm7,%%xmm8,%%xmm9,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfnmsubps (%%r14),%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfnmsubps %%xmm8,(%%r14),%%xmm6,%%xmm9", 0);
+GEN_test_VFNMSUBPS_xmm(VFNMSUBPS)
+
+#define GEN_test_VFNMSUBPS_ymm(_name) \
+ GEN_test(_name##_ymm, \
+ "vfnmsubps %%ymm7,%%ymm8,%%ymm6,%%ymm9", 0); \
+ GEN_test(_name##_ymm_src_dst, \
+ "vfnmsubps %%ymm7,%%ymm8,%%ymm9,%%ymm9", 0); \
+ GEN_test(_name##_ymm_mem1, \
+ "vfnmsubps (%%r14),%%ymm8,%%ymm6,%%ymm9", 0); \
+ GEN_test(_name##_ymm_mem2, \
+ "vfnmsubps %%ymm8,(%%r14),%%ymm6,%%ymm9", 0);
+GEN_test_VFNMSUBPS_ymm(VFNMSUBPS)
+
+#define GEN_test_VFNMSUBSD_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfnmsubsd %%xmm7,%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfnmsubsd %%xmm7,%%xmm8,%%xmm9,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfnmsubsd (%%r14),%%xmm8,%%xmm6,%%xmm9", 1); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfnmsubsd %%xmm8,(%%r14),%%xmm6,%%xmm9", 1);
+GEN_test_VFNMSUBSD_xmm(VFNMSUBSD)
+
+#define GEN_test_VFNMSUBSS_xmm(_name) \
+ GEN_test(_name##_xmm, \
+ "vfnmsubss %%xmm7,%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_src_dst, \
+ "vfnmsubss %%xmm7,%%xmm8,%%xmm9,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem1, \
+ "vfnmsubss (%%r14),%%xmm8,%%xmm6,%%xmm9", 0); \
+ GEN_test(_name##_xmm_mem2, \
+ "vfnmsubss %%xmm8,(%%r14),%%xmm6,%%xmm9", 0);
+GEN_test_VFNMSUBSS_xmm(VFNMSUBSS)
+
+#define DO_test_block(_name, _sub, _bname, _block) \
+ test_##_name##_##_sub(_bname,_block);
+
+#define DO_test(_name, _sub, _isD) { \
+ Block* b = memalign32(sizeof(Block)); \
+ oneBlock(b); \
+ DO_test_block(_name, _sub, "ones", b); \
+ if (_isD) { \
+ specialDBlock(b); \
+ DO_test_block(_name, _sub, "specialD", b); \
+ } else { \
+ specialFBlock(b); \
+ DO_test_block(_name, _sub, "specialF", b); \
+ } \
+ randBlock(b); \
+ DO_test_block(_name, _sub, "rand", b); \
+ free(b); \
+}
+
+#define DO_tests_xmm(_name,_isD) \
+ DO_test(_name, xmm, _isD); \
+ DO_test(_name, xmm_src_dst, _isD); \
+ DO_test(_name, xmm_mem1, _isD); \
+ DO_test(_name, xmm_mem2, _isD);
+
+#define DO_tests_ymm(_name,_isD) \
+ DO_test(_name, ymm, _isD); \
+ DO_test(_name, ymm_src_dst, _isD); \
+ DO_test(_name, ymm_mem1, _isD); \
+ DO_test(_name, ymm_mem2, _isD);
+
+int main ( void )
+{
+ init_special_values();
+
+ // 128
+ DO_tests_xmm(VFMADDPD, 1);
+ DO_tests_xmm(VFMADDPS, 0);
+ DO_tests_xmm(VFMADDSD, 1);
+ DO_tests_xmm(VFMADDSS, 0);
+ DO_tests_xmm(VFMADDSUBPD, 1);
+ DO_tests_xmm(VFMADDSUBPS, 0);
+ DO_tests_xmm(VFMSUBADDPD, 1);
+ DO_tests_xmm(VFMSUBADDPS, 0);
+ DO_tests_xmm(VFMSUBPD, 1);
+ DO_tests_xmm(VFMSUBPS, 0);
+ DO_tests_xmm(VFMSUBSD, 1);
+ DO_tests_xmm(VFMSUBSS, 0);
+ DO_tests_xmm(VFNMADDPD, 1);
+ DO_tests_xmm(VFNMADDPS, 0);
+ DO_tests_xmm(VFNMADDSD, 1);
+ DO_tests_xmm(VFNMADDSS, 0);
+ DO_tests_xmm(VFNMSUBPD, 1);
+ DO_tests_xmm(VFNMSUBPS, 0);
+ DO_tests_xmm(VFNMSUBSD, 1);
+ DO_tests_xmm(VFNMSUBSS, 0);
+
+ // 256
+ /*
+ DO_tests_ymm(VFMADDPD, 1);
+ DO_tests_ymm(VFMADDPS, 0);
+ DO_tests_ymm(VFMADDSUBPD, 1);
+ DO_tests_ymm(VFMADDSUBPS, 0);
+ DO_tests_ymm(VFMSUBADDPD, 1);
+ DO_tests_ymm(VFMSUBADDPS, 0);
+ DO_tests_ymm(VFMSUBPD, 1);
+ DO_tests_ymm(VFMSUBPS, 0);
+ DO_tests_ymm(VFNMADDPD, 1);
+ DO_tests_ymm(VFNMADDPS, 0);
+ DO_tests_ymm(VFNMSUBPD, 1);
+ DO_tests_ymm(VFNMSUBPS, 0);
+ */
+
+ return 0;
+}
diff --git a/none/tests/amd64/fma4.stderr.exp b/none/tests/amd64/fma4.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/amd64/fma4.stderr.exp
diff --git a/none/tests/amd64/fma4.stdout.exp b/none/tests/amd64/fma4.stdout.exp
new file mode 100644
index 0000000..a0991ab
--- /dev/null
+++ b/none/tests/amd64/fma4.stdout.exp
@@ -0,0 +1,3360 @@
+VFMADDPD_xmm ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMADDPD_xmm specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ INF ].[ INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMADDPD_xmm rand
+ before
+r1: 7d6528c5fa956a0d.69c3e9a6af27d13b.5175e39d19c9ca1e.98f24a4984175700
+r2: b6d2fb5aa7bc5127.fe9915e556a044b2.60b160857d45c484.47b8d8c0eeef1e50
+r3: 065d77195d623e6b.842adc6450659e17.19a348215c3a67fd.399182c2dbcc2d38
+r4: cb509970b8136c85.d740b80eb7839b97.d89998df5035ed36.4a4bc43968bc40e5
+ m: 5ff85bc9535c191f.d3a727d1a705f65d.f9dd4a29f8c093db.56b01a12b0ca1583
+ after
+r1: 7d6528c5fa956a0d.69c3e9a6af27d13b.5175e39d19c9ca1e.98f24a4984175700
+r2: b6d2fb5aa7bc5127.fe9915e556a044b2.60b160857d45c484.47b8d8c0eeef1e50
+r3: 065d77195d623e6b.842adc6450659e17.19a348215c3a67fd.399182c2dbcc2d38
+r4: [ ZERO ].[ ZERO ].5175e39d19c9ca1e.415b315cb6ea9ab9
+ m: 5ff85bc9535c191f.d3a727d1a705f65d.f9dd4a29f8c093db.56b01a12b0ca1583
+
+VFMADDPD_xmm_src_dst ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMADDPD_xmm_src_dst specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ INF ].[ INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMADDPD_xmm_src_dst rand
+ before
+r1: 20a1bb92cbc97fe8.542da4983df76c96.d8bc5c6dee699597.398e0039cf03663d
+r2: 6897b536bbe4da8a.369dab4f9465b86e.d182c916cebc2e17.cfaff39be272ef40
+r3: 95264321bf3b68b2.55c2b9e2c95c9810.407b8d9035449b06.f4e06e2205236eb7
+r4: 019963bf7459630b.8d69483df7e8c6a9.81f2a547be8d1811.84ededbc53239dcf
+ m: 0a3e0f7c75cb0842.b95ed64d3b13ff64.f0350ca70523e0e4.5ba1ec54e87d39b3
+ after
+r1: 20a1bb92cbc97fe8.542da4983df76c96.d8bc5c6dee699597.398e0039cf03663d
+r2: 6897b536bbe4da8a.369dab4f9465b86e.d182c916cebc2e17.cfaff39be272ef40
+r3: 95264321bf3b68b2.55c2b9e2c95c9810.407b8d9035449b06.f4e06e2205236eb7
+r4: [ ZERO ].[ ZERO ].d8bc5c6dee699597.398e0039cf03663d
+ m: 0a3e0f7c75cb0842.b95ed64d3b13ff64.f0350ca70523e0e4.5ba1ec54e87d39b3
+
+VFMADDPD_xmm_mem1 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMADDPD_xmm_mem1 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMADDPD_xmm_mem1 rand
+ before
+r1: 0a5f45c55f1c9202.b76ddefcb0ebfe6e.e98ebd1ca893312a.54cae7d5e13dfe91
+r2: 5f490104ced83ff8.6262dd37727c80f3.c84ab71340684590.4d325b2d5a70a792
+r3: 63483da65c8c49d0.96084deb9ed0411e.e9b5f3f66b2e58c1.21a6c3476d21f1e5
+r4: 73a8f718a8c3ec35.2e2dac0350f6fd1c.a81b6e33c572a86a.acf29b0f395c98b4
+ m: ecb42ac54b0966d4.089b756aa3f77018.61c82534e9bf6f37.c9e25f72d82e582b
+ after
+r1: 0a5f45c55f1c9202.b76ddefcb0ebfe6e.e98ebd1ca893312a.54cae7d5e13dfe91
+r2: 5f490104ced83ff8.6262dd37727c80f3.c84ab71340684590.4d325b2d5a70a792
+r3: 63483da65c8c49d0.96084deb9ed0411e.e9b5f3f66b2e58c1.21a6c3476d21f1e5
+r4: [ ZERO ].[ ZERO ].721253d095545e3c.c9e25f72d82e582b
+ m: ecb42ac54b0966d4.089b756aa3f77018.61c82534e9bf6f37.c9e25f72d82e582b
+
+VFMADDPD_xmm_mem2 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMADDPD_xmm_mem2 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMADDPD_xmm_mem2 rand
+ before
+r1: 28bad218e4ebf159.ff1f240eb3e1553f.6f07136773a2ead3.56428c5a66a2ec77
+r2: 8404eb7f0cf4ca6f.ee8536da9dbf68bc.3026343700a654eb.2ddd9db4ffc411c4
+r3: 5cdf726562b02dc2.b39925ba7d9d67bc.ff6f850f2c57ea2a.2c810e6dc1a1833d
+r4: 0c9761367fac55ff.28276f9a6e880c6b.372f015d9242e83d.2ef85b6fc544fd0f
+ m: f078b65e01737fd2.2bfa8f668c8b14f4.36b2a38dcef18acf.0e0f01a829ba3c66
+ after
+r1: 28bad218e4ebf159.ff1f240eb3e1553f.6f07136773a2ead3.56428c5a66a2ec77
+r2: 8404eb7f0cf4ca6f.ee8536da9dbf68bc.3026343700a654eb.2ddd9db4ffc411c4
+r3: 5cdf726562b02dc2.b39925ba7d9d67bc.ff6f850f2c57ea2a.2c810e6dc1a1833d
+r4: [ ZERO ].[ ZERO ].f6325bf1fc5cab6d.2ddd9db4ffc411c4
+ m: f078b65e01737fd2.2bfa8f668c8b14f4.36b2a38dcef18acf.0e0f01a829ba3c66
+
+VFMADDPS_xmm ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMADDPS_xmm specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].bf800000.3f800000.[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMADDPS_xmm rand
+ before
+r1: 65ce6d49.8492e7e7.96df010b.f4b23b84.57436a09.7df30b8d.aa927a03.090dfc6d
+r2: c5e48064.a393c8e9.47a34273.c10a3c47.f5304f3e.3ad1a923.dc4c446c.[-SUBNR]
+r3: 6d08ed19.fa045f84.1810cd8c.109ed568.6ec34f98.a2199d3c.810bdacf.ab80ee3d
+r4: b984aed6.2671e865.e6f21d40.fc7bc013.1c4a6784.50562685.769ab818.a5b7985e
+ m: 05a5c205.c3659f38.8e17b17d.a2acb976.5d0f926c.e1157eaa.95c45b33.8afcb3df
+ after
+r1: 65ce6d49.8492e7e7.96df010b.f4b23b84.57436a09.7df30b8d.aa927a03.090dfc6d
+r2: c5e48064.a393c8e9.47a34273.c10a3c47.f5304f3e.3ad1a923.dc4c446c.[-SUBNR]
+r3: 6d08ed19.fa045f84.1810cd8c.109ed568.6ec34f98.a2199d3c.810bdacf.ab80ee3d
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ -INF ].7df30b8d.aa927a03.090dfc6d
+ m: 05a5c205.c3659f38.8e17b17d.a2acb976.5d0f926c.e1157eaa.95c45b33.8afcb3df
+
+VFMADDPS_xmm_src_dst ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMADDPS_xmm_src_dst specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMADDPS_xmm_src_dst rand
+ before
+r1: acb72214.6c6cbfa9.ea4a022e.1d3d7dbb.8b5fccbe.f0e1e256.bc563e0c.775bfaed
+r2: 0c05cb6e.bd128663.d7568e3e.8a3ac80e.048612e5.1a468e36.c51cdd8f.87e12ab4
+r3: 80ddba7e.53e42d12.3208cf9b.04b0569c.22cf5e4c.fad1bdf5.8de2b4a9.d799ff5f
+r4: 6489eab2.c96df363.d52c4330.a7aae391.4288ae61.2c0dad40.f0733f44.8390351b
+ m: 14575775.bc3a1202.9d8e66ea.90352a18.c1fbfd8f.4d8698c2.cb9dfb4e.a5d18713
+ after
+r1: acb72214.6c6cbfa9.ea4a022e.1d3d7dbb.8b5fccbe.f0e1e256.bc563e0c.775bfaed
+r2: 0c05cb6e.bd128663.d7568e3e.8a3ac80e.048612e5.1a468e36.c51cdd8f.87e12ab4
+r3: 80ddba7e.53e42d12.3208cf9b.04b0569c.22cf5e4c.fad1bdf5.8de2b4a9.d799ff5f
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].8b5eae69.f0e1e256.76150d13.775bfaed
+ m: 14575775.bc3a1202.9d8e66ea.90352a18.c1fbfd8f.4d8698c2.cb9dfb4e.a5d18713
+
+VFMADDPS_xmm_mem1 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMADDPS_xmm_mem1 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ -INF ].[ INF ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMADDPS_xmm_mem1 rand
+ before
+r1: ec91fe34.c7d6c79a.66fab2b3.db5ce85e.f9754842.f9c9ba28.f82a63b1.5c68b274
+r2: 4784d959.87cd4ed8.0c3ca578.a32bd88e.474289e7.cb61501e.54e7f35b.c162726a
+r3: 837be651.97abe268.6b1fba26.04afb8d5.08aebee8.5fda964f.bba02737.f3c98220
+r4: fbc42088.94fdc0f5.5f706da7.1bf2425f.9605e2b2.52c1c868.09217c31.0baca0c3
+ m: 0aaa836b.194e242c.c5fc3ae9.04033357.4e92f1b2.40a12214.1a366d35.2714867e
+ after
+r1: ec91fe34.c7d6c79a.66fab2b3.db5ce85e.f9754842.f9c9ba28.f82a63b1.5c68b274
+r2: 4784d959.87cd4ed8.0c3ca578.a32bd88e.474289e7.cb61501e.54e7f35b.c162726a
+r3: 837be651.97abe268.6b1fba26.04afb8d5.08aebee8.5fda964f.bba02737.f3c98220
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].4e92f1b2.ebc06284.d1111ba1.75b23ef0
+ m: 0aaa836b.194e242c.c5fc3ae9.04033357.4e92f1b2.40a12214.1a366d35.2714867e
+
+VFMADDPS_xmm_mem2 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMADDPS_xmm_mem2 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMADDPS_xmm_mem2 rand
+ before
+r1: 0e780c65.c22b4ab8.778d9ed6.d9eb46ea.8ca3e752.c306df00.caab752f.630ff07e
+r2: 627bb6e1.2d1f6d46.51ef145c.b9b83843.ac82c100.7a7d3cd8.f54b130c.daa89cef
+r3: 61ff7d4d.f3b6ca81.31f01866.bd76c58f.0a7c7a27.fe917447.77e3c0b6.a9ec44fc
+r4: 69505d14.b27d9d16.f25b26e0.042fa9fa.02dd0e32.eecfc5fa.2c3ffa1a.ebe6a4d2
+ m: d4ba52a2.06ff21b1.70fbbab6.a7f19faf.f0f1798f.e3c1699c.f02b3b25.bca27a9c
+ after
+r1: 0e780c65.c22b4ab8.778d9ed6.d9eb46ea.8ca3e752.c306df00.caab752f.630ff07e
+r2: 627bb6e1.2d1f6d46.51ef145c.b9b83843.ac82c100.7a7d3cd8.f54b130c.daa89cef
+r3: 61ff7d4d.f3b6ca81.31f01866.bd76c58f.0a7c7a27.fe917447.77e3c0b6.a9ec44fc
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].bbee26e1.[ INF ].[ -INF ].daa89cef
+ m: d4ba52a2.06ff21b1.70fbbab6.a7f19faf.f0f1798f.e3c1699c.f02b3b25.bca27a9c
+
+VFMADDSD_xmm ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMADDSD_xmm specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMADDSD_xmm rand
+ before
+r1: 0088596389c893fd.879d51d4c5c764db.3004b7a97cf69dda.9f7301c1392d8087
+r2: 47086cc3da642fa7.130d662777beb4a9.1e61c5ec52f79c60.15e3c8dc7e9273bf
+r3: 0784892e9360315b.f0177599dbe14b46.16559ec50352a3d9.2d460a61a5dd0f6f
+r4: 9a49ac115048d4c4.f987fa170d3ce4dd.742c3e9e2b92eef2.c569453ccd1b0fc4
+ m: 5da3cfd6aea6558e.0c28728e28dc3c9c.9432a2e46543b956.b819f459105730e9
+ after
+r1: 0088596389c893fd.879d51d4c5c764db.3004b7a97cf69dda.9f7301c1392d8087
+r2: 47086cc3da642fa7.130d662777beb4a9.1e61c5ec52f79c60.15e3c8dc7e9273bf
+r3: 0784892e9360315b.f0177599dbe14b46.16559ec50352a3d9.2d460a61a5dd0f6f
+r4: [ ZERO ].[ ZERO ].[ ZERO ].9f7301c1392d8087
+ m: 5da3cfd6aea6558e.0c28728e28dc3c9c.9432a2e46543b956.b819f459105730e9
+
+VFMADDSD_xmm_src_dst ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMADDSD_xmm_src_dst specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMADDSD_xmm_src_dst rand
+ before
+r1: adddf0eb4808f067.04c857e949cc0fac.d2b3c4044ef23fb2.e22093a48a9d2e0b
+r2: e4450ababbfae0f9.bc3127138b19183c.89fba268812abdb2.1e4a9e0958fac555
+r3: 5f2619b1a20662f0.12305efa0acd1475.1755377e9a786f01.4a6592749579b0f4
+r4: 7acb193b9abab2f9.e1917689e3f6bf86.d70f7fb13667914c.413cead25e27ac14
+ m: 918107c43ea20cc0.0420edac31a0d599.2573776df1835e3e.de9a220dce0e75e0
+ after
+r1: adddf0eb4808f067.04c857e949cc0fac.d2b3c4044ef23fb2.e22093a48a9d2e0b
+r2: e4450ababbfae0f9.bc3127138b19183c.89fba268812abdb2.1e4a9e0958fac555
+r3: 5f2619b1a20662f0.12305efa0acd1475.1755377e9a786f01.4a6592749579b0f4
+r4: [ ZERO ].[ ZERO ].[ ZERO ].e22093a48a9d2e0b
+ m: 918107c43ea20cc0.0420edac31a0d599.2573776df1835e3e.de9a220dce0e75e0
+
+VFMADDSD_xmm_mem1 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMADDSD_xmm_mem1 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMADDSD_xmm_mem1 rand
+ before
+r1: 0194ddb82b49abf0.59a93d4f11d611db.5cce191e65591384.ff4cb613013cc685
+r2: 24509983fc3bcc36.baf7e45e9fa43077.da6c63303173ecc9.7e1e22cf15bd5c2f
+r3: 570037914d04ab3d.05d75ec6f616ee9a.fa99500fef6024ba.39dce32c239cf309
+r4: f6f2b14fbb3184b2.141625713239066f.17a0dc273ba9f803.0a52741849e54740
+ m: 5d700527e24d9241.c57eb74d70183523.8fcf04e5b2dca44f.cf4c517ea3a413ff
+ after
+r1: 0194ddb82b49abf0.59a93d4f11d611db.5cce191e65591384.ff4cb613013cc685
+r2: 24509983fc3bcc36.baf7e45e9fa43077.da6c63303173ecc9.7e1e22cf15bd5c2f
+r3: 570037914d04ab3d.05d75ec6f616ee9a.fa99500fef6024ba.39dce32c239cf309
+r4: [ ZERO ].[ ZERO ].[ ZERO ].780b3465b16e86e6
+ m: 5d700527e24d9241.c57eb74d70183523.8fcf04e5b2dca44f.cf4c517ea3a413ff
+
+VFMADDSD_xmm_mem2 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMADDSD_xmm_mem2 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMADDSD_xmm_mem2 rand
+ before
+r1: e8c72e865de41295.f2db8f44cbbf37e2.bc70c3b3ef84644b.6295f64a4ce61473
+r2: f34428d9c8833f5b.78fb29445f3bc8d7.fcd015ff8f2e73a3.a0fae06860b606c7
+r3: da30ef8bc0b5573e.34a901384a97a32f.a93bf6332d650e02.66478ac4fc21a428
+r4: f9da7f07e00794eb.00b0940ba5e08516.20fd62bd65b57115.8e48704b3c31abc2
+ m: ac8dd5bbc503330e.b9dd5dab8e212ab7.be625608d5abd787.f5c90ee73af5d7c0
+ after
+r1: e8c72e865de41295.f2db8f44cbbf37e2.bc70c3b3ef84644b.6295f64a4ce61473
+r2: f34428d9c8833f5b.78fb29445f3bc8d7.fcd015ff8f2e73a3.a0fae06860b606c7
+r3: da30ef8bc0b5573e.34a901384a97a32f.a93bf6332d650e02.66478ac4fc21a428
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ -INF ]
+ m: ac8dd5bbc503330e.b9dd5dab8e212ab7.be625608d5abd787.f5c90ee73af5d7c0
+
+VFMADDSS_xmm ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMADDSS_xmm specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMADDSS_xmm rand
+ before
+r1: 4e94ec12.0b386f52.3bfcd803.21664d3e.ddb5cd80.16d27d05.7796e086.1576e44f
+r2: 3d3cc078.4c2f8563.63d98100.79bbabd9.db43c391.c6b69f3a.f17a6312.e7c28d9a
+r3: d4d14e59.2776b1ef.0b40d58c.b22d00b1.125934a7.81e479d3.3d431279.cce48fce
+r4: 6f9f9022.35982fa0.10fd4e94.e9c808f5.df411d2e.e2e7467c.38bb69a6.e1e9a617
+ m: 69f2843d.15223a22.4edb6a05.3a967ecf.9e477892.854b43e0.beafe485.41dc8da0
+ after
+r1: 4e94ec12.0b386f52.3bfcd803.21664d3e.ddb5cd80.16d27d05.7796e086.1576e44f
+r2: 3d3cc078.4c2f8563.63d98100.79bbabd9.db43c391.c6b69f3a.f17a6312.e7c28d9a
+r3: d4d14e59.2776b1ef.0b40d58c.b22d00b1.125934a7.81e479d3.3d431279.cce48fce
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].752db367
+ m: 69f2843d.15223a22.4edb6a05.3a967ecf.9e477892.854b43e0.beafe485.41dc8da0
+
+VFMADDSS_xmm_src_dst ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMADDSS_xmm_src_dst specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMADDSS_xmm_src_dst rand
+ before
+r1: 20162517.609f0f22.a1a7a4c9.c0a51f6b.acb9433f.079dacac.abeb0002.08c90296
+r2: ef56701d.b49bea4c.e52e79ce.9700a7f7.63e279a2.0368bc8b.db3b3709.54bcbf24
+r3: 31005fb9.ada2074b.f63a63fe.dcb4d29c.200d1726.1638b12a.2a6a0786.3ec28077
+r4: 445ef059.e641a1cc.b097e047.aacc5b89.3f871736.dc9ac535.7446eb65.e4e703bb
+ m: 83bd1e68.fb03f57b.ef136b94.1e54ffe8.1c9c7740.ef193457.95996092.6235021b
+ after
+r1: 20162517.609f0f22.a1a7a4c9.c0a51f6b.acb9433f.079dacac.abeb0002.08c90296
+r2: ef56701d.b49bea4c.e52e79ce.9700a7f7.63e279a2.0368bc8b.db3b3709.54bcbf24
+r3: 31005fb9.ada2074b.f63a63fe.dcb4d29c.200d1726.1638b12a.2a6a0786.3ec28077
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].fa2a533a
+ m: 83bd1e68.fb03f57b.ef136b94.1e54ffe8.1c9c7740.ef193457.95996092.6235021b
+
+VFMADDSS_xmm_mem1 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMADDSS_xmm_mem1 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMADDSS_xmm_mem1 rand
+ before
+r1: 4969e552.89753f03.8f7980d1.535979e5.139832af.ee423c3d.6930e0fa.d3ba39c4
+r2: f4ad4183.2c22ba11.6c949cea.66e687ae.80c745ef.729f1792.ccd7e987.538166e1
+r3: ded72f67.[ NAN ].623139cb.7207e36c.bf75aa6c.1abe0103.9a5af627.[ NAN ]
+r4: 6431aa6a.1e5e366d.4c1cd561.94c94a4e.2ced5f92.7f2b383c.af8484c5.f3078d2a
+ m: e309aef8.a605af13.0821eb96.e737777e.237d5fcd.3f71f6e8.e6230d4d.4add00ad
+ after
+r1: 4969e552.89753f03.8f7980d1.535979e5.139832af.ee423c3d.6930e0fa.d3ba39c4
+r2: f4ad4183.2c22ba11.6c949cea.66e687ae.80c745ef.729f1792.ccd7e987.538166e1
+r3: ded72f67.[ NAN ].623139cb.7207e36c.bf75aa6c.1abe0103.9a5af627.[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: e309aef8.a605af13.0821eb96.e737777e.237d5fcd.3f71f6e8.e6230d4d.4add00ad
+
+VFMADDSS_xmm_mem2 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMADDSS_xmm_mem2 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMADDSS_xmm_mem2 rand
+ before
+r1: b5a9377e.b31749ef.710cf757.885d2728.[ SUBNR].f61c78b4.1d010fab.20265755
+r2: 385e4166.df2141ad.63a87691.92481679.1f103033.3fb8fa4b.2feb05cb.92ed4f4d
+r3: c673c91e.c9aed3f8.b9c3e32f.2103009d.dbacfa35.b7d2b75a.f8ad6b99.bb3fa4c2
+r4: bc36ca10.0a4a3a7d.5127ba1c.529aa0bf.928efefd.f9f5ec8d.5313bd01.b82612e0
+ m: 76f140aa.4182b4e7.06a17746.411ab40c.9f043af6.a1aed58f.1ee978ef.a4b054d2
+ after
+r1: b5a9377e.b31749ef.710cf757.885d2728.[ SUBNR].f61c78b4.1d010fab.20265755
+r2: 385e4166.df2141ad.63a87691.92481679.1f103033.3fb8fa4b.2feb05cb.92ed4f4d
+r3: c673c91e.c9aed3f8.b9c3e32f.2103009d.dbacfa35.b7d2b75a.f8ad6b99.bb3fa4c2
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].208400c5
+ m: 76f140aa.4182b4e7.06a17746.411ab40c.9f043af6.a1aed58f.1ee978ef.a4b054d2
+
+VFMADDSUBPD_xmm ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].0101010101010101.8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMADDSUBPD_xmm specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ INF ].[ INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMADDSUBPD_xmm rand
+ before
+r1: 51f2275707e17ae4.b3fd9698098ef5b0.5e58aa8b4c88ae0d.34fa174f9ce927c4
+r2: a7837c83faf3cb1d.360794fec60222d6.2ad7482a960fb2b2.7014160ebbdb47e4
+r3: d5f13a9ab645e140.698bec649583f5aa.61cd123e19cf1e2b.b001f1161e946f5c
+r4: 37885d08d662faf9.2a541ab7911c2b5a.5e86033374552e23.ce8e2455e0205c58
+ m: 2993e139f7d64ff4.532f9ae1d7da8010.7c4e1775412d1d47.a8872cb61d8aca05
+ after
+r1: 51f2275707e17ae4.b3fd9698098ef5b0.5e58aa8b4c88ae0d.34fa174f9ce927c4
+r2: a7837c83faf3cb1d.360794fec60222d6.2ad7482a960fb2b2.7014160ebbdb47e4
+r3: d5f13a9ab645e140.698bec649583f5aa.61cd123e19cf1e2b.b001f1161e946f5c
+r4: [ ZERO ].[ ZERO ].5e58aa8b4c88ae0d.e0268617aa3e8910
+ m: 2993e139f7d64ff4.532f9ae1d7da8010.7c4e1775412d1d47.a8872cb61d8aca05
+
+VFMADDSUBPD_xmm_src_dst ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].0101010101010101.8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMADDSUBPD_xmm_src_dst specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ INF ].[ INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMADDSUBPD_xmm_src_dst rand
+ before
+r1: 0760c299b42e1fdc.c2e9e9cf82c7aff8.19714a711ce12843.18b88425f2de758f
+r2: 2d39fd95a9f5a45d.514c816eaff2763f.8f3a9991a2ff8bc2.fceca88e7b281821
+r3: f76b8d9773b81b24.de24e0a879648e11.3cf6fe426e128171.2ef114ddd37570e8
+r4: c1426e0dae01c0dd.433f816bfd2bb699.7af177f11da748fc.8b9145fe16d0390f
+ m: e70a9c61f55fce33.5d68e1a25652a804.a77700084a491a0e.f099b6dd61462ec3
+ after
+r1: 0760c299b42e1fdc.c2e9e9cf82c7aff8.19714a711ce12843.18b88425f2de758f
+r2: 2d39fd95a9f5a45d.514c816eaff2763f.8f3a9991a2ff8bc2.fceca88e7b281821
+r3: f76b8d9773b81b24.de24e0a879648e11.3cf6fe426e128171.2ef114ddd37570e8
+r4: [ ZERO ].[ ZERO ].ca3d0a91c2c9ec74.488ef07566005301
+ m: e70a9c61f55fce33.5d68e1a25652a804.a77700084a491a0e.f099b6dd61462ec3
+
+VFMADDSUBPD_xmm_mem1 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].0101010101010101.8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMADDSUBPD_xmm_mem1 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMADDSUBPD_xmm_mem1 rand
+ before
+r1: c50f1401e45b82d3.086a7a39a1e6217d.1dd493f591843454.37d5e366d0e20c30
+r2: b79cd05818831869.2112ca1cf9f1dd31.3a542e238fe5d179.3d1148867eb08f81
+r3: 19ffced22c62cba0.822c4c377b82984c.5842cbfee0f72e2a.de18612787bc73e3
+r4: 478209dbbd84d925.08847c7642a20df9.d4ec68f21f468712.f7b8ab3708137382
+ m: 9c727edf66767ca3.8fe6d7c56a5ff965.0b9c016be95f18de.62bba1a11cc04c89
+ after
+r1: c50f1401e45b82d3.086a7a39a1e6217d.1dd493f591843454.37d5e366d0e20c30
+r2: b79cd05818831869.2112ca1cf9f1dd31.3a542e238fe5d179.3d1148867eb08f81
+r3: 19ffced22c62cba0.822c4c377b82984c.5842cbfee0f72e2a.de18612787bc73e3
+r4: [ ZERO ].[ ZERO ].52a7b532dd468037.e2bba1a11cc04c89
+ m: 9c727edf66767ca3.8fe6d7c56a5ff965.0b9c016be95f18de.62bba1a11cc04c89
+
+VFMADDSUBPD_xmm_mem2 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].0101010101010101.8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMADDSUBPD_xmm_mem2 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMADDSUBPD_xmm_mem2 rand
+ before
+r1: 761b274ac4c4f0c7.f31ed81010c417bc.579f90d5d9cd1c3a.fceebf50e0d0ba24
+r2: 30c9028972f8733d.11f7fa4450de2529.1541139c8b1cd0d1.a11d81326f4e7880
+r3: 25c80a060da03fb0.c33ebc4b44b8ddd8.a1cd852d9cd97050.2d146432e64644c9
+r4: b3633c2f304791cd.e6c097130b5efcf6.5791e2f2a78f3762.7c9fe23c60c5d82b
+ m: 35e7926e777aa43f.56470887bfdd3daf.94d7265949ca62b4.6a8a793cf9d5f0d1
+ after
+r1: 761b274ac4c4f0c7.f31ed81010c417bc.579f90d5d9cd1c3a.fceebf50e0d0ba24
+r2: 30c9028972f8733d.11f7fa4450de2529.1541139c8b1cd0d1.a11d81326f4e7880
+r3: 25c80a060da03fb0.c33ebc4b44b8ddd8.a1cd852d9cd97050.2d146432e64644c9
+r4: [ ZERO ].[ ZERO ].1541139c8b1cd0d1.57b0deab16a341d2
+ m: 35e7926e777aa43f.56470887bfdd3daf.94d7265949ca62b4.6a8a793cf9d5f0d1
+
+VFMADDSUBPS_xmm ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101.81010101.01010101.81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMADDSUBPS_xmm specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].bf800000.bf800000.[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMADDSUBPS_xmm rand
+ before
+r1: 06a10a31.[ NAN ].ef9f8c92.7c405d2f.b2ed4ecc.1e172df2.d3a0a41f.ce854ae7
+r2: 84db9fe3.e4b100d4.8d969e22.5f9318a0.0e1d55b9.c001d4c7.93aee0cf.fbdea09a
+r3: 09e14df0.41cdc14f.0bf7ba22.83e22a31.04b4378b.ce1492e0.8680a739.9beeae16
+r4: f30110c4.32a534d0.478d5d7e.053a4e0c.f0fdf0ae.e1dda4e8.88e2774a.cbc13287
+ m: 9c86e5cb.54c59402.1c250222.00a7415e.2e467d8e.98e7468c.75a0cbed.a561e618
+ after
+r1: 06a10a31.[ NAN ].ef9f8c92.7c405d2f.b2ed4ecc.1e172df2.d3a0a41f.ce854ae7
+r2: 84db9fe3.e4b100d4.8d969e22.5f9318a0.0e1d55b9.c001d4c7.93aee0cf.fbdea09a
+r3: 09e14df0.41cdc14f.0bf7ba22.83e22a31.04b4378b.ce1492e0.8680a739.9beeae16
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].b2ed4ecc.4e96b300.d3a0a41f.584f90c4
+ m: 9c86e5cb.54c59402.1c250222.00a7415e.2e467d8e.98e7468c.75a0cbed.a561e618
+
+VFMADDSUBPS_xmm_src_dst ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101.81010101.01010101.81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMADDSUBPS_xmm_src_dst specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMADDSUBPS_xmm_src_dst rand
+ before
+r1: 62bbc771.43b71e92.668b24fb.9133bf52.1adad897.8cbfb478.29861f0d.48dc87f5
+r2: 9fedb222.9a090d2c.018b42f3.d3ec8415.1004ff35.5bf02957.[-SUBNR].ce3ed14b
+r3: b168a24a.f5479e7b.c9f1d5f8.e2de4bd3.6c11edd5.a106e2d6.55f9b979.53917f46
+r4: f2789356.f1fb0d2b.99885af4.db13d1b7.894d9fe1.f98d1aa0.861ef69c.f4e34e11
+ m: bf6982b0.29b396ea.4f1e4ed5.da99d2ee.c5040fc7.[ SUBNR].ee9b23ed.cc40fad9
+ after
+r1: 62bbc771.43b71e92.668b24fb.9133bf52.1adad897.8cbfb478.29861f0d.48dc87f5
+r2: 9fedb222.9a090d2c.018b42f3.d3ec8415.1004ff35.5bf02957.[-SUBNR].ce3ed14b
+r3: b168a24a.f5479e7b.c9f1d5f8.e2de4bd3.6c11edd5.a106e2d6.55f9b979.53917f46
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].1adad897.[ -INF ].29861f0d.[ INF ]
+ m: bf6982b0.29b396ea.4f1e4ed5.da99d2ee.c5040fc7.[ SUBNR].ee9b23ed.cc40fad9
+
+VFMADDSUBPS_xmm_mem1 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101.81010101.01010101.81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMADDSUBPS_xmm_mem1 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ -INF ].[ -INF ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMADDSUBPS_xmm_mem1 rand
+ before
+r1: 74876ac6.3afb7562.c67d2c86.fa7c09a3.7b813bf1.5120fbc8.683cbc58.f8b23fca
+r2: 6e1d4703.bf5de53f.d97270f2.57c73303.07121ecd.88441b7d.d2cc3eca.9347d80f
+r3: 077815d3.5567232e.66c99707.0e860c39.c501b4c6.4209aa2e.0719232d.ba0b82d5
+r4: 9ce5d1a2.97a56adb.474e1bb0.3bc55073.109cfa47.1afbe686.e2ede96f.8809f947
+ m: 89ad76dc.21a1f8f1.5acd7ad9.f991bada.462deabe.ada60932.41150c7a.1a4df892
+ after
+r1: 74876ac6.3afb7562.c67d2c86.fa7c09a3.7b813bf1.5120fbc8.683cbc58.f8b23fca
+r2: 6e1d4703.bf5de53f.d97270f2.57c73303.07121ecd.88441b7d.d2cc3eca.9347d80f
+r3: 077815d3.5567232e.66c99707.0e860c39.c501b4c6.4209aa2e.0719232d.ba0b82d5
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].462deabe.2da60932.41150c7a.9a4df892
+ m: 89ad76dc.21a1f8f1.5acd7ad9.f991bada.462deabe.ada60932.41150c7a.1a4df892
+
+VFMADDSUBPS_xmm_mem2 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101.81010101.01010101.81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMADDSUBPS_xmm_mem2 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMADDSUBPS_xmm_mem2 rand
+ before
+r1: 2a1f00ed.91e9071d.79112f6f.64f5079c.c2018297.97974fdd.fe5d063c.8be33ce1
+r2: db866b41.[-SUBNR].82e7b65c.99fdf3e5.df63bd3c.7359f634.f791559f.f8d88161
+r3: f82db344.8c8c9a65.4f1c8c8d.b3b639e1.fba1981a.dd7938e3.067d7491.7c37833e
+r4: de62d563.51fe96da.be7a2cef.cf2b96bb.70050d9d.72825295.09eddffd.330cfda3
+ m: e76fcc08.6aeb0414.a9cd126c.0869c6a0.9cdd1a32.cd007ff7.daac12cf.3a64acbd
+ after
+r1: 2a1f00ed.91e9071d.79112f6f.64f5079c.c2018297.97974fdd.fe5d063c.8be33ce1
+r2: db866b41.[-SUBNR].82e7b65c.99fdf3e5.df63bd3c.7359f634.f791559f.f8d88161
+r3: f82db344.8c8c9a65.4f1c8c8d.b3b639e1.fba1981a.dd7938e3.067d7491.7c37833e
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].df63b483.f359f5b7.f791559f.78ecfef8
+ m: e76fcc08.6aeb0414.a9cd126c.0869c6a0.9cdd1a32.cd007ff7.daac12cf.3a64acbd
+
+VFMSUBADDPD_xmm ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].8101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMSUBADDPD_xmm specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ INF ].[ INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMSUBADDPD_xmm rand
+ before
+r1: 6fa194a173e020c0.ede3baf27b7b85bb.d973ba438b80fdb5.56878af3ad4a4cb8
+r2: d444299809682589.6787a06c436d8e39.8514e93e478d067a.5a4ac156a6cb98bf
+r3: 71a4885bc70f501c.f18441c67d4b9e45.fa0ba48e9db3d6f2.c0c135e244f24dfe
+r4: a20cab554a62dd24.68a718ec4422710c.95a6e59e2a7fabcb.65b86284a1cb27a3
+ m: c3ca90f22dec084f.a9bca1cab4fdc2ba.b330aadc8a7cbfaf.26fbc229d962e2d7
+ after
+r1: 6fa194a173e020c0.ede3baf27b7b85bb.d973ba438b80fdb5.56878af3ad4a4cb8
+r2: d444299809682589.6787a06c436d8e39.8514e93e478d067a.5a4ac156a6cb98bf
+r3: 71a4885bc70f501c.f18441c67d4b9e45.fa0ba48e9db3d6f2.c0c135e244f24dfe
+r4: [ ZERO ].[ ZERO ].5973ba438b80fdb5.db1cc786de73a79f
+ m: c3ca90f22dec084f.a9bca1cab4fdc2ba.b330aadc8a7cbfaf.26fbc229d962e2d7
+
+VFMSUBADDPD_xmm_src_dst ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].8101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMSUBADDPD_xmm_src_dst specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ INF ].[ INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMSUBADDPD_xmm_src_dst rand
+ before
+r1: 3028339e0d3a0c46.8e8f584ceae94e7a.aef4eeb358364f4a.dd55d3bb09c439c9
+r2: 45738ec585d726b8.f4ecb95e02f1d179.e33fad8f313a9649.67940f284cfce9a3
+r3: 5df79fd3324f914f.b79f41ec172107e2.af5de4ddb013d258.a082f55bbf17ae91
+r4: d6006035af2e8bb7.b3736be34585abe2.6c9a8e07714d3d22.64ecfe407d2043c1
+ m: 0bd9cf5599014e9d.c435b32da92a7aa5.7742a77a11751354.8f9ea7c3a323665c
+ after
+r1: 3028339e0d3a0c46.8e8f584ceae94e7a.aef4eeb358364f4a.dd55d3bb09c439c9
+r2: 45738ec585d726b8.f4ecb95e02f1d179.e33fad8f313a9649.67940f284cfce9a3
+r3: 5df79fd3324f914f.b79f41ec172107e2.af5de4ddb013d258.a082f55bbf17ae91
+r4: [ ZERO ].[ ZERO ].[ -INF ].[ INF ]
+ m: 0bd9cf5599014e9d.c435b32da92a7aa5.7742a77a11751354.8f9ea7c3a323665c
+
+VFMSUBADDPD_xmm_mem1 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].8101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMSUBADDPD_xmm_mem1 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMSUBADDPD_xmm_mem1 rand
+ before
+r1: 57d0e8a18b5417ad.c6b295b85f1c3056.2ca02ba32b169299.fd646dd04c2dd191
+r2: 182fa58322b12192.95b48e6f81658922.e70216ec5cbcf49e.8a09cb539549408a
+r3: a9430469f9a6aaf9.0d07193d2e134034.05b265c33ff4760f.125b3d3899837173
+r4: 655800beacbeec8e.0a79b210803112b9.e0fd139371495497.7124406c74e81e7a
+ m: aaba95edd88623fc.68d5d5d393ccbadd.d52f1cc78e47c9e3.83314ed9438203c8
+ after
+r1: 57d0e8a18b5417ad.c6b295b85f1c3056.2ca02ba32b169299.fd646dd04c2dd191
+r2: 182fa58322b12192.95b48e6f81658922.e70216ec5cbcf49e.8a09cb539549408a
+r3: a9430469f9a6aaf9.0d07193d2e134034.05b265c33ff4760f.125b3d3899837173
+r4: [ ZERO ].[ ZERO ].552f1cc78e47c9e3.83314ed9438203c8
+ m: aaba95edd88623fc.68d5d5d393ccbadd.d52f1cc78e47c9e3.83314ed9438203c8
+
+VFMSUBADDPD_xmm_mem2 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].8101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMSUBADDPD_xmm_mem2 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMSUBADDPD_xmm_mem2 rand
+ before
+r1: d2b5bf6419898df0.03e6fe7283eff6cb.40947ccd307b129e.244ee56d2260de8c
+r2: 3b947b8f0a536415.b779aada6ea680b0.7d772f10f5706b75.304780122c8b69f0
+r3: 3fa5c4d84771e518.605a54f56dfe15b7.e82632fc79b30f14.83e79bb67d116120
+r4: 3b3296ac6d6e4ba4.d95578b09e02700d.ddeb80fe57ce3c26.f9fcb34432fe8249
+ m: 8c88ed7717d6d466.003692f81dbe4ede.b71315802c502c58.6d5043a8665c8797
+ after
+r1: d2b5bf6419898df0.03e6fe7283eff6cb.40947ccd307b129e.244ee56d2260de8c
+r2: 3b947b8f0a536415.b779aada6ea680b0.7d772f10f5706b75.304780122c8b69f0
+r3: 3fa5c4d84771e518.605a54f56dfe15b7.e82632fc79b30f14.83e79bb67d116120
+r4: [ ZERO ].[ ZERO ].fd772f10f5706b75.b147ff7383304159
+ m: 8c88ed7717d6d466.003692f81dbe4ede.b71315802c502c58.6d5043a8665c8797
+
+VFMSUBADDPS_xmm ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101.01010101.81010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMSUBADDPS_xmm specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].3f800000.3f800000.[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMSUBADDPS_xmm rand
+ before
+r1: 8cf3c5a6.e236ba0a.b0c81fb7.053f6b55.d4eaedef.93c21b55.bdb0c6ce.36392d36
+r2: 98bf1ba3.6919393b.c4d999db.7390839e.8fbc05b8.29b247ca.c4e8bba2.bda13050
+r3: 0d37eadc.490b8fa6.1a337e4f.82bd51e7.44d55845.89abea63.5dc49b10.189f4c14
+r4: 45a92ebc.1d99f6f6.8da34afe.4ed3935a.4f80e204.4f3a41cb.6610e404.623f3cac
+ m: 9d5fe4af.824eabd8.f8f577d6.f4dd0223.0b0b9f60.18e987ae.ba97106b.b88dbd45
+ after
+r1: 8cf3c5a6.e236ba0a.b0c81fb7.053f6b55.d4eaedef.93c21b55.bdb0c6ce.36392d36
+r2: 98bf1ba3.6919393b.c4d999db.7390839e.8fbc05b8.29b247ca.c4e8bba2.bda13050
+r3: 0d37eadc.490b8fa6.1a337e4f.82bd51e7.44d55845.89abea63.5dc49b10.189f4c14
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].54eaedef.93c21b55.e332bca0.36392d36
+ m: 9d5fe4af.824eabd8.f8f577d6.f4dd0223.0b0b9f60.18e987ae.ba97106b.b88dbd45
+
+VFMSUBADDPS_xmm_src_dst ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101.01010101.81010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMSUBADDPS_xmm_src_dst specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMSUBADDPS_xmm_src_dst rand
+ before
+r1: 71a60620.13b6eaf8.39f583c2.90e85d6f.d6c08bc5.7f47f9ba.34279d2f.35968b0a
+r2: 1eca927d.6d5eee01.2a6fe8ae.3cfe5e6a.0beca39f.21ddd399.b28a073e.f6656128
+r3: fe178332.2bd1f4a0.a92e2587.172ec23f.05dbe25a.9a3951f7.0e8dc882.1606fcca
+r4: 6ed9d5a9.ea9b3880.90ffb337.3b81451b.22d94462.84e6ae81.26fc5ee9.b286181e
+ m: ca5b844f.4549f54e.bdaf0fab.c405a22a.bd31c523.7e7128e3.d4a3445e.e5f0714d
+ after
+r1: 71a60620.13b6eaf8.39f583c2.90e85d6f.d6c08bc5.7f47f9ba.34279d2f.35968b0a
+r2: 1eca927d.6d5eee01.2a6fe8ae.3cfe5e6a.0beca39f.21ddd399.b28a073e.f6656128
+r3: fe178332.2bd1f4a0.a92e2587.172ec23f.05dbe25a.9a3951f7.0e8dc882.1606fcca
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].56c08bc5.7f47f9ba.b4279d2f.69704cee
+ m: ca5b844f.4549f54e.bdaf0fab.c405a22a.bd31c523.7e7128e3.d4a3445e.e5f0714d
+
+VFMSUBADDPS_xmm_mem1 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101.01010101.81010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMSUBADDPS_xmm_mem1 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ INF ].[ INF ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMSUBADDPS_xmm_mem1 rand
+ before
+r1: 6eeb8d90.d86668b6.0a08b6d0.cfc59797.3131620a.2265f8c8.f64df6cd.cb51c286
+r2: b6d3ebd9.407ecd63.55d72390.77cddd8e.dc231681.0c4e5ddd.66c8f022.81b3c8f2
+r3: fe609a94.181e6002.78e7d2d9.d92a333d.1854ddf6.d8b991ce.01deaf49.23243fc0
+r4: a2de962f.fdd15c3e.50063f96.10e753cd.4210b3d3.2431d146.a45cad2e.ccb0e21a
+ m: fe98dc15.8b24fec4.bafee7b3.3811fa6d.b7a39486.894259f1.290e68be.98626e2d
+ after
+r1: 6eeb8d90.d86668b6.0a08b6d0.cfc59797.3131620a.2265f8c8.f64df6cd.cb51c286
+r2: b6d3ebd9.407ecd63.55d72390.77cddd8e.dc231681.0c4e5ddd.66c8f022.81b3c8f2
+r3: fe609a94.181e6002.78e7d2d9.d92a333d.1854ddf6.d8b991ce.01deaf49.23243fc0
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].379f57a6.a595975e.28018454.98626e2d
+ m: fe98dc15.8b24fec4.bafee7b3.3811fa6d.b7a39486.894259f1.290e68be.98626e2d
+
+VFMSUBADDPS_xmm_mem2 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101.01010101.81010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMSUBADDPS_xmm_mem2 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMSUBADDPS_xmm_mem2 rand
+ before
+r1: 6ddc67b2.5da28240.909c451c.6eb3e447.d1587d7a.a579647d.6dc05be3.a4469f24
+r2: 4df43372.0fd7245d.afacd5bd.ced9cd88.ee7d691b.14613094.4d3d038a.0b69312c
+r3: f92e3cc1.3e4f1fc8.f3fa1382.738f705b.685c54d5.7186f6e2.a353dba0.ead5df70
+r4: cdd47e0b.8597b02c.38527c57.7ae28aed.9c423a14.5875f514.4ccc5e10.5c99661d
+ m: 2533f6bc.813a1336.5b808a28.feded669.e77b1844.66b967d6.24750ac6.7ebe825f
+ after
+r1: 6ddc67b2.5da28240.909c451c.6eb3e447.d1587d7a.a579647d.6dc05be3.a4469f24
+r2: 4df43372.0fd7245d.afacd5bd.ced9cd88.ee7d691b.14613094.4d3d038a.0b69312c
+r3: f92e3cc1.3e4f1fc8.f3fa1382.738f705b.685c54d5.7186f6e2.a353dba0.ead5df70
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ -INF ].[ INF ].cd3d038a.[ -INF ]
+ m: 2533f6bc.813a1336.5b808a28.feded669.e77b1844.66b967d6.24750ac6.7ebe825f
+
+VFMSUBPD_xmm ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].8101010101010101.8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMSUBPD_xmm specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ INF ].[ INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMSUBPD_xmm rand
+ before
+r1: 5c979f40cdc58392.364fbbe21b8d12fc.a353e8d137de89d3.071b5bad6b52ee61
+r2: d04b750405c33deb.a68d8a6feefdf8d2.2d16a827667197b8.d187cbb340606850
+r3: dc9d7472c7c07dee.870474bd92394516.e11053b38ffdcd30.5e88d8c318f5aa57
+r4: dbd798f8ac487f46.b581f3b7244eb4f5.1b8ce6e04f0e66e8.8ae9fdca101c70a3
+ m: 2b46de0152e87ea0.0ccf8549bf47029a.37d75b1941319f8c.3175b6b243e17860
+ after
+r1: 5c979f40cdc58392.364fbbe21b8d12fc.a353e8d137de89d3.071b5bad6b52ee61
+r2: d04b750405c33deb.a68d8a6feefdf8d2.2d16a827667197b8.d187cbb340606850
+r3: dc9d7472c7c07dee.870474bd92394516.e11053b38ffdcd30.5e88d8c318f5aa57
+r4: [ ZERO ].[ ZERO ].ce371eadf7f414b3.f02279f67e169df7
+ m: 2b46de0152e87ea0.0ccf8549bf47029a.37d75b1941319f8c.3175b6b243e17860
+
+VFMSUBPD_xmm_src_dst ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].8101010101010101.8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMSUBPD_xmm_src_dst specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ INF ].[ INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMSUBPD_xmm_src_dst rand
+ before
+r1: 263641f8552cb7a7.68bca55e8030eb32.913db0cc02f1b3c7.2ff97f68cd517cb9
+r2: 2af3bd4b509e6608.a513cfe482162be8.850ae0642ddae046.6041d5d9cb7738db
+r3: 91c94f65dfccc66f.9e9f80c6e2047dea.6f8ae74d5f7960b4.a01933ef595f6af1
+r4: b903f1b29f411487.312d32f1bb069e61.ab09c2f3335970be.cb4d15989216cc28
+ m: fcefa19f2c8a8cfd.3989634f2a294a7c.95d26cc246074b10.bda9f7bf92a71bac
+ after
+r1: 263641f8552cb7a7.68bca55e8030eb32.913db0cc02f1b3c7.2ff97f68cd517cb9
+r2: 2af3bd4b509e6608.a513cfe482162be8.850ae0642ddae046.6041d5d9cb7738db
+r3: 91c94f65dfccc66f.9e9f80c6e2047dea.6f8ae74d5f7960b4.a01933ef595f6af1
+r4: [ ZERO ].[ ZERO ].113db0cc02f1b3c7.eba035d6c0887eba
+ m: fcefa19f2c8a8cfd.3989634f2a294a7c.95d26cc246074b10.bda9f7bf92a71bac
+
+VFMSUBPD_xmm_mem1 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].8101010101010101.8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMSUBPD_xmm_mem1 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMSUBPD_xmm_mem1 rand
+ before
+r1: b8d75a9620326a7d.927f8ecd4a783d65.8932e026330d2e55.52f8564f761e13a8
+r2: 470818041ac5e9b2.18db305838ff3248.e3761d8b97fa553a.6508ac365a886f48
+r3: 06ced856b4d04648.a668c3da0fcbe652.ffe81c5e0d57fc6a.d4a3775f58f0ecba
+r4: 527594f68adebded.1af4c541ebe715af.39d4db0931b25e92.7a9632b68f624628
+ m: 85484a52397b894a.4f49b178e95f7a8a.ed8854faa096b85e.32ad5a2818eb39be
+ after
+r1: b8d75a9620326a7d.927f8ecd4a783d65.8932e026330d2e55.52f8564f761e13a8
+r2: 470818041ac5e9b2.18db305838ff3248.e3761d8b97fa553a.6508ac365a886f48
+r3: 06ced856b4d04648.a668c3da0fcbe652.ffe81c5e0d57fc6a.d4a3775f58f0ecba
+r4: [ ZERO ].[ ZERO ].[ INF ].f9be0494676cc397
+ m: 85484a52397b894a.4f49b178e95f7a8a.ed8854faa096b85e.32ad5a2818eb39be
+
+VFMSUBPD_xmm_mem2 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].8101010101010101.8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMSUBPD_xmm_mem2 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMSUBPD_xmm_mem2 rand
+ before
+r1: fc95f5d55c34e70e.2034036b2540d210.764f859cf68f4679.dab3699f129680a9
+r2: 13a692ea909413e3.6b813705ba95d96d.32746a5ace2a448f.4d76dd08966fd815
+r3: 27c81bff70274976.0afcca34c46a4acc.7c44fda2c4f3ed4e.66c03150c383fd2d
+r4: 92478e7f987ac472.db7137e460cce35a.b00b3cdf75747e60.035ee161b2ddaa1e
+ m: b16fe6d6a518c184.b9abfaffa9c65e42.2915227d7d3b3371.fe1c6a2981899c14
+ after
+r1: fc95f5d55c34e70e.2034036b2540d210.764f859cf68f4679.dab3699f129680a9
+r2: 13a692ea909413e3.6b813705ba95d96d.32746a5ace2a448f.4d76dd08966fd815
+r3: 27c81bff70274976.0afcca34c46a4acc.7c44fda2c4f3ed4e.66c03150c383fd2d
+r4: [ ZERO ].[ ZERO ].656bba253e3582e8.[ -INF ]
+ m: b16fe6d6a518c184.b9abfaffa9c65e42.2915227d7d3b3371.fe1c6a2981899c14
+
+VFMSUBPS_xmm ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101.81010101.81010101.81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMSUBPS_xmm specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].3f800000.bf800000.[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMSUBPS_xmm rand
+ before
+r1: e08c1f71.338e7c57.7f778f72.bc6577b1.45aeabe8.76d3472e.35c64793.4c948f3a
+r2: 7be936ba.dd663098.0aa27329.b5b3ecd2.5e21d38d.[ NAN ].8228f38b.2e093fbc
+r3: ded3251e.3f2e1bf3.37f62011.aebf77d2.d2bc96d6.b1a87f5b.c30eedfc.43f567c8
+r4: 6597ea0a.f6727713.e0401415.c692d5dd.fbc9f130.2bfc1b23.d243aed4.a862c488
+ m: 6c7f80e8.9ebd80a5.e34bca20.163ac21e.3795df08.06520647.8d94b3ff.795f1228
+ after
+r1: e08c1f71.338e7c57.7f778f72.bc6577b1.45aeabe8.76d3472e.35c64793.4c948f3a
+r2: 7be936ba.dd663098.0aa27329.b5b3ecd2.5e21d38d.[ NAN ].8228f38b.2e093fbc
+r3: ded3251e.3f2e1bf3.37f62011.aebf77d2.d2bc96d6.b1a87f5b.c30eedfc.43f567c8
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].f16e6d6a.[ NAN ].b5c64793.cc948f3a
+ m: 6c7f80e8.9ebd80a5.e34bca20.163ac21e.3795df08.06520647.8d94b3ff.795f1228
+
+VFMSUBPS_xmm_src_dst ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101.81010101.81010101.81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMSUBPS_xmm_src_dst specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMSUBPS_xmm_src_dst rand
+ before
+r1: 4fd7e326.d29b7454.1ae5bf20.bcc2f9c2.e06c5cc8.e1357d72.cece7967.d1f50cd5
+r2: 6aed102f.2e988dcd.62d86d00.d43737f5.549a65de.5531bc50.72bb7bf9.cc326fbb
+r3: 190c026f.4f4108bb.97f152ac.79a338e2.ed6bf4b5.00d2fe8f.552735a2.8721f705
+r4: b87fb552.d02120cc.96fce910.c815b7b5.082a07b9.7ea580d9.54e0244c.1dcf60e0
+ m: a2932544.4ec512a9.39c5af18.dc96719b.02249956.6a367eda.49b0c2e5.ab476577
+ after
+r1: 4fd7e326.d29b7454.1ae5bf20.bcc2f9c2.e06c5cc8.e1357d72.cece7967.d1f50cd5
+r2: 6aed102f.2e988dcd.62d86d00.d43737f5.549a65de.5531bc50.72bb7bf9.cc326fbb
+r3: 190c026f.4f4108bb.97f152ac.79a338e2.ed6bf4b5.00d2fe8f.552735a2.8721f705
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].606c5cc8.[ INF ].[ INF ].51f50cd5
+ m: a2932544.4ec512a9.39c5af18.dc96719b.02249956.6a367eda.49b0c2e5.ab476577
+
+VFMSUBPS_xmm_mem1 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101.81010101.81010101.81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMSUBPS_xmm_mem1 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ INF ].[ -INF ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMSUBPS_xmm_mem1 rand
+ before
+r1: 35954eb1.64b81a01.5d181eb0.d13422c0.35a6a7f8.600f343f.11658d57.4d95c3f7
+r2: cccf2d05.af86747e.dec1b4c5.c4fa8650.fefa2b0b.fdbeddb4.88c90090.1dc5368c
+r3: c38dbdac.cabb5bcc.988bec41.d1f55876.ba6d23fb.ddcfb6e4.8aa9987b.39e47961
+r4: 751dfa13.52e40c98.67444211.1330555e.c34a8a35.9bcdfb7c.f3d1cf04.bdfd4aa3
+ m: 40c9e0a4.e28cc38e.27b63222.a6b73935.76df5c23.d344e727.9f0d2317.c41d637d
+ after
+r1: 35954eb1.64b81a01.5d181eb0.d13422c0.35a6a7f8.600f343f.11658d57.4d95c3f7
+r2: cccf2d05.af86747e.dec1b4c5.c4fa8650.fefa2b0b.fdbeddb4.88c90090.1dc5368c
+r3: c38dbdac.cabb5bcc.988bec41.d1f55876.ba6d23fb.ddcfb6e4.8aa9987b.39e47961
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].79e43f92.[ INF ].1f0d2317.441d637d
+ m: 40c9e0a4.e28cc38e.27b63222.a6b73935.76df5c23.d344e727.9f0d2317.c41d637d
+
+VFMSUBPS_xmm_mem2 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101.81010101.81010101.81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMSUBPS_xmm_mem2 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMSUBPS_xmm_mem2 rand
+ before
+r1: [ NAN ].1740bc59.b4ae395f.a797c027.2f769533.22c0b892.6a280fa0.6b4f801c
+r2: 8da998f8.8c8b32a6.eaf8d1b4.31daa560.4a5c32cf.23cea869.30f00f8b.cd9f5fac
+r3: c8746293.ddf96221.a55f780d.618fa50b.23de2e65.73f9f357.cd2f9fc5.071aba58
+r4: 8a8cc509.a7178875.c1b1aa55.52bf7b54.16458560.adcdd709.1db23c38.34cb4d4d
+ m: 313cbec6.8670df4e.1ab8e17b.2178e568.[ NAN ].6ed78e2a.fc4561d2.70bed6b6
+ after
+r1: [ NAN ].1740bc59.b4ae395f.a797c027.2f769533.22c0b892.6a280fa0.6b4f801c
+r2: 8da998f8.8c8b32a6.eaf8d1b4.31daa560.4a5c32cf.23cea869.30f00f8b.cd9f5fac
+r3: c8746293.ddf96221.a55f780d.618fa50b.23de2e65.73f9f357.cd2f9fc5.071aba58
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ].[ INF ].[ INF ].4d9f5fac
+ m: 313cbec6.8670df4e.1ab8e17b.2178e568.[ NAN ].6ed78e2a.fc4561d2.70bed6b6
+
+VFMSUBSD_xmm ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMSUBSD_xmm specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMSUBSD_xmm rand
+ before
+r1: 17d247361590a45a.8c419b68e9c69d73.bafa353551a25467.46b48a7dd8000fc0
+r2: 9a985ec5f0031343.f3185309c7b360a0.23de85e7f3ba676c.d7ca3327879cb597
+r3: 14dcfee0b45668b5.2a09854ad64de91c.16da21aeefac01e4.8b55d9bb9a9e8466
+r4: e2e823f1fc15de5d.0fe0ad1832a0f513.ef3804f7e2035f7c.3d1ff6252d13375a
+ m: 6109ca6565cab2e7.7d69475df9b640b0.0a452b2c674cbddf.cbf508515b068b9e
+ after
+r1: 17d247361590a45a.8c419b68e9c69d73.bafa353551a25467.46b48a7dd8000fc0
+r2: 9a985ec5f0031343.f3185309c7b360a0.23de85e7f3ba676c.d7ca3327879cb597
+r3: 14dcfee0b45668b5.2a09854ad64de91c.16da21aeefac01e4.8b55d9bb9a9e8466
+r4: [ ZERO ].[ ZERO ].[ ZERO ].c6b48a7dd8000fc0
+ m: 6109ca6565cab2e7.7d69475df9b640b0.0a452b2c674cbddf.cbf508515b068b9e
+
+VFMSUBSD_xmm_src_dst ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMSUBSD_xmm_src_dst specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMSUBSD_xmm_src_dst rand
+ before
+r1: eb8aeda98a0320fe.506fd007449d8620.c34d90bb1a1256ba.10a38a2b40833c5f
+r2: ddb98a28084c634f.63bfc3013161828e.759b310e98e167b9.e8f5f99ff99706c8
+r3: 94e09c4d7a2fb985.94259c37dc0df227.7e7d09937d452c87.2eb7cf99a14da407
+r4: 6a4d20867d3a5b4d.bd6dd8955fad8f17.393d14b564cbe1d0.c0b48a0655b1d345
+ m: bc4a103eacf98853.bc63f107d94d1889.02284fdfe9fec142.78baa5d030d04fb1
+ after
+r1: eb8aeda98a0320fe.506fd007449d8620.c34d90bb1a1256ba.10a38a2b40833c5f
+r2: ddb98a28084c634f.63bfc3013161828e.759b310e98e167b9.e8f5f99ff99706c8
+r3: 94e09c4d7a2fb985.94259c37dc0df227.7e7d09937d452c87.2eb7cf99a14da407
+r4: [ ZERO ].[ ZERO ].[ ZERO ].69bc3599af13da2f
+ m: bc4a103eacf98853.bc63f107d94d1889.02284fdfe9fec142.78baa5d030d04fb1
+
+VFMSUBSD_xmm_mem1 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMSUBSD_xmm_mem1 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMSUBSD_xmm_mem1 rand
+ before
+r1: e6246ae1a4f77a42.6cd3657964fa47a9.348ab47fa96b0987.34939ce54eb5d374
+r2: 442729db00c06ec7.a888afd71cbfd9a5.2daf41013f9df44b.ce0cec2fcc6d1cbd
+r3: 329e49985ce0a08d.4e504c0d1ea88aa7.48e3f1cf4820c03b.24f10f9cc602e6b6
+r4: 0cd7c78555e44c41.38f5b60885c215db.e072c1566081a703.100e83175782ed8c
+ m: 2e1c9d0c8757ad8f.43446bb26e18386e.53a7ab02214be64e.702ec38c9cf9ec6a
+ after
+r1: e6246ae1a4f77a42.6cd3657964fa47a9.348ab47fa96b0987.34939ce54eb5d374
+r2: 442729db00c06ec7.a888afd71cbfd9a5.2daf41013f9df44b.ce0cec2fcc6d1cbd
+r3: 329e49985ce0a08d.4e504c0d1ea88aa7.48e3f1cf4820c03b.24f10f9cc602e6b6
+r4: [ ZERO ].[ ZERO ].[ ZERO ].f02ec38c9cf9ec6a
+ m: 2e1c9d0c8757ad8f.43446bb26e18386e.53a7ab02214be64e.702ec38c9cf9ec6a
+
+VFMSUBSD_xmm_mem2 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFMSUBSD_xmm_mem2 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFMSUBSD_xmm_mem2 rand
+ before
+r1: f4bac99b8dc50022.4c09e6f9f4b7ac8c.fbcfad402a0ab8c9.1e1f4ce7b072a07d
+r2: bafd469c03bb81a7.2d0fa3c734a93060.3637c27a144a5b20.f8ab9814aff9c5f0
+r3: dc31117d86c46bc9.c3241e0a49fd7e17.5e28e61e7d9809fe.d89f25ffb69a16f0
+r4: b6a224a9b26dfb35.eb12d4ad50bc53dc.d1f115970180fe0f.9bc76e95e06250a9
+ m: a49c7d8b21406d97.7fa6409c64f46bdc.e9dd4c503b8c7801.1defefc04a5c2f46
+ after
+r1: f4bac99b8dc50022.4c09e6f9f4b7ac8c.fbcfad402a0ab8c9.1e1f4ce7b072a07d
+r2: bafd469c03bb81a7.2d0fa3c734a93060.3637c27a144a5b20.f8ab9814aff9c5f0
+r3: dc31117d86c46bc9.c3241e0a49fd7e17.5e28e61e7d9809fe.d89f25ffb69a16f0
+r4: [ ZERO ].[ ZERO ].[ ZERO ].78ab9814aff9c5f0
+ m: a49c7d8b21406d97.7fa6409c64f46bdc.e9dd4c503b8c7801.1defefc04a5c2f46
+
+VFMSUBSS_xmm ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMSUBSS_xmm specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMSUBSS_xmm rand
+ before
+r1: 026a1791.72ccfc9a.5caddec3.a1b08243.033786b7.c84ab17d.3be2256e.10956ff4
+r2: 2c59ee26.3f9ae6eb.5ef02a0e.24fd533c.7c4dbf37.4346e632.cf6e8a89.4c18cbde
+r3: 7db5feb7.24386535.623ea069.09e69bf4.ae69f33c.480a53ca.b65d9cff.1df10031
+r4: 53ca44ae.bd31b525.4262bdc1.6b771596.f6d81f33.742433f2.cc7dd6bb.9c2cca19
+ m: 09e4bb78.a8121467.db27fc00.66bc7f4f.b0e63d86.6320c355.ed98b4a9.e8d6e4c1
+ after
+r1: 026a1791.72ccfc9a.5caddec3.a1b08243.033786b7.c84ab17d.3be2256e.10956ff4
+r2: 2c59ee26.3f9ae6eb.5ef02a0e.24fd533c.7c4dbf37.4346e632.cf6e8a89.4c18cbde
+r3: 7db5feb7.24386535.623ea069.09e69bf4.ae69f33c.480a53ca.b65d9cff.1df10031
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].2a8fd809
+ m: 09e4bb78.a8121467.db27fc00.66bc7f4f.b0e63d86.6320c355.ed98b4a9.e8d6e4c1
+
+VFMSUBSS_xmm_src_dst ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMSUBSS_xmm_src_dst specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMSUBSS_xmm_src_dst rand
+ before
+r1: fb4f5f82.7e66bca6.095bd914.17c2934b.39df4ba2.b0883fa0.f57ab3b5.1afb0c56
+r2: 84562c36.ddb9ea8e.a8c8d0e7.9a950eb5.eb0e45f4.f7eae27e.c0f14ecb.50a5fc04
+r3: 02471f02.6197d9cd.943b5e67.093fabba.23c025e6.d5d2e99c.2ac801d7.a6e270f6
+r4: cf6c3250.a58dc60d.a980fe7f.83ce2785.3d42e9e6.e5cb90a6.0fca48c5.37bd2658
+ m: 4912638e.4626edfa.c3622c1b.224d3e43.95de8b5f.c4611347.4bc49f81.2043d857
+ after
+r1: fb4f5f82.7e66bca6.095bd914.17c2934b.39df4ba2.b0883fa0.f57ab3b5.1afb0c56
+r2: 84562c36.ddb9ea8e.a8c8d0e7.9a950eb5.eb0e45f4.f7eae27e.c0f14ecb.50a5fc04
+r3: 02471f02.6197d9cd.943b5e67.093fabba.23c025e6.d5d2e99c.2ac801d7.a6e270f6
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].48f547d7
+ m: 4912638e.4626edfa.c3622c1b.224d3e43.95de8b5f.c4611347.4bc49f81.2043d857
+
+VFMSUBSS_xmm_mem1 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMSUBSS_xmm_mem1 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMSUBSS_xmm_mem1 rand
+ before
+r1: cb85ad27.dfef8a41.beaf6427.02c9ac20.87e109bc.0d20ad2c.ba8283f8.7c7f421f
+r2: b0100d87.0c73d98e.7631228f.404d2c47.6f975f6b.5d959b00.38d06f14.677d22db
+r3: 56017d1a.6a3e158c.c6b5e33f.f7e57be5.a94b87d7.4f4b1970.a17adfc3.fe4a32b8
+r4: 17a2fb4c.94dd7be8.8c072223.439e5525.914b7f6c.80ce6328.d14c4ff0.5df12fe2
+ m: 50408289.27db464e.a3f35b27.42837634.83e14297.8babb4d3.a4113b87.9f7ed584
+ after
+r1: cb85ad27.dfef8a41.beaf6427.02c9ac20.87e109bc.0d20ad2c.ba8283f8.7c7f421f
+r2: b0100d87.0c73d98e.7631228f.404d2c47.6f975f6b.5d959b00.38d06f14.677d22db
+r3: 56017d1a.6a3e158c.c6b5e33f.f7e57be5.a94b87d7.4f4b1970.a17adfc3.fe4a32b8
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ -INF ]
+ m: 50408289.27db464e.a3f35b27.42837634.83e14297.8babb4d3.a4113b87.9f7ed584
+
+VFMSUBSS_xmm_mem2 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFMSUBSS_xmm_mem2 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFMSUBSS_xmm_mem2 rand
+ before
+r1: 5e270e3e.bfc4b369.e7450a38.0da0993e.db5accc2.0d6d491e.f5972073.e0fedfcb
+r2: 9ba39cd5.f625fee5.33c9ac40.c2027b6e.f502195a.a1a15db4.a2a879a2.3d7c0ae2
+r3: 640027bc.6b896370.654abc2d.7db4d8f1.2c2526cc.e3d22e42.8611c200.d10412f6
+r4: 168aaa5d.b77c1eb3.5895b6ea.59c26bf2.de0fee83.708cf673.7d9e7877.b9a3b333
+ m: 0b8c2426.798b6a5d.e7761663.7239f19e.660b6dea.e45bf2f5.621a15f4.1064a8c4
+ after
+r1: 5e270e3e.bfc4b369.e7450a38.0da0993e.db5accc2.0d6d491e.f5972073.e0fedfcb
+r2: 9ba39cd5.f625fee5.33c9ac40.c2027b6e.f502195a.a1a15db4.a2a879a2.3d7c0ae2
+r3: 640027bc.6b896370.654abc2d.7db4d8f1.2c2526cc.e3d22e42.8611c200.d10412f6
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].bd7c0ae2
+ m: 0b8c2426.798b6a5d.e7761663.7239f19e.660b6dea.e45bf2f5.621a15f4.1064a8c4
+
+VFNMADDPD_xmm ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMADDPD_xmm specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ -INF ].[ -INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMADDPD_xmm rand
+ before
+r1: a0538e824a418418.f0b95884e5242620.20669f6fdacc5d71.13531763f353aed5
+r2: 312ce5ddc92aa790.4e2af939ce90c5a5.676d807dee6a7596.6a13f9b17d7d8194
+r3: 1a6126a38fd31173.dc95746e47878c59.996a0d80bdc2740e.452737c8cbeddc2b
+r4: b83e4c403ac7fc6a.78c5450f6f173567.11aa41e4e25f9685.7f5b4e96f8b07cc6
+ m: 651153206692a424.fc88e808604c7cfc.2a781815facd19a8.f37bb80620d01d92
+ after
+r1: a0538e824a418418.f0b95884e5242620.20669f6fdacc5d71.13531763f353aed5
+r2: 312ce5ddc92aa790.4e2af939ce90c5a5.676d807dee6a7596.6a13f9b17d7d8194
+r3: 1a6126a38fd31173.dc95746e47878c59.996a0d80bdc2740e.452737c8cbeddc2b
+r4: [ ZERO ].[ ZERO ].40e804d935c94236.ef4cfc9426475baf
+ m: 651153206692a424.fc88e808604c7cfc.2a781815facd19a8.f37bb80620d01d92
+
+VFNMADDPD_xmm_src_dst ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMADDPD_xmm_src_dst specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ -INF ].[ -INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMADDPD_xmm_src_dst rand
+ before
+r1: 7e2538b0aec1474b.46a8d94636311f44.42228e7fa1993723.7e53f304605c7bbb
+r2: 5fc5f55aaedf1f8b.30f295b30ed2d86a.b3f2a08f714e2da1.fdaf7a7cd45d516c
+r3: 643e888b03796992.9732973d033b649a.db3648af097836cf.4a5aca5a97e15cd2
+r4: e9dcecb049196109.58335bce32797f02.1438844d02a38f59.43215d8ac5f35818
+ m: 4aeb1e341b4e429f.4dc35e54b697e4cc.bc4550d3fa5c74ea.c2d1b1f87b9f006c
+ after
+r1: 7e2538b0aec1474b.46a8d94636311f44.42228e7fa1993723.7e53f304605c7bbb
+r2: 5fc5f55aaedf1f8b.30f295b30ed2d86a.b3f2a08f714e2da1.fdaf7a7cd45d516c
+r3: 643e888b03796992.9732973d033b649a.db3648af097836cf.4a5aca5a97e15cd2
+r4: [ ZERO ].[ ZERO ].42228e7fa1993723.[ INF ]
+ m: 4aeb1e341b4e429f.4dc35e54b697e4cc.bc4550d3fa5c74ea.c2d1b1f87b9f006c
+
+VFNMADDPD_xmm_mem1 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMADDPD_xmm_mem1 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMADDPD_xmm_mem1 rand
+ before
+r1: e3b7188215a149fe.53ac1abaaba25024.2da9a6af8d2f212e.a4344190d5f211f7
+r2: 0f8bd808d4a0b2d2.47bb0dec2ea57f37.c5af844c56a6d2d3.c616893fedf747e7
+r3: 2cb55931f3d6b9c8.03bdb2d65bac2c31.dea5e516f24fc282.024505efe2bb5e68
+r4: 957f97690fcf998c.647b85644dc3143d.d5d5c579fcb62eea.358c328ece4911a6
+ m: a6368e1cc3188fca.46c4038221f7f388.078c20e1106551b5.3bb68b07cdad1dcc
+ after
+r1: e3b7188215a149fe.53ac1abaaba25024.2da9a6af8d2f212e.a4344190d5f211f7
+r2: 0f8bd808d4a0b2d2.47bb0dec2ea57f37.c5af844c56a6d2d3.c616893fedf747e7
+r3: 2cb55931f3d6b9c8.03bdb2d65bac2c31.dea5e516f24fc282.024505efe2bb5e68
+r4: [ ZERO ].[ ZERO ].e465907374c51f40.3bb68b07cdad1dcc
+ m: a6368e1cc3188fca.46c4038221f7f388.078c20e1106551b5.3bb68b07cdad1dcc
+
+VFNMADDPD_xmm_mem2 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMADDPD_xmm_mem2 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMADDPD_xmm_mem2 rand
+ before
+r1: bb263bb7ac3dd62d.8563a61df253853d.ce16f2bacbea6990.f0908c45fcf43e06
+r2: 2f9b99a465c8ac61.fd23ec1fdce48589.87bf3870c9d1b026.30e6b13676282f82
+r3: 60e0a4508b474b13.8ad25076fcb5b098.8ed3ed6fa5a46224.d78477c55858ae69
+r4: a9435828b945f0ef.083a4f0c6dd2c295.409d0d24fbf1bd35.c23659debd8d75ea
+ m: 650eb2968b4fd6a0.532863cf4c4877ad.f76b95fa6844fb06.cbc7d36dc1d5402f
+ after
+r1: bb263bb7ac3dd62d.8563a61df253853d.ce16f2bacbea6990.f0908c45fcf43e06
+r2: 2f9b99a465c8ac61.fd23ec1fdce48589.87bf3870c9d1b026.30e6b13676282f82
+r3: 60e0a4508b474b13.8ad25076fcb5b098.8ed3ed6fa5a46224.d78477c55858ae69
+r4: [ ZERO ].[ ZERO ].c6512dbbb384d605.e35e7aa391627f17
+ m: 650eb2968b4fd6a0.532863cf4c4877ad.f76b95fa6844fb06.cbc7d36dc1d5402f
+
+VFNMADDPS_xmm ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMADDPS_xmm specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].bf800000.3f800000.[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMADDPS_xmm rand
+ before
+r1: f28eac08.9ff03bd3.47680aaa.b4228a0b.10877f5c.87275943.cf05615f.813bcd64
+r2: aa0f44e9.8eb45934.c0c5bf89.c26cb8dc.e73ec9b8.f5291397.a9ba7f9e.19ccd6b6
+r3: ebdd75a5.f6276c6e.9a0dfe58.9133bc4c.d8dc6e79.4dd364af.37b3aa17.a4931751
+r4: 0f443ca8.73d6b22d.b10a4403.3e825486.3fad6a0b.2cb38936.54bc5db7.3e9c4e61
+ m: 7490935e.9f4d651f.e1890b76.e4653ab7.78fcbada.2d54bed9.dca11469.04f43511
+ after
+r1: f28eac08.9ff03bd3.47680aaa.b4228a0b.10877f5c.87275943.cf05615f.813bcd64
+r2: aa0f44e9.8eb45934.c0c5bf89.c26cb8dc.e73ec9b8.f5291397.a9ba7f9e.19ccd6b6
+r3: ebdd75a5.f6276c6e.9a0dfe58.9133bc4c.d8dc6e79.4dd364af.37b3aa17.a4931751
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ -INF ].[ INF ].cf05615f.81347245
+ m: 7490935e.9f4d651f.e1890b76.e4653ab7.78fcbada.2d54bed9.dca11469.04f43511
+
+VFNMADDPS_xmm_src_dst ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMADDPS_xmm_src_dst specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMADDPS_xmm_src_dst rand
+ before
+r1: 740c7833.1916c2ee.0656d19d.a0e92b0a.df175852.ed423e44.ab2d4b18.12a6898d
+r2: 6d05e693.7bbf0446.fc3d1165.8d19e2ac.d04842df.070a4722.9d2e7eb2.83be0602
+r3: b9c7d9eb.61d469d4.9e0a48b8.c8011cc8.a7dc73ed.18371320.8e6e2a22.7349679c
+r4: b59e4ea5.68df2b44.ca89f084.6cae958b.bf1fe8e9.bb56dee9.59baca54.ff526986
+ m: bed6402f.2b6e8641.5b8587b3.952b0921.765d9b3d.8cf2e62a.dcdeda34.42e5c8ed
+ after
+r1: 740c7833.1916c2ee.0656d19d.a0e92b0a.df175852.ed423e44.ab2d4b18.12a6898d
+r2: 6d05e693.7bbf0446.fc3d1165.8d19e2ac.d04842df.070a4722.9d2e7eb2.83be0602
+r3: b9c7d9eb.61d469d4.9e0a48b8.c8011cc8.a7dc73ed.18371320.8e6e2a22.7349679c
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].df175852.ed423e44.377ea3ec.c39c2f42
+ m: bed6402f.2b6e8641.5b8587b3.952b0921.765d9b3d.8cf2e62a.dcdeda34.42e5c8ed
+
+VFNMADDPS_xmm_mem1 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMADDPS_xmm_mem1 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ -INF ].[ INF ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMADDPS_xmm_mem1 rand
+ before
+r1: 2ebbabf3.470db878.2ccb8833.608433b6.27e28a57.2897658e.f2a6d6ae.590f40fd
+r2: 62988b5f.5746fb94.1b276fef.e9c6d174.2ef9b0a2.2bd197c3.76de3baf.5fdb8ce1
+r3: b6badcde.f8a78c42.0365b8d3.4bfc9c8a.e7f00989.302dba72.46518421.715669c6
+r4: 876d9bdc.c5bca72e.bf51e0cb.a2325322.ad11927a.d336084a.3ccd2df1.aa8a93d7
+ m: 2ffdc2c5.5b0f8703.2db762c3.0b75b069.dea946e0.b179bef5.361cb20c.2785c541
+ after
+r1: 2ebbabf3.470db878.2ccb8833.608433b6.27e28a57.2897658e.f2a6d6ae.590f40fd
+r2: 62988b5f.5746fb94.1b276fef.e9c6d174.2ef9b0a2.2bd197c3.76de3baf.5fdb8ce1
+r3: b6badcde.f8a78c42.0365b8d3.4bfc9c8a.e7f00989.302dba72.46518421.715669c6
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].dea9450c.b179bef5.fdb5e16d.[ -INF ]
+ m: 2ffdc2c5.5b0f8703.2db762c3.0b75b069.dea946e0.b179bef5.361cb20c.2785c541
+
+VFNMADDPS_xmm_mem2 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMADDPS_xmm_mem2 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMADDPS_xmm_mem2 rand
+ before
+r1: 0bb64f05.552e696e.2762baa7.a1d0708a.d5042027.6581181f.0f0b8f5d.0353bc2f
+r2: 77e43d08.4fa5891a.8b206463.81504fb2.ed6e1ebb.8cda5175.a26641cf.5aff34ce
+r3: cfd2893a.e6ff22b4.33bbdde4.c7ff080c.84323c09.c110a7a3.ccf94350.4995e94a
+r4: 6fce2e08.b6c871e8.fc009f14.8dec59c5.f49e747b.a1b05354.6a8f11cb.ec2196ce
+ m: b32227dc.5a8cb261.c3bb28e1.f220fb09.9bfcc47e.c7469435.56f6272c.5eb0f887
+ after
+r1: 0bb64f05.552e696e.2762baa7.a1d0708a.d5042027.6581181f.0f0b8f5d.0353bc2f
+r2: 77e43d08.4fa5891a.8b206463.81504fb2.ed6e1ebb.8cda5175.a26641cf.5aff34ce
+r3: cfd2893a.e6ff22b4.33bbdde4.c7ff080c.84323c09.c110a7a3.ccf94350.4995e94a
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].ed6e1ebb.c8e06ace.646facd3.e8cf43d8
+ m: b32227dc.5a8cb261.c3bb28e1.f220fb09.9bfcc47e.c7469435.56f6272c.5eb0f887
+
+VFNMADDSD_xmm ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMADDSD_xmm specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ -INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMADDSD_xmm rand
+ before
+r1: f71b72246ed821cc.62b7f4350fa9ad03.d399277fd05ca4f2.6ef8025fbb4dcba1
+r2: 97050b4a8f37f9d4.b7c27dfe029229e0.fac199e95780c036.8c621d512005ca47
+r3: ef2cecbc58357726.9ca64127e7e72ccc.6ac01727f93e24ad.8d00f4eca9e2b2a5
+r4: 5bdb13e5665fd76e.ee30ba9cd9b572f2.81e19ba751200b05.4e9e031d71f33fe9
+ m: 37607b3155405557.892d6649f507b77e.997223d4fcb4b3e7.a908c6d194412d3c
+ after
+r1: f71b72246ed821cc.62b7f4350fa9ad03.d399277fd05ca4f2.6ef8025fbb4dcba1
+r2: 97050b4a8f37f9d4.b7c27dfe029229e0.fac199e95780c036.8c621d512005ca47
+r3: ef2cecbc58357726.9ca64127e7e72ccc.6ac01727f93e24ad.8d00f4eca9e2b2a5
+r4: [ ZERO ].[ ZERO ].[ ZERO ].6ef8025fbb4dcba1
+ m: 37607b3155405557.892d6649f507b77e.997223d4fcb4b3e7.a908c6d194412d3c
+
+VFNMADDSD_xmm_src_dst ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMADDSD_xmm_src_dst specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ -INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMADDSD_xmm_src_dst rand
+ before
+r1: de05200cbf652c8e.4966c11a56eab69e.0fbdaa1a95855502.7b09baf22fda37cd
+r2: ae17ffe2435999be.0baa45fb18692c7b.3f0f2ce5b8203000.a06e5a6e5dc91ac6
+r3: 02e2121f7aa8d894.a9c470d95890d444.86b5a6a102107e8e.f40422303b1b9254
+r4: 36b2573003de24bc.007fbd9e326c6c23.3ef813ba0fe17c57.53958e24e4db5aa2
+ m: a5d2c97f7788bae1.eca9a838c108ae44.c4276f9d7a206608.9aed1b36751530dd
+ after
+r1: de05200cbf652c8e.4966c11a56eab69e.0fbdaa1a95855502.7b09baf22fda37cd
+r2: ae17ffe2435999be.0baa45fb18692c7b.3f0f2ce5b8203000.a06e5a6e5dc91ac6
+r3: 02e2121f7aa8d894.a9c470d95890d444.86b5a6a102107e8e.f40422303b1b9254
+r4: [ ZERO ].[ ZERO ].[ ZERO ].7b09baf22fda37cd
+ m: a5d2c97f7788bae1.eca9a838c108ae44.c4276f9d7a206608.9aed1b36751530dd
+
+VFNMADDSD_xmm_mem1 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMADDSD_xmm_mem1 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMADDSD_xmm_mem1 rand
+ before
+r1: ad90647a7432d6af.490cad91217056d5.748db6b4df58784c.a3da435209d5ce30
+r2: a936258b9666b4d4.f37549976fb022ff.aa75e46ddb16edd0.4b278464bc28f0c8
+r3: f411072078b28ffa.c6b0f635c6d5ccf1.c32cf63309e40240.6e9f5a58ac1a54d1
+r4: ec6d05a4b6a1a4cd.9e88325743eb11d5.19fee7710650f247.e80f3f1bf2b5b476
+ m: eb961e83edc02ffa.57cb79e901fcadd7.0937b3956de6fb92.9444b197ac07cce3
+ after
+r1: ad90647a7432d6af.490cad91217056d5.748db6b4df58784c.a3da435209d5ce30
+r2: a936258b9666b4d4.f37549976fb022ff.aa75e46ddb16edd0.4b278464bc28f0c8
+r3: f411072078b28ffa.c6b0f635c6d5ccf1.c32cf63309e40240.6e9f5a58ac1a54d1
+r4: [ ZERO ].[ ZERO ].[ ZERO ].f9d70aa71c28d932
+ m: eb961e83edc02ffa.57cb79e901fcadd7.0937b3956de6fb92.9444b197ac07cce3
+
+VFNMADDSD_xmm_mem2 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMADDSD_xmm_mem2 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMADDSD_xmm_mem2 rand
+ before
+r1: 4fd84b29b99a6b2d.cd4345d71d165b24.ef23560adb3157cc.50072abaf61c5a46
+r2: 727e8a02b5bb9511.dbbd140db245d8e8.270ecc3cebbd43a2.f727286eebfe18c9
+r3: b2d6d57a7db0e953.5f056177dd93e04f.0d4312973a16fac0.656f27a1a7bbc398
+r4: 692a2afdae04a39e.34e7a802b90e2f84.fd0f238763c9b9d1.76aaa13e475e17e0
+ m: f4c785f8e443fea0.362f659862c280b3.52bffb790361bc82.06a61431e6f4cfcd
+ after
+r1: 4fd84b29b99a6b2d.cd4345d71d165b24.ef23560adb3157cc.50072abaf61c5a46
+r2: 727e8a02b5bb9511.dbbd140db245d8e8.270ecc3cebbd43a2.f727286eebfe18c9
+r3: b2d6d57a7db0e953.5f056177dd93e04f.0d4312973a16fac0.656f27a1a7bbc398
+r4: [ ZERO ].[ ZERO ].[ ZERO ].f727286eebfe18c9
+ m: f4c785f8e443fea0.362f659862c280b3.52bffb790361bc82.06a61431e6f4cfcd
+
+VFNMADDSS_xmm ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMADDSS_xmm specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMADDSS_xmm rand
+ before
+r1: b0f9e0d5.b9fa3702.41a91527.f6b99009.6a9d96d7.b56b3f7e.f02dfb66.a188a88b
+r2: f70c3901.ccb48a72.30203299.8e011bb2.a0f5f10f.15717d72.120cd2c9.93275e44
+r3: 264b8be9.b6fd329c.e1613adc.48a6dcd9.5015078b.c002b309.470f1546.d9dbad27
+r4: 9a04d2f8.16626c2c.2f38a8db.40b290ab.d648d4b9.52a71df1.6a0141c9.8eb2505e
+ m: ad810a9a.856e74cd.f571f982.9134f354.8dd95404.66eef7d3.59b0d13f.cfb80416
+ after
+r1: b0f9e0d5.b9fa3702.41a91527.f6b99009.6a9d96d7.b56b3f7e.f02dfb66.a188a88b
+r2: f70c3901.ccb48a72.30203299.8e011bb2.a0f5f10f.15717d72.120cd2c9.93275e44
+r3: 264b8be9.b6fd329c.e1613adc.48a6dcd9.5015078b.c002b309.470f1546.d9dbad27
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].ad8f9ed9
+ m: ad810a9a.856e74cd.f571f982.9134f354.8dd95404.66eef7d3.59b0d13f.cfb80416
+
+VFNMADDSS_xmm_src_dst ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMADDSS_xmm_src_dst specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMADDSS_xmm_src_dst rand
+ before
+r1: bc0f303b.a1ad862b.11d8a7bd.5735c0ff.d31583d8.98627c5e.efe64192.b7f7857a
+r2: 23fa3e47.06acddf4.5d393078.afc3b5d8.03485ea0.8590e93c.07700db0.637e8eb7
+r3: 3e8e322a.4ff6b6d1.b75f0f9f.b4e98c0d.78bee0cb.c8037a19.7f1bb183.ee56dcf9
+r4: 69170850.19174d71.f918c11e.83b301c8.90c305c2.fe476aa2.31b0aaf9.758d2b6b
+ m: 00e0ba25.[ NAN ].012ec0e2.372ed235.a6a3c9f2.c2e8f683.fbfe73fd.132e3739
+ after
+r1: bc0f303b.a1ad862b.11d8a7bd.5735c0ff.d31583d8.98627c5e.efe64192.b7f7857a
+r2: 23fa3e47.06acddf4.5d393078.afc3b5d8.03485ea0.8590e93c.07700db0.637e8eb7
+r3: 3e8e322a.4ff6b6d1.b75f0f9f.b4e98c0d.78bee0cb.c8037a19.7f1bb183.ee56dcf9
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ -INF ]
+ m: 00e0ba25.[ NAN ].012ec0e2.372ed235.a6a3c9f2.c2e8f683.fbfe73fd.132e3739
+
+VFNMADDSS_xmm_mem1 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMADDSS_xmm_mem1 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMADDSS_xmm_mem1 rand
+ before
+r1: 5f364616.9d10a4a4.a96e8ad5.ed65b981.15a929c7.b1735a67.b7d0887b.e445bb91
+r2: e266a78d.90ffdc91.cea49ae5.c06573d8.3b2220ae.6674d2fb.42f1655f.05df749c
+r3: e5bad9f8.74f6c1ee.4d9b6cfd.cd38bc65.725aaa11.7e7599eb.792f8795.92071e89
+r4: c47fd8c1.e480916a.[ SUBNR].2fed4f55.189dc35e.9404ece2.36546909.a6ca7482
+ m: db00a056.7c2a86af.c40047f4.038de9d3.87376700.45ac078c.562d87a7.5d3333b4
+ after
+r1: 5f364616.9d10a4a4.a96e8ad5.ed65b981.15a929c7.b1735a67.b7d0887b.e445bb91
+r2: e266a78d.90ffdc91.cea49ae5.c06573d8.3b2220ae.6674d2fb.42f1655f.05df749c
+r3: e5bad9f8.74f6c1ee.4d9b6cfd.cd38bc65.725aaa11.7e7599eb.792f8795.92071e89
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].5d3333b4
+ m: db00a056.7c2a86af.c40047f4.038de9d3.87376700.45ac078c.562d87a7.5d3333b4
+
+VFNMADDSS_xmm_mem2 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMADDSS_xmm_mem2 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMADDSS_xmm_mem2 rand
+ before
+r1: 868b2e22.d97fdd69.760648ac.6426460c.1c749362.2cfa2597.b6855d5c.d44e174a
+r2: 216a7d91.960bd145.f0fdfb1c.6ec3212c.349f42f2.e67983ac.302a6712.2627dc71
+r3: 08eb890f.505a9fef.0fb2dc30.3e71375e.2906701b.0eb55d7a.a1e722b7.70cb3d54
+r4: 96584f08.a2f98312.aff067d5.f03b44cf.58f31949.403befab.e5870936.cd45f720
+ m: 29fec9e8.2973b95b.ac8519f5.9f2d04ab.1eb33ae9.199674ec.d8d7987a.5aa2c601
+ after
+r1: 868b2e22.d97fdd69.760648ac.6426460c.1c749362.2cfa2597.b6855d5c.d44e174a
+r2: 216a7d91.960bd145.f0fdfb1c.6ec3212c.349f42f2.e67983ac.302a6712.2627dc71
+r3: 08eb890f.505a9fef.0fb2dc30.3e71375e.2906701b.0eb55d7a.a1e722b7.70cb3d54
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ -INF ]
+ m: 29fec9e8.2973b95b.ac8519f5.9f2d04ab.1eb33ae9.199674ec.d8d7987a.5aa2c601
+
+VFNMSUBPD_xmm ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].8101010101010101.8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMSUBPD_xmm specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ -INF ].[ -INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMSUBPD_xmm rand
+ before
+r1: 1c28f51c80557c76.e23b6d7d6753321d.d592cd65355229e8.56a34b7132ed6522
+r2: cb24ce0e442a090e.2de0df5a65ba8b51.dadbd02a2efc4a4c.3cb79f06723292b0
+r3: 913d502c107e9cd0.6a3eec76b56ecb74.89dc3ea5a31f12c3.64df0e25357e07d6
+r4: ccbe78e080dd7167.73220ebf7179adb2.3edf14402e48bffa.abe616bb98dc80c1
+ m: d6f4419831d4c380.2458c320b8e9ef36.55324c696b018a9d.ed9a32b2b658bb9d
+ after
+r1: 1c28f51c80557c76.e23b6d7d6753321d.d592cd65355229e8.56a34b7132ed6522
+r2: cb24ce0e442a090e.2de0df5a65ba8b51.dadbd02a2efc4a4c.3cb79f06723292b0
+r3: 913d502c107e9cd0.6a3eec76b56ecb74.89dc3ea5a31f12c3.64df0e25357e07d6
+r4: [ ZERO ].[ ZERO ].5592cd65355229e8.e1a6ec7f48ced2e4
+ m: d6f4419831d4c380.2458c320b8e9ef36.55324c696b018a9d.ed9a32b2b658bb9d
+
+VFNMSUBPD_xmm_src_dst ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].8101010101010101.8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMSUBPD_xmm_src_dst specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ -INF ].[ -INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMSUBPD_xmm_src_dst rand
+ before
+r1: 0d2ba7bfbfefcfc7.5bab8685a4c94b2d.2a1fe48bf7d8b257.06c5dff7abfe7295
+r2: cbafa6c1c5b8d1e7.f3e9d3da51267dc3.19f3d7116d5971d5.d234977794db61d6
+r3: 6ecc3a09dfbd048c.c8dc260bdc0b4323.7ef922696a0f05c2.2cb3d81c8dfb468b
+r4: 50cd6006aa89a564.b651fc046084577a.b57fbffe8986a7cb.f20e1dd4b168dbe1
+ m: cfff1221c2a9f018.9914d0b1f99e76f3.1acfac3d674a969c.ff10e3891c30dd04
+ after
+r1: 0d2ba7bfbfefcfc7.5bab8685a4c94b2d.2a1fe48bf7d8b257.06c5dff7abfe7295
+r2: cbafa6c1c5b8d1e7.f3e9d3da51267dc3.19f3d7116d5971d5.d234977794db61d6
+r3: 6ecc3a09dfbd048c.c8dc260bdc0b4323.7ef922696a0f05c2.2cb3d81c8dfb468b
+r4: [ ZERO ].[ ZERO ].aa1fe48bf7d8b257.[ -INF ]
+ m: cfff1221c2a9f018.9914d0b1f99e76f3.1acfac3d674a969c.ff10e3891c30dd04
+
+VFNMSUBPD_xmm_mem1 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].8101010101010101.8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMSUBPD_xmm_mem1 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMSUBPD_xmm_mem1 rand
+ before
+r1: 45af4ec7c2a82157.4df11effc5645bbb.0937e4909fe80ce0.2f87a429eb5f081f
+r2: 10271064461273cb.adb462d8dde2c3fe.de016364cdeb4644.5e3dde9f39ff175e
+r3: 8ab45265eb742321.9729192a5f256ae7.f57a25258fdf8073.67ff0cd7231ec7ef
+r4: 10a112344c596d04.e61bbedf67380ca3.aaee27407e51f51a.2899aabdc5c8d4fc
+ m: ff3c4b3f064d8c21.7557cde51027645d.59a8632038cce2e4.7cd7343d3907fab1
+ after
+r1: 45af4ec7c2a82157.4df11effc5645bbb.0937e4909fe80ce0.2f87a429eb5f081f
+r2: 10271064461273cb.adb462d8dde2c3fe.de016364cdeb4644.5e3dde9f39ff175e
+r3: 8ab45265eb742321.9729192a5f256ae7.f57a25258fdf8073.67ff0cd7231ec7ef
+r4: [ ZERO ].[ ZERO ].[ -INF ].[ -INF ]
+ m: ff3c4b3f064d8c21.7557cde51027645d.59a8632038cce2e4.7cd7343d3907fab1
+
+VFNMSUBPD_xmm_mem2 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].8101010101010101.8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMSUBPD_xmm_mem2 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMSUBPD_xmm_mem2 rand
+ before
+r1: b1cff9f1b4ddbe23.22a9c22776ff3042.5df6d73059dd837e.3e8527449ee9f43b
+r2: 83a818b6f3943cb7.c8dd1991b6cb297d.14227fde7c0f1494.4c6efdbc0d7a7fc6
+r3: d111a5f95efe4589.42bf4f0fec980e3b.d97955953deed0d2.81603593a4c5577d
+r4: f7579b2891a81344.6e1bdf8d327099a8.084857c13907f4e2.b82548b37fd6378d
+ m: 51c6f6af2a1de395.26bc45f7a76187ef.fcd880ce0be4bb73.cf8ab30ab9b9dc22
+ after
+r1: b1cff9f1b4ddbe23.22a9c22776ff3042.5df6d73059dd837e.3e8527449ee9f43b
+r2: 83a818b6f3943cb7.c8dd1991b6cb297d.14227fde7c0f1494.4c6efdbc0d7a7fc6
+r3: d111a5f95efe4589.42bf4f0fec980e3b.d97955953deed0d2.81603593a4c5577d
+r4: [ ZERO ].[ ZERO ].[ -INF ].cc6efdbc0d7a7fc6
+ m: 51c6f6af2a1de395.26bc45f7a76187ef.fcd880ce0be4bb73.cf8ab30ab9b9dc22
+
+VFNMSUBPS_xmm ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101.81010101.81010101.81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMSUBPS_xmm specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].3f800000.bf800000.[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMSUBPS_xmm rand
+ before
+r1: 3ca9b2f8.c2eaf127.4870fd3a.6577943d.1378cc28.5014632f.a05bf383.6f7b0267
+r2: 124ecb70.f79979a7.ae018440.88bd7bbe.a773373b.a32026c3.09648309.bc276589
+r3: 30ff3e83.65b8b6c1.363c54f6.2d3ffa9d.1614be74.a19641da.e470df8a.bcc9c0b3
+r4: f209069e.a7d3e520.baedeb49.6f09ca07.baa85b3d.e501ef21.0e4d83f1.8c6ed012
+ m: b4b81f2b.59754171.17dfc424.6b28aa27.f17c0c04.0cee6e43.64c5ec2b.482151d1
+ after
+r1: 3ca9b2f8.c2eaf127.4870fd3a.6577943d.1378cc28.5014632f.a05bf383.6f7b0267
+r2: 124ecb70.f79979a7.ae018440.88bd7bbe.a773373b.a32026c3.09648309.bc276589
+r3: 30ff3e83.65b8b6c1.363c54f6.2d3ffa9d.1614be74.a19641da.e470df8a.bcc9c0b3
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].9378cc28.d014632f.2e570262.ef7b0267
+ m: b4b81f2b.59754171.17dfc424.6b28aa27.f17c0c04.0cee6e43.64c5ec2b.482151d1
+
+VFNMSUBPS_xmm_src_dst ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101.81010101.81010101.81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMSUBPS_xmm_src_dst specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMSUBPS_xmm_src_dst rand
+ before
+r1: d2588598.182a085f.2ae05c72.3ca7542a.15dacc33.b1e8f8ee.c0a59422.0beffe1d
+r2: a7353550.7f7e7497.cdba2d21.fe93853b.840e9838.717bc9cb.[ NAN ].f1e39422
+r3: 919b29bf.2bfec2c5.dd3bb51c.cef7f987.98666b7e.e7341f88.fecd97fa.1709cf0b
+r4: ebd55f51.b7352d94.362d6f4f.c8df6c3a.ae2d4071.b09e34d1.97ade8b4.986d6b05
+ m: 1130d272.c0b0f3b1.b55dd7a6.0757997f.23ae157d.67454552.a7246adc.911c233b
+ after
+r1: d2588598.182a085f.2ae05c72.3ca7542a.15dacc33.b1e8f8ee.c0a59422.0beffe1d
+r2: a7353550.7f7e7497.cdba2d21.fe93853b.840e9838.717bc9cb.[ NAN ].f1e39422
+r3: 919b29bf.2bfec2c5.dd3bb51c.cef7f987.98666b7e.e7341f88.fecd97fa.1709cf0b
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].95dacc33.629b9a7e.[ NAN ].cad30f47
+ m: 1130d272.c0b0f3b1.b55dd7a6.0757997f.23ae157d.67454552.a7246adc.911c233b
+
+VFNMSUBPS_xmm_mem1 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101.81010101.81010101.81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMSUBPS_xmm_mem1 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ INF ].[ -INF ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMSUBPS_xmm_mem1 rand
+ before
+r1: 5ff87f8e.e1fa4dc7.34966a0e.a86c3d83.5136e60e.a8b68eb6.0aff985d.1d21b4da
+r2: 30796011.b79f7a83.90a6a371.c6291371.9511ad90.107c4aa9.9c0bee25.5989da0e
+r3: e2ff7367.dd2bb590.a557fdbc.7d9bd976.4c8b686f.3a23b6d9.3a12e81f.605f5002
+r4: d0d6b3fd.f02b399c.4f77f7dc.eacd49be.d0f01218.c3380ef0.bee10237.4fafd4e3
+ m: 56491d3d.8b2a4350.6ad00abc.28cb1f74.7e8ba7f5.47468d9a.0543b959.418620dc
+ after
+r1: 5ff87f8e.e1fa4dc7.34966a0e.a86c3d83.5136e60e.a8b68eb6.0aff985d.1d21b4da
+r2: 30796011.b79f7a83.90a6a371.c6291371.9511ad90.107c4aa9.9c0bee25.5989da0e
+r3: e2ff7367.dd2bb590.a557fdbc.7d9bd976.4c8b686f.3a23b6d9.3a12e81f.605f5002
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].fe8ba7f5.c7468d9a.16a09964.fa70800f
+ m: 56491d3d.8b2a4350.6ad00abc.28cb1f74.7e8ba7f5.47468d9a.0543b959.418620dc
+
+VFNMSUBPS_xmm_mem2 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101.81010101.81010101.81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMSUBPS_xmm_mem2 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ NAN ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMSUBPS_xmm_mem2 rand
+ before
+r1: cfa6ab95.4bb50e5b.d22fb347.54a219c5.b2aa2374.61d97084.eb068871.53eff01a
+r2: 99375b70.cb57d766.63606f6b.895df1dc.c89783ff.ad7ef35a.4cf4eb6b.a0f602c9
+r3: 0e492839.a79cda20.f92eb913.e40864e6.1c9fc204.c8c052c7.04da5f34.44a81014
+r4: 8c280e5e.7c115333.70670d2b.81b02e0f.0a0edcee.4d2cc878.ef855eb6.5c10d628
+ m: 6d1f094a.e6417d4c.a4d5e89f.7a600a82.ee30cd29.d94c9218.e8bf66df.043a1230
+ after
+r1: cfa6ab95.4bb50e5b.d22fb347.54a219c5.b2aa2374.61d97084.eb068871.53eff01a
+r2: 99375b70.cb57d766.63606f6b.895df1dc.c89783ff.ad7ef35a.4cf4eb6b.a0f602c9
+r3: 0e492839.a79cda20.f92eb913.e40864e6.1c9fc204.c8c052c7.04da5f34.44a81014
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].4b6166f5.e299afb8.ccf4eb6b.20f602c9
+ m: 6d1f094a.e6417d4c.a4d5e89f.7a600a82.ee30cd29.d94c9218.e8bf66df.043a1230
+
+VFNMSUBSD_xmm ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMSUBSD_xmm specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ -INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMSUBSD_xmm rand
+ before
+r1: 0f7c166980b89616.7145c55bed24b56c.2450922107afec54.cd54f29957327e59
+r2: cc893028e602d73e.b2831f4bf609ebf8.08bc254274de12d8.79127ed27105d7cf
+r3: 029353f1b5ac7f6f.455b745cb01a6853.f6be84f8bb673f4f.c8c387756fbfd9bd
+r4: 0be77b318842c856.059940783863e7a8.4aa3aaaf78d5b065.9635886e6d6a3f50
+ m: 44cea455fc4eef9f.ce09fd8da9f12525.60b794d448b4a0c8.be32fda98514c6b3
+ after
+r1: 0f7c166980b89616.7145c55bed24b56c.2450922107afec54.cd54f29957327e59
+r2: cc893028e602d73e.b2831f4bf609ebf8.08bc254274de12d8.79127ed27105d7cf
+r3: 029353f1b5ac7f6f.455b745cb01a6853.f6be84f8bb673f4f.c8c387756fbfd9bd
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ INF ]
+ m: 44cea455fc4eef9f.ce09fd8da9f12525.60b794d448b4a0c8.be32fda98514c6b3
+
+VFNMSUBSD_xmm_src_dst ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMSUBSD_xmm_src_dst specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ -INF ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMSUBSD_xmm_src_dst rand
+ before
+r1: 0a97cbc7ac5e30f5.7b7629851fcfdef3.94463cd1c7914d22.1e876212d6c92a13
+r2: b78debf535fec705.eaad3f4eb709cd41.419ca01490f7f11f.910033957a94279b
+r3: a8fb004a32b8ef7b.f67abbd38dacaf39.c504bb084073c96c.f268ed1e8d817879
+r4: 392f0631401ae502.7aa91a00bcc34007.7bcc8918719010b5.1f8d0a9a2b9cdad6
+ m: c773fa18fab0e446.5406d6c1605a3bd8.bf3e07b2c2da04a6.f33908f372f209e1
+ after
+r1: 0a97cbc7ac5e30f5.7b7629851fcfdef3.94463cd1c7914d22.1e876212d6c92a13
+r2: b78debf535fec705.eaad3f4eb709cd41.419ca01490f7f11f.910033957a94279b
+r3: a8fb004a32b8ef7b.f67abbd38dacaf39.c504bb084073c96c.f268ed1e8d817879
+r4: [ ZERO ].[ ZERO ].[ ZERO ].9e876212d6c92a13
+ m: c773fa18fab0e446.5406d6c1605a3bd8.bf3e07b2c2da04a6.f33908f372f209e1
+
+VFNMSUBSD_xmm_mem1 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMSUBSD_xmm_mem1 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMSUBSD_xmm_mem1 rand
+ before
+r1: ac14d76afd052af4.5e5d6d02967e5ed8.eca72f41cddddee9.493a63177b8ec0c3
+r2: 455d9993e4a5f1b8.76795aaf7a3a6332.6053ff312e26dd2d.ff5a95f0647cbcab
+r3: ee9c3c004c1c753e.762819b5269b0613.768d72ee82413c1c.ef651c6c49c9b9c3
+r4: 031cbc1bd0f7f431.3c3427feb9ab05a7.89a385e564b83663.f729737645807338
+ m: e02816510cc1a83d.a26aff774c781a19.f7df3280711908ad.f17116fa75aea535
+ after
+r1: ac14d76afd052af4.5e5d6d02967e5ed8.eca72f41cddddee9.493a63177b8ec0c3
+r2: 455d9993e4a5f1b8.76795aaf7a3a6332.6053ff312e26dd2d.ff5a95f0647cbcab
+r3: ee9c3c004c1c753e.762819b5269b0613.768d72ee82413c1c.ef651c6c49c9b9c3
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ -INF ]
+ m: e02816510cc1a83d.a26aff774c781a19.f7df3280711908ad.f17116fa75aea535
+
+VFNMSUBSD_xmm_mem2 ones
+ before
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+ after
+r1: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r2: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r3: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].8101010101010101
+ m: 0101010101010101.0101010101010101.0101010101010101.0101010101010101
+
+VFNMSUBSD_xmm_mem2 specialD
+ before
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ -INF ].[ INF ].bff0000000000000.3ff0000000000000
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+ after
+r1: bff0000000000000.3ff0000000000000.[ -ZERO ].[ ZERO ]
+r2: [ NAN ].[ NAN ].[ -INF ].[ INF ]
+r3: [ -ZERO ].[ ZERO ].[ -SUBNORMAL ].[ SUBNORMAL ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [ -SUBNORMAL ].[ SUBNORMAL ].[ NAN ].[ NAN ]
+
+VFNMSUBSD_xmm_mem2 rand
+ before
+r1: e10d450f9d06ce0f.86961d0dfe0e0295.1a8f772c44efeda7.ba0881e4f45d0ce7
+r2: 621745bf1e53a253.c283fdabe8787949.50fd4f567ac722fc.2fbc3120de9c6479
+r3: bf9212cf2c335fb5.33ff1b3c28c23a5e.f376b669ae2ce35a.2a57a09a50746818
+r4: 54caa9aa633342e0.b5d4f4aedaf80203.6146a9d07daa6c6a.88a64c3f65f3d5f0
+ m: 7d0a04bc5edd8780.25d002ec19278d62.f4b822f982cef9da.2674b1f93a24672c
+ after
+r1: e10d450f9d06ce0f.86961d0dfe0e0295.1a8f772c44efeda7.ba0881e4f45d0ce7
+r2: 621745bf1e53a253.c283fdabe8787949.50fd4f567ac722fc.2fbc3120de9c6479
+r3: bf9212cf2c335fb5.33ff1b3c28c23a5e.f376b669ae2ce35a.2a57a09a50746818
+r4: [ ZERO ].[ ZERO ].[ ZERO ].afbc3120de9c6479
+ m: 7d0a04bc5edd8780.25d002ec19278d62.f4b822f982cef9da.2674b1f93a24672c
+
+VFNMSUBSS_xmm ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMSUBSS_xmm specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMSUBSS_xmm rand
+ before
+r1: 95a02171.b9c06a42.5dbdc3e2.025a96a7.091a1f4f.5923c556.de8f49b6.eb14daf9
+r2: fad6fc35.116526d2.3a68b37d.b09eda00.fdb69b3e.9f350d8a.8dc29260.92cde983
+r3: 07f98f74.015af8db.989c4ca7.3ffe1597.2ad99232.f0910c21.0fd806e5.4e5e51f5
+r4: 1855d89a.262a1b0a.53270c4d.cc860398.edcf0197.e7c200c7.409e2430.38d0ce7b
+ m: 8836d113.1b62cd0b.48d36e5b.73435f30.a2e4e3d9.2054232a.fde0652d.6f311b42
+ after
+r1: 95a02171.b9c06a42.5dbdc3e2.025a96a7.091a1f4f.5923c556.de8f49b6.eb14daf9
+r2: fad6fc35.116526d2.3a68b37d.b09eda00.fdb69b3e.9f350d8a.8dc29260.92cde983
+r3: 07f98f74.015af8db.989c4ca7.3ffe1597.2ad99232.f0910c21.0fd806e5.4e5e51f5
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].6b14daf9
+ m: 8836d113.1b62cd0b.48d36e5b.73435f30.a2e4e3d9.2054232a.fde0652d.6f311b42
+
+VFNMSUBSS_xmm_src_dst ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMSUBSS_xmm_src_dst specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMSUBSS_xmm_src_dst rand
+ before
+r1: b5e8784c.7c8c4889.516eeebe.4f40e68b.a6643465.38d4b1f3.206a46c7.0c8cf676
+r2: fab6c9af.e737c931.4bc20861.7c8954d4.539af0a5.cbcde8d1.860844ed.2dee1843
+r3: b2edbeaa.f5ec8bae.129c392f.172a6438.06d41307.74cb026e.0b85da88.ee6240d4
+r4: 3bda55a8.4439ccad.82c8fc16.3b30d4e2.1b5c9af6.cf5b3c77.8baf8485.6af42855
+ m: f0c78914.70a9c6d9.7711cd01.05a75eff.ee7f7fdd.7908d297.e250bfd0.beb18ef3
+ after
+r1: b5e8784c.7c8c4889.516eeebe.4f40e68b.a6643465.38d4b1f3.206a46c7.0c8cf676
+r2: fab6c9af.e737c931.4bc20861.7c8954d4.539af0a5.cbcde8d1.860844ed.2dee1843
+r3: b2edbeaa.f5ec8bae.129c392f.172a6438.06d41307.74cb026e.0b85da88.ee6240d4
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].d96314a3
+ m: f0c78914.70a9c6d9.7711cd01.05a75eff.ee7f7fdd.7908d297.e250bfd0.beb18ef3
+
+VFNMSUBSS_xmm_mem1 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMSUBSS_xmm_mem1 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMSUBSS_xmm_mem1 rand
+ before
+r1: 2c00565c.14c9b5e0.cc4528dc.9099beba.db89c02a.0d5fff7b.ec350556.05a42bda
+r2: 4dd3b8eb.cc24d76b.5f2e8993.f914b241.3ec65948.28ea00ce.852ad401.5bd9be35
+r3: ad8bac2d.35466629.0b996d12.5b24f4bd.738244a3.6537113d.88fba7bf.dd5d0131
+r4: a9732d8e.ebbc9fc3.ac524f46.d3d3415d.d6087fa7.61d26d73.d373fa7b.a73bb1fa
+ m: 9ed8377b.8811bde8.1e25ab19.7c2f544b.c3a505c0.b746521e.41604a20.d37f8abb
+ after
+r1: 2c00565c.14c9b5e0.cc4528dc.9099beba.db89c02a.0d5fff7b.ec350556.05a42bda
+r2: 4dd3b8eb.cc24d76b.5f2e8993.f914b241.3ec65948.28ea00ce.852ad401.5bd9be35
+r3: ad8bac2d.35466629.0b996d12.5b24f4bd.738244a3.6537113d.88fba7bf.dd5d0131
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].79bbfa37
+ m: 9ed8377b.8811bde8.1e25ab19.7c2f544b.c3a505c0.b746521e.41604a20.d37f8abb
+
+VFNMSUBSS_xmm_mem2 ones
+ before
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+ after
+r1: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r2: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r3: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].81010101
+ m: 01010101.01010101.01010101.01010101.01010101.01010101.01010101.01010101
+
+VFNMSUBSS_xmm_mem2 specialF
+ before
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+ after
+r1: [ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ]
+r2: [ -INF ].[ INF ].bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ]
+r3: bf800000.3f800000.[-ZERO ].[ ZERO ].[-ZERO ].[ ZERO ].[ NAN ].[ NAN ]
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ NAN ]
+ m: [-ZERO ].[ ZERO ].[ NAN ].[ NAN ].[ -INF ].[ INF ].bf800000.3f800000
+
+VFNMSUBSS_xmm_mem2 rand
+ before
+r1: e606c65e.abd1fe42.3ddefd78.7344eab3.96a5d25b.031ff9e7.ae8c119c.[-SUBNR]
+r2: df49d6a4.ee899c7e.e449c250.d31cbfc2.ab54e2e2.e2e9a17d.f5c4cdda.c86ba5d7
+r3: e3ed64ba.edc4d347.f131748c.b8c58fa4.5efe32c3.f031858a.f4d4fac6.c72a608a
+r4: 4f3e6b0b.450ee14a.3f639117.3f4b1584.0aefbd68.c882e0ba.8688124d.9a8034e6
+ m: [ NAN ].91f40032.a9ab95df.84b80f8f.0d727f3f.0669eeba.87ac9259.5c78dc16
+ after
+r1: e606c65e.abd1fe42.3ddefd78.7344eab3.96a5d25b.031ff9e7.ae8c119c.[-SUBNR]
+r2: df49d6a4.ee899c7e.e449c250.d31cbfc2.ab54e2e2.e2e9a17d.f5c4cdda.c86ba5d7
+r3: e3ed64ba.edc4d347.f131748c.b8c58fa4.5efe32c3.f031858a.f4d4fac6.c72a608a
+r4: [ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].[ ZERO ].64259fff
+ m: [ NAN ].91f40032.a9ab95df.84b80f8f.0d727f3f.0669eeba.87ac9259.5c78dc16
+
diff --git a/none/tests/amd64/fma4.vgtest b/none/tests/amd64/fma4.vgtest
new file mode 100644
index 0000000..d1b0aa6
--- /dev/null
+++ b/none/tests/amd64/fma4.vgtest
@@ -0,0 +1,6 @@
+prog: fma4
+# The "correct" test includes ../../../tests/x86_amd64_features amd64-fma4
+# But since VEX just uses AVX instructions to implement the fma4 one, just
+# check that we could create the test binary and whether we have AVX.
+prereq: test -x fma4 && ../../../tests/x86_amd64_features amd64-avx
+vgopts: -q
diff --git a/none/tests/amd64/insn_fpu.def b/none/tests/amd64/insn_fpu.def
index c99815e..590f584 100644
--- a/none/tests/amd64/insn_fpu.def
+++ b/none/tests/amd64/insn_fpu.def
@@ -58,6 +58,18 @@
fiaddl st0.pd[-1234567.7654321] : m32.sd[87654321] => st0.pd[86419753.2345679]
fiaddl st0.pd[1234567.7654321] : m32.sd[-87654321] => st0.pd[-86419753.2345679]
fiaddl st0.pd[-1234567.7654321] : m32.sd[-87654321] => st0.pd[-88888888.7654321]
+fcoms st0.ps[1234.5678] : m32.ps[1234.5676] => st0.ps[1234.5678] fpusw[0x4700,0x0000]
+fcoms st0.ps[1234.5678] : m32.ps[1234.5679] => st0.ps[1234.5678] fpusw[0x4700,0x0100]
+fcoms st0.ps[1234.5678] : m32.ps[1234.5678] => st0.ps[1234.5678] fpusw[0x4700,0x4000]
+fcoml st0.pd[1234567.7654321] : m64.pd[1234567.7654320] => st0.pd[1234567.7654321] fpusw[0x4700,0x0000]
+fcoml st0.pd[1234567.7654321] : m64.pd[1234567.7654322] => st0.pd[1234567.7654321] fpusw[0x4700,0x0100]
+fcoml st0.pd[1234567.7654321] : m64.pd[1234567.7654321] => st0.pd[1234567.7654321] fpusw[0x4700,0x4000]
+fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5676] => st0.ps[8765.4321] fpusw[0x4700,0x0000]
+fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5679] => st0.ps[8765.4321] fpusw[0x4700,0x0100]
+fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5678] => st0.ps[8765.4321] fpusw[0x4700,0x4000]
+fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654320] => st0.pd[7654321.1234567] fpusw[0x4700,0x0000]
+fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654322] => st0.pd[7654321.1234567] fpusw[0x4700,0x0100]
+fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654321] => st0.pd[7654321.1234567] fpusw[0x4700,0x4000]
fcomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] eflags[0x45,0x00]
fcomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] eflags[0x45,0x01]
fcomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] eflags[0x45,0x40]
diff --git a/none/tests/amd64/insn_fpu.stdout.exp b/none/tests/amd64/insn_fpu.stdout.exp
index 2dbaa07..67128c1 100644
--- a/none/tests/amd64/insn_fpu.stdout.exp
+++ b/none/tests/amd64/insn_fpu.stdout.exp
@@ -58,6 +58,18 @@
fiaddl_6 ... ok
fiaddl_7 ... ok
fiaddl_8 ... ok
+fcoms_1 ... ok
+fcoms_2 ... ok
+fcoms_3 ... ok
+fcoml_1 ... ok
+fcoml_2 ... ok
+fcoml_3 ... ok
+fcomps_1 ... ok
+fcomps_2 ... ok
+fcomps_3 ... ok
+fcompl_1 ... ok
+fcompl_2 ... ok
+fcompl_3 ... ok
fcomi_1 ... ok
fcomi_2 ... ok
fcomi_3 ... ok
diff --git a/none/tests/amd64/pcmpstr64.c b/none/tests/amd64/pcmpstr64.c
index 0694012..a76ec55 100644
--- a/none/tests/amd64/pcmpstr64.c
+++ b/none/tests/amd64/pcmpstr64.c
@@ -203,10 +203,16 @@
even if they would probably work. Life is too short to have
unvalidated cases in the code base. */
switch (imm8) {
- case 0x00: case 0x02: case 0x08: case 0x0A: case 0x0C: case 0x0E:
- case 0x12: case 0x14: case 0x18: case 0x1A:
- case 0x30: case 0x34: case 0x38: case 0x3A:
- case 0x40: case 0x42: case 0x44: case 0x46: case 0x4A:
+ case 0x00: case 0x02:
+ case 0x08: case 0x0A: case 0x0C: case 0x0E:
+ case 0x12: case 0x14:
+ case 0x18: case 0x1A:
+ case 0x30: case 0x34:
+ case 0x38: case 0x3A:
+ case 0x40: case 0x42: case 0x44: case 0x46:
+ case 0x4A:
+ case 0x62:
+ case 0x70: case 0x72:
break;
default:
return False;
@@ -1971,6 +1977,246 @@
//////////////////////////////////////////////////////////
// //
+// ISTRI_70 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_70 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x70, %%xmm2, %%xmm11" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_70 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x70, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_70 ( void )
+{
+ char* wot = "70";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_70;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_70;
+
+ try_istri(wot,h,s, "abcdacbdabcdabcd", "000000000000000a");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000000b");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "00000000000000ab");
+ try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd");
+
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0bcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcda0cd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdab0d", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdabc0", "000000000000abcd");
+
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000a0cd");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000ab0d");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abc0");
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000bbbb");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000baba");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "00000000000baba0");
+
+ try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe");
+ try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe");
+}
+
+
+//////////////////////////////////////////////////////////
+// //
+// ISTRI_62 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_62 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x62, %%xmm2, %%xmm11" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_62 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x62, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_62 ( void )
+{
+ char* wot = "62";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_62;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_62;
+
+ try_istri(wot,h,s, "abcdacbdabcdabcd", "000000000000000a");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000000b");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "00000000000000ab");
+ try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd");
+
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0bcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcda0cd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdab0d", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdabc0", "000000000000abcd");
+
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000a0cd");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000ab0d");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abc0");
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000bbbb");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000baba");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "00000000000baba0");
+
+ try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe");
+ try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe");
+}
+
+
+//////////////////////////////////////////////////////////
+// //
+// ISTRI_72 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_72 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x72, %%xmm2, %%xmm11" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_72 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x72, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_72 ( void )
+{
+ char* wot = "72";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_72;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_72;
+
+ try_istri(wot,h,s, "abcdacbdabcdabcd", "000000000000000a");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000000b");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "00000000000000ab");
+ try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd");
+
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0bcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcda0cd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdab0d", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdabc0", "000000000000abcd");
+
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000a0cd");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000ab0d");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abc0");
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000bbbb");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000baba");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "00000000000baba0");
+
+ try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe");
+ try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe");
+}
+
+
+//////////////////////////////////////////////////////////
+// //
// main //
// //
//////////////////////////////////////////////////////////
@@ -1995,5 +2241,8 @@
istri_0E();
istri_14();
istri_34();
+ istri_70();
+ istri_62();
+ istri_72();
return 0;
}
diff --git a/none/tests/amd64/pcmpstr64.stdout.exp b/none/tests/amd64/pcmpstr64.stdout.exp
index 4921586..ae006e1 100644
--- a/none/tests/amd64/pcmpstr64.stdout.exp
+++ b/none/tests/amd64/pcmpstr64.stdout.exp
@@ -458,3 +458,69 @@
istri 34 fc937cbfbf53f8e2 0d136bcb024d3fb7 -> 08810000 08810000
istri 34 2ca34182c29a82ab 302ebd646775ab54 -> 08810000 08810000
istri 34 3f2987608c11be6f a9ecb661f8e0a8cb -> 08c10000 08c10000
+istri 70 abcdacbdabcdabcd 000000000000000a -> 0881000e 0881000e
+istri 70 abcdabcdabcdabcd 000000000000000b -> 0881000f 0881000f
+istri 70 abcdabcdabcdabcd 00000000000000ab -> 0881000d 0881000d
+istri 70 abcdabc0abcdabcd 000000000000abcd -> 00c00010 00c00010
+istri 70 abcdabcdabcdabcd 000000000000abcd -> 00800010 00800010
+istri 70 0bcdabcdabcdabcd 000000000000abcd -> 00c00010 00c00010
+istri 70 abcdabcdabcda0cd 000000000000abcd -> 00c00010 00c00010
+istri 70 abcdabcdabcdab0d 000000000000abcd -> 00c00010 00c00010
+istri 70 abcdabcdabcdabc0 000000000000abcd -> 00c00010 00c00010
+istri 70 abcdabcdabcdabcd 000000000000abcd -> 00800010 00800010
+istri 70 abcdabcdabcdabcd 000000000000a0cd -> 0081000f 0081000f
+istri 70 abcdabcdabcdabcd 000000000000ab0d -> 0081000f 0081000f
+istri 70 abcdabcdabcdabcd 000000000000abc0 -> 0881000f 0881000f
+istri 70 0000000000000000 0000000000000000 -> 00c00010 00c00010
+istri 70 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000010 00000010
+istri 70 0000abcdabcdabcd 000000000000abcd -> 00c00010 00c00010
+istri 70 0000abcdabcdabcd 000000000000dcba -> 00c00010 00c00010
+istri 70 0000abcdabcdabcd 000000000000bbbb -> 08c1000b 08c1000b
+istri 70 0000abcdabcdabcd 000000000000baba -> 08c10009 08c10009
+istri 70 0000abcdabcdabcd 00000000000baba0 -> 08c1000b 08c1000b
+istri 70 0ddc0ffeebadf00d 00000000cafebabe -> 08c10000 08c10000
+istri 70 0ddc0ffeebadfeed 00000000cafebabe -> 08c10004 08c10004
+istri 62 abcdacbdabcdabcd 000000000000000a -> 0081000f 0081000f
+istri 62 abcdabcdabcdabcd 000000000000000b -> 0081000e 0081000e
+istri 62 abcdabcdabcdabcd 00000000000000ab -> 0081000f 0081000f
+istri 62 abcdabc0abcdabcd 000000000000abcd -> 08c10007 08c10007
+istri 62 abcdabcdabcdabcd 000000000000abcd -> 0881000f 0881000f
+istri 62 0bcdabcdabcdabcd 000000000000abcd -> 08c1000e 08c1000e
+istri 62 abcdabcdabcda0cd 000000000000abcd -> 08c10001 08c10001
+istri 62 abcdabcdabcdab0d 000000000000abcd -> 08c10000 08c10000
+istri 62 abcdabcdabcdabc0 000000000000abcd -> 00c00010 00c00010
+istri 62 abcdabcdabcdabcd 000000000000abcd -> 0881000f 0881000f
+istri 62 abcdabcdabcdabcd 000000000000a0cd -> 0881000d 0881000d
+istri 62 abcdabcdabcdabcd 000000000000ab0d -> 0881000c 0881000c
+istri 62 abcdabcdabcdabcd 000000000000abc0 -> 00800010 00800010
+istri 62 0000000000000000 0000000000000000 -> 00c00010 00c00010
+istri 62 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 0801000f 0801000f
+istri 62 0000abcdabcdabcd 000000000000abcd -> 08c1000b 08c1000b
+istri 62 0000abcdabcdabcd 000000000000dcba -> 08c1000b 08c1000b
+istri 62 0000abcdabcdabcd 000000000000bbbb -> 00c1000a 00c1000a
+istri 62 0000abcdabcdabcd 000000000000baba -> 00c1000b 00c1000b
+istri 62 0000abcdabcdabcd 00000000000baba0 -> 00c00010 00c00010
+istri 62 0ddc0ffeebadf00d 00000000cafebabe -> 00c00010 00c00010
+istri 62 0ddc0ffeebadfeed 00000000cafebabe -> 00c1000a 00c1000a
+istri 72 abcdacbdabcdabcd 000000000000000a -> 0881000e 0881000e
+istri 72 abcdabcdabcdabcd 000000000000000b -> 0881000f 0881000f
+istri 72 abcdabcdabcdabcd 00000000000000ab -> 0881000d 0881000d
+istri 72 abcdabc0abcdabcd 000000000000abcd -> 00c00010 00c00010
+istri 72 abcdabcdabcdabcd 000000000000abcd -> 00800010 00800010
+istri 72 0bcdabcdabcdabcd 000000000000abcd -> 00c00010 00c00010
+istri 72 abcdabcdabcda0cd 000000000000abcd -> 00c00010 00c00010
+istri 72 abcdabcdabcdab0d 000000000000abcd -> 00c00010 00c00010
+istri 72 abcdabcdabcdabc0 000000000000abcd -> 00c00010 00c00010
+istri 72 abcdabcdabcdabcd 000000000000abcd -> 00800010 00800010
+istri 72 abcdabcdabcdabcd 000000000000a0cd -> 0081000f 0081000f
+istri 72 abcdabcdabcdabcd 000000000000ab0d -> 0081000f 0081000f
+istri 72 abcdabcdabcdabcd 000000000000abc0 -> 0881000f 0881000f
+istri 72 0000000000000000 0000000000000000 -> 00c00010 00c00010
+istri 72 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000010 00000010
+istri 72 0000abcdabcdabcd 000000000000abcd -> 00c00010 00c00010
+istri 72 0000abcdabcdabcd 000000000000dcba -> 00c00010 00c00010
+istri 72 0000abcdabcdabcd 000000000000bbbb -> 08c1000b 08c1000b
+istri 72 0000abcdabcdabcd 000000000000baba -> 08c10009 08c10009
+istri 72 0000abcdabcdabcd 00000000000baba0 -> 08c1000b 08c1000b
+istri 72 0ddc0ffeebadf00d 00000000cafebabe -> 08c10000 08c10000
+istri 72 0ddc0ffeebadfeed 00000000cafebabe -> 08c10004 08c10004
diff --git a/none/tests/amd64/pcmpstr64w.c b/none/tests/amd64/pcmpstr64w.c
index 858cfd8..6a1adad 100644
--- a/none/tests/amd64/pcmpstr64w.c
+++ b/none/tests/amd64/pcmpstr64w.c
@@ -209,7 +209,7 @@
unvalidated cases in the code base. */
switch (imm8) {
case 0x01: case 0x03: case 0x09: case 0x0B: case 0x0D:
- case 0x13: case 0x1B:
+ case 0x13: case 0x19: case 0x1B:
case 0x39: case 0x3B:
case 0x45: case 0x4B:
break;
@@ -1255,6 +1255,99 @@
//////////////////////////////////////////////////////////
// //
+// ISTRI_19 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_19 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x19, %%xmm2, %%xmm11" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_19 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK_wide( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x19, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_19 ( void )
+{
+ char* wot = "19";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_19;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_19;
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa00aa");
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaa00aa");
+
+ try_istri(wot,h,s, "aaaaaaaa00aaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa00aa");
+ try_istri(wot,h,s, "aaaaaaaa00aaaaaa", "aaaaaaaaaaaa00aa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaa00aaaaaa");
+
+ try_istri(wot,h,s, "0000000000000000", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "8000000000000000", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "0000000000000001", "aaaaaaaa00aaaaaa");
+
+ try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000");
+}
+
+
+
+//////////////////////////////////////////////////////////
+// //
// main //
// //
//////////////////////////////////////////////////////////
@@ -1271,5 +1364,6 @@
istri_45();
istri_01();
istri_39();
+ istri_19();
return 0;
}
diff --git a/none/tests/amd64/pcmpstr64w.stdout.exp b/none/tests/amd64/pcmpstr64w.stdout.exp
index 77d555d..c18184c 100644
--- a/none/tests/amd64/pcmpstr64w.stdout.exp
+++ b/none/tests/amd64/pcmpstr64w.stdout.exp
@@ -258,3 +258,33 @@
istri 39 0000000000000001 aaaaaaaa00aaaaaa -> 08c10000 08c10000
istri 39 0000000000000000 aaaaaaaaaaaaaaaa -> 00400008 00400008
istri 39 aaaaaaaaaaaaaaaa 0000000000000000 -> 08810000 08810000
+istri 19 0000000000000000 0000000000000000 -> 00c00008 00c00008
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 19 aaaa2aaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010005 00010005
+istri 19 aaaaaaaaa2aaaaaa aaaaaaaaaaaaaaaa -> 00010003 00010003
+istri 19 aaaaaaaaaaaaa2aa aaaaaaaaaaaaaaaa -> 00010001 00010001
+istri 19 aaaaaaaaaaaaaaaa aaaa2aaaaaaaaaaa -> 00010005 00010005
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaaa2aaaaaa -> 00010003 00010003
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaa2a -> 08010000 08010000
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 19 baaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010007 00010007
+istri 19 b9aaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010007 00010007
+istri 19 b9baaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010006 00010006
+istri 19 b9baaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010006 00010006
+istri 19 b9baaaaaaaaaaaaa aaaaaaaaaaaa7aaa -> 00010001 00010001
+istri 19 b9baaaaaaaaaaaaa aaaaaaaa2aaa4aaa -> 00010001 00010001
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 19 aaaaaaaaaaaa00aa aaaaaaaaaaaaaaaa -> 00410001 00410001
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaaaaaa00aa -> 00810001 00810001
+istri 19 aaaaaaaaaaaa00aa aaaaaaaaaaaa00aa -> 00c00008 00c00008
+istri 19 aaaaaaaa00aaaaaa aaaaaaaaaaaaaaaa -> 00410003 00410003
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaaaaaa00aa -> 00810001 00810001
+istri 19 aaaaaaaa00aaaaaa aaaaaaaaaaaa00aa -> 00c10001 00c10001
+istri 19 aaaaaaaaaaaa00aa aaaaaaaaaaaaaaaa -> 00410001 00410001
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaa00aaaaaa -> 00810003 00810003
+istri 19 aaaaaaaaaaaa00aa aaaaaaaa00aaaaaa -> 00c10001 00c10001
+istri 19 0000000000000000 aaaaaaaa00aaaaaa -> 08c10000 08c10000
+istri 19 8000000000000000 aaaaaaaa00aaaaaa -> 08c10000 08c10000
+istri 19 0000000000000001 aaaaaaaa00aaaaaa -> 08c10000 08c10000
+istri 19 0000000000000000 aaaaaaaaaaaaaaaa -> 08410000 08410000
+istri 19 aaaaaaaaaaaaaaaa 0000000000000000 -> 08810000 08810000
diff --git a/none/tests/amd64/x87trigOOR.c b/none/tests/amd64/x87trigOOR.c
deleted file mode 120000
index 64f32e6..0000000
--- a/none/tests/amd64/x87trigOOR.c
+++ /dev/null
@@ -1 +0,0 @@
-../x86/x87trigOOR.c
\ No newline at end of file
diff --git a/none/tests/amd64/x87trigOOR.c b/none/tests/amd64/x87trigOOR.c
new file mode 100644
index 0000000..0485559
--- /dev/null
+++ b/none/tests/amd64/x87trigOOR.c
@@ -0,0 +1,159 @@
+
+/* Tests out of range handling for FSIN, FCOS, FSINCOS and FPTAN. Be
+ careful with the inline assembly -- this program is compiled as
+ both a 32-bit and 64-bit test. */
+
+#include <stdio.h>
+#include <string.h>
+#include <assert.h>
+
+typedef unsigned short int UShort;
+typedef unsigned int UInt;
+typedef double Double;
+typedef unsigned long long int ULong;
+
+typedef struct { Double arg; Double st0; Double st1; UShort fpusw; } Res;
+
+#define SHIFT_C3 14
+#define SHIFT_C2 10
+#define SHIFT_C1 9
+#define SHIFT_C0 8
+
+
+#define my_offsetof(type,memb) ((int)(unsigned long int)&((type*)0)->memb)
+
+void do_fsin ( /*OUT*/Res* r, double d )
+{
+ assert(my_offsetof(Res,arg) == 0);
+ assert(my_offsetof(Res,st0) == 8);
+ assert(my_offsetof(Res,st1) == 16);
+ assert(my_offsetof(Res,fpusw) == 24);
+ memset(r, 0, sizeof(*r));
+ r->arg = d;
+ __asm__ __volatile__(
+ "finit" "\n\t"
+ "fldpi" "\n\t"
+ "fldl 0(%0)" "\n\t" // .arg
+ "fsin" "\n\t"
+ "fstsw %%ax" "\n\t"
+ "fstpl 8(%0)" "\n\t" // .st0
+ "fstpl 16(%0)" "\n\t" // .st1
+ "movw %%ax, 24(%0)" "\n\t" // .fpusw
+ "finit" "\n"
+ : : "r"(r) : "eax","cc","memory"
+ );
+}
+
+void do_fcos ( /*OUT*/Res* r, double d )
+{
+ assert(my_offsetof(Res,arg) == 0);
+ assert(my_offsetof(Res,st0) == 8);
+ assert(my_offsetof(Res,st1) == 16);
+ assert(my_offsetof(Res,fpusw) == 24);
+ memset(r, 0, sizeof(*r));
+ r->arg = d;
+ __asm__ __volatile__(
+ "finit" "\n\t"
+ "fldpi" "\n\t"
+ "fldl 0(%0)" "\n\t" // .arg
+ "fcos" "\n\t"
+ "fstsw %%ax" "\n\t"
+ "fstpl 8(%0)" "\n\t" // .st0
+ "fstpl 16(%0)" "\n\t" // .st1
+ "movw %%ax, 24(%0)" "\n\t" // .fpusw
+ "finit" "\n"
+ : : "r"(r) : "eax","cc","memory"
+ );
+}
+
+void do_fsincos ( /*OUT*/Res* r, double d )
+{
+ assert(my_offsetof(Res,arg) == 0);
+ assert(my_offsetof(Res,st0) == 8);
+ assert(my_offsetof(Res,st1) == 16);
+ assert(my_offsetof(Res,fpusw) == 24);
+ memset(r, 0, sizeof(*r));
+ r->arg = d;
+ __asm__ __volatile__(
+ "finit" "\n\t"
+ "fldpi" "\n\t"
+ "fldl 0(%0)" "\n\t" // .arg
+ "fsincos" "\n\t"
+ "fstsw %%ax" "\n\t"
+ "fstpl 8(%0)" "\n\t" // .st0
+ "fstpl 16(%0)" "\n\t" // .st1
+ "movw %%ax, 24(%0)" "\n\t" // .fpusw
+ "finit" "\n"
+ : : "r"(r) : "eax","cc","memory"
+ );
+}
+
+void do_fptan ( /*OUT*/Res* r, double d )
+{
+ assert(my_offsetof(Res,arg) == 0);
+ assert(my_offsetof(Res,st0) == 8);
+ assert(my_offsetof(Res,st1) == 16);
+ assert(my_offsetof(Res,fpusw) == 24);
+ memset(r, 0, sizeof(*r));
+ r->arg = d;
+ __asm__ __volatile__(
+ "finit" "\n\t"
+ "fldpi" "\n\t"
+ "fldl 0(%0)" "\n\t" // .arg
+ "fptan" "\n\t"
+ "fstsw %%ax" "\n\t"
+ "fstpl 8(%0)" "\n\t" // .st0
+ "fstpl 16(%0)" "\n\t" // .st1
+ "movw %%ax, 24(%0)" "\n\t" // .fpusw
+ "finit" "\n"
+ : : "r"(r) : "eax","cc","memory"
+ );
+}
+
+
+void try ( char* name, void(*fn)(Res*,double), double d )
+{
+ Res r;
+ fn(&r, d);
+ // Mask out all except C2 (range)
+ r.fpusw &= (1 << SHIFT_C2);
+ printf("%s %16e --> %16e %16e %04x\n",
+ name, r.arg, r.st0, r.st1, (UInt)r.fpusw);
+}
+
+int main ( void )
+{
+ Double limit = 9223372036854775808.0; // 2^63
+
+ char* names[4] = { "fsin ", "fcos ", "fsincos", "fptan " };
+ void(*fns[4])(Res*,double) = { do_fsin, do_fcos, do_fsincos, do_fptan };
+
+ int i;
+ for (i = 0; i < 4; i++) {
+ char* name = names[i];
+ void (*fn)(Res*,double) = fns[i];
+
+ try( name, fn, 0.0 );
+ try( name, fn, 0.123 );
+ try( name, fn, -0.456 );
+ try( name, fn, 37.0 );
+ try( name, fn, -53.0 );
+ printf("\n");
+
+ try( name, fn, limit * 0.900000 );
+ try( name, fn, limit * 0.999999 );
+ try( name, fn, limit * 1.000000 );
+ try( name, fn, limit * 1.000001 );
+ try( name, fn, limit * 1.100000 );
+ printf("\n");
+
+ try( name, fn, -limit * 0.900000 );
+ try( name, fn, -limit * 0.999999 );
+ try( name, fn, -limit * 1.000000 );
+ try( name, fn, -limit * 1.000001 );
+ try( name, fn, -limit * 1.100000 );
+ printf("\n");
+ }
+
+ return 0;
+}
diff --git a/none/tests/amd64/xacq_xrel.c b/none/tests/amd64/xacq_xrel.c
index 5f9fac0..24cdafa 100644
--- a/none/tests/amd64/xacq_xrel.c
+++ b/none/tests/amd64/xacq_xrel.c
@@ -168,7 +168,7 @@
"movabsq $0xffeeddccbbaa9988, %%rbx" "\n\t"
"xacquire lock cmpxchg8b (%0)" "\n\t"
"xrelease lock cmpxchg8b (%0)" "\n\t"
- : : "r"(&n) : "cc", "memory", "rax", "rdx", "rcx", "rdx"
+ : : "r"(&n) : "cc", "memory", "rax", "rbx", "rcx", "rdx"
);
printf("result for '%-3s' is %016llx\n", "cmpxchg8b", n);
}
diff --git a/none/tests/arm/Makefile.am b/none/tests/arm/Makefile.am
index 4507a20..7b10de8 100644
--- a/none/tests/arm/Makefile.am
+++ b/none/tests/arm/Makefile.am
@@ -12,6 +12,10 @@
v6intARM.stdout.exp v6intARM.stderr.exp v6intARM.vgtest \
v6intThumb.stdout.exp v6intThumb.stderr.exp v6intThumb.vgtest \
v6media.stdout.exp v6media.stderr.exp v6media.vgtest \
+ v8crypto_a.stdout.exp v8crypto_a.stderr.exp v8crypto_a.vgtest \
+ v8crypto_t.stdout.exp v8crypto_t.stderr.exp v8crypto_t.vgtest \
+ v8memory_a.stdout.exp v8memory_a.stderr.exp v8memory_a.vgtest \
+ v8memory_t.stdout.exp v8memory_t.stderr.exp v8memory_t.vgtest \
vcvt_fixed_float_VFP.stdout.exp vcvt_fixed_float_VFP.stderr.exp \
vcvt_fixed_float_VFP.vgtest \
vfp.stdout.exp vfp.stderr.exp vfp.vgtest \
@@ -27,6 +31,10 @@
v6intARM \
v6intThumb \
v6media \
+ v8crypto_a \
+ v8crypto_t \
+ v8memory_a \
+ v8memory_t \
vcvt_fixed_float_VFP \
vfp \
vfpv4_fma
@@ -49,6 +57,14 @@
v6media_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -mthumb
+v8crypto_a_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -marm
+v8crypto_t_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -mthumb
+
+v8memory_a_CFLAGS = $(AM_CFLAGS) -g -O0 \
+ -march=armv8-a -mfpu=crypto-neon-fp-armv8 -marm
+v8memory_t_CFLAGS = $(AM_CFLAGS) -g -O0 \
+ -march=armv8-a -mfpu=crypto-neon-fp-armv8 -mthumb
+
vfp_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
-mfpu=neon \
-mthumb
diff --git a/none/tests/arm/Makefile.in b/none/tests/arm/Makefile.in
new file mode 100644
index 0000000..86754f2
--- /dev/null
+++ b/none/tests/arm/Makefile.in
@@ -0,0 +1,1348 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+am__is_gnu_make = { \
+ if test -z '$(MAKELEVEL)'; then \
+ false; \
+ elif test -n '$(MAKE_HOST)'; then \
+ true; \
+ elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
+ true; \
+ else \
+ false; \
+ fi; \
+}
+am__make_running_with_option = \
+ case $${target_option-} in \
+ ?) ;; \
+ *) echo "am__make_running_with_option: internal error: invalid" \
+ "target option '$${target_option-}' specified" >&2; \
+ exit 1;; \
+ esac; \
+ has_opt=no; \
+ sane_makeflags=$$MAKEFLAGS; \
+ if $(am__is_gnu_make); then \
+ sane_makeflags=$$MFLAGS; \
+ else \
+ case $$MAKEFLAGS in \
+ *\\[\ \ ]*) \
+ bs=\\; \
+ sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
+ | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \
+ esac; \
+ fi; \
+ skip_next=no; \
+ strip_trailopt () \
+ { \
+ flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
+ }; \
+ for flg in $$sane_makeflags; do \
+ test $$skip_next = yes && { skip_next=no; continue; }; \
+ case $$flg in \
+ *=*|--*) continue;; \
+ -*I) strip_trailopt 'I'; skip_next=yes;; \
+ -*I?*) strip_trailopt 'I';; \
+ -*O) strip_trailopt 'O'; skip_next=yes;; \
+ -*O?*) strip_trailopt 'O';; \
+ -*l) strip_trailopt 'l'; skip_next=yes;; \
+ -*l?*) strip_trailopt 'l';; \
+ -[dEDm]) skip_next=yes;; \
+ -[JT]) skip_next=yes;; \
+ esac; \
+ case $$flg in \
+ *$$target_option*) has_opt=yes; break;; \
+ esac; \
+ done; \
+ test $$has_opt = yes
+am__make_dryrun = (target_option=n; $(am__make_running_with_option))
+am__make_keepgoing = (target_option=k; $(am__make_running_with_option))
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+@COMPILER_IS_CLANG_TRUE@am__append_1 = -Wno-cast-align -Wno-self-assign \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-compare
+
+@SOLARIS_XPG_SYMBOLS_PRESENT_TRUE@am__append_2 = -Wl,-M,$(top_srcdir)/solaris/vgpreload-solaris.mapfile
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_3 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+
+# Make sure that all test programs have threaded errno.
+# Disable largefile support as there are test cases explictly enabling it.
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
+@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
+@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-constant-out-of-range-compare \
+@COMPILER_IS_CLANG_TRUE@ -Wno-self-assign -Wno-string-plus-int \
+@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
+@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
+@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
+check_PROGRAMS = allexec$(EXEEXT) intdiv$(EXEEXT) ldrt$(EXEEXT) \
+ ldrt_arm$(EXEEXT) neon128$(EXEEXT) neon64$(EXEEXT) \
+ v6intARM$(EXEEXT) v6intThumb$(EXEEXT) v6media$(EXEEXT) \
+ v8crypto_a$(EXEEXT) v8crypto_t$(EXEEXT) v8memory_a$(EXEEXT) \
+ v8memory_t$(EXEEXT) vcvt_fixed_float_VFP$(EXEEXT) vfp$(EXEEXT) \
+ vfpv4_fma$(EXEEXT)
+subdir = none/tests/arm
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.ac
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+DIST_COMMON = $(srcdir)/Makefile.am $(dist_noinst_SCRIPTS) \
+ $(am__DIST_COMMON)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+allexec_SOURCES = allexec.c
+allexec_OBJECTS = allexec-allexec.$(OBJEXT)
+allexec_LDADD = $(LDADD)
+allexec_LINK = $(CCLD) $(allexec_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+intdiv_SOURCES = intdiv.c
+intdiv_OBJECTS = intdiv-intdiv.$(OBJEXT)
+intdiv_LDADD = $(LDADD)
+intdiv_LINK = $(CCLD) $(intdiv_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+ldrt_SOURCES = ldrt.c
+ldrt_OBJECTS = ldrt-ldrt.$(OBJEXT)
+ldrt_LDADD = $(LDADD)
+ldrt_LINK = $(CCLD) $(ldrt_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) \
+ -o $@
+ldrt_arm_SOURCES = ldrt_arm.c
+ldrt_arm_OBJECTS = ldrt_arm-ldrt_arm.$(OBJEXT)
+ldrt_arm_LDADD = $(LDADD)
+ldrt_arm_LINK = $(CCLD) $(ldrt_arm_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+neon128_SOURCES = neon128.c
+neon128_OBJECTS = neon128-neon128.$(OBJEXT)
+neon128_LDADD = $(LDADD)
+neon128_LINK = $(CCLD) $(neon128_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+neon64_SOURCES = neon64.c
+neon64_OBJECTS = neon64-neon64.$(OBJEXT)
+neon64_LDADD = $(LDADD)
+neon64_LINK = $(CCLD) $(neon64_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+v6intARM_SOURCES = v6intARM.c
+v6intARM_OBJECTS = v6intARM-v6intARM.$(OBJEXT)
+v6intARM_LDADD = $(LDADD)
+v6intARM_LINK = $(CCLD) $(v6intARM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+v6intThumb_SOURCES = v6intThumb.c
+v6intThumb_OBJECTS = v6intThumb-v6intThumb.$(OBJEXT)
+v6intThumb_LDADD = $(LDADD)
+v6intThumb_LINK = $(CCLD) $(v6intThumb_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+v6media_SOURCES = v6media.c
+v6media_OBJECTS = v6media-v6media.$(OBJEXT)
+v6media_LDADD = $(LDADD)
+v6media_LINK = $(CCLD) $(v6media_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+v8crypto_a_SOURCES = v8crypto_a.c
+v8crypto_a_OBJECTS = v8crypto_a-v8crypto_a.$(OBJEXT)
+v8crypto_a_LDADD = $(LDADD)
+v8crypto_a_LINK = $(CCLD) $(v8crypto_a_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+v8crypto_t_SOURCES = v8crypto_t.c
+v8crypto_t_OBJECTS = v8crypto_t-v8crypto_t.$(OBJEXT)
+v8crypto_t_LDADD = $(LDADD)
+v8crypto_t_LINK = $(CCLD) $(v8crypto_t_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+v8memory_a_SOURCES = v8memory_a.c
+v8memory_a_OBJECTS = v8memory_a-v8memory_a.$(OBJEXT)
+v8memory_a_LDADD = $(LDADD)
+v8memory_a_LINK = $(CCLD) $(v8memory_a_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+v8memory_t_SOURCES = v8memory_t.c
+v8memory_t_OBJECTS = v8memory_t-v8memory_t.$(OBJEXT)
+v8memory_t_LDADD = $(LDADD)
+v8memory_t_LINK = $(CCLD) $(v8memory_t_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+vcvt_fixed_float_VFP_SOURCES = vcvt_fixed_float_VFP.c
+vcvt_fixed_float_VFP_OBJECTS = vcvt_fixed_float_VFP.$(OBJEXT)
+vcvt_fixed_float_VFP_LDADD = $(LDADD)
+vfp_SOURCES = vfp.c
+vfp_OBJECTS = vfp-vfp.$(OBJEXT)
+vfp_LDADD = $(LDADD)
+vfp_LINK = $(CCLD) $(vfp_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o \
+ $@
+vfpv4_fma_SOURCES = vfpv4_fma.c
+vfpv4_fma_OBJECTS = vfpv4_fma-vfpv4_fma.$(OBJEXT)
+vfpv4_fma_LDADD = $(LDADD)
+vfpv4_fma_LINK = $(CCLD) $(vfpv4_fma_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+SCRIPTS = $(dist_noinst_SCRIPTS)
+AM_V_P = $(am__v_P_@AM_V@)
+am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
+am__v_P_0 = false
+am__v_P_1 = :
+AM_V_GEN = $(am__v_GEN_@AM_V@)
+am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@)
+am__v_GEN_0 = @echo " GEN " $@;
+am__v_GEN_1 =
+AM_V_at = $(am__v_at_@AM_V@)
+am__v_at_ = $(am__v_at_@AM_DEFAULT_V@)
+am__v_at_0 = @
+am__v_at_1 =
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+AM_V_lt = $(am__v_lt_@AM_V@)
+am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)
+am__v_lt_0 = --silent
+am__v_lt_1 =
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+AM_V_CC = $(am__v_CC_@AM_V@)
+am__v_CC_ = $(am__v_CC_@AM_DEFAULT_V@)
+am__v_CC_0 = @echo " CC " $@;
+am__v_CC_1 =
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+AM_V_CCLD = $(am__v_CCLD_@AM_V@)
+am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
+am__v_CCLD_0 = @echo " CCLD " $@;
+am__v_CCLD_1 =
+SOURCES = allexec.c intdiv.c ldrt.c ldrt_arm.c neon128.c neon64.c \
+ v6intARM.c v6intThumb.c v6media.c v8crypto_a.c v8crypto_t.c \
+ v8memory_a.c v8memory_t.c vcvt_fixed_float_VFP.c vfp.c \
+ vfpv4_fma.c
+DIST_SOURCES = allexec.c intdiv.c ldrt.c ldrt_arm.c neon128.c neon64.c \
+ v6intARM.c v6intThumb.c v6media.c v8crypto_a.c v8crypto_t.c \
+ v8memory_a.c v8memory_t.c vcvt_fixed_float_VFP.c vfp.c \
+ vfpv4_fma.c
+am__can_run_installinfo = \
+ case $$AM_UPDATE_INFO_DIR in \
+ n|no|NO) false;; \
+ *) (install-info --version) >/dev/null 2>&1;; \
+ esac
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+ BEGIN { nonempty = 0; } \
+ { items[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in items) print i; }; } \
+'
+# Make sure the list of sources is unique. This is necessary because,
+# e.g., the same source file might be shared among _SOURCES variables
+# for different programs/libraries.
+am__define_uniq_tagged_files = \
+ list='$(am__tagged_files)'; \
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+FLAG_OCTEON2 = @FLAG_OCTEON2@
+FLAG_T_TEXT = @FLAG_T_TEXT@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_CAST_ALIGN = @FLAG_W_CAST_ALIGN@
+FLAG_W_CAST_QUAL = @FLAG_W_CAST_QUAL@
+FLAG_W_EMPTY_BODY = @FLAG_W_EMPTY_BODY@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_FORMAT = @FLAG_W_FORMAT@
+FLAG_W_FORMAT_SECURITY = @FLAG_W_FORMAT_SECURITY@
+FLAG_W_FORMAT_SIGNEDNESS = @FLAG_W_FORMAT_SIGNEDNESS@
+FLAG_W_IGNORED_QUALIFIERS = @FLAG_W_IGNORED_QUALIFIERS@
+FLAG_W_MISSING_PARAMETER_TYPE = @FLAG_W_MISSING_PARAMETER_TYPE@
+FLAG_W_NO_INFINITE_RECURSION = @FLAG_W_NO_INFINITE_RECURSION@
+FLAG_W_NO_MEMSET_TRANSPOSED_ARGS = @FLAG_W_NO_MEMSET_TRANSPOSED_ARGS@
+FLAG_W_NO_MISMATCHED_NEW_DELETE = @FLAG_W_NO_MISMATCHED_NEW_DELETE@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_POINTER_SIGN = @FLAG_W_NO_POINTER_SIGN@
+FLAG_W_NO_STATIC_LOCAL_IN_INLINE = @FLAG_W_NO_STATIC_LOCAL_IN_INLINE@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+FLAG_W_NO_UNUSED_FUNCTION = @FLAG_W_NO_UNUSED_FUNCTION@
+FLAG_W_OLD_STYLE_DECLARATION = @FLAG_W_OLD_STYLE_DECLARATION@
+FLAG_W_WRITE_STRINGS = @FLAG_W_WRITE_STRINGS@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+HWCAP_HAS_ALTIVEC = @HWCAP_HAS_ALTIVEC@
+HWCAP_HAS_DFP = @HWCAP_HAS_DFP@
+HWCAP_HAS_HTM = @HWCAP_HAS_HTM@
+HWCAP_HAS_ISA_2_05 = @HWCAP_HAS_ISA_2_05@
+HWCAP_HAS_ISA_2_06 = @HWCAP_HAS_ISA_2_06@
+HWCAP_HAS_ISA_2_07 = @HWCAP_HAS_ISA_2_07@
+HWCAP_HAS_ISA_3_00 = @HWCAP_HAS_ISA_3_00@
+HWCAP_HAS_VSX = @HWCAP_HAS_VSX@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LIB_UBSAN = @LIB_UBSAN@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY_2 = @PREFERRED_STACK_BOUNDARY_2@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+SOLARIS_UNDEF_LARGESOURCE = @SOLARIS_UNDEF_LARGESOURCE@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+VG_TMPDIR = @VG_TMPDIR@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = -O2 -g -std=gnu99 -Wall -Wmissing-prototypes -Wshadow \
+ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \
+ @FLAG_W_CAST_ALIGN@ @FLAG_W_CAST_QUAL@ @FLAG_W_WRITE_STRINGS@ \
+ @FLAG_W_EMPTY_BODY@ @FLAG_W_FORMAT@ @FLAG_W_FORMAT_SIGNEDNESS@ \
+ @FLAG_W_FORMAT_SECURITY@ @FLAG_W_IGNORED_QUALIFIERS@ \
+ @FLAG_W_MISSING_PARAMETER_TYPE@ @FLAG_W_OLD_STYLE_DECLARATION@ \
+ @FLAG_FNO_STACK_PROTECTOR@ @FLAG_FSANITIZE@ \
+ -fno-strict-aliasing -fno-builtin $(am__append_1)
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fpic -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# These flags are used for building the preload shared objects (PSOs).
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads. Also, we must use any
+# -mpreferred-stack-boundary flag to build the preload shared
+# objects, since that risks misaligning the client's stack and
+# results in segfaults like (eg) #324050.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \
+@VGCONF_OS_IS_DARWIN_TRUE@ -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
+ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
+AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
+AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ @FLAG_M32@ $(am__empty)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) @FLAG_M32@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ intdiv.stdout.exp intdiv.stderr.exp intdiv.vgtest \
+ ldrt.stdout.exp ldrt.stderr.exp ldrt.vgtest \
+ ldrt_arm.stdout.exp ldrt_arm.stderr.exp ldrt_arm.vgtest \
+ neon128.stdout.exp neon128.stderr.exp neon128.vgtest \
+ neon64.stdout.exp neon64.stderr.exp neon64.vgtest \
+ v6intARM.stdout.exp v6intARM.stderr.exp v6intARM.vgtest \
+ v6intThumb.stdout.exp v6intThumb.stderr.exp v6intThumb.vgtest \
+ v6media.stdout.exp v6media.stderr.exp v6media.vgtest \
+ v8crypto_a.stdout.exp v8crypto_a.stderr.exp v8crypto_a.vgtest \
+ v8crypto_t.stdout.exp v8crypto_t.stderr.exp v8crypto_t.vgtest \
+ v8memory_a.stdout.exp v8memory_a.stderr.exp v8memory_a.vgtest \
+ v8memory_t.stdout.exp v8memory_t.stderr.exp v8memory_t.vgtest \
+ vcvt_fixed_float_VFP.stdout.exp vcvt_fixed_float_VFP.stderr.exp \
+ vcvt_fixed_float_VFP.vgtest \
+ vfp.stdout.exp vfp.stderr.exp vfp.vgtest \
+ vfpv4_fma.stdout.exp vfpv4_fma.stderr.exp vfpv4_fma.vgtest
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+
+# These two are specific to their ARM/Thumb respectively and so we
+# hardwire -marm/-mthumb. neon64 and neon128 are compilable on both,
+# however, ask for them to be compiled on thumb, as that looks
+# like that's going to be the more common use case. They also
+# need special helping w.r.t -mfpu and -mfloat-abi, though.
+# Also force -O0 since -O takes hundreds of MB of memory
+# for v6intThumb.c.
+v6intARM_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -marm
+v6intThumb_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -mthumb
+v6media_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -mthumb
+v8crypto_a_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -marm
+v8crypto_t_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -mthumb
+v8memory_a_CFLAGS = $(AM_CFLAGS) -g -O0 \
+ -march=armv8-a -mfpu=crypto-neon-fp-armv8 -marm
+
+v8memory_t_CFLAGS = $(AM_CFLAGS) -g -O0 \
+ -march=armv8-a -mfpu=crypto-neon-fp-armv8 -mthumb
+
+vfp_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
+ -mfpu=neon \
+ -mthumb
+
+neon128_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
+ -mfpu=neon \
+ -mthumb
+
+neon64_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
+ -mfpu=neon \
+ -mthumb
+
+intdiv_CFLAGS = $(AM_CFLAGS) -g -mcpu=cortex-a15 -mthumb
+ldrt_CFLAGS = $(AM_CFLAGS) -g -mcpu=cortex-a8 -mthumb
+ldrt_arm_CFLAGS = $(AM_CFLAGS) -g -mcpu=cortex-a8 -marm
+vfpv4_fma_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a15 -mfpu=vfpv4 -marm
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
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+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vfpv4_fma_CFLAGS) $(CFLAGS) -c -o vfpv4_fma-vfpv4_fma.o `test -f 'vfpv4_fma.c' || echo '$(srcdir)/'`vfpv4_fma.c
+
+vfpv4_fma-vfpv4_fma.obj: vfpv4_fma.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vfpv4_fma_CFLAGS) $(CFLAGS) -MT vfpv4_fma-vfpv4_fma.obj -MD -MP -MF $(DEPDIR)/vfpv4_fma-vfpv4_fma.Tpo -c -o vfpv4_fma-vfpv4_fma.obj `if test -f 'vfpv4_fma.c'; then $(CYGPATH_W) 'vfpv4_fma.c'; else $(CYGPATH_W) '$(srcdir)/vfpv4_fma.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/vfpv4_fma-vfpv4_fma.Tpo $(DEPDIR)/vfpv4_fma-vfpv4_fma.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='vfpv4_fma.c' object='vfpv4_fma-vfpv4_fma.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(vfpv4_fma_CFLAGS) $(CFLAGS) -c -o vfpv4_fma-vfpv4_fma.obj `if test -f 'vfpv4_fma.c'; then $(CYGPATH_W) 'vfpv4_fma.c'; else $(CYGPATH_W) '$(srcdir)/vfpv4_fma.c'; fi`
+
+ID: $(am__tagged_files)
+ $(am__define_uniq_tagged_files); mkid -fID $$unique
+tags: tags-am
+TAGS: tags
+
+tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+ set x; \
+ here=`pwd`; \
+ $(am__define_uniq_tagged_files); \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: ctags-am
+
+CTAGS: ctags
+ctags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+ $(am__define_uniq_tagged_files); \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+cscopelist: cscopelist-am
+
+cscopelist-am: $(am__tagged_files)
+ list='$(am__tagged_files)'; \
+ case "$(srcdir)" in \
+ [\\/]* | ?:[\\/]*) sdir="$(srcdir)" ;; \
+ *) sdir=$(subdir)/$(srcdir) ;; \
+ esac; \
+ for i in $$list; do \
+ if test -f "$$i"; then \
+ echo "$(subdir)/$$i"; \
+ else \
+ echo "$$sdir/$$i"; \
+ fi; \
+ done >> $(top_builddir)/cscope.files
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ if test -z '$(STRIP)'; then \
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ install; \
+ else \
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \
+ fi
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS TAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local cscopelist-am \
+ ctags ctags-am distclean distclean-compile distclean-generic \
+ distclean-tags distdir dvi dvi-am html html-am info info-am \
+ install install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-html \
+ install-html-am install-info install-info-am install-man \
+ install-pdf install-pdf-am install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ maintainer-clean maintainer-clean-generic mostlyclean \
+ mostlyclean-compile mostlyclean-generic pdf pdf-am ps ps-am \
+ tags tags-am uninstall uninstall-am
+
+.PRECIOUS: Makefile
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
+# It needs to be depended on by an 'uninstall-local' rule.
+uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
+uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/none/tests/arm/allexec.c b/none/tests/arm/allexec.c
deleted file mode 120000
index 6d6a9cf..0000000
--- a/none/tests/arm/allexec.c
+++ /dev/null
@@ -1 +0,0 @@
-../allexec.c
\ No newline at end of file
diff --git a/none/tests/allexec.c b/none/tests/arm/allexec.c
similarity index 100%
rename from none/tests/allexec.c
rename to none/tests/arm/allexec.c
diff --git a/none/tests/arm/v6intARM.c b/none/tests/arm/v6intARM.c
index 56675a9..8c615f6 100644
--- a/none/tests/arm/v6intARM.c
+++ b/none/tests/arm/v6intARM.c
@@ -13,8 +13,8 @@
\
__asm__ volatile( \
"movs %3,%3;" \
- "msrne cpsr_f,#(1<<29);" \
- "msreq cpsr_f,#0;" \
+ "msrne cpsr_fs,#(1<<29);" \
+ "msreq cpsr_fs,#0;" \
"mov " #RM ",%2;" \
/* set #RD to 0x55555555 so we can see which parts get overwritten */ \
"mov " #RD ", #0x55" "\n\t" \
@@ -30,7 +30,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, RMval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -45,8 +45,8 @@
\
__asm__ volatile( \
"movs %4,%4;" \
- "msrne cpsr_f,#(1<<29);" \
- "msreq cpsr_f,#0;" \
+ "msrne cpsr_fs,#(1<<29);" \
+ "msreq cpsr_fs,#0;" \
"mov " #RM ",%2;" \
"mov " #RN ",%3;" \
instruction ";" \
@@ -59,7 +59,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, RMval, RNval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -74,8 +74,8 @@
\
__asm__ volatile( \
"movs %5,%5;" \
- "msrne cpsr_f,#(1<<29);" \
- "msreq cpsr_f,#0;" \
+ "msrne cpsr_fs,#(1<<29);" \
+ "msreq cpsr_fs,#0;" \
"mov " #RM ",%2;" \
"mov " #RN ",%3;" \
"mov " #RS ",%4;" \
@@ -89,7 +89,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, RMval, RNval, RSval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -105,8 +105,8 @@
\
__asm__ volatile( \
"movs %7,%7;" \
- "msrne cpsr_f,#(1<<29);" \
- "msreq cpsr_f,#0;" \
+ "msrne cpsr_fs,#(1<<29);" \
+ "msreq cpsr_fs,#0;" \
"mov " #RD ",%3;" \
"mov " #RD2 ",%4;" \
"mov " #RM ",%5;" \
@@ -122,7 +122,7 @@
printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, out2, RMval, RSval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
diff --git a/none/tests/arm/v6intThumb.c b/none/tests/arm/v6intThumb.c
index 94336e6..e05b900 100644
--- a/none/tests/arm/v6intThumb.c
+++ b/none/tests/arm/v6intThumb.c
@@ -22,7 +22,7 @@
unsigned int cpsr; \
\
__asm__ volatile( \
- "msr cpsr_f, %2;" \
+ "msr cpsr_fs, %2;" \
instruction ";" \
"mov %0," #RD ";" \
"mrs %1,cpsr;" \
@@ -33,7 +33,7 @@
printf("%s :: rd 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -50,7 +50,7 @@
unsigned int cpsr; \
\
__asm__ volatile( \
- "msr cpsr_f, %2;" \
+ "msr cpsr_fs, %2;" \
"mov " #RD ",%3;" \
instruction ";" \
"mov %0," #RD ";" \
@@ -62,7 +62,7 @@
printf("%s :: rd 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -77,7 +77,7 @@
unsigned int cpsr; \
\
__asm__ volatile( \
- "msr cpsr_f, %3;" \
+ "msr cpsr_fs, %3;" \
"mov " #RM ",%2;" \
/* set #RD to 0x55555555 so we can see which parts get overwritten */ \
"mov " #RD ", #0x55" "\n\t" \
@@ -93,7 +93,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, RMval, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -109,7 +109,7 @@
unsigned int cpsr; \
\
__asm__ volatile( \
- "msr cpsr_f, %3;" \
+ "msr cpsr_fs, %3;" \
"mov " #RM ",%2;" \
"mov " #RD ",%4;" \
instruction ";" \
@@ -122,7 +122,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, RMval, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -138,7 +138,7 @@
unsigned int cpsr; \
\
__asm__ volatile( \
- "msr cpsr_f, %4;" \
+ "msr cpsr_fs, %4;" \
"mov " #RM ",%2;" \
"mov " #RN ",%3;" \
instruction ";" \
@@ -151,7 +151,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, RMval, RNval, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -165,7 +165,7 @@
unsigned int cpsr; \
\
__asm__ volatile( \
- "msr cpsr_f, %5;" \
+ "msr cpsr_fs, %5;" \
"mov " #RM ",%2;" \
"mov " #RN ",%3;" \
"mov " #RS ",%4;" \
@@ -179,7 +179,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, RMval, RNval, RSval, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -194,7 +194,7 @@
unsigned int cpsr; \
\
__asm__ volatile( \
- "msr cpsr_f, %7;" \
+ "msr cpsr_fs, %7;" \
"mov " #RD ",%3;" \
"mov " #RD2 ",%4;" \
"mov " #RM ",%5;" \
@@ -210,7 +210,7 @@
printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, out2, RMval, RSval, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -225,7 +225,7 @@
unsigned int cpsr; \
__asm__ volatile(\
".align 4;" \
- "msr cpsr_f, %2;" \
+ "msr cpsr_fs, %2;" \
"mov " #RD ", #0;" \
".align 2;" \
".thumb;" \
@@ -248,7 +248,7 @@
); \
printf("%s :: rd 0x%08x, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -264,7 +264,7 @@
unsigned int cpsr; \
__asm__ volatile(\
".align 4;" \
- "msr cpsr_f, %3;" \
+ "msr cpsr_fs, %3;" \
".align 2;" \
".thumb;" \
".syntax unified;" \
@@ -287,7 +287,7 @@
); \
printf("%s :: s0 0x%08x s1 0x%08x, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, out2, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -302,7 +302,7 @@
unsigned int cpsr; \
__asm__ volatile(\
".align 4;" \
- "msr cpsr_f, %3;" \
+ "msr cpsr_fs, %3;" \
"mov " #RD ", #0;" \
"mov " #RD2 ", #0;" \
".align 2;" \
@@ -327,7 +327,7 @@
); \
printf("%s :: rd 0x%08x rd2 0x%08x, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, out2, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -358,7 +358,7 @@
__asm__ volatile(
".thumb;\n"
".syntax unified ;\n"
- "msr cpsr_f, %3 ;\n"
+ "msr cpsr_fs, %3 ;\n"
"mov r9, %2 ;\n"
"movw r2, #:lower16:.ldrwpclabel1 ;\n"
"movt r2, #:upper16:.ldrwpclabel1 ;\n"
@@ -386,7 +386,7 @@
"cpsr 0x%08x %c%c%c%c\n", \
out, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
diff --git a/none/tests/arm/v6media.c b/none/tests/arm/v6media.c
index 44aba5d..af7a8df 100644
--- a/none/tests/arm/v6media.c
+++ b/none/tests/arm/v6media.c
@@ -7,7 +7,7 @@
#include <stdio.h>
-static int gen_cin(cin)
+static int gen_cin(int cin)
{
int r = ((cin & 1) ? (1<<29) : 0);
//r |= (1 << 31) | (1 << 30);
@@ -37,7 +37,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \
instruction, out, RMval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -66,7 +66,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \
instruction, out, RMval, RNval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -96,7 +96,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \
instruction, out, RMval, RNval, RSval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -129,7 +129,7 @@
printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \
instruction, out, out2, RMval, RSval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
diff --git a/none/tests/arm/v8crypto_a.c b/none/tests/arm/v8crypto_a.c
new file mode 100644
index 0000000..81a5ffa
--- /dev/null
+++ b/none/tests/arm/v8crypto_a.c
@@ -0,0 +1,255 @@
+
+/*
+gcc -o v8crypto v8crypto.c -march=armv8-a -mfpu=crypto-neon-fp-armv8
+gcc -o v8crypto v8crypto.c -mfpu=crypto-neon-fp-armv8
+*/
+
+#include <stdio.h>
+#include <assert.h>
+#include <malloc.h> // memalign
+#include <string.h> // memset
+#include "tests/malloc.h"
+#include <math.h> // isnormal
+
+typedef unsigned char UChar;
+typedef unsigned short int UShort;
+typedef unsigned int UInt;
+typedef signed int Int;
+typedef unsigned char UChar;
+typedef unsigned long long int ULong;
+typedef signed long long int Long;
+typedef double Double;
+typedef float Float;
+
+typedef unsigned char Bool;
+#define False ((Bool)0)
+#define True ((Bool)1)
+
+
+#define ITERS 1
+
+typedef
+ enum { TyHF=1234, TySF, TyDF, TyB, TyH, TyS, TyD, TyNONE }
+ LaneTy;
+
+union _V128 {
+ UChar u8[16];
+ UShort u16[8];
+ UInt u32[4];
+ ULong u64[2];
+ Float f32[4];
+ Double f64[2];
+};
+typedef union _V128 V128;
+
+static inline UChar randUChar ( void )
+{
+ static UInt seed = 80021;
+ seed = 1103515245 * seed + 12345;
+ return (seed >> 17) & 0xFF;
+}
+
+//static ULong randULong ( LaneTy ty )
+//{
+// Int i;
+// ULong r = 0;
+// for (i = 0; i < 8; i++) {
+// r = (r << 8) | (ULong)(0xFF & randUChar());
+// }
+// return r;
+//}
+
+/* Generates a random V128. Ensures that that it contains normalised
+ FP numbers when viewed as either F32x4 or F64x2, so that it is
+ reasonable to use in FP test cases. */
+static void randV128 ( /*OUT*/V128* v, LaneTy ty )
+{
+ static UInt nCalls = 0, nIters = 0;
+ Int i;
+ nCalls++;
+ while (1) {
+ nIters++;
+ for (i = 0; i < 16; i++) {
+ v->u8[i] = randUChar();
+ }
+ if (isnormal(v->f32[0]) && isnormal(v->f32[1]) && isnormal(v->f32[2])
+ && isnormal(v->f32[3]) && isnormal(v->f64[0]) && isnormal(v->f64[1]))
+ break;
+ }
+ if (0 == (nCalls & 0xFF))
+ printf("randV128: %u calls, %u iters\n", nCalls, nIters);
+}
+
+static void showV128 ( V128* v )
+{
+ Int i;
+ for (i = 15; i >= 0; i--)
+ printf("%02x", (Int)v->u8[i]);
+}
+
+//static void showBlock ( const char* msg, V128* block, Int nBlock )
+//{
+// Int i;
+// printf("%s\n", msg);
+// for (i = 0; i < nBlock; i++) {
+// printf(" ");
+// showV128(&block[i]);
+// printf("\n");
+// }
+//}
+
+
+/* ---------------------------------------------------------------- */
+/* -- Parameterisable test macros -- */
+/* ---------------------------------------------------------------- */
+
+#define DO50(_action) \
+ do { \
+ Int _qq; for (_qq = 0; _qq < 50; _qq++) { _action ; } \
+ } while (0)
+
+
+/* Generate a test that involves two vector regs,
+ with no bias as towards which is input or output.
+ It's OK to use r8 as scratch.*/
+#define GEN_TWOVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( LaneTy ty ) { \
+ Int i; \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[4+1]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ randV128(&block[2], ty); \
+ randV128(&block[3], ty); \
+ __asm__ __volatile__( \
+ "mov r9, #0 ; vmsr fpscr, r9 ; " \
+ "add r9, %0, #0 ; vld1.8 { q"#VECREG1NO" }, [r9] ; " \
+ "add r9, %0, #16 ; vld1.8 { q"#VECREG2NO" }, [r9] ; " \
+ INSN " ; " \
+ "add r9, %0, #32 ; vst1.8 { q"#VECREG1NO" }, [r9] ; " \
+ "add r9, %0, #48 ; vst1.8 { q"#VECREG2NO" }, [r9] ; " \
+ "vmrs r9, fpscr ; str r9, [%0, #64] " \
+ : : "r"(&block[0]) \
+ : "cc", "memory", "q"#VECREG1NO, "q"#VECREG2NO, "r8", "r9" \
+ ); \
+ printf(INSN " "); \
+ UInt fpscr = 0xFFFFFFFF & block[4].u32[0]; \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf(" fpscr=%08x\n", fpscr); \
+ } \
+ }
+
+
+/* Generate a test that involves three vector regs,
+ with no bias as towards which is input or output. It's also OK
+ to use r8 scratch. */
+#define GEN_THREEVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO,VECREG3NO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( LaneTy ty ) { \
+ Int i; \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[6+1]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ randV128(&block[2], ty); \
+ randV128(&block[3], ty); \
+ randV128(&block[4], ty); \
+ randV128(&block[5], ty); \
+ __asm__ __volatile__( \
+ "mov r9, #0 ; vmsr fpscr, r9 ; " \
+ "add r9, %0, #0 ; vld1.8 { q"#VECREG1NO" }, [r9] ; " \
+ "add r9, %0, #16 ; vld1.8 { q"#VECREG2NO" }, [r9] ; " \
+ "add r9, %0, #32 ; vld1.8 { q"#VECREG3NO" }, [r9] ; " \
+ INSN " ; " \
+ "add r9, %0, #48 ; vst1.8 { q"#VECREG1NO" }, [r9] ; " \
+ "add r9, %0, #64 ; vst1.8 { q"#VECREG2NO" }, [r9] ; " \
+ "add r9, %0, #80 ; vst1.8 { q"#VECREG3NO" }, [r9] ; " \
+ "vmrs r9, fpscr ; str r9, [%0, #96] " \
+ : : "r"(&block[0]) \
+ : "cc", "memory", "q"#VECREG1NO, "q"#VECREG2NO, "q"#VECREG3NO, \
+ "r8", "r9" \
+ ); \
+ printf(INSN " "); \
+ UInt fpscr = 0xFFFFFFFF & block[6].u32[0]; \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf(" "); \
+ showV128(&block[4]); printf(" "); \
+ showV128(&block[5]); printf(" fpscr=%08x\n", fpscr); \
+ } \
+ }
+
+// ======================== CRYPTO ========================
+
+GEN_TWOVEC_TEST(aesd_q_q, "aesd.8 q3, q4", 3, 4)
+GEN_TWOVEC_TEST(aese_q_q, "aese.8 q12, q13", 12, 13)
+GEN_TWOVEC_TEST(aesimc_q_q, "aesimc.8 q15, q0", 15, 0)
+GEN_TWOVEC_TEST(aesmc_q_q, "aesmc.8 q1, q9", 1, 9)
+
+GEN_THREEVEC_TEST(sha1c_q_q_q, "sha1c.32 q11, q10, q2", 11, 10, 2)
+GEN_TWOVEC_TEST(sha1h_q_q, "sha1h.32 q6, q7", 6, 7)
+GEN_THREEVEC_TEST(sha1m_q_q_q, "sha1m.32 q2, q8, q13", 2, 8, 13)
+GEN_THREEVEC_TEST(sha1p_q_q_q, "sha1p.32 q3, q9, q14", 3, 9, 14)
+GEN_THREEVEC_TEST(sha1su0_q_q_q, "sha1su0.32 q4, q10, q15", 4, 10, 15)
+GEN_TWOVEC_TEST(sha1su1_q_q, "sha1su1.32 q11, q2", 11, 2)
+
+GEN_THREEVEC_TEST(sha256h2_q_q_q, "sha256h2.32 q9, q8, q7", 9, 8, 7)
+GEN_THREEVEC_TEST(sha256h_q_q_q, "sha256h.32 q10, q9, q8", 10, 9, 8)
+GEN_TWOVEC_TEST(sha256su0_q_q, "sha256su0.32 q11, q10", 11, 10)
+GEN_THREEVEC_TEST(sha256su1_q_q_q, "sha256su1.32 q12, q11, q10", 12, 11, 10)
+
+// This is a bit complex. This really mentions three registers, so it
+// should really be a THREEVEC variant. But the two source registers
+// are D registers. So we say it is just a TWOVEC insn, producing a Q
+// and taking a single Q (q7); q7 is the d14-d15 register pair, which
+// is why the insn itself is mentions d14 and d15 whereas the
+// numbers that follow mention q7. The result (q7) is 128 bits wide and
+// so is unaffected by these shenanigans.
+GEN_TWOVEC_TEST(pmull_q_d_d, "vmull.p64 q13, d14, d15", 13, 7)
+
+int main ( void )
+{
+ // ======================== CRYPTO ========================
+
+ // aesd.8 q_q (aes single round decryption)
+ // aese.8 q_q (aes single round encryption)
+ // aesimc.8 q_q (aes inverse mix columns)
+ // aesmc.8 q_q (aes mix columns)
+ if (1) DO50( test_aesd_q_q(TyNONE) );
+ if (1) DO50( test_aese_q_q(TyNONE) );
+ if (1) DO50( test_aesimc_q_q(TyNONE) );
+ if (1) DO50( test_aesmc_q_q(TyNONE) );
+
+ // sha1c.32 q_q_q
+ // sha1h.32 q_q
+ // sha1m.32 q_q_q
+ // sha1p.32 q_q_q
+ // sha1su0.32 q_q_q
+ // sha1su1.32 q_q
+ if (1) DO50( test_sha1c_q_q_q(TyNONE) );
+ if (1) DO50( test_sha1h_q_q(TyNONE) );
+ if (1) DO50( test_sha1m_q_q_q(TyNONE) );
+ if (1) DO50( test_sha1p_q_q_q(TyNONE) );
+ if (1) DO50( test_sha1su0_q_q_q(TyNONE) );
+ if (1) DO50( test_sha1su1_q_q(TyNONE) );
+
+ // sha256h2.32 q_q_q
+ // sha256h.32 q_q_q
+ // sha256su0.32 q_q
+ // sha256su1.32 q_q_q
+ if (1) DO50( test_sha256h2_q_q_q(TyNONE) );
+ if (1) DO50( test_sha256h_q_q_q(TyNONE) );
+ if (1) DO50( test_sha256su0_q_q(TyNONE) );
+ if (1) DO50( test_sha256su1_q_q_q(TyNONE) );
+
+ // vmull.64 q_d_d
+ if (1) DO50( test_pmull_q_d_d(TyD) );
+
+ return 0;
+}
diff --git a/none/tests/arm/v8crypto_a.stderr.exp b/none/tests/arm/v8crypto_a.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/arm/v8crypto_a.stderr.exp
diff --git a/none/tests/arm/v8crypto_a.stdout.exp b/none/tests/arm/v8crypto_a.stdout.exp
new file mode 100644
index 0000000..d1df49c
--- /dev/null
+++ b/none/tests/arm/v8crypto_a.stdout.exp
@@ -0,0 +1,764 @@
+aesd.8 q3, q4 5175e39d19c9ca1e98f24a4984175700 7d6528c5fa956a0d69c3e9a6af27d13b 0b2e475e420871824d7cdc612ba75949 7d6528c5fa956a0d69c3e9a6af27d13b fpscr=00000000
+aesd.8 q3, q4 19a348215c3a67fd399182c2dbcc2d38 065d77195d623e6b842adc6450659e17 cefe1576cbb79d35090c4bc5cd5e254e 065d77195d623e6b842adc6450659e17 fpscr=00000000
+aesd.8 q3, q4 f9dd4a29f8c093db56b01a12b0ca1583 5ff85bc9535c191fd3a727d1a705f65d 8787cfa0c55f8b880ec24d33671ce39c 5ff85bc9535c191fd3a727d1a705f65d fpscr=00000000
+aesd.8 q3, q4 d182c916cebc2e17cfaff39be272ef40 6897b536bbe4da8a369dab4f9465b86e 0fa1ba54db875e753f2fda19695e01c3 6897b536bbe4da8a369dab4f9465b86e fpscr=00000000
+aesd.8 q3, q4 81f2a547be8d181184ededbc53239dcf 019963bf7459630b8d69483df7e8c6a9 1d4f03e13a592943100557914019c7d3 019963bf7459630b8d69483df7e8c6a9 fpscr=00000000
+aesd.8 q3, q4 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 708971e54d4a5bee2651524c4d73e17d 0a5f45c55f1c9202b76ddefcb0ebfe6e fpscr=00000000
+aesd.8 q3, q4 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 7ebee36ccf2be6e3b221fcaa201aec63 63483da65c8c49d096084deb9ed0411e fpscr=00000000
+aesd.8 q3, q4 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 03af402bb4e5954d1a01ee34dd79fb66 ecb42ac54b0966d4089b756aa3f77018 fpscr=00000000
+aesd.8 q3, q4 8404eb7f0cf4ca6fee8536da9dbf68bc ff6f850f2c57ea2a2c810e6dc1a1833d a73054d003e9766854053c20a8714591 ff6f850f2c57ea2a2c810e6dc1a1833d fpscr=00000000
+aesd.8 q3, q4 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 297777a9c72ee6de5f10eeecc2112f74 f078b65e01737fd22bfa8f668c8b14f4 fpscr=00000000
+aesd.8 q3, q4 c5e48064a393c8e947a34273c10a3c47 6ec34f98a2199d3c810bdacfab80ee3d 586fed550ecfe2b5093d7f78c7cf5fbd 6ec34f98a2199d3c810bdacfab80ee3d fpscr=00000000
+aesd.8 q3, q4 b984aed62671e865e6f21d40fc7bc013 5d0f926ce1157eaa95c45b338afcb3df 0f2435c0aeea985f31ce8f8f8f8c6d27 5d0f926ce1157eaa95c45b338afcb3df fpscr=00000000
+aesd.8 q3, q4 acb722146c6cbfa9ea4a022e1d3d7dbb 048612e51a468e36c51cdd8f87e12ab4 37b92e2b6f93ef6e0f2edaf14e9508fb 048612e51a468e36c51cdd8f87e12ab4 fpscr=00000000
+aesd.8 q3, q4 80ddba7e53e42d123208cf9b04b0569c 4288ae612c0dad40f0733f448390351b ea033acba85417486bed00efa8eb9bea 4288ae612c0dad40f0733f448390351b fpscr=00000000
+aesd.8 q3, q4 14575775bc3a12029d8e66ea90352a18 f9754842f9c9ba28f82a63b15c68b274 271d6fb2538d36956894e257bc7ecbb8 f9754842f9c9ba28f82a63b15c68b274 fpscr=00000000
+aesd.8 q3, q4 4784d95987cd4ed80c3ca578a32bd88e 08aebee85fda964fbba02737f3c98220 6c1c2d56923b11852d95469220870abe 08aebee85fda964fbba02737f3c98220 fpscr=00000000
+aesd.8 q3, q4 fbc4208894fdc0f55f706da71bf2425f 4e92f1b240a122141a366d352714867e 6d983ba2d2f552e019b9887468a7517b 4e92f1b240a122141a366d352714867e fpscr=00000000
+aesd.8 q3, q4 0e780c65c22b4ab8778d9ed6d9eb46ea ac82c1007a7d3cd8f54b130cdaa89cef d5c70fbc1a64b4909a147a7a11b98036 ac82c1007a7d3cd8f54b130cdaa89cef fpscr=00000000
+aesd.8 q3, q4 61ff7d4df3b6ca8131f01866bd76c58f 02dd0e32eecfc5fa2c3ffa1aebe6a4d2 b95ffb6b00963b03de94d801deaf8f8d 02dd0e32eecfc5fa2c3ffa1aebe6a4d2 fpscr=00000000
+aesd.8 q3, q4 d4ba52a206ff21b170fbbab6a7f19faf 3004b7a97cf69dda9f7301c1392d8087 df97789eae93fe05bd5acb0261402aee 3004b7a97cf69dda9f7301c1392d8087 fpscr=00000000
+aesd.8 q3, q4 47086cc3da642fa7130d662777beb4a9 16559ec50352a3d92d460a61a5dd0f6f 7fccf0a57000b88ae58dfe98d12404c7 16559ec50352a3d92d460a61a5dd0f6f fpscr=00000000
+aesd.8 q3, q4 9a49ac115048d4c4f987fa170d3ce4dd 9432a2e46543b956b819f459105730e9 dedfb377d705d774d90319b6f89ed728 9432a2e46543b956b819f459105730e9 fpscr=00000000
+aesd.8 q3, q4 adddf0eb4808f06704c857e949cc0fac 89fba268812abdb21e4a9e0958fac555 e3116541a62412b5122310a043944869 89fba268812abdb21e4a9e0958fac555 fpscr=00000000
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+randV128: 768 calls, 793 iters
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+randV128: 1024 calls, 1056 iters
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+randV128: 1792 calls, 1843 iters
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+randV128: 2560 calls, 2639 iters
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+randV128: 2816 calls, 2905 iters
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+randV128: 3584 calls, 3699 iters
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+vmull.p64 q13, d14, d15 d384cd518929e2387c136cc3c41570ee 7a791cc22258550b79be1ff6470d35ca 15e85b45dac8ce3b536a167102c2320e 7a791cc22258550b79be1ff6470d35ca fpscr=00000000
+vmull.p64 q13, d14, d15 fc8bb01edfacdf8ac25fc5383270090d 5c212178108f417431a96bc9774a7e25 0e3d2037f99d0518a83c2b858efa3224 5c212178108f417431a96bc9774a7e25 fpscr=00000000
diff --git a/none/tests/arm/v8crypto_a.vgtest b/none/tests/arm/v8crypto_a.vgtest
new file mode 100644
index 0000000..e32317a
--- /dev/null
+++ b/none/tests/arm/v8crypto_a.vgtest
@@ -0,0 +1,2 @@
+prog: v8crypto_a
+vgopts: -q
diff --git a/none/tests/arm/v8crypto_t.c b/none/tests/arm/v8crypto_t.c
new file mode 100644
index 0000000..81a5ffa
--- /dev/null
+++ b/none/tests/arm/v8crypto_t.c
@@ -0,0 +1,255 @@
+
+/*
+gcc -o v8crypto v8crypto.c -march=armv8-a -mfpu=crypto-neon-fp-armv8
+gcc -o v8crypto v8crypto.c -mfpu=crypto-neon-fp-armv8
+*/
+
+#include <stdio.h>
+#include <assert.h>
+#include <malloc.h> // memalign
+#include <string.h> // memset
+#include "tests/malloc.h"
+#include <math.h> // isnormal
+
+typedef unsigned char UChar;
+typedef unsigned short int UShort;
+typedef unsigned int UInt;
+typedef signed int Int;
+typedef unsigned char UChar;
+typedef unsigned long long int ULong;
+typedef signed long long int Long;
+typedef double Double;
+typedef float Float;
+
+typedef unsigned char Bool;
+#define False ((Bool)0)
+#define True ((Bool)1)
+
+
+#define ITERS 1
+
+typedef
+ enum { TyHF=1234, TySF, TyDF, TyB, TyH, TyS, TyD, TyNONE }
+ LaneTy;
+
+union _V128 {
+ UChar u8[16];
+ UShort u16[8];
+ UInt u32[4];
+ ULong u64[2];
+ Float f32[4];
+ Double f64[2];
+};
+typedef union _V128 V128;
+
+static inline UChar randUChar ( void )
+{
+ static UInt seed = 80021;
+ seed = 1103515245 * seed + 12345;
+ return (seed >> 17) & 0xFF;
+}
+
+//static ULong randULong ( LaneTy ty )
+//{
+// Int i;
+// ULong r = 0;
+// for (i = 0; i < 8; i++) {
+// r = (r << 8) | (ULong)(0xFF & randUChar());
+// }
+// return r;
+//}
+
+/* Generates a random V128. Ensures that that it contains normalised
+ FP numbers when viewed as either F32x4 or F64x2, so that it is
+ reasonable to use in FP test cases. */
+static void randV128 ( /*OUT*/V128* v, LaneTy ty )
+{
+ static UInt nCalls = 0, nIters = 0;
+ Int i;
+ nCalls++;
+ while (1) {
+ nIters++;
+ for (i = 0; i < 16; i++) {
+ v->u8[i] = randUChar();
+ }
+ if (isnormal(v->f32[0]) && isnormal(v->f32[1]) && isnormal(v->f32[2])
+ && isnormal(v->f32[3]) && isnormal(v->f64[0]) && isnormal(v->f64[1]))
+ break;
+ }
+ if (0 == (nCalls & 0xFF))
+ printf("randV128: %u calls, %u iters\n", nCalls, nIters);
+}
+
+static void showV128 ( V128* v )
+{
+ Int i;
+ for (i = 15; i >= 0; i--)
+ printf("%02x", (Int)v->u8[i]);
+}
+
+//static void showBlock ( const char* msg, V128* block, Int nBlock )
+//{
+// Int i;
+// printf("%s\n", msg);
+// for (i = 0; i < nBlock; i++) {
+// printf(" ");
+// showV128(&block[i]);
+// printf("\n");
+// }
+//}
+
+
+/* ---------------------------------------------------------------- */
+/* -- Parameterisable test macros -- */
+/* ---------------------------------------------------------------- */
+
+#define DO50(_action) \
+ do { \
+ Int _qq; for (_qq = 0; _qq < 50; _qq++) { _action ; } \
+ } while (0)
+
+
+/* Generate a test that involves two vector regs,
+ with no bias as towards which is input or output.
+ It's OK to use r8 as scratch.*/
+#define GEN_TWOVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( LaneTy ty ) { \
+ Int i; \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[4+1]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ randV128(&block[2], ty); \
+ randV128(&block[3], ty); \
+ __asm__ __volatile__( \
+ "mov r9, #0 ; vmsr fpscr, r9 ; " \
+ "add r9, %0, #0 ; vld1.8 { q"#VECREG1NO" }, [r9] ; " \
+ "add r9, %0, #16 ; vld1.8 { q"#VECREG2NO" }, [r9] ; " \
+ INSN " ; " \
+ "add r9, %0, #32 ; vst1.8 { q"#VECREG1NO" }, [r9] ; " \
+ "add r9, %0, #48 ; vst1.8 { q"#VECREG2NO" }, [r9] ; " \
+ "vmrs r9, fpscr ; str r9, [%0, #64] " \
+ : : "r"(&block[0]) \
+ : "cc", "memory", "q"#VECREG1NO, "q"#VECREG2NO, "r8", "r9" \
+ ); \
+ printf(INSN " "); \
+ UInt fpscr = 0xFFFFFFFF & block[4].u32[0]; \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf(" fpscr=%08x\n", fpscr); \
+ } \
+ }
+
+
+/* Generate a test that involves three vector regs,
+ with no bias as towards which is input or output. It's also OK
+ to use r8 scratch. */
+#define GEN_THREEVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO,VECREG3NO) \
+ __attribute__((noinline)) \
+ static void test_##TESTNAME ( LaneTy ty ) { \
+ Int i; \
+ for (i = 0; i < ITERS; i++) { \
+ V128 block[6+1]; \
+ memset(block, 0x55, sizeof(block)); \
+ randV128(&block[0], ty); \
+ randV128(&block[1], ty); \
+ randV128(&block[2], ty); \
+ randV128(&block[3], ty); \
+ randV128(&block[4], ty); \
+ randV128(&block[5], ty); \
+ __asm__ __volatile__( \
+ "mov r9, #0 ; vmsr fpscr, r9 ; " \
+ "add r9, %0, #0 ; vld1.8 { q"#VECREG1NO" }, [r9] ; " \
+ "add r9, %0, #16 ; vld1.8 { q"#VECREG2NO" }, [r9] ; " \
+ "add r9, %0, #32 ; vld1.8 { q"#VECREG3NO" }, [r9] ; " \
+ INSN " ; " \
+ "add r9, %0, #48 ; vst1.8 { q"#VECREG1NO" }, [r9] ; " \
+ "add r9, %0, #64 ; vst1.8 { q"#VECREG2NO" }, [r9] ; " \
+ "add r9, %0, #80 ; vst1.8 { q"#VECREG3NO" }, [r9] ; " \
+ "vmrs r9, fpscr ; str r9, [%0, #96] " \
+ : : "r"(&block[0]) \
+ : "cc", "memory", "q"#VECREG1NO, "q"#VECREG2NO, "q"#VECREG3NO, \
+ "r8", "r9" \
+ ); \
+ printf(INSN " "); \
+ UInt fpscr = 0xFFFFFFFF & block[6].u32[0]; \
+ showV128(&block[0]); printf(" "); \
+ showV128(&block[1]); printf(" "); \
+ showV128(&block[2]); printf(" "); \
+ showV128(&block[3]); printf(" "); \
+ showV128(&block[4]); printf(" "); \
+ showV128(&block[5]); printf(" fpscr=%08x\n", fpscr); \
+ } \
+ }
+
+// ======================== CRYPTO ========================
+
+GEN_TWOVEC_TEST(aesd_q_q, "aesd.8 q3, q4", 3, 4)
+GEN_TWOVEC_TEST(aese_q_q, "aese.8 q12, q13", 12, 13)
+GEN_TWOVEC_TEST(aesimc_q_q, "aesimc.8 q15, q0", 15, 0)
+GEN_TWOVEC_TEST(aesmc_q_q, "aesmc.8 q1, q9", 1, 9)
+
+GEN_THREEVEC_TEST(sha1c_q_q_q, "sha1c.32 q11, q10, q2", 11, 10, 2)
+GEN_TWOVEC_TEST(sha1h_q_q, "sha1h.32 q6, q7", 6, 7)
+GEN_THREEVEC_TEST(sha1m_q_q_q, "sha1m.32 q2, q8, q13", 2, 8, 13)
+GEN_THREEVEC_TEST(sha1p_q_q_q, "sha1p.32 q3, q9, q14", 3, 9, 14)
+GEN_THREEVEC_TEST(sha1su0_q_q_q, "sha1su0.32 q4, q10, q15", 4, 10, 15)
+GEN_TWOVEC_TEST(sha1su1_q_q, "sha1su1.32 q11, q2", 11, 2)
+
+GEN_THREEVEC_TEST(sha256h2_q_q_q, "sha256h2.32 q9, q8, q7", 9, 8, 7)
+GEN_THREEVEC_TEST(sha256h_q_q_q, "sha256h.32 q10, q9, q8", 10, 9, 8)
+GEN_TWOVEC_TEST(sha256su0_q_q, "sha256su0.32 q11, q10", 11, 10)
+GEN_THREEVEC_TEST(sha256su1_q_q_q, "sha256su1.32 q12, q11, q10", 12, 11, 10)
+
+// This is a bit complex. This really mentions three registers, so it
+// should really be a THREEVEC variant. But the two source registers
+// are D registers. So we say it is just a TWOVEC insn, producing a Q
+// and taking a single Q (q7); q7 is the d14-d15 register pair, which
+// is why the insn itself is mentions d14 and d15 whereas the
+// numbers that follow mention q7. The result (q7) is 128 bits wide and
+// so is unaffected by these shenanigans.
+GEN_TWOVEC_TEST(pmull_q_d_d, "vmull.p64 q13, d14, d15", 13, 7)
+
+int main ( void )
+{
+ // ======================== CRYPTO ========================
+
+ // aesd.8 q_q (aes single round decryption)
+ // aese.8 q_q (aes single round encryption)
+ // aesimc.8 q_q (aes inverse mix columns)
+ // aesmc.8 q_q (aes mix columns)
+ if (1) DO50( test_aesd_q_q(TyNONE) );
+ if (1) DO50( test_aese_q_q(TyNONE) );
+ if (1) DO50( test_aesimc_q_q(TyNONE) );
+ if (1) DO50( test_aesmc_q_q(TyNONE) );
+
+ // sha1c.32 q_q_q
+ // sha1h.32 q_q
+ // sha1m.32 q_q_q
+ // sha1p.32 q_q_q
+ // sha1su0.32 q_q_q
+ // sha1su1.32 q_q
+ if (1) DO50( test_sha1c_q_q_q(TyNONE) );
+ if (1) DO50( test_sha1h_q_q(TyNONE) );
+ if (1) DO50( test_sha1m_q_q_q(TyNONE) );
+ if (1) DO50( test_sha1p_q_q_q(TyNONE) );
+ if (1) DO50( test_sha1su0_q_q_q(TyNONE) );
+ if (1) DO50( test_sha1su1_q_q(TyNONE) );
+
+ // sha256h2.32 q_q_q
+ // sha256h.32 q_q_q
+ // sha256su0.32 q_q
+ // sha256su1.32 q_q_q
+ if (1) DO50( test_sha256h2_q_q_q(TyNONE) );
+ if (1) DO50( test_sha256h_q_q_q(TyNONE) );
+ if (1) DO50( test_sha256su0_q_q(TyNONE) );
+ if (1) DO50( test_sha256su1_q_q_q(TyNONE) );
+
+ // vmull.64 q_d_d
+ if (1) DO50( test_pmull_q_d_d(TyD) );
+
+ return 0;
+}
diff --git a/none/tests/arm/v8crypto_t.stderr.exp b/none/tests/arm/v8crypto_t.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/arm/v8crypto_t.stderr.exp
diff --git a/none/tests/arm/v8crypto_t.stdout.exp b/none/tests/arm/v8crypto_t.stdout.exp
new file mode 100644
index 0000000..d1df49c
--- /dev/null
+++ b/none/tests/arm/v8crypto_t.stdout.exp
@@ -0,0 +1,764 @@
+aesd.8 q3, q4 5175e39d19c9ca1e98f24a4984175700 7d6528c5fa956a0d69c3e9a6af27d13b 0b2e475e420871824d7cdc612ba75949 7d6528c5fa956a0d69c3e9a6af27d13b fpscr=00000000
+aesd.8 q3, q4 19a348215c3a67fd399182c2dbcc2d38 065d77195d623e6b842adc6450659e17 cefe1576cbb79d35090c4bc5cd5e254e 065d77195d623e6b842adc6450659e17 fpscr=00000000
+aesd.8 q3, q4 f9dd4a29f8c093db56b01a12b0ca1583 5ff85bc9535c191fd3a727d1a705f65d 8787cfa0c55f8b880ec24d33671ce39c 5ff85bc9535c191fd3a727d1a705f65d fpscr=00000000
+aesd.8 q3, q4 d182c916cebc2e17cfaff39be272ef40 6897b536bbe4da8a369dab4f9465b86e 0fa1ba54db875e753f2fda19695e01c3 6897b536bbe4da8a369dab4f9465b86e fpscr=00000000
+aesd.8 q3, q4 81f2a547be8d181184ededbc53239dcf 019963bf7459630b8d69483df7e8c6a9 1d4f03e13a592943100557914019c7d3 019963bf7459630b8d69483df7e8c6a9 fpscr=00000000
+aesd.8 q3, q4 e98ebd1ca893312a54cae7d5e13dfe91 0a5f45c55f1c9202b76ddefcb0ebfe6e 708971e54d4a5bee2651524c4d73e17d 0a5f45c55f1c9202b76ddefcb0ebfe6e fpscr=00000000
+aesd.8 q3, q4 e9b5f3f66b2e58c121a6c3476d21f1e5 63483da65c8c49d096084deb9ed0411e 7ebee36ccf2be6e3b221fcaa201aec63 63483da65c8c49d096084deb9ed0411e fpscr=00000000
+aesd.8 q3, q4 61c82534e9bf6f37c9e25f72d82e582b ecb42ac54b0966d4089b756aa3f77018 03af402bb4e5954d1a01ee34dd79fb66 ecb42ac54b0966d4089b756aa3f77018 fpscr=00000000
+aesd.8 q3, q4 8404eb7f0cf4ca6fee8536da9dbf68bc ff6f850f2c57ea2a2c810e6dc1a1833d a73054d003e9766854053c20a8714591 ff6f850f2c57ea2a2c810e6dc1a1833d fpscr=00000000
+aesd.8 q3, q4 36b2a38dcef18acf0e0f01a829ba3c66 f078b65e01737fd22bfa8f668c8b14f4 297777a9c72ee6de5f10eeecc2112f74 f078b65e01737fd22bfa8f668c8b14f4 fpscr=00000000
+aesd.8 q3, q4 c5e48064a393c8e947a34273c10a3c47 6ec34f98a2199d3c810bdacfab80ee3d 586fed550ecfe2b5093d7f78c7cf5fbd 6ec34f98a2199d3c810bdacfab80ee3d fpscr=00000000
+aesd.8 q3, q4 b984aed62671e865e6f21d40fc7bc013 5d0f926ce1157eaa95c45b338afcb3df 0f2435c0aeea985f31ce8f8f8f8c6d27 5d0f926ce1157eaa95c45b338afcb3df fpscr=00000000
+aesd.8 q3, q4 acb722146c6cbfa9ea4a022e1d3d7dbb 048612e51a468e36c51cdd8f87e12ab4 37b92e2b6f93ef6e0f2edaf14e9508fb 048612e51a468e36c51cdd8f87e12ab4 fpscr=00000000
+aesd.8 q3, q4 80ddba7e53e42d123208cf9b04b0569c 4288ae612c0dad40f0733f448390351b ea033acba85417486bed00efa8eb9bea 4288ae612c0dad40f0733f448390351b fpscr=00000000
+aesd.8 q3, q4 14575775bc3a12029d8e66ea90352a18 f9754842f9c9ba28f82a63b15c68b274 271d6fb2538d36956894e257bc7ecbb8 f9754842f9c9ba28f82a63b15c68b274 fpscr=00000000
+aesd.8 q3, q4 4784d95987cd4ed80c3ca578a32bd88e 08aebee85fda964fbba02737f3c98220 6c1c2d56923b11852d95469220870abe 08aebee85fda964fbba02737f3c98220 fpscr=00000000
+aesd.8 q3, q4 fbc4208894fdc0f55f706da71bf2425f 4e92f1b240a122141a366d352714867e 6d983ba2d2f552e019b9887468a7517b 4e92f1b240a122141a366d352714867e fpscr=00000000
+aesd.8 q3, q4 0e780c65c22b4ab8778d9ed6d9eb46ea ac82c1007a7d3cd8f54b130cdaa89cef d5c70fbc1a64b4909a147a7a11b98036 ac82c1007a7d3cd8f54b130cdaa89cef fpscr=00000000
+aesd.8 q3, q4 61ff7d4df3b6ca8131f01866bd76c58f 02dd0e32eecfc5fa2c3ffa1aebe6a4d2 b95ffb6b00963b03de94d801deaf8f8d 02dd0e32eecfc5fa2c3ffa1aebe6a4d2 fpscr=00000000
+aesd.8 q3, q4 d4ba52a206ff21b170fbbab6a7f19faf 3004b7a97cf69dda9f7301c1392d8087 df97789eae93fe05bd5acb0261402aee 3004b7a97cf69dda9f7301c1392d8087 fpscr=00000000
+aesd.8 q3, q4 47086cc3da642fa7130d662777beb4a9 16559ec50352a3d92d460a61a5dd0f6f 7fccf0a57000b88ae58dfe98d12404c7 16559ec50352a3d92d460a61a5dd0f6f fpscr=00000000
+aesd.8 q3, q4 9a49ac115048d4c4f987fa170d3ce4dd 9432a2e46543b956b819f459105730e9 dedfb377d705d774d90319b6f89ed728 9432a2e46543b956b819f459105730e9 fpscr=00000000
+aesd.8 q3, q4 adddf0eb4808f06704c857e949cc0fac 89fba268812abdb21e4a9e0958fac555 e3116541a62412b5122310a043944869 89fba268812abdb21e4a9e0958fac555 fpscr=00000000
+aesd.8 q3, q4 5f2619b1a20662f012305efa0acd1475 d70f7fb13667914c413cead25e27ac14 fd817e5297bbc678e74c9aee50d8d3d8 d70f7fb13667914c413cead25e27ac14 fpscr=00000000
+aesd.8 q3, q4 918107c43ea20cc00420edac31a0d599 5cce191e65591384ff4cb613013cc685 08b8cb7a801c5786579282f46363e9c4 5cce191e65591384ff4cb613013cc685 fpscr=00000000
+aesd.8 q3, q4 24509983fc3bcc36baf7e45e9fa43077 fa99500fef6024ba39dce32c239cf309 780bc8f09c7638f08212331e4157128a fa99500fef6024ba39dce32c239cf309 fpscr=00000000
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+aesd.8 q3, q4 e8c72e865de41295f2db8f44cbbf37e2 fcd015ff8f2e73a3a0fae06860b606c7 0e7bd8af9b4006247f872e42481049c2 fcd015ff8f2e73a3a0fae06860b606c7 fpscr=00000000
+aesd.8 q3, q4 da30ef8bc0b5573e34a901384a97a32f 20fd62bd65b571158e48704b3c31abc2 0fe0232414c52c0b2980bf8fc052b453 20fd62bd65b571158e48704b3c31abc2 fpscr=00000000
+aesd.8 q3, q4 ac8dd5bbc503330eb9dd5dab8e212ab7 ddb5cd8016d27d057796e0861576e44f e8ccb6492cdacd9ea976ecfaec5134e1 ddb5cd8016d27d057796e0861576e44f fpscr=00000000
+aesd.8 q3, q4 3d3cc0784c2f856363d9810079bbabd9 125934a781e479d33d431279cce48fce d23755ef4e8422fc80bca6af9d59ba87 125934a781e479d33d431279cce48fce fpscr=00000000
+aesd.8 q3, q4 6f9f902235982fa010fd4e94e9c808f5 9e477892854b43e0beafe48541dc8da0 6f48b8fc2b9b6272fc2d67e3bea9c8ed 9e477892854b43e0beafe48541dc8da0 fpscr=00000000
+aesd.8 q3, q4 20162517609f0f22a1a7a4c9c0a51f6b 63e279a20368bc8bdb3b370954bcbf24 e71c4bd2648e22b700ba471fbd26a792 63e279a20368bc8bdb3b370954bcbf24 fpscr=00000000
+aesd.8 q3, q4 31005fb9ada2074bf63a63fedcb4d29c 3f871736dc9ac5357446eb65e4e703bb 7601a873d750978a2cea51e81176d43d 3f871736dc9ac5357446eb65e4e703bb fpscr=00000000
+aesd.8 q3, q4 83bd1e68fb03f57bef136b941e54ffe8 139832afee423c3d6930e0fad3ba39c4 803212319699ce982fc2c745dcf84242 139832afee423c3d6930e0fad3ba39c4 fpscr=00000000
+aesd.8 q3, q4 f4ad41832c22ba116c949cea66e687ae 2ced5f927f2b383caf8484c5f3078d2a ad7c11e32de034fa5072a34e3340e94f 2ced5f927f2b383caf8484c5f3078d2a fpscr=00000000
+aesd.8 q3, q4 e309aef8a605af130821eb96e737777e b5a9377eb31749ef710cf757885d2728 06faf5dcb958c4552f476cddaf39f9b9 b5a9377eb31749ef710cf757885d2728 fpscr=00000000
+aesd.8 q3, q4 dbacfa35b7d2b75af8ad6b99bb3fa4c2 c673c91ec9aed3f8b9c3e32f2103009d 37458c0bde6d971a8aef1d79f8016684 c673c91ec9aed3f8b9c3e32f2103009d fpscr=00000000
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+aesd.8 q3, q4 2ad7482a960fb2b27014160ebbdb47e4 a7837c83faf3cb1d360794fec60222d6 1382afb7b4e5111bb8fdbc17985528a1 a7837c83faf3cb1d360794fec60222d6 fpscr=00000000
+aesd.8 q3, q4 5e86033374552e23ce8e2455e0205c58 37885d08d662faf92a541ab7911c2b5a 2c7a1949e46dd17a1ad7023baeb29d6a 37885d08d662faf92a541ab7911c2b5a fpscr=00000000
+aesd.8 q3, q4 19714a711ce1284318b88425f2de758f 0760c299b42e1fdcc2e9e9cf82c7aff8 d070b2c8e98eb36e6fe37abb7a5f9702 0760c299b42e1fdcc2e9e9cf82c7aff8 fpscr=00000000
+aesd.8 q3, q4 3cf6fe426e1281712ef114ddd37570e8 f76b8d9773b81b24de24e0a879648e11 62b537b559e3baedde750c3f17628f69 f76b8d9773b81b24de24e0a879648e11 fpscr=00000000
+aesd.8 q3, q4 a77700084a491a0ef099b6dd61462ec3 e70a9c61f55fce335d68e1a25652a804 b22b19e4729bda8bf413dc6b18ff1c31 e70a9c61f55fce335d68e1a25652a804 fpscr=00000000
+aesd.8 q3, q4 3a542e238fe5d1793d1148867eb08f81 b79cd058188318692112ca1cf9f1dd31 ead51203b4f8117c85b14837c4d30cfc b79cd058188318692112ca1cf9f1dd31 fpscr=00000000
+aesd.8 q3, q4 d4ec68f21f468712f7b8ab3708137382 478209dbbd84d92508847c7642a20df9 5c6d9d4c22560db21a458af87da8d803 478209dbbd84d92508847c7642a20df9 fpscr=00000000
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+aesd.8 q3, q4 a1cd852d9cd970502d146432e64644c9 25c80a060da03fb0c33ebc4b44b8ddd8 1a95920b4f0c2da0ac36f9af99af73e3 25c80a060da03fb0c33ebc4b44b8ddd8 fpscr=00000000
+aesd.8 q3, q4 94d7265949ca62b46a8a793cf9d5f0d1 35e7926e777aa43f56470887bfdd3daf 9880c7b2f1bf2cced10880fe6dfcc68a 35e7926e777aa43f56470887bfdd3daf fpscr=00000000
+aesd.8 q3, q4 84db9fe3e4b100d48d969e225f9318a0 04b4378bce1492e08680a7399beeae16 88ff74f73a135b28950679449e296f79 04b4378bce1492e08680a7399beeae16 fpscr=00000000
+aese.8 q12, q13 f30110c432a534d0478d5d7e053a4e0c 2e467d8e98e7468c75a0cbeda561e618 acd8c2d623393c4ae0a040dcc12c90fa 2e467d8e98e7468c75a0cbeda561e618 fpscr=00000000
+aese.8 q12, q13 62bbc77143b71e92668b24fb9133bf52 9fedb2229a090d2c018b42f3d3ec8415 3563e2ed859e9dae2cb17d3054ae33a0 9fedb2229a090d2c018b42f3d3ec8415 fpscr=00000000
+aese.8 q12, q13 894d9fe1f98d1aa0861ef69cf4e34e11 f2789356f1fb0d2b99885af4db13d1b7 3090dba9c08cfe3d1596f04521389124 f2789356f1fb0d2b99885af4db13d1b7 fpscr=00000000
+aese.8 q12, q13 74876ac63afb7562c67d2c86fa7c09a3 07121ecd88441b7dd2cc3eca9347d80f 37c83e2bfae292c0f92a9f298f08c991 07121ecd88441b7dd2cc3eca9347d80f fpscr=00000000
+aese.8 q12, q13 077815d35567232e66c997070e860c39 109cfa471afbe686e2ede96f8809f947 8436e6225f73dfc24469a645f0def3f3 109cfa471afbe686e2ede96f8809f947 fpscr=00000000
+aese.8 q12, q13 89ad76dc21a1f8f15acd7ad9f991bada c201829797974fddfe5d063c8be33ce1 4e6044b34940bf714091a9d9b30510e2 c201829797974fddfe5d063c8be33ce1 fpscr=00000000
+aese.8 q12, q13 fba1981add7938e3067d74917c37833e f82db3448c8c9a654f1c8c8db3b639e1 d1eff4583b0cf1448a643a9c7be6419e f82db3448c8c9a654f1c8c8db3b639e1 fpscr=00000000
+aese.8 q12, q13 9cdd1a32cd007ff7daac12cf3a64acbd e76fcc086aeb0414a9cd126c0869c6a0 5cef02808fd7f6112337210a21e963a4 e76fcc086aeb0414a9cd126c0869c6a0 fpscr=00000000
+aese.8 q12, q13 8514e93e478d067a5a4ac156a6cb98bf d4442998096825896787a06c436d8e39 2fbd47242724ba0dd9532680d1d9ef44 d4442998096825896787a06c436d8e39 fpscr=00000000
+aese.8 q12, q13 95a6e59e2a7fabcb65b86284a1cb27a3 a20cab554a62dd2468a718ec4422710c d0c0b11fd71e2fdfd9ac38459aa4da79 a20cab554a62dd2468a718ec4422710c fpscr=00000000
+aese.8 q12, q13 aef4eeb358364f4add55d3bb09c439c9 3028339e0d3a0c468e8f584ceae94e7a fc57f5d8edd8c1fe11861a680bfe3d6d 3028339e0d3a0c468e8f584ceae94e7a fpscr=00000000
+aese.8 q12, q13 af5de4ddb013d258a082f55bbf17ae91 5df79fd3324f914fb79f41ec172107e2 13a4d3abf00521f0c2ac1aa9894a8d8f 5df79fd3324f914fb79f41ec172107e2 fpscr=00000000
+aese.8 q12, q13 7742a77a117513548f9ea7c3a323665c 0bd9cf5599014e9dc435b32da92a7aa5 c4629c15b30145dd67144c281092fa99 0bd9cf5599014e9dc435b32da92a7aa5 fpscr=00000000
+randV128: 256 calls, 266 iters
+aese.8 q12, q13 e70216ec5cbcf49e8a09cb539549408a 182fa58322b1219295b48e6f81658922 f37adda8c0716dfefad803eb16d76ec2 182fa58322b1219295b48e6f81658922 fpscr=00000000
+aese.8 q12, q13 e0fd1393714954977124406c74e81e7a d52f1cc78e47c9e383314ed9438203c8 1659a420890276929ab55ed596abab37 d52f1cc78e47c9e383314ed9438203c8 fpscr=00000000
+aese.8 q12, q13 d2b5bf6419898df003e6fe7283eff6cb 7d772f10f5706b75304780122c8b69f0 ce32db92c343609779258ed07999f3e2 7d772f10f5706b75304780122c8b69f0 fpscr=00000000
+aese.8 q12, q13 3fa5c4d84771e518605a54f56dfe15b7 ddeb80fe57ce3c26f9fcb34432fe8249 ca2488f7ee631bb2cf2f35c8980894bb ddeb80fe57ce3c26f9fcb34432fe8249 fpscr=00000000
+aese.8 q12, q13 d4eaedef93c21b55bdb0c6ce36392d36 8cf3c5a6e236ba0ab0c81fb7053f6b55 a3bc5a3bd76f34cfc3d432b66abf35fb 8cf3c5a6e236ba0ab0c81fb7053f6b55 fpscr=00000000
+aese.8 q12, q13 44d5584589abea635dc49b10189f4c14 0d37eadc490b8fa61a337e4f82bd51e7 ba68a4eea09337a6b8984dcf3be0d90d 0d37eadc490b8fa61a337e4f82bd51e7 fpscr=00000000
+aese.8 q12, q13 0b0b9f6018e987aeba97106bb88dbd45 9d5fe4af824eabd8f8f577d6f4dd0223 b8aa088a2c5321382920717a905c8533 9d5fe4af824eabd8f8f577d6f4dd0223 fpscr=00000000
+aese.8 q12, q13 0beca39f21ddd399b28a073ef6656128 1eca927d6d5eee012a6fe8ae3cfe5e6a 29d975984614c74674f7276059ecdf2c 1eca927d6d5eee012a6fe8ae3cfe5e6a fpscr=00000000
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+vmull.p64 q13, d14, d15 d384cd518929e2387c136cc3c41570ee 7a791cc22258550b79be1ff6470d35ca 15e85b45dac8ce3b536a167102c2320e 7a791cc22258550b79be1ff6470d35ca fpscr=00000000
+vmull.p64 q13, d14, d15 fc8bb01edfacdf8ac25fc5383270090d 5c212178108f417431a96bc9774a7e25 0e3d2037f99d0518a83c2b858efa3224 5c212178108f417431a96bc9774a7e25 fpscr=00000000
diff --git a/none/tests/arm/v8crypto_t.vgtest b/none/tests/arm/v8crypto_t.vgtest
new file mode 100644
index 0000000..a121035
--- /dev/null
+++ b/none/tests/arm/v8crypto_t.vgtest
@@ -0,0 +1,2 @@
+prog: v8crypto_t
+vgopts: -q
diff --git a/none/tests/arm/v8memory_a.c b/none/tests/arm/v8memory_a.c
new file mode 100644
index 0000000..f52ae79
--- /dev/null
+++ b/none/tests/arm/v8memory_a.c
@@ -0,0 +1,164 @@
+
+/*
+gcc -g -o v8memory_a -march=armv8-a -mfpu=crypto-neon-fp-armv8 \
+ none/tests/arm/v8memory.c -I. -Wall -marm
+
+gcc -g -o v8memory_t -march=armv8-a -mfpu=crypto-neon-fp-armv8 \
+ none/tests/arm/v8memory.c -I. -Wall -mthumb
+*/
+
+/* These tests unfortunately are unable to check the relative
+ placement (or, even, presence) of the required memory fences
+ relative to the store/load required. They only verify the
+ data-movement component. */
+
+#include <stdio.h>
+#include <malloc.h> // memalign
+#include <string.h> // memset
+#include "tests/malloc.h"
+#include <assert.h>
+
+typedef unsigned char UChar;
+typedef unsigned short int UShort;
+typedef unsigned int UInt;
+typedef signed int Int;
+typedef unsigned char UChar;
+typedef signed long long int Long;
+typedef unsigned long long int ULong;
+
+typedef unsigned char Bool;
+#define False ((Bool)0)
+#define True ((Bool)1)
+
+static inline UChar randUChar ( void )
+{
+ static UInt seed = 90210; // Somewhere in Beverly Hills, allegedly.
+ seed = 1103515245 * seed + 12345;
+ return (seed >> 17) & 0xFF;
+}
+
+static UInt randUInt ( void )
+{
+ Int i;
+ UInt r = 0;
+ for (i = 0; i < 4; i++) {
+ r = (r << 8) | (UInt)(0xFF & randUChar());
+ }
+ return r;
+}
+
+static void show_block_xor ( UChar* block1, UChar* block2, Int n )
+{
+ Int i;
+ printf(" ");
+ for (i = 0; i < n; i++) {
+ if (i > 0 && 0 == (i & 15)) printf("\n ");
+ if (0 == (i & 15)) printf("[%3d] ", i);
+ UInt diff = 0xFF & (UInt)(block1[i] - block2[i]);
+ if (diff == 0)
+ printf(".. ");
+ else
+ printf("%02x ", diff);
+ }
+ printf("\n");
+}
+
+
+// INSN may mention the following regs as containing load/store data:
+// r2 r3 r6 r9
+// INSN must mention the following reg as containing the EA: r10
+//
+// INSN can use r4 and r5 as scratch
+//
+// In: rand: memory area (128 bytes), r2, r3, r6, r9
+// r10 pointing to middle of memory area
+//
+// Out: memory area, r2, r3, r6, r9, r10
+//
+// What is printed out: the XOR of the new and old versions of the
+// following:
+// the memory area
+// r2, r3 r6 r9 r10
+
+#define MEM_TEST(INSN) { \
+ int i; \
+ const int N = 128; \
+ UChar* area1 = memalign16(N); \
+ UChar* area2 = memalign16(N); \
+ for (i = 0; i < N; i++) area1[i] = area2[i] = randUChar(); \
+ UInt block1[5]; \
+ UInt block2[5]; \
+ /* 0:r2 1:r3 2:r6 3:r9 4:r10 */ \
+ for (i = 0; i < 5; i++) block1[i] = block2[i] = randUInt(); \
+ block1[4] = block2[4] = (UInt)(&area1[N/2]); \
+ __asm__ __volatile__( \
+ "ldr r2, [%0, #0] ; " \
+ "ldr r3, [%0, #4] ; " \
+ "ldr r6, [%0, #8] ; " \
+ "ldr r9, [%0, #12] ; " \
+ "ldr r10, [%0, #16] ; " \
+ INSN " ; " \
+ "str r2, [%0, #0] ; " \
+ "str r3, [%0, #4] ; " \
+ "str r6, [%0, #8] ; " \
+ "str r9, [%0, #12] ; " \
+ "str r10, [%0, #16] ; " \
+ : : "r"(&block1[0]) : "r2", "r3", "r4", "r5", "r6", "r9", "r10", \
+ "memory", "cc" \
+ ); \
+ printf("%s with r10 = middle_of_block\n", INSN); \
+ show_block_xor(&area1[0], &area2[0], N); \
+ printf(" %08x r2 (xor, data intreg #1)\n", block1[0] ^ block2[0]); \
+ printf(" %08x r3 (xor, data intreg #2)\n", block1[1] ^ block2[1]); \
+ printf(" %08x r6 (xor, data intreg #3)\n", block1[2] ^ block2[2]); \
+ printf(" %08x r9 (xor, data intreg #4)\n", block1[3] ^ block2[3]); \
+ printf(" %08x r10 (xor, addr intreg #1)\n", block1[4] ^ block2[4]); \
+ printf("\n"); \
+ free(area1); free(area2); \
+ }
+
+
+int main ( void )
+{
+ ////////////////////////////////////////////////////////////////
+ printf("LDA{,B,H} (reg)\n\n");
+ MEM_TEST("lda r6, [r10]")
+ MEM_TEST("ldab r9, [r10]")
+ MEM_TEST("ldah r3, [r10]")
+
+ ////////////////////////////////////////////////////////////////
+ printf("STL{,B,H} (reg)\n\n");
+ MEM_TEST("stl r6, [r10]")
+ MEM_TEST("stlb r9, [r10]")
+ MEM_TEST("stlh r3, [r10]")
+
+ ////////////////////////////////////////////////////////////////
+ printf("LDAEX{,B,H,D} (reg)\n\n");
+ MEM_TEST("ldaex r6, [r10]")
+ MEM_TEST("ldaexb r9, [r10]")
+ MEM_TEST("ldaexh r3, [r10]")
+ MEM_TEST("ldaexd r2, r3, [r10]")
+
+ ////////////////////////////////////////////////////////////////
+ // These verify that stlex* do notice a cleared (missing) reservation.
+ printf("STLEX{,B,H,D} (reg) -- expected to fail\n\n");
+ MEM_TEST("clrex; stlex r9, r6, [r10]")
+ MEM_TEST("clrex; stlexb r9, r6, [r10]")
+ MEM_TEST("clrex; stlexh r9, r3, [r10]")
+ MEM_TEST("clrex; stlexd r9, r2, r3, [r10]")
+
+ ////////////////////////////////////////////////////////////////
+ // These verify that stlex* do notice a successful reservation.
+ // By using ldaex* to create the reservation in the first place,
+ // they also verify that ldaex* actually create a reservation.
+ printf("STLEX{,B,H,D} (reg) -- expected to succeed\n\n");
+ MEM_TEST("ldaex r2, [r10] ; stlex r9, r6, [r10]")
+ MEM_TEST("ldaexb r2, [r10] ; stlexb r9, r6, [r10]")
+ MEM_TEST("ldaexh r2, [r10] ; stlexh r9, r3, [r10]")
+ MEM_TEST("mov r4, r2 ; mov r5, r3 ; " // preserve r2/r3 around the ldrexd
+ "ldaexd r2, r3, [r10] ; "
+ "mov r2, r4 ; mov r3, r5 ; "
+ "stlexd r9, r2, r3, [r10]")
+
+ return 0;
+}
diff --git a/none/tests/arm/v8memory_a.stderr.exp b/none/tests/arm/v8memory_a.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/arm/v8memory_a.stderr.exp
diff --git a/none/tests/arm/v8memory_a.stdout.exp b/none/tests/arm/v8memory_a.stdout.exp
new file mode 100644
index 0000000..d42f76a
--- /dev/null
+++ b/none/tests/arm/v8memory_a.stdout.exp
@@ -0,0 +1,280 @@
+LDA{,B,H} (reg)
+
+lda r6, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 94c87dfb r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+ldab r9, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ bf153f1b r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+ldah r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ bf1bfa0f r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+STL{,B,H} (reg)
+
+stl r6, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] 5f 54 c5 05 .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+stlb r9, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] 99 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+stlh r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] 72 97 .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+LDAEX{,B,H,D} (reg)
+
+ldaex r6, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 9b7a3e28 r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+ldaexb r9, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 4490a389 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+ldaexh r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ ab5a6969 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+ldaexd r2, r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 5b766a75 r2 (xor, data intreg #1)
+ 22d70ad9 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+STLEX{,B,H,D} (reg) -- expected to fail
+
+clrex; stlex r9, r6, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ d8d1584e r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+clrex; stlexb r9, r6, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ bb0a700f r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+clrex; stlexh r9, r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ adc8836c r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+clrex; stlexd r9, r2, r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 9b43a481 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+STLEX{,B,H,D} (reg) -- expected to succeed
+
+ldaex r2, [r10] ; stlex r9, r6, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] 31 40 35 27 .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0f73db2f r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ b2943eb7 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+ldaexb r2, [r10] ; stlexb r9, r6, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] df .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ b000c173 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ c522f103 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+ldaexh r2, [r10] ; stlexh r9, r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] 2d ee .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 62f1d42d r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 966d434a r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+mov r4, r2 ; mov r5, r3 ; ldaexd r2, r3, [r10] ; mov r2, r4 ; mov r3, r5 ; stlexd r9, r2, r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] ec b1 cc 36 7c 21 2b 86 .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ f841384f r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
diff --git a/none/tests/arm/v8memory_a.vgtest b/none/tests/arm/v8memory_a.vgtest
new file mode 100644
index 0000000..1e5e726
--- /dev/null
+++ b/none/tests/arm/v8memory_a.vgtest
@@ -0,0 +1,2 @@
+prog: v8memory_a
+vgopts: -q
diff --git a/none/tests/arm/v8memory_t.c b/none/tests/arm/v8memory_t.c
new file mode 100644
index 0000000..f52ae79
--- /dev/null
+++ b/none/tests/arm/v8memory_t.c
@@ -0,0 +1,164 @@
+
+/*
+gcc -g -o v8memory_a -march=armv8-a -mfpu=crypto-neon-fp-armv8 \
+ none/tests/arm/v8memory.c -I. -Wall -marm
+
+gcc -g -o v8memory_t -march=armv8-a -mfpu=crypto-neon-fp-armv8 \
+ none/tests/arm/v8memory.c -I. -Wall -mthumb
+*/
+
+/* These tests unfortunately are unable to check the relative
+ placement (or, even, presence) of the required memory fences
+ relative to the store/load required. They only verify the
+ data-movement component. */
+
+#include <stdio.h>
+#include <malloc.h> // memalign
+#include <string.h> // memset
+#include "tests/malloc.h"
+#include <assert.h>
+
+typedef unsigned char UChar;
+typedef unsigned short int UShort;
+typedef unsigned int UInt;
+typedef signed int Int;
+typedef unsigned char UChar;
+typedef signed long long int Long;
+typedef unsigned long long int ULong;
+
+typedef unsigned char Bool;
+#define False ((Bool)0)
+#define True ((Bool)1)
+
+static inline UChar randUChar ( void )
+{
+ static UInt seed = 90210; // Somewhere in Beverly Hills, allegedly.
+ seed = 1103515245 * seed + 12345;
+ return (seed >> 17) & 0xFF;
+}
+
+static UInt randUInt ( void )
+{
+ Int i;
+ UInt r = 0;
+ for (i = 0; i < 4; i++) {
+ r = (r << 8) | (UInt)(0xFF & randUChar());
+ }
+ return r;
+}
+
+static void show_block_xor ( UChar* block1, UChar* block2, Int n )
+{
+ Int i;
+ printf(" ");
+ for (i = 0; i < n; i++) {
+ if (i > 0 && 0 == (i & 15)) printf("\n ");
+ if (0 == (i & 15)) printf("[%3d] ", i);
+ UInt diff = 0xFF & (UInt)(block1[i] - block2[i]);
+ if (diff == 0)
+ printf(".. ");
+ else
+ printf("%02x ", diff);
+ }
+ printf("\n");
+}
+
+
+// INSN may mention the following regs as containing load/store data:
+// r2 r3 r6 r9
+// INSN must mention the following reg as containing the EA: r10
+//
+// INSN can use r4 and r5 as scratch
+//
+// In: rand: memory area (128 bytes), r2, r3, r6, r9
+// r10 pointing to middle of memory area
+//
+// Out: memory area, r2, r3, r6, r9, r10
+//
+// What is printed out: the XOR of the new and old versions of the
+// following:
+// the memory area
+// r2, r3 r6 r9 r10
+
+#define MEM_TEST(INSN) { \
+ int i; \
+ const int N = 128; \
+ UChar* area1 = memalign16(N); \
+ UChar* area2 = memalign16(N); \
+ for (i = 0; i < N; i++) area1[i] = area2[i] = randUChar(); \
+ UInt block1[5]; \
+ UInt block2[5]; \
+ /* 0:r2 1:r3 2:r6 3:r9 4:r10 */ \
+ for (i = 0; i < 5; i++) block1[i] = block2[i] = randUInt(); \
+ block1[4] = block2[4] = (UInt)(&area1[N/2]); \
+ __asm__ __volatile__( \
+ "ldr r2, [%0, #0] ; " \
+ "ldr r3, [%0, #4] ; " \
+ "ldr r6, [%0, #8] ; " \
+ "ldr r9, [%0, #12] ; " \
+ "ldr r10, [%0, #16] ; " \
+ INSN " ; " \
+ "str r2, [%0, #0] ; " \
+ "str r3, [%0, #4] ; " \
+ "str r6, [%0, #8] ; " \
+ "str r9, [%0, #12] ; " \
+ "str r10, [%0, #16] ; " \
+ : : "r"(&block1[0]) : "r2", "r3", "r4", "r5", "r6", "r9", "r10", \
+ "memory", "cc" \
+ ); \
+ printf("%s with r10 = middle_of_block\n", INSN); \
+ show_block_xor(&area1[0], &area2[0], N); \
+ printf(" %08x r2 (xor, data intreg #1)\n", block1[0] ^ block2[0]); \
+ printf(" %08x r3 (xor, data intreg #2)\n", block1[1] ^ block2[1]); \
+ printf(" %08x r6 (xor, data intreg #3)\n", block1[2] ^ block2[2]); \
+ printf(" %08x r9 (xor, data intreg #4)\n", block1[3] ^ block2[3]); \
+ printf(" %08x r10 (xor, addr intreg #1)\n", block1[4] ^ block2[4]); \
+ printf("\n"); \
+ free(area1); free(area2); \
+ }
+
+
+int main ( void )
+{
+ ////////////////////////////////////////////////////////////////
+ printf("LDA{,B,H} (reg)\n\n");
+ MEM_TEST("lda r6, [r10]")
+ MEM_TEST("ldab r9, [r10]")
+ MEM_TEST("ldah r3, [r10]")
+
+ ////////////////////////////////////////////////////////////////
+ printf("STL{,B,H} (reg)\n\n");
+ MEM_TEST("stl r6, [r10]")
+ MEM_TEST("stlb r9, [r10]")
+ MEM_TEST("stlh r3, [r10]")
+
+ ////////////////////////////////////////////////////////////////
+ printf("LDAEX{,B,H,D} (reg)\n\n");
+ MEM_TEST("ldaex r6, [r10]")
+ MEM_TEST("ldaexb r9, [r10]")
+ MEM_TEST("ldaexh r3, [r10]")
+ MEM_TEST("ldaexd r2, r3, [r10]")
+
+ ////////////////////////////////////////////////////////////////
+ // These verify that stlex* do notice a cleared (missing) reservation.
+ printf("STLEX{,B,H,D} (reg) -- expected to fail\n\n");
+ MEM_TEST("clrex; stlex r9, r6, [r10]")
+ MEM_TEST("clrex; stlexb r9, r6, [r10]")
+ MEM_TEST("clrex; stlexh r9, r3, [r10]")
+ MEM_TEST("clrex; stlexd r9, r2, r3, [r10]")
+
+ ////////////////////////////////////////////////////////////////
+ // These verify that stlex* do notice a successful reservation.
+ // By using ldaex* to create the reservation in the first place,
+ // they also verify that ldaex* actually create a reservation.
+ printf("STLEX{,B,H,D} (reg) -- expected to succeed\n\n");
+ MEM_TEST("ldaex r2, [r10] ; stlex r9, r6, [r10]")
+ MEM_TEST("ldaexb r2, [r10] ; stlexb r9, r6, [r10]")
+ MEM_TEST("ldaexh r2, [r10] ; stlexh r9, r3, [r10]")
+ MEM_TEST("mov r4, r2 ; mov r5, r3 ; " // preserve r2/r3 around the ldrexd
+ "ldaexd r2, r3, [r10] ; "
+ "mov r2, r4 ; mov r3, r5 ; "
+ "stlexd r9, r2, r3, [r10]")
+
+ return 0;
+}
diff --git a/none/tests/arm/v8memory_t.stderr.exp b/none/tests/arm/v8memory_t.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/arm/v8memory_t.stderr.exp
diff --git a/none/tests/arm/v8memory_t.stdout.exp b/none/tests/arm/v8memory_t.stdout.exp
new file mode 100644
index 0000000..d42f76a
--- /dev/null
+++ b/none/tests/arm/v8memory_t.stdout.exp
@@ -0,0 +1,280 @@
+LDA{,B,H} (reg)
+
+lda r6, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 94c87dfb r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+ldab r9, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ bf153f1b r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+ldah r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ bf1bfa0f r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+STL{,B,H} (reg)
+
+stl r6, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] 5f 54 c5 05 .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+stlb r9, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] 99 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+stlh r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] 72 97 .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+LDAEX{,B,H,D} (reg)
+
+ldaex r6, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 9b7a3e28 r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+ldaexb r9, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 4490a389 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+ldaexh r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ ab5a6969 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+ldaexd r2, r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 5b766a75 r2 (xor, data intreg #1)
+ 22d70ad9 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 00000000 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+STLEX{,B,H,D} (reg) -- expected to fail
+
+clrex; stlex r9, r6, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ d8d1584e r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+clrex; stlexb r9, r6, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ bb0a700f r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+clrex; stlexh r9, r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ adc8836c r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+clrex; stlexd r9, r2, r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 9b43a481 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+STLEX{,B,H,D} (reg) -- expected to succeed
+
+ldaex r2, [r10] ; stlex r9, r6, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] 31 40 35 27 .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0f73db2f r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ b2943eb7 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+ldaexb r2, [r10] ; stlexb r9, r6, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] df .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ b000c173 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ c522f103 r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+ldaexh r2, [r10] ; stlexh r9, r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] 2d ee .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 62f1d42d r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ 966d434a r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
+mov r4, r2 ; mov r5, r3 ; ldaexd r2, r3, [r10] ; mov r2, r4 ; mov r3, r5 ; stlexd r9, r2, r3, [r10] with r10 = middle_of_block
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] ec b1 cc 36 7c 21 2b 86 .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 00000000 r2 (xor, data intreg #1)
+ 00000000 r3 (xor, data intreg #2)
+ 00000000 r6 (xor, data intreg #3)
+ f841384f r9 (xor, data intreg #4)
+ 00000000 r10 (xor, addr intreg #1)
+
diff --git a/none/tests/arm/v8memory_t.vgtest b/none/tests/arm/v8memory_t.vgtest
new file mode 100644
index 0000000..5a91413
--- /dev/null
+++ b/none/tests/arm/v8memory_t.vgtest
@@ -0,0 +1,2 @@
+prog: v8memory_t
+vgopts: -q
diff --git a/none/tests/arm/vfp.c b/none/tests/arm/vfp.c
index 7d7f0dc..c7360af 100644
--- a/none/tests/arm/vfp.c
+++ b/none/tests/arm/vfp.c
@@ -848,55 +848,55 @@
printf("do_vldm_vstm_check:\n");
__asm__ volatile(
"mov r1, %0\n\t"
- "vldmia r1!, {s0, s1, s2, s3}\n\t"
+ "vldmia r1!, {s16, s17, s18, s19}\n\t"
"mov r0, %1\n\t"
"sub r1, r1, %0\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s2\n\t"
+ "vmov r1, s18\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s3\n\t"
+ "vmov r1, s19\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s0\n\t"
+ "vmov r1, s16\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
/* --- */
"add r1, %0, #32\n\t"
- "vldmdb r1!, {s5, s6}\n\t"
+ "vldmdb r1!, {s25, s26}\n\t"
"mov r0, %1\n\t"
"sub r1, r1, %0\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s5\n\t"
+ "vmov r1, s25\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s6\n\t"
+ "vmov r1, s26\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
/* --- */
"add r1, %0, #4\n\t"
- "vldmia r1, {s0, s1, s2, s3}\n\t"
+ "vldmia r1, {s20, s21, s22, s23}\n\t"
"mov r0, %1\n\t"
"sub r1, r1, %0\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s2\n\t"
+ "vmov r1, s22\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s3\n\t"
+ "vmov r1, s23\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s0\n\t"
+ "vmov r1, s20\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
/* --- */
@@ -970,15 +970,15 @@
"bl printf\n\t"
/* --- */
"mov r0, #0x55\n\t"
- "vmov s0, r0\n\t"
+ "vmov s20, r0\n\t"
"mov r0, #0x56\n\t"
- "vmov s1, r0\n\t"
+ "vmov s21, r0\n\t"
"mov r0, #0x57\n\t"
- "vmov s2, r0\n\t"
+ "vmov s22, r0\n\t"
"mov r0, #0x58\n\t"
- "vmov s3, r0\n\t"
+ "vmov s23, r0\n\t"
"add r1, %0, #0\n\t"
- "vstmia r1!, {s0, s1, s2, s3}\n\t"
+ "vstmia r1!, {s20, s21, s22, s23}\n\t"
"mov r0, %1\n\t"
"sub r1, r1, %0\n\t"
"mov r3, r1\n\t"
@@ -1044,7 +1044,8 @@
:
: "r" (data), "r" (format), "r"(&res)
: "r0", "r1", "r2", "r3", "r5", "r12", "r14", "memory",
- "s0", "s1", "s2", "s3", "s5", "s6", "s16", "s17",
+ "s0", "s1", "s2", "s3", "s5", "s6", "s16", "s17", "s18", "s19",
+ "s20", "s21", "s22", "s23", "s25", "s26",
"d10", "d30", "d31"
);
printf("data:\n");
diff --git a/none/tests/arm64/Makefile.am b/none/tests/arm64/Makefile.am
index f06e30b..a0a2cfe 100644
--- a/none/tests/arm64/Makefile.am
+++ b/none/tests/arm64/Makefile.am
@@ -4,6 +4,7 @@
dist_noinst_SCRIPTS = filter_stderr
EXTRA_DIST = \
+ crc32.stdout.exp crc32.stderr.exp crc32.vgtest \
cvtf_imm.stdout.exp cvtf_imm.stderr.exp cvtf_imm.vgtest \
fp_and_simd.stdout.exp fp_and_simd.stderr.exp fp_and_simd.vgtest \
integer.stdout.exp integer.stderr.exp integer.vgtest \
@@ -16,12 +17,17 @@
integer \
memory
+if BUILD_ARMV8_CRC_TESTS
+ check_PROGRAMS += crc32
+endif
+
AM_CFLAGS += @FLAG_M64@
AM_CXXFLAGS += @FLAG_M64@
AM_CCASFLAGS += @FLAG_M64@
allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+crc32_CFLAGS = $(AM_CFLAGS) -march=armv8-a+crc
fp_and_simd_CFLAGS = $(AM_CFLAGS) -march=armv8-a+crypto
integer_CFLAGS = $(AM_CFLAGS) -g -O0 -DTEST_BFM=0
diff --git a/none/tests/arm64/Makefile.in b/none/tests/arm64/Makefile.in
new file mode 100644
index 0000000..1d94d1d
--- /dev/null
+++ b/none/tests/arm64/Makefile.in
@@ -0,0 +1,1045 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+am__is_gnu_make = { \
+ if test -z '$(MAKELEVEL)'; then \
+ false; \
+ elif test -n '$(MAKE_HOST)'; then \
+ true; \
+ elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
+ true; \
+ else \
+ false; \
+ fi; \
+}
+am__make_running_with_option = \
+ case $${target_option-} in \
+ ?) ;; \
+ *) echo "am__make_running_with_option: internal error: invalid" \
+ "target option '$${target_option-}' specified" >&2; \
+ exit 1;; \
+ esac; \
+ has_opt=no; \
+ sane_makeflags=$$MAKEFLAGS; \
+ if $(am__is_gnu_make); then \
+ sane_makeflags=$$MFLAGS; \
+ else \
+ case $$MAKEFLAGS in \
+ *\\[\ \ ]*) \
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+ sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
+ | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \
+ esac; \
+ fi; \
+ skip_next=no; \
+ strip_trailopt () \
+ { \
+ flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
+ }; \
+ for flg in $$sane_makeflags; do \
+ test $$skip_next = yes && { skip_next=no; continue; }; \
+ case $$flg in \
+ *=*|--*) continue;; \
+ -*I) strip_trailopt 'I'; skip_next=yes;; \
+ -*I?*) strip_trailopt 'I';; \
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+ -*O?*) strip_trailopt 'O';; \
+ -*l) strip_trailopt 'l'; skip_next=yes;; \
+ -*l?*) strip_trailopt 'l';; \
+ -[dEDm]) skip_next=yes;; \
+ -[JT]) skip_next=yes;; \
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+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
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+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_3 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+
+# Make sure that all test programs have threaded errno.
+# Disable largefile support as there are test cases explictly enabling it.
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
+@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
+@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-constant-out-of-range-compare \
+@COMPILER_IS_CLANG_TRUE@ -Wno-self-assign -Wno-string-plus-int \
+@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
+@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
+@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
+check_PROGRAMS = allexec$(EXEEXT) cvtf_imm$(EXEEXT) \
+ fp_and_simd$(EXEEXT) integer$(EXEEXT) memory$(EXEEXT) \
+ $(am__EXEEXT_1)
+@BUILD_ARMV8_CRC_TESTS_TRUE@am__append_8 = crc32
+subdir = none/tests/arm64
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.ac
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
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+ $(am__DIST_COMMON)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
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+@BUILD_ARMV8_CRC_TESTS_TRUE@am__EXEEXT_1 = crc32$(EXEEXT)
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+ $(LDFLAGS) -o $@
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+ $(LDFLAGS) -o $@
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+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+integer_SOURCES = integer.c
+integer_OBJECTS = integer-integer.$(OBJEXT)
+integer_LDADD = $(LDADD)
+integer_LINK = $(CCLD) $(integer_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
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+AM_V_P = $(am__v_P_@AM_V@)
+am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
+am__v_P_0 = false
+am__v_P_1 = :
+AM_V_GEN = $(am__v_GEN_@AM_V@)
+am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@)
+am__v_GEN_0 = @echo " GEN " $@;
+am__v_GEN_1 =
+AM_V_at = $(am__v_at_@AM_V@)
+am__v_at_ = $(am__v_at_@AM_DEFAULT_V@)
+am__v_at_0 = @
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+am__v_lt_0 = --silent
+am__v_lt_1 =
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+AM_V_CC = $(am__v_CC_@AM_V@)
+am__v_CC_ = $(am__v_CC_@AM_DEFAULT_V@)
+am__v_CC_0 = @echo " CC " $@;
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+AM_V_CCLD = $(am__v_CCLD_@AM_V@)
+am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
+am__v_CCLD_0 = @echo " CCLD " $@;
+am__v_CCLD_1 =
+SOURCES = allexec.c crc32.c cvtf_imm.c fp_and_simd.c integer.c \
+ memory.c
+DIST_SOURCES = allexec.c crc32.c cvtf_imm.c fp_and_simd.c integer.c \
+ memory.c
+am__can_run_installinfo = \
+ case $$AM_UPDATE_INFO_DIR in \
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+ esac
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+# Read a list of newline-separated strings from the standard input,
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+ BEGIN { nonempty = 0; } \
+ { items[$$0] = 1; nonempty = 1; } \
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+'
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+ list='$(am__tagged_files)'; \
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+ $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/depcomp
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+FLAG_M64 = @FLAG_M64@
+FLAG_MIPS32 = @FLAG_MIPS32@
+FLAG_MIPS64 = @FLAG_MIPS64@
+FLAG_MLONG_DOUBLE_128 = @FLAG_MLONG_DOUBLE_128@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_OCTEON = @FLAG_OCTEON@
+FLAG_OCTEON2 = @FLAG_OCTEON2@
+FLAG_T_TEXT = @FLAG_T_TEXT@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_CAST_ALIGN = @FLAG_W_CAST_ALIGN@
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+FLAG_W_FORMAT_SIGNEDNESS = @FLAG_W_FORMAT_SIGNEDNESS@
+FLAG_W_IGNORED_QUALIFIERS = @FLAG_W_IGNORED_QUALIFIERS@
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+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
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+SOLARIS_UNDEF_LARGESOURCE = @SOLARIS_UNDEF_LARGESOURCE@
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+VERSION = @VERSION@
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+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
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+VG_TMPDIR = @VG_TMPDIR@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
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+am__include = @am__include@
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+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = -O2 -g -std=gnu99 -Wall -Wmissing-prototypes -Wshadow \
+ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \
+ @FLAG_W_CAST_ALIGN@ @FLAG_W_CAST_QUAL@ @FLAG_W_WRITE_STRINGS@ \
+ @FLAG_W_EMPTY_BODY@ @FLAG_W_FORMAT@ @FLAG_W_FORMAT_SIGNEDNESS@ \
+ @FLAG_W_FORMAT_SECURITY@ @FLAG_W_IGNORED_QUALIFIERS@ \
+ @FLAG_W_MISSING_PARAMETER_TYPE@ @FLAG_W_OLD_STYLE_DECLARATION@ \
+ @FLAG_FNO_STACK_PROTECTOR@ @FLAG_FSANITIZE@ \
+ -fno-strict-aliasing -fno-builtin $(am__append_1)
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fpic -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# These flags are used for building the preload shared objects (PSOs).
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads. Also, we must use any
+# -mpreferred-stack-boundary flag to build the preload shared
+# objects, since that risks misaligning the client's stack and
+# results in segfaults like (eg) #324050.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \
+@VGCONF_OS_IS_DARWIN_TRUE@ -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
+ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
+AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
+AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ @FLAG_M64@ $(am__empty)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) @FLAG_M64@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ crc32.stdout.exp crc32.stderr.exp crc32.vgtest \
+ cvtf_imm.stdout.exp cvtf_imm.stderr.exp cvtf_imm.vgtest \
+ fp_and_simd.stdout.exp fp_and_simd.stderr.exp fp_and_simd.vgtest \
+ integer.stdout.exp integer.stderr.exp integer.vgtest \
+ memory.stdout.exp memory.stderr.exp memory.vgtest
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+crc32_CFLAGS = $(AM_CFLAGS) -march=armv8-a+crc
+fp_and_simd_CFLAGS = $(AM_CFLAGS) -march=armv8-a+crypto
+integer_CFLAGS = $(AM_CFLAGS) -g -O0 -DTEST_BFM=0
+fp_and_simd_LDADD = -lm
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/arm64/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/arm64/Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+$(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__empty):
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES) $(EXTRA_allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(AM_V_CCLD)$(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+
+crc32$(EXEEXT): $(crc32_OBJECTS) $(crc32_DEPENDENCIES) $(EXTRA_crc32_DEPENDENCIES)
+ @rm -f crc32$(EXEEXT)
+ $(AM_V_CCLD)$(crc32_LINK) $(crc32_OBJECTS) $(crc32_LDADD) $(LIBS)
+
+cvtf_imm$(EXEEXT): $(cvtf_imm_OBJECTS) $(cvtf_imm_DEPENDENCIES) $(EXTRA_cvtf_imm_DEPENDENCIES)
+ @rm -f cvtf_imm$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(cvtf_imm_OBJECTS) $(cvtf_imm_LDADD) $(LIBS)
+
+fp_and_simd$(EXEEXT): $(fp_and_simd_OBJECTS) $(fp_and_simd_DEPENDENCIES) $(EXTRA_fp_and_simd_DEPENDENCIES)
+ @rm -f fp_and_simd$(EXEEXT)
+ $(AM_V_CCLD)$(fp_and_simd_LINK) $(fp_and_simd_OBJECTS) $(fp_and_simd_LDADD) $(LIBS)
+
+integer$(EXEEXT): $(integer_OBJECTS) $(integer_DEPENDENCIES) $(EXTRA_integer_DEPENDENCIES)
+ @rm -f integer$(EXEEXT)
+ $(AM_V_CCLD)$(integer_LINK) $(integer_OBJECTS) $(integer_LDADD) $(LIBS)
+
+memory$(EXEEXT): $(memory_OBJECTS) $(memory_DEPENDENCIES) $(EXTRA_memory_DEPENDENCIES)
+ @rm -f memory$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(memory_OBJECTS) $(memory_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/allexec-allexec.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/crc32-crc32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cvtf_imm.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fp_and_simd-fp_and_simd.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/integer-integer.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/memory.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.o$$||'`;\
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ $< &&\
+@am__fastdepCC_TRUE@ $(am__mv) $$depbase.Tpo $$depbase.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.obj$$||'`;\
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ `$(CYGPATH_W) '$<'` &&\
+@am__fastdepCC_TRUE@ $(am__mv) $$depbase.Tpo $$depbase.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+
+allexec-allexec.o: allexec.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.o -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='allexec.c' object='allexec-allexec.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.o `test -f 'allexec.c' || echo '$(srcdir)/'`allexec.c
+
+allexec-allexec.obj: allexec.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.obj -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
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+# Otherwise a system limit (for SysV at least) may be exceeded.
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diff --git a/none/tests/arm64/allexec.c b/none/tests/arm64/allexec.c
deleted file mode 120000
index 6d6a9cf..0000000
--- a/none/tests/arm64/allexec.c
+++ /dev/null
@@ -1 +0,0 @@
-../allexec.c
\ No newline at end of file
diff --git a/none/tests/allexec.c b/none/tests/arm64/allexec.c
similarity index 100%
copy from none/tests/allexec.c
copy to none/tests/arm64/allexec.c
diff --git a/none/tests/arm64/crc32.c b/none/tests/arm64/crc32.c
new file mode 100644
index 0000000..43102c6
--- /dev/null
+++ b/none/tests/arm64/crc32.c
@@ -0,0 +1,123 @@
+
+/* To compile:
+ gcc -Wall -g -o crc32 none/tests/arm64/crc32.c -march=armv8-a+crc
+ -march=armv8-a+crc+crypto is also OK
+*/
+
+#include <stdio.h>
+#include <malloc.h> // memalign
+#include <string.h> // memset
+#include <assert.h>
+
+typedef unsigned char UChar;
+typedef unsigned short int UShort;
+typedef unsigned int UInt;
+typedef signed int Int;
+typedef unsigned char UChar;
+typedef signed long long int Long;
+typedef unsigned long long int ULong;
+
+typedef unsigned char Bool;
+#define False ((Bool)0)
+#define True ((Bool)1)
+
+
+#define TESTINST3(instruction, RMval, RNval, RD, RM, RN, carryin) \
+{ \
+ ULong out; \
+ ULong nzcv_out; \
+ ULong nzcv_in = (carryin ? (1<<29) : 0); \
+ __asm__ __volatile__( \
+ "msr nzcv,%4;" \
+ "mov " #RM ",%2;" \
+ "mov " #RN ",%3;" \
+ instruction ";" \
+ "mov %0," #RD ";" \
+ "mrs %1,nzcv;" \
+ : "=&r" (out), "=&r" (nzcv_out) \
+ : "r" (RMval), "r" (RNval), "r" (nzcv_in) \
+ : #RD, #RM, #RN, "cc", "memory" \
+ ); \
+ printf("%s :: rd %016llx rm %016llx, rn %016llx, " \
+ "cin %d, nzcv %08llx %c%c%c%c\n", \
+ instruction, out, ((ULong)RMval), ((ULong)RNval), \
+ carryin ? 1 : 0, \
+ nzcv_out & 0xffff0000, \
+ ((1<<31) & nzcv_out) ? 'N' : ' ', \
+ ((1<<30) & nzcv_out) ? 'Z' : ' ', \
+ ((1<<29) & nzcv_out) ? 'C' : ' ', \
+ ((1<<28) & nzcv_out) ? 'V' : ' ' \
+ ); \
+}
+
+int main ( void )
+{
+////////////////////////////////////////////////////////////////
+printf("CRC32/CRC32C\n");
+
+TESTINST3("crc32b w21,w20,w19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0);
+TESTINST3("crc32b w21,w20,w19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0);
+TESTINST3("crc32b w21,w20,w19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0);
+TESTINST3("crc32b w21,w20,w19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0);
+TESTINST3("crc32b w21,w20,w19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0);
+TESTINST3("crc32b w21,w20,w19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0);
+TESTINST3("crc32b w21,w20,w19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0);
+
+TESTINST3("crc32h w21,w20,w19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0);
+TESTINST3("crc32h w21,w20,w19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0);
+TESTINST3("crc32h w21,w20,w19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0);
+TESTINST3("crc32h w21,w20,w19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0);
+TESTINST3("crc32h w21,w20,w19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0);
+TESTINST3("crc32h w21,w20,w19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0);
+TESTINST3("crc32h w21,w20,w19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0);
+
+TESTINST3("crc32w w21,w20,w19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0);
+TESTINST3("crc32w w21,w20,w19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0);
+TESTINST3("crc32w w21,w20,w19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0);
+TESTINST3("crc32w w21,w20,w19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0);
+TESTINST3("crc32w w21,w20,w19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0);
+TESTINST3("crc32w w21,w20,w19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0);
+TESTINST3("crc32w w21,w20,w19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0);
+
+TESTINST3("crc32x w21,w20,x19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0);
+TESTINST3("crc32x w21,w20,x19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0);
+TESTINST3("crc32x w21,w20,x19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0);
+TESTINST3("crc32x w21,w20,x19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0);
+TESTINST3("crc32x w21,w20,x19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0);
+TESTINST3("crc32x w21,w20,x19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0);
+TESTINST3("crc32x w21,w20,x19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0);
+
+TESTINST3("crc32cb w21,w20,w19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0);
+TESTINST3("crc32cb w21,w20,w19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0);
+TESTINST3("crc32cb w21,w20,w19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0);
+TESTINST3("crc32cb w21,w20,w19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0);
+TESTINST3("crc32cb w21,w20,w19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0);
+TESTINST3("crc32cb w21,w20,w19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0);
+TESTINST3("crc32cb w21,w20,w19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0);
+
+TESTINST3("crc32ch w21,w20,w19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0);
+TESTINST3("crc32ch w21,w20,w19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0);
+TESTINST3("crc32ch w21,w20,w19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0);
+TESTINST3("crc32ch w21,w20,w19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0);
+TESTINST3("crc32ch w21,w20,w19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0);
+TESTINST3("crc32ch w21,w20,w19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0);
+TESTINST3("crc32ch w21,w20,w19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0);
+
+TESTINST3("crc32cw w21,w20,w19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0);
+TESTINST3("crc32cw w21,w20,w19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0);
+TESTINST3("crc32cw w21,w20,w19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0);
+TESTINST3("crc32cw w21,w20,w19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0);
+TESTINST3("crc32cw w21,w20,w19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0);
+TESTINST3("crc32cw w21,w20,w19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0);
+TESTINST3("crc32cw w21,w20,w19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0);
+
+TESTINST3("crc32cx w21,w20,x19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0);
+TESTINST3("crc32cx w21,w20,x19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0);
+TESTINST3("crc32cx w21,w20,x19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0);
+TESTINST3("crc32cx w21,w20,x19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0);
+TESTINST3("crc32cx w21,w20,x19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0);
+TESTINST3("crc32cx w21,w20,x19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0);
+TESTINST3("crc32cx w21,w20,x19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0);
+
+return 0;
+}
diff --git a/none/tests/arm64/crc32.stderr.exp b/none/tests/arm64/crc32.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/arm64/crc32.stderr.exp
diff --git a/none/tests/arm64/crc32.stdout.exp b/none/tests/arm64/crc32.stdout.exp
new file mode 100644
index 0000000..88af551
--- /dev/null
+++ b/none/tests/arm64/crc32.stdout.exp
@@ -0,0 +1,57 @@
+CRC32/CRC32C
+crc32b w21,w20,w19 :: rd 00000000f8957d4c rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000
+crc32b w21,w20,w19 :: rd 00000000f810b326 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000
+crc32b w21,w20,w19 :: rd 00000000ef405c96 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000
+crc32b w21,w20,w19 :: rd 00000000a0db523c rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000
+crc32b w21,w20,w19 :: rd 0000000096de687b rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000
+crc32b w21,w20,w19 :: rd 000000005b546bd0 rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000
+crc32b w21,w20,w19 :: rd 000000008f7a8684 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000
+crc32h w21,w20,w19 :: rd 00000000862b47a9 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000
+crc32h w21,w20,w19 :: rd 000000009a47a305 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000
+crc32h w21,w20,w19 :: rd 00000000a788663d rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000
+crc32h w21,w20,w19 :: rd 00000000b6c6f66f rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000
+crc32h w21,w20,w19 :: rd 00000000b046464a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000
+crc32h w21,w20,w19 :: rd 00000000fb8f180e rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000
+crc32h w21,w20,w19 :: rd 00000000c758d232 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000
+crc32w w21,w20,w19 :: rd 00000000b24959b6 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000
+crc32w w21,w20,w19 :: rd 00000000532cb693 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000
+crc32w w21,w20,w19 :: rd 00000000ffe2757b rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000
+crc32w w21,w20,w19 :: rd 00000000c3c8592d rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000
+crc32w w21,w20,w19 :: rd 00000000e44ccdd5 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000
+crc32w w21,w20,w19 :: rd 0000000004826ea7 rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000
+crc32w w21,w20,w19 :: rd 00000000784b67ea rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000
+crc32x w21,w20,x19 :: rd 000000009ca1d692 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000
+crc32x w21,w20,x19 :: rd 00000000b2eefa0a rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000
+crc32x w21,w20,x19 :: rd 00000000918ddaac rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000
+crc32x w21,w20,x19 :: rd 000000000449ce8d rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000
+crc32x w21,w20,x19 :: rd 000000001f887163 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000
+crc32x w21,w20,x19 :: rd 000000003ba77596 rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000
+crc32x w21,w20,x19 :: rd 00000000b1fd8b1d rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000
+crc32cb w21,w20,w19 :: rd 000000006c0c7e5d rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000
+crc32cb w21,w20,w19 :: rd 000000006c89b037 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000
+crc32cb w21,w20,w19 :: rd 0000000052bea2f4 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000
+crc32cb w21,w20,w19 :: rd 00000000e3e1185e rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000
+crc32cb w21,w20,w19 :: rd 000000002a4ef571 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000
+crc32cb w21,w20,w19 :: rd 00000000ec8c8b20 rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000
+crc32cb w21,w20,w19 :: rd 000000009e8f3600 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000
+crc32ch w21,w20,w19 :: rd 00000000318aa9b9 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000
+crc32ch w21,w20,w19 :: rd 0000000092c475a7 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000
+crc32ch w21,w20,w19 :: rd 00000000a4056232 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000
+crc32ch w21,w20,w19 :: rd 00000000eeee7718 rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000
+crc32ch w21,w20,w19 :: rd 0000000071b21af8 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000
+crc32ch w21,w20,w19 :: rd 00000000fcb40509 rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000
+crc32ch w21,w20,w19 :: rd 00000000ade3dc67 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000
+crc32cw w21,w20,w19 :: rd 000000004f6e8750 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000
+crc32cw w21,w20,w19 :: rd 000000004548949c rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000
+crc32cw w21,w20,w19 :: rd 0000000050fc77a7 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000
+crc32cw w21,w20,w19 :: rd 000000000b0f3746 rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000
+crc32cw w21,w20,w19 :: rd 0000000092a3acf2 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000
+crc32cw w21,w20,w19 :: rd 00000000d91fb7ba rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000
+crc32cw w21,w20,w19 :: rd 000000006b548718 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000
+crc32cx w21,w20,x19 :: rd 00000000252d3dc0 rm 4b154113f7d32514, rn cce230caafbf9cc9, cin 0, nzcv 00000000
+crc32cx w21,w20,x19 :: rd 0000000094dc9608 rm 33d5d595721d4f13, rn f4509311f443a7ce, cin 0, nzcv 00000000
+crc32cx w21,w20,x19 :: rd 0000000004d0ed55 rm 4a3c6de6954cbc17, rn 111b21e39fbd7254, cin 0, nzcv 00000000
+crc32cx w21,w20,x19 :: rd 000000004c3be587 rm fbb5c64ed1b044c6, rn 33ca4c4fb3960326, cin 0, nzcv 00000000
+crc32cx w21,w20,x19 :: rd 00000000b914bc44 rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000
+crc32cx w21,w20,x19 :: rd 000000005b10caab rm 02fe41918ac5cdba, rn 48e0815289728f05, cin 0, nzcv 00000000
+crc32cx w21,w20,x19 :: rd 00000000803f9752 rm b60a8f381f187bae, rn 008c208cc413ff72, cin 0, nzcv 00000000
diff --git a/none/tests/arm64/crc32.vgtest b/none/tests/arm64/crc32.vgtest
new file mode 100644
index 0000000..24ce0e3
--- /dev/null
+++ b/none/tests/arm64/crc32.vgtest
@@ -0,0 +1,3 @@
+prog: crc32
+prereq: test -x crc32
+vgopts: -q
diff --git a/none/tests/arm64/fp_and_simd.c b/none/tests/arm64/fp_and_simd.c
index 0aba2c8..2379e15 100644
--- a/none/tests/arm64/fp_and_simd.c
+++ b/none/tests/arm64/fp_and_simd.c
@@ -3104,8 +3104,8 @@
GEN_BINARY_TEST(pmull, 8h, 8b, 8b)
GEN_BINARY_TEST(pmull2, 8h, 16b, 16b)
-//GEN_BINARY_TEST(pmull, 1q, 1d, 1d)
-//GEN_BINARY_TEST(pmull, 1q, 2d, 2d)
+GEN_BINARY_TEST(pmull, 1q, 1d, 1d)
+GEN_BINARY_TEST(pmull2, 1q, 2d, 2d)
GEN_UNARY_TEST(rbit, 16b, 16b)
GEN_UNARY_TEST(rbit, 8b, 8b)
@@ -4523,10 +4523,6 @@
// ======================== CRYPTO ========================
-// These tests are believed to be correct but are disabled because
-// GNU assembler (GNU Binutils) 2.24.0.20140311 Linaro 2014.03
-// cannot be persuaded to accept those instructions (AFAICT).
-
GEN_TWOVEC_TEST(aesd_16b_16b, "aesd v6.16b, v27.16b", 6, 27)
GEN_TWOVEC_TEST(aese_16b_16b, "aese v6.16b, v27.16b", 6, 27)
GEN_TWOVEC_TEST(aesimc_16b_16b, "aesimc v6.16b, v27.16b", 6, 27)
@@ -5795,11 +5791,10 @@
if (1) test_pmul_16b_16b_16b(TyB);
if (1) test_pmul_8b_8b_8b(TyB);
- // pmull{2} 8h_8b_8b,8h_16b_16b,1q_1d_1d,1q_2d_2d
+ // pmull{2} 8h_8b_8b,8h_16b_16b
+ // pmull{2} 1q_1d_1d,1q_2d_2d is in the crypto section below
if (1) test_pmull_8h_8b_8b(TyB);
if (1) test_pmull2_8h_16b_16b(TyB);
- //if (0) test_pmull_1q_1d_1d(TyD);
- //if (0) test_pmull_1q_2d_2d(TyD);
// rbit 16b,8b
// rev16 16b,8b
@@ -7389,10 +7384,10 @@
// aese 16b (aes single round encryption)
// aesimc 16b (aes inverse mix columns)
// aesmc 16b (aes mix columns)
- if (0) test_aesd_16b_16b(TyNONE);
- if (0) test_aese_16b_16b(TyNONE);
- if (0) test_aesimc_16b_16b(TyNONE);
- if (0) test_aesmc_16b_16b(TyNONE);
+ if (1) DO50( test_aesd_16b_16b(TyNONE) );
+ if (1) DO50( test_aese_16b_16b(TyNONE) );
+ if (1) DO50( test_aesimc_16b_16b(TyNONE) );
+ if (1) DO50( test_aesmc_16b_16b(TyNONE) );
// sha1c q_s_4s
// sha1h s_s
@@ -7400,23 +7395,27 @@
// sha1p q_s_4s
// sha1su0 4s_4s_4s
// sha1su1 4s_4s
- if (0) test_sha1c_q_s_4s(TyNONE);
- if (0) test_sha1h_s_s(TyNONE);
- if (0) test_sha1m_q_s_4s(TyNONE);
- if (0) test_sha1p_q_s_4s(TyNONE);
- if (0) test_sha1su0_4s_4s_4s(TyNONE);
- if (0) test_sha1su1_4s_4s(TyNONE);
+ if (1) DO50( test_sha1c_q_s_4s(TyNONE) );
+ if (1) DO50( test_sha1h_s_s(TyNONE) );
+ if (1) DO50( test_sha1m_q_s_4s(TyNONE) );
+ if (1) DO50( test_sha1p_q_s_4s(TyNONE) );
+ if (1) DO50( test_sha1su0_4s_4s_4s(TyNONE) );
+ if (1) DO50( test_sha1su1_4s_4s(TyNONE) );
// sha256h2 q_q_4s
// sha256h q_q_4s
// sha256su0 4s_4s
// sha256su1 4s_4s_4s
- if (0) test_sha256h2_q_q_4s(TyNONE);
- if (0) test_sha256h_q_q_4s(TyNONE);
- if (0) test_sha256su0_4s_4s(TyNONE);
- if (0) test_sha256su1_4s_4s_4s(TyNONE);
+ if (1) DO50( test_sha256h2_q_q_4s(TyNONE) );
+ if (1) DO50( test_sha256h_q_q_4s(TyNONE) );
+ if (1) DO50( test_sha256su0_4s_4s(TyNONE) );
+ if (1) DO50( test_sha256su1_4s_4s_4s(TyNONE) );
- return 0;
+ // pmull{2} 1q_1d_1d,1q_2d_2d
+ if (1) test_pmull_1q_1d_1d(TyD);
+ if (1) test_pmull2_1q_2d_2d(TyD);
+
+return 0;
}
diff --git a/none/tests/arm64/fp_and_simd.stdout.exp b/none/tests/arm64/fp_and_simd.stdout.exp
index 04fe205..c1ee8df 100644
--- a/none/tests/arm64/fp_and_simd.stdout.exp
+++ b/none/tests/arm64/fp_and_simd.stdout.exp
@@ -28793,3 +28793,719 @@
xtn2 v8.8h, v7.4s84dc03eb98680d7370a20b36262e4d85 03eb0d730b364d8567181415788bf1b7 fpsr=00000000
xtn v8.8b, v7.8h2ca8635ab8c96385922e6ada920bfd94 0000000000000000a85ac9852eda0b94 fpsr=00000000
xtn2 v8.16b, v7.8hcb1fb88391120d19091694424470869f 1f8312191642709f078822ac5f050d24 fpsr=00000000
+aesd v6.16b, v27.16b ad3c6e02b07fb70d9fd77489491a1302 739d536739e995431983556db1388e96 e1fd94bc9c947bb6f2f175aedc358be7 739d536739e995431983556db1388e96 fpsr=00000000
+aesd v6.16b, v27.16b 6a5ead74eeb3b9815ad00525782dec40 9d5c678e38c8da85c06cb0684f364ebb b27800142644d2304a6a1a6537031063 9d5c678e38c8da85c06cb0684f364ebb fpsr=00000000
+aesd v6.16b, v27.16b c1ec8190d147c9c125fb7f908222e72f fb81e698f37f844b0e7dcb69dd8f8948 84dc65bfa218c6cf94b345690b760a0a fb81e698f37f844b0e7dcb69dd8f8948 fpsr=00000000
+randV128: 9728 calls, 10055 iters
+aesd v6.16b, v27.16b ecea3363ccecf67463980750bd239e1d 1a0877230e10be492570ec1c59f5e287 aec8d472d64a3c8ba83b015d98558637 1a0877230e10be492570ec1c59f5e287 fpsr=00000000
+aesd v6.16b, v27.16b d079abd022ef8de2209bc2fd4fd2ed1a 5a1a823b3344761afa896f5da6563841 eb39633ccf4f18e1e300b5477a0e4c57 5a1a823b3344761afa896f5da6563841 fpsr=00000000
+aesd v6.16b, v27.16b 080cb0c0566aab73a4675f4ff17bd71e 862af10e4d680dc72f62aa7c1c297fbb 5336c5ece64877c644236f66ce6af829 862af10e4d680dc72f62aa7c1c297fbb fpsr=00000000
+aesd v6.16b, v27.16b f384a210c73caf094fdd3b280500bb0b fd16247abc5ae23123ddfe591b4f19d4 e9526558d792077603741a2cb8d3dcef fd16247abc5ae23123ddfe591b4f19d4 fpsr=00000000
+aesd v6.16b, v27.16b f1c1dfa3d544fa8282dbb866eb3ffabf 1fbf7c61e1fb553637d8cad404a8656e 61d51ba899851ec6288a6e3ed2f47151 1fbf7c61e1fb553637d8cad404a8656e fpsr=00000000
+aesd v6.16b, v27.16b 63a2c958e164ebbf9c4236ea0219f31b 4d0558a11b2bc6b7ca346ecc3614c467 280ffa69c3f35ebf1489b223b992ac01 4d0558a11b2bc6b7ca346ecc3614c467 fpsr=00000000
+aesd v6.16b, v27.16b a809c00f4a7ae2a0fdf11394aa6f0600 e6c8191bcaca96943cd14b23127395a0 9a54ca9bb6c45e283add2220ddfce547 e6c8191bcaca96943cd14b23127395a0 fpsr=00000000
+aesd v6.16b, v27.16b 21d523a77167400406cab144441f944c 4ae71eaf4fb825acee8fc0b7f7a538f9 4b68bcbf05c02c6fd1a1aa7ec8ef8bd2 4ae71eaf4fb825acee8fc0b7f7a538f9 fpsr=00000000
+aesd v6.16b, v27.16b 2de55201b50b64cd16ab70da2f0afce0 da44c73d09d5d2e13f4d2e6a458a0e52 58f5796d263a9d4278f104fc4c9cad3e da44c73d09d5d2e13f4d2e6a458a0e52 fpsr=00000000
+aesd v6.16b, v27.16b 2c1aaefe7646afda8e76af36cb0f9f9b f5be75a45901fd128fedf41a5d01768b 35e84846e5d757b14e1deb4209169f7c f5be75a45901fd128fedf41a5d01768b fpsr=00000000
+aesd v6.16b, v27.16b 7f54967c15f8800acd09ce377910db5f fb3487c69e1b061e3f4e72a89eecd084 b016dcc04f55789bce909e6e044de39f fb3487c69e1b061e3f4e72a89eecd084 fpsr=00000000
+aesd v6.16b, v27.16b 85736a5cf101373e33452dbf98ec130b 4d875d8138044ee6ae4f08f468297d1c 17a3afc9b107c22d12ba45cc7536b287 4d875d8138044ee6ae4f08f468297d1c fpsr=00000000
+aesd v6.16b, v27.16b 9e578b7e6a403556210a2dac8882a47e 4b9758b7889d344a3dd118de1c99dc34 e79f0912b544d9c43b1fc11ec4c9a95c 4b9758b7889d344a3dd118de1c99dc34 fpsr=00000000
+aesd v6.16b, v27.16b 2be058c1e196d933f6382ee0aab3f099 5344d746edc4192a4bb4ff46191c4ead 4bf01feac11b518e811d5ac5cd487328 5344d746edc4192a4bb4ff46191c4ead fpsr=00000000
+aesd v6.16b, v27.16b 8bee3107b5e483b213af8e395d5f573d c76e3b0fc85a5c6638d81f0bc0923265 7502efbf5d80ac19133abca10b5aa35e c76e3b0fc85a5c6638d81f0bc0923265 fpsr=00000000
+aesd v6.16b, v27.16b 1f60772e460894b6d74faf9802663748 07f5e3f2783f5dde651dd70f70dbe83d 1e48129334cdc1f7d1adef853eb2e73f 07f5e3f2783f5dde651dd70f70dbe83d fpsr=00000000
+aesd v6.16b, v27.16b 45188918f5e36b1ea2f7f1dcf8a8f39b 71b82fcf5d527d723163873089d6d115 2ce7ff0d288a0fb86f4794832256c5e6 71b82fcf5d527d723163873089d6d115 fpsr=00000000
+aesd v6.16b, v27.16b 60f4c8a3225569c9d589b3e79f05e815 68998085d8751b01fd8a904f6c654ccd 7ed51e23bf9032b114b31d6fee54d42d 68998085d8751b01fd8a904f6c654ccd fpsr=00000000
+aesd v6.16b, v27.16b cdd593b02b3dec99cfe35598585d7898 497635f64887986d2871524c7866b944 5474ca984f4938ba0071dd19b0c0c593 497635f64887986d2871524c7866b944 fpsr=00000000
+aesd v6.16b, v27.16b ee9b4a1f727d576cf0e637ce828f0203 7630ae000d67539412f92b070eba795c f0cb30cbe2d9c4e16b0e03123b43ae84 7630ae000d67539412f92b070eba795c fpsr=00000000
+aesd v6.16b, v27.16b 23264ed057f407239972ba6b7e7de735 4ea84c8588f6ac571b037d608c41ebf3 042c0eedb36d31caefe6819e116a6ac7 4ea84c8588f6ac571b037d608c41ebf3 fpsr=00000000
+aesd v6.16b, v27.16b cb56fea238815e9e29673e4daa05860f 32bb6f6318140396a46da83755db70ea 7da38ddd699c35bf5453d6bdb4adac2a 32bb6f6318140396a46da83755db70ea fpsr=00000000
+aesd v6.16b, v27.16b 460abb777805bcbd00a5215569083f71 814c757b1da1b9310d180b6bc6686721 1bcd3681319095f0bc985ed1f31dec6c 814c757b1da1b9310d180b6bc6686721 fpsr=00000000
+aesd v6.16b, v27.16b f424e42e746080607f0bc5631866733c 9b3ac0adf87d2e08b4e406de41c83079 1561be4106be33f7f0e964cd59dea668 9b3ac0adf87d2e08b4e406de41c83079 fpsr=00000000
+aesd v6.16b, v27.16b 3682d9a68e720a67067b8a5719ff814d e165afd90888c1fafbb0f96e25db2ccf 6d59596b0da68f75dcb0185b21140f11 e165afd90888c1fafbb0f96e25db2ccf fpsr=00000000
+aesd v6.16b, v27.16b 6c05fbc0251bbab1f3d3cf11ccb3c987 b2aca3deaea1d2e9425e45fcd380ba06 cbb4f7e99c66cf5eceb78f5356c05e91 b2aca3deaea1d2e9425e45fcd380ba06 fpsr=00000000
+aesd v6.16b, v27.16b f48da95c9a3bf120a8f5f4708f61acc9 6ff0fb9e49aac1b3e8cc4968aa993afd c25b08a8e8e1cd22a913353472ac4828 6ff0fb9e49aac1b3e8cc4968aa993afd fpsr=00000000
+aesd v6.16b, v27.16b 30fa435a4cb20e9285bf5956c4eb89f2 771218f73981ef394ddc66920b040d93 5f00e0181661250e3fc84f88b16657d8 771218f73981ef394ddc66920b040d93 fpsr=00000000
+aesd v6.16b, v27.16b 2af058cadf07bb5bd26cfb5a54a292aa 8da508d99c81ec6f2bc5ac931bae0d0e 92b7da828981da2864ed6e1269dc6c1d 8da508d99c81ec6f2bc5ac931bae0d0e fpsr=00000000
+aesd v6.16b, v27.16b e96b1ef89a1d86f9d65d69a0e8532a20 ed42b59f0c84ce7fcea9779b8f0ee08f 0abad40a308de9dc354c104934f90e1b ed42b59f0c84ce7fcea9779b8f0ee08f fpsr=00000000
+aesd v6.16b, v27.16b 1363c75fcba1aff3b98f0e4324f734d6 51541fd8086f65a2e8c65239c5da7d08 e0a410eaf6faa77033b2a4bd70ec2d9c 51541fd8086f65a2e8c65239c5da7d08 fpsr=00000000
+aesd v6.16b, v27.16b 18bba562f32113bad9fc9d4d1cf04559 edbb5450e210bfa0636ed3536fcefb29 8f74aaa177d1b643e3525ae9c02e2bd0 edbb5450e210bfa0636ed3536fcefb29 fpsr=00000000
+aesd v6.16b, v27.16b 075ffc9cdbded89459b649b57785a713 504f4555819aa491ea5603b2501943f1 3da00112da1c5c36467cae384b86db3b 504f4555819aa491ea5603b2501943f1 fpsr=00000000
+aesd v6.16b, v27.16b dd1059319baa20f37ecfc98578bf954d f37ed68061f18e9e5a3eabc01f1e79f2 0a2bbe56c3f1abb314458368a65773f4 f37ed68061f18e9e5a3eabc01f1e79f2 fpsr=00000000
+aesd v6.16b, v27.16b 4a92530d7e9e5eb0f1cf93555fffa9da 4f2b9966be5424d760f6b995600539c3 255bbd053614950a1fdb961fac10108e 4f2b9966be5424d760f6b995600539c3 fpsr=00000000
+aesd v6.16b, v27.16b b56b1ddc388375a510e91c4f709a338b de707d888fd16358600e91cc74bad158 30b0fffd0554b42120443b41d04890a9 de707d888fd16358600e91cc74bad158 fpsr=00000000
+aesd v6.16b, v27.16b 92e993cdf07e325e166ca690b3d078e3 7752e50575dda055df864181d3827c4e 90bb74b12a48b09e67fe30e312710f18 7752e50575dda055df864181d3827c4e fpsr=00000000
+aesd v6.16b, v27.16b 44eb16c00571f5bb63388ff68782d8c3 7cb131bbd0583cae3d3f2a93da3d9983 8d38120376f4292fb546f8bc9d4c3d72 7cb131bbd0583cae3d3f2a93da3d9983 fpsr=00000000
+aesd v6.16b, v27.16b 28530594d83a1f9c582d39624d8eb10b 4d6dc28b01229743db18abe4ebcb88d8 c5d997cbbc6874efe5d15bdc413431a9 4d6dc28b01229743db18abe4ebcb88d8 fpsr=00000000
+aesd v6.16b, v27.16b a0ffc02ac7ba0fe0552a04b464d5669b 4865f854671b10f318f32552660caa2d 6ae5cb8ac8e57b82473727f565f17679 4865f854671b10f318f32552660caa2d fpsr=00000000
+aesd v6.16b, v27.16b 0bd0a76335d12669b8114fcb2c365453 d07b31f8632207a054aff7bea9df5e61 675a7be89feb9a12b90ea33f837e35a1 d07b31f8632207a054aff7bea9df5e61 fpsr=00000000
+aesd v6.16b, v27.16b caa71b1d7f5ec315e3c07a890693dd13 428dd0565419dc28f02b810816260456 7c3ccbcc97d2638b0b95e59182165968 428dd0565419dc28f02b810816260456 fpsr=00000000
+aesd v6.16b, v27.16b 3c627c39074346c53618e5cc51cb60ba 36eb1351c08c8ca54b99e1a6df4e0e6b e69110f7a367309031f24558135f0651 36eb1351c08c8ca54b99e1a6df4e0e6b fpsr=00000000
+aesd v6.16b, v27.16b 6928b9be9652a24cc6e73fb6ed8ba9ff 2a4129a4d9f77dbf4db3025708d21c52 2afdef4364158b7e92e4d2e0ce299618 2a4129a4d9f77dbf4db3025708d21c52 fpsr=00000000
+aesd v6.16b, v27.16b de71c48aa75553a8c0e632da166a6673 c02c9d891e69c40d6625d2bd93e19652 673385d5e9cea029db8d170ac56d157b c02c9d891e69c40d6625d2bd93e19652 fpsr=00000000
+aesd v6.16b, v27.16b be37b48f2ec7626099265e5be83c9627 5a8cccdff1c1c26ff6d0b3b9df5bd949 b2d6476cae0a53fbeffe923b06a5c145 5a8cccdff1c1c26ff6d0b3b9df5bd949 fpsr=00000000
+aesd v6.16b, v27.16b 695ae8ae89882f54b287221bc4e198fb 57411888b1e1d6c55e95042b4c1f4718 97396923d10c23ac7644ef0883e4174d 57411888b1e1d6c55e95042b4c1f4718 fpsr=00000000
+aese v6.16b, v27.16b 40bac0c61b781b646ae9dff80a38cdcf 182be162bfa760eefc5126f23b0e3f9f 496c89499005fd7ec78121676a9e9953 182be162bfa760eefc5126f23b0e3f9f fpsr=00000000
+aese v6.16b, v27.16b a2369db94177856f222bf4d318239483 fc2a864e7af5c1cc33e778f00b0922bd e24b4e6882e5af0a7d9c1b26581364b2 fc2a864e7af5c1cc33e778f00b0922bd fpsr=00000000
+aese v6.16b, v27.16b f0afde665d64ce57392fc18c50804ef7 631e672c42a9583d60365a041cee4f54 c0d47cd6cb9f560229c890c4dcbd140a 631e672c42a9583d60365a041cee4f54 fpsr=00000000
+aese v6.16b, v27.16b 8906e3accf2054fa0fd3a6031230590a aee6e4dc78a48522e61e2d0dcf9e2742 a9bdf3511ee4c561c1e13eabcc5f3d52 aee6e4dc78a48522e61e2d0dcf9e2742 fpsr=00000000
+aese v6.16b, v27.16b cd190d6cf58c7a3904f80418bd13189e 3c635e3e7bc6a95b227e50ec83f80869 1944ca00f7e9edaab2da66bfa1d62068 3c635e3e7bc6a95b227e50ec83f80869 fpsr=00000000
+aese v6.16b, v27.16b 1cc9bb8732869df4797e3babb109e891 6d753531abef23c87637248299de54a7 ee3b654e760e19eb3465aea5a3f9c005 6d753531abef23c87637248299de54a7 fpsr=00000000
+aese v6.16b, v27.16b d7f64edbe3ef1f0bce45aa9c4ef22bc4 a2fdc79769fe5449412a07ad702f6bdd 7ea8092973c1a72cb22bb3c79d8295d4 a2fdc79769fe5449412a07ad702f6bdd fpsr=00000000
+aese v6.16b, v27.16b 5e7f25496aa7605e612db1caf5ae4017 3bd8764e14d59bbee4355c4e68caaceb f3adcec59743ede15e5c0f5f4d4055b0 3bd8764e14d59bbee4355c4e68caaceb fpsr=00000000
+aese v6.16b, v27.16b 1046a0b0268dbecc9516b016061d886a 96e9a2380d535807bd398044e19177b1 f11516c43464771f94798e00441d04b9 96e9a2380d535807bd398044e19177b1 fpsr=00000000
+aese v6.16b, v27.16b 4d2920f278839c37c7e00861df1e629d 150faa33b357ec032f15d5713d622d0f 1fe684789b107e1898f751ca6a48c14f 150faa33b357ec032f15d5713d622d0f fpsr=00000000
+aese v6.16b, v27.16b 750a04eebf67577d596a1989e2932f8f 172aee2066c2b69397abbbb4d91e2de4 3578778b8b5d8728e2b7f827aa063a7f 172aee2066c2b69397abbbb4d91e2de4 fpsr=00000000
+aese v6.16b, v27.16b fd19cedf8774169858da90ec17a5d712 fd2e982d2758730db83eadcf07934a2d e0695e89e105b12aca9a4d2663712775 fd2e982d2758730db83eadcf07934a2d fpsr=00000000
+aese v6.16b, v27.16b 26bdab4f754d6df0cf81b7fa56d78c77 56fbbb4e78c65f8d9d1ecef5155af893 d7db927c005dcaff1a5a2376513db669 56fbbb4e78c65f8d9d1ecef5155af893 fpsr=00000000
+aese v6.16b, v27.16b f3f7e552902d1a7c5e828dbef693abf4 eb5413380eb2f9f93050780a9d2569ca 0bb525029f4e42977f0a118daddbe6b2 eb5413380eb2f9f93050780a9d2569ca fpsr=00000000
+aese v6.16b, v27.16b c3a5dac739f47e1b64bb741858bb956a 1a1bfecc49fea131d3b20aedfed2fcb0 5101f92ba9f936e524ae9ee63567f357 1a1bfecc49fea131d3b20aedfed2fcb0 fpsr=00000000
+aese v6.16b, v27.16b f6a8ec8dcf81f8af420dcbe8dc2da9b7 452edfea8988b714e626e47d99421226 5af1ea8549a8c3ea6e44842a6d011581 452edfea8988b714e626e47d99421226 fpsr=00000000
+aese v6.16b, v27.16b eddf7b85b3b6e8175658f30ee0cb47bb cc6e13712f319c84c88a679bcd550a0c deb5e3bf0b0b45dcd8c8922afd1722a9 cc6e13712f319c84c88a679bcd550a0c fpsr=00000000
+randV128: 9984 calls, 10317 iters
+aese v6.16b, v27.16b 062ce68f4471af32037c4b6ac673d058 0ebbfc439bd9b060d9bff227faeb4441 9e2e224b5746a200eb88c0e330c256d4 0ebbfc439bd9b060d9bff227faeb4441 fpsr=00000000
+aese v6.16b, v27.16b a46e8d8ce293ace2a65833dbee06a36d 6bf5f93f2b60518779a5e50181e420a7 dd54ec6d9e98924da81454578a0df674 6bf5f93f2b60518779a5e50181e420a7 fpsr=00000000
+aese v6.16b, v27.16b 2584d059eefc4005a2ce0c43b76420d9 44fb6b4441a6e1da091ca109c120ff1c 79b59ea4621bea9e38d232d6efbe95a6 44fb6b4441a6e1da091ca109c120ff1c fpsr=00000000
+aese v6.16b, v27.16b e94f10d9c78cc97c54bc3580816da87e f8afb1333d8bc039e803851f1b7e4182 2d081e87657d326eb8e101db82c5e7b0 f8afb1333d8bc039e803851f1b7e4182 fpsr=00000000
+aese v6.16b, v27.16b 50b0adebce23aa271e040f73ac019a3a e7ef2bec7eee4d84773cf223eee045b7 e7079ec5f9f8440a2ccf9453a9bd545d e7ef2bec7eee4d84773cf223eee045b7 fpsr=00000000
+aese v6.16b, v27.16b bb85056e61a140e65f84f9fc99ff57ee 729c3a4f64b0e89b15a547f49a246b9c 6bfdebfdd6b975ff7bd4c230dd82ae40 729c3a4f64b0e89b15a547f49a246b9c fpsr=00000000
+aese v6.16b, v27.16b 89af7a44e3e5ed98781d53fba7493e7a f8973d3c4fb2f15e231fe4747f2b1311 9177d8bc39aaa0b461079c73a35ba97f f8973d3c4fb2f15e231fe4747f2b1311 fpsr=00000000
+aese v6.16b, v27.16b 1b0d6c4bb1d1111fc7af7d5037bdafbe 6b07214774db1d78622b6fe10ddd898b a65ff7fe06d0e3858067fec85167c996 6b07214774db1d78622b6fe10ddd898b fpsr=00000000
+aese v6.16b, v27.16b 76f2a134b6f1cf670cc778fc77026b2a 9679213d6a4586a079f7a65a13965e46 860496019d22cdc6433d3b24e18d1d50 9679213d6a4586a079f7a65a13965e46 fpsr=00000000
+aese v6.16b, v27.16b 2e12c1fef2ef646da7b42ec54992db8f 74d00d959e05d5cdb86b1e5a8a292eea 509ee67fc0ea4be02e25c8dbbe87044d 74d00d959e05d5cdb86b1e5a8a292eea fpsr=00000000
+aese v6.16b, v27.16b 620056d2b3ace79f3231adbcd4654d03 65ec462f70fd6bdd7d6836bfd3785755 2ecba25484a4ca2cc5ce647bc5d114b1 65ec462f70fd6bdd7d6836bfd3785755 fpsr=00000000
+aese v6.16b, v27.16b 719bbf915a07b9dd0c2055c1785a2168 caac2beb3e0ba7b12ace4e6a4d613b69 4328a2daf7e22250969a7262eafeaf7c caac2beb3e0ba7b12ace4e6a4d613b69 fpsr=00000000
+aese v6.16b, v27.16b bbc25c1945e23807966084b39653b89c 02f21da96b11e9291f7cc73b58c53a04 319c13e7a79083318b043ec4560d1a46 02f21da96b11e9291f7cc73b58c53a04 fpsr=00000000
+aese v6.16b, v27.16b a1568e4bd71bc7fd2fd09c748d2e7180 6e9d7b4854ed9224bb5400125484b207 ec5f2e7b22ace635351ffc338a42de17 6e9d7b4854ed9224bb5400125484b207 fpsr=00000000
+aese v6.16b, v27.16b 8237b4076d94c39f3751fce2beccadf4 6d8ca5a95b8001845e3559cfa27e0552 0543c2e4f93782af9cea25d8dffa0624 6d8ca5a95b8001845e3559cfa27e0552 fpsr=00000000
+aese v6.16b, v27.16b be452e2c692b8ecc0fc405de880dcbd8 5fa0fbaddfaa962869fe3352a29393c5 4e806a0c330b0369e5d9ad64f80c05a4 5fa0fbaddfaa962869fe3352a29393c5 fpsr=00000000
+aese v6.16b, v27.16b b6605d9c2ac18766160716494bd12b0c a5b9de32414ab2ef3b90ed7bb3a3bb3f 7f8860e4d840eca7413596237d3d0fc3 a5b9de32414ab2ef3b90ed7bb3a3bb3f fpsr=00000000
+aese v6.16b, v27.16b c968a13511360f4badfb900168f82e6f 9eb7ae19e042b5ba34cbe829358ddda2 a1040d71ee9d76a14c9ef4345b92bcbd 9eb7ae19e042b5ba34cbe829358ddda2 fpsr=00000000
+aese v6.16b, v27.16b 583d58d97d6a855c337fd2e63e6233e3 aa7aca411c71fd69b58f833d88335acc ef8cf94644d14f964ea0bcb989afd115 aa7aca411c71fd69b58f833d88335acc fpsr=00000000
+aese v6.16b, v27.16b c2bee466cf3c4a7908753cda2eee9a46 2ae2928c56b6ecdd1dbc1e980d73919f eedd2b87595e3849264a242c9b7e9335 2ae2928c56b6ecdd1dbc1e980d73919f fpsr=00000000
+aese v6.16b, v27.16b 67cda5bd658ebc828dbc2ebc977ec479 7dcf66d9edf2e2f3cc321a18232ee2f9 c419f74383532ea38d775849a21018cd 7dcf66d9edf2e2f3cc321a18232ee2f9 fpsr=00000000
+aese v6.16b, v27.16b a848f9bea23e3e572133096bd9f0105c 0420a70742053d8e23d1d69e2b44aebb e198ae56778d583589457be691e29e94 0420a70742053d8e23d1d69e2b44aebb fpsr=00000000
+aese v6.16b, v27.16b e4104349e32e2dd824bb2dc95525decf 1db7b4f8b4cf608d8278b20a849554c5 5b2e7ec824e768fc3e5ce32e99f8db67 1db7b4f8b4cf608d8278b20a849554c5 fpsr=00000000
+aese v6.16b, v27.16b 2b72ee8aa330a8cf47090f3b8e0134f6 67271c86c2e4e605cce14b456c3c8bb3 ef9b08fe3d27897498fc2ff329481b6e 67271c86c2e4e605cce14b456c3c8bb3 fpsr=00000000
+aese v6.16b, v27.16b 8b32b49e70087736d4624c13aa67af30 fca38dbdb5a56dc74a8868299b0da3a2 a687fe260b0212a1c781a280f595364f fca38dbdb5a56dc74a8868299b0da3a2 fpsr=00000000
+aese v6.16b, v27.16b 9fd766147a372ca08964ca7037a92452 dcfcc18ffd34334687cf9ccb53300e31 1762e514abee5c8e43f1c0ea1a7bb1fb dcfcc18ffd34334687cf9ccb53300e31 fpsr=00000000
+aese v6.16b, v27.16b c74165cc219c28eec4efe83495a5f43b 67121adafb729760e498490bf5862b3f 57f59e47b726d219d0ed0875e02832f2 67121adafb729760e498490bf5862b3f fpsr=00000000
+aese v6.16b, v27.16b 625010a5c619ca00e7e3063d253d7ecc fec5f77f0e40faf6c0c1cfc8e0ef5bad e8933f57ccb59442a62a04e6decbddef fec5f77f0e40faf6c0c1cfc8e0ef5bad fpsr=00000000
+aese v6.16b, v27.16b d0e3c881c88c72b65220856c474f22e6 00f5b95e967cbbe87b2b8de4754bfd5b 582b9e9ea5f2a3582347ddc4708c307a 00f5b95e967cbbe87b2b8de4754bfd5b fpsr=00000000
+aese v6.16b, v27.16b 71dceb3e87d681f06485c4a159bc4167 cd82bf57f4063a1576b6e33d137a7129 8fc304f9c9b420d9d658eade6570cc2f cd82bf57f4063a1576b6e33d137a7129 fpsr=00000000
+aese v6.16b, v27.16b a619dcbe64d7568e7df423bcbd643a30 c64b694a87c0d85f104131b51a5b18f7 11d593bf3c75d53e5c001901d0f0c9c6 c64b694a87c0d85f104131b51a5b18f7 fpsr=00000000
+aese v6.16b, v27.16b cf7bf8dfbf6f526ffe4b039dd2276e20 4a321817b089f4a4a9aed82aebd051a5 76d975e85b68e11f123b24a9978eb997 4a321817b089f4a4a9aed82aebd051a5 fpsr=00000000
+aese v6.16b, v27.16b 4ae2a182f67ed475466cc323f9e43b19 b9152b9dce40eec6a2db387de5b77c13 07a9a0c069ed7e6d9c6880580db20f67 b9152b9dce40eec6a2db387de5b77c13 fpsr=00000000
+aesimc v6.16b, v27.16b 792e37876be33c7eb535c430917d04fa 74d502be41c727a35aaaaf8e68f1fa20 cdce819f0f496d2913c25f5febdcff8b 74d502be41c727a35aaaaf8e68f1fa20 fpsr=00000000
+aesimc v6.16b, v27.16b bc3f18ce7e80eb6bac8765a2fbd026a2 db53fe586afcff1c32f99f3dd55e2aae 17316e6614966b9ca245dd5385c96427 db53fe586afcff1c32f99f3dd55e2aae fpsr=00000000
+aesimc v6.16b, v27.16b 72f5a6378d33401c8a42065a96be03f2 4c6d7e4ca8c0d41189a9686a8bde6d9b 0f201b2798cba55bd4e17166d2b769af 4c6d7e4ca8c0d41189a9686a8bde6d9b fpsr=00000000
+aesimc v6.16b, v27.16b fb3041a1fbde9b71b0460838c228fbca 2903e37a5cf30862bf9a68f4eb5122c8 d6f461f0dc7319735e75e072428a2bb3 2903e37a5cf30862bf9a68f4eb5122c8 fpsr=00000000
+aesimc v6.16b, v27.16b b7cf48ee255f5d4a7c72ca1cdfec6c0b d2f78cc2e575fbef35ac02bd5497a915 8f77079441d84c51efcc9491a59ea6e2 d2f78cc2e575fbef35ac02bd5497a915 fpsr=00000000
+aesimc v6.16b, v27.16b 07b41bfc6d97e58651a8ace64eebb892 a528d904a3250b974abf93a326906362 f17f2df397060b807d893504d97ae9fd a528d904a3250b974abf93a326906362 fpsr=00000000
+aesimc v6.16b, v27.16b 4bbd1bac326694078cc60f766f043f42 05752b20f6e59a3c5fb27d87c21baf8f 7954a1f7b8e0a548d308df1387a403d9 05752b20f6e59a3c5fb27d87c21baf8f fpsr=00000000
+aesimc v6.16b, v27.16b e1cba7ded5abc8ab8fad52aca01960fa 4fc0e1f53f9408bcd2671f49871aed7b 813e0226199e10885c144ce784f7f880 4fc0e1f53f9408bcd2671f49871aed7b fpsr=00000000
+aesimc v6.16b, v27.16b 2bbe1f72b548e454ba3dd66744087b99 e5e75b65de11b4f906bcdac9d56b7e08 f71a31e0dde7a810488addb63c491ca1 e5e75b65de11b4f906bcdac9d56b7e08 fpsr=00000000
+aesimc v6.16b, v27.16b 8976e448321b45e06b57fa88b8b3f101 26cbfa4e323dfed158920de70defc114 0c8f62b8c985452949e95cdcb66514f0 26cbfa4e323dfed158920de70defc114 fpsr=00000000
+aesimc v6.16b, v27.16b 59d35540ad064d3005d81ef05ef82110 734c1d919bf847252aca18838e861781 53374097a86e76b125a0e11fc0887ea8 734c1d919bf847252aca18838e861781 fpsr=00000000
+aesimc v6.16b, v27.16b feb4d23985e75c24e5a3a37d95b86ba7 2b4a250e7922eed5dc425c7cb910df2d 75afef7f1d284a1f88a46ffdbc186c93 2b4a250e7922eed5dc425c7cb910df2d fpsr=00000000
+aesimc v6.16b, v27.16b d5fbbc151b9fd19c6d97e810bed330a6 aea471a52d9b53c0ccda38b4ed6d79f9 9dc0e566198d2d9ce7733c32a3103784 aea471a52d9b53c0ccda38b4ed6d79f9 fpsr=00000000
+aesimc v6.16b, v27.16b 408673b2ce0e0c77fc934d893829cfed 5d3c61361643d7c85c740d098a7c46c5 e64bb62db4dfe1c0fe9cf7b9f9a9dffa 5d3c61361643d7c85c740d098a7c46c5 fpsr=00000000
+aesimc v6.16b, v27.16b 9e3655f1fe146d97f37933c7639aa85c 97f156a195f9d9cbecef3a5cf11fa570 a7135f7aa14a118482739e0a5b87799e 97f156a195f9d9cbecef3a5cf11fa570 fpsr=00000000
+aesimc v6.16b, v27.16b 50ecc4b30c9155dab127f9aca0061cd3 bda2afc5099fb9abdb2a1f8d8134f6dc f5eb0d6668b0cb971c2f1e4ef7c3a50e bda2afc5099fb9abdb2a1f8d8134f6dc fpsr=00000000
+aesimc v6.16b, v27.16b b5861fd657652421967e00164e4c8a31 2e30cc84d213d84689071d7c9a9c9ae8 143a5a225854ecbfc821999f87a26f3e 2e30cc84d213d84689071d7c9a9c9ae8 fpsr=00000000
+aesimc v6.16b, v27.16b 2ee4c73a3f6f384d035ea7e7cd4e5358 4a7b0ebc5137967d566493099d37f073 41df1805b141770a4e30c0168f09b01f 4a7b0ebc5137967d566493099d37f073 fpsr=00000000
+aesimc v6.16b, v27.16b 19e81bc12590f33c57a74efd7eead626 7263d54ee5e95130a322e114e9e5595e 1643be619a90f4933c1a96c439749fd9 7263d54ee5e95130a322e114e9e5595e fpsr=00000000
+aesimc v6.16b, v27.16b d9717c4a68a9b5cff3395639c001737c 05c87f1aef0a6b3fd021687cdf863489 57b3662a3c41c10dc93ba0b7778d4f51 05c87f1aef0a6b3fd021687cdf863489 fpsr=00000000
+aesimc v6.16b, v27.16b cb5e49b46998dce535f41e7bf4738b3a 638a6e00ce7a448a3c418723defae1d4 428e5a11df63a167936381a8af93b29f 638a6e00ce7a448a3c418723defae1d4 fpsr=00000000
+aesimc v6.16b, v27.16b 5191e2e0863ecb6080b706a379207d40 ed8801e0e2183af047629fe74621c11f a2315d4a20d19859d289b0b6d8113646 ed8801e0e2183af047629fe74621c11f fpsr=00000000
+aesimc v6.16b, v27.16b cae8a8af227bdf1f31636f91afe8aa6e 02a4999a8bc6af5351630fa978da334a 89f1439efe70a39c815aeca372aa9497 02a4999a8bc6af5351630fa978da334a fpsr=00000000
+aesimc v6.16b, v27.16b 9744faff9a2f7a01aad9b824f7aa70a4 02bc950d2a620391bb263749d3079835 7b24a0d9b343351ff81aa9a8afe01620 02bc950d2a620391bb263749d3079835 fpsr=00000000
+aesimc v6.16b, v27.16b 178538b15039fbe74bf7423eb04832c1 4eb1561b1fce958ce48978a7b7864ebf d19fb64aeeb6ef7f71be92eff49a9638 4eb1561b1fce958ce48978a7b7864ebf fpsr=00000000
+aesimc v6.16b, v27.16b aa8bc3a5a47bc3b1729e6cbd3ba04da7 46643aa2c8e8c5222d6d31a38538b8ca 630870a196080e5742e0e1910251ba26 46643aa2c8e8c5222d6d31a38538b8ca fpsr=00000000
+aesimc v6.16b, v27.16b 48b3a4838891f434f5b2c21d9dfd3334 7edfc4381afe34f6feb33985451dc240 afb4afe96c000e4401c93f0635921d60 7edfc4381afe34f6feb33985451dc240 fpsr=00000000
+aesimc v6.16b, v27.16b b67ef19ebca981a29c388cf45db521de 73497c08c0b579a1826a94497b821131 b12a22f762bd9ae8d1abade217dad4c0 73497c08c0b579a1826a94497b821131 fpsr=00000000
+aesimc v6.16b, v27.16b 3100fc6309c2421992aea89fda27f0f2 7794749d59f7277d6c1586526eaabe9f ee37f92ae7bb6ac227528c5476617785 7794749d59f7277d6c1586526eaabe9f fpsr=00000000
+aesimc v6.16b, v27.16b d50cc09d5758a4e426b121e8fa754e7d ced212e49d99e99e4886c3d254ee4378 3cc92f30964b04aa00372ec6b50abb85 ced212e49d99e99e4886c3d254ee4378 fpsr=00000000
+aesimc v6.16b, v27.16b b6d547c3818437207cc28f15a6075d6d 200f93cda4dee4707359677d7d91d185 cfa09e80d37b54129436e0721f0dd872 200f93cda4dee4707359677d7d91d185 fpsr=00000000
+randV128: 10240 calls, 10580 iters
+aesimc v6.16b, v27.16b 476bf72ac340e9c91743ea4a2d279a8f c0bd400f881de94f524f48da153ec7f4 ca002ed632cf35fbaa8cb51c71b5934f c0bd400f881de94f524f48da153ec7f4 fpsr=00000000
+aesimc v6.16b, v27.16b 19847f0098518dbedbafe6b5c5f01718 5cc09807b9650bbedc76898f37ffe791 ccc90e08458b25828e4b98f134ee83e7 5cc09807b9650bbedc76898f37ffe791 fpsr=00000000
+aesimc v6.16b, v27.16b f73a8b3082f12e2f1e7bbb9ea8cca501 9b584c9117b484617ef57bfabb4b7145 1022fbd7c1d0de89239e3285e736beab 9b584c9117b484617ef57bfabb4b7145 fpsr=00000000
+aesimc v6.16b, v27.16b 406d7b9ae2002efc4088c8e4339ba62b 8b8b774b9b2780cb831d9111d69440dd 0a618ed959d7b7ce1ae434d4d352e0be 8b8b774b9b2780cb831d9111d69440dd fpsr=00000000
+aesimc v6.16b, v27.16b 84c74ad9dce6f7c3887fef7266034475 e9bd93b0dfe1218669cf46081453804a 4ac3de2085275269fe401a4c4730d228 e9bd93b0dfe1218669cf46081453804a fpsr=00000000
+aesimc v6.16b, v27.16b ee5e5359038ab241b049323f4e2f4eb1 a21c027f88b991cc1d72a48eebb5a327 346d099345358498a92a9a5c0327e41a a21c027f88b991cc1d72a48eebb5a327 fpsr=00000000
+aesimc v6.16b, v27.16b 7b0a39ead7b444746feba54117664185 17882697f6902f7f02e60a81bb9a0854 8d94e0d72b509ed30588d3313c757541 17882697f6902f7f02e60a81bb9a0854 fpsr=00000000
+aesimc v6.16b, v27.16b a7e15eda8a465c7d750bd9c2e5e210b0 632cb1cf4c0a735b3c900ef47d6748c9 e7b15730adea4e67af883140f5f2ed71 632cb1cf4c0a735b3c900ef47d6748c9 fpsr=00000000
+aesimc v6.16b, v27.16b b3060b26a3bb77a7d8c17031c86c1a1d 2c8001e175baa063d9c53ed21d6e0a2d 0346b6bf4c1a81db4f90537ce35d5cb6 2c8001e175baa063d9c53ed21d6e0a2d fpsr=00000000
+aesimc v6.16b, v27.16b 9ad98c5ca1cee1dd8ae82fadc51a8679 6979ff159c80742f5f636ef5ef0f8638 9499ed1a257b435a3c9d585e7d90a81b 6979ff159c80742f5f636ef5ef0f8638 fpsr=00000000
+aesimc v6.16b, v27.16b bc38415ce561f8ffec5f76183bcab5a5 79f7084a203e4f9f2b4aff3e522b1ccb 36c4c4fa0654ee72ab9424bbf1ddf87a 79f7084a203e4f9f2b4aff3e522b1ccb fpsr=00000000
+aesimc v6.16b, v27.16b 7a058b06ce521fed5d08a6518a5e0681 bdd97e6262d290939f5a508da7a22dc6 ac5e9f1522eaadd672628d85a4fce95f bdd97e6262d290939f5a508da7a22dc6 fpsr=00000000
+aesimc v6.16b, v27.16b 331ec93abd83b3873dc11f3713b4daed 9400c03bc11d97ea1a72c1c24d541809 a0e52a000a91053fee4ae32cc241870c 9400c03bc11d97ea1a72c1c24d541809 fpsr=00000000
+aesimc v6.16b, v27.16b 47645cd811d216aced6b40ab35ad90c9 5e4d2fb69dffc486fd73b3bda4213e74 fc1c82e8effff6c6b28de758ac92b342 5e4d2fb69dffc486fd73b3bda4213e74 fpsr=00000000
+aesimc v6.16b, v27.16b 17b7a3c02a20a73ecce6698d502988f5 7c9e2ab356577845a73e855d0de9fee6 347b94a00fda59b0bfff1f1e7c5b6cb7 7c9e2ab356577845a73e855d0de9fee6 fpsr=00000000
+aesimc v6.16b, v27.16b 02f7fed1694dc71b3b12fabdc5082250 4dd411124d07120978b19884e78bb841 beeecd074d44b0e811cb404f8607e8fc 4dd411124d07120978b19884e78bb841 fpsr=00000000
+aesimc v6.16b, v27.16b 6903ceed2d39d52499cf541bf329bfbc 31cf45b3e2eef3b0d1ad4b1093e9cc63 ad8bc9e703948c541293c6602824c61f 31cf45b3e2eef3b0d1ad4b1093e9cc63 fpsr=00000000
+aesimc v6.16b, v27.16b abbd72f2d6c3323946fdd6873a6ebf17 896e257674eb7a1b1112fee270e19b2e 89b856d3dd6c347b9a1e4bd052d6f151 896e257674eb7a1b1112fee270e19b2e fpsr=00000000
+aesimc v6.16b, v27.16b b493113b63df082a99c012dade548580 dbf1d8fa34d7519911cf872de79078ac ddc1ceda9241a159fe34803ef7423523 dbf1d8fa34d7519911cf872de79078ac fpsr=00000000
+aesmc v6.16b, v27.16b 131d6ae10faafbbcc796e6d83d22e83a a64f531cbf23f560690bb28f126072f3 6f20cd2413094b58e19084aa3877a519 a64f531cbf23f560690bb28f126072f3 fpsr=00000000
+aesmc v6.16b, v27.16b 05eb9049d92cb5b3fe76dabcee2b273c 9bea7238809eb8436047d60fa7e39d3a fd336297f847114b40f711586588828c 9bea7238809eb8436047d60fa7e39d3a fpsr=00000000
+aesmc v6.16b, v27.16b eadee154214596ee9b3e4f66514f9f66 1ca1962ed527f9215665528e04f85c61 7dc5fd400cf274a012ecd3c20fdaceda 1ca1962ed527f9215665528e04f85c61 fpsr=00000000
+aesmc v6.16b, v27.16b 23d6bfe045d5fd4c00cfa4b6c46db297 89551edd20a019dbac4386ea8b810c47 3ee9975f8ff93206a30594b149d44c90 89551edd20a019dbac4386ea8b810c47 fpsr=00000000
+aesmc v6.16b, v27.16b 0fb38acea7bc4aae8d0a3a8baa67bfb1 41e76a27c1e77752c1c3d3049c5c0fce 665b8056ffa84f1b8512266439c6a856 41e76a27c1e77752c1c3d3049c5c0fce fpsr=00000000
+aesmc v6.16b, v27.16b 0e55a0fda7d9def4a0cd70c6601b2792 a435dbea16dd7364f6c398bb966ac4d4 98acbc282e8ce8967abf38ebfe656f18 a435dbea16dd7364f6c398bb966ac4d4 fpsr=00000000
+aesmc v6.16b, v27.16b 1320d00781636ef2aa2435f1d98b8c3a 0313746b1f2601730e0cd0282c220e25 dc3cb55a8c1f04dcb8f289391b1b7356 0313746b1f2601730e0cd0282c220e25 fpsr=00000000
+aesmc v6.16b, v27.16b ed88aa5e6256c7dc3dc60b85c59fc6e1 17950d93cc81c987d899dab7125edb8e 18963aa859185a182a37704128dfd33d 17950d93cc81c987d899dab7125edb8e fpsr=00000000
+aesmc v6.16b, v27.16b 924cc8cf1899de0110897956bb86d2a7 8f6cc30e66a3a78f7a3f56ba1ae4d3cf b89fa8a142df4232481c2dd049e15f15 8f6cc30e66a3a78f7a3f56ba1ae4d3cf fpsr=00000000
+aesmc v6.16b, v27.16b 634e8a3a030b1443824de0451b1f116c c978f6ba4d6bfb6a53dea114a29655c8 d2fc0cdfb49077e4e5e7675ddf576140 c978f6ba4d6bfb6a53dea114a29655c8 fpsr=00000000
+aesmc v6.16b, v27.16b bf6c517f848cc881f3f19f33434ce212 27990578e2ba26fac3561da40c52c259 5a3de541568e81dd214ba7e1632b3cb1 27990578e2ba26fac3561da40c52c259 fpsr=00000000
+aesmc v6.16b, v27.16b 07887c7dfafb5a9ac45716fe95eba578 08ae50288571871d2b872a49b8f97962 96276906c0ec1e5c200ba4404d21380e 08ae50288571871d2b872a49b8f97962 fpsr=00000000
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+aesmc v6.16b, v27.16b d656943ae78ed41641f6a755fb65ab0d 301558db14ceabf1f3027f3a7342bdb3 5bf9646045e1e1c5ce4f3104d71f6790 301558db14ceabf1f3027f3a7342bdb3 fpsr=00000000
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+aesmc v6.16b, v27.16b 03eabab4de30073c7c8a01f4e7141c97 184607206c264312e4d54cf61928dd6b 1183fc178ba992ab4b3cee127acdab9b 184607206c264312e4d54cf61928dd6b fpsr=00000000
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+aesmc v6.16b, v27.16b f3effa9dd1ae772de62e4f4c15f95af6 cdf2373324636999fed7bd984913d58e 11b79d00f25acad53e8965dedda64339 cdf2373324636999fed7bd984913d58e fpsr=00000000
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+aesmc v6.16b, v27.16b 8cab0f89e97c2d28b6b280e5c91bb65e d2bb04d94d57b480330a903e68dc1014 70ddd5cce24d47c6beef28ee201f23ac d2bb04d94d57b480330a903e68dc1014 fpsr=00000000
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+aesmc v6.16b, v27.16b 8386fcb2e453a1263f997f54261c505f 8c1e3a2bd87f71f45f74df98437b8a1e 5aa2f18aa2084fc7a64efe7a55a7df81 8c1e3a2bd87f71f45f74df98437b8a1e fpsr=00000000
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+aesmc v6.16b, v27.16b f10fdbf281f172f57b92f7ce5b41cde7 1300c921d6a8acdba70bdc6c8d2f0522 8cddbb11c55dad3c3654750b4df5d4e9 1300c921d6a8acdba70bdc6c8d2f0522 fpsr=00000000
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+randV128: 10496 calls, 10841 iters
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+randV128: 11776 calls, 12169 iters
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+randV128: 12032 calls, 12432 iters
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+sha256su1 v29.4s, v28.4s, v27.4s 40a8543bf8c05042ff701f696d424c97 258ad8c5b81d43bffc39ee5fb5c1cd11 ff7092965f4c83b406f1e71e07babce3 dc9df9164dbc201812b3df9a3b37b265 258ad8c5b81d43bffc39ee5fb5c1cd11 ff7092965f4c83b406f1e71e07babce3 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s 9f787a81b93292c78ebea218ac9b1355 8494b887361b25a5c8ba1a8834072b56 18affc49c303c620a7026e96cf7b5233 7e7767750d76b010c6854c7a1139e6ed 8494b887361b25a5c8ba1a8834072b56 18affc49c303c620a7026e96cf7b5233 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s d9723b8a4d8fe3bd7eb07e1df2c7d505 d576da8b3dd25c9a4acd86c4b02f0a6b b9f6cf3ce5c124b9d4129a5e0aac70b1 fecc50cd32f1c51b7ada912df48819da d576da8b3dd25c9a4acd86c4b02f0a6b b9f6cf3ce5c124b9d4129a5e0aac70b1 fpsr=00000000
+randV128: 13056 calls, 13481 iters
+sha256su1 v29.4s, v28.4s, v27.4s f32cfccc772b6657535a966a839d365b 1bc5a1458f960bd1078514076d0e0f03 e5d76ee389dbbfb213374f6cfc21b911 6ca40df2b6633bb53d859dc5332fad9b 1bc5a1458f960bd1078514076d0e0f03 e5d76ee389dbbfb213374f6cfc21b911 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s f03921bafb5b3fcb90d0d0f5a3eeda0b 5b157229f2bc567f82f8a946af78ddd3 a1e83cb373a4bd40e58470b4e9afd107 fde63316135e870d9d75063aeffc61da 5b157229f2bc567f82f8a946af78ddd3 a1e83cb373a4bd40e58470b4e9afd107 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s d52d0ec89d72924bba260eb1969166c8 99fab1ac289861d840392974ba3f188f f0bb9e1e67704197d10ce32815295d46 8df0e3aa22fc0edb9faef936ffab1382 99fab1ac289861d840392974ba3f188f f0bb9e1e67704197d10ce32815295d46 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s a59b276b21c5840b54703592a0577e47 d808c240f77d5110c55c7784d33a65eb d7e5f89a299470eb59e58abec4640083 f847e8028dd3ae768f594f121c168aaf d808c240f77d5110c55c7784d33a65eb d7e5f89a299470eb59e58abec4640083 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s 6519d0164ba83941e3c1298d0616c43c 1dd3095b21bf495a9474796d3c3a679a 59faae9a7d646d6f01214a683b345e72 f7ee35ae93f2c70708088c50559045ae 1dd3095b21bf495a9474796d3c3a679a 59faae9a7d646d6f01214a683b345e72 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s 19396c3ddf6dd31feb2fce940aa2de5b 6befe9706cb36deb329711203a16c251 7b8f249227335c584ed6071dbc6b1cc6 55179db5c85317aacea8cdfe02e8cb23 6befe9706cb36deb329711203a16c251 7b8f249227335c584ed6071dbc6b1cc6 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s c4916054a26b78daefcd079df2ce7057 c7f0c8f39bace2f722d82493129f1bc4 4136bdf7ec5562dac416a5ce8de0dd34 fc9538cdfdde35c814ceefa632b3d3e2 c7f0c8f39bace2f722d82493129f1bc4 4136bdf7ec5562dac416a5ce8de0dd34 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s 3569085972ffcbb2e94a96b806ab15a6 ae84df3c8e1fa228e6f60870f0644670 32d3f2da6d2a553613133b37cf01047f 3b67b6a73fbe6996fea524af4dc7cfbb ae84df3c8e1fa228e6f60870f0644670 32d3f2da6d2a553613133b37cf01047f fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s b8f00e15b5ff4d4f0b034b855c0e54ac c70decd5d3e44178398b13f82bcefa2e d99c18061c22129c71218f8e383e0db9 f686d96808619ad86e1d5df8e0b3edb5 c70decd5d3e44178398b13f82bcefa2e d99c18061c22129c71218f8e383e0db9 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s 55183e9b28018b030b1527ee579b7d8a 906549367ef961fc41e7ac5981ef9d21 46e13377e73796d5d8e4557db2418c07 d8a7e3ae7bed250549d37dcad30cac7b 906549367ef961fc41e7ac5981ef9d21 46e13377e73796d5d8e4557db2418c07 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s 0f75fc5f9058a9016e960ee53b2733f4 0c205ad353b128e8811fb587369dd3fe 7d37a8a392bd0714cf7171f781df241c 6253264c61e774c0e3a1d4a4df935dc3 0c205ad353b128e8811fb587369dd3fe 7d37a8a392bd0714cf7171f781df241c fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s eb9bacd5af59cb7fb898e3604c851b9d 40d383211561ba727d4813778eac4179 8233dbfce209898fd8dcc9f0e9eb79ad 58531ea299229d71649bfb7bbf9bbe3b 40d383211561ba727d4813778eac4179 8233dbfce209898fd8dcc9f0e9eb79ad fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s ec1db1724b5716af6c308b52ce89d73a 2f1027938a5c39ccbb74aa1bcdef8a45 586730f9996e3e787739405c2e39306e 98eeb6982c6808147502641162d3856a 2f1027938a5c39ccbb74aa1bcdef8a45 586730f9996e3e787739405c2e39306e fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s 179170a926a7adc60e73ebaf05080e7f de6cac9d76f7cc2abdb85e69373b5318 03690a0b7d414c03319cb930949feb13 b41055dab011af4229aff374525eee43 de6cac9d76f7cc2abdb85e69373b5318 03690a0b7d414c03319cb930949feb13 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s 708a4dee069cb5f72373e56b35d6611f 507b74b39b8594c20728125410633fa3 89cbcfa750d5d7668a19195e60ee514f 8a0b398dc368ef285cfec15c8e4a4a78 507b74b39b8594c20728125410633fa3 89cbcfa750d5d7668a19195e60ee514f fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s fa9badb5ae8a51782f455d7ba3c576cf 8ad0e44abe5bb7c61ed8acd09d3bf29d eb22e142d87f01d305c445dcd4fc03d7 b4080ce9dd39cb1c1a54f58e2383ac8f 8ad0e44abe5bb7c61ed8acd09d3bf29d eb22e142d87f01d305c445dcd4fc03d7 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s ba5af173e1c6a57bb5fe39d291acf043 900160d4a3cc586b86dd0ed2209810b8 3002a54fd892f07f27b11e9d359da75f 1a72902d90f642e55fcd10e53e9032fc 900160d4a3cc586b86dd0ed2209810b8 3002a54fd892f07f27b11e9d359da75f fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s 65a14cc70f2d9be5c2491d4ddf4d3ea9 5a007f421463c89d74f48b96c8a4e19b cba456ce177ec0eada71b313f227909e 126bfabac5dd674178393b9d0caf611f 5a007f421463c89d74f48b96c8a4e19b cba456ce177ec0eada71b313f227909e fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s 0e440c96c4d1a5675731bd341d2f1f24 6daed38f5045ab636fa16fb9d0e5533e 83da8f8f824bbe9754c00bc74dd5b56e 2e4a6d0191f1f7eebd8e2fcc358a3260 6daed38f5045ab636fa16fb9d0e5533e 83da8f8f824bbe9754c00bc74dd5b56e fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s 8e7e03b6880c9926c8a9d27e1d1258dd 6fa105ab508cbf039dccadfc9135a3fd be84cc1ce8cbb33dd7fb24d9d620bdb9 c7923ab80910cf7618d8fb226aa28269 6fa105ab508cbf039dccadfc9135a3fd be84cc1ce8cbb33dd7fb24d9d620bdb9 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s eae397991e339c569ac5401c25c88c87 616d7809d98d28b281882b524e67748b a007de9d795df29c752a934bc58a6bb3 cf09579c5d69d4268907cec2ee549cd2 616d7809d98d28b281882b524e67748b a007de9d795df29c752a934bc58a6bb3 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s 4aa6921dad9c08a3a0ebcbb04d506b9e ce7fe16ab2371043078429e487da088b 4da2b7405983ad776f027253776dcc19 97c721eea5fbfb0b607e23bbf7d7bc9c ce7fe16ab2371043078429e487da088b 4da2b7405983ad776f027253776dcc19 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s 2ce0b55b910c860b7d087208d1c42be8 acfa82139dcac00cbbfadcc536f2937a a01a658a3526118454efa3521a7682f3 c43e2ccdf2f1111d992f34ab58bede60 acfa82139dcac00cbbfadcc536f2937a a01a658a3526118454efa3521a7682f3 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s 0baf46374a31c31e9df304501f95581e 1d37b6599461f69c89ade1d324f690b4 9c024eeed29b41f8a8070b3cf27a31f5 175234f44d9e5310a0e297fe723b0fbf 1d37b6599461f69c89ade1d324f690b4 9c024eeed29b41f8a8070b3cf27a31f5 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s eda7a9269a60e51084bf647b799a97f3 26cbe2af584fd72af3af1a0396bba5eb 45f0d4e0f3356206ee5c8e05444d7dd2 0d51d4db6f296e394e0c92188ac91c9a 26cbe2af584fd72af3af1a0396bba5eb 45f0d4e0f3356206ee5c8e05444d7dd2 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s d35c419b47ed0f14b582787d24a48b1d cb4b6a89aee886e87d166c48ce1576d3 a1775cd45b4897e4ab0310a252c10b40 e58afd6aeeca7085aa4398a7fad36c4d cb4b6a89aee886e87d166c48ce1576d3 a1775cd45b4897e4ab0310a252c10b40 fpsr=00000000
+sha256su1 v29.4s, v28.4s, v27.4s c462740a142b655fb54f224a658ad94e 0f49b15b5a81270bacf4bb9612d6a622 b22a4a3fd02904c46211750661ad7ef1 1086338cba86b6677c44ef17b54e8d34 0f49b15b5a81270bacf4bb9612d6a622 b22a4a3fd02904c46211750661ad7ef1 fpsr=00000000
+pmull v9.1q, v7.1d, v8.1d c24da4e7c56e0c25073948d77e1d233a f75a1d9a216edfc7045febe1a4d5d98a 001d7606b697893ced1721a29aea08a4 fpsr=00000000
+pmull2 v9.1q, v7.2d, v8.2d cb8acfd884207d2a8de4b3b5e64f7f43 bd6c634aafa1f3630c23d386c401bb44 759bae09ccbf866ea596eb35c23576be fpsr=00000000
diff --git a/none/tests/arm64/memory.c b/none/tests/arm64/memory.c
index 6034807..91949ac 100644
--- a/none/tests/arm64/memory.c
+++ b/none/tests/arm64/memory.c
@@ -157,18 +157,18 @@
////////////////////////////////////////////////////////////////
// This is a bit tricky. We load the value from just before and
-// just after the actual instruction. Because TESTINSN2_hide2
-// generates two fixed insns either side of the test insn, these
-// should be constant and hence "safe" to check.
+// just after the actual instruction. So we place a couple of
+// nop insns either side of the test insn, these should "safe"
+// to check.
printf("LDR (literal, int reg)\n");
-TESTINST2_hide2("xyzzy00: ldr x21, xyzzy00 - 8", AREA_MID, x21,x22,0);
-TESTINST2_hide2("xyzzy01: ldr x21, xyzzy01 + 0", AREA_MID, x21,x22,0);
-TESTINST2_hide2("xyzzy02: ldr x21, xyzzy02 + 8", AREA_MID, x21,x22,0);
+TESTINST2_hide2("nop; nop; nop; xyzzy00: ldr x21, xyzzy00 - 8; nop; nop; nop", AREA_MID, x21,x22,0);
+TESTINST2_hide2("nop; nop; nop; xyzzy01: ldr x21, xyzzy01 + 0; nop; nop; nop", AREA_MID, x21,x22,0);
+TESTINST2_hide2("nop; nop; nop; xyzzy02: ldr x21, xyzzy02 + 8; nop; nop; nop", AREA_MID, x21,x22,0);
-TESTINST2_hide2("xyzzy03: ldr x21, xyzzy03 - 4", AREA_MID, x21,x22,0);
-TESTINST2_hide2("xyzzy04: ldr x21, xyzzy04 + 0", AREA_MID, x21,x22,0);
-TESTINST2_hide2("xyzzy05: ldr x21, xyzzy05 + 4", AREA_MID, x21,x22,0);
+TESTINST2_hide2("nop; nop; nop; xyzzy03: ldr x21, xyzzy03 - 4; nop; nop; nop", AREA_MID, x21,x22,0);
+TESTINST2_hide2("nop; nop; nop; xyzzy04: ldr x21, xyzzy04 + 0; nop; nop; nop", AREA_MID, x21,x22,0);
+TESTINST2_hide2("nop; nop; nop; xyzzy05: ldr x21, xyzzy05 + 4; nop; nop; nop", AREA_MID, x21,x22,0);
////////////////////////////////////////////////////////////////
printf("{LD,ST}R (integer register) (entirely MISSING)\n");
@@ -280,6 +280,18 @@
////////////////////////////////////////////////////////////////
printf("STL{R,RH,RB} (entirely MISSING)\n");
+
+////////////////////////////////////////////////////////////////
+// TESTINST2_hide2 allows use of x28 as scratch
+printf("LDPSW (immediate, simm7)\n");
+
+TESTINST2_hide2("ldpsw x21, x28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+
} /* end of test_memory_old() */
@@ -1608,6 +1620,12 @@
MEM_TEST("prfm pstl3keep, [x5,w6,sxtw #0]", 12, 4);
MEM_TEST("prfm pstl3strm, [x5,w6,sxtw #3]", 12, -4);
+////////////////////////////////////////////////////////////////
+printf("LDPSW (immediate, simm7)\n");
+MEM_TEST("ldpsw x13, x23, [x5], #-24", 0, 0);
+MEM_TEST("ldpsw x13, x23, [x5, #-40]!", 0, 0);
+MEM_TEST("ldpsw x13, x23, [x5, #-40]", 0, 0);
+
} /* end of test_memory2() */
////////////////////////////////////////////////////////////////
diff --git a/none/tests/arm64/memory.stdout.exp b/none/tests/arm64/memory.stdout.exp
index 397ce08..be57108 100644
--- a/none/tests/arm64/memory.stdout.exp
+++ b/none/tests/arm64/memory.stdout.exp
@@ -21,12 +21,12 @@
ldp w21, w28, [x22, #-40] ; add x21,x21,x28 :: rd 000000019b999794 rn (hidden), cin 0, nzcv 00000000
ldp w21, w28, [x22, #-40] ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
LDR (literal, int reg)
-xyzzy00: ldr x21, xyzzy00 - 8 :: rd aa0003f6d51b4203 rn (hidden), cin 0, nzcv 00000000
-xyzzy01: ldr x21, xyzzy01 + 0 :: rd aa1503e258000015 rn (hidden), cin 0, nzcv 00000000
-xyzzy02: ldr x21, xyzzy02 + 8 :: rd 911e43a0d53b4201 rn (hidden), cin 0, nzcv 00000000
-xyzzy03: ldr x21, xyzzy03 - 4 :: rd 58fffff5aa0003f6 rn (hidden), cin 0, nzcv 00000000
-xyzzy04: ldr x21, xyzzy04 + 0 :: rd aa1503e258000015 rn (hidden), cin 0, nzcv 00000000
-xyzzy05: ldr x21, xyzzy05 + 4 :: rd d53b4201aa1503e2 rn (hidden), cin 0, nzcv 00000000
+nop; nop; nop; xyzzy00: ldr x21, xyzzy00 - 8; nop; nop; nop :: rd d503201fd503201f rn (hidden), cin 0, nzcv 00000000
+nop; nop; nop; xyzzy01: ldr x21, xyzzy01 + 0; nop; nop; nop :: rd d503201f58000015 rn (hidden), cin 0, nzcv 00000000
+nop; nop; nop; xyzzy02: ldr x21, xyzzy02 + 8; nop; nop; nop :: rd d503201fd503201f rn (hidden), cin 0, nzcv 00000000
+nop; nop; nop; xyzzy03: ldr x21, xyzzy03 - 4; nop; nop; nop :: rd 58fffff5d503201f rn (hidden), cin 0, nzcv 00000000
+nop; nop; nop; xyzzy04: ldr x21, xyzzy04 + 0; nop; nop; nop :: rd d503201f58000015 rn (hidden), cin 0, nzcv 00000000
+nop; nop; nop; xyzzy05: ldr x21, xyzzy05 + 4; nop; nop; nop :: rd d503201fd503201f rn (hidden), cin 0, nzcv 00000000
{LD,ST}R (integer register) (entirely MISSING)
LDRS{B,H,W} (uimm12)
ldrsw x21, [x22, #24] :: rd ffffffff8b8a8988 rn (hidden), cin 0, nzcv 00000000
@@ -98,6 +98,13 @@
ldarh w21, [x22] :: rd 000000000000f1f0 rn (hidden), cin 0, nzcv 00000000
ldarb w21, [x22] :: rd 00000000000000f0 rn (hidden), cin 0, nzcv 00000000
STL{R,RH,RB} (entirely MISSING)
+LDPSW (immediate, simm7)
+ldpsw x21, x28, [x22], #-24 ; add x21,x21,x28 :: rd ffffffffebe9e7e4 rn (hidden), cin 0, nzcv 00000000
+ldpsw x21, x28, [x22], #-24 ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
+ldpsw x21, x28, [x22, #-40]! ; add x21,x21,x28 :: rd ffffffff9b999794 rn (hidden), cin 0, nzcv 00000000
+ldpsw x21, x28, [x22, #-40]! ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
+ldpsw x21, x28, [x22, #-40] ; add x21,x21,x28 :: rd ffffffff9b999794 rn (hidden), cin 0, nzcv 00000000
+ldpsw x21, x28, [x22, #-40] ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
LDR,STR (immediate, uimm12)ldr x13, [x5, #24] with x5 = middle_of_block+-1, x6=0
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
@@ -26258,3 +26265,94 @@
0 x5 (sub, base reg)
0 x6 (sub, index reg)
+LDPSW (immediate, simm7)
+ldpsw x13, x23, [x5], #-24 with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 5430cb99daf026bb x13 (xor, xfer intreg #1)
+ 58eb9b702726900d x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldpsw x13, x23, [x5, #-40]! with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 7f799c624bfa7f08 x13 (xor, xfer intreg #1)
+ 3e7857cc51fd19f0 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -40 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldpsw x13, x23, [x5, #-40] with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 01ba3febe99768c0 x13 (xor, xfer intreg #1)
+ 1cef424f7c21ff9b x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
diff --git a/none/tests/bug234814.vgtest b/none/tests/bug234814.vgtest
index 67a28e6..31f95aa 100644
--- a/none/tests/bug234814.vgtest
+++ b/none/tests/bug234814.vgtest
@@ -1 +1,2 @@
+prereq: ! ../../tests/arch_test tilegx
prog: bug234814
diff --git a/none/tests/cmdline1.stdout.exp b/none/tests/cmdline1.stdout.exp
index cc25a16..0faec69 100644
--- a/none/tests/cmdline1.stdout.exp
+++ b/none/tests/cmdline1.stdout.exp
@@ -90,6 +90,8 @@
--vgdb-shadow-registers=no|yes let gdb see the shadow registers [no]
--vgdb-prefix=<prefix> prefix for vgdb FIFOs [.../vgdb-pipe]
--run-libc-freeres=no|yes free up glibc memory at exit on Linux? [yes]
+ --run-cxx-freeres=no|yes free up libstdc++ memory at exit on Linux
+ and Solaris? [yes]
--sim-hints=hint1,hint2,... activate unusual sim behaviours [none]
where hint is one of:
lax-ioctls lax-doors fuse-compatible enable-outer
diff --git a/none/tests/cmdline2.stdout.exp b/none/tests/cmdline2.stdout.exp
index 580fa19..b124f20 100644
--- a/none/tests/cmdline2.stdout.exp
+++ b/none/tests/cmdline2.stdout.exp
@@ -90,6 +90,8 @@
--vgdb-shadow-registers=no|yes let gdb see the shadow registers [no]
--vgdb-prefix=<prefix> prefix for vgdb FIFOs [.../vgdb-pipe]
--run-libc-freeres=no|yes free up glibc memory at exit on Linux? [yes]
+ --run-cxx-freeres=no|yes free up libstdc++ memory at exit on Linux
+ and Solaris? [yes]
--sim-hints=hint1,hint2,... activate unusual sim behaviours [none]
where hint is one of:
lax-ioctls lax-doors fuse-compatible enable-outer
diff --git a/none/tests/darwin/Makefile.in b/none/tests/darwin/Makefile.in
new file mode 100644
index 0000000..47370fd
--- /dev/null
+++ b/none/tests/darwin/Makefile.in
@@ -0,0 +1,962 @@
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+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = -O2 -g -std=gnu99 -Wall -Wmissing-prototypes -Wshadow \
+ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \
+ @FLAG_W_CAST_ALIGN@ @FLAG_W_CAST_QUAL@ @FLAG_W_WRITE_STRINGS@ \
+ @FLAG_W_EMPTY_BODY@ @FLAG_W_FORMAT@ @FLAG_W_FORMAT_SIGNEDNESS@ \
+ @FLAG_W_FORMAT_SECURITY@ @FLAG_W_IGNORED_QUALIFIERS@ \
+ @FLAG_W_MISSING_PARAMETER_TYPE@ @FLAG_W_OLD_STYLE_DECLARATION@ \
+ @FLAG_FNO_STACK_PROTECTOR@ @FLAG_FSANITIZE@ \
+ -fno-strict-aliasing -fno-builtin $(am__append_1)
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fpic -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# These flags are used for building the preload shared objects (PSOs).
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads. Also, we must use any
+# -mpreferred-stack-boundary flag to build the preload shared
+# objects, since that risks misaligning the client's stack and
+# results in segfaults like (eg) #324050.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \
+@VGCONF_OS_IS_DARWIN_TRUE@ -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
+ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
+AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
+AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ $(AM_FLAG_M3264_PRI)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) \
+ $(AM_FLAG_M3264_PRI)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ access_extended.stderr.exp access_extended.vgtest \
+ apple-main-arg.stderr.exp apple-main-arg.vgtest \
+ bug228343.stderr.exp bug228343.stdout.exp bug228343.vgtest \
+ bug254164.stderr.exp bug254164.vgtest \
+ rlimit.stderr.exp rlimit.vgtest
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/darwin/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/darwin/Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+$(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__empty):
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+
+access_extended$(EXEEXT): $(access_extended_OBJECTS) $(access_extended_DEPENDENCIES) $(EXTRA_access_extended_DEPENDENCIES)
+ @rm -f access_extended$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(access_extended_OBJECTS) $(access_extended_LDADD) $(LIBS)
+
+apple-main-arg$(EXEEXT): $(apple_main_arg_OBJECTS) $(apple_main_arg_DEPENDENCIES) $(EXTRA_apple_main_arg_DEPENDENCIES)
+ @rm -f apple-main-arg$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(apple_main_arg_OBJECTS) $(apple_main_arg_LDADD) $(LIBS)
+
+bug228343$(EXEEXT): $(bug228343_OBJECTS) $(bug228343_DEPENDENCIES) $(EXTRA_bug228343_DEPENDENCIES)
+ @rm -f bug228343$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug228343_OBJECTS) $(bug228343_LDADD) $(LIBS)
+
+bug254164$(EXEEXT): $(bug254164_OBJECTS) $(bug254164_DEPENDENCIES) $(EXTRA_bug254164_DEPENDENCIES)
+ @rm -f bug254164$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug254164_OBJECTS) $(bug254164_LDADD) $(LIBS)
+
+rlimit$(EXEEXT): $(rlimit_OBJECTS) $(rlimit_DEPENDENCIES) $(EXTRA_rlimit_DEPENDENCIES)
+ @rm -f rlimit$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(rlimit_OBJECTS) $(rlimit_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/access_extended.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/apple-main-arg.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug228343.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug254164.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rlimit.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.o$$||'`;\
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ $< &&\
+@am__fastdepCC_TRUE@ $(am__mv) $$depbase.Tpo $$depbase.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
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+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.obj$$||'`;\
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ `$(CYGPATH_W) '$<'` &&\
+@am__fastdepCC_TRUE@ $(am__mv) $$depbase.Tpo $$depbase.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
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+ID: $(am__tagged_files)
+ $(am__define_uniq_tagged_files); mkid -fID $$unique
+tags: tags-am
+TAGS: tags
+
+tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+ set x; \
+ here=`pwd`; \
+ $(am__define_uniq_tagged_files); \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
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+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
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+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
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+
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+GTAGS:
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+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+cscopelist: cscopelist-am
+
+cscopelist-am: $(am__tagged_files)
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+ esac; \
+ for i in $$list; do \
+ if test -f "$$i"; then \
+ echo "$(subdir)/$$i"; \
+ else \
+ echo "$$sdir/$$i"; \
+ fi; \
+ done >> $(top_builddir)/cscope.files
+
+distclean-tags:
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+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
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+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
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+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
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+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
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+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
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+check: check-am
+all-am: Makefile $(SCRIPTS)
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+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
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+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
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+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
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+ done
+
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+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
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+# Tell versions [3.59,3.63) of GNU make to not export all variables.
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diff --git a/none/tests/ioctl_moans.c b/none/tests/ioctl_moans.c
index 378ff44..3af6d4f 100644
--- a/none/tests/ioctl_moans.c
+++ b/none/tests/ioctl_moans.c
@@ -2,6 +2,7 @@
10 unique moans should be produced.
*/
+#include <unistd.h>
#include <sys/ioctl.h>
/* An ioctl request for a strange ioctl device driver.
diff --git a/none/tests/libvex_test.c b/none/tests/libvex_test.c
index 57184c0..2c3986d 100644
--- a/none/tests/libvex_test.c
+++ b/none/tests/libvex_test.c
@@ -129,8 +129,8 @@
case VexArchPPC32: return 0;
case VexArchPPC64: return 0;
case VexArchS390X: return VEX_HWCAPS_S390X_LDISP;
- case VexArchMIPS32: return 0;
- case VexArchMIPS64: return 0;
+ case VexArchMIPS32: return VEX_PRID_COMP_MIPS;
+ case VexArchMIPS64: return VEX_PRID_COMP_MIPS;
case VexArchTILEGX: return 0;
default: failure_exit();
}
diff --git a/none/tests/linux/Makefile.in b/none/tests/linux/Makefile.in
new file mode 100644
index 0000000..10bd957
--- /dev/null
+++ b/none/tests/linux/Makefile.in
@@ -0,0 +1,1048 @@
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+GREP = @GREP@
+HWCAP_HAS_ALTIVEC = @HWCAP_HAS_ALTIVEC@
+HWCAP_HAS_DFP = @HWCAP_HAS_DFP@
+HWCAP_HAS_HTM = @HWCAP_HAS_HTM@
+HWCAP_HAS_ISA_2_05 = @HWCAP_HAS_ISA_2_05@
+HWCAP_HAS_ISA_2_06 = @HWCAP_HAS_ISA_2_06@
+HWCAP_HAS_ISA_2_07 = @HWCAP_HAS_ISA_2_07@
+HWCAP_HAS_ISA_3_00 = @HWCAP_HAS_ISA_3_00@
+HWCAP_HAS_VSX = @HWCAP_HAS_VSX@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LIB_UBSAN = @LIB_UBSAN@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY_2 = @PREFERRED_STACK_BOUNDARY_2@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+SOLARIS_UNDEF_LARGESOURCE = @SOLARIS_UNDEF_LARGESOURCE@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+VG_TMPDIR = @VG_TMPDIR@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = -O2 -g -std=gnu99 -Wall -Wmissing-prototypes -Wshadow \
+ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \
+ @FLAG_W_CAST_ALIGN@ @FLAG_W_CAST_QUAL@ @FLAG_W_WRITE_STRINGS@ \
+ @FLAG_W_EMPTY_BODY@ @FLAG_W_FORMAT@ @FLAG_W_FORMAT_SIGNEDNESS@ \
+ @FLAG_W_FORMAT_SECURITY@ @FLAG_W_IGNORED_QUALIFIERS@ \
+ @FLAG_W_MISSING_PARAMETER_TYPE@ @FLAG_W_OLD_STYLE_DECLARATION@ \
+ @FLAG_FNO_STACK_PROTECTOR@ @FLAG_FSANITIZE@ \
+ -fno-strict-aliasing -fno-builtin $(am__append_1)
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fpic -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# These flags are used for building the preload shared objects (PSOs).
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads. Also, we must use any
+# -mpreferred-stack-boundary flag to build the preload shared
+# objects, since that risks misaligning the client's stack and
+# results in segfaults like (eg) #324050.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \
+@VGCONF_OS_IS_DARWIN_TRUE@ -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
+ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
+AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
+AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ $(AM_FLAG_M3264_PRI)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) \
+ $(AM_FLAG_M3264_PRI)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS)
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ blockfault.stderr.exp blockfault.vgtest \
+ brk-overflow1.stderr.exp brk-overflow1.vgtest \
+ brk-overflow2.stderr.exp brk-overflow2.vgtest \
+ mremap.stderr.exp mremap.stderr.exp-glibc27 mremap.stdout.exp \
+ mremap.vgtest \
+ mremap2.stderr.exp mremap2.stdout.exp mremap2.vgtest \
+ mremap3.stderr.exp mremap3.stdout.exp mremap3.vgtest \
+ mremap4.stderr.exp mremap4.vgtest \
+ mremap5.stderr.exp mremap5.vgtest \
+ mremap6.stderr.exp mremap6.vgtest \
+ pthread-stack.stderr.exp pthread-stack.vgtest \
+ stack-overflow.stderr.exp stack-overflow.vgtest
+
+
+# Special needs
+pthread_stack_LDADD = -lpthread
+stack_overflow_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_UNINITIALIZED@ \
+ @FLAG_W_NO_INFINITE_RECURSION@
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/linux/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/linux/Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+$(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__empty):
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+
+blockfault$(EXEEXT): $(blockfault_OBJECTS) $(blockfault_DEPENDENCIES) $(EXTRA_blockfault_DEPENDENCIES)
+ @rm -f blockfault$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(blockfault_OBJECTS) $(blockfault_LDADD) $(LIBS)
+
+brk-overflow1$(EXEEXT): $(brk_overflow1_OBJECTS) $(brk_overflow1_DEPENDENCIES) $(EXTRA_brk_overflow1_DEPENDENCIES)
+ @rm -f brk-overflow1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(brk_overflow1_OBJECTS) $(brk_overflow1_LDADD) $(LIBS)
+
+brk-overflow2$(EXEEXT): $(brk_overflow2_OBJECTS) $(brk_overflow2_DEPENDENCIES) $(EXTRA_brk_overflow2_DEPENDENCIES)
+ @rm -f brk-overflow2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(brk_overflow2_OBJECTS) $(brk_overflow2_LDADD) $(LIBS)
+
+mremap$(EXEEXT): $(mremap_OBJECTS) $(mremap_DEPENDENCIES) $(EXTRA_mremap_DEPENDENCIES)
+ @rm -f mremap$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(mremap_OBJECTS) $(mremap_LDADD) $(LIBS)
+
+mremap2$(EXEEXT): $(mremap2_OBJECTS) $(mremap2_DEPENDENCIES) $(EXTRA_mremap2_DEPENDENCIES)
+ @rm -f mremap2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(mremap2_OBJECTS) $(mremap2_LDADD) $(LIBS)
+
+mremap3$(EXEEXT): $(mremap3_OBJECTS) $(mremap3_DEPENDENCIES) $(EXTRA_mremap3_DEPENDENCIES)
+ @rm -f mremap3$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(mremap3_OBJECTS) $(mremap3_LDADD) $(LIBS)
+
+mremap4$(EXEEXT): $(mremap4_OBJECTS) $(mremap4_DEPENDENCIES) $(EXTRA_mremap4_DEPENDENCIES)
+ @rm -f mremap4$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(mremap4_OBJECTS) $(mremap4_LDADD) $(LIBS)
+
+mremap5$(EXEEXT): $(mremap5_OBJECTS) $(mremap5_DEPENDENCIES) $(EXTRA_mremap5_DEPENDENCIES)
+ @rm -f mremap5$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(mremap5_OBJECTS) $(mremap5_LDADD) $(LIBS)
+
+mremap6$(EXEEXT): $(mremap6_OBJECTS) $(mremap6_DEPENDENCIES) $(EXTRA_mremap6_DEPENDENCIES)
+ @rm -f mremap6$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(mremap6_OBJECTS) $(mremap6_LDADD) $(LIBS)
+
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+ $(AM_V_CCLD)$(LINK) $(pthread_stack_OBJECTS) $(pthread_stack_LDADD) $(LIBS)
+
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+ @rm -f stack-overflow$(EXEEXT)
+ $(AM_V_CCLD)$(stack_overflow_LINK) $(stack_overflow_OBJECTS) $(stack_overflow_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/blockfault.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/brk-overflow1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/brk-overflow2.Po@am__quote@
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+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mremap5.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mremap6.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pthread-stack.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/stack_overflow-stack-overflow.Po@am__quote@
+
+.c.o:
+@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.o$$||'`;\
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ $< &&\
+@am__fastdepCC_TRUE@ $(am__mv) $$depbase.Tpo $$depbase.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ $<
+
+.c.obj:
+@am__fastdepCC_TRUE@ $(AM_V_CC)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.obj$$||'`;\
+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ `$(CYGPATH_W) '$<'` &&\
+@am__fastdepCC_TRUE@ $(am__mv) $$depbase.Tpo $$depbase.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+
+stack_overflow-stack-overflow.o: stack-overflow.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(stack_overflow_CFLAGS) $(CFLAGS) -MT stack_overflow-stack-overflow.o -MD -MP -MF $(DEPDIR)/stack_overflow-stack-overflow.Tpo -c -o stack_overflow-stack-overflow.o `test -f 'stack-overflow.c' || echo '$(srcdir)/'`stack-overflow.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/stack_overflow-stack-overflow.Tpo $(DEPDIR)/stack_overflow-stack-overflow.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='stack-overflow.c' object='stack_overflow-stack-overflow.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(stack_overflow_CFLAGS) $(CFLAGS) -c -o stack_overflow-stack-overflow.o `test -f 'stack-overflow.c' || echo '$(srcdir)/'`stack-overflow.c
+
+stack_overflow-stack-overflow.obj: stack-overflow.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(stack_overflow_CFLAGS) $(CFLAGS) -MT stack_overflow-stack-overflow.obj -MD -MP -MF $(DEPDIR)/stack_overflow-stack-overflow.Tpo -c -o stack_overflow-stack-overflow.obj `if test -f 'stack-overflow.c'; then $(CYGPATH_W) 'stack-overflow.c'; else $(CYGPATH_W) '$(srcdir)/stack-overflow.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/stack_overflow-stack-overflow.Tpo $(DEPDIR)/stack_overflow-stack-overflow.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='stack-overflow.c' object='stack_overflow-stack-overflow.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(stack_overflow_CFLAGS) $(CFLAGS) -c -o stack_overflow-stack-overflow.obj `if test -f 'stack-overflow.c'; then $(CYGPATH_W) 'stack-overflow.c'; else $(CYGPATH_W) '$(srcdir)/stack-overflow.c'; fi`
+
+ID: $(am__tagged_files)
+ $(am__define_uniq_tagged_files); mkid -fID $$unique
+tags: tags-am
+TAGS: tags
+
+tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+ set x; \
+ here=`pwd`; \
+ $(am__define_uniq_tagged_files); \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: ctags-am
+
+CTAGS: ctags
+ctags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+ $(am__define_uniq_tagged_files); \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+cscopelist: cscopelist-am
+
+cscopelist-am: $(am__tagged_files)
+ list='$(am__tagged_files)'; \
+ case "$(srcdir)" in \
+ [\\/]* | ?:[\\/]*) sdir="$(srcdir)" ;; \
+ *) sdir=$(subdir)/$(srcdir) ;; \
+ esac; \
+ for i in $$list; do \
+ if test -f "$$i"; then \
+ echo "$(subdir)/$$i"; \
+ else \
+ echo "$$sdir/$$i"; \
+ fi; \
+ done >> $(top_builddir)/cscope.files
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ if test -z '$(STRIP)'; then \
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ install; \
+ else \
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \
+ fi
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
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+
+install-dvi: install-dvi-am
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+install-exec-am:
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+install-html: install-html-am
+
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+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS TAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local cscopelist-am \
+ ctags ctags-am distclean distclean-compile distclean-generic \
+ distclean-tags distdir dvi dvi-am html html-am info info-am \
+ install install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-html \
+ install-html-am install-info install-info-am install-man \
+ install-pdf install-pdf-am install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ maintainer-clean maintainer-clean-generic mostlyclean \
+ mostlyclean-compile mostlyclean-generic pdf pdf-am ps ps-am \
+ tags tags-am uninstall uninstall-am
+
+.PRECIOUS: Makefile
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
+# It needs to be depended on by an 'uninstall-local' rule.
+uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
+uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/none/tests/linux/brk-overflow1.stderr.exp b/none/tests/linux/brk-overflow1.stderr.exp
index f131579..96741db 100644
--- a/none/tests/linux/brk-overflow1.stderr.exp
+++ b/none/tests/linux/brk-overflow1.stderr.exp
@@ -1,3 +1,4 @@
brk segment overflow in thread #1: can't grow to 0x........
+(see section Limitations in user manual)
diff --git a/none/tests/linux/brk-overflow2.stderr.exp b/none/tests/linux/brk-overflow2.stderr.exp
index df62858..5cdf1f7 100644
--- a/none/tests/linux/brk-overflow2.stderr.exp
+++ b/none/tests/linux/brk-overflow2.stderr.exp
@@ -1,5 +1,8 @@
brk segment overflow in thread #1: can't grow to 0x........
+(see section Limitations in user manual)
brk segment overflow in thread #1: can't grow to 0x........
+(see section Limitations in user manual)
brk segment overflow in thread #1: can't grow to 0x........
+(see section Limitations in user manual)
diff --git a/none/tests/mips32/FPUarithmetic.c b/none/tests/mips32/FPUarithmetic.c
index 72806fa..7b12c75 100644
--- a/none/tests/mips32/FPUarithmetic.c
+++ b/none/tests/mips32/FPUarithmetic.c
@@ -1,3 +1,5 @@
+#if defined(__mips_hard_float)
+
#include <stdio.h>
#include <stdlib.h>
@@ -235,4 +237,8 @@
return 0;
}
-
+#else
+int main() {
+ return 0;
+}
+#endif
diff --git a/none/tests/mips32/FPUarithmetic.vgtest b/none/tests/mips32/FPUarithmetic.vgtest
index c33c448..1d2cace 100644
--- a/none/tests/mips32/FPUarithmetic.vgtest
+++ b/none/tests/mips32/FPUarithmetic.vgtest
@@ -1,2 +1,3 @@
prog: FPUarithmetic
+prereq: ../../../tests/mips_features fpu
vgopts: -q
diff --git a/none/tests/mips32/Makefile.am b/none/tests/mips32/Makefile.am
index fb6fa23..6f9fd7a 100644
--- a/none/tests/mips32/Makefile.am
+++ b/none/tests/mips32/Makefile.am
@@ -6,8 +6,13 @@
EXTRA_DIST = \
block_size.stdout.exp block_size.stderr.exp block_size.vgtest \
branches.stdout.exp branches.stderr.exp branches.vgtest \
+ bug320057-mips32.stdout.exp bug320057-mips32.stderr.exp \
+ bug320057-mips32.vgtest \
+ change_fp_mode.stdout.exp change_fp_mode.stdout.exp-fpu32 \
+ change_fp_mode.stderr.exp change_fp_mode.vgtest \
FPUarithmetic.stdout.exp FPUarithmetic.stdout.exp-mips32 \
FPUarithmetic.stderr.exp FPUarithmetic.vgtest \
+ fpu_branches.stdout.exp fpu_branches.stderr.exp fpu_branches.vgtest \
LoadStore.stdout.exp LoadStore.stdout.exp-BE LoadStore.stderr.exp \
LoadStore.vgtest \
LoadStore1.stdout.exp LoadStore1.stdout.exp-LE LoadStore1.stderr.exp \
@@ -16,30 +21,31 @@
MIPS32int.stdout.exp-mips32-BE MIPS32int.stdout.exp-mips32r2-BE \
MIPS32int.stdout.exp-mips32-LE MIPS32int.stdout.exp-mips32r2-LE \
MIPS32int.stderr.exp MIPS32int.vgtest \
- MoveIns.stdout.exp MoveIns.stdout.exp-BE MoveIns.stderr.exp MoveIns.vgtest \
- round.stdout.exp round.stderr.exp round.vgtest \
- vfp.stdout.exp-mips32-BE vfp.stdout.exp-mips32r2-BE \
- vfp.stdout.exp-mips32-LE vfp.stdout.exp-mips32r2-LE vfp.stderr.exp \
- vfp.vgtest \
- SignalException.stderr.exp SignalException.vgtest \
- bug320057-mips32.stdout.exp bug320057-mips32.stderr.exp \
- bug320057-mips32.vgtest \
mips32_dsp.stdout.exp-LE mips32_dsp.stdout.exp-BE \
mips32_dsp.stderr.exp mips32_dsp.vgtest \
mips32_dspr2.stdout.exp mips32_dspr2.stderr.exp \
mips32_dspr2.vgtest \
- unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
- unaligned_load_store.stderr.exp unaligned_load_store.vgtest \
- test_fcsr.stdout.exp test_fcsr.stderr.exp test_fcsr.vgtest \
- test_math.stdout.exp test_math.stderr.exp test_math.vgtest \
+ MoveIns.stdout.exp MoveIns.stdout.exp-BE \
+ MoveIns.stdout.exp-mips32r2-BE MoveIns.stdout.exp-mips32r2-LE \
+ MoveIns.stderr.exp MoveIns.vgtest \
round_fpu64.stdout.exp round_fpu64.stdout.exp-fpu32 \
round_fpu64.stderr.exp round_fpu64.vgtest \
- fpu_branches.stdout.exp fpu_branches.stderr.exp fpu_branches.vgtest
+ round.stdout.exp round.stderr.exp round.vgtest \
+ SignalException.stderr.exp SignalException.vgtest \
+ test_fcsr.stdout.exp test_fcsr.stderr.exp test_fcsr.vgtest \
+ test_math.stdout.exp test_math.stderr.exp test_math.vgtest \
+ unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
+ unaligned_load_store.stderr.exp unaligned_load_store.vgtest \
+ vfp.stdout.exp-mips32-BE vfp.stdout.exp-mips32r2-BE \
+ vfp.stdout.exp-mips32-LE vfp.stdout.exp-mips32r2-LE vfp.stderr.exp \
+ vfp.stdout.exp-mips32r2-fpu_64-BE vfp.stdout.exp-mips32r2-fpu_64-LE \
+ vfp.vgtest
check_PROGRAMS = \
allexec \
block_size \
branches \
+ change_fp_mode \
FPUarithmetic \
LoadStore \
LoadStore1 \
diff --git a/none/tests/mips32/Makefile.in b/none/tests/mips32/Makefile.in
new file mode 100644
index 0000000..74970d2
--- /dev/null
+++ b/none/tests/mips32/Makefile.in
@@ -0,0 +1,1191 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+am__is_gnu_make = { \
+ if test -z '$(MAKELEVEL)'; then \
+ false; \
+ elif test -n '$(MAKE_HOST)'; then \
+ true; \
+ elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
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+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
+ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
+AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
+AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ @FLAG_M32@ $(am__empty)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) @FLAG_M32@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ block_size.stdout.exp block_size.stderr.exp block_size.vgtest \
+ branches.stdout.exp branches.stderr.exp branches.vgtest \
+ bug320057-mips32.stdout.exp bug320057-mips32.stderr.exp \
+ bug320057-mips32.vgtest \
+ change_fp_mode.stdout.exp change_fp_mode.stdout.exp-fpu32 \
+ change_fp_mode.stderr.exp change_fp_mode.vgtest \
+ FPUarithmetic.stdout.exp FPUarithmetic.stdout.exp-mips32 \
+ FPUarithmetic.stderr.exp FPUarithmetic.vgtest \
+ fpu_branches.stdout.exp fpu_branches.stderr.exp fpu_branches.vgtest \
+ LoadStore.stdout.exp LoadStore.stdout.exp-BE LoadStore.stderr.exp \
+ LoadStore.vgtest \
+ LoadStore1.stdout.exp LoadStore1.stdout.exp-LE LoadStore1.stderr.exp \
+ LoadStore1.vgtest \
+ MemCpyTest.stdout.exp MemCpyTest.stderr.exp MemCpyTest.vgtest \
+ MIPS32int.stdout.exp-mips32-BE MIPS32int.stdout.exp-mips32r2-BE \
+ MIPS32int.stdout.exp-mips32-LE MIPS32int.stdout.exp-mips32r2-LE \
+ MIPS32int.stderr.exp MIPS32int.vgtest \
+ mips32_dsp.stdout.exp-LE mips32_dsp.stdout.exp-BE \
+ mips32_dsp.stderr.exp mips32_dsp.vgtest \
+ mips32_dspr2.stdout.exp mips32_dspr2.stderr.exp \
+ mips32_dspr2.vgtest \
+ MoveIns.stdout.exp MoveIns.stdout.exp-BE \
+ MoveIns.stdout.exp-mips32r2-BE MoveIns.stdout.exp-mips32r2-LE \
+ MoveIns.stderr.exp MoveIns.vgtest \
+ round_fpu64.stdout.exp round_fpu64.stdout.exp-fpu32 \
+ round_fpu64.stderr.exp round_fpu64.vgtest \
+ round.stdout.exp round.stderr.exp round.vgtest \
+ SignalException.stderr.exp SignalException.vgtest \
+ test_fcsr.stdout.exp test_fcsr.stderr.exp test_fcsr.vgtest \
+ test_math.stdout.exp test_math.stderr.exp test_math.vgtest \
+ unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
+ unaligned_load_store.stderr.exp unaligned_load_store.vgtest \
+ vfp.stdout.exp-mips32-BE vfp.stdout.exp-mips32r2-BE \
+ vfp.stdout.exp-mips32-LE vfp.stdout.exp-mips32r2-LE vfp.stderr.exp \
+ vfp.stdout.exp-mips32r2-fpu_64-BE vfp.stdout.exp-mips32r2-fpu_64-LE \
+ vfp.vgtest
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+bug320057_mips32_LDFLAGS = -lrt
+
+# C++ tests
+test_math_SOURCES = test_math.cpp
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .cpp .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/mips32/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/mips32/Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+$(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__empty):
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+
+FPUarithmetic$(EXEEXT): $(FPUarithmetic_OBJECTS) $(FPUarithmetic_DEPENDENCIES) $(EXTRA_FPUarithmetic_DEPENDENCIES)
+ @rm -f FPUarithmetic$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(FPUarithmetic_OBJECTS) $(FPUarithmetic_LDADD) $(LIBS)
+
+LoadStore$(EXEEXT): $(LoadStore_OBJECTS) $(LoadStore_DEPENDENCIES) $(EXTRA_LoadStore_DEPENDENCIES)
+ @rm -f LoadStore$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(LoadStore_OBJECTS) $(LoadStore_LDADD) $(LIBS)
+
+LoadStore1$(EXEEXT): $(LoadStore1_OBJECTS) $(LoadStore1_DEPENDENCIES) $(EXTRA_LoadStore1_DEPENDENCIES)
+ @rm -f LoadStore1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(LoadStore1_OBJECTS) $(LoadStore1_LDADD) $(LIBS)
+
+MIPS32int$(EXEEXT): $(MIPS32int_OBJECTS) $(MIPS32int_DEPENDENCIES) $(EXTRA_MIPS32int_DEPENDENCIES)
+ @rm -f MIPS32int$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(MIPS32int_OBJECTS) $(MIPS32int_LDADD) $(LIBS)
+
+MemCpyTest$(EXEEXT): $(MemCpyTest_OBJECTS) $(MemCpyTest_DEPENDENCIES) $(EXTRA_MemCpyTest_DEPENDENCIES)
+ @rm -f MemCpyTest$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(MemCpyTest_OBJECTS) $(MemCpyTest_LDADD) $(LIBS)
+
+MoveIns$(EXEEXT): $(MoveIns_OBJECTS) $(MoveIns_DEPENDENCIES) $(EXTRA_MoveIns_DEPENDENCIES)
+ @rm -f MoveIns$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(MoveIns_OBJECTS) $(MoveIns_LDADD) $(LIBS)
+
+SignalException$(EXEEXT): $(SignalException_OBJECTS) $(SignalException_DEPENDENCIES) $(EXTRA_SignalException_DEPENDENCIES)
+ @rm -f SignalException$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(SignalException_OBJECTS) $(SignalException_LDADD) $(LIBS)
+
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES) $(EXTRA_allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(AM_V_CCLD)$(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+
+block_size$(EXEEXT): $(block_size_OBJECTS) $(block_size_DEPENDENCIES) $(EXTRA_block_size_DEPENDENCIES)
+ @rm -f block_size$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(block_size_OBJECTS) $(block_size_LDADD) $(LIBS)
+
+branches$(EXEEXT): $(branches_OBJECTS) $(branches_DEPENDENCIES) $(EXTRA_branches_DEPENDENCIES)
+ @rm -f branches$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(branches_OBJECTS) $(branches_LDADD) $(LIBS)
+
+bug320057-mips32$(EXEEXT): $(bug320057_mips32_OBJECTS) $(bug320057_mips32_DEPENDENCIES) $(EXTRA_bug320057_mips32_DEPENDENCIES)
+ @rm -f bug320057-mips32$(EXEEXT)
+ $(AM_V_CCLD)$(bug320057_mips32_LINK) $(bug320057_mips32_OBJECTS) $(bug320057_mips32_LDADD) $(LIBS)
+
+change_fp_mode$(EXEEXT): $(change_fp_mode_OBJECTS) $(change_fp_mode_DEPENDENCIES) $(EXTRA_change_fp_mode_DEPENDENCIES)
+ @rm -f change_fp_mode$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(change_fp_mode_OBJECTS) $(change_fp_mode_LDADD) $(LIBS)
+
+fpu_branches$(EXEEXT): $(fpu_branches_OBJECTS) $(fpu_branches_DEPENDENCIES) $(EXTRA_fpu_branches_DEPENDENCIES)
+ @rm -f fpu_branches$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(fpu_branches_OBJECTS) $(fpu_branches_LDADD) $(LIBS)
+
+mips32_dsp$(EXEEXT): $(mips32_dsp_OBJECTS) $(mips32_dsp_DEPENDENCIES) $(EXTRA_mips32_dsp_DEPENDENCIES)
+ @rm -f mips32_dsp$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(mips32_dsp_OBJECTS) $(mips32_dsp_LDADD) $(LIBS)
+
+mips32_dspr2$(EXEEXT): $(mips32_dspr2_OBJECTS) $(mips32_dspr2_DEPENDENCIES) $(EXTRA_mips32_dspr2_DEPENDENCIES)
+ @rm -f mips32_dspr2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(mips32_dspr2_OBJECTS) $(mips32_dspr2_LDADD) $(LIBS)
+
+round$(EXEEXT): $(round_OBJECTS) $(round_DEPENDENCIES) $(EXTRA_round_DEPENDENCIES)
+ @rm -f round$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(round_OBJECTS) $(round_LDADD) $(LIBS)
+
+round_fpu64$(EXEEXT): $(round_fpu64_OBJECTS) $(round_fpu64_DEPENDENCIES) $(EXTRA_round_fpu64_DEPENDENCIES)
+ @rm -f round_fpu64$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(round_fpu64_OBJECTS) $(round_fpu64_LDADD) $(LIBS)
+
+test_fcsr$(EXEEXT): $(test_fcsr_OBJECTS) $(test_fcsr_DEPENDENCIES) $(EXTRA_test_fcsr_DEPENDENCIES)
+ @rm -f test_fcsr$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(test_fcsr_OBJECTS) $(test_fcsr_LDADD) $(LIBS)
+
+test_math$(EXEEXT): $(test_math_OBJECTS) $(test_math_DEPENDENCIES) $(EXTRA_test_math_DEPENDENCIES)
+ @rm -f test_math$(EXEEXT)
+ $(AM_V_CXXLD)$(CXXLINK) $(test_math_OBJECTS) $(test_math_LDADD) $(LIBS)
+
+unaligned_load_store$(EXEEXT): $(unaligned_load_store_OBJECTS) $(unaligned_load_store_DEPENDENCIES) $(EXTRA_unaligned_load_store_DEPENDENCIES)
+ @rm -f unaligned_load_store$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(unaligned_load_store_OBJECTS) $(unaligned_load_store_LDADD) $(LIBS)
+
+vfp$(EXEEXT): $(vfp_OBJECTS) $(vfp_DEPENDENCIES) $(EXTRA_vfp_DEPENDENCIES)
+ @rm -f vfp$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(vfp_OBJECTS) $(vfp_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/FPUarithmetic.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/LoadStore.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/LoadStore1.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MIPS32int.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MemCpyTest.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MoveIns.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/SignalException.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/allexec-allexec.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/block_size.Po@am__quote@
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+@am__fastdepCXX_TRUE@ $(CXXCOMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ $< &&\
+@am__fastdepCXX_TRUE@ $(am__mv) $$depbase.Tpo $$depbase.Po
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+
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+@am__fastdepCXX_TRUE@ $(am__mv) $$depbase.Tpo $$depbase.Po
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+@am__fastdepCXX_FALSE@ $(AM_V_CXX@am__nodep@)$(CXXCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
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+ID: $(am__tagged_files)
+ $(am__define_uniq_tagged_files); mkid -fID $$unique
+tags: tags-am
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+
+tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+ set x; \
+ here=`pwd`; \
+ $(am__define_uniq_tagged_files); \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
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+ test -z "$(CTAGS_ARGS)$$unique" \
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+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+cscopelist: cscopelist-am
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+cscopelist-am: $(am__tagged_files)
+ list='$(am__tagged_files)'; \
+ case "$(srcdir)" in \
+ [\\/]* | ?:[\\/]*) sdir="$(srcdir)" ;; \
+ *) sdir=$(subdir)/$(srcdir) ;; \
+ esac; \
+ for i in $$list; do \
+ if test -f "$$i"; then \
+ echo "$(subdir)/$$i"; \
+ else \
+ echo "$$sdir/$$i"; \
+ fi; \
+ done >> $(top_builddir)/cscope.files
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
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+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
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+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
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+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
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+ install; \
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+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \
+ fi
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
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+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
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+distclean: distclean-am
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+ distclean-tags
+
+dvi: dvi-am
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+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
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+ clean-checkPROGRAMS clean-generic clean-local cscopelist-am \
+ ctags ctags-am distclean distclean-compile distclean-generic \
+ distclean-tags distdir dvi dvi-am html html-am info info-am \
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+ tags tags-am uninstall uninstall-am
+
+.PRECIOUS: Makefile
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
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+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
+# It needs to be depended on by an 'uninstall-local' rule.
+uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
+uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/none/tests/mips32/MoveIns.c b/none/tests/mips32/MoveIns.c
index 77db9d4..ce2cb13 100644
--- a/none/tests/mips32/MoveIns.c
+++ b/none/tests/mips32/MoveIns.c
@@ -1,3 +1,6 @@
+#if defined(__mips_hard_float)
+
+#include <stdint.h>
#include <stdio.h>
const float fs_f[] = {
@@ -9,6 +12,17 @@
-347856.475, 356047.56, -1.0, 23.04
};
+unsigned long long data[] = {
+ 0x1234567887654321ull, 0x66785bd668466667ull,
+ 0xBFF550ff07788000ull, 0x0004789236500000ull,
+ 0x3FF0001256789600ull, 0x0012365478000000ull,
+ 0x252a2e2b252a2e2bull, 0x26852147962d2d2aull,
+ 0x1234567887654321ull, 0x66785bd668466667ull,
+ 0x789651ff07788055ull, 0x00ff23f4f1f5f6f8ull,
+ 0x3FF0001256789600ull, 0xaabbcdfeefcd1256ull,
+ 0xa1b2b2a1a3a5a6aaull, 0x2569874123654786ull
+};
+
unsigned int mem[] = {
0x4095A266, 0x66666666,
0xBFF00000, 0x00000000,
@@ -22,259 +36,236 @@
};
// mfc1 rt, fs
-#define TESTINSNMOVE(instruction, offset, FS, RT) \
-{ \
- float out; \
- int out1; \
- __asm__ volatile( \
- "move $t0, %2\n\t" \
- "lwc1 $" #FS ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.s %0, $" #FS"\n\t" \
- "move %1, $" #RT "\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (mem) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: fs %f, rt 0x%x\n", \
- instruction, out, out1); \
+#define TESTINSNMOVE(instruction, offset, FS, RT) \
+{ \
+ float out; \
+ int out1; \
+ __asm__ volatile( \
+ ".set push \n\t" \
+ ".set oddspreg \n\t" \
+ "move $t0, %2\n\t" \
+ "lwc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FS"\n\t" \
+ "move %1, $" #RT "\n\t" \
+ ".set pop \n\t" \
+ : "=f" (out), "=r" (out1) \
+ : "r" (mem) \
+ : "t0", "$"#FS, #RT, "memory" \
+ ); \
+ printf("%s :: fs %f, rt 0x%x\n", \
+ instruction, out, out1); \
}
// mfhc1 rt, fs
-#define TESTINSNMOVEd(instruction, offset, FS, RT) \
-{ \
- double out; \
- int out1; \
- __asm__ volatile( \
- "move $t0, %2\n\t" \
- "ldc1 $" #FS ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #FS"\n\t" \
- "move %1, $" #RT "\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (mem) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: fs %lf, rt 0x%x\n", \
- instruction, out, out1); \
+#define TESTINSNMOVEd(instruction, offset, FS, RT) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $t0, %1\n\t" \
+ "ldc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "move %0, $" #RT "\n\t" \
+ : "=r" (out) \
+ : "r" (data) \
+ : "t0", "$"#FS, #RT, "memory" \
+ ); \
+ printf("%s :: rt 0x%x\n", \
+ instruction, out); \
}
// mtc1 rt, fs
-#define TESTINSNMOVEt(instruction, offset, FS, RT) \
-{ \
- float out; \
- int out1; \
- __asm__ volatile( \
- "move $t0, %2\n\t" \
- "lw $" #RT ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.s %0, $" #FS"\n\t" \
- "move %1, $" #RT "\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (mem) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: fs %f, rt 0x%x\n", \
- instruction, out, out1); \
+#define TESTINSNMOVEt(instruction, offset, FS, RT) \
+{ \
+ float out; \
+ int out1; \
+ __asm__ volatile( \
+ ".set push \n\t" \
+ ".set oddspreg \n\t" \
+ "move $t0, %2\n\t" \
+ "lw $" #RT ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FS"\n\t" \
+ "move %1, $" #RT "\n\t" \
+ ".set pop \n\t" \
+ : "=f" (out), "=r" (out1) \
+ : "r" (mem) \
+ : "t0", "$"#FS, #RT, "memory" \
+ ); \
+ printf("%s :: fs %f, rt 0x%x\n", \
+ instruction, out, out1); \
}
// mthc1 rt, fs
-#define TESTINSNMOVEtd(instruction, offset, FS, RT) \
-{ \
- double out; \
- int out1; \
- __asm__ volatile( \
- "move $t0, %2\n\t" \
- "lw $" #RT ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #FS"\n\t" \
- "move %1, $" #RT "\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (mem) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: fs %lf, rt 0x%x\n", \
- instruction, out, out1); \
+#define TESTINSNMOVEtd(instruction, offset, offset2, FS, RT) \
+{ \
+ unsigned long long out = 0; \
+ __asm__ volatile ( \
+ "move $t0, %2 \n\t" \
+ "move $t1, %1 \n\t" \
+ "ldc1 $"#FS"," #offset2"($t0)" "\n\t" \
+ "lw $"#RT"," #offset"($t1) \n\t" \
+ instruction "\n\t" \
+ "move $"#RT", %0 \n\t" \
+ "sdc1 $"#FS ", 0($"#RT")" "\n\t" \
+ : : "r" (&out), "r" (mem), "r" (data) \
+ : "t0", "t1", "$"#FS, #RT, "memory" \
+ ); \
+ printf("%s :: out: %llx\n", instruction, out); \
}
// mov.s fd, fs
-#define TESTINSNMOVE1s(instruction, offset, FD, FS) \
-{ \
- float out; \
- int out1; \
- __asm__ volatile( \
- "move $t0, %2\n\t" \
- "lwc1 $" #FS ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.s %0, $" #FD"\n\t" \
- "mfc1 %1, $" #FD"\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (fs_f) \
- : "cc", "memory" \
- ); \
- printf("%s :: fs %f, rt 0x%x\n", \
- instruction, out, out1); \
+#define TESTINSNMOVE1s(instruction, offset, FD, FS) \
+{ \
+ float out; \
+ int out1; \
+ __asm__ volatile( \
+ ".set push \n\t" \
+ ".set oddspreg \n\t" \
+ "move $t0, %2\n\t" \
+ "lwc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FD"\n\t" \
+ "mfc1 %1, $" #FD"\n\t" \
+ ".set pop \n\t" \
+ : "=f" (out), "=r" (out1) \
+ : "r" (fs_f) \
+ : "t0", "$"#FS, "$"#FD, "memory" \
+ ); \
+ printf("%s :: fs %f, rt 0x%x\n", \
+ instruction, out, out1); \
}
// mov.d fd, fs
-#define TESTINSNMOVE1d(instruction, offset, FD, FS) \
-{ \
- double out; \
- int out1; \
- __asm__ volatile( \
- "move $t0, %2\n\t" \
- "ldc1 $" #FS ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #FD"\n\t" \
- "mfc1 %1, $" #FD"\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (fs_f) \
- : "cc", "memory" \
- ); \
- printf("%s ::fs %f, rt 0x%x\n", \
- instruction, out, out1); \
+#define TESTINSNMOVE1d(instruction, offset, FD, FS) \
+{ \
+ double out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $t0, %2\n\t" \
+ "ldc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #FD"\n\t" \
+ "mfc1 %1, $" #FD"\n\t" \
+ : "=f" (out), "=r" (out1) \
+ : "r" (fs_f) \
+ : "t0", "$"#FS, "$"#FD, "memory" \
+ ); \
+ printf("%s ::fs %f, rt 0x%x\n", \
+ instruction, out, out1); \
}
// movf rd, rs
-#define TESTINSNMOVE2(instruction, RDval, RSval, RD, RS, cc) \
-{ \
- int out; \
- __asm__ volatile( \
- "li $t0, 1\n\t" \
- "move $t1, %3\n\t" \
- "mtc1 $t0, $f0\n\t" \
- "mtc1 $t1, $f2\n\t" \
- "c.eq.s $f0, $f2\n\t" \
- "move $" #RS ", %1\n\t" \
- "move $" #RD ", %2\n\t" \
- instruction "\n\t" \
- "move %0, $" #RD "\n\t" \
- : "=&r" (out) \
- : "r" (RSval), "r" (RDval), "r" (cc) \
- : "t0", "t1", #RD, #RS, "cc", "memory" \
- ); \
- printf("%s :: out: 0x%x, RDval: 0x%x, RSval: 0x%x, cc: %d\n", \
- instruction, out, RDval, RSval, cc); \
+#define TESTINSNMOVE2(instruction, RDval, RSval, RD, RS, cc) \
+{ \
+ int out; \
+ __asm__ volatile( \
+ "li $t0, 1\n\t" \
+ "move $t1, %3\n\t" \
+ "mtc1 $t0, $f0\n\t" \
+ "mtc1 $t1, $f2\n\t" \
+ "c.eq.s $f0, $f2\n\t" \
+ "move $" #RS ", %1\n\t" \
+ "move $" #RD ", %2\n\t" \
+ instruction "\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=r" (out) \
+ : "r" (RSval), "r" (RDval), "r" (cc) \
+ : "t0", "t1", #RD, #RS \
+ ); \
+ printf("%s :: out: 0x%x, RDval: 0x%x, RSval: 0x%x, cc: %d\n",\
+ instruction, out, RDval, RSval, cc); \
}
// movf.s fd, fs
-#define TESTINSNMOVE2s(instruction, FD, FS, cc, offset) \
-{ \
- float out; \
- __asm__ volatile( \
- "li $t0, 1\n\t" \
- "move $t1, %1\n\t" \
- "mtc1 $t0, $f0\n\t" \
- "mtc1 $t1, $f2\n\t" \
- "c.eq.s $f0, $f2\n\t" \
- "move $t0, %2\n\t" \
- "lwc1 $" #FD ", 4($t0)\n\t" \
- "lwc1 $" #FS ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.s %0, $" #FD"\n\t" \
- : "=&f" (out) \
- : "r" (cc), "r" (fs_f) \
- : "t0", "t1", "cc", "memory" \
- ); \
- printf("%s :: out: %f, cc: %d\n", \
- instruction, out, cc); \
+#define TESTINSNMOVE2s(instruction, FD, FS, cc, offset) \
+{ \
+ float out; \
+ __asm__ volatile( \
+ "li $t0, 1\n\t" \
+ "move $t1, %1\n\t" \
+ "mtc1 $t0, $f0\n\t" \
+ "mtc1 $t1, $f2\n\t" \
+ "c.eq.s $f0, $f2\n\t" \
+ "move $t0, %2\n\t" \
+ "lwc1 $" #FD ", 4($t0)\n\t" \
+ "lwc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FD"\n\t" \
+ : "=f" (out) \
+ : "r" (cc), "r" (fs_f) \
+ : "t0", "t1", "$"#FD, "$"#FS, "memory" \
+ ); \
+ printf("%s :: out: %f, cc: %d\n", \
+ instruction, out, cc); \
}
// movf.d fd, fs
-#if (__mips_fpr==64)
-#define TESTINSNMOVE2d(instruction, FD, FS, cc, offset) \
-{ \
- double out; \
- int out1; \
- int out2; \
- __asm__ volatile( \
- "li $t0, 1\n\t" \
- "mtc1 $t0, $f0\n\t" \
- "mtc1 %3, $f2\n\t" \
- "move $t0, %4\n\t" \
- "ldc1 $f4, 8($t0)\n\t" \
- "c.eq.s $f0, $f2\n\t" \
- "ldc1 $" #FS ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #FD"\n\t" \
- "mfc1 %1, $f4\n\t" \
- "mfhc1 %2, $f4\n\t" \
- : "=&f" (out), "=&r" (out1), "=&r" (out2) \
- : "r" (cc), "r" (mem) \
- : "t0", "t1", "cc", "memory" \
- ); \
- printf("%s :: out: 0x%x 0x%x, cc: %d\n", \
- instruction, out1, out2, cc); \
+#define TESTINSNMOVE2d(instruction, FD, FS, cc, offset) \
+{ \
+ double out; \
+ uint64_t outl; \
+ __asm__ volatile( \
+ "li $t0, 1 \n\t" \
+ "move $t1, %1 \n\t" \
+ "mtc1 $t0, $f0 \n\t" \
+ "mtc1 $t1, $f2 \n\t" \
+ "move $t0, %2 \n\t" \
+ "ldc1 $f4, 8($t0) \n\t" \
+ "c.eq.s $f0, $f2\n\t" \
+ "ldc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #FD"\n\t" \
+ "sdc1 $f4, 0(%3)" \
+ : "=&f" (out) \
+ : "r" (cc), "r" (mem), "r" (&outl) \
+ : "t0", "t1", "$f0", "$f2", "$f4", "$"#FS, "$"#FD, "memory" \
+ ); \
+ printf("%s :: out: 0x%x 0x%x, cc: %d\n", \
+ instruction, (uint32_t)outl, (uint32_t)(outl >> 32), cc); \
}
-#else
-#define TESTINSNMOVE2d(instruction, FD, FS, cc, offset) \
-{ \
- double out; \
- int out1; \
- int out2; \
- __asm__ volatile( \
- "li $t0, 1\n\t" \
- "move $t1, %3\n\t" \
- "mtc1 $t0, $f0\n\t" \
- "mtc1 $t1, $f2\n\t" \
- "move $t0, %4\n\t" \
- "ldc1 $f4, 8($t0)\n\t" \
- "c.eq.s $f0, $f2\n\t" \
- "ldc1 $" #FS ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #FD"\n\t" \
- "mfc1 %1, $f4\n\t" \
- "mfc1 %2, $f5\n\t" \
- : "=&f" (out), "=&r" (out1), "=&r" (out2) \
- : "r" (cc), "r" (mem) \
- : "t0", "t1", "cc", "memory" \
- ); \
- printf("%s :: out: 0x%x 0x%x, cc: %d\n", \
- instruction, out1, out2, cc); \
-}
-#endif
// movn.s fd, fs, rt
-#define TESTINSNMOVEN1s(instruction, offset, RTval, FD, FS, RT) \
-{ \
- float out; \
- int out1; \
- __asm__ volatile( \
- "move $" #RT ", %3\n\t" \
- "move $t0, %2\n\t" \
- "lwc1 $" #FS ", "#offset"($t0)\n\t" \
- "mtc1 $0, $" #FD "\n\t" \
- instruction "\n\t" \
- "mov.s %0, $" #FD"\n\t" \
- "mfc1 %1, $" #FD"\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (fs_f), "r" (RTval) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: fs rt 0x%x\n", \
- instruction, out1); \
+#define TESTINSNMOVEN1s(instruction, offset, RTval, FD, FS, RT) \
+{ \
+ float out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $" #RT ", %3\n\t" \
+ "move $t0, %2\n\t" \
+ "lwc1 $" #FS ", "#offset"($t0)\n\t" \
+ "mtc1 $0, $" #FD "\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FD"\n\t" \
+ "mfc1 %1, $" #FD"\n\t" \
+ : "=f" (out), "=r" (out1) \
+ : "r" (fs_f), "r" (RTval) \
+ : "t0", "$"#FS, "$"#FD, #RT, "memory" \
+ ); \
+ printf("%s :: fs rt 0x%x\n", \
+ instruction, out1); \
}
// movn.d fd, fs, rt
-#define TESTINSNMOVEN1d(instruction, offset, RTval, FD, FS, RT) \
-{ \
- double out; \
- int out1; \
- __asm__ volatile( \
- "move $" #RT ", %3\n\t" \
- "move $t0, %2\n\t" \
- "ldc1 $" #FS ", "#offset"($t0)\n\t" \
- "mtc1 $0, $" #FD "\n\t" \
- "mtc1 $0, $" #FD + 1"\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #FD"\n\t" \
- "mfc1 %1, $" #FD"\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (fs_f), "r" (RTval) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: fs %lf, rt 0x%x\n", \
- instruction, out, out1); \
+#define TESTINSNMOVEN1d(instruction, offset, RTval, FD, FS, RT) \
+{ \
+ double out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $" #RT ", %3\n\t" \
+ "move $t0, %2\n\t" \
+ "ldc1 $" #FS ", "#offset"($t0)\n\t" \
+ "mtc1 $0, $" #FD "\n\t" \
+ "mtc1 $0, $" #FD + 1"\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #FD"\n\t" \
+ "mfc1 %1, $" #FD"\n\t" \
+ : "=f" (out), "=r" (out1) \
+ : "r" (fs_f), "r" (RTval) \
+ : "t0", "$"#FS, "$"#FD, #RT, "memory" \
+ ); \
+ printf("%s :: fs %lf, rt 0x%x\n", \
+ instruction, out, out1); \
}
int main()
@@ -337,6 +328,44 @@
TESTINSNMOVEt("mtc1 $t1, $f25", 34, f25, t1);
TESTINSNMOVEt("mtc1 $t2, $f26", 38, f26, t2);
+#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
+ printf("MFHC1\n");
+ TESTINSNMOVEd("mfhc1 $t1, $f0", 0, f0, t1);
+ TESTINSNMOVEd("mfhc1 $t2, $f2", 8, f2, t2);
+ TESTINSNMOVEd("mfhc1 $t3, $f4", 16, f4, t3);
+ TESTINSNMOVEd("mfhc1 $v0, $f6", 24, f6, v0);
+ TESTINSNMOVEd("mfhc1 $v1, $f8", 32, f8, v1);
+ TESTINSNMOVEd("mfhc1 $a0, $f10", 40, f10, a0);
+ TESTINSNMOVEd("mfhc1 $a1, $f12", 48, f12, a1);
+ TESTINSNMOVEd("mfhc1 $a2, $f14", 56, f14, a2);
+ TESTINSNMOVEd("mfhc1 $a3, $f16", 64, f16, a3);
+ TESTINSNMOVEd("mfhc1 $s0, $f18", 72, f18, s0);
+ TESTINSNMOVEd("mfhc1 $s1, $f20", 80, f20, s1);
+ TESTINSNMOVEd("mfhc1 $s2, $f22", 88, f22, s2);
+ TESTINSNMOVEd("mfhc1 $s3, $f24", 96, f24, s3);
+ TESTINSNMOVEd("mfhc1 $s4, $f26", 104, f26, s4);
+ TESTINSNMOVEd("mfhc1 $s5, $f28", 112, f28, s5);
+ TESTINSNMOVEd("mfhc1 $s6, $f30", 120, f30, s6);
+
+ printf("MTHC1\n");
+ TESTINSNMOVEtd("mthc1 $t2, $f0", 0, 0, f0, t2);
+ TESTINSNMOVEtd("mthc1 $t3, $f2", 4, 8, f2, t3);
+ TESTINSNMOVEtd("mthc1 $v0, $f4", 8, 16, f4, v0);
+ TESTINSNMOVEtd("mthc1 $v1, $f6", 12, 24, f6, v1);
+ TESTINSNMOVEtd("mthc1 $a0, $f8", 16, 32, f8, a0);
+ TESTINSNMOVEtd("mthc1 $a1, $f10", 20, 40, f10, a1);
+ TESTINSNMOVEtd("mthc1 $a2, $f12", 24, 48, f12, a1);
+ TESTINSNMOVEtd("mthc1 $a3, $f14", 28, 56, f14, a3);
+ TESTINSNMOVEtd("mthc1 $s0, $f16", 32, 64, f16, s0);
+ TESTINSNMOVEtd("mthc1 $s1, $f18", 36, 72, f18, s1);
+ TESTINSNMOVEtd("mthc1 $s2, $f20", 40, 80, f20, s2);
+ TESTINSNMOVEtd("mthc1 $s3, $f22", 44, 88, f22, s3);
+ TESTINSNMOVEtd("mthc1 $s4, $f24", 48, 96, f24, s4);
+ TESTINSNMOVEtd("mthc1 $s5, $f26", 52, 104, f26, s5);
+ TESTINSNMOVEtd("mthc1 $s6, $f28", 56, 112, f28, s6);
+ TESTINSNMOVEtd("mthc1 $s7, $f30", 60, 120, f30, s7);
+#endif
+
printf("MOV.S\n");
TESTINSNMOVE1s("mov.s $f0, $f0", 0, f0, f0);
TESTINSNMOVE1s("mov.s $f0, $f1", 4, f0, f1);
@@ -631,5 +660,11 @@
TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 52, 0xffffffff, f0, f2, t3);
TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 56, 0x80000000, f0, f2, t3);
TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 60, 0x7fffffff, f0, f2, t3);
+
return 0;
}
+#else
+int main() {
+ return 0;
+}
+#endif
diff --git a/none/tests/mips32/MoveIns.stdout.exp-mips32r2-BE b/none/tests/mips32/MoveIns.stdout.exp-mips32r2-BE
new file mode 100644
index 0000000..a354f3b
--- /dev/null
+++ b/none/tests/mips32/MoveIns.stdout.exp-mips32r2-BE
@@ -0,0 +1,373 @@
+MFC1
+mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
+mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
+mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
+mfc1 $t4, $f3 :: fs 0.000000, rt 0x0
+mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
+mfc1 $t6, $f5 :: fs 0.000000, rt 0x0
+mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
+mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
+mfc1 $v1, $f8 :: fs nan, rt 0xffffffff
+mfc1 $s0, $f9 :: fs nan, rt 0xffffffff
+mfc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
+mfc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
+mfc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
+mfc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
+mfc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
+mfc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
+mfc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
+mfc1 $a0, $f17 :: fs 4.676074, rt 0x4095a266
+mfc1 $a1, $f18 :: fs 272008302207532160516096.000000, rt 0x66666666
+mfc1 $a2, $f19 :: fs -1.875000, rt 0xbff00000
+mfc1 $a3, $f20 :: fs 0.000000, rt 0x0
+mfc1 $v0, $f21 :: fs 1.875000, rt 0x3ff00000
+mfc1 $v1, $f22 :: fs 0.000000, rt 0x0
+mfc1 $t8, $f23 :: fs 0.000000, rt 0x252a2e2b
+mfc1 $t9, $f24 :: fs 0.000000, rt 0x262d2d2a
+mfc1 $t1, $f25 :: fs nan, rt 0xffffffff
+mfc1 $t2, $f26 :: fs nan, rt 0xffffffff
+MTC1
+mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
+mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
+mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
+mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
+mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
+mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
+mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
+mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
+mtc1 $v1, $f8 :: fs nan, rt 0xffffffff
+mtc1 $s0, $f9 :: fs nan, rt 0xffffffff
+mtc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
+mtc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
+mtc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
+mtc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
+mtc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
+mtc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
+mtc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
+mtc1 $a0, $f17 :: fs -0.000000, rt 0xa2666666
+mtc1 $a1, $f18 :: fs 272421228250166506553344.000000, rt 0x6666bff0
+mtc1 $a2, $f19 :: fs 0.000000, rt 0x0
+mtc1 $a3, $f20 :: fs 0.000000, rt 0x3ff0
+mtc1 $v0, $f21 :: fs 0.000000, rt 0x0
+mtc1 $v1, $f22 :: fs 0.000000, rt 0x252a
+mtc1 $t8, $f23 :: fs 0.000000, rt 0x2e2b262d
+mtc1 $t9, $f24 :: fs 0.000000, rt 0x2d2affff
+mtc1 $t1, $f25 :: fs nan, rt 0xffffffff
+mtc1 $t2, $f26 :: fs nan, rt 0xffff41d2
+MFHC1
+mfhc1 $t1, $f0 :: rt 0x12345678
+mfhc1 $t2, $f2 :: rt 0x66785bd6
+mfhc1 $t3, $f4 :: rt 0xbff550ff
+mfhc1 $v0, $f6 :: rt 0x47892
+mfhc1 $v1, $f8 :: rt 0x3ff00012
+mfhc1 $a0, $f10 :: rt 0x123654
+mfhc1 $a1, $f12 :: rt 0x252a2e2b
+mfhc1 $a2, $f14 :: rt 0x26852147
+mfhc1 $a3, $f16 :: rt 0x12345678
+mfhc1 $s0, $f18 :: rt 0x66785bd6
+mfhc1 $s1, $f20 :: rt 0x789651ff
+mfhc1 $s2, $f22 :: rt 0xff23f4
+mfhc1 $s3, $f24 :: rt 0x3ff00012
+mfhc1 $s4, $f26 :: rt 0xaabbcdfe
+mfhc1 $s5, $f28 :: rt 0xa1b2b2a1
+mfhc1 $s6, $f30 :: rt 0x25698741
+MTHC1
+mthc1 $t2, $f0 :: out: 4095a26687654321
+mthc1 $t3, $f2 :: out: 6666666668466667
+mthc1 $v0, $f4 :: out: bff0000007788000
+mthc1 $v1, $f6 :: out: 36500000
+mthc1 $a0, $f8 :: out: 3ff0000056789600
+mthc1 $a1, $f10 :: out: 78000000
+mthc1 $a2, $f12 :: out: 1252a2e2b
+mthc1 $a3, $f14 :: out: 262d2d2a962d2d2a
+mthc1 $s0, $f16 :: out: ffffffff87654321
+mthc1 $s1, $f18 :: out: ffffffff68466667
+mthc1 $s2, $f20 :: out: 41d2658007788055
+mthc1 $s3, $f22 :: out: b487e5c9f1f5f6f8
+mthc1 $s4, $f24 :: out: 4202658056789600
+mthc1 $s5, $f26 :: out: b750e388efcd1256
+mthc1 $s6, $f28 :: out: 3e45798ea3a5a6aa
+mthc1 $s7, $f30 :: out: e2308c3a23654786
+MOV.S
+mov.s $f0, $f0 :: fs 0.000000, rt 0x0
+mov.s $f0, $f1 :: fs 456.248962, rt 0x43e41fde
+mov.s $f1, $f2 :: fs 3.000000, rt 0x40400000
+mov.s $f2, $f3 :: fs -1.000000, rt 0xbf800000
+mov.s $f3, $f4 :: fs 1384.599976, rt 0x44ad1333
+mov.s $f4, $f5 :: fs -7.294568, rt 0xc0e96d19
+mov.s $f5, $f6 :: fs 1000000000.000000, rt 0x4e6e6b28
+mov.s $f6, $f7 :: fs -5786.470215, rt 0xc5b4d3c3
+mov.s $f7, $f8 :: fs 1752.000000, rt 0x44db0000
+mov.s $f8, $f9 :: fs 0.002457, rt 0x3b210e02
+mov.s $f9, $f10 :: fs 0.000000, rt 0x322bcc77
+mov.s $f10, $f11 :: fs -248562.765625, rt 0xc872bcb1
+mov.s $f11, $f12 :: fs -45786.476562, rt 0xc732da7a
+mov.s $f12, $f13 :: fs 456.248962, rt 0x43e41fde
+mov.s $f13, $f14 :: fs 34.000462, rt 0x42080079
+mov.s $f14, $f15 :: fs 45786.476562, rt 0x4732da7a
+mov.s $f15, $f16 :: fs 1752065.000000, rt 0x49d5e008
+mov.s $f16, $f17 :: fs 0.000000, rt 0x0
+mov.s $f17, $f18 :: fs 456.248962, rt 0x43e41fde
+mov.s $f18, $f19 :: fs 3.000000, rt 0x40400000
+mov.s $f19, $f20 :: fs -1.000000, rt 0xbf800000
+mov.s $f20, $f21 :: fs 1384.599976, rt 0x44ad1333
+mov.s $f21, $f22 :: fs -7.294568, rt 0xc0e96d19
+mov.s $f22, $f23 :: fs 1000000000.000000, rt 0x4e6e6b28
+mov.s $f23, $f24 :: fs -5786.470215, rt 0xc5b4d3c3
+mov.s $f24, $f25 :: fs 1752.000000, rt 0x44db0000
+mov.s $f25, $f26 :: fs 0.002457, rt 0x3b210e02
+MOV.D
+mov.d $f0, $f0 ::fs 0.000000, rt 0x43e41fde
+mov.d $f0, $f0 ::fs 32.000023, rt 0xbf800000
+mov.d $f0, $f2 ::fs 68651422688883217793024.000000, rt 0xc0e96d19
+mov.d $f2, $f4 ::fs 6560668703763947508025308754622564314214011401697745896073690307624960.000000, rt 0xc5b4d3c3
+mov.d $f2, $f4 ::fs 510015646723392374046720.000000, rt 0x3b210e02
+mov.d $f4, $f6 ::fs 0.000000, rt 0xc872bcb1
+mov.d $f4, $f6 ::fs -97892595594330935155564225983676416.000000, rt 0x43e41fde
+mov.d $f6, $f8 ::fs 12885895398.356678, rt 0x4732da7a
+mov.d $f6, $f8 ::fs 499539571012599806217935122808662584365932347392.000000, rt 0x42d60000
+mov.d $f8, $f10 ::fs 0.000000, rt 0x43e41fde
+mov.d $f8, $f10 ::fs 32.000023, rt 0xbf800000
+mov.d $f10, $f12 ::fs 68651422688883217793024.000000, rt 0xc0e96d19
+mov.d $f10, $f12 ::fs 6560668703763947508025308754622564314214011401697745896073690307624960.000000, rt 0xc5b4d3c3
+mov.d $f12, $f14 ::fs 510015646723392374046720.000000, rt 0x3b210e02
+mov.d $f12, $f14 ::fs 0.000000, rt 0xc872bcb1
+mov.d $f14, $f16 ::fs -97892595594330935155564225983676416.000000, rt 0x43e41fde
+mov.d $f14, $f16 ::fs 12885895398.356678, rt 0x4732da7a
+mov.d $f16, $f18 ::fs 499539571012599806217935122808662584365932347392.000000, rt 0x42d60000
+mov.d $f16, $f18 ::fs 0.000000, rt 0x43e41fde
+mov.d $f18, $f20 ::fs 32.000023, rt 0xbf800000
+mov.d $f18, $f20 ::fs 68651422688883217793024.000000, rt 0xc0e96d19
+mov.d $f20, $f22 ::fs 6560668703763947508025308754622564314214011401697745896073690307624960.000000, rt 0xc5b4d3c3
+mov.d $f20, $f22 ::fs 510015646723392374046720.000000, rt 0x3b210e02
+mov.d $f22, $f24 ::fs 0.000000, rt 0xc872bcb1
+mov.d $f22, $f24 ::fs -97892595594330935155564225983676416.000000, rt 0x43e41fde
+mov.d $f24, $f26 ::fs 12885895398.356678, rt 0x4732da7a
+mov.d $f24, $f26 ::fs 499539571012599806217935122808662584365932347392.000000, rt 0x42d60000
+MOVF
+movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
+MOVF.S
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 3.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -1.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1384.599976, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -7.294568, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1000000000.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -5786.470215, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1752.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 0.002457, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -248562.765625, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+MOVF.D
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xb750e388 0x42026580, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xe2308c3a 0x3e45798e, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3746f65f 0x3fbf9add, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x66666666 0x4095a266, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0x3ff00000, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x262d2d2a 0x252a2e2b, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xb750e388 0x42026580, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xe2308c3a 0x3e45798e, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3746f65f 0x3fbf9add, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x66666666 0x4095a266, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0x3ff00000, cc: 0
+MOVN.S
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.s $f0, $f2, $t3 :: fs rt 0x40400000
+movn.s $f0, $f2, $t3 :: fs rt 0xbf800000
+movn.s $f0, $f2, $t3 :: fs rt 0x44ad1333
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
+movn.s $f0, $f2, $t3 :: fs rt 0x44db0000
+movn.s $f0, $f2, $t3 :: fs rt 0x3b210e02
+movn.s $f0, $f2, $t3 :: fs rt 0x322bcc77
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.s $f0, $f2, $t3 :: fs rt 0x42080079
+movn.s $f0, $f2, $t3 :: fs rt 0x4732da7a
+MOVN.D
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.d $f0, $f2, $t3 :: fs rt 0x40400000
+movn.d $f0, $f2, $t3 :: fs rt 0xbf800000
+movn.d $f0, $f2, $t3 :: fs rt 0x44ad1333
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
+movn.d $f0, $f2, $t3 :: fs rt 0x44db0000
+movn.d $f0, $f2, $t3 :: fs rt 0x3b210e02
+movn.d $f0, $f2, $t3 :: fs rt 0x322bcc77
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.d $f0, $f2, $t3 :: fs rt 0x42080079
+movn.d $f0, $f2, $t3 :: fs rt 0x4732da7a
+MOVT
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
+MOVT.S
+movt.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 3.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -1.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1384.599976, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -7.294568, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1000000000.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -5786.470215, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1752.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 0.002457, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -248562.765625, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+MOVT.D
+movt.d $f4, $f6, $fcc0 :: out: 0x66666666 0x4095a266, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0x3ff00000, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x262d2d2a 0x252a2e2b, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xb750e388 0x42026580, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xe2308c3a 0x3e45798e, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3746f65f 0x3fbf9add, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x66666666 0x4095a266, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0x3ff00000, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x262d2d2a 0x252a2e2b, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+MOVZ.S
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0xc0e96d19
+movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0xc872bcb1
+movz.s $f0, $f2, $t3 :: fs rt 0xc732da7a
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+MOVZ.D
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0xc0e96d19
+movz.d $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0xc872bcb1
+movz.d $f0, $f2, $t3 :: fs rt 0xc732da7a
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
diff --git a/none/tests/mips32/MoveIns.stdout.exp-mips32r2-LE b/none/tests/mips32/MoveIns.stdout.exp-mips32r2-LE
new file mode 100644
index 0000000..22f1ab9
--- /dev/null
+++ b/none/tests/mips32/MoveIns.stdout.exp-mips32r2-LE
@@ -0,0 +1,373 @@
+MFC1
+mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
+mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
+mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
+mfc1 $t4, $f3 :: fs 0.000000, rt 0x0
+mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
+mfc1 $t6, $f5 :: fs 0.000000, rt 0x0
+mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
+mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
+mfc1 $v1, $f8 :: fs nan, rt 0xffffffff
+mfc1 $s0, $f9 :: fs nan, rt 0xffffffff
+mfc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
+mfc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
+mfc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
+mfc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
+mfc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
+mfc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
+mfc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
+mfc1 $a0, $f17 :: fs 4.676074, rt 0x4095a266
+mfc1 $a1, $f18 :: fs 272008302207532160516096.000000, rt 0x66666666
+mfc1 $a2, $f19 :: fs -1.875000, rt 0xbff00000
+mfc1 $a3, $f20 :: fs 0.000000, rt 0x0
+mfc1 $v0, $f21 :: fs 1.875000, rt 0x3ff00000
+mfc1 $v1, $f22 :: fs 0.000000, rt 0x0
+mfc1 $t8, $f23 :: fs 0.000000, rt 0x252a2e2b
+mfc1 $t9, $f24 :: fs 0.000000, rt 0x262d2d2a
+mfc1 $t1, $f25 :: fs nan, rt 0xffffffff
+mfc1 $t2, $f26 :: fs nan, rt 0xffffffff
+MTC1
+mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
+mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
+mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
+mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
+mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
+mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
+mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
+mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
+mtc1 $v1, $f8 :: fs nan, rt 0xffffffff
+mtc1 $s0, $f9 :: fs nan, rt 0xffffffff
+mtc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
+mtc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
+mtc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
+mtc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
+mtc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
+mtc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
+mtc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
+mtc1 $a0, $f17 :: fs 271833904815561865428992.000000, rt 0x66664095
+mtc1 $a1, $f18 :: fs 0.000000, rt 0x6666
+mtc1 $a2, $f19 :: fs 0.000000, rt 0xbff0
+mtc1 $a3, $f20 :: fs 0.000000, rt 0x0
+mtc1 $v0, $f21 :: fs 0.000000, rt 0x3ff0
+mtc1 $v1, $f22 :: fs 0.000000, rt 0x2e2b0000
+mtc1 $t8, $f23 :: fs 0.000000, rt 0x2d2a252a
+mtc1 $t9, $f24 :: fs nan, rt 0xffff262d
+mtc1 $t1, $f25 :: fs nan, rt 0xffffffff
+mtc1 $t2, $f26 :: fs 76148150529073774329856.000000, rt 0x6580ffff
+MFHC1
+mfhc1 $t1, $f0 :: rt 0x12345678
+mfhc1 $t2, $f2 :: rt 0x66785bd6
+mfhc1 $t3, $f4 :: rt 0xbff550ff
+mfhc1 $v0, $f6 :: rt 0x47892
+mfhc1 $v1, $f8 :: rt 0x3ff00012
+mfhc1 $a0, $f10 :: rt 0x123654
+mfhc1 $a1, $f12 :: rt 0x252a2e2b
+mfhc1 $a2, $f14 :: rt 0x26852147
+mfhc1 $a3, $f16 :: rt 0x12345678
+mfhc1 $s0, $f18 :: rt 0x66785bd6
+mfhc1 $s1, $f20 :: rt 0x789651ff
+mfhc1 $s2, $f22 :: rt 0xff23f4
+mfhc1 $s3, $f24 :: rt 0x3ff00012
+mfhc1 $s4, $f26 :: rt 0xaabbcdfe
+mfhc1 $s5, $f28 :: rt 0xa1b2b2a1
+mfhc1 $s6, $f30 :: rt 0x25698741
+MTHC1
+mthc1 $t2, $f0 :: out: 4095a26687654321
+mthc1 $t3, $f2 :: out: 6666666668466667
+mthc1 $v0, $f4 :: out: bff0000007788000
+mthc1 $v1, $f6 :: out: 36500000
+mthc1 $a0, $f8 :: out: 3ff0000056789600
+mthc1 $a1, $f10 :: out: 78000000
+mthc1 $a2, $f12 :: out: 1252a2e2b
+mthc1 $a3, $f14 :: out: 262d2d2a962d2d2a
+mthc1 $s0, $f16 :: out: ffffffff87654321
+mthc1 $s1, $f18 :: out: ffffffff68466667
+mthc1 $s2, $f20 :: out: 41d2658007788055
+mthc1 $s3, $f22 :: out: b487e5c9f1f5f6f8
+mthc1 $s4, $f24 :: out: 4202658056789600
+mthc1 $s5, $f26 :: out: b750e388efcd1256
+mthc1 $s6, $f28 :: out: 3e45798ea3a5a6aa
+mthc1 $s7, $f30 :: out: e2308c3a23654786
+MOV.S
+mov.s $f0, $f0 :: fs 0.000000, rt 0x0
+mov.s $f0, $f1 :: fs 456.248962, rt 0x43e41fde
+mov.s $f1, $f2 :: fs 3.000000, rt 0x40400000
+mov.s $f2, $f3 :: fs -1.000000, rt 0xbf800000
+mov.s $f3, $f4 :: fs 1384.599976, rt 0x44ad1333
+mov.s $f4, $f5 :: fs -7.294568, rt 0xc0e96d19
+mov.s $f5, $f6 :: fs 1000000000.000000, rt 0x4e6e6b28
+mov.s $f6, $f7 :: fs -5786.470215, rt 0xc5b4d3c3
+mov.s $f7, $f8 :: fs 1752.000000, rt 0x44db0000
+mov.s $f8, $f9 :: fs 0.002457, rt 0x3b210e02
+mov.s $f9, $f10 :: fs 0.000000, rt 0x322bcc77
+mov.s $f10, $f11 :: fs -248562.765625, rt 0xc872bcb1
+mov.s $f11, $f12 :: fs -45786.476562, rt 0xc732da7a
+mov.s $f12, $f13 :: fs 456.248962, rt 0x43e41fde
+mov.s $f13, $f14 :: fs 34.000462, rt 0x42080079
+mov.s $f14, $f15 :: fs 45786.476562, rt 0x4732da7a
+mov.s $f15, $f16 :: fs 1752065.000000, rt 0x49d5e008
+mov.s $f16, $f17 :: fs 0.000000, rt 0x0
+mov.s $f17, $f18 :: fs 456.248962, rt 0x43e41fde
+mov.s $f18, $f19 :: fs 3.000000, rt 0x40400000
+mov.s $f19, $f20 :: fs -1.000000, rt 0xbf800000
+mov.s $f20, $f21 :: fs 1384.599976, rt 0x44ad1333
+mov.s $f21, $f22 :: fs -7.294568, rt 0xc0e96d19
+mov.s $f22, $f23 :: fs 1000000000.000000, rt 0x4e6e6b28
+mov.s $f23, $f24 :: fs -5786.470215, rt 0xc5b4d3c3
+mov.s $f24, $f25 :: fs 1752.000000, rt 0x44db0000
+mov.s $f25, $f26 :: fs 0.002457, rt 0x3b210e02
+MOV.D
+mov.d $f0, $f0 ::fs 11600973572943642624.000000, rt 0x0
+mov.d $f0, $f0 ::fs -0.007813, rt 0x40400000
+mov.d $f0, $f2 ::fs -52072.789633, rt 0x44ad1333
+mov.d $f2, $f4 ::fs -6445705852632282607665545216.000000, rt 0x4e6e6b28
+mov.d $f2, $f4 ::fs 0.000000, rt 0x44db0000
+mov.d $f4, $f6 ::fs -102014360350703794652958156923702465265664.000000, rt 0x322bcc77
+mov.d $f4, $f6 ::fs 11600980417357008896.000000, rt 0xc732da7a
+mov.d $f6, $f8 ::fs 97892595018733988536880335157198848.000000, rt 0x42080079
+mov.d $f6, $f8 ::fs 96757042599808.125000, rt 0x49d5e008
+mov.d $f8, $f10 ::fs 11600973572943642624.000000, rt 0x0
+mov.d $f8, $f10 ::fs -0.007813, rt 0x40400000
+mov.d $f10, $f12 ::fs -52072.789633, rt 0x44ad1333
+mov.d $f10, $f12 ::fs -6445705852632282607665545216.000000, rt 0x4e6e6b28
+mov.d $f12, $f14 ::fs 0.000000, rt 0x44db0000
+mov.d $f12, $f14 ::fs -102014360350703794652958156923702465265664.000000, rt 0x322bcc77
+mov.d $f14, $f16 ::fs 11600980417357008896.000000, rt 0xc732da7a
+mov.d $f14, $f16 ::fs 97892595018733988536880335157198848.000000, rt 0x42080079
+mov.d $f16, $f18 ::fs 96757042599808.125000, rt 0x49d5e008
+mov.d $f16, $f18 ::fs 11600973572943642624.000000, rt 0x0
+mov.d $f18, $f20 ::fs -0.007813, rt 0x40400000
+mov.d $f18, $f20 ::fs -52072.789633, rt 0x44ad1333
+mov.d $f20, $f22 ::fs -6445705852632282607665545216.000000, rt 0x4e6e6b28
+mov.d $f20, $f22 ::fs 0.000000, rt 0x44db0000
+mov.d $f22, $f24 ::fs -102014360350703794652958156923702465265664.000000, rt 0x322bcc77
+mov.d $f22, $f24 ::fs 11600980417357008896.000000, rt 0xc732da7a
+mov.d $f24, $f26 ::fs 97892595018733988536880335157198848.000000, rt 0x42080079
+mov.d $f24, $f26 ::fs 96757042599808.125000, rt 0x49d5e008
+MOVF
+movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
+MOVF.S
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 3.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -1.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1384.599976, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -7.294568, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1000000000.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -5786.470215, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1752.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 0.002457, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -248562.765625, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+MOVF.D
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42026580 0xb750e388, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3e45798e 0xe2308c3a, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3fbf9add 0x3746f65f, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x4095a266 0x66666666, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3ff00000 0x0, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x252a2e2b 0x262d2d2a, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x42026580 0xb750e388, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3e45798e 0xe2308c3a, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3fbf9add 0x3746f65f, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x4095a266 0x66666666, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3ff00000 0x0, cc: 0
+MOVN.S
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.s $f0, $f2, $t3 :: fs rt 0x40400000
+movn.s $f0, $f2, $t3 :: fs rt 0xbf800000
+movn.s $f0, $f2, $t3 :: fs rt 0x44ad1333
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
+movn.s $f0, $f2, $t3 :: fs rt 0x44db0000
+movn.s $f0, $f2, $t3 :: fs rt 0x3b210e02
+movn.s $f0, $f2, $t3 :: fs rt 0x322bcc77
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.s $f0, $f2, $t3 :: fs rt 0x42080079
+movn.s $f0, $f2, $t3 :: fs rt 0x4732da7a
+MOVN.D
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.d $f0, $f2, $t3 :: fs rt 0x40400000
+movn.d $f0, $f2, $t3 :: fs rt 0xbf800000
+movn.d $f0, $f2, $t3 :: fs rt 0x44ad1333
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
+movn.d $f0, $f2, $t3 :: fs rt 0x44db0000
+movn.d $f0, $f2, $t3 :: fs rt 0x3b210e02
+movn.d $f0, $f2, $t3 :: fs rt 0x322bcc77
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.d $f0, $f2, $t3 :: fs rt 0x42080079
+movn.d $f0, $f2, $t3 :: fs rt 0x4732da7a
+MOVT
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
+MOVT.S
+movt.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 3.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -1.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1384.599976, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -7.294568, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1000000000.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -5786.470215, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1752.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 0.002457, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -248562.765625, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+MOVT.D
+movt.d $f4, $f6, $fcc0 :: out: 0x4095a266 0x66666666, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3ff00000 0x0, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x252a2e2b 0x262d2d2a, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x42026580 0xb750e388, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3e45798e 0xe2308c3a, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3fbf9add 0x3746f65f, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x4095a266 0x66666666, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3ff00000 0x0, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x252a2e2b 0x262d2d2a, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+MOVZ.S
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0xc0e96d19
+movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0xc872bcb1
+movz.s $f0, $f2, $t3 :: fs rt 0xc732da7a
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+MOVZ.D
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0xc0e96d19
+movz.d $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0xc872bcb1
+movz.d $f0, $f2, $t3 :: fs rt 0xc732da7a
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
diff --git a/none/tests/mips32/MoveIns.vgtest b/none/tests/mips32/MoveIns.vgtest
index 662bf4f..5725290 100644
--- a/none/tests/mips32/MoveIns.vgtest
+++ b/none/tests/mips32/MoveIns.vgtest
@@ -1,2 +1,3 @@
prog: MoveIns
+prereq: ../../../tests/mips_features fpu
vgopts: -q
diff --git a/none/tests/mips32/allexec.c b/none/tests/mips32/allexec.c
deleted file mode 120000
index 6d6a9cf..0000000
--- a/none/tests/mips32/allexec.c
+++ /dev/null
@@ -1 +0,0 @@
-../allexec.c
\ No newline at end of file
diff --git a/none/tests/allexec.c b/none/tests/mips32/allexec.c
similarity index 100%
copy from none/tests/allexec.c
copy to none/tests/mips32/allexec.c
diff --git a/none/tests/mips32/change_fp_mode.c b/none/tests/mips32/change_fp_mode.c
new file mode 100644
index 0000000..87b10e9
--- /dev/null
+++ b/none/tests/mips32/change_fp_mode.c
@@ -0,0 +1,85 @@
+#if defined(__mips_hard_float)
+
+#include <elf.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/prctl.h>
+
+#if !defined(PR_SET_FP_MODE)
+# define PR_SET_FP_MODE 45
+#endif
+
+#if !defined(PR_GET_FP_MODE)
+# define PR_GET_FP_MODE 46
+#endif
+
+/* Determine FP mode based on sdc1 behavior
+ returns 1 if FR = 1 mode is detected. */
+static int get_fp_mode(void) {
+ unsigned long long result = 0;
+ __asm__ volatile(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ ".set oddspreg\n\t"
+ "lui $t0, 0x3FF0\n\t"
+ "ldc1 $f0, %0\n\t"
+ "mtc1 $t0, $f1\n\t"
+ "sdc1 $f0, %0\n\t"
+ ".set pop\n\t"
+ : "+m"(result)
+ :
+ : "t0", "$f0", "$f1", "memory");
+
+ return (result != 0x3FF0000000000000ull);
+}
+
+static void fatal_error(const char* msg) {
+ fprintf(stderr, "Error: %s\n", msg);
+ exit(1);
+}
+
+static void test(int* fr_prctl, int* fr_detected) {
+ *fr_prctl = prctl(PR_GET_FP_MODE);
+ *fr_detected = get_fp_mode();
+
+ if (*fr_prctl < 0) {
+ fatal_error("prctl(PR_GET_FP_MODE) fails.");
+ }
+
+ printf("fr_prctl: %d, fr_detected: %d\n", *fr_prctl, *fr_detected);
+
+ if (*fr_prctl != *fr_detected) {
+ fatal_error("fr_prctl != fr_detected");
+ }
+}
+
+int main() {
+ int fr_prctl, fr_detected;
+
+ test(&fr_prctl, &fr_detected);
+
+ /* FP64 */
+ if (fr_prctl == 1) {
+
+ /* Change mode to FP32 */
+ if (prctl(PR_SET_FP_MODE, 0) != 0) {
+ fatal_error("prctl(PR_SET_FP_MODE, 0) fails.");
+ }
+
+ test(&fr_prctl, &fr_detected);
+
+ /* Change back FP mode */
+ if (prctl(PR_SET_FP_MODE, 1) != 0) {
+ fatal_error("prctl(PR_SET_FP_MODE, 1) fails.");
+ }
+
+ test(&fr_prctl, &fr_detected);
+ }
+
+ return 0;
+}
+#else
+int main() {
+ return 0;
+}
+#endif
diff --git a/none/tests/mips32/change_fp_mode.stderr.exp b/none/tests/mips32/change_fp_mode.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/mips32/change_fp_mode.stderr.exp
diff --git a/none/tests/mips32/change_fp_mode.stdout.exp b/none/tests/mips32/change_fp_mode.stdout.exp
new file mode 100644
index 0000000..61640e3
--- /dev/null
+++ b/none/tests/mips32/change_fp_mode.stdout.exp
@@ -0,0 +1,3 @@
+fr_prctl: 1, fr_detected: 1
+fr_prctl: 0, fr_detected: 0
+fr_prctl: 1, fr_detected: 1
diff --git a/none/tests/mips32/change_fp_mode.stdout.exp-fpu32 b/none/tests/mips32/change_fp_mode.stdout.exp-fpu32
new file mode 100644
index 0000000..2525770
--- /dev/null
+++ b/none/tests/mips32/change_fp_mode.stdout.exp-fpu32
@@ -0,0 +1 @@
+fr_prctl: 0, fr_detected: 0
diff --git a/none/tests/mips32/change_fp_mode.vgtest b/none/tests/mips32/change_fp_mode.vgtest
new file mode 100644
index 0000000..df9ed62
--- /dev/null
+++ b/none/tests/mips32/change_fp_mode.vgtest
@@ -0,0 +1,3 @@
+prog: change_fp_mode
+prereq: ../../../tests/mips_features fpu
+vgopts: -q
diff --git a/none/tests/mips32/fpu_branches.c b/none/tests/mips32/fpu_branches.c
index f81321d..dbf9aa0 100644
--- a/none/tests/mips32/fpu_branches.c
+++ b/none/tests/mips32/fpu_branches.c
@@ -1,3 +1,5 @@
+#if defined(__mips_hard_float)
+
#include <stdio.h>
#define MAX_ARR 24
@@ -314,4 +316,8 @@
}
return 0;
}
-
+#else
+int main() {
+ return 0;
+}
+#endif
diff --git a/none/tests/mips32/fpu_branches.vgtest b/none/tests/mips32/fpu_branches.vgtest
index 2066512..1854b59 100644
--- a/none/tests/mips32/fpu_branches.vgtest
+++ b/none/tests/mips32/fpu_branches.vgtest
@@ -1,2 +1,3 @@
prog: fpu_branches
+prereq: ../../../tests/mips_features fpu
vgopts: -q
diff --git a/none/tests/mips32/round.c b/none/tests/mips32/round.c
index 310dd36..feba168 100644
--- a/none/tests/mips32/round.c
+++ b/none/tests/mips32/round.c
@@ -1,3 +1,5 @@
+#if defined(__mips_hard_float)
+
#include <stdio.h>
typedef enum {
@@ -149,12 +151,24 @@
}
}
+void clear_fcc(){
+ __asm__ __volatile__(
+ "cfc1 $t0, $31" "\n\t"
+ "and $t0, $t0, 0x17FFFFF" "\n\t"
+ "ctc1 $t0, $31" "\n\t"
+ :
+ :
+ : "t0"
+ );
+}
+
int directedRoundingMode(flt_dir_op_t op) {
int fd_w = 0;
int i;
int fcsr = 0;
round_mode_t rm = TO_NEAREST;
for (i = 0; i < 24; i++) {
+ clear_fcc();
set_rounding_mode(rm);
switch(op) {
case CEILWS:
@@ -217,6 +231,7 @@
set_rounding_mode(rm);
printf("roundig mode: %s\n", round_mode_name[rm]);
for (i = 0; i < 24; i++) {
+ clear_fcc();
set_rounding_mode(rm);
switch(op1) {
case CVTDS:
@@ -276,4 +291,9 @@
}
return 0;
}
+#else
+int main() {
+ return 0;
+}
+#endif
diff --git a/none/tests/mips32/round.vgtest b/none/tests/mips32/round.vgtest
index d5eb00e..a0374b4 100644
--- a/none/tests/mips32/round.vgtest
+++ b/none/tests/mips32/round.vgtest
@@ -1,2 +1,3 @@
prog: round
+prereq: ../../../tests/mips_features fpu
vgopts: -q
diff --git a/none/tests/mips32/round_fpu64.c b/none/tests/mips32/round_fpu64.c
index 837e4b2..a4715f2 100644
--- a/none/tests/mips32/round_fpu64.c
+++ b/none/tests/mips32/round_fpu64.c
@@ -1,3 +1,5 @@
+#if defined(__mips_hard_float)
+
#include <stdio.h>
#include <stdlib.h>
#include <signal.h>
@@ -202,3 +204,8 @@
#endif
return 0;
}
+#else
+int main() {
+ return 0;
+}
+#endif
diff --git a/none/tests/mips32/round_fpu64.vgtest b/none/tests/mips32/round_fpu64.vgtest
index 95d11b0..92f44af 100644
--- a/none/tests/mips32/round_fpu64.vgtest
+++ b/none/tests/mips32/round_fpu64.vgtest
@@ -1,2 +1,3 @@
prog: round_fpu64
+prereq: ../../../tests/mips_features fpu
vgopts: -q
diff --git a/none/tests/mips32/test_fcsr.c b/none/tests/mips32/test_fcsr.c
index 737c87b..6bb03a0 100644
--- a/none/tests/mips32/test_fcsr.c
+++ b/none/tests/mips32/test_fcsr.c
@@ -1,3 +1,5 @@
+#if defined(__mips_hard_float)
+
#include <stdio.h>
int main ()
@@ -23,3 +25,8 @@
printf("FCSR::1: 0x%x, 2: 0x%x\n", out[0], out[1]);
return 0;
}
+#else
+int main() {
+ return 0;
+}
+#endif
diff --git a/none/tests/mips32/test_fcsr.vgtest b/none/tests/mips32/test_fcsr.vgtest
index c864d25..69dba5b 100644
--- a/none/tests/mips32/test_fcsr.vgtest
+++ b/none/tests/mips32/test_fcsr.vgtest
@@ -1,2 +1,3 @@
prog: test_fcsr
+prereq: ../../../tests/mips_features fpu
vgopts: -q
diff --git a/none/tests/mips32/vfp.c b/none/tests/mips32/vfp.c
index c372658..9412457 100644
--- a/none/tests/mips32/vfp.c
+++ b/none/tests/mips32/vfp.c
@@ -1,3 +1,7 @@
+#if defined(__mips_hard_float)
+#include <setjmp.h>
+#include <signal.h>
+#include <stdint.h>
#include <stdio.h>
unsigned int mem[] = {
@@ -12,6 +16,18 @@
0x3FBF9ADD, 0x3746F65F
};
+long long meml[] = {
+ 0x236457894095A266, 0x7777777766666666,
+ 0xBFF00000aaaaccde, 0x0004563217800000,
+ 0x3FF0556644770000, 0x0002255889900000,
+ 0x25254123698a2e2b, 0x21a2b3d6f62d2d2a,
+ 0xFFaabb22ccFFFFFF, 0x542698eeFFFFFFFF,
+ 0x41D2658041D26580, 0xB487E5C9B487E5C9,
+ 0x420774411aa26580, 0xaabbccddB750E388,
+ 0xffffeeee3E45798E, 0xccccccccE2308C3A,
+ 0x123abb983FBF9ADD, 0x002255443746F65F
+};
+
float fs_f[] = {
0, 456.2489562, 3, -1,
1384.6, -7.2945676, 1000000000, -5786.47,
@@ -45,199 +61,204 @@
};
// ldc1 $f0, 0($t1)
-#if (__mips_fpr==64)
-#define TESTINSN5LOAD(instruction, RTval, offset, RT) \
-{ \
- double out; \
- int out1; \
- int out2; \
- __asm__ volatile( \
- "move $t1, %3\n\t" \
- "li $t0, " #RTval"\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #RT "\n\t" \
- "mfc1 %1, $" #RT "\n\t" \
- "mfhc1 %2, $" #RT "\n\t" \
- : "=&f" (out), "=&r" (out1), "=&r" (out2) \
- : "r" (mem), "r" (RTval) \
- : "cc", "memory" \
- ); \
- printf("%s :: ft 0x%x%x\n", \
- instruction, out1, out2); \
+#define TESTINSN5LOAD(instruction, RTval, offset, RT) \
+{ \
+ double out; \
+ uint64_t outl; \
+ __asm__ volatile( \
+ "move $t1, %1\n\t" \
+ "li $t0, " #RTval"\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #RT "\n\t" \
+ "sdc1 $" #RT ", 0(%3) \n\t" \
+ : "=&f" (out) \
+ : "r" (mem), "r" (RTval), "r" (&outl) \
+ : "t0", "t1", "$"#RT, "memory" \
+ ); \
+ printf("%s :: ft 0x%x%x\n", \
+ instruction, (uint32_t)outl, (uint32_t)(outl >> 32)); \
}
-#else
-#define TESTINSN5LOAD(instruction, RTval, offset, RT) \
-{ \
- double out; \
- int out1; \
- int out2; \
- __asm__ volatile( \
- "move $t1, %3\n\t" \
- "li $t0, " #RTval"\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #RT "\n\t" \
- "mfc1 %1, $" #RT "\n\t" \
- "mfc1 %2, $f1\n\t" \
- : "=&f" (out), "=&r" (out1), "=&r" (out2) \
- : "r" (mem), "r" (RTval) \
- : "cc", "memory" \
- ); \
- printf("%s :: ft 0x%x%x\n", \
- instruction, out1, out2); \
-}
-#endif
// lwc1 $f0, 0($t1)
-#define TESTINSN5LOADw(instruction, RTval, offset, RT) \
-{ \
- double out; \
- int out1; \
- __asm__ volatile( \
- "move $t1, %2\n\t" \
- "li $t0, " #RTval"\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #RT "\n\t" \
- "mfc1 %1, $" #RT "\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (mem), "r" (RTval) \
- : "cc", "memory" \
- ); \
- printf("%s :: ft 0x%x\n", \
- instruction, out1); \
+#define TESTINSN5LOADw(instruction, RTval, offset, RT) \
+{ \
+ double out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $t1, %2\n\t" \
+ "li $t0, " #RTval"\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #RT "\n\t" \
+ "mfc1 %1, $" #RT "\n\t" \
+ : "=f" (out), "=r" (out1) \
+ : "r" (mem), "r" (RTval) \
+ : "t0", "t1", "$"#RT, "memory" \
+ ); \
+ printf("%s :: ft 0x%x\n", \
+ instruction, out1); \
}
// lwxc1 $f0, $a3($v0)
-#define TESTINSN6LOADw(instruction, indexVal, fd, index, base) \
-{ \
- int out; \
- __asm__ volatile( \
- "move $" #base ", %1\n\t" \
- "li $" #index ", " #indexVal"\n\t" \
- instruction "\n\t" \
- "mfc1 %0, $" #fd "\n\t" \
- : "=&r" (out) \
- : "r" (mem) \
- : "cc", "memory" \
- ); \
- printf("%s :: ft 0x%x\n", \
- instruction, out); \
+#define TESTINSN6LOADw(instruction, indexVal, fd, index, base) \
+{ \
+ int out; \
+ __asm__ volatile( \
+ "move $" #base ", %1\n\t" \
+ "li $" #index ", " #indexVal"\n\t" \
+ instruction "\n\t" \
+ "mfc1 %0, $" #fd "\n\t" \
+ : "=r" (out) \
+ : "r" (mem) \
+ : #base, #index, "$"#fd, "memory" \
+ ); \
+ printf("%s :: ft 0x%x\n", \
+ instruction, out); \
}
// ldxc1 $f0, $a3($v0)
-#if (__mips_fpr==64)
-#define TESTINSN6LOADd(instruction, indexVal, fd, index, base) \
-{ \
- int out1; \
- int out2; \
- __asm__ volatile( \
- "move $" #base ", %2\n\t" \
- "li $" #index ", " #indexVal"\n\t" \
- instruction "\n\t" \
- "mfc1 %0, $" #fd "\n\t" \
- "mfhc1 %1, $" #fd "\n\t" \
- : "=&r" (out1), "=&r" (out2) \
- : "r" (mem) \
- : "cc", "memory" \
- ); \
- printf("%s :: ft lo: 0x%x, ft hi: 0x%x\n", \
- instruction, out1, out2); \
+#define TESTINSN6LOADd(instruction, indexVal, fd, index, base) \
+{ \
+ uint64_t out; \
+ __asm__ volatile( \
+ "move $" #base ", %0\n\t" \
+ "li $" #index ", " #indexVal"\n\t" \
+ instruction "\n\t" \
+ "sdc1 $"#fd ", 0(%1)" \
+ : : "r" (mem), "r" (&out) \
+ : #base, #index, "$"#fd, "memory" \
+ ); \
+ printf("%s :: ft lo: 0x%x, ft hi: 0x%x\n", \
+ instruction, (uint32_t)out, (uint32_t)(out >> 32)); \
}
-#else
-#define TESTINSN6LOADd(instruction, indexVal, fd, index, base) \
-{ \
- int out1; \
- int out2; \
- __asm__ volatile( \
- "move $" #base ", %2\n\t" \
- "li $" #index ", " #indexVal"\n\t" \
- instruction "\n\t" \
- "mfc1 %0, $" #fd "\n\t" \
- "mfc1 %1, $f1\n\t" \
- : "=&r" (out1), "=&r" (out2) \
- : "r" (mem) \
- : "cc", "memory" \
- ); \
- printf("%s :: ft lo: 0x%x, ft hi: 0x%x\n", \
- instruction, out1, out2); \
+
+// luxc1 $f0, $a3($v0)
+#define TESTINSN6LOADlu(instruction, indexVal, fd, index, base) \
+{ \
+ uint64_t out; \
+ __asm__ volatile( \
+ "move $" #base ", %0\n\t" \
+ "li $" #index ", " #indexVal"\n\t" \
+ instruction "\n\t" \
+ "sdc1 $"#fd ", 0(%1)" \
+ : : "r" (meml), "r" (&out) \
+ : #base, #index, "$"#fd, "memory" \
+ ); \
+ printf("%s :: ft lo: 0x%x, ft hi: 0x%x\n", \
+ instruction, (uint32_t)out, (uint32_t)(out >> 32)); \
}
-#endif
// sdc1 $f0, 0($t0)
-#define TESTINST1(offset) \
-{ \
- unsigned int out; \
- __asm__ volatile( \
- "move $t0, %1\n\t" \
- "move $t1, %2\n\t" \
- "ldc1 $f0, "#offset"($t1)\n\t" \
- "sdc1 $f0, "#offset"($t0) \n\t" \
- "lw %0, "#offset"($t0)\n\t" \
- : "=&r" (out) \
- : "r" (mem1), "r" (fs_d) \
- : "t1", "t0", "cc", "memory" \
- ); \
- printf("sdc1 $f0, 0($t0) :: out: 0x%x\n", \
- out); \
+#define TESTINST1(offset) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $t0, %1\n\t" \
+ "move $t1, %2\n\t" \
+ "ldc1 $f0, "#offset"($t1)\n\t" \
+ "sdc1 $f0, "#offset"($t0) \n\t" \
+ "lw %0, "#offset"($t0)\n\t" \
+ : "=r" (out) \
+ : "r" (mem1), "r" (fs_d) \
+ : "t1", "t0", "$f0", "memory" \
+ ); \
+ printf("sdc1 $f0, 0($t0) :: out: 0x%x\n", \
+ out); \
}
// sdxc1 $f0, $t2($t0)
-#define TESTINST1a(offset) \
-{ \
- unsigned int out; \
- unsigned int out1; \
- __asm__ volatile( \
- "move $t0, %2\n\t" \
- "move $t1, %3\n\t" \
- "li $t2, "#offset"\n\t" \
- "ldc1 $f0, "#offset"($t1)\n\t" \
- "sdxc1 $f0, $t2($t0) \n\t" \
- "lw %0, "#offset"($t0)\n\t" \
- "addi $t0, $t0, 4 \n\t" \
- "lw %1, "#offset"($t0)\n\t" \
- : "=&r" (out), "=&r" (out1) \
- : "r" (mem1), "r" (fs_d) \
- : "t2", "t1", "t0", "cc", "memory" \
- ); \
- printf("sdc1 $f0, #t2($t0) :: out: 0x%x : out1: 0x%x\n", \
- out, out1); \
+#define TESTINST1a(offset) \
+{ \
+ unsigned int out; \
+ unsigned int out1; \
+ __asm__ volatile( \
+ "move $t0, %2\n\t" \
+ "move $t1, %3\n\t" \
+ "li $t2, "#offset"\n\t" \
+ "ldc1 $f0, "#offset"($t1)\n\t" \
+ "sdxc1 $f0, $t2($t0) \n\t" \
+ "lw %0, "#offset"($t0)\n\t" \
+ "addi $t0, $t0, 4 \n\t" \
+ "lw %1, "#offset"($t0)\n\t" \
+ : "=r" (out), "=r" (out1) \
+ : "r" (mem1), "r" (fs_d) \
+ : "t2", "t1", "t0", "$f0", "memory" \
+ ); \
+ printf("sdc1 $f0, #t2($t0) :: out: 0x%x : out1: 0x%x\n", \
+ out, out1); \
+}
+
+// SUXC1 $f0, $t2($t0)
+#define TESTINST1b(offset, unligned_offset) \
+{ \
+ unsigned int out; \
+ unsigned int out1; \
+ __asm__ volatile( \
+ "move $t0, %2\n\t" \
+ "move $t1, %3\n\t" \
+ "li $t2, "#unligned_offset"\n\t" \
+ "ldc1 $f0, "#offset"($t1)\n\t" \
+ "suxc1 $f0, $t2($t0) \n\t" \
+ "lw %0, "#offset"($t0)\n\t" \
+ "addi $t0, $t0, 4 \n\t" \
+ "lw %1, "#offset"($t0)\n\t" \
+ : "=r" (out), "=r" (out1) \
+ : "r" (mem1), "r" (fs_d) \
+ : "t2", "t1", "t0", "$f0", "memory" \
+ ); \
+ printf("suxc1 $f0, #t2($t0) :: out: 0x%x : out1: 0x%x\n", \
+ out, out1); \
}
// swc1 $f0, 0($t0)
-#define TESTINST2(offset) \
-{ \
- unsigned int out; \
- __asm__ volatile( \
- "move $t0, %1\n\t" \
- "move $t1, %2\n\t" \
- "lwc1 $f0, "#offset"($t1)\n\t" \
- "swc1 $f0, "#offset"($t0) \n\t" \
- "lw %0, "#offset"($t0)\n\t" \
- : "=&r" (out) \
- : "r" (mem1f), "r" (fs_f) \
- : "t1", "t0", "cc", "memory" \
- ); \
- printf("swc1 $f0, 0($t0) :: out: 0x%x\n", \
- out); \
+#define TESTINST2(offset) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $t0, %1\n\t" \
+ "move $t1, %2\n\t" \
+ "lwc1 $f0, "#offset"($t1)\n\t" \
+ "swc1 $f0, "#offset"($t0) \n\t" \
+ "lw %0, "#offset"($t0)\n\t" \
+ : "=r" (out) \
+ : "r" (mem1f), "r" (fs_f) \
+ : "t1", "t0", "$f0", "memory" \
+ ); \
+ printf("swc1 $f0, 0($t0) :: out: 0x%x\n", \
+ out); \
}
// SWXC1 $f0, $t2($t0)
-#define TESTINST2a(offset) \
-{ \
- unsigned int out; \
- __asm__ volatile( \
- "move $t0, %1\n\t" \
- "move $t1, %2\n\t" \
- "li $t2, "#offset" \n\t" \
- "lwc1 $f0, "#offset"($t1)\n\t" \
- "swxc1 $f0, $t2($t0) \n\t" \
- "lw %0, "#offset"($t0)\n\t" \
- : "=&r" (out) \
- : "r" (mem1f), "r" (fs_f) \
- : "t2", "t1", "t0", "cc", "memory" \
- ); \
- printf("swxc1 $f0, 0($t0) :: out: 0x%x\n", \
- out); \
+#define TESTINST2a(offset) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $t0, %1\n\t" \
+ "move $t1, %2\n\t" \
+ "li $t2, "#offset" \n\t" \
+ "lwc1 $f0, "#offset"($t1)\n\t" \
+ "swxc1 $f0, $t2($t0) \n\t" \
+ "lw %0, "#offset"($t0)\n\t" \
+ : "=r" (out) \
+ : "r" (mem1f), "r" (fs_f) \
+ : "t2", "t1", "t0", "$f0", "memory" \
+ ); \
+ printf("swxc1 $f0, 0($t0) :: out: 0x%x\n", \
+ out); \
}
+
+#define TEST_FPU64 \
+ __asm__ __volatile__( \
+ "cvt.l.s $f0, $f0" "\n\t" \
+ : \
+ : \
+ : "$f0" \
+ );
+
+static void handler(int sig)
+{
+ exit(0);
+}
+
void ppMem(double *m, int len)
{
int i;
@@ -448,6 +469,70 @@
ppMemF(mem1f, 16);
#endif
+#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_fpr==64 || __mips_fpr==xx)
+ signal(SIGILL, handler);
+ /* Test fpu64 mode. */
+ TEST_FPU64;
+
+ printf("luxc1\n");
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 40, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 48, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 56, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 64, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 40, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 48, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 56, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 64, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 40, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 48, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 56, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 64, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+
+ printf("SUXC1\n");
+ TESTINST1b(0, 0);
+ TESTINST1b(0, 1);
+ TESTINST1b(8, 8);
+ TESTINST1b(8, 9);
+ TESTINST1b(16, 16);
+ TESTINST1b(16, 17);
+ TESTINST1b(24, 24);
+ TESTINST1b(24, 25);
+ TESTINST1b(32, 32);
+ TESTINST1b(32, 35);
+ TESTINST1b(40, 40);
+ TESTINST1b(40, 42);
+ TESTINST1b(48, 48);
+ TESTINST1b(48, 50);
+ TESTINST1b(56, 56);
+ TESTINST1b(56, 60);
+ TESTINST1b(64, 64);
+ TESTINST1b(64, 67);
+ ppMem(mem1, 16);
+#endif
return 0;
}
-
+#else
+int main() {
+ return 0;
+}
+#endif
diff --git a/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-BE b/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-BE
new file mode 100644
index 0000000..7e6477f
--- /dev/null
+++ b/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-BE
@@ -0,0 +1,239 @@
+LDC1
+ldc1 $f0, 0($t1) :: ft 0x666666664095a266
+ldc1 $f0, 8($t1) :: ft 0x0bff00000
+ldc1 $f0, 16($t1) :: ft 0x03ff00000
+ldc1 $f0, 24($t1) :: ft 0x262d2d2a252a2e2b
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0xb487e5c941d26580
+ldc1 $f0, 48($t1) :: ft 0xb750e38842026580
+ldc1 $f0, 56($t1) :: ft 0xe2308c3a3e45798e
+ldc1 $f0, 64($t1) :: ft 0x3746f65f3fbf9add
+ldc1 $f0, 0($t1) :: ft 0x666666664095a266
+ldc1 $f0, 8($t1) :: ft 0x0bff00000
+ldc1 $f0, 16($t1) :: ft 0x03ff00000
+ldc1 $f0, 24($t1) :: ft 0x262d2d2a252a2e2b
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0xb487e5c941d26580
+ldc1 $f0, 48($t1) :: ft 0xb750e38842026580
+ldc1 $f0, 56($t1) :: ft 0xe2308c3a3e45798e
+ldc1 $f0, 0($t1) :: ft 0x666666664095a266
+ldc1 $f0, 8($t1) :: ft 0x0bff00000
+ldc1 $f0, 16($t1) :: ft 0x03ff00000
+ldc1 $f0, 24($t1) :: ft 0x262d2d2a252a2e2b
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0xb487e5c941d26580
+ldc1 $f0, 48($t1) :: ft 0xb750e38842026580
+ldc1 $f0, 56($t1) :: ft 0xe2308c3a3e45798e
+ldc1 $f0, 64($t1) :: ft 0x3746f65f3fbf9add
+ldc1 $f0, 0($t1) :: ft 0x666666664095a266
+LWC1
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+lwc1 $f0, 4($t1) :: ft 0x66666666
+lwc1 $f0, 8($t1) :: ft 0xbff00000
+lwc1 $f0, 12($t1) :: ft 0x0
+lwc1 $f0, 16($t1) :: ft 0x3ff00000
+lwc1 $f0, 20($t1) :: ft 0x0
+lwc1 $f0, 24($t1) :: ft 0x252a2e2b
+lwc1 $f0, 28($t1) :: ft 0x262d2d2a
+lwc1 $f0, 32($t1) :: ft 0xffffffff
+lwc1 $f0, 36($t1) :: ft 0xffffffff
+lwc1 $f0, 40($t1) :: ft 0x41d26580
+lwc1 $f0, 44($t1) :: ft 0xb487e5c9
+lwc1 $f0, 48($t1) :: ft 0x42026580
+lwc1 $f0, 52($t1) :: ft 0xb750e388
+lwc1 $f0, 56($t1) :: ft 0x3e45798e
+lwc1 $f0, 60($t1) :: ft 0xe2308c3a
+lwc1 $f0, 64($t1) :: ft 0x3fbf9add
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+lwc1 $f0, 8($t1) :: ft 0xbff00000
+lwc1 $f0, 16($t1) :: ft 0x3ff00000
+lwc1 $f0, 24($t1) :: ft 0x252a2e2b
+lwc1 $f0, 32($t1) :: ft 0xffffffff
+lwc1 $f0, 40($t1) :: ft 0x41d26580
+lwc1 $f0, 48($t1) :: ft 0x42026580
+lwc1 $f0, 56($t1) :: ft 0x3e45798e
+lwc1 $f0, 64($t1) :: ft 0x3fbf9add
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+LWXC1
+lwxc1 $f0, $a3($v0) :: ft 0x4095a266
+lwxc1 $f0, $a3($v0) :: ft 0x66666666
+lwxc1 $f0, $a3($v0) :: ft 0xbff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x3ff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+lwxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0x41d26580
+lwxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+lwxc1 $f0, $a3($v0) :: ft 0x42026580
+lwxc1 $f0, $a3($v0) :: ft 0xb750e388
+lwxc1 $f0, $a3($v0) :: ft 0x3e45798e
+lwxc1 $f0, $a3($v0) :: ft 0xe2308c3a
+lwxc1 $f0, $a3($v0) :: ft 0x3fbf9add
+lwxc1 $f0, $a3($v0) :: ft 0x4095a266
+lwxc1 $f0, $a3($v0) :: ft 0x66666666
+lwxc1 $f0, $a3($v0) :: ft 0xbff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x3ff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+lwxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0x41d26580
+lwxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+lwxc1 $f0, $a3($v0) :: ft 0x42026580
+lwxc1 $f0, $a3($v0) :: ft 0xb750e388
+lwxc1 $f0, $a3($v0) :: ft 0x3e45798e
+LDXC1
+ldxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x4095a266
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0xbff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0x3ff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x262d2d2a, ft hi: 0x252a2e2b
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft lo: 0xb487e5c9, ft hi: 0x41d26580
+ldxc1 $f0, $a3($v0) :: ft lo: 0xb750e388, ft hi: 0x42026580
+ldxc1 $f0, $a3($v0) :: ft lo: 0xe2308c3a, ft hi: 0x3e45798e
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3746f65f, ft hi: 0x3fbf9add
+ldxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x4095a266
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0xbff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0x3ff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x262d2d2a, ft hi: 0x252a2e2b
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft lo: 0xb487e5c9, ft hi: 0x41d26580
+ldxc1 $f0, $a3($v0) :: ft lo: 0xb750e388, ft hi: 0x42026580
+ldxc1 $f0, $a3($v0) :: ft lo: 0xe2308c3a, ft hi: 0x3e45798e
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3746f65f, ft hi: 0x3fbf9add
+ldxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x4095a266
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0xbff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0x3ff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x262d2d2a, ft hi: 0x252a2e2b
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft lo: 0xb487e5c9, ft hi: 0x41d26580
+ldxc1 $f0, $a3($v0) :: ft lo: 0xb750e388, ft hi: 0x42026580
+ldxc1 $f0, $a3($v0) :: ft lo: 0xe2308c3a, ft hi: 0x3e45798e
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3746f65f, ft hi: 0x3fbf9add
+ldxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x4095a266
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0xbff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0x3ff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x262d2d2a, ft hi: 0x252a2e2b
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+SDC1
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x407c83fb
+sdc1 $f0, 0($t0) :: out: 0x40080000
+sdc1 $f0, 0($t0) :: out: 0xbff00000
+sdc1 $f0, 0($t0) :: out: 0x4095a266
+sdc1 $f0, 0($t0) :: out: 0xc01d2da3
+sdc1 $f0, 0($t0) :: out: 0x41cdcd65
+sdc1 $f0, 0($t0) :: out: 0xc0b69a78
+sdc1 $f0, 0($t0) :: out: 0x409b6000
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
+SDXC1
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0x407c83fb : out1: 0xb97f122f
+sdc1 $f0, #t2($t0) :: out: 0x40080000 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0xbff00000 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0x4095a266 : out1: 0x66666666
+sdc1 $f0, #t2($t0) :: out: 0xc01d2da3 : out1: 0x2101d847
+sdc1 $f0, #t2($t0) :: out: 0x41cdcd65 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0xc0b69a78 : out1: 0x51eb851f
+sdc1 $f0, #t2($t0) :: out: 0x409b6000 : out1: 0x0
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
+SWC1
+swc1 $f0, 0($t0) :: out: 0x0
+swc1 $f0, 0($t0) :: out: 0x40400000
+swc1 $f0, 0($t0) :: out: 0x44ad1333
+swc1 $f0, 0($t0) :: out: 0x4e6e6b28
+swc1 $f0, 0($t0) :: out: 0x44db0000
+swc1 $f0, 0($t0) :: out: 0x322bcc77
+swc1 $f0, 0($t0) :: out: 0xc732da7a
+swc1 $f0, 0($t0) :: out: 0x42080079
+swc1 $f0, 0($t0) :: out: 0x49d5e008
+MEM1:
+0.000000, 0.000000, 3.000000, 0.000000
+1384.599976, 0.000000, 1000000000.000000, 0.000000
+1752.000000, 0.000000, 0.000000, 0.000000
+-45786.476562, 0.000000, 34.000462, 0.000000
+SWXC1
+swxc1 $f0, 0($t0) :: out: 0x0
+swxc1 $f0, 0($t0) :: out: 0x40400000
+swxc1 $f0, 0($t0) :: out: 0x44ad1333
+swxc1 $f0, 0($t0) :: out: 0x4e6e6b28
+swxc1 $f0, 0($t0) :: out: 0x44db0000
+swxc1 $f0, 0($t0) :: out: 0x322bcc77
+swxc1 $f0, 0($t0) :: out: 0xc732da7a
+swxc1 $f0, 0($t0) :: out: 0x42080079
+swxc1 $f0, 0($t0) :: out: 0x49d5e008
+MEM1:
+0.000000, 0.000000, 3.000000, 0.000000
+1384.599976, 0.000000, 1000000000.000000, 0.000000
+1752.000000, 0.000000, 0.000000, 0.000000
+-45786.476562, 0.000000, 34.000462, 0.000000
+luxc1
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+luxc1 $f0, $a3($v0) :: ft lo: 0x89900000, ft hi: 0x22558
+luxc1 $f0, $a3($v0) :: ft lo: 0x698a2e2b, ft hi: 0x25254123
+luxc1 $f0, $a3($v0) :: ft lo: 0xf62d2d2a, ft hi: 0x21a2b3d6
+luxc1 $f0, $a3($v0) :: ft lo: 0xccffffff, ft hi: 0xffaabb22
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+luxc1 $f0, $a3($v0) :: ft lo: 0x89900000, ft hi: 0x22558
+luxc1 $f0, $a3($v0) :: ft lo: 0x698a2e2b, ft hi: 0x25254123
+luxc1 $f0, $a3($v0) :: ft lo: 0xf62d2d2a, ft hi: 0x21a2b3d6
+luxc1 $f0, $a3($v0) :: ft lo: 0xccffffff, ft hi: 0xffaabb22
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+luxc1 $f0, $a3($v0) :: ft lo: 0x89900000, ft hi: 0x22558
+luxc1 $f0, $a3($v0) :: ft lo: 0x698a2e2b, ft hi: 0x25254123
+luxc1 $f0, $a3($v0) :: ft lo: 0xf62d2d2a, ft hi: 0x21a2b3d6
+luxc1 $f0, $a3($v0) :: ft lo: 0xccffffff, ft hi: 0xffaabb22
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+SUXC1
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0x407c83fb : out1: 0xb97f122f
+suxc1 $f0, #t2($t0) :: out: 0x407c83fb : out1: 0xb97f122f
+suxc1 $f0, #t2($t0) :: out: 0x40080000 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0x40080000 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0xbff00000 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0xbff00000 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0x4095a266 : out1: 0x66666666
+suxc1 $f0, #t2($t0) :: out: 0x4095a266 : out1: 0x66666666
+suxc1 $f0, #t2($t0) :: out: 0xc01d2da3 : out1: 0x2101d847
+suxc1 $f0, #t2($t0) :: out: 0xc01d2da3 : out1: 0x2101d847
+suxc1 $f0, #t2($t0) :: out: 0x41cdcd65 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0x41cdcd65 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0xc0b69a78 : out1: 0x51eb851f
+suxc1 $f0, #t2($t0) :: out: 0xc0b69a78 : out1: 0x51eb851f
+suxc1 $f0, #t2($t0) :: out: 0x409b6000 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0x409b6000 : out1: 0x0
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
\ No newline at end of file
diff --git a/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-LE b/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-LE
new file mode 100644
index 0000000..d63c535
--- /dev/null
+++ b/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-LE
@@ -0,0 +1,239 @@
+LDC1
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+ldc1 $f0, 8($t1) :: ft 0xbff000000
+ldc1 $f0, 16($t1) :: ft 0x3ff000000
+ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
+ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
+ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
+ldc1 $f0, 64($t1) :: ft 0x3fbf9add3746f65f
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+ldc1 $f0, 8($t1) :: ft 0xbff000000
+ldc1 $f0, 16($t1) :: ft 0x3ff000000
+ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
+ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
+ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+ldc1 $f0, 8($t1) :: ft 0xbff000000
+ldc1 $f0, 16($t1) :: ft 0x3ff000000
+ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
+ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
+ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
+ldc1 $f0, 64($t1) :: ft 0x3fbf9add3746f65f
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+LWC1
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+lwc1 $f0, 4($t1) :: ft 0x66666666
+lwc1 $f0, 8($t1) :: ft 0xbff00000
+lwc1 $f0, 12($t1) :: ft 0x0
+lwc1 $f0, 16($t1) :: ft 0x3ff00000
+lwc1 $f0, 20($t1) :: ft 0x0
+lwc1 $f0, 24($t1) :: ft 0x252a2e2b
+lwc1 $f0, 28($t1) :: ft 0x262d2d2a
+lwc1 $f0, 32($t1) :: ft 0xffffffff
+lwc1 $f0, 36($t1) :: ft 0xffffffff
+lwc1 $f0, 40($t1) :: ft 0x41d26580
+lwc1 $f0, 44($t1) :: ft 0xb487e5c9
+lwc1 $f0, 48($t1) :: ft 0x42026580
+lwc1 $f0, 52($t1) :: ft 0xb750e388
+lwc1 $f0, 56($t1) :: ft 0x3e45798e
+lwc1 $f0, 60($t1) :: ft 0xe2308c3a
+lwc1 $f0, 64($t1) :: ft 0x3fbf9add
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+lwc1 $f0, 8($t1) :: ft 0xbff00000
+lwc1 $f0, 16($t1) :: ft 0x3ff00000
+lwc1 $f0, 24($t1) :: ft 0x252a2e2b
+lwc1 $f0, 32($t1) :: ft 0xffffffff
+lwc1 $f0, 40($t1) :: ft 0x41d26580
+lwc1 $f0, 48($t1) :: ft 0x42026580
+lwc1 $f0, 56($t1) :: ft 0x3e45798e
+lwc1 $f0, 64($t1) :: ft 0x3fbf9add
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+LWXC1
+lwxc1 $f0, $a3($v0) :: ft 0x4095a266
+lwxc1 $f0, $a3($v0) :: ft 0x66666666
+lwxc1 $f0, $a3($v0) :: ft 0xbff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x3ff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+lwxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0x41d26580
+lwxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+lwxc1 $f0, $a3($v0) :: ft 0x42026580
+lwxc1 $f0, $a3($v0) :: ft 0xb750e388
+lwxc1 $f0, $a3($v0) :: ft 0x3e45798e
+lwxc1 $f0, $a3($v0) :: ft 0xe2308c3a
+lwxc1 $f0, $a3($v0) :: ft 0x3fbf9add
+lwxc1 $f0, $a3($v0) :: ft 0x4095a266
+lwxc1 $f0, $a3($v0) :: ft 0x66666666
+lwxc1 $f0, $a3($v0) :: ft 0xbff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x3ff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+lwxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0x41d26580
+lwxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+lwxc1 $f0, $a3($v0) :: ft 0x42026580
+lwxc1 $f0, $a3($v0) :: ft 0xb750e388
+lwxc1 $f0, $a3($v0) :: ft 0x3e45798e
+LDXC1
+ldxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x66666666
+ldxc1 $f0, $a3($v0) :: ft lo: 0xbff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3ff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x252a2e2b, ft hi: 0x262d2d2a
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft lo: 0x41d26580, ft hi: 0xb487e5c9
+ldxc1 $f0, $a3($v0) :: ft lo: 0x42026580, ft hi: 0xb750e388
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3e45798e, ft hi: 0xe2308c3a
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3fbf9add, ft hi: 0x3746f65f
+ldxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x66666666
+ldxc1 $f0, $a3($v0) :: ft lo: 0xbff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3ff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x252a2e2b, ft hi: 0x262d2d2a
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft lo: 0x41d26580, ft hi: 0xb487e5c9
+ldxc1 $f0, $a3($v0) :: ft lo: 0x42026580, ft hi: 0xb750e388
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3e45798e, ft hi: 0xe2308c3a
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3fbf9add, ft hi: 0x3746f65f
+ldxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x66666666
+ldxc1 $f0, $a3($v0) :: ft lo: 0xbff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3ff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x252a2e2b, ft hi: 0x262d2d2a
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft lo: 0x41d26580, ft hi: 0xb487e5c9
+ldxc1 $f0, $a3($v0) :: ft lo: 0x42026580, ft hi: 0xb750e388
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3e45798e, ft hi: 0xe2308c3a
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3fbf9add, ft hi: 0x3746f65f
+ldxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x66666666
+ldxc1 $f0, $a3($v0) :: ft lo: 0xbff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3ff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x252a2e2b, ft hi: 0x262d2d2a
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+SDC1
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0xb97f122f
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x66666666
+sdc1 $f0, 0($t0) :: out: 0x2101d847
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x51eb851f
+sdc1 $f0, 0($t0) :: out: 0x0
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
+SDXC1
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0xb97f122f : out1: 0x407c83fb
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x40080000
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0xbff00000
+sdc1 $f0, #t2($t0) :: out: 0x66666666 : out1: 0x4095a266
+sdc1 $f0, #t2($t0) :: out: 0x2101d847 : out1: 0xc01d2da3
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x41cdcd65
+sdc1 $f0, #t2($t0) :: out: 0x51eb851f : out1: 0xc0b69a78
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x409b6000
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
+SWC1
+swc1 $f0, 0($t0) :: out: 0x0
+swc1 $f0, 0($t0) :: out: 0x40400000
+swc1 $f0, 0($t0) :: out: 0x44ad1333
+swc1 $f0, 0($t0) :: out: 0x4e6e6b28
+swc1 $f0, 0($t0) :: out: 0x44db0000
+swc1 $f0, 0($t0) :: out: 0x322bcc77
+swc1 $f0, 0($t0) :: out: 0xc732da7a
+swc1 $f0, 0($t0) :: out: 0x42080079
+swc1 $f0, 0($t0) :: out: 0x49d5e008
+MEM1:
+0.000000, 0.000000, 3.000000, 0.000000
+1384.599976, 0.000000, 1000000000.000000, 0.000000
+1752.000000, 0.000000, 0.000000, 0.000000
+-45786.476562, 0.000000, 34.000462, 0.000000
+SWXC1
+swxc1 $f0, 0($t0) :: out: 0x0
+swxc1 $f0, 0($t0) :: out: 0x40400000
+swxc1 $f0, 0($t0) :: out: 0x44ad1333
+swxc1 $f0, 0($t0) :: out: 0x4e6e6b28
+swxc1 $f0, 0($t0) :: out: 0x44db0000
+swxc1 $f0, 0($t0) :: out: 0x322bcc77
+swxc1 $f0, 0($t0) :: out: 0xc732da7a
+swxc1 $f0, 0($t0) :: out: 0x42080079
+swxc1 $f0, 0($t0) :: out: 0x49d5e008
+MEM1:
+0.000000, 0.000000, 3.000000, 0.000000
+1384.599976, 0.000000, 1000000000.000000, 0.000000
+1752.000000, 0.000000, 0.000000, 0.000000
+-45786.476562, 0.000000, 34.000462, 0.000000
+luxc1
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+luxc1 $f0, $a3($v0) :: ft lo: 0x89900000, ft hi: 0x22558
+luxc1 $f0, $a3($v0) :: ft lo: 0x698a2e2b, ft hi: 0x25254123
+luxc1 $f0, $a3($v0) :: ft lo: 0xf62d2d2a, ft hi: 0x21a2b3d6
+luxc1 $f0, $a3($v0) :: ft lo: 0xccffffff, ft hi: 0xffaabb22
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+luxc1 $f0, $a3($v0) :: ft lo: 0x89900000, ft hi: 0x22558
+luxc1 $f0, $a3($v0) :: ft lo: 0x698a2e2b, ft hi: 0x25254123
+luxc1 $f0, $a3($v0) :: ft lo: 0xf62d2d2a, ft hi: 0x21a2b3d6
+luxc1 $f0, $a3($v0) :: ft lo: 0xccffffff, ft hi: 0xffaabb22
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+luxc1 $f0, $a3($v0) :: ft lo: 0x89900000, ft hi: 0x22558
+luxc1 $f0, $a3($v0) :: ft lo: 0x698a2e2b, ft hi: 0x25254123
+luxc1 $f0, $a3($v0) :: ft lo: 0xf62d2d2a, ft hi: 0x21a2b3d6
+luxc1 $f0, $a3($v0) :: ft lo: 0xccffffff, ft hi: 0xffaabb22
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+SUXC1
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0xb97f122f : out1: 0x407c83fb
+suxc1 $f0, #t2($t0) :: out: 0xb97f122f : out1: 0x407c83fb
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x40080000
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x40080000
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0xbff00000
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0xbff00000
+suxc1 $f0, #t2($t0) :: out: 0x66666666 : out1: 0x4095a266
+suxc1 $f0, #t2($t0) :: out: 0x66666666 : out1: 0x4095a266
+suxc1 $f0, #t2($t0) :: out: 0x2101d847 : out1: 0xc01d2da3
+suxc1 $f0, #t2($t0) :: out: 0x2101d847 : out1: 0xc01d2da3
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x41cdcd65
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x41cdcd65
+suxc1 $f0, #t2($t0) :: out: 0x51eb851f : out1: 0xc0b69a78
+suxc1 $f0, #t2($t0) :: out: 0x51eb851f : out1: 0xc0b69a78
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x409b6000
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x409b6000
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
diff --git a/none/tests/mips32/vfp.vgtest b/none/tests/mips32/vfp.vgtest
index fd3e759..043eeb4 100644
--- a/none/tests/mips32/vfp.vgtest
+++ b/none/tests/mips32/vfp.vgtest
@@ -1,2 +1,3 @@
prog: vfp
+prereq: ../../../tests/mips_features fpu
vgopts: -q
diff --git a/none/tests/mips64/Makefile.am b/none/tests/mips64/Makefile.am
index 2876030..3c603a0 100644
--- a/none/tests/mips64/Makefile.am
+++ b/none/tests/mips64/Makefile.am
@@ -10,6 +10,7 @@
branch_and_jump_instructions.stdout.exp \
branch_and_jump_instructions.stderr.exp branch_and_jump_instructions.vgtest \
branches.stdout.exp branches.stderr.exp branches.vgtest \
+ change_fp_mode.stderr.exp change_fp_mode.stdout.exp change_fp_mode.vgtest \
cvm_bbit.stdout.exp cvm_bbit.stdout.exp-non-octeon \
cvm_bbit.stderr.exp cvm_bbit.vgtest \
cvm_ins.stdout.exp cvm_ins.stdout.exp-non-octeon \
@@ -65,6 +66,7 @@
arithmetic_instruction \
branch_and_jump_instructions \
branches \
+ change_fp_mode \
cvm_bbit \
cvm_ins \
cvm_lx_ins \
diff --git a/none/tests/mips64/Makefile.in b/none/tests/mips64/Makefile.in
new file mode 100644
index 0000000..66e6b0f
--- /dev/null
+++ b/none/tests/mips64/Makefile.in
@@ -0,0 +1,1408 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+am__is_gnu_make = { \
+ if test -z '$(MAKELEVEL)'; then \
+ false; \
+ elif test -n '$(MAKE_HOST)'; then \
+ true; \
+ elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
+ true; \
+ else \
+ false; \
+ fi; \
+}
+am__make_running_with_option = \
+ case $${target_option-} in \
+ ?) ;; \
+ *) echo "am__make_running_with_option: internal error: invalid" \
+ "target option '$${target_option-}' specified" >&2; \
+ exit 1;; \
+ esac; \
+ has_opt=no; \
+ sane_makeflags=$$MAKEFLAGS; \
+ if $(am__is_gnu_make); then \
+ sane_makeflags=$$MFLAGS; \
+ else \
+ case $$MAKEFLAGS in \
+ *\\[\ \ ]*) \
+ bs=\\; \
+ sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
+ | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \
+ esac; \
+ fi; \
+ skip_next=no; \
+ strip_trailopt () \
+ { \
+ flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
+ }; \
+ for flg in $$sane_makeflags; do \
+ test $$skip_next = yes && { skip_next=no; continue; }; \
+ case $$flg in \
+ *=*|--*) continue;; \
+ -*I) strip_trailopt 'I'; skip_next=yes;; \
+ -*I?*) strip_trailopt 'I';; \
+ -*O) strip_trailopt 'O'; skip_next=yes;; \
+ -*O?*) strip_trailopt 'O';; \
+ -*l) strip_trailopt 'l'; skip_next=yes;; \
+ -*l?*) strip_trailopt 'l';; \
+ -[dEDm]) skip_next=yes;; \
+ -[JT]) skip_next=yes;; \
+ esac; \
+ case $$flg in \
+ *$$target_option*) has_opt=yes; break;; \
+ esac; \
+ done; \
+ test $$has_opt = yes
+am__make_dryrun = (target_option=n; $(am__make_running_with_option))
+am__make_keepgoing = (target_option=k; $(am__make_running_with_option))
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+@COMPILER_IS_CLANG_TRUE@am__append_1 = -Wno-cast-align -Wno-self-assign \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-compare
+
+@SOLARIS_XPG_SYMBOLS_PRESENT_TRUE@am__append_2 = -Wl,-M,$(top_srcdir)/solaris/vgpreload-solaris.mapfile
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_3 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+
+# Make sure that all test programs have threaded errno.
+# Disable largefile support as there are test cases explictly enabling it.
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
+@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
+@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-constant-out-of-range-compare \
+@COMPILER_IS_CLANG_TRUE@ -Wno-self-assign -Wno-string-plus-int \
+@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
+@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
+@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
+check_PROGRAMS = allexec$(EXEEXT) arithmetic_instruction$(EXEEXT) \
+ branch_and_jump_instructions$(EXEEXT) branches$(EXEEXT) \
+ change_fp_mode$(EXEEXT) cvm_bbit$(EXEEXT) cvm_ins$(EXEEXT) \
+ cvm_lx_ins$(EXEEXT) cvm_atomic$(EXEEXT) \
+ cvm_atomic_thread$(EXEEXT) extract_insert_bit_field$(EXEEXT) \
+ fpu_arithmetic$(EXEEXT) fpu_branches$(EXEEXT) \
+ fpu_control_word$(EXEEXT) fpu_load_store$(EXEEXT) \
+ load_indexed_instructions$(EXEEXT) load_store$(EXEEXT) \
+ load_store_multiple$(EXEEXT) load_store_unaligned$(EXEEXT) \
+ logical_instructions$(EXEEXT) move_instructions$(EXEEXT) \
+ rotate_swap$(EXEEXT) round$(EXEEXT) \
+ shift_instructions$(EXEEXT) test_block_size$(EXEEXT) \
+ test_fcsr$(EXEEXT) test_math$(EXEEXT) unaligned_load$(EXEEXT) \
+ unaligned_load_store$(EXEEXT)
+subdir = none/tests/mips64
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.ac
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+DIST_COMMON = $(srcdir)/Makefile.am $(dist_noinst_SCRIPTS) \
+ $(am__DIST_COMMON)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+allexec_SOURCES = allexec.c
+allexec_OBJECTS = allexec-allexec.$(OBJEXT)
+allexec_LDADD = $(LDADD)
+allexec_LINK = $(CCLD) $(allexec_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+arithmetic_instruction_SOURCES = arithmetic_instruction.c
+arithmetic_instruction_OBJECTS = arithmetic_instruction.$(OBJEXT)
+arithmetic_instruction_LDADD = $(LDADD)
+branch_and_jump_instructions_SOURCES = branch_and_jump_instructions.c
+branch_and_jump_instructions_OBJECTS = \
+ branch_and_jump_instructions.$(OBJEXT)
+branch_and_jump_instructions_LDADD = $(LDADD)
+branches_SOURCES = branches.c
+branches_OBJECTS = branches.$(OBJEXT)
+branches_LDADD = $(LDADD)
+change_fp_mode_SOURCES = change_fp_mode.c
+change_fp_mode_OBJECTS = change_fp_mode.$(OBJEXT)
+change_fp_mode_LDADD = $(LDADD)
+cvm_atomic_SOURCES = cvm_atomic.c
+cvm_atomic_OBJECTS = cvm_atomic-cvm_atomic.$(OBJEXT)
+cvm_atomic_LDADD = $(LDADD)
+cvm_atomic_LINK = $(CCLD) $(cvm_atomic_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+cvm_atomic_thread_SOURCES = cvm_atomic_thread.c
+cvm_atomic_thread_OBJECTS = \
+ cvm_atomic_thread-cvm_atomic_thread.$(OBJEXT)
+cvm_atomic_thread_LDADD = $(LDADD)
+cvm_atomic_thread_LINK = $(CCLD) $(cvm_atomic_thread_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+cvm_bbit_SOURCES = cvm_bbit.c
+cvm_bbit_OBJECTS = cvm_bbit-cvm_bbit.$(OBJEXT)
+cvm_bbit_LDADD = $(LDADD)
+cvm_bbit_LINK = $(CCLD) $(cvm_bbit_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+cvm_ins_SOURCES = cvm_ins.c
+cvm_ins_OBJECTS = cvm_ins-cvm_ins.$(OBJEXT)
+cvm_ins_LDADD = $(LDADD)
+cvm_ins_LINK = $(CCLD) $(cvm_ins_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+cvm_lx_ins_SOURCES = cvm_lx_ins.c
+cvm_lx_ins_OBJECTS = cvm_lx_ins-cvm_lx_ins.$(OBJEXT)
+cvm_lx_ins_LDADD = $(LDADD)
+cvm_lx_ins_LINK = $(CCLD) $(cvm_lx_ins_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+extract_insert_bit_field_SOURCES = extract_insert_bit_field.c
+extract_insert_bit_field_OBJECTS = extract_insert_bit_field.$(OBJEXT)
+extract_insert_bit_field_LDADD = $(LDADD)
+fpu_arithmetic_SOURCES = fpu_arithmetic.c
+fpu_arithmetic_OBJECTS = fpu_arithmetic-fpu_arithmetic.$(OBJEXT)
+fpu_arithmetic_LDADD = $(LDADD)
+fpu_arithmetic_LINK = $(CCLD) $(fpu_arithmetic_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+fpu_branches_SOURCES = fpu_branches.c
+fpu_branches_OBJECTS = fpu_branches.$(OBJEXT)
+fpu_branches_LDADD = $(LDADD)
+fpu_control_word_SOURCES = fpu_control_word.c
+fpu_control_word_OBJECTS = fpu_control_word.$(OBJEXT)
+fpu_control_word_LDADD = $(LDADD)
+fpu_load_store_SOURCES = fpu_load_store.c
+fpu_load_store_OBJECTS = fpu_load_store.$(OBJEXT)
+fpu_load_store_LDADD = $(LDADD)
+load_indexed_instructions_SOURCES = load_indexed_instructions.c
+load_indexed_instructions_OBJECTS = \
+ load_indexed_instructions-load_indexed_instructions.$(OBJEXT)
+load_indexed_instructions_LDADD = $(LDADD)
+load_indexed_instructions_LINK = $(CCLD) \
+ $(load_indexed_instructions_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+load_store_SOURCES = load_store.c
+load_store_OBJECTS = load_store.$(OBJEXT)
+load_store_LDADD = $(LDADD)
+load_store_multiple_SOURCES = load_store_multiple.c
+load_store_multiple_OBJECTS = load_store_multiple.$(OBJEXT)
+load_store_multiple_LDADD = $(LDADD)
+load_store_unaligned_SOURCES = load_store_unaligned.c
+load_store_unaligned_OBJECTS = load_store_unaligned.$(OBJEXT)
+load_store_unaligned_LDADD = $(LDADD)
+logical_instructions_SOURCES = logical_instructions.c
+logical_instructions_OBJECTS = logical_instructions.$(OBJEXT)
+logical_instructions_LDADD = $(LDADD)
+move_instructions_SOURCES = move_instructions.c
+move_instructions_OBJECTS = move_instructions.$(OBJEXT)
+move_instructions_LDADD = $(LDADD)
+rotate_swap_SOURCES = rotate_swap.c
+rotate_swap_OBJECTS = rotate_swap.$(OBJEXT)
+rotate_swap_LDADD = $(LDADD)
+round_SOURCES = round.c
+round_OBJECTS = round.$(OBJEXT)
+round_LDADD = $(LDADD)
+shift_instructions_SOURCES = shift_instructions.c
+shift_instructions_OBJECTS = shift_instructions.$(OBJEXT)
+shift_instructions_LDADD = $(LDADD)
+test_block_size_SOURCES = test_block_size.c
+test_block_size_OBJECTS = test_block_size.$(OBJEXT)
+test_block_size_LDADD = $(LDADD)
+test_fcsr_SOURCES = test_fcsr.c
+test_fcsr_OBJECTS = test_fcsr.$(OBJEXT)
+test_fcsr_LDADD = $(LDADD)
+am_test_math_OBJECTS = test_math.$(OBJEXT)
+test_math_OBJECTS = $(am_test_math_OBJECTS)
+test_math_LDADD = $(LDADD)
+unaligned_load_SOURCES = unaligned_load.c
+unaligned_load_OBJECTS = unaligned_load.$(OBJEXT)
+unaligned_load_LDADD = $(LDADD)
+unaligned_load_store_SOURCES = unaligned_load_store.c
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+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ @FLAG_M64@ $(am__empty)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) @FLAG_M64@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ arithmetic_instruction.stdout.exp-mips64 \
+ arithmetic_instruction.stdout.exp-mips64r2 arithmetic_instruction.stderr.exp \
+ arithmetic_instruction.vgtest \
+ branch_and_jump_instructions.stdout.exp \
+ branch_and_jump_instructions.stderr.exp branch_and_jump_instructions.vgtest \
+ branches.stdout.exp branches.stderr.exp branches.vgtest \
+ change_fp_mode.stderr.exp change_fp_mode.stdout.exp change_fp_mode.vgtest \
+ cvm_bbit.stdout.exp cvm_bbit.stdout.exp-non-octeon \
+ cvm_bbit.stderr.exp cvm_bbit.vgtest \
+ cvm_ins.stdout.exp cvm_ins.stdout.exp-non-octeon \
+ cvm_ins.stderr.exp cvm_ins.vgtest \
+ cvm_lx_ins.stdout.exp-LE cvm_lx_ins.stdout.exp-BE \
+ cvm_lx_ins.stdout.exp-non-octeon \
+ cvm_lx_ins.stderr.exp cvm_lx_ins.vgtest \
+ cvm_atomic.stdout.exp-LE cvm_atomic.stdout.exp-non-octeon \
+ cvm_atomic.stderr.exp cvm_atomic.vgtest \
+ cvm_atomic_thread.stdout.exp-LE cvm_atomic_thread.stdout.exp-non-octeon \
+ cvm_atomic_thread.stderr.exp cvm_atomic_thread.vgtest \
+ extract_insert_bit_field.stdout.exp-mips64 \
+ extract_insert_bit_field.stdout.exp-mips64r2 \
+ extract_insert_bit_field.stderr.exp extract_insert_bit_field.vgtest \
+ fpu_arithmetic.stdout.exp fpu_arithmetic.stderr.exp fpu_arithmetic.vgtest \
+ fpu_branches.stdout.exp fpu_branches.stderr.exp fpu_branches.vgtest \
+ fpu_control_word.stdout.exp fpu_control_word.stderr.exp \
+ fpu_control_word.vgtest \
+ fpu_load_store.stdout.exp-BE fpu_load_store.stdout.exp-LE \
+ fpu_load_store.stderr.exp fpu_load_store.vgtest \
+ load_indexed_instructions.stdout.exp-BE \
+ load_indexed_instructions.stdout.exp-LE \
+ load_indexed_instructions.stdout.exp-non-octeon \
+ load_indexed_instructions.stderr.exp load_indexed_instructions.vgtest \
+ load_store.stdout.exp-BE load_store.stdout.exp-LE load_store.stderr.exp \
+ load_store.vgtest \
+ load_store_multiple.stdout.exp-BE load_store_multiple.stdout.exp-LE \
+ load_store_multiple.stderr.exp load_store_multiple.vgtest \
+ load_store_unaligned.stdout.exp load_store_unaligned.stderr.exp \
+ load_store_unaligned.vgtest \
+ logical_instructions.stdout.exp logical_instructions.stderr.exp \
+ logical_instructions.vgtest \
+ move_instructions.stdout.exp-BE move_instructions.stdout.exp-LE \
+ move_instructions.stderr.exp move_instructions.vgtest \
+ rotate_swap.stdout.exp-mips64 rotate_swap.stdout.exp-mips64r2 \
+ rotate_swap.stderr.exp rotate_swap.vgtest \
+ round.stdout.exp round.stderr.exp round.vgtest \
+ shift_instructions.stdout.exp-mips64 shift_instructions.stdout.exp-mips64r2 \
+ shift_instructions.stderr.exp shift_instructions.vgtest \
+ test_block_size.stdout.exp test_block_size.stderr.exp \
+ test_block_size.vgtest \
+ test_fcsr.stdout.exp test_fcsr.stderr.exp \
+ test_fcsr.vgtest \
+ test_math.stdout.exp test_math.stderr.exp test_math.vgtest \
+ unaligned_load.stdout.exp-BE unaligned_load.stdout.exp-LE \
+ unaligned_load.stderr.exp unaligned_load.vgtest \
+ unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
+ unaligned_load_store.stderr.exp unaligned_load_store.vgtest \
+ const.h macro_fpu.h macro_int.h macro_load_store.h rounding_mode.h
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+cvm_bbit_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON@
+cvm_ins_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON@
+cvm_lx_ins_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON2@
+cvm_atomic_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON2@
+cvm_atomic_thread_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON2@
+load_indexed_instructions_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON2@
+fpu_arithmetic_CFLAGS = $(AM_CFLAGS) -lm
+
+# C++ tests
+test_math_SOURCES = test_math.cpp
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .cpp .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/mips64/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/mips64/Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+$(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__empty):
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES) $(EXTRA_allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(AM_V_CCLD)$(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+
+arithmetic_instruction$(EXEEXT): $(arithmetic_instruction_OBJECTS) $(arithmetic_instruction_DEPENDENCIES) $(EXTRA_arithmetic_instruction_DEPENDENCIES)
+ @rm -f arithmetic_instruction$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(arithmetic_instruction_OBJECTS) $(arithmetic_instruction_LDADD) $(LIBS)
+
+branch_and_jump_instructions$(EXEEXT): $(branch_and_jump_instructions_OBJECTS) $(branch_and_jump_instructions_DEPENDENCIES) $(EXTRA_branch_and_jump_instructions_DEPENDENCIES)
+ @rm -f branch_and_jump_instructions$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(branch_and_jump_instructions_OBJECTS) $(branch_and_jump_instructions_LDADD) $(LIBS)
+
+branches$(EXEEXT): $(branches_OBJECTS) $(branches_DEPENDENCIES) $(EXTRA_branches_DEPENDENCIES)
+ @rm -f branches$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(branches_OBJECTS) $(branches_LDADD) $(LIBS)
+
+change_fp_mode$(EXEEXT): $(change_fp_mode_OBJECTS) $(change_fp_mode_DEPENDENCIES) $(EXTRA_change_fp_mode_DEPENDENCIES)
+ @rm -f change_fp_mode$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(change_fp_mode_OBJECTS) $(change_fp_mode_LDADD) $(LIBS)
+
+cvm_atomic$(EXEEXT): $(cvm_atomic_OBJECTS) $(cvm_atomic_DEPENDENCIES) $(EXTRA_cvm_atomic_DEPENDENCIES)
+ @rm -f cvm_atomic$(EXEEXT)
+ $(AM_V_CCLD)$(cvm_atomic_LINK) $(cvm_atomic_OBJECTS) $(cvm_atomic_LDADD) $(LIBS)
+
+cvm_atomic_thread$(EXEEXT): $(cvm_atomic_thread_OBJECTS) $(cvm_atomic_thread_DEPENDENCIES) $(EXTRA_cvm_atomic_thread_DEPENDENCIES)
+ @rm -f cvm_atomic_thread$(EXEEXT)
+ $(AM_V_CCLD)$(cvm_atomic_thread_LINK) $(cvm_atomic_thread_OBJECTS) $(cvm_atomic_thread_LDADD) $(LIBS)
+
+cvm_bbit$(EXEEXT): $(cvm_bbit_OBJECTS) $(cvm_bbit_DEPENDENCIES) $(EXTRA_cvm_bbit_DEPENDENCIES)
+ @rm -f cvm_bbit$(EXEEXT)
+ $(AM_V_CCLD)$(cvm_bbit_LINK) $(cvm_bbit_OBJECTS) $(cvm_bbit_LDADD) $(LIBS)
+
+cvm_ins$(EXEEXT): $(cvm_ins_OBJECTS) $(cvm_ins_DEPENDENCIES) $(EXTRA_cvm_ins_DEPENDENCIES)
+ @rm -f cvm_ins$(EXEEXT)
+ $(AM_V_CCLD)$(cvm_ins_LINK) $(cvm_ins_OBJECTS) $(cvm_ins_LDADD) $(LIBS)
+
+cvm_lx_ins$(EXEEXT): $(cvm_lx_ins_OBJECTS) $(cvm_lx_ins_DEPENDENCIES) $(EXTRA_cvm_lx_ins_DEPENDENCIES)
+ @rm -f cvm_lx_ins$(EXEEXT)
+ $(AM_V_CCLD)$(cvm_lx_ins_LINK) $(cvm_lx_ins_OBJECTS) $(cvm_lx_ins_LDADD) $(LIBS)
+
+extract_insert_bit_field$(EXEEXT): $(extract_insert_bit_field_OBJECTS) $(extract_insert_bit_field_DEPENDENCIES) $(EXTRA_extract_insert_bit_field_DEPENDENCIES)
+ @rm -f extract_insert_bit_field$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(extract_insert_bit_field_OBJECTS) $(extract_insert_bit_field_LDADD) $(LIBS)
+
+fpu_arithmetic$(EXEEXT): $(fpu_arithmetic_OBJECTS) $(fpu_arithmetic_DEPENDENCIES) $(EXTRA_fpu_arithmetic_DEPENDENCIES)
+ @rm -f fpu_arithmetic$(EXEEXT)
+ $(AM_V_CCLD)$(fpu_arithmetic_LINK) $(fpu_arithmetic_OBJECTS) $(fpu_arithmetic_LDADD) $(LIBS)
+
+fpu_branches$(EXEEXT): $(fpu_branches_OBJECTS) $(fpu_branches_DEPENDENCIES) $(EXTRA_fpu_branches_DEPENDENCIES)
+ @rm -f fpu_branches$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(fpu_branches_OBJECTS) $(fpu_branches_LDADD) $(LIBS)
+
+fpu_control_word$(EXEEXT): $(fpu_control_word_OBJECTS) $(fpu_control_word_DEPENDENCIES) $(EXTRA_fpu_control_word_DEPENDENCIES)
+ @rm -f fpu_control_word$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(fpu_control_word_OBJECTS) $(fpu_control_word_LDADD) $(LIBS)
+
+fpu_load_store$(EXEEXT): $(fpu_load_store_OBJECTS) $(fpu_load_store_DEPENDENCIES) $(EXTRA_fpu_load_store_DEPENDENCIES)
+ @rm -f fpu_load_store$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(fpu_load_store_OBJECTS) $(fpu_load_store_LDADD) $(LIBS)
+
+load_indexed_instructions$(EXEEXT): $(load_indexed_instructions_OBJECTS) $(load_indexed_instructions_DEPENDENCIES) $(EXTRA_load_indexed_instructions_DEPENDENCIES)
+ @rm -f load_indexed_instructions$(EXEEXT)
+ $(AM_V_CCLD)$(load_indexed_instructions_LINK) $(load_indexed_instructions_OBJECTS) $(load_indexed_instructions_LDADD) $(LIBS)
+
+load_store$(EXEEXT): $(load_store_OBJECTS) $(load_store_DEPENDENCIES) $(EXTRA_load_store_DEPENDENCIES)
+ @rm -f load_store$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(load_store_OBJECTS) $(load_store_LDADD) $(LIBS)
+
+load_store_multiple$(EXEEXT): $(load_store_multiple_OBJECTS) $(load_store_multiple_DEPENDENCIES) $(EXTRA_load_store_multiple_DEPENDENCIES)
+ @rm -f load_store_multiple$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(load_store_multiple_OBJECTS) $(load_store_multiple_LDADD) $(LIBS)
+
+load_store_unaligned$(EXEEXT): $(load_store_unaligned_OBJECTS) $(load_store_unaligned_DEPENDENCIES) $(EXTRA_load_store_unaligned_DEPENDENCIES)
+ @rm -f load_store_unaligned$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(load_store_unaligned_OBJECTS) $(load_store_unaligned_LDADD) $(LIBS)
+
+logical_instructions$(EXEEXT): $(logical_instructions_OBJECTS) $(logical_instructions_DEPENDENCIES) $(EXTRA_logical_instructions_DEPENDENCIES)
+ @rm -f logical_instructions$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(logical_instructions_OBJECTS) $(logical_instructions_LDADD) $(LIBS)
+
+move_instructions$(EXEEXT): $(move_instructions_OBJECTS) $(move_instructions_DEPENDENCIES) $(EXTRA_move_instructions_DEPENDENCIES)
+ @rm -f move_instructions$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(move_instructions_OBJECTS) $(move_instructions_LDADD) $(LIBS)
+
+rotate_swap$(EXEEXT): $(rotate_swap_OBJECTS) $(rotate_swap_DEPENDENCIES) $(EXTRA_rotate_swap_DEPENDENCIES)
+ @rm -f rotate_swap$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(rotate_swap_OBJECTS) $(rotate_swap_LDADD) $(LIBS)
+
+round$(EXEEXT): $(round_OBJECTS) $(round_DEPENDENCIES) $(EXTRA_round_DEPENDENCIES)
+ @rm -f round$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(round_OBJECTS) $(round_LDADD) $(LIBS)
+
+shift_instructions$(EXEEXT): $(shift_instructions_OBJECTS) $(shift_instructions_DEPENDENCIES) $(EXTRA_shift_instructions_DEPENDENCIES)
+ @rm -f shift_instructions$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(shift_instructions_OBJECTS) $(shift_instructions_LDADD) $(LIBS)
+
+test_block_size$(EXEEXT): $(test_block_size_OBJECTS) $(test_block_size_DEPENDENCIES) $(EXTRA_test_block_size_DEPENDENCIES)
+ @rm -f test_block_size$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(test_block_size_OBJECTS) $(test_block_size_LDADD) $(LIBS)
+
+test_fcsr$(EXEEXT): $(test_fcsr_OBJECTS) $(test_fcsr_DEPENDENCIES) $(EXTRA_test_fcsr_DEPENDENCIES)
+ @rm -f test_fcsr$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(test_fcsr_OBJECTS) $(test_fcsr_LDADD) $(LIBS)
+
+test_math$(EXEEXT): $(test_math_OBJECTS) $(test_math_DEPENDENCIES) $(EXTRA_test_math_DEPENDENCIES)
+ @rm -f test_math$(EXEEXT)
+ $(AM_V_CXXLD)$(CXXLINK) $(test_math_OBJECTS) $(test_math_LDADD) $(LIBS)
+
+unaligned_load$(EXEEXT): $(unaligned_load_OBJECTS) $(unaligned_load_DEPENDENCIES) $(EXTRA_unaligned_load_DEPENDENCIES)
+ @rm -f unaligned_load$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(unaligned_load_OBJECTS) $(unaligned_load_LDADD) $(LIBS)
+
+unaligned_load_store$(EXEEXT): $(unaligned_load_store_OBJECTS) $(unaligned_load_store_DEPENDENCIES) $(EXTRA_unaligned_load_store_DEPENDENCIES)
+ @rm -f unaligned_load_store$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(unaligned_load_store_OBJECTS) $(unaligned_load_store_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/allexec-allexec.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arithmetic_instruction.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/branch_and_jump_instructions.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/branches.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/change_fp_mode.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cvm_atomic-cvm_atomic.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cvm_atomic_thread-cvm_atomic_thread.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cvm_bbit-cvm_bbit.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cvm_ins-cvm_ins.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cvm_lx_ins-cvm_lx_ins.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/extract_insert_bit_field.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fpu_arithmetic-fpu_arithmetic.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fpu_branches.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fpu_control_word.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fpu_load_store.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/load_indexed_instructions-load_indexed_instructions.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/load_store.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/load_store_multiple.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/load_store_unaligned.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/logical_instructions.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/move_instructions.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rotate_swap.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/round.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/shift_instructions.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_block_size.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_fcsr.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_math.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/unaligned_load.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/unaligned_load_store.Po@am__quote@
+
+.c.o:
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+@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $$depbase.Tpo -c -o $@ $< &&\
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+ test -f "$(distdir)/$$file" \
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+ || exit 1; \
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+
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+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
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+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
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+ dsymutil $$f; \
+ fi; \
+ done
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+# It needs to be depended on by an 'install-exec-local' rule.
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+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
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+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
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+# It needs to be depended on by an 'uninstall-local' rule.
+uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
+uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/none/tests/mips64/allexec.c b/none/tests/mips64/allexec.c
deleted file mode 120000
index 6d6a9cf..0000000
--- a/none/tests/mips64/allexec.c
+++ /dev/null
@@ -1 +0,0 @@
-../allexec.c
\ No newline at end of file
diff --git a/none/tests/allexec.c b/none/tests/mips64/allexec.c
similarity index 100%
copy from none/tests/allexec.c
copy to none/tests/mips64/allexec.c
diff --git a/none/tests/mips64/change_fp_mode.c b/none/tests/mips64/change_fp_mode.c
new file mode 100644
index 0000000..a1f7c04
--- /dev/null
+++ b/none/tests/mips64/change_fp_mode.c
@@ -0,0 +1,266 @@
+#if defined(__mips_hard_float)
+
+#include <elf.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/prctl.h>
+
+#if !defined(PR_SET_FP_MODE)
+# define PR_SET_FP_MODE 45
+#endif
+
+#if !defined(PR_GET_FP_MODE)
+# define PR_GET_FP_MODE 46
+#endif
+
+#define TEST_LD(instruction, source) \
+{ \
+ unsigned int result1, result2; \
+ __asm__ volatile( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ "li $t0, 0x5a5a\n\t" \
+ "mtc1 $t0, $f0\n\t" \
+ "mtc1 $t0, $f1\n\t" \
+ "move $t0, %2\n\t" \
+ instruction"\n\t" \
+ "swc1 $f0, %0\n\t" \
+ "swc1 $f1, %1\n\t" \
+ ".set pop\n\t" \
+ : "=m"(result1), "=m"(result2) \
+ : "r" (&source) \
+ : "t0", "$f0", "$f1"); \
+ printf(instruction" :: lo32(f1): %x, lo32(f0): %x\n", \
+ result2, result1); \
+}
+
+#define _TEST_ST(instruction) \
+ __asm__ volatile( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ "li $t0, 0x5a5a\n\t" \
+ "dmtc1 $t0, $f1\n\t" \
+ "move $t0, %0\n\t" \
+ "ldc1 $f0, 0($t0)\n\t" \
+ "move $t0, %1\n\t" \
+ instruction"\n\t" \
+ ".set pop\n\t" \
+ : \
+ : "r" (&source64), "r" (&result) \
+ : "t0", "$f0", "$f1", "memory")
+
+#define TEST_ST64(instruction) \
+{ \
+ unsigned long result; \
+ _TEST_ST(instruction); \
+ printf(instruction" :: mem: %lx\n", result); \
+}
+
+#define TEST_ST32(instruction) \
+{ \
+ unsigned int result; \
+ _TEST_ST(instruction); \
+ printf(instruction" :: mem: %x\n", result); \
+}
+
+#define TEST_MT(instruction) \
+{ \
+ unsigned int result1, result2; \
+ __asm__ volatile( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ "li $t0, 0x5a5a\n\t" \
+ "mtc1 $t0, $f0\n\t" \
+ "mtc1 $t0, $f1\n\t" \
+ "ld $t0, %2\n\t" \
+ instruction"\n\t" \
+ "swc1 $f0, %0\n\t" \
+ "swc1 $f1, %1\n\t" \
+ ".set pop\n\t" \
+ : "=m"(result1), "=m"(result2) \
+ : "m" (source64) \
+ : "t0", "$f0", "$f1"); \
+ printf(instruction" :: lo32(f1): %x, lo32(f0): %x\n", \
+ result2, result1); \
+}
+
+#define TEST_MF(instruction) \
+{ \
+ unsigned long result; \
+ __asm__ volatile( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ "li $t0, 0x5a5a\n\t" \
+ "dmtc1 $t0, $f1\n\t" \
+ "ldc1 $f0, %1\n\t" \
+ "move $t0, $0\n\t" \
+ instruction"\n\t" \
+ "sd $t0, %0\n\t" \
+ ".set pop\n\t" \
+ : "=m" (result) \
+ : "m" (source64) \
+ : "t0", "$f0", "$f1"); \
+ printf(instruction" :: t0: %lx\n", result); \
+}
+
+#define TEST_MOVE(instruction) \
+{ \
+ unsigned int result1, result2; \
+ __asm__ volatile( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ "li $t0, 0x5a5a\n\t" \
+ "mtc1 $t0, $f0\n\t" \
+ "li $t0, 0x6b6b\n\t" \
+ "mtc1 $t0, $f1\n\t" \
+ "li $t0, 0x7c7c\n\t" \
+ "dmtc1 $t0, $f2\n\t" \
+ "ldc1 $f2, %2\n\t" \
+ instruction"\n\t" \
+ "swc1 $f0, %0\n\t" \
+ "swc1 $f1, %1\n\t" \
+ ".set pop\n\t" \
+ : "=m"(result1), "=m"(result2) \
+ : "m" (source64) \
+ : "t0", "$f0", "$f1", "$f2"); \
+ printf(instruction" :: lo32(f1): %x, lo32(f0): %x\n", \
+ result2, result1); \
+}
+
+unsigned long source64 = 0x1234567890abcdefull;
+unsigned int source32 = 0x12345678u;
+
+/* Determine FP mode based on sdc1 behavior
+ returns 1 if FR = 1 mode is detected (assumes FRE = 0) */
+static int get_fp_mode(void) {
+ unsigned long result = 0;
+ __asm__ volatile(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ "lui $t0, 0x3ff0\n\t"
+ "ldc1 $f0, %0\n\t"
+ "mtc1 $t0, $f1\n\t"
+ "sdc1 $f0, %0\n\t"
+ ".set pop\n\t"
+ : "+m"(result)
+ :
+ : "t0", "$f0", "$f1", "memory");
+
+ return (result != 0x3ff0000000000000ull);
+}
+
+static void fatal_error(const char* msg) {
+ fprintf(stderr, "Error: %s\n", msg);
+ exit(1);
+}
+
+static void test(int* fr_prctl, int* fr_detected) {
+
+ *fr_prctl = prctl(PR_GET_FP_MODE);
+ *fr_detected = get_fp_mode();
+
+ if (*fr_prctl < 0) {
+ fatal_error("prctl(PR_GET_FP_MODE) fails.");
+ }
+
+ printf("fr_prctl: %d, fr_detected: %d\n", *fr_prctl, *fr_detected);
+
+ if (*fr_prctl != *fr_detected) {
+ fatal_error("fr_prctl != fr_detected");
+ }
+
+ TEST_LD("lwc1 $f0, 0($t0)", source32);
+ TEST_LD("lwc1 $f1, 0($t0)", source32);
+
+ TEST_LD("lwxc1 $f0, $0($t0)", source32);
+ TEST_LD("lwxc1 $f1, $0($t0)", source32);
+
+ TEST_LD("ldc1 $f0, 0($t0)", source64);
+ TEST_LD("ldc1 $f1, 0($t0)", source64);
+
+ TEST_LD("ldxc1 $f0, $0($t0)", source64);
+ TEST_LD("ldxc1 $f1, $0($t0)", source64);
+
+ TEST_ST32("swc1 $f0, 0($t0)");
+ TEST_ST32("swc1 $f1, 0($t0)");
+
+ TEST_ST32("swxc1 $f0, $0($t0)");
+ TEST_ST32("swxc1 $f1, $0($t0)");
+
+ TEST_ST64("sdc1 $f0, 0($t0)");
+ TEST_ST64("sdc1 $f1, 0($t0)");
+
+ TEST_ST64("sdxc1 $f0, $0($t0)");
+ TEST_ST64("sdxc1 $f1, $0($t0)");
+
+ TEST_MT("mtc1 $t0, $f0");
+ TEST_MT("mtc1 $t0, $f1");
+
+ TEST_MT("dmtc1 $t0, $f0");
+ TEST_MT("dmtc1 $t0, $f1");
+
+ TEST_MF("mfc1 $t0, $f0");
+ TEST_MF("mfc1 $t0, $f1");
+
+ TEST_MF("dmfc1 $t0, $f0");
+ TEST_MF("dmfc1 $t0, $f1");
+
+ TEST_MOVE("movn.s $f0, $f2, $t0");
+ TEST_MOVE("movn.s $f0, $f1, $t0");
+ TEST_MOVE("movn.s $f1, $f2, $t0");
+ TEST_MOVE("movn.s $f0, $f2, $0");
+ TEST_MOVE("movn.s $f0, $f1, $0");
+ TEST_MOVE("movn.s $f1, $f2, $0");
+
+ TEST_MOVE("movn.d $f0, $f2, $t0");
+ TEST_MOVE("movn.d $f0, $f1, $t0");
+ TEST_MOVE("movn.d $f1, $f2, $t0");
+ TEST_MOVE("movn.d $f0, $f2, $0");
+ TEST_MOVE("movn.d $f0, $f1, $0");
+ TEST_MOVE("movn.d $f1, $f2, $0");
+
+ TEST_MOVE("movz.s $f0, $f2, $t0");
+ TEST_MOVE("movz.s $f0, $f1, $t0");
+ TEST_MOVE("movz.s $f1, $f2, $t0");
+ TEST_MOVE("movz.s $f0, $f2, $0");
+ TEST_MOVE("movz.s $f0, $f1, $0");
+ TEST_MOVE("movz.s $f1, $f2, $0");
+
+ TEST_MOVE("movz.d $f0, $f2, $t0");
+ TEST_MOVE("movz.d $f0, $f1, $t0");
+ TEST_MOVE("movz.d $f1, $f2, $t0");
+ TEST_MOVE("movz.d $f0, $f2, $0");
+ TEST_MOVE("movz.d $f0, $f1, $0");
+ TEST_MOVE("movz.d $f1, $f2, $0");
+}
+
+int main() {
+ int fr_prctl, fr_detected;
+
+ test(&fr_prctl, &fr_detected);
+
+ /* FP64 */
+ if (fr_prctl == 1) {
+
+ /* Change mode to FP32 */
+ if (prctl(PR_SET_FP_MODE, 0) != 0) {
+ fatal_error("prctl(PR_SET_FP_MODE, 0) fails.");
+ }
+
+ test(&fr_prctl, &fr_detected);
+
+ /* Change back FP mode */
+ if (prctl(PR_SET_FP_MODE, 1) != 0) {
+ fatal_error("prctl(PR_SET_FP_MODE, 1) fails.");
+ }
+
+ test(&fr_prctl, &fr_detected);
+ }
+
+ return 0;
+}
+#else
+int main() {
+ return 0;
+}
+#endif
diff --git a/none/tests/mips64/change_fp_mode.stderr.exp b/none/tests/mips64/change_fp_mode.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/mips64/change_fp_mode.stderr.exp
diff --git a/none/tests/mips64/change_fp_mode.stdout.exp b/none/tests/mips64/change_fp_mode.stdout.exp
new file mode 100644
index 0000000..f527e1e
--- /dev/null
+++ b/none/tests/mips64/change_fp_mode.stdout.exp
@@ -0,0 +1,147 @@
+fr_prctl: 1, fr_detected: 1
+lwc1 $f0, 0($t0) :: lo32(f1): 5a5a, lo32(f0): 12345678
+lwc1 $f1, 0($t0) :: lo32(f1): 12345678, lo32(f0): 5a5a
+lwxc1 $f0, $0($t0) :: lo32(f1): 5a5a, lo32(f0): 12345678
+lwxc1 $f1, $0($t0) :: lo32(f1): 12345678, lo32(f0): 5a5a
+ldc1 $f0, 0($t0) :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+ldc1 $f1, 0($t0) :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+ldxc1 $f0, $0($t0) :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+ldxc1 $f1, $0($t0) :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+swc1 $f0, 0($t0) :: mem: 90abcdef
+swc1 $f1, 0($t0) :: mem: 5a5a
+swxc1 $f0, $0($t0) :: mem: 90abcdef
+swxc1 $f1, $0($t0) :: mem: 5a5a
+sdc1 $f0, 0($t0) :: mem: 1234567890abcdef
+sdc1 $f1, 0($t0) :: mem: 5a5a
+sdxc1 $f0, $0($t0) :: mem: 1234567890abcdef
+sdxc1 $f1, $0($t0) :: mem: 5a5a
+mtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+mtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+dmtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+dmtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+mfc1 $t0, $f0 :: t0: ffffffff90abcdef
+mfc1 $t0, $f1 :: t0: 5a5a
+dmfc1 $t0, $f0 :: t0: 1234567890abcdef
+dmfc1 $t0, $f1 :: t0: 5a5a
+movn.s $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movn.s $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movn.s $f1, $f2, $t0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movn.s $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.s $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.s $f1, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movn.d $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movn.d $f1, $f2, $t0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movn.d $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f1, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f1, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movz.s $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movz.s $f1, $f2, $0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movz.d $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f1, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movz.d $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movz.d $f1, $f2, $0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+fr_prctl: 0, fr_detected: 0
+lwc1 $f0, 0($t0) :: lo32(f1): 5a5a, lo32(f0): 12345678
+lwc1 $f1, 0($t0) :: lo32(f1): 12345678, lo32(f0): 5a5a
+lwxc1 $f0, $0($t0) :: lo32(f1): 5a5a, lo32(f0): 12345678
+lwxc1 $f1, $0($t0) :: lo32(f1): 12345678, lo32(f0): 5a5a
+ldc1 $f0, 0($t0) :: lo32(f1): 12345678, lo32(f0): 90abcdef
+ldc1 $f1, 0($t0) :: lo32(f1): 12345678, lo32(f0): 90abcdef
+ldxc1 $f0, $0($t0) :: lo32(f1): 12345678, lo32(f0): 90abcdef
+ldxc1 $f1, $0($t0) :: lo32(f1): 12345678, lo32(f0): 90abcdef
+swc1 $f0, 0($t0) :: mem: 90abcdef
+swc1 $f1, 0($t0) :: mem: 12345678
+swxc1 $f0, $0($t0) :: mem: 90abcdef
+swxc1 $f1, $0($t0) :: mem: 12345678
+sdc1 $f0, 0($t0) :: mem: 1234567890abcdef
+sdc1 $f1, 0($t0) :: mem: 1234567890abcdef
+sdxc1 $f0, $0($t0) :: mem: 1234567890abcdef
+sdxc1 $f1, $0($t0) :: mem: 1234567890abcdef
+mtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+mtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+dmtc1 $t0, $f0 :: lo32(f1): 12345678, lo32(f0): 90abcdef
+dmtc1 $t0, $f1 :: lo32(f1): 12345678, lo32(f0): 90abcdef
+mfc1 $t0, $f0 :: t0: ffffffff90abcdef
+mfc1 $t0, $f1 :: t0: 12345678
+dmfc1 $t0, $f0 :: t0: 1234567890abcdef
+dmfc1 $t0, $f1 :: t0: 1234567890abcdef
+movn.s $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movn.s $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movn.s $f1, $f2, $t0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movn.s $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.s $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.s $f1, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f0, $f2, $t0 :: lo32(f1): 12345678, lo32(f0): 90abcdef
+movn.d $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f1, $f2, $t0 :: lo32(f1): 12345678, lo32(f0): 90abcdef
+movn.d $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f1, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f1, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movz.s $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movz.s $f1, $f2, $0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movz.d $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f1, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f0, $f2, $0 :: lo32(f1): 12345678, lo32(f0): 90abcdef
+movz.d $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f1, $f2, $0 :: lo32(f1): 12345678, lo32(f0): 90abcdef
+fr_prctl: 1, fr_detected: 1
+lwc1 $f0, 0($t0) :: lo32(f1): 5a5a, lo32(f0): 12345678
+lwc1 $f1, 0($t0) :: lo32(f1): 12345678, lo32(f0): 5a5a
+lwxc1 $f0, $0($t0) :: lo32(f1): 5a5a, lo32(f0): 12345678
+lwxc1 $f1, $0($t0) :: lo32(f1): 12345678, lo32(f0): 5a5a
+ldc1 $f0, 0($t0) :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+ldc1 $f1, 0($t0) :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+ldxc1 $f0, $0($t0) :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+ldxc1 $f1, $0($t0) :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+swc1 $f0, 0($t0) :: mem: 90abcdef
+swc1 $f1, 0($t0) :: mem: 5a5a
+swxc1 $f0, $0($t0) :: mem: 90abcdef
+swxc1 $f1, $0($t0) :: mem: 5a5a
+sdc1 $f0, 0($t0) :: mem: 1234567890abcdef
+sdc1 $f1, 0($t0) :: mem: 5a5a
+sdxc1 $f0, $0($t0) :: mem: 1234567890abcdef
+sdxc1 $f1, $0($t0) :: mem: 5a5a
+mtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+mtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+dmtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
+dmtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+mfc1 $t0, $f0 :: t0: ffffffff90abcdef
+mfc1 $t0, $f1 :: t0: 5a5a
+dmfc1 $t0, $f0 :: t0: 1234567890abcdef
+dmfc1 $t0, $f1 :: t0: 5a5a
+movn.s $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movn.s $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movn.s $f1, $f2, $t0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movn.s $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.s $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.s $f1, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movn.d $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movn.d $f1, $f2, $t0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movn.d $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movn.d $f1, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f1, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.s $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movz.s $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movz.s $f1, $f2, $0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
+movz.d $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f1, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
+movz.d $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
+movz.d $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
+movz.d $f1, $f2, $0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
diff --git a/none/tests/mips64/change_fp_mode.vgtest b/none/tests/mips64/change_fp_mode.vgtest
new file mode 100644
index 0000000..df9ed62
--- /dev/null
+++ b/none/tests/mips64/change_fp_mode.vgtest
@@ -0,0 +1,3 @@
+prog: change_fp_mode
+prereq: ../../../tests/mips_features fpu
+vgopts: -q
diff --git a/none/tests/mips64/round.c b/none/tests/mips64/round.c
index e46c7b6..4634057 100644
--- a/none/tests/mips64/round.c
+++ b/none/tests/mips64/round.c
@@ -9,6 +9,7 @@
int i;
int fcsr = 0;
for (i = 0; i < MAX_ARR; i++) {
+ clear_fcc();
switch(op) {
case CEILWS:
UNOPfw("ceil.w.s");
@@ -111,6 +112,7 @@
set_rounding_mode(rm);
printf("roundig mode: %s\n", round_mode_name[rm]);
for (i = 0; i < MAX_ARR; i++) {
+ clear_fcc();
set_rounding_mode(rm);
switch(op1) {
case CVTDS:
diff --git a/none/tests/mips64/rounding_mode.h b/none/tests/mips64/rounding_mode.h
index 38354be..c42cb34 100644
--- a/none/tests/mips64/rounding_mode.h
+++ b/none/tests/mips64/rounding_mode.h
@@ -60,4 +60,15 @@
break;
}
}
+
+void clear_fcc(){
+ __asm__ __volatile__(
+ "cfc1 $t0, $31" "\n\t"
+ "and $t0, $t0, 0x17FFFFF" "\n\t"
+ "ctc1 $t0, $31" "\n\t"
+ :
+ :
+ : "t0"
+ );
+}
#endif
diff --git a/none/tests/mips64/test_math.cpp b/none/tests/mips64/test_math.cpp
deleted file mode 120000
index b2ce3d0..0000000
--- a/none/tests/mips64/test_math.cpp
+++ /dev/null
@@ -1 +0,0 @@
-../mips32/test_math.cpp
\ No newline at end of file
diff --git a/none/tests/mips64/test_math.cpp b/none/tests/mips64/test_math.cpp
new file mode 100644
index 0000000..8a0f2dc
--- /dev/null
+++ b/none/tests/mips64/test_math.cpp
@@ -0,0 +1,115 @@
+#include <fenv.h>
+#include <limits.h>
+#include <math.h>
+#include <stdint.h>
+#include <stdio.h>
+
+static void DivideByZero() {
+ // volatile to prevent compiler optimizations.
+ volatile float zero = 0.0f;
+ volatile float result __attribute__((unused)) = 123.0f / zero;
+}
+
+int main () {
+ /* Testing lrint. */
+ fesetround(FE_UPWARD); // lrint/lrintf/lrintl obey the rounding mode.
+ printf("fesetround(FE_UPWARD)\n");
+ printf("lrint(1234.01): %ld\n", lrint(1234.01));
+ printf("lrintf(1234.01f): %ld\n", lrintf(1234.01f));
+ printf("lrintl(1234.01): %ld\n", lrintl(1234.01));
+ fesetround(FE_TOWARDZERO); // lrint/lrintf/lrintl obey the rounding mode.
+ printf("fesetround(FE_TOWARDZERO)\n");
+ printf("lrint(1234.01): %ld\n", lrint(1234.01));
+ printf("lrintf(1234.01f): %ld\n", lrintf(1234.01f));
+ printf("lrintl(1234.01): %ld\n", lrintl(1234.01));
+ fesetround(FE_UPWARD); // llrint/llrintf/llrintl obey the rounding mode.
+ printf("fesetround(FE_UPWARD)\n");
+ printf("llrint(1234.01): %lld\n", llrint(1234.01));
+ printf("llrintf(1234.01f): %lld\n", llrintf(1234.01f));
+ printf("llrintf(1234.01f): %lld\n", llrintl(1234.01));
+ fesetround(FE_TOWARDZERO); // llrint/llrintf/llrintl obey the rounding mode.
+ printf("fesetround(FE_TOWARDZERO)\n");
+ printf("llrint(1234.01): %lld\n", llrint(1234.01));
+ printf("llrintf(1234.01f): %lld\n", llrintf(1234.01f));
+ printf("llrintl(1234.01): %lld\n", llrintl(1234.01));
+
+ /* Tesing rint. */
+ fesetround(FE_UPWARD); // rint/rintf/rintl obey the rounding mode.
+ printf("fesetround(FE_UPWARD)\n");
+ feclearexcept(FE_ALL_EXCEPT); // rint/rintf/rintl do set the FE_INEXACT flag.
+ printf("feclearexcept(FE_ALL_EXCEPT)\n");
+ printf("rint(1234.0): %f\n", rint(1234.0));
+ printf("(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): %d\n",
+ (fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT));
+ printf("rint(1234.01): %f\n", rint(1234.01));
+ printf("(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): %d\n",
+ (fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT));
+
+ feclearexcept(FE_ALL_EXCEPT); // rint/rintf/rintl do set the FE_INEXACT flag.
+ printf("feclearexcept(FE_ALL_EXCEPT)\n");
+ printf("rintf(1234.0f): %f\n", rintf(1234.0f));
+ printf("(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): %d\n",
+ (fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT));
+ printf("rintf(1234.01f): %f\n", rintf(1234.01f));
+ printf("(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): %d\n",
+ (fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT));
+
+ feclearexcept(FE_ALL_EXCEPT); // rint/rintf/rintl do set the FE_INEXACT flag.
+ printf("feclearexcept(FE_ALL_EXCEPT)\n");
+ printf("rintl(1234.0): %Lf\n", rintl(1234.0));
+ printf("(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): %d\n",
+ (fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT));
+ printf("rintl(1234.01): %Lf\n", rintl(1234.01));
+ printf("(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): %d\n",
+ (fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT));
+
+ fesetround(FE_TOWARDZERO); // rint/rintf obey the rounding mode.
+ printf("fesetround(FE_TOWARDZERO)\n");
+ printf("rint(1234.01): %f\n", rint(1234.01));
+ printf("rintf(1234.01f): %f\n", rintf(1234.01f));
+ printf("rintl(1234.01): %Lf\n", rintl(1234.01));
+
+ /* Testing nearbyint. */
+ fesetround(FE_UPWARD); // nearbyint/nearbyintf/nearbyintl obey the rounding mode.
+ printf("fesetround(FE_UPWARD)\n");
+ feclearexcept(FE_ALL_EXCEPT); // nearbyint/nearbyintf/nearbyintl don't set the FE_INEXACT flag.
+ printf("feclearexcept(FE_ALL_EXCEPT)\n");
+ printf("nearbyint(1234.0): %f\n", nearbyint(1234.0));
+ printf("nearbyint(1234.01): %f\n", nearbyint(1234.01));
+
+ feclearexcept(FE_ALL_EXCEPT);
+ printf("feclearexcept(FE_ALL_EXCEPT)\n");
+ printf("nearbyintf(1234.0f): %f\n", nearbyintf(1234.0f));
+ printf("nearbyintf(1234.01f): %f\n", nearbyintf(1234.01f));
+
+ feclearexcept(FE_ALL_EXCEPT); // nearbyint/nearbyintf/nearbyintl don't set the FE_INEXACT flag.
+ printf("feclearexcept(FE_ALL_EXCEPT)\n");
+ printf("nearbyintl(1234.0f): %Lf\n", nearbyintl(1234.0f));
+ printf("nearbyintl(1234.01f): %Lf\n", nearbyintl(1234.01f));
+
+ fesetround(FE_TOWARDZERO); // nearbyint/nearbyintf/nearbyintl obey the rounding mode.
+ printf("fesetround(FE_TOWARDZERO)\n");
+ printf("nearbyint(1234.01): %f\n", nearbyint(1234.01));
+ printf("nearbyintf(1234.01f): %f\n", nearbyintf(1234.01f));
+ printf("nearbyintl(1234.01): %Lf\n", nearbyintl(1234.01));
+
+ /* Test log. */
+ printf("log(M_E): %lf\n", log(M_E));
+
+ /* Test tgamma. */
+ printf("tgamma(5.0): %lf\n", tgamma(5.0));
+
+ /* Test cbrt. */
+ printf("cbrt(27.0): %lf\n", cbrt(27.0));
+
+ /* Test dividing by zero. */
+ // Clearing clears.
+ printf("feclearexcept(FE_ALL_EXCEPT): %d\n", feclearexcept(FE_ALL_EXCEPT));
+
+ // Dividing by zero sets FE_DIVBYZERO.
+ DivideByZero();
+ int raised = fetestexcept(FE_DIVBYZERO | FE_OVERFLOW);
+ printf("raised: %d\n", raised);
+
+ return 0;
+}
diff --git a/none/tests/mips64/test_math.vgtest b/none/tests/mips64/test_math.vgtest
deleted file mode 120000
index c2ace8d..0000000
--- a/none/tests/mips64/test_math.vgtest
+++ /dev/null
@@ -1 +0,0 @@
-../mips32/test_math.vgtest
\ No newline at end of file
diff --git a/none/tests/mips64/test_math.vgtest b/none/tests/mips64/test_math.vgtest
new file mode 100644
index 0000000..a0d94d5
--- /dev/null
+++ b/none/tests/mips64/test_math.vgtest
@@ -0,0 +1,2 @@
+prog: test_math
+vgopts: -q
diff --git a/none/tests/nocwd.c b/none/tests/nocwd.c
new file mode 100644
index 0000000..d01d623
--- /dev/null
+++ b/none/tests/nocwd.c
@@ -0,0 +1,45 @@
+#include <limits.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+
+int
+main (int argc, char **argv)
+{
+ char template[] = "/tmp/wd_test_XXXXXX";
+ char *tmpdir = mkdtemp(template);
+ if (tmpdir == NULL)
+ {
+ perror ("Couldn't mkdtemp");
+ exit (-1);
+ }
+
+ if (chdir (tmpdir) != 0)
+ {
+ perror ("Couldn't chdir into tmpdir");
+ exit (-1);
+ }
+
+ /* Go deep. */
+ int dirslen = PATH_MAX;
+ while (dirslen > 0)
+ {
+ /* We don't do any error checking in case some OS fails. */
+ mkdir ("subdir", S_IRWXU);
+ chdir ("subdir");
+ dirslen -= strlen ("subdir");
+ }
+
+ /* Make one component inaccessible. */
+ chmod(tmpdir, 0);
+
+ /* Remove the current dir (don't check error, might fail). */
+ rmdir ("../subdir");
+
+ execlp ("echo", "echo", "Hello", "World", (char *) NULL);
+ perror ("Couldn't execlp");
+ return -1;
+}
diff --git a/none/tests/nocwd.stderr.exp b/none/tests/nocwd.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/nocwd.stderr.exp
diff --git a/none/tests/nocwd.stdout.exp b/none/tests/nocwd.stdout.exp
new file mode 100644
index 0000000..557db03
--- /dev/null
+++ b/none/tests/nocwd.stdout.exp
@@ -0,0 +1 @@
+Hello World
diff --git a/none/tests/nocwd.vgtest b/none/tests/nocwd.vgtest
new file mode 100644
index 0000000..74e2b4a
--- /dev/null
+++ b/none/tests/nocwd.vgtest
@@ -0,0 +1,2 @@
+prog: nocwd
+vgopts: -q --trace-children=yes
diff --git a/none/tests/ppc32/Makefile.am b/none/tests/ppc32/Makefile.am
index 196239e..c4af707 100644
--- a/none/tests/ppc32/Makefile.am
+++ b/none/tests/ppc32/Makefile.am
@@ -38,7 +38,8 @@
test_dfp3.stderr.exp test_dfp3.stdout.exp test_dfp3.vgtest \
test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \
test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest \
- jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.vgtest \
+ jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.vgtest \
+ jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.stdout.exp-LE \
jm_fp_isa_2_07.stderr.exp jm_fp_isa_2_07.stdout.exp jm_fp_isa_2_07.vgtest \
jm_int_isa_2_07.stderr.exp jm_int_isa_2_07.vgtest \
jm_int_isa_2_07.stdout.exp \
diff --git a/none/tests/ppc32/Makefile.in b/none/tests/ppc32/Makefile.in
new file mode 100644
index 0000000..ec161c6
--- /dev/null
+++ b/none/tests/ppc32/Makefile.in
@@ -0,0 +1,1553 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
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+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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+
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+
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+
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+ fi; \
+}
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+ *) echo "am__make_running_with_option: internal error: invalid" \
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+
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+ round$(EXEEXT) test_isa_2_06_part1$(EXEEXT) \
+ test_isa_2_06_part2$(EXEEXT) test_isa_2_06_part3$(EXEEXT) \
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+testVMX_LINK = $(CCLD) $(testVMX_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp1_SOURCES = test_dfp1.c
+test_dfp1_OBJECTS = test_dfp1-test_dfp1.$(OBJEXT)
+test_dfp1_DEPENDENCIES =
+test_dfp1_LINK = $(CCLD) $(test_dfp1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp2_SOURCES = test_dfp2.c
+test_dfp2_OBJECTS = test_dfp2-test_dfp2.$(OBJEXT)
+test_dfp2_DEPENDENCIES =
+test_dfp2_LINK = $(CCLD) $(test_dfp2_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp3_SOURCES = test_dfp3.c
+test_dfp3_OBJECTS = test_dfp3-test_dfp3.$(OBJEXT)
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+ $(LDFLAGS) -o $@
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+ test_isa_2_06_part1-test_isa_2_06_part1.$(OBJEXT)
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+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_IPA_ICF = @FLAG_FNO_IPA_ICF@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_FSANITIZE = @FLAG_FSANITIZE@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MIPS32 = @FLAG_MIPS32@
+FLAG_MIPS64 = @FLAG_MIPS64@
+FLAG_MLONG_DOUBLE_128 = @FLAG_MLONG_DOUBLE_128@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_OCTEON = @FLAG_OCTEON@
+FLAG_OCTEON2 = @FLAG_OCTEON2@
+FLAG_T_TEXT = @FLAG_T_TEXT@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_CAST_ALIGN = @FLAG_W_CAST_ALIGN@
+FLAG_W_CAST_QUAL = @FLAG_W_CAST_QUAL@
+FLAG_W_EMPTY_BODY = @FLAG_W_EMPTY_BODY@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_FORMAT = @FLAG_W_FORMAT@
+FLAG_W_FORMAT_SECURITY = @FLAG_W_FORMAT_SECURITY@
+FLAG_W_FORMAT_SIGNEDNESS = @FLAG_W_FORMAT_SIGNEDNESS@
+FLAG_W_IGNORED_QUALIFIERS = @FLAG_W_IGNORED_QUALIFIERS@
+FLAG_W_MISSING_PARAMETER_TYPE = @FLAG_W_MISSING_PARAMETER_TYPE@
+FLAG_W_NO_INFINITE_RECURSION = @FLAG_W_NO_INFINITE_RECURSION@
+FLAG_W_NO_MEMSET_TRANSPOSED_ARGS = @FLAG_W_NO_MEMSET_TRANSPOSED_ARGS@
+FLAG_W_NO_MISMATCHED_NEW_DELETE = @FLAG_W_NO_MISMATCHED_NEW_DELETE@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_POINTER_SIGN = @FLAG_W_NO_POINTER_SIGN@
+FLAG_W_NO_STATIC_LOCAL_IN_INLINE = @FLAG_W_NO_STATIC_LOCAL_IN_INLINE@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+FLAG_W_NO_UNUSED_FUNCTION = @FLAG_W_NO_UNUSED_FUNCTION@
+FLAG_W_OLD_STYLE_DECLARATION = @FLAG_W_OLD_STYLE_DECLARATION@
+FLAG_W_WRITE_STRINGS = @FLAG_W_WRITE_STRINGS@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+HWCAP_HAS_ALTIVEC = @HWCAP_HAS_ALTIVEC@
+HWCAP_HAS_DFP = @HWCAP_HAS_DFP@
+HWCAP_HAS_HTM = @HWCAP_HAS_HTM@
+HWCAP_HAS_ISA_2_05 = @HWCAP_HAS_ISA_2_05@
+HWCAP_HAS_ISA_2_06 = @HWCAP_HAS_ISA_2_06@
+HWCAP_HAS_ISA_2_07 = @HWCAP_HAS_ISA_2_07@
+HWCAP_HAS_ISA_3_00 = @HWCAP_HAS_ISA_3_00@
+HWCAP_HAS_VSX = @HWCAP_HAS_VSX@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LIB_UBSAN = @LIB_UBSAN@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY_2 = @PREFERRED_STACK_BOUNDARY_2@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+SOLARIS_UNDEF_LARGESOURCE = @SOLARIS_UNDEF_LARGESOURCE@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+VG_TMPDIR = @VG_TMPDIR@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = -O2 -g -std=gnu99 -Wall -Wmissing-prototypes -Wshadow \
+ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \
+ @FLAG_W_CAST_ALIGN@ @FLAG_W_CAST_QUAL@ @FLAG_W_WRITE_STRINGS@ \
+ @FLAG_W_EMPTY_BODY@ @FLAG_W_FORMAT@ @FLAG_W_FORMAT_SIGNEDNESS@ \
+ @FLAG_W_FORMAT_SECURITY@ @FLAG_W_IGNORED_QUALIFIERS@ \
+ @FLAG_W_MISSING_PARAMETER_TYPE@ @FLAG_W_OLD_STYLE_DECLARATION@ \
+ @FLAG_FNO_STACK_PROTECTOR@ @FLAG_FSANITIZE@ \
+ -fno-strict-aliasing -fno-builtin $(am__append_1)
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fpic -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# These flags are used for building the preload shared objects (PSOs).
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads. Also, we must use any
+# -mpreferred-stack-boundary flag to build the preload shared
+# objects, since that risks misaligning the client's stack and
+# results in segfaults like (eg) #324050.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \
+@VGCONF_OS_IS_DARWIN_TRUE@ -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
+ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
+AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
+AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ @FLAG_M32@ $(am__empty)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) @FLAG_M32@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+EXTRA_DIST = \
+ bug129390-ppc32.stdout.exp bug129390-ppc32.stderr.exp \
+ bug129390-ppc32.vgtest \
+ bug139050-ppc32.stdout.exp bug139050-ppc32.stderr.exp \
+ bug139050-ppc32.vgtest \
+ ldstrev.stderr.exp ldstrev.stdout.exp ldstrev.vgtest \
+ jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
+ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-BE2 \
+ jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
+ jm-vmx.vgtest \
+ jm-misc.stderr.exp jm-misc.stdout.exp jm-misc.vgtest \
+ lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
+ mftocrf.stderr.exp mftocrf.stdout.exp mftocrf.vgtest \
+ mcrfs.stderr.exp mcrfs.stdout.exp mcrfs.vgtest \
+ round.stderr.exp round.stdout.exp round.vgtest \
+ test_fx.stderr.exp test_fx.stdout.exp test_fx.stdout.exp_Minus_nan \
+ test_fx.vgtest \
+ test_gx.stderr.exp test_gx.stdout.exp test_gx.stdout.exp_Minus_nan \
+ test_gx.vgtest \
+ testVMX.stderr.exp testVMX.stdout.exp testVMX.vgtest \
+ twi.stderr.exp twi.stdout.exp twi.vgtest \
+ tw.stderr.exp tw.stdout.exp tw.vgtest \
+ xlc_dbl_u32.stderr.exp xlc_dbl_u32.stdout.exp xlc_dbl_u32.vgtest \
+ opcodes.h \
+ power5+_round.stderr.exp power5+_round.stdout.exp power5+_round.vgtest \
+ power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \
+ test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
+ test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
+ test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
+ test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
+ test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
+ test_dfp2.stdout.exp_Without_dcffix \
+ test_dfp3.stderr.exp test_dfp3.stdout.exp test_dfp3.vgtest \
+ test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \
+ test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest \
+ jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.vgtest \
+ jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.stdout.exp-LE \
+ jm_fp_isa_2_07.stderr.exp jm_fp_isa_2_07.stdout.exp jm_fp_isa_2_07.vgtest \
+ jm_int_isa_2_07.stderr.exp jm_int_isa_2_07.vgtest \
+ jm_int_isa_2_07.stdout.exp \
+ test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest \
+ test_tm.stderr.exp test_tm.stdout.exp test_tm.vgtest \
+ test_touch_tm.stderr.exp test_touch_tm.stdout.exp test_touch_tm.vgtest \
+ ldst_multiple.stderr.exp ldst_multiple.stdout.exp ldst_multiple.vgtest \
+ data-cache-instructions.stderr.exp data-cache-instructions.stdout.exp data-cache-instructions.vgtest
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+@HAS_ALTIVEC_FALSE@BUILD_FLAG_ALTIVEC =
+@HAS_ALTIVEC_TRUE@BUILD_FLAG_ALTIVEC = -maltivec
+@HAS_ALTIVEC_FALSE@BUILD_FLAG_ABI_ALTIVEC =
+@HAS_ALTIVEC_TRUE@BUILD_FLAG_ABI_ALTIVEC = -mabi=altivec
+@HAS_ALTIVEC_FALSE@ALTIVEC_FLAG =
+@HAS_ALTIVEC_TRUE@ALTIVEC_FLAG = -DHAS_ALTIVEC
+@HAS_VSX_FALSE@BUILD_FLAG_VSX =
+@HAS_VSX_TRUE@BUILD_FLAG_VSX = -mvsx
+@HAS_VSX_FALSE@VSX_FLAG =
+@HAS_VSX_TRUE@VSX_FLAG = -DHAS_VSX
+@HAS_DFP_FALSE@BUILD_FLAGS_DFP =
+@HAS_DFP_TRUE@BUILD_FLAGS_DFP = -mhard-dfp -mcpu=power6
+@HAS_DFP_FALSE@DFP_FLAG =
+@HAS_DFP_TRUE@DFP_FLAG = -DHAS_DFP
+@HAS_ISA_2_07_FALSE@BUILD_FLAGS_ISA_2_07 =
+@HAS_ISA_2_07_TRUE@BUILD_FLAGS_ISA_2_07 = -mcpu=power8
+@HAS_ISA_2_07_FALSE@ISA_2_07_FLAG =
+@HAS_ISA_2_07_TRUE@ISA_2_07_FLAG = -DHAS_ISA_2_07
+@SUPPORTS_HTM_TRUE@HTM_FLAG = -mhtm -DSUPPORTS_HTM
+jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames \
+ @FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_ALTIVEC)
+
+testVMX_CFLAGS = $(AM_CFLAGS) -O -g -Wall -DALTIVEC \
+ -DGCC_COMPILER @FLAG_M32@ $(BUILD_FLAG_ALTIVEC) \
+ $(BUILD_FLAG_ABI_ALTIVEC)
+
+test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
+ @FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
+ @FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
+ @FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
+
+test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
+
+test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_2_07_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
+
+test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_2_07_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
+
+test_isa_2_06_part3_LDADD = -lm
+test_dfp1_LDADD = -lm
+test_dfp2_LDADD = -lm
+test_dfp3_LDADD = -lm
+test_dfp4_LDADD = -lm
+test_dfp5_LDADD = -lm
+test_isa_2_07_part1_LDADD = -lm
+test_isa_2_07_part2_LDADD = -lm
+test_tm_LDADD = -lm
+test_touch_tm_LDADD = -lm
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/ppc32/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/ppc32/Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+$(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__empty):
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES) $(EXTRA_allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(AM_V_CCLD)$(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+
+bug129390-ppc32$(EXEEXT): $(bug129390_ppc32_OBJECTS) $(bug129390_ppc32_DEPENDENCIES) $(EXTRA_bug129390_ppc32_DEPENDENCIES)
+ @rm -f bug129390-ppc32$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug129390_ppc32_OBJECTS) $(bug129390_ppc32_LDADD) $(LIBS)
+
+bug139050-ppc32$(EXEEXT): $(bug139050_ppc32_OBJECTS) $(bug139050_ppc32_DEPENDENCIES) $(EXTRA_bug139050_ppc32_DEPENDENCIES)
+ @rm -f bug139050-ppc32$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug139050_ppc32_OBJECTS) $(bug139050_ppc32_LDADD) $(LIBS)
+
+data-cache-instructions$(EXEEXT): $(data_cache_instructions_OBJECTS) $(data_cache_instructions_DEPENDENCIES) $(EXTRA_data_cache_instructions_DEPENDENCIES)
+ @rm -f data-cache-instructions$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(data_cache_instructions_OBJECTS) $(data_cache_instructions_LDADD) $(LIBS)
+
+jm-insns$(EXEEXT): $(jm_insns_OBJECTS) $(jm_insns_DEPENDENCIES) $(EXTRA_jm_insns_DEPENDENCIES)
+ @rm -f jm-insns$(EXEEXT)
+ $(AM_V_CCLD)$(jm_insns_LINK) $(jm_insns_OBJECTS) $(jm_insns_LDADD) $(LIBS)
+
+ldst_multiple$(EXEEXT): $(ldst_multiple_OBJECTS) $(ldst_multiple_DEPENDENCIES) $(EXTRA_ldst_multiple_DEPENDENCIES)
+ @rm -f ldst_multiple$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(ldst_multiple_OBJECTS) $(ldst_multiple_LDADD) $(LIBS)
+
+ldstrev$(EXEEXT): $(ldstrev_OBJECTS) $(ldstrev_DEPENDENCIES) $(EXTRA_ldstrev_DEPENDENCIES)
+ @rm -f ldstrev$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(ldstrev_OBJECTS) $(ldstrev_LDADD) $(LIBS)
+
+lsw$(EXEEXT): $(lsw_OBJECTS) $(lsw_DEPENDENCIES) $(EXTRA_lsw_DEPENDENCIES)
+ @rm -f lsw$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(lsw_OBJECTS) $(lsw_LDADD) $(LIBS)
+
+mcrfs$(EXEEXT): $(mcrfs_OBJECTS) $(mcrfs_DEPENDENCIES) $(EXTRA_mcrfs_DEPENDENCIES)
+ @rm -f mcrfs$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(mcrfs_OBJECTS) $(mcrfs_LDADD) $(LIBS)
+
+mftocrf$(EXEEXT): $(mftocrf_OBJECTS) $(mftocrf_DEPENDENCIES) $(EXTRA_mftocrf_DEPENDENCIES)
+ @rm -f mftocrf$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(mftocrf_OBJECTS) $(mftocrf_LDADD) $(LIBS)
+
+power5+_round$(EXEEXT): $(power5__round_OBJECTS) $(power5__round_DEPENDENCIES) $(EXTRA_power5__round_DEPENDENCIES)
+ @rm -f power5+_round$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(power5__round_OBJECTS) $(power5__round_LDADD) $(LIBS)
+
+power6_bcmp$(EXEEXT): $(power6_bcmp_OBJECTS) $(power6_bcmp_DEPENDENCIES) $(EXTRA_power6_bcmp_DEPENDENCIES)
+ @rm -f power6_bcmp$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(power6_bcmp_OBJECTS) $(power6_bcmp_LDADD) $(LIBS)
+
+round$(EXEEXT): $(round_OBJECTS) $(round_DEPENDENCIES) $(EXTRA_round_DEPENDENCIES)
+ @rm -f round$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(round_OBJECTS) $(round_LDADD) $(LIBS)
+
+testVMX$(EXEEXT): $(testVMX_OBJECTS) $(testVMX_DEPENDENCIES) $(EXTRA_testVMX_DEPENDENCIES)
+ @rm -f testVMX$(EXEEXT)
+ $(AM_V_CCLD)$(testVMX_LINK) $(testVMX_OBJECTS) $(testVMX_LDADD) $(LIBS)
+
+test_dfp1$(EXEEXT): $(test_dfp1_OBJECTS) $(test_dfp1_DEPENDENCIES) $(EXTRA_test_dfp1_DEPENDENCIES)
+ @rm -f test_dfp1$(EXEEXT)
+ $(AM_V_CCLD)$(test_dfp1_LINK) $(test_dfp1_OBJECTS) $(test_dfp1_LDADD) $(LIBS)
+
+test_dfp2$(EXEEXT): $(test_dfp2_OBJECTS) $(test_dfp2_DEPENDENCIES) $(EXTRA_test_dfp2_DEPENDENCIES)
+ @rm -f test_dfp2$(EXEEXT)
+ $(AM_V_CCLD)$(test_dfp2_LINK) $(test_dfp2_OBJECTS) $(test_dfp2_LDADD) $(LIBS)
+
+test_dfp3$(EXEEXT): $(test_dfp3_OBJECTS) $(test_dfp3_DEPENDENCIES) $(EXTRA_test_dfp3_DEPENDENCIES)
+ @rm -f test_dfp3$(EXEEXT)
+ $(AM_V_CCLD)$(test_dfp3_LINK) $(test_dfp3_OBJECTS) $(test_dfp3_LDADD) $(LIBS)
+
+test_dfp4$(EXEEXT): $(test_dfp4_OBJECTS) $(test_dfp4_DEPENDENCIES) $(EXTRA_test_dfp4_DEPENDENCIES)
+ @rm -f test_dfp4$(EXEEXT)
+ $(AM_V_CCLD)$(test_dfp4_LINK) $(test_dfp4_OBJECTS) $(test_dfp4_LDADD) $(LIBS)
+
+test_dfp5$(EXEEXT): $(test_dfp5_OBJECTS) $(test_dfp5_DEPENDENCIES) $(EXTRA_test_dfp5_DEPENDENCIES)
+ @rm -f test_dfp5$(EXEEXT)
+ $(AM_V_CCLD)$(test_dfp5_LINK) $(test_dfp5_OBJECTS) $(test_dfp5_LDADD) $(LIBS)
+
+test_fx$(EXEEXT): $(test_fx_OBJECTS) $(test_fx_DEPENDENCIES) $(EXTRA_test_fx_DEPENDENCIES)
+ @rm -f test_fx$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(test_fx_OBJECTS) $(test_fx_LDADD) $(LIBS)
+
+test_gx$(EXEEXT): $(test_gx_OBJECTS) $(test_gx_DEPENDENCIES) $(EXTRA_test_gx_DEPENDENCIES)
+ @rm -f test_gx$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(test_gx_OBJECTS) $(test_gx_LDADD) $(LIBS)
+
+test_isa_2_06_part1$(EXEEXT): $(test_isa_2_06_part1_OBJECTS) $(test_isa_2_06_part1_DEPENDENCIES) $(EXTRA_test_isa_2_06_part1_DEPENDENCIES)
+ @rm -f test_isa_2_06_part1$(EXEEXT)
+ $(AM_V_CCLD)$(test_isa_2_06_part1_LINK) $(test_isa_2_06_part1_OBJECTS) $(test_isa_2_06_part1_LDADD) $(LIBS)
+
+test_isa_2_06_part2$(EXEEXT): $(test_isa_2_06_part2_OBJECTS) $(test_isa_2_06_part2_DEPENDENCIES) $(EXTRA_test_isa_2_06_part2_DEPENDENCIES)
+ @rm -f test_isa_2_06_part2$(EXEEXT)
+ $(AM_V_CCLD)$(test_isa_2_06_part2_LINK) $(test_isa_2_06_part2_OBJECTS) $(test_isa_2_06_part2_LDADD) $(LIBS)
+
+test_isa_2_06_part3$(EXEEXT): $(test_isa_2_06_part3_OBJECTS) $(test_isa_2_06_part3_DEPENDENCIES) $(EXTRA_test_isa_2_06_part3_DEPENDENCIES)
+ @rm -f test_isa_2_06_part3$(EXEEXT)
+ $(AM_V_CCLD)$(test_isa_2_06_part3_LINK) $(test_isa_2_06_part3_OBJECTS) $(test_isa_2_06_part3_LDADD) $(LIBS)
+
+test_isa_2_07_part1$(EXEEXT): $(test_isa_2_07_part1_OBJECTS) $(test_isa_2_07_part1_DEPENDENCIES) $(EXTRA_test_isa_2_07_part1_DEPENDENCIES)
+ @rm -f test_isa_2_07_part1$(EXEEXT)
+ $(AM_V_CCLD)$(test_isa_2_07_part1_LINK) $(test_isa_2_07_part1_OBJECTS) $(test_isa_2_07_part1_LDADD) $(LIBS)
+
+test_isa_2_07_part2$(EXEEXT): $(test_isa_2_07_part2_OBJECTS) $(test_isa_2_07_part2_DEPENDENCIES) $(EXTRA_test_isa_2_07_part2_DEPENDENCIES)
+ @rm -f test_isa_2_07_part2$(EXEEXT)
+ $(AM_V_CCLD)$(test_isa_2_07_part2_LINK) $(test_isa_2_07_part2_OBJECTS) $(test_isa_2_07_part2_LDADD) $(LIBS)
+
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+ @rm -f test_tm$(EXEEXT)
+ $(AM_V_CCLD)$(test_tm_LINK) $(test_tm_OBJECTS) $(test_tm_LDADD) $(LIBS)
+
+test_touch_tm$(EXEEXT): $(test_touch_tm_OBJECTS) $(test_touch_tm_DEPENDENCIES) $(EXTRA_test_touch_tm_DEPENDENCIES)
+ @rm -f test_touch_tm$(EXEEXT)
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+ @rm -f tw$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(tw_OBJECTS) $(tw_LDADD) $(LIBS)
+
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+ @rm -f twi$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(twi_OBJECTS) $(twi_LDADD) $(LIBS)
+
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+ @rm -f xlc_dbl_u32$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(xlc_dbl_u32_OBJECTS) $(xlc_dbl_u32_LDADD) $(LIBS)
+
+mostlyclean-compile:
+ -rm -f *.$(OBJEXT)
+
+distclean-compile:
+ -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/allexec-allexec.Po@am__quote@
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+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ if test -z '$(STRIP)'; then \
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ install; \
+ else \
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \
+ fi
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS TAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local cscopelist-am \
+ ctags ctags-am distclean distclean-compile distclean-generic \
+ distclean-tags distdir dvi dvi-am html html-am info info-am \
+ install install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-html \
+ install-html-am install-info install-info-am install-man \
+ install-pdf install-pdf-am install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ maintainer-clean maintainer-clean-generic mostlyclean \
+ mostlyclean-compile mostlyclean-generic pdf pdf-am ps ps-am \
+ tags tags-am uninstall uninstall-am
+
+.PRECIOUS: Makefile
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
+# It needs to be depended on by an 'uninstall-local' rule.
+uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
+uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/none/tests/ppc32/allexec.c b/none/tests/ppc32/allexec.c
deleted file mode 120000
index 6d6a9cf..0000000
--- a/none/tests/ppc32/allexec.c
+++ /dev/null
@@ -1 +0,0 @@
-../allexec.c
\ No newline at end of file
diff --git a/none/tests/allexec.c b/none/tests/ppc32/allexec.c
similarity index 100%
copy from none/tests/allexec.c
copy to none/tests/ppc32/allexec.c
diff --git a/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp b/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp
index 8ee724a..0c27edf 100644
--- a/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp
+++ b/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp
@@ -2,224 +2,777 @@
mfvsrd: 090a0b0c0e0d0e0f => 000000000e0d0e0f
mfvsrd: f1f2f3f4f5f6f7f8 => 00000000f5f6f7f8
mfvsrd: f9fafbfcfefdfeff => 00000000fefdfeff
+mfvsrd: 00007fffffffffff => 00000000ffffffff
+mfvsrd: ffff000000000000 => 0000000000000000
+mfvsrd: 0000800000000000 => 0000000000000000
+mfvsrd: 0000000000000000 => 0000000000000000
+mfvsrd: ffffffffffffffff => 00000000ffffffff
mfvsrwz: 0102030405060708 => 0000000005060708
mfvsrwz: 090a0b0c0e0d0e0f => 000000000e0d0e0f
mfvsrwz: f1f2f3f4f5f6f7f8 => 00000000f5f6f7f8
mfvsrwz: f9fafbfcfefdfeff => 00000000fefdfeff
+mfvsrwz: 00007fffffffffff => 00000000ffffffff
+mfvsrwz: ffff000000000000 => 0000000000000000
+mfvsrwz: 0000800000000000 => 0000000000000000
+mfvsrwz: 0000000000000000 => 0000000000000000
+mfvsrwz: ffffffffffffffff => 00000000ffffffff
mtvsrd: 0102030405060708 => 0000000005060708
mtvsrd: 090a0b0c0e0d0e0f => 000000000e0d0e0f
mtvsrd: f1f2f3f4f5f6f7f8 => 00000000f5f6f7f8
mtvsrd: f9fafbfcfefdfeff => 00000000fefdfeff
+mtvsrd: 00007fffffffffff => 00000000ffffffff
+mtvsrd: ffff000000000000 => 0000000000000000
+mtvsrd: 0000800000000000 => 0000000000000000
+mtvsrd: 0000000000000000 => 0000000000000000
+mtvsrd: ffffffffffffffff => 00000000ffffffff
mtvsrwz: 05060708 => 0000000005060708
mtvsrwz: 0e0d0e0f => 000000000e0d0e0f
mtvsrwz: f5f6f7f8 => 00000000f5f6f7f8
mtvsrwz: fefdfeff => 00000000fefdfeff
+mtvsrwz: ffffffff => 00000000ffffffff
+mtvsrwz: 00000000 => 0000000000000000
+mtvsrwz: 00000000 => 0000000000000000
+mtvsrwz: 00000000 => 0000000000000000
+mtvsrwz: ffffffff => 00000000ffffffff
mtfprwa: 05060708 => 0000000005060708
mtfprwa: 0e0d0e0f => 000000000e0d0e0f
mtfprwa: f5f6f7f8 => fffffffff5f6f7f8
mtfprwa: fefdfeff => fffffffffefdfeff
+mtfprwa: ffffffff => ffffffffffffffff
+mtfprwa: 00000000 => 0000000000000000
+mtfprwa: 00000000 => 0000000000000000
+mtfprwa: 00000000 => 0000000000000000
+mtfprwa: ffffffff => ffffffffffffffff
vaddudm: 0102030405060708 @@ 0102030405060708 ==> 020406080a0c0e10
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 121416181c1a1c1e
vaddudm: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> f2f4f6f8fafcff00
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 030507090d0b0d0e
+vaddudm: 0102030405060708 @@ 00007fffffffffff ==> 0102830405060707
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 09090b0c0e0d0e0f
+vaddudm: 0102030405060708 @@ 0000800000000000 ==> 0102830405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vaddudm: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f2f4f6f8fafcff00
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 030507090d0b0d0e
vaddudm: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> e3e5e7e9ebedeff0
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f3f5f7f9fdfbfdfe
+vaddudm: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> f1f373f4f5f6f7f7
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9f9fbfcfefdfeff
+vaddudm: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f373f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vaddudm: 00007fffffffffff @@ 0102030405060708 ==> 0102830405060707
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 09090b0c0e0d0e0f
+vaddudm: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> f1f373f4f5f6f7f7
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> f9f9fbfcfefdfeff
+vaddudm: 00007fffffffffff @@ 00007fffffffffff ==> 0000fffffffffffe
+ ffff000000000000 @@ ffff000000000000 ==> fffe000000000000
+vaddudm: 00007fffffffffff @@ 0000800000000000 ==> 0000ffffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vaddudm: 0000800000000000 @@ 0102030405060708 ==> 0102830405060708
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vaddudm: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> f1f373f4f5f6f7f8
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vaddudm: 0000800000000000 @@ 00007fffffffffff ==> 0000ffffffffffff
+ 0000000000000000 @@ ffff000000000000 ==> ffff000000000000
+vaddudm: 0000800000000000 @@ 0000800000000000 ==> 0001000000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vsubudm: 0102030405060708 @@ 0102030405060708 ==> 0000000000000000
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000000000000000
vsubudm: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0f0f0f0f0f0f0f10
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0f0f0f0f0f0f0f10
+vsubudm: 0102030405060708 @@ 00007fffffffffff ==> 0101830405060709
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090b0b0c0e0d0e0f
+vsubudm: 0102030405060708 @@ 0000800000000000 ==> 0101830405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vsubudm: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f0f0f0f0f0f0f0f0
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> f0f0f0f0f0f0f0f0
vsubudm: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsubudm: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> f1f273f4f5f6f7f9
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fbfbfcfefdfeff
+vsubudm: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f273f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vsubudm: 00007fffffffffff @@ 0102030405060708 ==> fefe7cfbfaf9f8f7
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> f6f4f4f3f1f2f1f1
+vsubudm: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0e0d8c0b0a090807
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 0604040301020101
+vsubudm: 00007fffffffffff @@ 00007fffffffffff ==> 0000000000000000
+ ffff000000000000 @@ ffff000000000000 ==> 0000000000000000
+vsubudm: 00007fffffffffff @@ 0000800000000000 ==> ffffffffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vsubudm: 0000800000000000 @@ 0102030405060708 ==> fefe7cfbfaf9f8f8
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> f6f5f4f3f1f2f1f1
+vsubudm: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0e0d8c0b0a090808
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0605040301020101
+vsubudm: 0000800000000000 @@ 00007fffffffffff ==> 0000000000000001
+ 0000000000000000 @@ ffff000000000000 ==> 0001000000000000
+vsubudm: 0000800000000000 @@ 0000800000000000 ==> 0000000000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vmaxud: 0102030405060708 @@ 0102030405060708 ==> 0102030405060708
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
vmaxud: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vmaxud: 0102030405060708 @@ 00007fffffffffff ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> ffff000000000000
+vmaxud: 0102030405060708 @@ 0000800000000000 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vmaxud: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f1f2f3f4f5f6f7f8
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> f9fafbfcfefdfeff
vmaxud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vmaxud: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> ffff000000000000
+vmaxud: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vmaxud: 00007fffffffffff @@ 0102030405060708 ==> 0102030405060708
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> ffff000000000000
+vmaxud: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> ffff000000000000
+vmaxud: 00007fffffffffff @@ 00007fffffffffff ==> 00007fffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vmaxud: 00007fffffffffff @@ 0000800000000000 ==> 0000800000000000
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vmaxud: 0000800000000000 @@ 0102030405060708 ==> 0102030405060708
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vmaxud: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vmaxud: 0000800000000000 @@ 00007fffffffffff ==> 0000800000000000
+ 0000000000000000 @@ ffff000000000000 ==> ffff000000000000
+vmaxud: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vmaxsd: 0102030405060708 @@ 0102030405060708 ==> 0102030405060708
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
vmaxsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0102030405060708
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 090a0b0c0e0d0e0f
+vmaxsd: 0102030405060708 @@ 00007fffffffffff ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090a0b0c0e0d0e0f
+vmaxsd: 0102030405060708 @@ 0000800000000000 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vmaxsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0102030405060708
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
vmaxsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vmaxsd: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 00007fffffffffff
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> ffff000000000000
+vmaxsd: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 0000800000000000
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 0000000000000000
+vmaxsd: 00007fffffffffff @@ 0102030405060708 ==> 0102030405060708
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vmaxsd: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 00007fffffffffff
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> ffff000000000000
+vmaxsd: 00007fffffffffff @@ 00007fffffffffff ==> 00007fffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vmaxsd: 00007fffffffffff @@ 0000800000000000 ==> 0000800000000000
+ ffff000000000000 @@ 0000000000000000 ==> 0000000000000000
+vmaxsd: 0000800000000000 @@ 0102030405060708 ==> 0102030405060708
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vmaxsd: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000800000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vmaxsd: 0000800000000000 @@ 00007fffffffffff ==> 0000800000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vmaxsd: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vminud: 0102030405060708 @@ 0102030405060708 ==> 0102030405060708
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
vminud: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0102030405060708
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 090a0b0c0e0d0e0f
+vminud: 0102030405060708 @@ 00007fffffffffff ==> 00007fffffffffff
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090a0b0c0e0d0e0f
+vminud: 0102030405060708 @@ 0000800000000000 ==> 0000800000000000
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 0000000000000000
vminud: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0102030405060708
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
vminud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vminud: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 00007fffffffffff
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fafbfcfefdfeff
+vminud: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 0000800000000000
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 0000000000000000
+vminud: 00007fffffffffff @@ 0102030405060708 ==> 00007fffffffffff
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vminud: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 00007fffffffffff
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vminud: 00007fffffffffff @@ 00007fffffffffff ==> 00007fffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vminud: 00007fffffffffff @@ 0000800000000000 ==> 00007fffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> 0000000000000000
+vminud: 0000800000000000 @@ 0102030405060708 ==> 0000800000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vminud: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000800000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vminud: 0000800000000000 @@ 00007fffffffffff ==> 00007fffffffffff
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vminud: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vminsd: 0102030405060708 @@ 0102030405060708 ==> 0102030405060708
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
vminsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vminsd: 0102030405060708 @@ 00007fffffffffff ==> 00007fffffffffff
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> ffff000000000000
+vminsd: 0102030405060708 @@ 0000800000000000 ==> 0000800000000000
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 0000000000000000
vminsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f1f2f3f4f5f6f7f8
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> f9fafbfcfefdfeff
vminsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vminsd: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fafbfcfefdfeff
+vminsd: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vminsd: 00007fffffffffff @@ 0102030405060708 ==> 00007fffffffffff
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> ffff000000000000
+vminsd: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vminsd: 00007fffffffffff @@ 00007fffffffffff ==> 00007fffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vminsd: 00007fffffffffff @@ 0000800000000000 ==> 00007fffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vminsd: 0000800000000000 @@ 0102030405060708 ==> 0000800000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vminsd: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vminsd: 0000800000000000 @@ 00007fffffffffff ==> 00007fffffffffff
+ 0000000000000000 @@ ffff000000000000 ==> ffff000000000000
+vminsd: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vcmpequd: 0102030405060708 @@ 0102030405060708 ==> ffffffffffffffff
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
vcmpequd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpequd: 0102030405060708 @@ 00007fffffffffff ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 0000000000000000
+vcmpequd: 0102030405060708 @@ 0000800000000000 ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 0000000000000000
vcmpequd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0000000000000000
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0000000000000000
vcmpequd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vcmpequd: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 0000000000000000
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 0000000000000000
+vcmpequd: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 0000000000000000
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 0000000000000000
+vcmpequd: 00007fffffffffff @@ 0102030405060708 ==> 0000000000000000
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vcmpequd: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpequd: 00007fffffffffff @@ 00007fffffffffff ==> ffffffffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffffffffffffffff
+vcmpequd: 00007fffffffffff @@ 0000800000000000 ==> 0000000000000000
+ ffff000000000000 @@ 0000000000000000 ==> 0000000000000000
+vcmpequd: 0000800000000000 @@ 0102030405060708 ==> 0000000000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vcmpequd: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpequd: 0000800000000000 @@ 00007fffffffffff ==> 0000000000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vcmpequd: 0000800000000000 @@ 0000800000000000 ==> ffffffffffffffff
+ 0000000000000000 @@ 0000000000000000 ==> ffffffffffffffff
vcmpgtud: 0102030405060708 @@ 0102030405060708 ==> 0000000000000000
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000000000000000
vcmpgtud: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpgtud: 0102030405060708 @@ 00007fffffffffff ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 0000000000000000
+vcmpgtud: 0102030405060708 @@ 0000800000000000 ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> ffffffffffffffff
vcmpgtud: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> ffffffffffffffff
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
vcmpgtud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpgtud: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 0000000000000000
+vcmpgtud: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> ffffffffffffffff
+vcmpgtud: 00007fffffffffff @@ 0102030405060708 ==> 0000000000000000
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
+vcmpgtud: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vcmpgtud: 00007fffffffffff @@ 00007fffffffffff ==> 0000000000000000
+ ffff000000000000 @@ ffff000000000000 ==> 0000000000000000
+vcmpgtud: 00007fffffffffff @@ 0000800000000000 ==> 0000000000000000
+ ffff000000000000 @@ 0000000000000000 ==> ffffffffffffffff
+vcmpgtud: 0000800000000000 @@ 0102030405060708 ==> 0000000000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vcmpgtud: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpgtud: 0000800000000000 @@ 00007fffffffffff ==> ffffffffffffffff
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vcmpgtud: 0000800000000000 @@ 0000800000000000 ==> 0000000000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vcmpgtsd: 0102030405060708 @@ 0102030405060708 ==> 0000000000000000
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000000000000000
vcmpgtsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vcmpgtsd: 0102030405060708 @@ 00007fffffffffff ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> ffffffffffffffff
+vcmpgtsd: 0102030405060708 @@ 0000800000000000 ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> ffffffffffffffff
vcmpgtsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0000000000000000
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0000000000000000
vcmpgtsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpgtsd: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 0000000000000000
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 0000000000000000
+vcmpgtsd: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 0000000000000000
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 0000000000000000
+vcmpgtsd: 00007fffffffffff @@ 0102030405060708 ==> 0000000000000000
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vcmpgtsd: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vcmpgtsd: 00007fffffffffff @@ 00007fffffffffff ==> 0000000000000000
+ ffff000000000000 @@ ffff000000000000 ==> 0000000000000000
+vcmpgtsd: 00007fffffffffff @@ 0000800000000000 ==> 0000000000000000
+ ffff000000000000 @@ 0000000000000000 ==> 0000000000000000
+vcmpgtsd: 0000800000000000 @@ 0102030405060708 ==> 0000000000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vcmpgtsd: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vcmpgtsd: 0000800000000000 @@ 00007fffffffffff ==> ffffffffffffffff
+ 0000000000000000 @@ ffff000000000000 ==> ffffffffffffffff
+vcmpgtsd: 0000800000000000 @@ 0000800000000000 ==> 0000000000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vrld: 0102030405060708 @@ 0102030405060708 ==> 0203040506070801
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0586070687078485
vrld: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0801020304050607
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 8485058607068707
+vrld: 0102030405060708 @@ 00007fffffffffff ==> 0081018202830384
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090a0b0c0e0d0e0f
+vrld: 0102030405060708 @@ 0000800000000000 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vrld: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f2f3f4f5f6f7f8f1
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 7dfe7f7eff7ffcfd
vrld: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f8f1f2f3f4f5f6f7
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> fcfd7dfe7f7eff7f
+vrld: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 78f979fa7afb7bfc
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fafbfcfefdfeff
+vrld: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vrld: 00007fffffffffff @@ 0102030405060708 ==> 007fffffffffff00
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 8000000000007fff
+vrld: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> ff00007fffffffff
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 7fff800000000000
+vrld: 00007fffffffffff @@ 00007fffffffffff ==> 80003fffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vrld: 00007fffffffffff @@ 0000800000000000 ==> 00007fffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vrld: 0000800000000000 @@ 0102030405060708 ==> 0080000000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vrld: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000008000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vrld: 0000800000000000 @@ 00007fffffffffff ==> 0000400000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vrld: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vsld: 0102030405060708 @@ 0102030405060708 ==> 0203040506070800
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0586070687078000
vsld: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0800000000000000
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 8000000000000000
+vsld: 0102030405060708 @@ 00007fffffffffff ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090a0b0c0e0d0e0f
+vsld: 0102030405060708 @@ 0000800000000000 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vsld: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f2f3f4f5f6f7f800
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 7dfe7f7eff7f8000
vsld: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f800000000000000
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 8000000000000000
+vsld: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 0000000000000000
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fafbfcfefdfeff
+vsld: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vsld: 00007fffffffffff @@ 0102030405060708 ==> 007fffffffffff00
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 8000000000000000
+vsld: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> ff00000000000000
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsld: 00007fffffffffff @@ 00007fffffffffff ==> 8000000000000000
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vsld: 00007fffffffffff @@ 0000800000000000 ==> 00007fffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vsld: 0000800000000000 @@ 0102030405060708 ==> 0080000000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vsld: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsld: 0000800000000000 @@ 00007fffffffffff ==> 0000000000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vsld: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vsrad: 0102030405060708 @@ 0102030405060708 ==> 0001020304050607
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000121416181c1a
vsrad: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000001
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsrad: 0102030405060708 @@ 00007fffffffffff ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090a0b0c0e0d0e0f
+vsrad: 0102030405060708 @@ 0000800000000000 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vsrad: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> fff1f2f3f4f5f6f7
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> fffff3f5f7f9fdfb
vsrad: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> fffffffffffffff1
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vsrad: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fafbfcfefdfeff
+vsrad: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vsrad: 00007fffffffffff @@ 0102030405060708 ==> 0000007fffffffff
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> fffffffe00000000
+vsrad: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vsrad: 00007fffffffffff @@ 00007fffffffffff ==> 0000000000000000
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vsrad: 00007fffffffffff @@ 0000800000000000 ==> 00007fffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vsrad: 0000800000000000 @@ 0102030405060708 ==> 0000008000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vsrad: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsrad: 0000800000000000 @@ 00007fffffffffff ==> 0000000000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vsrad: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vsrd: 0102030405060708 @@ 0102030405060708 ==> 0001020304050607
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000121416181c1a
vsrd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000001
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsrd: 0102030405060708 @@ 00007fffffffffff ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090a0b0c0e0d0e0f
+vsrd: 0102030405060708 @@ 0000800000000000 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vsrd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 00f1f2f3f4f5f6f7
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0001f3f5f7f9fdfb
vsrd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 00000000000000f1
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0000000000000001
+vsrd: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 0000000000000001
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fafbfcfefdfeff
+vsrd: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vsrd: 00007fffffffffff @@ 0102030405060708 ==> 0000007fffffffff
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 0001fffe00000000
+vsrd: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000001
+vsrd: 00007fffffffffff @@ 00007fffffffffff ==> 0000000000000000
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vsrd: 00007fffffffffff @@ 0000800000000000 ==> 00007fffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vsrd: 0000800000000000 @@ 0102030405060708 ==> 0000008000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vsrd: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsrd: 0000800000000000 @@ 00007fffffffffff ==> 0000000000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vsrd: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vpkudum: Inputs: 05060708 0e0d0e0f 05060708 0e0d0e0f
Output: 05060708 0e0d0e0f 05060708 0e0d0e0f
vpkudum: Inputs: 05060708 0e0d0e0f f5f6f7f8 fefdfeff
Output: 05060708 0e0d0e0f f5f6f7f8 fefdfeff
+vpkudum: Inputs: 05060708 0e0d0e0f ffffffff 00000000
+ Output: 05060708 0e0d0e0f ffffffff 00000000
+vpkudum: Inputs: 05060708 0e0d0e0f 00000000 00000000
+ Output: 05060708 0e0d0e0f 00000000 00000000
vpkudum: Inputs: f5f6f7f8 fefdfeff 05060708 0e0d0e0f
Output: f5f6f7f8 fefdfeff 05060708 0e0d0e0f
vpkudum: Inputs: f5f6f7f8 fefdfeff f5f6f7f8 fefdfeff
Output: f5f6f7f8 fefdfeff f5f6f7f8 fefdfeff
+vpkudum: Inputs: f5f6f7f8 fefdfeff ffffffff 00000000
+ Output: f5f6f7f8 fefdfeff ffffffff 00000000
+vpkudum: Inputs: f5f6f7f8 fefdfeff 00000000 00000000
+ Output: f5f6f7f8 fefdfeff 00000000 00000000
+vpkudum: Inputs: ffffffff 00000000 05060708 0e0d0e0f
+ Output: ffffffff 00000000 05060708 0e0d0e0f
+vpkudum: Inputs: ffffffff 00000000 f5f6f7f8 fefdfeff
+ Output: ffffffff 00000000 f5f6f7f8 fefdfeff
+vpkudum: Inputs: ffffffff 00000000 ffffffff 00000000
+ Output: ffffffff 00000000 ffffffff 00000000
+vpkudum: Inputs: ffffffff 00000000 00000000 00000000
+ Output: ffffffff 00000000 00000000 00000000
+vpkudum: Inputs: 00000000 00000000 05060708 0e0d0e0f
+ Output: 00000000 00000000 05060708 0e0d0e0f
+vpkudum: Inputs: 00000000 00000000 f5f6f7f8 fefdfeff
+ Output: 00000000 00000000 f5f6f7f8 fefdfeff
+vpkudum: Inputs: 00000000 00000000 ffffffff 00000000
+ Output: 00000000 00000000 ffffffff 00000000
+vpkudum: Inputs: 00000000 00000000 00000000 00000000
+ Output: 00000000 00000000 00000000 00000000
vpmsumd: 0102030405060708 @@ 0102030405060708 ==> 0040004000400040
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0045004500410015
vpmsumd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 07c007c006d00735
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> a260a260a374a2c5
+vpmsumd: 0102030405060708 @@ 00007fffffffffff ==> 07060182fc7efe7f
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 0478fefc030202f8
+vpmsumd: 0102030405060708 @@ 0000800000000000 ==> 0000008101820283
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 0384000000000000
vpmsumd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 07c007c006d00735
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> a260a260a374a2c5
vpmsumd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0040004000400040
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0045004500410015
+vpmsumd: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 575629aad456d657
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 2c50aeac535252a8
+vpmsumd: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 000078f979fa7afb
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 7bfc000000000000
+vpmsumd: 00007fffffffffff @@ 0102030405060708 ==> 07060182fc7efe7f
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 0478fefc030202f8
+vpmsumd: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 575629aad456d657
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 2c50aeac535252a8
+vpmsumd: 00007fffffffffff @@ 00007fffffffffff ==> 5555555515555555
+ ffff000000000000 @@ ffff000000000000 ==> 5555555555555555
+vpmsumd: 00007fffffffffff @@ 0000800000000000 ==> 000000003fffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff800000000000
+vpmsumd: 0000800000000000 @@ 0102030405060708 ==> 0000008101820283
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0384000000000000
+vpmsumd: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 000078f979fa7afb
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 7bfc000000000000
+vpmsumd: 0000800000000000 @@ 00007fffffffffff ==> 000000003fffffff
+ 0000000000000000 @@ ffff000000000000 ==> ffff800000000000
+vpmsumd: 0000800000000000 @@ 0000800000000000 ==> 0000000040000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vnand: 0102030405060708 @@ 0102030405060708 ==> fefdfcfbfaf9f8f7
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> f6f5f4f3f1f2f1f0
vnand: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> fefdfcfbfaf9f8f7
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> f6f5f4f3f1f2f1f0
+vnand: 0102030405060708 @@ 00007fffffffffff ==> fffffcfbfaf9f8f7
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> f6f5ffffffffffff
+vnand: 0102030405060708 @@ 0000800000000000 ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> ffffffffffffffff
vnand: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> fefdfcfbfaf9f8f7
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> f6f5f4f3f1f2f1f0
vnand: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0e0d0c0b0a090807
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0605040301020100
+vnand: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> ffff8c0b0a090807
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 0605ffffffffffff
+vnand: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> ffff7fffffffffff
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> ffffffffffffffff
+vnand: 00007fffffffffff @@ 0102030405060708 ==> fffffcfbfaf9f8f7
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> f6f5ffffffffffff
+vnand: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> ffff8c0b0a090807
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 0605ffffffffffff
+vnand: 00007fffffffffff @@ 00007fffffffffff ==> ffff800000000000
+ ffff000000000000 @@ ffff000000000000 ==> 0000ffffffffffff
+vnand: 00007fffffffffff @@ 0000800000000000 ==> ffffffffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffffffffffffffff
+vnand: 0000800000000000 @@ 0102030405060708 ==> ffffffffffffffff
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
+vnand: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> ffff7fffffffffff
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vnand: 0000800000000000 @@ 00007fffffffffff ==> ffffffffffffffff
+ 0000000000000000 @@ ffff000000000000 ==> ffffffffffffffff
+vnand: 0000800000000000 @@ 0000800000000000 ==> ffff7fffffffffff
+ 0000000000000000 @@ 0000000000000000 ==> ffffffffffffffff
vorc: 0102030405060708 @@ 0102030405060708 ==> ffffffffffffffff
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
vorc: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0f0f0f0f0f0f0f0f
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0f0f0f0f0f0f0f0f
+vorc: 0102030405060708 @@ 00007fffffffffff ==> ffff830405060708
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090affffffffffff
+vorc: 0102030405060708 @@ 0000800000000000 ==> ffff7fffffffffff
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> ffffffffffffffff
vorc: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> ffffffffffffffff
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
vorc: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vorc: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> fffff3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9faffffffffffff
+vorc: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> ffffffffffffffff
+vorc: 00007fffffffffff @@ 0102030405060708 ==> fefdffffffffffff
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> fffff4f3f1f2f1f0
+vorc: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0e0d7fffffffffff
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> ffff040301020100
+vorc: 00007fffffffffff @@ 00007fffffffffff ==> ffffffffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffffffffffffffff
+vorc: 00007fffffffffff @@ 0000800000000000 ==> ffff7fffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffffffffffffffff
+vorc: 0000800000000000 @@ 0102030405060708 ==> fefdfcfbfaf9f8f7
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> f6f5f4f3f1f2f1f0
+vorc: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0e0d8c0b0a090807
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0605040301020100
+vorc: 0000800000000000 @@ 00007fffffffffff ==> ffff800000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000ffffffffffff
+vorc: 0000800000000000 @@ 0000800000000000 ==> ffffffffffffffff
+ 0000000000000000 @@ 0000000000000000 ==> ffffffffffffffff
veqv: 0102030405060708 @@ 0102030405060708 ==> ffffffffffffffff
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
veqv: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0f0f0f0f0f0f0f0f
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0f0f0f0f0f0f0f0f
+veqv: 0102030405060708 @@ 00007fffffffffff ==> fefd830405060708
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090af4f3f1f2f1f0
+veqv: 0102030405060708 @@ 0000800000000000 ==> fefd7cfbfaf9f8f7
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> f6f5f4f3f1f2f1f0
veqv: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0f0f0f0f0f0f0f0f
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0f0f0f0f0f0f0f0f
veqv: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+veqv: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 0e0d73f4f5f6f7f8
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fa040301020100
+veqv: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 0e0d8c0b0a090807
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 0605040301020100
+veqv: 00007fffffffffff @@ 0102030405060708 ==> fefd830405060708
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 090af4f3f1f2f1f0
+veqv: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0e0d73f4f5f6f7f8
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> f9fa040301020100
+veqv: 00007fffffffffff @@ 00007fffffffffff ==> ffffffffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffffffffffffffff
+veqv: 00007fffffffffff @@ 0000800000000000 ==> ffff000000000000
+ ffff000000000000 @@ 0000000000000000 ==> 0000ffffffffffff
+veqv: 0000800000000000 @@ 0102030405060708 ==> fefd7cfbfaf9f8f7
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> f6f5f4f3f1f2f1f0
+veqv: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0e0d8c0b0a090807
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0605040301020100
+veqv: 0000800000000000 @@ 00007fffffffffff ==> ffff000000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000ffffffffffff
+veqv: 0000800000000000 @@ 0000800000000000 ==> ffffffffffffffff
+ 0000000000000000 @@ 0000000000000000 ==> ffffffffffffffff
vcipher: 0102030405060708 @@ 0102030405060708 ==> 15abdc2823b74b86
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 22037bc3e1e25abc
vcipher: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> e55b2cd8d347bb76
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> d2f38b331112aa4c
+vcipher: 0102030405060708 @@ 00007fffffffffff ==> 14a9a0d3d94eb371
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> d4f670cfefef54b3
+vcipher: 0102030405060708 @@ 0000800000000000 ==> 14a95f2c26b14c8e
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 2b0970cfefef54b3
vcipher: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 8720c49da1d37bca
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 906d1f673bb72743
vcipher: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 77d0346d51238b3a
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 609def97cb47d7b3
+vcipher: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 8622b8665b2a833d
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 6698146b35ba294c
+vcipher: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 86224799a4d57cc2
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 9967146b35ba294c
+vcipher: 00007fffffffffff @@ 0102030405060708 ==> fd8b1512668ffb6b
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 44a1fbab18f18719
+vcipher: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0d7be5e2967f0b9b
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> b4510b5be80177e9
+vcipher: 00007fffffffffff @@ 00007fffffffffff ==> fc8969e99c76039c
+ ffff000000000000 @@ ffff000000000000 ==> b254f0a716fc8916
+vcipher: 00007fffffffffff @@ 0000800000000000 ==> fc8996166389fc63
+ ffff000000000000 @@ 0000000000000000 ==> 4dabf0a716fc8916
+vcipher: 0000800000000000 @@ 0102030405060708 ==> 626160676665646b
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> c4802fc16d6e6d6c
+vcipher: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 929190979695949b
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 3470df319d9e9d9c
+vcipher: 0000800000000000 @@ 00007fffffffffff ==> 63631c9c9c9c9c9c
+ 0000000000000000 @@ ffff000000000000 ==> 327524cd63636363
+vcipher: 0000800000000000 @@ 0000800000000000 ==> 6363e36363636363
+ 0000000000000000 @@ 0000000000000000 ==> cd8a24cd63636363
vcipherlast: 0102030405060708 @@ 0102030405060708 ==> 7d6d28726e61acfa
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 08dd703ca57acbf1
vcipherlast: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 8d9dd8829e915c0a
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> f82d80cc558a3b01
+vcipherlast: 0102030405060708 @@ 00007fffffffffff ==> 7c6f54899498540d
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> fe287b30ab77c5fe
+vcipherlast: 0102030405060708 @@ 0000800000000000 ==> 7c6fab766b67abf2
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 01d77b30ab77c5fe
vcipherlast: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> a0400c12e32bbcb7
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 905e064db58466bf
vcipherlast: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 50b0fce213db4c47
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 60aef6bd4574964f
+vcipherlast: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> a14270e919d24440
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 66ab0d41bb8968b0
+vcipherlast: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> a1428f16e62dbbbf
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 99540d41bb8968b0
+vcipherlast: 00007fffffffffff @@ 0102030405060708 ==> 621460671310641e
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 1f69d91a6d6e186c
+vcipherlast: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 92e49097e3e094ee
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> ef9929ea9d9ee89c
+vcipherlast: 00007fffffffffff @@ 00007fffffffffff ==> 63161c9ce9e99ce9
+ ffff000000000000 @@ ffff000000000000 ==> e99cd21663631663
+vcipherlast: 00007fffffffffff @@ 0000800000000000 ==> 6316e36316166316
+ ffff000000000000 @@ 0000000000000000 ==> 1663d21663631663
+vcipherlast: 0000800000000000 @@ 0102030405060708 ==> 626160676665646b
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 6a69c66f6d6e6d6c
+vcipherlast: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 929190979695949b
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 9a99369f9d9e9d9c
+vcipherlast: 0000800000000000 @@ 00007fffffffffff ==> 63631c9c9c9c9c9c
+ 0000000000000000 @@ ffff000000000000 ==> 9c9ccd6363636363
+vcipherlast: 0000800000000000 @@ 0000800000000000 ==> 6363e36363636363
+ 0000000000000000 @@ 0000000000000000 ==> 6363cd6363636363
vncipher: 0102030405060708 @@ 0102030405060708 ==> fe67ce881a80f569
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 19db0b0605541639
vncipher: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0e973e78ea700599
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> e92bfbf6f5a4e6c9
+vncipher: 0102030405060708 @@ 00007fffffffffff ==> de98809d822f77d0
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 1424f3081f45082e
+vncipher: 0102030405060708 @@ 0000800000000000 ==> 0facae567dd0882f
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 3aef223c1f45082e
vncipher: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 8b10c2d5607a5569
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 581826de46277b9c
vncipher: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 7be03225908aa599
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> a8e8d62eb6d78b6c
+vncipher: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> abef8cc0f8d5d7d0
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 55e7ded05c36658b
+vncipher: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 7adba20b072a282f
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 7b2c0fe45c36658b
+vncipher: 00007fffffffffff @@ 0102030405060708 ==> 359e61e1b44edf06
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> ec338260e6209378
+vncipher: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> c56e911144be2ff6
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 1cc3729016d06388
+vncipher: 00007fffffffffff @@ 00007fffffffffff ==> 15612ff42ce15dbf
+ ffff000000000000 @@ ffff000000000000 ==> e1cc7a6efc318d6f
+vncipher: 00007fffffffffff @@ 0000800000000000 ==> c455013fd31ea240
+ ffff000000000000 @@ 0000000000000000 ==> cf07ab5afc318d6f
+vncipher: 0000800000000000 @@ 0102030405060708 ==> 796e736035022f14
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> cfb37d6d48434c45
+vncipher: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 899e8390c5f2dfe4
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 3f438d9db8b3bcb5
+vncipher: 0000800000000000 @@ 00007fffffffffff ==> 59913d75adadadad
+ 0000000000000000 @@ ffff000000000000 ==> c24c856352525252
+vncipher: 0000800000000000 @@ 0000800000000000 ==> 88a513be52525252
+ 0000000000000000 @@ 0000000000000000 ==> ec87545752525252
vncipherlast: 0102030405060708 @@ 0102030405060708 ==> 08f19dbb336cd089
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 49afdef7d9ae363f
vncipherlast: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> f8016d4bc39c2079
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> b95f2e07295ec6cf
+vncipherlast: 0102030405060708 @@ 00007fffffffffff ==> 09f3e140c995287e
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> bf5ad5fbd7a33830
+vncipherlast: 0102030405060708 @@ 0000800000000000 ==> 09f31ebf366ad781
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 40a5d5fbd7a33830
vncipherlast: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 2a2360e572020b5d
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 60dc7571021928b5
vncipherlast: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> dad3901582f2fbad
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 902c8581f2e9d845
+vncipherlast: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 2b211c1e88fbf3aa
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 96297e7d0c1426ba
+vncipherlast: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 2b21e3e177040c55
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 69d67e7d0c1426ba
+vncipherlast: 00007fffffffffff @@ 0102030405060708 ==> 535051797854555a
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 7477605e5c707372
+vncipherlast: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> a3a0a18988a4a5aa
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 848790aeac808382
+vncipherlast: 00007fffffffffff @@ 00007fffffffffff ==> 52522d8282adadad
+ ffff000000000000 @@ ffff000000000000 ==> 82826b52527d7d7d
+vncipherlast: 00007fffffffffff @@ 0000800000000000 ==> 5252d27d7d525252
+ ffff000000000000 @@ 0000000000000000 ==> 7d7d6b52527d7d7d
+vncipherlast: 0000800000000000 @@ 0102030405060708 ==> 535051565754555a
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 5b58315e5c5f5c5d
+vncipherlast: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> a3a0a1a6a7a4a5aa
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> aba8c1aeacafacad
+vncipherlast: 0000800000000000 @@ 00007fffffffffff ==> 52522dadadadadad
+ 0000000000000000 @@ ffff000000000000 ==> adad3a5252525252
+vncipherlast: 0000800000000000 @@ 0000800000000000 ==> 5252d25252525252
+ 0000000000000000 @@ 0000000000000000 ==> 52523a5252525252
vmulouw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 00193c6aa4917040 00c56e34124ba4e1
vmulouw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 04d39d63184f87c0 0dfee4d8b9c6e2f1
@@ -300,6 +853,14 @@
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> fbfafdfffffcfffe
vpermxor: 0102030405060708 @@ f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> fdfcfbfaf9f8f7f6
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f5f4f3f1f1f2f1f0
+vpermxor: 0102030405060708 @@ 00007fffffffffff @@ 0102030405060708 ==> 017efefefefefefe
+ 090a0b0c0e0d0e0f @@ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> fe01010101010101
+vpermxor: 0102030405060708 @@ 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0f70f0f0f0f0f0f0
+ 090a0b0c0e0d0e0f @@ ffff000000000000 @@ f9fafbfcfefdfeff ==> f00f0f0f0f0f0f0f
+vpermxor: 0102030405060708 @@ 0000800000000000 @@ 0102030405060708 ==> 0181010101010101
+ 090a0b0c0e0d0e0f @@ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0101010101010101
+vpermxor: 0102030405060708 @@ 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0f8f0f0f0f0f0f0f
+ 090a0b0c0e0d0e0f @@ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0f0f0f0f0f0f0f0f
vpermxor: f1f2f3f4f5f6f7f8 @@ 0102030405060708 @@ 0102030405060708 ==> f3f2f5f4f7f6f9f8
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> fbfafdfffffcfffe
vpermxor: f1f2f3f4f5f6f7f8 @@ 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> fdfcfbfaf9f8f7f6
@@ -308,36 +869,96 @@
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0b0a0d0f0f0c0f0e
vpermxor: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0d0c0b0a09080706
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0504030101020100
+vpermxor: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff @@ 0102030405060708 ==> f18e0e0e0e0e0e0e
+ f9fafbfcfefdfeff @@ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 0ef1f1f1f1f1f1f1
+vpermxor: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> ff80000000000000
+ f9fafbfcfefdfeff @@ ffff000000000000 @@ f9fafbfcfefdfeff ==> 00ffffffffffffff
+vpermxor: f1f2f3f4f5f6f7f8 @@ 0000800000000000 @@ 0102030405060708 ==> f171f1f1f1f1f1f1
+ f9fafbfcfefdfeff @@ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> f1f1f1f1f1f1f1f1
+vpermxor: f1f2f3f4f5f6f7f8 @@ 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> ff7fffffffffffff
+ f9fafbfcfefdfeff @@ 0000000000000000 @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vpermxor: 00007fffffffffff @@ 0102030405060708 @@ 0102030405060708 ==> 0203040506070809
+ ffff000000000000 @@ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0a0b0c0e0e0d0e0f
+vpermxor: 00007fffffffffff @@ 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0203040506070809
+ ffff000000000000 @@ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0a0b0c0e0e0d0e0f
+vpermxor: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f2f3f4f5f6f7f8f9
+ ffff000000000000 @@ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> fafbfcfefefdfeff
+vpermxor: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f2f3f4f5f6f7f8f9
+ ffff000000000000 @@ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> fafbfcfefefdfeff
+vpermxor: 00007fffffffffff @@ 00007fffffffffff @@ 0102030405060708 ==> 007fffffffffffff
+ ffff000000000000 @@ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> ff00000000000000
+vpermxor: 00007fffffffffff @@ 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 007fffffffffffff
+ ffff000000000000 @@ ffff000000000000 @@ f9fafbfcfefdfeff ==> ff00000000000000
+vpermxor: 00007fffffffffff @@ 0000800000000000 @@ 0102030405060708 ==> 0080000000000000
+ ffff000000000000 @@ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vpermxor: 00007fffffffffff @@ 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0080000000000000
+ ffff000000000000 @@ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vpermxor: 0000800000000000 @@ 0102030405060708 @@ 0102030405060708 ==> 0203040506070809
+ 0000000000000000 @@ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0a0b0c0e0e0d0e0f
+vpermxor: 0000800000000000 @@ 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0203040506070809
+ 0000000000000000 @@ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0a0b0c0e0e0d0e0f
+vpermxor: 0000800000000000 @@ f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f2f3f4f5f6f7f8f9
+ 0000000000000000 @@ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> fafbfcfefefdfeff
+vpermxor: 0000800000000000 @@ f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f2f3f4f5f6f7f8f9
+ 0000000000000000 @@ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> fafbfcfefefdfeff
+vpermxor: 0000800000000000 @@ 00007fffffffffff @@ 0102030405060708 ==> 007fffffffffffff
+ 0000000000000000 @@ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> ff00000000000000
+vpermxor: 0000800000000000 @@ 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 007fffffffffffff
+ 0000000000000000 @@ ffff000000000000 @@ f9fafbfcfefdfeff ==> ff00000000000000
+vpermxor: 0000800000000000 @@ 0000800000000000 @@ 0102030405060708 ==> 0080000000000000
+ 0000000000000000 @@ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vpermxor: 0000800000000000 @@ 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0080000000000000
+ 0000000000000000 @@ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
vclzb: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 07060605050505040404040404040404
vclzb: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+vclzb: 00007fffffffffff @@ ffff000000000000 ==> 08080100000000000000080808080808
+vclzb: 0000800000000000 @@ 0000000000000000 ==> 08080008080808080808080808080808
vclzw: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 00000007000000050000000400000004
vclzw: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+vclzw: 00007fffffffffff @@ ffff000000000000 ==> 00000011000000000000000000000020
+vclzw: 0000800000000000 @@ 0000000000000000 ==> 00000010000000200000002000000020
vclzh: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 00070006000500050004000400040004
vclzh: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+vclzh: 00007fffffffffff @@ ffff000000000000 ==> 00100001000000000000001000100010
+vclzh: 0000800000000000 @@ 0000000000000000 ==> 00100000001000100010001000100010
vclzd: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 00000000000000070000000000000004
vclzd: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+vclzd: 00007fffffffffff @@ ffff000000000000 ==> 00000000000000110000000000000000
+vclzd: 0000800000000000 @@ 0000000000000000 ==> 00000000000000100000000000000040
vpopcntb: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 01010201020203010202030203030304
vpopcntb: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 05050605060607050606070607070708
+vpopcntb: 00007fffffffffff @@ ffff000000000000 ==> 00000708080808080808000000000000
+vpopcntb: 0000800000000000 @@ 0000000000000000 ==> 00000100000000000000000000000000
vpopcnth: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 00020003000400040004000500060007
vpopcnth: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 000a000b000c000c000c000d000e000f
+vpopcnth: 00007fffffffffff @@ ffff000000000000 ==> 0000000f001000100010000000000000
+vpopcnth: 0000800000000000 @@ 0000000000000000 ==> 00000001000000000000000000000000
vpopcntw: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 0000000500000008000000090000000d
vpopcntw: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 0000001500000018000000190000001d
+vpopcntw: 00007fffffffffff @@ ffff000000000000 ==> 0000000f000000200000001000000000
+vpopcntw: 0000800000000000 @@ 0000000000000000 ==> 00000001000000000000000000000000
vpopcntd: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 000000000000000d0000000000000016
vpopcntd: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 000000000000002d0000000000000036
+vpopcntd: 00007fffffffffff @@ ffff000000000000 ==> 000000000000002f0000000000000010
+vpopcntd: 0000800000000000 @@ 0000000000000000 ==> 00000000000000010000000000000000
vsbox: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 7c777bf26b6fc53001672bfeabd7ab76
vsbox: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> a1890dbfe6426841992d0fb0bb54bb16
+vsbox: 00007fffffffffff @@ ffff000000000000 ==> 6363d216161616161616636363636363
+vsbox: 0000800000000000 @@ 0000000000000000 ==> 6363cd63636363636363636363636363
vgbbd: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 00000000011e66aa00000000ff1f6ba5
vgbbd: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> ffffffff011e66aaffffffffff1f6ba5
+vgbbd: 00007fffffffffff @@ ffff000000000000 ==> 1f3f3f3f3f3f3f3fc0c0c0c0c0c0c0c0
+vgbbd: 0000800000000000 @@ 0000000000000000 ==> 20000000000000000000000000000000
vshasigmad: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 088207870e8c098d || 8b9e1b9b13149015
vshasigmad: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> c8f5100c7844a0fc || e9b5916d0131c581
@@ -347,6 +968,14 @@
vshasigmad: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 52af4a56221efaa6 || 73efcb375b6b9fdb
vshasigmad: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 8bf92f9ed2b06655 || 299d6bbd9e22f4c7
vshasigmad: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 986700cc8f5613df || 7a3f676a2ef03935
+vshasigmad: 00007fffffffffff @@ ffff000000000000 ==> 7f003f7fffffffff || 7eff810000000000
+vshasigmad: 00007fffffffffff @@ ffff000000000000 ==> fffc1e000ffffff8 || fc07e3ffe0000007
+vshasigmad: 00007fffffffffff @@ ffff000000000000 ==> fffffff03e07e0ff || 0000000fc1f03e00
+vshasigmad: 00007fffffffffff @@ ffff000000000000 ==> fffc3ffe1f80003f || 0003c003c07fff80
+vshasigmad: 0000800000000000 @@ 0000000000000000 ==> 0000418000000000 || 0000000000000000
+vshasigmad: 0000800000000000 @@ 0000000000000000 ==> 0004020010000000 || 0000000000000000
+vshasigmad: 0000800000000000 @@ 0000000000000000 ==> 0000000000082100 || 0000000000000000
+vshasigmad: 0000800000000000 @@ 0000000000000000 ==> 0000000220000040 || 0000000000000000
vshasigmaw: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 88e344269168cdae || 9bf057355c5e785e
vshasigmaw: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 41e2c021c36443a2 || 44e5c72626c5e584
@@ -356,6 +985,14 @@
vshasigmaw: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 27b89a7ba53e19f8 || 22bf9d7c409fbfde
vshasigmaw: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 6814e0ad5965f19e || 0a7682cfffbb77ab
vshasigmaw: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 54200fe9e7b2997b || 71052acc5efb57bb
+vshasigmaw: 00007fffffffffff @@ ffff000000000000 ==> e1ffcf001fffffff || de0021ff00000000
+vshasigmaw: 00007fffffffffff @@ ffff000000000000 ==> 3000601f003fffff || 603f9fc000000000
+vshasigmaw: 00007fffffffffff @@ ffff000000000000 ==> 3e07e3fcffffffff || c3f83c0700000000
+vshasigmaw: 00007fffffffffff @@ ffff000000000000 ==> 03dffe70ffffffff || fc60039f00000000
+vshasigmaw: 0000800000000000 @@ 0000000000000000 ==> 2000110000000000 || 0000000000000000
+vshasigmaw: 0000800000000000 @@ 0000000000000000 ==> 5000002000000000 || 0000000000000000
+vshasigmaw: 0000800000000000 @@ 0000000000000000 ==> 0200200400000000 || 0000000000000000
+vshasigmaw: 0000800000000000 @@ 0000000000000000 ==> 0040021000000000 || 0000000000000000
bcdadd.: 8045090189321003 || 001122334556677d @@ 8045090189321003 || 001122334556677d ==> 6090180378642006 || 002244669113354d
bcdadd.: 8045090189321003 || 001122334556677d @@ 8045090189321003 || 001122334556677d ==> 6090180378642006 || 002244669113354d
@@ -425,63 +1062,219 @@
vaddcuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 00000000000000000000000000000000
vaddcuq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
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vaddcuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 00000000000000000000000000000000
vaddcuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000001
+vaddcuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00007fffffffffffffff000000000000 ==> 00000000000000000000000000000000
+vaddcuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00008000000000000000000000000000 ==> 00000000000000000000000000000000
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vadduqm: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 020406080a0c0e10121416181c1a1c1e
vadduqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> f2f4f6f8fafcff01030507090d0b0d0e
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vadduqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> f2f4f6f8fafcff01030507090d0b0d0e
vadduqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> e3e5e7e9ebedeff1f3f5f7f9fdfbfdfe
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+vadduqm: 00008000000000000000000000000000 @@ 00008000000000000000000000000000 ==> 00010000000000000000000000000000
vsubcuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 00000000000000000000000000000001
vsubcuq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
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vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0ef
vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0
vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> ffffffffffffffffffffffffffffffff
vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 00000000000000000000000000000000
+vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> f1f273f4f5f6f7f8f9fbfbfcfefdfefe
+vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> f1f273f4f5f6f7f8f9fbfbfcfefdfeff
+vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00008000000000000000000000000000 @@ f000000000000000 ==> f1f273f4f5f6f7f8f9fafbfcfefdfefe
+vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00008000000000000000000000000000 @@ f000000000000001 ==> f1f273f4f5f6f7f8f9fafbfcfefdfeff
+vsubeuqm: 00007fffffffffffffff000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> fefe7cfbfaf9f8f7f6f4f4f3f1f2f1f0
+vsubeuqm: 00007fffffffffffffff000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> fefe7cfbfaf9f8f7f6f4f4f3f1f2f1f1
+vsubeuqm: 00007fffffffffffffff000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> 0e0d8c0b0a0908070604040301020100
+vsubeuqm: 00007fffffffffffffff000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 0e0d8c0b0a0908070604040301020101
+vsubeuqm: 00007fffffffffffffff000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> ffffffffffffffffffffffffffffffff
+vsubeuqm: 00007fffffffffffffff000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> 00000000000000000000000000000000
+vsubeuqm: 00007fffffffffffffff000000000000 @@ 00008000000000000000000000000000 @@ f000000000000000 ==> fffffffffffffffffffeffffffffffff
+vsubeuqm: 00007fffffffffffffff000000000000 @@ 00008000000000000000000000000000 @@ f000000000000001 ==> ffffffffffffffffffff000000000000
+vsubeuqm: 00008000000000000000000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> fefe7cfbfaf9f8f7f6f5f4f3f1f2f1f0
+vsubeuqm: 00008000000000000000000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> fefe7cfbfaf9f8f7f6f5f4f3f1f2f1f1
+vsubeuqm: 00008000000000000000000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> 0e0d8c0b0a0908070605040301020100
+vsubeuqm: 00008000000000000000000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 0e0d8c0b0a0908070605040301020101
+vsubeuqm: 00008000000000000000000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> 00000000000000000000ffffffffffff
+vsubeuqm: 00008000000000000000000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> 00000000000000000001000000000000
+vsubeuqm: 00008000000000000000000000000000 @@ 00008000000000000000000000000000 @@ f000000000000000 ==> ffffffffffffffffffffffffffffffff
+vsubeuqm: 00008000000000000000000000000000 @@ 00008000000000000000000000000000 @@ f000000000000001 ==> 00000000000000000000000000000000
All done. Tested 66 different instructions
diff --git a/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp-LE b/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp-LE
new file mode 100644
index 0000000..8ee724a
--- /dev/null
+++ b/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp-LE
@@ -0,0 +1,487 @@
+mfvsrd: 0102030405060708 => 0000000005060708
+mfvsrd: 090a0b0c0e0d0e0f => 000000000e0d0e0f
+mfvsrd: f1f2f3f4f5f6f7f8 => 00000000f5f6f7f8
+mfvsrd: f9fafbfcfefdfeff => 00000000fefdfeff
+
+mfvsrwz: 0102030405060708 => 0000000005060708
+mfvsrwz: 090a0b0c0e0d0e0f => 000000000e0d0e0f
+mfvsrwz: f1f2f3f4f5f6f7f8 => 00000000f5f6f7f8
+mfvsrwz: f9fafbfcfefdfeff => 00000000fefdfeff
+
+mtvsrd: 0102030405060708 => 0000000005060708
+mtvsrd: 090a0b0c0e0d0e0f => 000000000e0d0e0f
+mtvsrd: f1f2f3f4f5f6f7f8 => 00000000f5f6f7f8
+mtvsrd: f9fafbfcfefdfeff => 00000000fefdfeff
+
+mtvsrwz: 05060708 => 0000000005060708
+mtvsrwz: 0e0d0e0f => 000000000e0d0e0f
+mtvsrwz: f5f6f7f8 => 00000000f5f6f7f8
+mtvsrwz: fefdfeff => 00000000fefdfeff
+
+mtfprwa: 05060708 => 0000000005060708
+mtfprwa: 0e0d0e0f => 000000000e0d0e0f
+mtfprwa: f5f6f7f8 => fffffffff5f6f7f8
+mtfprwa: fefdfeff => fffffffffefdfeff
+
+vaddudm: 0102030405060708 @@ 0102030405060708 ==> 020406080a0c0e10
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 121416181c1a1c1e
+vaddudm: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> f2f4f6f8fafcff00
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 030507090d0b0d0e
+vaddudm: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f2f4f6f8fafcff00
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 030507090d0b0d0e
+vaddudm: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> e3e5e7e9ebedeff0
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f3f5f7f9fdfbfdfe
+
+vsubudm: 0102030405060708 @@ 0102030405060708 ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vsubudm: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0f0f0f0f0f0f0f10
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0f0f0f0f0f0f0f10
+vsubudm: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f0f0f0f0f0f0f0f0
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> f0f0f0f0f0f0f0f0
+vsubudm: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0000000000000000
+
+vmaxud: 0102030405060708 @@ 0102030405060708 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vmaxud: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vmaxud: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> f9fafbfcfefdfeff
+vmaxud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+
+vmaxsd: 0102030405060708 @@ 0102030405060708 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vmaxsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 090a0b0c0e0d0e0f
+vmaxsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0102030405060708
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vmaxsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+
+vminud: 0102030405060708 @@ 0102030405060708 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vminud: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 090a0b0c0e0d0e0f
+vminud: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0102030405060708
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vminud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+
+vminsd: 0102030405060708 @@ 0102030405060708 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vminsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vminsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> f9fafbfcfefdfeff
+vminsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+
+vcmpequd: 0102030405060708 @@ 0102030405060708 ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
+vcmpequd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpequd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0000000000000000
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vcmpequd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+
+vcmpgtud: 0102030405060708 @@ 0102030405060708 ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vcmpgtud: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpgtud: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
+vcmpgtud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0000000000000000
+
+vcmpgtsd: 0102030405060708 @@ 0102030405060708 ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vcmpgtsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vcmpgtsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0000000000000000
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vcmpgtsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0000000000000000
+
+vrld: 0102030405060708 @@ 0102030405060708 ==> 0203040506070801
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0586070687078485
+vrld: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0801020304050607
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 8485058607068707
+vrld: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f2f3f4f5f6f7f8f1
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 7dfe7f7eff7ffcfd
+vrld: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f8f1f2f3f4f5f6f7
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> fcfd7dfe7f7eff7f
+
+vsld: 0102030405060708 @@ 0102030405060708 ==> 0203040506070800
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0586070687078000
+vsld: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0800000000000000
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 8000000000000000
+vsld: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f2f3f4f5f6f7f800
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 7dfe7f7eff7f8000
+vsld: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f800000000000000
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 8000000000000000
+
+vsrad: 0102030405060708 @@ 0102030405060708 ==> 0001020304050607
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000121416181c1a
+vsrad: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000001
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsrad: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> fff1f2f3f4f5f6f7
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> fffff3f5f7f9fdfb
+vsrad: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> fffffffffffffff1
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+
+vsrd: 0102030405060708 @@ 0102030405060708 ==> 0001020304050607
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000121416181c1a
+vsrd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000001
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsrd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 00f1f2f3f4f5f6f7
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0001f3f5f7f9fdfb
+vsrd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 00000000000000f1
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0000000000000001
+
+vpkudum: Inputs: 05060708 0e0d0e0f 05060708 0e0d0e0f
+ Output: 05060708 0e0d0e0f 05060708 0e0d0e0f
+vpkudum: Inputs: 05060708 0e0d0e0f f5f6f7f8 fefdfeff
+ Output: 05060708 0e0d0e0f f5f6f7f8 fefdfeff
+vpkudum: Inputs: f5f6f7f8 fefdfeff 05060708 0e0d0e0f
+ Output: f5f6f7f8 fefdfeff 05060708 0e0d0e0f
+vpkudum: Inputs: f5f6f7f8 fefdfeff f5f6f7f8 fefdfeff
+ Output: f5f6f7f8 fefdfeff f5f6f7f8 fefdfeff
+
+vpmsumd: 0102030405060708 @@ 0102030405060708 ==> 0040004000400040
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0045004500410015
+vpmsumd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 07c007c006d00735
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> a260a260a374a2c5
+vpmsumd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 07c007c006d00735
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> a260a260a374a2c5
+vpmsumd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0040004000400040
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0045004500410015
+
+vnand: 0102030405060708 @@ 0102030405060708 ==> fefdfcfbfaf9f8f7
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> f6f5f4f3f1f2f1f0
+vnand: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> fefdfcfbfaf9f8f7
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> f6f5f4f3f1f2f1f0
+vnand: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> fefdfcfbfaf9f8f7
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> f6f5f4f3f1f2f1f0
+vnand: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0e0d0c0b0a090807
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0605040301020100
+
+vorc: 0102030405060708 @@ 0102030405060708 ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
+vorc: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0f0f0f0f0f0f0f0f
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0f0f0f0f0f0f0f0f
+vorc: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
+vorc: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+
+veqv: 0102030405060708 @@ 0102030405060708 ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
+veqv: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0f0f0f0f0f0f0f0f
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0f0f0f0f0f0f0f0f
+veqv: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0f0f0f0f0f0f0f0f
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0f0f0f0f0f0f0f0f
+veqv: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+
+vcipher: 0102030405060708 @@ 0102030405060708 ==> 15abdc2823b74b86
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 22037bc3e1e25abc
+vcipher: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> e55b2cd8d347bb76
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> d2f38b331112aa4c
+vcipher: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 8720c49da1d37bca
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 906d1f673bb72743
+vcipher: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 77d0346d51238b3a
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 609def97cb47d7b3
+
+vcipherlast: 0102030405060708 @@ 0102030405060708 ==> 7d6d28726e61acfa
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 08dd703ca57acbf1
+vcipherlast: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 8d9dd8829e915c0a
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> f82d80cc558a3b01
+vcipherlast: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> a0400c12e32bbcb7
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 905e064db58466bf
+vcipherlast: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 50b0fce213db4c47
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 60aef6bd4574964f
+
+vncipher: 0102030405060708 @@ 0102030405060708 ==> fe67ce881a80f569
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 19db0b0605541639
+vncipher: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0e973e78ea700599
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> e92bfbf6f5a4e6c9
+vncipher: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 8b10c2d5607a5569
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 581826de46277b9c
+vncipher: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 7be03225908aa599
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> a8e8d62eb6d78b6c
+
+vncipherlast: 0102030405060708 @@ 0102030405060708 ==> 08f19dbb336cd089
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 49afdef7d9ae363f
+vncipherlast: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> f8016d4bc39c2079
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> b95f2e07295ec6cf
+vncipherlast: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 2a2360e572020b5d
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 60dc7571021928b5
+vncipherlast: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> dad3901582f2fbad
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 902c8581f2e9d845
+
+vmulouw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 00193c6aa4917040 00c56e34124ba4e1
+vmulouw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 04d39d63184f87c0 0dfee4d8b9c6e2f1
+vmulouw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 04d39d63184f87c0 0dfee4d8b9c6e2f1
+vmulouw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> ec52a4e230d08040 fdfd020406050201
+
+vmuluwm: 01020304 05060708 090a0b0c 0e0d0e0f ==> 14191810a4917040 b56a0890124ba4e1
+vmuluwm: 01020304 05060708 090a0b0c 0e0d0e0f ==> 7c8fabd0184f87c0 346fa3d0b9c6e2f1
+vmuluwm: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 7c8fabd0184f87c0 346fa3d0b9c6e2f1
+vmuluwm: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 89c9209030d08040 5838201006050201
+
+vmulosw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 00193c6aa4917040 00c56e34124ba4e1
+vmulosw: 01020304 05060708 090a0b0c 0e0d0e0f ==> ffcd965b184f87c0 fff1d6c9b9c6e2f1
+vmulosw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> ffcd965b184f87c0 fff1d6c9b9c6e2f1
+vmulosw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 0064b4f230d08040 0001040606050201
+
+vmuleuw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0001040a14191810 0051b52bb56a0890
+vmuleuw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 00f3d9b37c8fabd0 08d3a173346fa3d0
+vmuleuw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 00f3d9b37c8fabd0 08d3a173346fa3d0
+vmuleuw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> e4ab55e389c92090 f41a344158382010
+
+vmulesw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0001040a14191810 0051b52bb56a0890
+vmulesw: 01020304 05060708 090a0b0c 0e0d0e0f ==> fff1d6af7c8fabd0 ffc99667346fa3d0
+vmulesw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> fff1d6af7c8fabd0 ffc99667346fa3d0
+vmulesw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 00c56dfb89c92090 00243c4958382010
+
+vmrgew: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0102030401020304 090a0b0c090a0b0c
+vmrgew: 01020304 05060708 090a0b0c 0e0d0e0f ==> 01020304f1f2f3f4 090a0b0cf9fafbfc
+vmrgew: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> f1f2f3f401020304 f9fafbfc090a0b0c
+vmrgew: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> f1f2f3f4f1f2f3f4 f9fafbfcf9fafbfc
+
+vmrgow: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0506070805060708 0e0d0e0f0e0d0e0f
+vmrgow: 01020304 05060708 090a0b0c 0e0d0e0f ==> 05060708f5f6f7f8 0e0d0e0ffefdfeff
+vmrgow: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> f5f6f7f805060708 fefdfeff0e0d0e0f
+vmrgow: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> f5f6f7f8f5f6f7f8 fefdfefffefdfeff
+
+vpmsumb: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0005001500050055 0005001500050001
+vpmsumb: 01020304 05060708 090a0b0c 0e0d0e0f ==> 011502c501150505 011502c5011500f1
+vpmsumb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 011502c501150505 011502c5011500f1
+vpmsumb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 0005001500050055 0005001500050001
+
+vpmsumh: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0004001400040054 0004001400000004
+vpmsumh: 01020304 05060708 090a0b0c 0e0d0e0f ==> 01e7c23401e045f4 01e7c2340001e1e4
+vpmsumh: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 01e7c23401e045f4 01e7c2340001e1e4
+vpmsumh: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 0004001400040054 0004001400000004
+
+vpmsumw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0010001000100050 0015001500110005
+vpmsumw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 03d003d784578410 02c5032720e32115
+vpmsumw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 03d003d784578410 02c5032720e32115
+vpmsumw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 0010001000100050 0015001500110005
+
+vpkudus: 000000007c118a2b, 00000000f1112345 @@ 000000007c118a2b, 00000000f1112345 ==> 7c118a2b f1112345 7c118a2b f1112345
+vpkudus: 000000007c118a2b, 00000000f1112345 @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> 7c118a2b f1112345 ffffffff ffffffff
+vpkudus: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 000000007c118a2b, 00000000f1112345 ==> ffffffff ffffffff 7c118a2b f1112345
+vpkudus: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> ffffffff ffffffff ffffffff ffffffff
+
+vpksdus: 000000007c118a2b, 00000000f1112345 @@ 000000007c118a2b, 00000000f1112345 ==> 7c118a2b f1112345 7c118a2b f1112345
+vpksdus: 000000007c118a2b, 00000000f1112345 @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> 7c118a2b f1112345 ffffffff 00000000
+vpksdus: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 000000007c118a2b, 00000000f1112345 ==> ffffffff 00000000 7c118a2b f1112345
+vpksdus: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> ffffffff 00000000 ffffffff 00000000
+
+vpksdss: 000000007c118a2b, 00000000f1112345 @@ 000000007c118a2b, 00000000f1112345 ==> 7c118a2b 7fffffff 7c118a2b 7fffffff
+vpksdss: 000000007c118a2b, 00000000f1112345 @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> 7c118a2b 7fffffff 7fffffff 80000000
+vpksdss: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 000000007c118a2b, 00000000f1112345 ==> 7fffffff 80000000 7c118a2b 7fffffff
+vpksdss: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> 7fffffff 80000000 7fffffff 80000000
+
+vupkhsw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0000000001020304 0000000005060708
+vupkhsw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> fffffffff1f2f3f4 fffffffff5f6f7f8
+
+vupklsw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 00000000090a0b0c 000000000e0d0e0f
+vupklsw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> fffffffff9fafbfc fffffffffefdfeff
+
+vpermxor: 0102030405060708 @@ 0102030405060708 @@ 0102030405060708 ==> 0302050407060908
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0b0a0d0f0f0c0f0e
+vpermxor: 0102030405060708 @@ 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0d0c0b0a09080706
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0504030101020100
+vpermxor: 0102030405060708 @@ f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f3f2f5f4f7f6f9f8
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> fbfafdfffffcfffe
+vpermxor: 0102030405060708 @@ f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> fdfcfbfaf9f8f7f6
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f5f4f3f1f1f2f1f0
+vpermxor: f1f2f3f4f5f6f7f8 @@ 0102030405060708 @@ 0102030405060708 ==> f3f2f5f4f7f6f9f8
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> fbfafdfffffcfffe
+vpermxor: f1f2f3f4f5f6f7f8 @@ 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> fdfcfbfaf9f8f7f6
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> f5f4f3f1f1f2f1f0
+vpermxor: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0302050407060908
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0b0a0d0f0f0c0f0e
+vpermxor: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0d0c0b0a09080706
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0504030101020100
+
+vclzb: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 07060605050505040404040404040404
+vclzb: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+
+vclzw: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 00000007000000050000000400000004
+vclzw: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+
+vclzh: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 00070006000500050004000400040004
+vclzh: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+
+vclzd: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 00000000000000070000000000000004
+vclzd: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+
+vpopcntb: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 01010201020203010202030203030304
+vpopcntb: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 05050605060607050606070607070708
+
+vpopcnth: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 00020003000400040004000500060007
+vpopcnth: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 000a000b000c000c000c000d000e000f
+
+vpopcntw: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 0000000500000008000000090000000d
+vpopcntw: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 0000001500000018000000190000001d
+
+vpopcntd: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 000000000000000d0000000000000016
+vpopcntd: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 000000000000002d0000000000000036
+
+vsbox: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 7c777bf26b6fc53001672bfeabd7ab76
+vsbox: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> a1890dbfe6426841992d0fb0bb54bb16
+
+vgbbd: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 00000000011e66aa00000000ff1f6ba5
+vgbbd: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> ffffffff011e66aaffffffffff1f6ba5
+
+vshasigmad: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 088207870e8c098d || 8b9e1b9b13149015
+vshasigmad: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> c8f5100c7844a0fc || e9b5916d0131c581
+vshasigmad: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 592bfd4c0062b487 || fb4fb96f4cf02615
+vshasigmad: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 1fe0874b08d19458 || fdb8e0eda977beb2
+vshasigmad: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 81eb6eee67e560e4 || 02f772f27a7df97c
+vshasigmad: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 52af4a56221efaa6 || 73efcb375b6b9fdb
+vshasigmad: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 8bf92f9ed2b06655 || 299d6bbd9e22f4c7
+vshasigmad: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 986700cc8f5613df || 7a3f676a2ef03935
+
+vshasigmaw: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 88e344269168cdae || 9bf057355c5e785e
+vshasigmaw: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 41e2c021c36443a2 || 44e5c72626c5e584
+vshasigmaw: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 106c98d5211d89e6 || 720efab787c30fd3
+vshasigmaw: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> f185aa4c42173cde || d4a08f69fb5ef21e
+vshasigmaw: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 4b2087e552ab0e6d || 583394f69f9dbb9d
+vshasigmaw: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 27b89a7ba53e19f8 || 22bf9d7c409fbfde
+vshasigmaw: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 6814e0ad5965f19e || 0a7682cfffbb77ab
+vshasigmaw: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 54200fe9e7b2997b || 71052acc5efb57bb
+
+bcdadd.: 8045090189321003 || 001122334556677d @@ 8045090189321003 || 001122334556677d ==> 6090180378642006 || 002244669113354d
+bcdadd.: 8045090189321003 || 001122334556677d @@ 8045090189321003 || 001122334556677d ==> 6090180378642006 || 002244669113354d
+bcdadd.: 8045090189321003 || 001122334556677d @@ 0000107600000001 || 319293945142031a ==> 8044982589321001 || 681828389414646d
+bcdadd.: 8045090189321003 || 001122334556677d @@ 0000107600000001 || 319293945142031a ==> 8044982589321001 || 681828389414646d
+bcdadd.: 8045090189321003 || 001122334556677d @@ 0000000000000000 || 000000000000000a ==> 8045090189321003 || 001122334556677d
+bcdadd.: 8045090189321003 || 001122334556677d @@ 0000000000000000 || 000000000000000a ==> 8045090189321003 || 001122334556677d
+bcdadd.: 8045090189321003 || 001122334556677d @@ 0000000000000000 || 0000000000000000 ==> 8045090189321003 || 001122334556677d
+bcdadd.: 8045090189321003 || 001122334556677d @@ 0000000000000000 || 0000000000000000 ==> 8045090189321003 || 001122334556677d
+bcdadd.: 0000107600000001 || 319293945142031a @@ 8045090189321003 || 001122334556677d ==> 8044982589321001 || 681828389414646d
+bcdadd.: 0000107600000001 || 319293945142031a @@ 8045090189321003 || 001122334556677d ==> 8044982589321001 || 681828389414646d
+bcdadd.: 0000107600000001 || 319293945142031a @@ 0000107600000001 || 319293945142031a ==> 0000215200000002 || 638587890284062c
+bcdadd.: 0000107600000001 || 319293945142031a @@ 0000107600000001 || 319293945142031a ==> 0000215200000002 || 638587890284062f
+bcdadd.: 0000107600000001 || 319293945142031a @@ 0000000000000000 || 000000000000000a ==> 0000107600000001 || 319293945142031c
+bcdadd.: 0000107600000001 || 319293945142031a @@ 0000000000000000 || 000000000000000a ==> 0000107600000001 || 319293945142031f
+bcdadd.: 0000107600000001 || 319293945142031a @@ 0000000000000000 || 0000000000000000 ==> 0000107600000001 || 319293945142031c
+bcdadd.: 0000107600000001 || 319293945142031a @@ 0000000000000000 || 0000000000000000 ==> 0000107600000001 || 319293945142031f
+bcdadd.: 0000000000000000 || 000000000000000a @@ 8045090189321003 || 001122334556677d ==> 8045090189321003 || 001122334556677d
+bcdadd.: 0000000000000000 || 000000000000000a @@ 8045090189321003 || 001122334556677d ==> 8045090189321003 || 001122334556677d
+bcdadd.: 0000000000000000 || 000000000000000a @@ 0000107600000001 || 319293945142031a ==> 0000107600000001 || 319293945142031c
+bcdadd.: 0000000000000000 || 000000000000000a @@ 0000107600000001 || 319293945142031a ==> 0000107600000001 || 319293945142031f
+bcdadd.: 0000000000000000 || 000000000000000a @@ 0000000000000000 || 000000000000000a ==> 0000000000000000 || 000000000000000c
+bcdadd.: 0000000000000000 || 000000000000000a @@ 0000000000000000 || 000000000000000a ==> 0000000000000000 || 000000000000000f
+bcdadd.: 0000000000000000 || 000000000000000a @@ 0000000000000000 || 0000000000000000 ==> 0000000000000000 || 000000000000000c
+bcdadd.: 0000000000000000 || 000000000000000a @@ 0000000000000000 || 0000000000000000 ==> 0000000000000000 || 000000000000000f
+bcdadd.: 0000000000000000 || 0000000000000000 @@ 8045090189321003 || 001122334556677d ==> 8045090189321003 || 001122334556677d
+bcdadd.: 0000000000000000 || 0000000000000000 @@ 8045090189321003 || 001122334556677d ==> 8045090189321003 || 001122334556677d
+bcdadd.: 0000000000000000 || 0000000000000000 @@ 0000107600000001 || 319293945142031a ==> 0000107600000001 || 319293945142031c
+bcdadd.: 0000000000000000 || 0000000000000000 @@ 0000107600000001 || 319293945142031a ==> 0000107600000001 || 319293945142031f
+bcdadd.: 0000000000000000 || 0000000000000000 @@ 0000000000000000 || 000000000000000a ==> 0000000000000000 || 000000000000000c
+bcdadd.: 0000000000000000 || 0000000000000000 @@ 0000000000000000 || 000000000000000a ==> 0000000000000000 || 000000000000000f
+bcdadd.: 0000000000000000 || 0000000000000000 @@ 0000000000000000 || 0000000000000000 ==> 0000000000000000 || 000000000000000c
+bcdadd.: 0000000000000000 || 0000000000000000 @@ 0000000000000000 || 0000000000000000 ==> 0000000000000000 || 000000000000000f
+
+bcdsub.: 8045090189321003 || 001122334556677d @@ 8045090189321003 || 001122334556677d ==> 0000000000000000 || 000000000000000c
+bcdsub.: 8045090189321003 || 001122334556677d @@ 8045090189321003 || 001122334556677d ==> 0000000000000000 || 000000000000000f
+bcdsub.: 8045090189321003 || 001122334556677d @@ 0000107600000001 || 319293945142031a ==> 8045197789321004 || 320416279698708d
+bcdsub.: 8045090189321003 || 001122334556677d @@ 0000107600000001 || 319293945142031a ==> 8045197789321004 || 320416279698708d
+bcdsub.: 8045090189321003 || 001122334556677d @@ 0000000000000000 || 000000000000000a ==> 8045090189321003 || 001122334556677d
+bcdsub.: 8045090189321003 || 001122334556677d @@ 0000000000000000 || 000000000000000a ==> 8045090189321003 || 001122334556677d
+bcdsub.: 8045090189321003 || 001122334556677d @@ 0000000000000000 || 0000000000000000 ==> 8045090189321003 || 001122334556677d
+bcdsub.: 8045090189321003 || 001122334556677d @@ 0000000000000000 || 0000000000000000 ==> 8045090189321003 || 001122334556677d
+bcdsub.: 0000107600000001 || 319293945142031a @@ 8045090189321003 || 001122334556677d ==> 8045197789321004 || 320416279698708c
+bcdsub.: 0000107600000001 || 319293945142031a @@ 8045090189321003 || 001122334556677d ==> 8045197789321004 || 320416279698708f
+bcdsub.: 0000107600000001 || 319293945142031a @@ 0000107600000001 || 319293945142031a ==> 0000000000000000 || 000000000000000c
+bcdsub.: 0000107600000001 || 319293945142031a @@ 0000107600000001 || 319293945142031a ==> 0000000000000000 || 000000000000000f
+bcdsub.: 0000107600000001 || 319293945142031a @@ 0000000000000000 || 000000000000000a ==> 0000107600000001 || 319293945142031c
+bcdsub.: 0000107600000001 || 319293945142031a @@ 0000000000000000 || 000000000000000a ==> 0000107600000001 || 319293945142031f
+bcdsub.: 0000107600000001 || 319293945142031a @@ 0000000000000000 || 0000000000000000 ==> 0000107600000001 || 319293945142031c
+bcdsub.: 0000107600000001 || 319293945142031a @@ 0000000000000000 || 0000000000000000 ==> 0000107600000001 || 319293945142031f
+bcdsub.: 0000000000000000 || 000000000000000a @@ 8045090189321003 || 001122334556677d ==> 8045090189321003 || 001122334556677c
+bcdsub.: 0000000000000000 || 000000000000000a @@ 8045090189321003 || 001122334556677d ==> 8045090189321003 || 001122334556677f
+bcdsub.: 0000000000000000 || 000000000000000a @@ 0000107600000001 || 319293945142031a ==> 0000107600000001 || 319293945142031d
+bcdsub.: 0000000000000000 || 000000000000000a @@ 0000107600000001 || 319293945142031a ==> 0000107600000001 || 319293945142031d
+bcdsub.: 0000000000000000 || 000000000000000a @@ 0000000000000000 || 000000000000000a ==> 0000000000000000 || 000000000000000c
+bcdsub.: 0000000000000000 || 000000000000000a @@ 0000000000000000 || 000000000000000a ==> 0000000000000000 || 000000000000000f
+bcdsub.: 0000000000000000 || 000000000000000a @@ 0000000000000000 || 0000000000000000 ==> 0000000000000000 || 000000000000000c
+bcdsub.: 0000000000000000 || 000000000000000a @@ 0000000000000000 || 0000000000000000 ==> 0000000000000000 || 000000000000000f
+bcdsub.: 0000000000000000 || 0000000000000000 @@ 8045090189321003 || 001122334556677d ==> 8045090189321003 || 001122334556677c
+bcdsub.: 0000000000000000 || 0000000000000000 @@ 8045090189321003 || 001122334556677d ==> 8045090189321003 || 001122334556677f
+bcdsub.: 0000000000000000 || 0000000000000000 @@ 0000107600000001 || 319293945142031a ==> 0000107600000001 || 319293945142031d
+bcdsub.: 0000000000000000 || 0000000000000000 @@ 0000107600000001 || 319293945142031a ==> 0000107600000001 || 319293945142031d
+bcdsub.: 0000000000000000 || 0000000000000000 @@ 0000000000000000 || 000000000000000a ==> 0000000000000000 || 000000000000000c
+bcdsub.: 0000000000000000 || 0000000000000000 @@ 0000000000000000 || 000000000000000a ==> 0000000000000000 || 000000000000000f
+bcdsub.: 0000000000000000 || 0000000000000000 @@ 0000000000000000 || 0000000000000000 ==> 0000000000000000 || 000000000000000c
+bcdsub.: 0000000000000000 || 0000000000000000 @@ 0000000000000000 || 0000000000000000 ==> 0000000000000000 || 000000000000000f
+
+vaddcuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 00000000000000000000000000000000
+vaddcuq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+vaddcuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 00000000000000000000000000000000
+vaddcuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000001
+
+vadduqm: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 020406080a0c0e10121416181c1a1c1e
+vadduqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> f2f4f6f8fafcff01030507090d0b0d0e
+vadduqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> f2f4f6f8fafcff01030507090d0b0d0e
+vadduqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> e3e5e7e9ebedeff1f3f5f7f9fdfbfdfe
+
+vsubcuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 00000000000000000000000000000001
+vsubcuq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+vsubcuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 00000000000000000000000000000001
+vsubcuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000001
+
+vsubuqm: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 00000000000000000000000000000000
+vsubuqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f10
+vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0
+vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+
+vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000020a0000000000000000
+vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000e3ea0000000000000000
+vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+
+vaddecuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000000
+vaddecuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> 00000000000000000000000000000000
+vaddecuq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> 00000000000000000000000000000000
+vaddecuq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 00000000000000000000000000000000
+vaddecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000000
+vaddecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> 00000000000000000000000000000000
+vaddecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> 00000000000000000000000000000001
+vaddecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 00000000000000000000000000000001
+
+vaddeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 020406080a0c0e10121416181c1a1c1e
+vaddeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> 020406080a0c0e10121416181c1a1c1f
+vaddeuqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> f2f4f6f8fafcff01030507090d0b0d0e
+vaddeuqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> f2f4f6f8fafcff01030507090d0b0d0f
+vaddeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> f2f4f6f8fafcff01030507090d0b0d0e
+vaddeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> f2f4f6f8fafcff01030507090d0b0d0f
+vaddeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> e3e5e7e9ebedeff1f3f5f7f9fdfbfdfe
+vaddeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> e3e5e7e9ebedeff1f3f5f7f9fdfbfdff
+
+vsubecuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000000
+vsubecuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> 00000000000000000000000000000001
+vsubecuq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> 00000000000000000000000000000000
+vsubecuq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 00000000000000000000000000000000
+vsubecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000001
+vsubecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> 00000000000000000000000000000001
+vsubecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> 00000000000000000000000000000000
+vsubecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 00000000000000000000000000000001
+
+vsubeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> ffffffffffffffffffffffffffffffff
+vsubeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> 00000000000000000000000000000000
+vsubeuqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> 0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f
+vsubeuqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f10
+vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0ef
+vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0
+vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> ffffffffffffffffffffffffffffffff
+vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 00000000000000000000000000000000
+
+All done. Tested 66 different instructions
diff --git a/none/tests/ppc32/test_isa_2_07_part1.c b/none/tests/ppc32/test_isa_2_07_part1.c
deleted file mode 120000
index b258517..0000000
--- a/none/tests/ppc32/test_isa_2_07_part1.c
+++ /dev/null
@@ -1 +0,0 @@
-../ppc64/test_isa_2_07_part1.c
\ No newline at end of file
diff --git a/none/tests/ppc32/test_isa_2_07_part1.c b/none/tests/ppc32/test_isa_2_07_part1.c
new file mode 100644
index 0000000..73a563c
--- /dev/null
+++ b/none/tests/ppc32/test_isa_2_07_part1.c
@@ -0,0 +1,2137 @@
+
+/* HOW TO COMPILE:
+
+ * 32bit build:
+ gcc -Winline -Wall -g -O -mregnames -maltivec -m32
+ * 64bit build:
+ gcc -Winline -Wall -g -O -mregnames -maltivec -m64
+
+
+ * test_isa_2_07_part1.c:
+ * PPC tests for the ISA 2.07. This file is based on the
+ * jm-insns.c file for the new instructions in the ISA 2.07. The
+ * test structure has been kept the same as the original file to
+ * the extent possible.
+ *
+ * Copyright (C) 2013 IBM
+ *
+ * Authors: Carl Love <carll@us.ibm.com>
+ * Maynard Johnson <maynardj@us.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Operation details
+ * -----------------
+ *
+ * The 'loops' (e.g. int_loops) do the actual work:
+ * - loops over as many arguments as the insn needs (regs | imms)
+ * - sets up the environment (reset cr,xer, assign src regs...)
+ * - maybe modifies the asm instn to test different imm args
+ * - calls the test function
+ * - retrieves relevant register data (rD,cr,xer,...)
+ * - prints argument and result data.
+ *
+ * More specifically...
+ *
+ * all_tests[i] holds insn tests
+ * - of which each holds: {instn_test_arr[], description, flags}
+ *
+ * flags hold 3 instn classifiers: {family, type, arg_type}
+ *
+ * // The main test loop:
+ * do_tests( user_ctl_flags ) {
+ * foreach(curr_test = all_test[i]) {
+ *
+ * // flags are used to control what tests are run:
+ * if (curr_test->flags && !user_ctl_flags)
+ * continue;
+ *
+ * // a 'loop_family_arr' is chosen based on the 'family' flag...
+ * switch(curr_test->flags->family) {
+ * case x: loop_family_arr = int_loops;
+ * ...
+ * }
+ *
+ * // ...and the actual test_loop to run is found by indexing into
+ * // the loop_family_arr with the 'arg_type' flag:
+ * test_loop = loop_family[curr_test->flags->arg_type]
+ *
+ * // finally, loop over all instn tests for this test:
+ * foreach (instn_test = curr_test->instn_test_arr[i]) {
+ *
+ * // and call the test_loop with the current instn_test function,name
+ * test_loop( instn_test->func, instn_test->name )
+ * }
+ * }
+ * }
+ *
+ */
+
+
+/**********************************************************************/
+
+/* Uncomment to enable output of CR flags for float tests */
+//#define TEST_FLOAT_FLAGS
+
+/* Uncomment to enable debug output */
+//#define DEBUG_ARGS_BUILD
+//#define DEBUG_FILTER
+
+/**********************************************************************/
+#include <stdio.h>
+
+#ifdef HAS_ISA_2_07
+
+#include "config.h"
+#include <altivec.h>
+#include <stdint.h>
+
+#include <assert.h>
+#include <ctype.h> // isspace
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h> // getopt
+
+#if !defined (__TEST_PPC_H__)
+#define __TEST_PPC_H__
+
+#include "tests/sys_mman.h"
+#include "tests/malloc.h" // memalign16
+
+#define STATIC_ASSERT(e) sizeof(struct { int:-!(e); })
+
+/* Something of the same size as void*, so can be safely be coerced
+ * to/from a pointer type. Also same size as the host's gp registers.
+ * According to the AltiVec section of the GCC manual, the syntax does
+ * not allow the use of a typedef name as a type specifier in conjunction
+ * with the vector keyword, so typedefs uint[32|64]_t are #undef'ed here
+ * and redefined using #define.
+ */
+#undef uint32_t
+#undef uint64_t
+#define uint32_t unsigned int
+#define uint64_t unsigned long long int
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#define ZERO 0
+#else
+typedef uint64_t HWord_t;
+#define ZERO 0ULL
+#endif /* __powerpc64__ */
+
+#ifdef VGP_ppc64le_linux
+#define isLE 1
+#else
+#define isLE 0
+#endif
+
+typedef uint64_t Word_t;
+
+enum {
+ compile_time_test1 = STATIC_ASSERT(sizeof(uint32_t) == 4),
+ compile_time_test2 = STATIC_ASSERT(sizeof(uint64_t) == 8),
+};
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define DEFAULT_VSCR 0x0
+
+static vector unsigned long long vec_out, vec_inA, vec_inB, vec_inC;
+static vector unsigned int vec_inA_wd, vec_inB_wd;
+
+/* XXXX these must all be callee-save regs! */
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+register HWord_t r14 __asm__ ("r14");
+register HWord_t r15 __asm__ ("r15");
+register HWord_t r16 __asm__ ("r16");
+register HWord_t r17 __asm__ ("r17");
+
+typedef void (*test_func_t) (void);
+typedef struct _test test_t;
+typedef struct _test_table test_table_t;
+struct _test {
+ test_func_t func;
+ const char *name;
+};
+
+struct _test_table {
+ test_t *tests;
+ const char *name;
+ uint32_t flags;
+};
+
+typedef void (*test_loop_t) (const char *name, test_func_t func,
+ uint32_t flags);
+
+enum test_flags {
+ /* Nb arguments */
+ PPC_ONE_ARG = 0x00000001,
+ PPC_TWO_ARGS = 0x00000002,
+ PPC_THREE_ARGS = 0x00000003,
+ PPC_CMP_ARGS = 0x00000004, // family: compare
+ PPC_CMPI_ARGS = 0x00000005, // family: compare
+ PPC_TWO_I16 = 0x00000006, // family: arith/logical
+ PPC_SPECIAL = 0x00000007, // family: logical
+ PPC_LD_ARGS = 0x00000008, // family: ldst
+ PPC_LDX_ARGS = 0x00000009, // family: ldst
+ PPC_ST_ARGS = 0x0000000A, // family: ldst
+ PPC_STX_ARGS = 0x0000000B, // family: ldst
+ PPC_STQ_ARGS = 0x0000000C, // family: ldst, two args, imm
+ PPC_LDQ_ARGS = 0x0000000D, // family: ldst, two args, imm
+ PPC_STQX_ARGS = 0x0000000E, // family: ldst, three args
+ PPC_LDQX_ARGS = 0x0000000F, // family: ldst, three_args
+ PPC_NB_ARGS = 0x0000000F,
+ /* Type */
+ PPC_ARITH = 0x00000100,
+ PPC_LOGICAL = 0x00000200,
+ PPC_COMPARE = 0x00000300,
+ PPC_CROP = 0x00000400,
+ PPC_LDST = 0x00000500,
+ PPC_POPCNT = 0x00000600,
+ PPC_ARITH_DRES = 0x00000700,
+ PPC_DOUBLE_IN_IRES = 0x00000800,
+ PPC_MOV = 0x00000A00,
+ PPC_SHA_OR_BCD = 0x00000B00,
+ PPC_TYPE = 0x00000F00,
+ /* Family */
+ PPC_INTEGER = 0x00010000,
+ PPC_FLOAT = 0x00020000,
+ PPC_405 = 0x00030000, // Leave so we keep numbering consistent
+ PPC_ALTIVEC = 0x00040000,
+ PPC_FALTIVEC = 0x00050000,
+ PPC_ALTIVECD = 0x00060000, /* double word Altivec tests */
+ PPC_ALTIVECQ = 0x00070000,
+ PPC_FAMILY = 0x000F0000,
+ /* Flags: these may be combined, so use separate bitfields. */
+ PPC_CR = 0x01000000,
+ PPC_XER_CA = 0x02000000,
+};
+
+#endif /* !defined (__TEST_PPC_H__) */
+
+/* -------------- END #include "test-ppc.h" -------------- */
+
+
+#if defined (DEBUG_ARGS_BUILD)
+#define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define AB_DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+
+#if defined (DEBUG_FILTER)
+#define FDPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define FDPRINTF(fmt, args...) do { } while (0)
+#endif
+
+#define unused __attribute__ (( unused ))
+
+typedef struct special {
+ const char *name;
+ void (*test_cb)(const char* name, test_func_t func,
+ unused uint32_t test_flags);
+} special_t;
+
+static void test_stq(void)
+{
+ __asm__ __volatile__ ("stq %0, 0(%1)" : :"r" (r14), "r" (r16));
+}
+
+static test_t tests_istq_ops_two_i16[] = {
+ { &test_stq , "stq", },
+ { NULL, NULL, },
+};
+
+static void test_lq(void)
+{
+ __asm__ __volatile__ ("lq %0, 0(%1)" : :"r" (r14), "r" (r16));
+}
+
+static test_t tests_ildq_ops_two_i16[] = {
+ { &test_lq , "lq", },
+ { NULL, NULL, },
+};
+
+#ifdef HAS_ISA_2_07
+Word_t * mem_resv;
+static void test_stbcx(void)
+{
+ /* Have to do the lbarx to the memory address to create the reservation
+ * or the store will not occur.
+ */
+ __asm__ __volatile__ ("lbarx %0, %1, %2" : :"r" (r14), "r" (r16),"r" (r17));
+ r14 = (HWord_t) 0xABEFCD0145236789ULL;
+ r15 = (HWord_t) 0x1155337744226688ULL;
+ __asm__ __volatile__ ("stbcx. %0, %1, %2" : :"r" (r14), "r" (r16),"r" (r17));
+}
+
+static void test_sthcx(void)
+{
+ /* Have to do the lharx to the memory address to create the reservation
+ * or the store will not occur.
+ */
+ __asm__ __volatile__ ("lharx %0, %1, %2" : :"r" (r14), "r" (r16),"r" (r17));
+ r14 = (HWord_t) 0xABEFCD0145236789ULL;
+ r15 = (HWord_t) 0x1155337744226688ULL;
+ __asm__ __volatile__ ("sthcx. %0, %1, %2" : :"r" (r14), "r" (r16),"r" (r17));
+}
+#endif
+
+static void test_stqcx(void)
+{
+ /* Have to do the lqarx to the memory address to create the reservation
+ * or the store will not occur.
+ */
+ __asm__ __volatile__ ("lqarx %0, %1, %2" : :"r" (r14), "r" (r16),"r" (r17));
+ r14 = (HWord_t) 0xABEFCD0145236789ULL;
+ r15 = (HWord_t) 0x1155337744226688ULL;
+ __asm__ __volatile__ ("stqcx. %0, %1, %2" : :"r" (r14), "r" (r16),"r" (r17));
+}
+
+static test_t tests_stq_ops_three[] = {
+#ifdef HAS_ISA_2_07
+ { &test_stbcx , "stbcx.", },
+ { &test_sthcx , "sthcx.", },
+#endif
+ { &test_stqcx , "stqcx.", },
+ { NULL, NULL, },
+};
+
+#ifdef HAS_ISA_2_07
+static void test_lbarx(void)
+{
+ __asm__ __volatile__ ("lbarx %0, %1, %2, 0" : :"r" (r14), "r" (r16),"r" (r17));
+}
+static void test_lharx(void)
+{
+ __asm__ __volatile__ ("lharx %0, %1, %2, 0" : :"r" (r14), "r" (r16),"r" (r17));
+}
+#endif
+static void test_lqarx(void)
+{
+ __asm__ __volatile__ ("lqarx %0, %1, %2, 0" : :"r" (r14), "r" (r16),"r" (r17));
+}
+
+static test_t tests_ldq_ops_three[] = {
+#ifdef HAS_ISA_2_07
+ { &test_lbarx , "lbarx", },
+ { &test_lharx , "lharx", },
+#endif
+ { &test_lqarx , "lqarx", },
+ { NULL, NULL, },
+};
+
+static void test_fmrgew (void)
+{
+ __asm__ __volatile__ ("fmrgew 17,14,15");
+};
+
+static void test_fmrgow (void)
+{
+ __asm__ __volatile__ ("fmrgow 17,14,15");
+};
+
+
+
+// VSX move instructions
+static void test_mfvsrd (void)
+{
+ __asm__ __volatile__ ("mfvsrd %0,%x1" : "=r" (r14) : "ws" (vec_inA));
+};
+
+static void test_mfvsrwz (void)
+{
+ __asm__ __volatile__ ("mfvsrwz %0,%x1" : "=r" (r14) : "ws" (vec_inA));
+};
+
+static void test_mtvsrd (void)
+{
+ __asm__ __volatile__ ("mtvsrd %x0,%1" : "=ws" (vec_out) : "r" (r14));
+};
+
+static void test_mtvsrwz (void)
+{
+ __asm__ __volatile__ ("mtvsrwz %x0,%1" : "=ws" (vec_out) : "r" (r14));
+};
+
+
+static void test_mtfprwa (void)
+{
+ __asm__ __volatile__ ("mtfprwa %x0,%1" : "=ws" (vec_out) : "r" (r14));
+};
+
+static test_t tests_move_ops_spe[] = {
+ { &test_mfvsrd , "mfvsrd" },
+ { &test_mfvsrwz , "mfvsrwz" },
+ { &test_mtvsrd , "mtvsrd" },
+ { &test_mtvsrwz , "mtvsrwz" },
+ { &test_mtfprwa , "mtfprwa" },
+ { NULL, NULL }
+};
+
+/* NOTE: Since these are "vector" instructions versus VSX, we must use
+ * vector constraints.
+ *
+ * Vector Double Word tests.
+ */
+static void test_vpkudum (void)
+{
+ __asm__ __volatile__ ("vpkudum %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vaddudm (void)
+{
+ __asm__ __volatile__ ("vaddudm %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vsubudm (void)
+{
+ __asm__ __volatile__ ("vsubudm %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vmaxud (void)
+{
+ __asm__ __volatile__ ("vmaxud %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vmaxsd (void)
+{
+ __asm__ __volatile__ ("vmaxsd %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vminud (void)
+{
+ __asm__ __volatile__ ("vminud %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vminsd (void)
+{
+ __asm__ __volatile__ ("vminsd %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vcmpequd (void)
+{
+ __asm__ __volatile__ ("vcmpequd %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vcmpgtud (void)
+{
+ __asm__ __volatile__ ("vcmpgtud %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vcmpgtsd (void)
+{
+ __asm__ __volatile__ ("vcmpgtsd %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vrld (void)
+{
+ __asm__ __volatile__ ("vrld %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vsld (void)
+{
+ __asm__ __volatile__ ("vsld %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vsrad (void)
+{
+ __asm__ __volatile__ ("vsrad %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vsrd (void)
+{
+ __asm__ __volatile__ ("vsrd %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+/* Vector Double Word saturate tests.*/
+
+static void test_vpkudus (void)
+{
+ __asm__ __volatile__ ("vpkudus %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vpksdus (void)
+{
+ __asm__ __volatile__ ("vpksdus %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vpksdss (void)
+{
+ __asm__ __volatile__ ("vpksdss %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+
+/* Vector unpack two words from one vector arg */
+static void test_vupkhsw (void)
+{
+ __asm__ __volatile__ ("vupkhsw %0, %1" : "=v" (vec_out): "v" (vec_inB_wd));
+}
+
+static void test_vupklsw (void)
+{
+ __asm__ __volatile__ ("vupklsw %0, %1" : "=v" (vec_out): "v" (vec_inB_wd));
+}
+
+
+/* Vector Integer Word tests.*/
+static void test_vmulouw (void)
+{
+ __asm__ __volatile__ ("vmulouw %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vmuluwm (void)
+{
+ __asm__ __volatile__ ("vmuluwm %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vmulosw (void)
+{
+ __asm__ __volatile__ ("vmulosw %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vmuleuw (void)
+{
+ __asm__ __volatile__ ("vmuleuw %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vmulesw (void)
+{
+ __asm__ __volatile__ ("vmulesw %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vmrgew (void)
+{
+ __asm__ __volatile__ ("vmrgew %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vmrgow (void)
+{
+ __asm__ __volatile__ ("vmrgow %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vpmsumb (void)
+{
+ __asm__ __volatile__ ("vpmsumb %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vpmsumh (void)
+{
+ __asm__ __volatile__ ("vpmsumh %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vpmsumw (void)
+{
+ __asm__ __volatile__ ("vpmsumw %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vpermxor (void)
+{
+ __asm__ __volatile__ ("vpermxor %0, %1, %2, %3" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB),"v" (vec_inC));
+}
+
+static void test_vpmsumd (void)
+{
+ __asm__ __volatile__ ("vpmsumd %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vnand (void)
+{
+ __asm__ __volatile__ ("vnand %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vorc (void)
+{
+ __asm__ __volatile__ ("vorc %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_veqv (void)
+{
+ __asm__ __volatile__ ("veqv %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vcipher (void)
+{
+ __asm__ __volatile__ ("vcipher %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vcipherlast (void)
+{
+ __asm__ __volatile__ ("vcipherlast %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vncipher (void)
+{
+ __asm__ __volatile__ ("vncipher %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vncipherlast (void)
+{
+ __asm__ __volatile__ ("vncipherlast %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vclzb (void)
+{
+ __asm__ __volatile__ ("vclzb %0, %1" : "=v" (vec_out): "v" (vec_inB));
+}
+
+static void test_vclzw (void)
+{
+ __asm__ __volatile__ ("vclzw %0, %1" : "=v" (vec_out): "v" (vec_inB));
+}
+
+static void test_vclzh (void)
+{
+ __asm__ __volatile__ ("vclzh %0, %1" : "=v" (vec_out): "v" (vec_inB));
+}
+
+static void test_vclzd (void)
+{
+ __asm__ __volatile__ ("vclzd %0, %1" : "=v" (vec_out): "v" (vec_inB));
+}
+
+static void test_vpopcntb (void)
+{
+ __asm__ __volatile__ ("vpopcntb %0, %1" : "=v" (vec_out): "v" (vec_inB));
+}
+
+static void test_vpopcnth (void)
+{
+ __asm__ __volatile__ ("vpopcnth %0, %1" : "=v" (vec_out): "v" (vec_inB));
+}
+
+static void test_vpopcntw (void)
+{
+ __asm__ __volatile__ ("vpopcntw %0, %1" : "=v" (vec_out): "v" (vec_inB));
+}
+
+static void test_vpopcntd (void)
+{
+ __asm__ __volatile__ ("vpopcntd %0, %1" : "=v" (vec_out): "v" (vec_inB));
+}
+
+static void test_vsbox (void)
+{
+ __asm__ __volatile__ ("vsbox %0, %1" : "=v" (vec_out): "v" (vec_inB));
+}
+
+static int st_six;
+static void test_vshasigmad (void)
+{
+ switch (st_six) {
+ case 0x00:
+ __asm__ __volatile__ ("vshasigmad %0, %1, 0, 0" : "=v" (vec_out): "v" (vec_inA));
+ break;
+ case 0x0f:
+ __asm__ __volatile__ ("vshasigmad %0, %1, 0, 15" : "=v" (vec_out): "v" (vec_inA));
+ break;
+ case 0x10:
+ __asm__ __volatile__ ("vshasigmad %0, %1, 1, 0" : "=v" (vec_out): "v" (vec_inA));
+ break;
+ case 0x1f:
+ __asm__ __volatile__ ("vshasigmad %0, %1, 1, 15" : "=v" (vec_out): "v" (vec_inA));
+ break;
+ }
+}
+
+static void test_vshasigmaw (void)
+{
+ switch (st_six) {
+ case 0x00:
+ __asm__ __volatile__ ("vshasigmaw %0, %1, 0, 0" : "=v" (vec_out): "v" (vec_inA));
+ break;
+ case 0x0f:
+ __asm__ __volatile__ ("vshasigmaw %0, %1, 0, 15" : "=v" (vec_out): "v" (vec_inA));
+ break;
+ case 0x10:
+ __asm__ __volatile__ ("vshasigmaw %0, %1, 1, 0" : "=v" (vec_out): "v" (vec_inA));
+ break;
+ case 0x1f:
+ __asm__ __volatile__ ("vshasigmaw %0, %1, 1, 15" : "=v" (vec_out): "v" (vec_inA));
+ break;
+ }
+}
+
+static int PS_bit;
+static void test_bcdadd (void)
+{
+ if (PS_bit)
+ __asm__ __volatile__ ("bcdadd. %0, %1, %2, 1" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+ else
+ __asm__ __volatile__ ("bcdadd. %0, %1, %2, 0" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_bcdsub (void)
+{
+ if (PS_bit)
+ __asm__ __volatile__ ("bcdsub. %0, %1, %2, 1" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+ else
+ __asm__ __volatile__ ("bcdsub. %0, %1, %2, 0" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vaddcuq (void)
+{
+ __asm__ __volatile__ ("vaddcuq %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vadduqm (void)
+{
+ __asm__ __volatile__ ("vadduqm %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vaddecuq (void)
+{
+ __asm__ __volatile__ ("vaddecuq %0, %1, %2, %3" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB),"v" (vec_inC));
+}
+
+static void test_vaddeuqm (void)
+{
+ __asm__ __volatile__ ("vaddeuqm %0, %1, %2, %3" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB),"v" (vec_inC));
+}
+
+static void test_vsubcuq (void)
+{
+ __asm__ __volatile__ ("vsubcuq %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vsubuqm (void)
+{
+ __asm__ __volatile__ ("vsubuqm %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vsubecuq (void)
+{
+ __asm__ __volatile__ ("vsubecuq %0, %1, %2, %3" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB),"v" (vec_inC));
+}
+
+static void test_vsubeuqm (void)
+{
+ __asm__ __volatile__ ("vsubeuqm %0, %1, %2, %3" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB),"v" (vec_inC));
+}
+
+static void test_vbpermq (void)
+{
+ __asm__ __volatile__ ("vbpermq %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vgbbd (void)
+{
+ __asm__ __volatile__ ("vgbbd %0, %1" : "=v" (vec_out): "v" (vec_inB));
+}
+
+
+static test_t tests_aa_quadword_two_args[] = {
+ { &test_vaddcuq , "vaddcuq" },
+ { &test_vadduqm , "vadduqm" },
+ { &test_vsubcuq , "vsubcuq" },
+ { &test_vsubuqm , "vsubuqm" },
+ { &test_vbpermq , "vbpermq" },
+ { NULL , NULL },
+};
+
+static test_t tests_aa_quadword_three_args[] = {
+ { &test_vaddecuq , "vaddecuq" },
+ { &test_vaddeuqm , "vaddeuqm" },
+ { &test_vsubecuq , "vsubecuq" },
+ { &test_vsubeuqm , "vsubeuqm" },
+ { NULL , NULL },
+};
+
+static test_t tests_aa_bcd_ops[] = {
+ { &test_bcdadd , "bcdadd." },
+ { &test_bcdsub , "bcdsub." },
+ { NULL , NULL },
+};
+
+static test_t tests_aa_SHA_ops[] = {
+ { &test_vshasigmad , "vshasigmad" },
+ { &test_vshasigmaw , "vshasigmaw" },
+ { NULL , NULL },
+};
+
+static test_t tests_aa_ops_three[] = {
+ { &test_vpermxor , "vpermxor" },
+ { NULL , NULL },
+};
+
+static test_t tests_aa_word_ops_one_arg_dres[] = {
+ { &test_vupkhsw , "vupkhsw" },
+ { &test_vupklsw , "vupklsw" },
+ { NULL , NULL }
+};
+
+static test_t tests_aa_word_ops_two_args_dres[] = {
+ { &test_vmulouw , "vmulouw" },
+ { &test_vmuluwm , "vmuluwm" },
+ { &test_vmulosw , "vmulosw" },
+ { &test_vmuleuw , "vmuleuw" },
+ { &test_vmulesw , "vmulesw" },
+ { &test_vmrgew , "vmrgew" },
+ { &test_vmrgow , "vmrgow" },
+ { &test_vpmsumb , "vpmsumb" },
+ { &test_vpmsumh , "vpmsumh" },
+ { &test_vpmsumw , "vpmsumw" },
+ { NULL , NULL }
+};
+
+static test_t tests_aa_dbl_ops_two_args[] = {
+ { &test_vaddudm , "vaddudm", },
+ { &test_vsubudm , "vsubudm", },
+ { &test_vmaxud , "vmaxud", },
+ { &test_vmaxsd , "vmaxsd", },
+ { &test_vminud , "vminud", },
+ { &test_vminsd , "vminsd", },
+ { &test_vcmpequd , "vcmpequd", },
+ { &test_vcmpgtud , "vcmpgtud", },
+ { &test_vcmpgtsd , "vcmpgtsd", },
+ { &test_vrld , "vrld", },
+ { &test_vsld , "vsld", },
+ { &test_vsrad , "vsrad", },
+ { &test_vsrd , "vsrd", },
+ { &test_vpkudum , "vpkudum", },
+ { &test_vpmsumd , "vpmsumd", },
+ { &test_vnand , "vnand", },
+ { &test_vorc , "vorc", },
+ { &test_veqv , "veqv", },
+ { &test_vcipher , "vcipher" },
+ { &test_vcipherlast , "vcipherlast" },
+ { &test_vncipher , "vncipher" },
+ { &test_vncipherlast , "vncipherlast" },
+ { NULL , NULL, },
+};
+
+static test_t tests_aa_dbl_ops_one_arg[] = {
+ { &test_vclzb , "vclzb" },
+ { &test_vclzw , "vclzw" },
+ { &test_vclzh , "vclzh" },
+ { &test_vclzd , "vclzd" },
+ { &test_vpopcntb , "vpopcntb" },
+ { &test_vpopcnth , "vpopcnth" },
+ { &test_vpopcntw , "vpopcntw" },
+ { &test_vpopcntd , "vpopcntd" },
+ { &test_vsbox , "vsbox" },
+ { &test_vgbbd , "vgbbd" },
+ { NULL , NULL, }
+};
+
+static test_t tests_aa_dbl_to_int_two_args[] = {
+ { &test_vpkudus , "vpkudus", },
+ { &test_vpksdus , "vpksdus", },
+ { &test_vpksdss , "vpksdss", },
+ { NULL , NULL, },
+};
+
+static int verbose = 0;
+static int arg_list_size = 0;
+static unsigned long long * vdargs = NULL;
+static unsigned long long * vdargs_x = NULL;
+#define NB_VDARGS 9
+#define NB_VDARGS_X 4
+
+static void build_vdargs_table (void)
+{
+ // Each VSX register holds two doubleword integer values
+ vdargs = memalign16(NB_VDARGS * sizeof(unsigned long long));
+ vdargs[0] = 0x0102030405060708ULL;
+ vdargs[1] = 0x090A0B0C0E0D0E0FULL;
+ vdargs[2] = 0xF1F2F3F4F5F6F7F8ULL;
+ vdargs[3] = 0xF9FAFBFCFEFDFEFFULL;
+ vdargs[4] = 0x00007FFFFFFFFFFFULL;
+ vdargs[5] = 0xFFFF000000000000ULL;
+ vdargs[6] = 0x0000800000000000ULL;
+ vdargs[7] = 0x0000000000000000ULL;
+ vdargs[8] = 0xFFFFFFFFFFFFFFFFULL;
+
+ vdargs_x = memalign16(NB_VDARGS_X * sizeof(unsigned long long));
+ vdargs_x[0] = 0x000000007c118a2bULL;
+ vdargs_x[1] = 0x00000000f1112345ULL;
+ vdargs_x[2] = 0x01F2F3F4F5F6F7F8ULL;
+ vdargs_x[3] = 0xF9FAFBFCFEFDFEFFULL;
+}
+
+static unsigned int * vwargs = NULL;
+#define NB_VWARGS 8
+
+static void build_vwargs_table (void)
+{
+ // Each VSX register holds 4 integer word values
+ size_t i = 0;
+ vwargs = memalign(8, 8 * sizeof(int));
+ assert(vwargs);
+ assert(0 == ((8-1) & (unsigned long)vwargs));
+ vwargs[i++] = 0x01020304;
+ vwargs[i++] = 0x05060708;
+ vwargs[i++] = 0x090A0B0C;
+ vwargs[i++] = 0x0E0D0E0F;
+ vwargs[i++] = 0xF1F2F3F4;
+ vwargs[i++] = 0xF5F6F7F8;
+ vwargs[i++] = 0xF9FAFBFC;
+ vwargs[i++] = 0xFEFDFEFF;
+}
+
+static unsigned long long vbcd_args[] __attribute__ ((aligned (16))) = {
+ 0x8045090189321003ULL, // Negative BCD value
+ 0x001122334556677dULL,
+ 0x0000107600000001ULL, // Positive BCD value
+ 0x319293945142031aULL,
+ 0x0ULL, // Valid BCD zero
+ 0xaULL,
+ 0x0ULL, // Invalid BCD zero (no sign code)
+ 0x0ULL
+};
+//#define NUM_VBCD_VALS (sizeof vbcd_args/sizeof vbcd_args[0])
+#define NUM_VBCD_VALS 8
+
+static void build_vargs_table (void)
+{
+ build_vdargs_table();
+ build_vwargs_table();
+}
+
+static double *fargs = NULL;
+static int nb_fargs = 0;
+
+static inline void register_farg (void *farg,
+ int s, uint16_t _exp, uint64_t mant)
+{
+ uint64_t tmp;
+
+ tmp = ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
+ *(uint64_t *)farg = tmp;
+ AB_DPRINTF("%d %03x %013llx => %016llx %0e\n",
+ s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
+}
+
+static void build_fargs_table (void)
+{
+ /* Double precision:
+ * Sign goes from zero to one (1 bit)
+ * Exponent goes from 0 to ((1 << 12) - 1) (11 bits)
+ * Mantissa goes from 1 to ((1 << 52) - 1) (52 bits)
+ * + special values:
+ * +0.0 : 0 0x000 0x0000000000000 => 0x0000000000000000
+ * -0.0 : 1 0x000 0x0000000000000 => 0x8000000000000000
+ * +infinity : 0 0x7FF 0x0000000000000 => 0x7FF0000000000000
+ * -infinity : 1 0x7FF 0x0000000000000 => 0xFFF0000000000000
+ * +QNaN : 0 0x7FF 0x8000000000000 => 0x7FF8000000000000
+ * -QNaN : 1 0x7FF 0x8000000000000 => 0xFFF8000000000000
+ * +SNaN : 0 0x7FF 0x7FFFFFFFFFFFF => 0x7FF7FFFFFFFFFFFF
+ * -SNaN : 1 0x7FF 0x7FFFFFFFFFFFF => 0xFFF7FFFFFFFFFFFF
+ * (8 values)
+
+ * Ref only:
+ * Single precision
+ * Sign: 1 bit
+ * Exponent: 8 bits
+ * Mantissa: 23 bits
+ * +0.0 : 0 0x00 0x000000 => 0x00000000
+ * -0.0 : 1 0x00 0x000000 => 0x80000000
+ * +infinity : 0 0xFF 0x000000 => 0x7F800000
+ * -infinity : 1 0xFF 0x000000 => 0xFF800000
+ * +QNaN : 0 0xFF 0x400000 => 0x7FC00000
+ * -QNaN : 1 0xFF 0x400000 => 0xFFC00000
+ * +SNaN : 0 0xFF 0x3FFFFF => 0x7FBFFFFF
+ * -SNaN : 1 0xFF 0x3FFFFF => 0xFFBFFFFF
+ */
+ uint64_t mant;
+ uint16_t _exp, e0, e1;
+ int s;
+ int i=0;
+
+ /* Note: VEX isn't so hot with denormals, so don't bother
+ testing them: set _exp > 0
+ */
+
+ if ( arg_list_size == 1 ) { // Large
+ fargs = malloc(200 * sizeof(double));
+ for (s=0; s<2; s++) {
+ for (e0=0; e0<2; e0++) {
+ for (e1=0x001; ; e1 = ((e1 + 1) << 2) + 6) {
+ if (e1 >= 0x400)
+ e1 = 0x3fe;
+ _exp = (e0 << 10) | e1;
+ for (mant = 0x0000000000001ULL; mant < (1ULL << 52);
+ /* Add 'random' bits */
+ mant = ((mant + 0x4A6) << 13) + 0x359) {
+ register_farg(&fargs[i++], s, _exp, mant);
+ }
+ if (e1 == 0x3fe)
+ break;
+ }
+ }
+ }
+ } else { // Default
+ fargs = malloc(16 * sizeof(double));
+ for (s=0; s<2; s++) { // x2
+ for (e1=0x001; ; e1 = ((e1 + 1) << 13) + 7) { // x2
+ if (e1 >= 0x400)
+ e1 = 0x3fe;
+ _exp = e1;
+ for (mant = 0x0000000000001ULL; mant < (1ULL << 52);
+ /* Add 'random' bits */
+ mant = ((mant + 0x4A6) << 29) + 0x359) { // x2
+ register_farg(&fargs[i++], s, _exp, mant);
+ }
+ if (e1 == 0x3fe)
+ break;
+ }
+ }
+ }
+
+ /* Special values */
+ /* +0.0 : 0 0x000 0x0000000000000 */
+ s = 0;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* -0.0 : 1 0x000 0x0000000000000 */
+ s = 1;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* +infinity : 0 0x7FF 0x0000000000000 */
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* -infinity : 1 0x7FF 0x0000000000000 */
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF */
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF */
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* +SNaN : 0 0x7FF 0x8000000000000 */
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* -SNaN : 1 0x7FF 0x8000000000000 */
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ AB_DPRINTF("Registered %d fargs values\n", i);
+
+ nb_fargs = i;
+}
+
+
+
+static int check_filter (char *filter)
+{
+ char *c;
+ int ret = 1;
+
+ if (filter != NULL) {
+ c = strchr(filter, '*');
+ if (c != NULL) {
+ *c = '\0';
+ ret = 0;
+ }
+ }
+ return ret;
+}
+
+static int check_name (const char* name, const char *filter,
+ int exact)
+{
+ int nlen, flen;
+ int ret = 0;
+
+ if (filter != NULL) {
+ for (; isspace(*name); name++)
+ continue;
+ FDPRINTF("Check '%s' againt '%s' (%s match)\n",
+ name, filter, exact ? "exact" : "starting");
+ nlen = strlen(name);
+ flen = strlen(filter);
+ if (exact) {
+ if (nlen == flen && memcmp(name, filter, flen) == 0)
+ ret = 1;
+ } else {
+ if (flen <= nlen && memcmp(name, filter, flen) == 0)
+ ret = 1;
+ }
+ } else {
+ ret = 1;
+ }
+ return ret;
+}
+
+
+typedef struct insn_sel_flags_t_struct {
+ int one_arg, two_args, three_args;
+ int arith, logical, compare, ldst;
+ int integer, floats, altivec, faltivec;
+ int cr;
+} insn_sel_flags_t;
+
+static void test_float_two_args (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ double res;
+ Word_t u0, u1, ur;
+ volatile uint32_t flags;
+ int i, j;
+
+ for (i=0; i<nb_fargs; i+=3) {
+ for (j=0; j<nb_fargs; j+=5) {
+ u0 = *(Word_t *)(&fargs[i]);
+ u1 = *(Word_t *)(&fargs[j]);
+ f14 = fargs[i];
+ f15 = fargs[j];
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ res = f17;
+ ur = *(uint64_t *)(&res);
+
+ printf("%s %016llx, %016llx => %016llx",
+ name, u0, u1, ur);
+#if defined TEST_FLOAT_FLAGS
+ printf(" (%08x)", flags);
+#endif
+ printf("\n");
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+
+static void mfvs(const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ /* This test is for move instructions where the input is a scalar register
+ * and the destination is a vector register.
+ */
+ int i;
+ volatile Word_t result;
+ result = 0ULL;
+
+ for (i=0; i < NB_VDARGS; i++) {
+ r14 = ZERO;
+ if (isLE)
+ vec_inA = (vector unsigned long long){ 0ULL, vdargs[i] };
+ else
+ vec_inA = (vector unsigned long long){ vdargs[i], 0ULL };
+
+ (*func)();
+ result = r14;
+ printf("%s: %016llx => %016llx\n", name, vdargs[i], result);
+ }
+}
+
+static void mtvs(const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ /* This test is for move instructions where the input is a scalar register
+ * and the destination is a vector register.
+ */
+ unsigned long long *dst;
+ int i;
+
+ for (i=0; i < NB_VDARGS; i++) {
+ r14 = vdargs[i];
+ vec_out = (vector unsigned long long){ 0ULL, 0ULL };
+
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ if (isLE)
+ dst++;
+ printf("%s: %016llx => %016llx\n", name, vdargs[i], *dst);
+ }
+}
+
+static void mtvs2s(const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ /* This test is the mtvsrwa instruction.
+ */
+ unsigned long long *dst;
+ int i;
+
+ for (i=0; i < NB_VDARGS; i++) {
+ // Only the lower half of the vdarg doubleword arg will be used as input by mtvsrwa
+ unsigned int * src = (unsigned int *)&vdargs[i];
+ if (!isLE)
+ src++;
+ r14 = vdargs[i];
+ vec_out = (vector unsigned long long){ 0ULL, 0ULL };
+
+ (*func)();
+ // Only doubleword 0 is used in output
+ dst = (unsigned long long *) &vec_out;
+ if (isLE)
+ dst++;
+ printf("%s: %08x => %016llx\n", name, *src, *dst);
+ }
+}
+
+static void test_special (special_t *table,
+ const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ const char *tmp;
+ int i;
+
+ for (tmp = name; isspace(*tmp); tmp++)
+ continue;
+ for (i=0; table[i].name != NULL; i++) {
+ if (strcmp(table[i].name, tmp) == 0) {
+ (*table[i].test_cb)(name, func, test_flags);
+ return;
+ }
+ }
+ fprintf(stderr, "ERROR: no test found for op '%s'\n", name);
+}
+
+static special_t special_move_ops[] = {
+ {
+ "mfvsrd", /* move from vector to scalar reg doubleword */
+ &mfvs,
+ },
+ {
+ "mtvsrd", /* move from scalar to vector reg doubleword */
+ &mtvs,
+ },
+ {
+ "mtfprwa", /* (extended mnemonic for mtvsrwa) move from scalar to vector reg with two’s-complement */
+ &mtvs2s,
+ },
+ {
+ "mfvsrwz", /* move from vector to scalar reg word */
+ &mfvs,
+ },
+ {
+ "mtvsrwz", /* move from scalar to vector reg word */
+ &mtvs2s,
+ }
+};
+
+static void test_move_special(const char* name, test_func_t func,
+ uint32_t test_flags)
+{
+ test_special(special_move_ops, name, func, test_flags);
+}
+
+/* Vector Double Word tests */
+
+static void test_av_dint_two_args (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+
+ unsigned long long * dst;
+ unsigned int * dst_int;
+ int i,j;
+ int family = test_flags & PPC_FAMILY;
+ int is_vpkudum, is_vpmsumd;
+ if (strcmp(name, "vpkudum") == 0)
+ is_vpkudum = 1;
+ else
+ is_vpkudum = 0;
+
+ if (strcmp(name, "vpmsumd") == 0)
+ is_vpmsumd = 1;
+ else
+ is_vpmsumd = 0;
+
+ for (i = 0; i < NB_VDARGS - 1; i+=2) {
+ if (isLE && family == PPC_ALTIVECQ)
+ vec_inA = (vector unsigned long long){ vdargs[i+1], vdargs[i] };
+ else
+ vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
+ for (j = 0; j < NB_VDARGS - 1; j+=2) {
+ if (isLE && family == PPC_ALTIVECQ)
+ vec_inB = (vector unsigned long long){ vdargs[j+1], vdargs[j] };
+ else
+ vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
+ vec_out = (vector unsigned long long){ 0,0 };
+
+ (*func)();
+ dst_int = (unsigned int *)&vec_out;
+ dst = (unsigned long long*)&vec_out;
+
+ printf("%s: ", name);
+
+ if (is_vpkudum) {
+ printf("Inputs: %08llx %08llx %08llx %08llx\n", vdargs[i] & 0x00000000ffffffffULL,
+ vdargs[i+1] & 0x00000000ffffffffULL, vdargs[j] & 0x00000000ffffffffULL,
+ vdargs[j+1] & 0x00000000ffffffffULL);
+ if (isLE)
+ printf(" Output: %08x %08x %08x %08x\n", dst_int[2], dst_int[3],
+ dst_int[0], dst_int[1]);
+ else
+ printf(" Output: %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
+ dst_int[2], dst_int[3]);
+ } else if (is_vpmsumd) {
+ printf("%016llx @@ %016llx ", vdargs[i], vdargs[j]);
+ if (isLE)
+ printf(" ==> %016llx\n", dst[1]);
+ else
+ printf(" ==> %016llx\n", dst[0]);
+ printf("\t%016llx @@ %016llx ", vdargs[i+1], vdargs[j+1]);
+ if (isLE)
+ printf(" ==> %016llx\n", dst[0]);
+ else
+ printf(" ==> %016llx\n", dst[1]);
+ } else if (family == PPC_ALTIVECQ) {
+ if (isLE)
+ printf("%016llx%016llx @@ %016llx%016llx ==> %016llx%016llx\n",
+ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1],
+ dst[1], dst[0]);
+ else
+ printf("%016llx%016llx @@ %016llx%016llx ==> %016llx%016llx\n",
+ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1],
+ dst[0], dst[1]);
+ } else {
+ printf("%016llx @@ %016llx ", vdargs[i], vdargs[j]);
+ printf(" ==> %016llx\n", dst[0]);
+ printf("\t%016llx @@ %016llx ", vdargs[i+1], vdargs[j+1]);
+ printf(" ==> %016llx\n", dst[1]);
+ }
+ }
+ }
+}
+
+static void test_av_dint_one_arg (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+
+ unsigned long long * dst;
+ int i;
+
+ for (i = 0; i < NB_VDARGS - 1; i+=2) {
+ vec_inB = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
+ vec_out = (vector unsigned long long){ 0,0 };
+
+ (*func)();
+ dst = (unsigned long long*)&vec_out;
+
+ printf("%s: ", name);
+ printf("%016llx @@ %016llx ", vdargs[i], vdargs[i + 1]);
+ printf(" ==> %016llx%016llx\n", dst[0], dst[1]);
+ }
+}
+
+static void test_av_dint_one_arg_SHA (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ unsigned long long * dst;
+ int i, st, six;
+
+ for (i = 0; i < NB_VDARGS - 1; i+=2) {
+ vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
+ vec_out = (vector unsigned long long){ 0,0 };
+
+ for (st = 0; st < 2; st++) {
+ for (six = 0; six < 16; six+=15) {
+ st_six = (st << 4) | six;
+ (*func)();
+ dst = (unsigned long long*)&vec_out;
+
+ printf("%s: ", name);
+ printf("%016llx @@ %016llx ", vdargs[i], vdargs[i + 1]);
+ printf(" ==> %016llx || %016llx\n", dst[0], dst[1]);
+ }
+ }
+ }
+}
+
+static void test_av_bcd (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ unsigned long long * dst;
+ int i, j;
+
+ for (i = 0; i < NUM_VBCD_VALS - 1; i+=2) {
+ if (isLE)
+ vec_inA = (vector unsigned long long){ vbcd_args[i+1], vbcd_args[i]};
+ else
+ vec_inA = (vector unsigned long long){ vbcd_args[i], vbcd_args[i+1] };
+ for (j = 0; j < NUM_VBCD_VALS - 1; j+=2) {
+ if (isLE)
+ vec_inB = (vector unsigned long long){ vbcd_args[j+1] , vbcd_args[j] };
+ else
+ vec_inB = (vector unsigned long long){ vbcd_args[j], vbcd_args[j+1] };
+ vec_out = (vector unsigned long long){ 0, 0 };
+
+ for (PS_bit = 0; PS_bit < 2; PS_bit++) {
+ (*func)();
+ dst = (unsigned long long*)&vec_out;
+ printf("%s: ", name);
+ printf("%016llx || %016llx @@ %016llx || %016llx",
+ vbcd_args[i], vbcd_args[i + 1],
+ vbcd_args[j], vbcd_args[j + 1]);
+ if (isLE)
+ printf(" ==> %016llx || %016llx\n", dst[1], dst[0]);
+ else
+ printf(" ==> %016llx || %016llx\n", dst[0], dst[1]);
+ }
+ }
+ }
+}
+
+/* Vector doubleword-to-int tests, two input args, integer result */
+static void test_av_dint_to_int_two_args (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+
+ unsigned int * dst_int;
+ int i,j;
+ for (i = 0; i < NB_VDARGS_X - 1; i+=2) {
+ vec_inA = (vector unsigned long long){ vdargs_x[i], vdargs_x[i+1] };
+ for (j = 0; j < NB_VDARGS_X - 1; j+=2) {
+ vec_inB = (vector unsigned long long){ vdargs_x[j], vdargs_x[j+1] };
+ vec_out = (vector unsigned long long){ 0,0 };
+
+ (*func)();
+ dst_int = (unsigned int *)&vec_out;
+
+ printf("%s: ", name);
+ printf("%016llx, %016llx @@ %016llx, %016llx ",
+ vdargs_x[i], vdargs_x[i+1],
+ vdargs_x[j], vdargs_x[j+1]);
+ if (isLE)
+ printf(" ==> %08x %08x %08x %08x\n", dst_int[2], dst_int[3],
+ dst_int[0], dst_int[1]);
+ else
+ printf(" ==> %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
+ dst_int[2], dst_int[3]);
+ }
+ }
+}
+
+/* Vector Word tests; two integer args, with double word result */
+
+static void test_av_wint_two_args_dres (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+
+ unsigned long long * dst;
+ int i,j;
+
+ for (i = 0; i < NB_VWARGS; i+=4) {
+ if (isLE)
+ vec_inA_wd = (vector unsigned int){ vwargs[i+3], vwargs[i+2], vwargs[i+1], vwargs[i] };
+ else
+ vec_inA_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
+ for (j = 0; j < NB_VWARGS; j+=4) {
+ if (isLE)
+ vec_inB_wd = (vector unsigned int){ vwargs[j+3], vwargs[j+2], vwargs[j+1], vwargs[j] };
+ else
+ vec_inB_wd = (vector unsigned int){ vwargs[j], vwargs[j+1], vwargs[j+2], vwargs[j+3] };
+ vec_out = (vector unsigned long long){ 0, 0 };
+
+ (*func)();
+ dst = (unsigned long long *)&vec_out;
+ printf("%s: ", name);
+ if (isLE)
+ printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
+ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[1], dst[0]);
+ else
+ printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
+ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
+ }
+ }
+}
+
+/* Vector Word tests; one input arg, with double word result */
+
+static void test_av_wint_one_arg_dres (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ unsigned long long * dst;
+ int i;
+ for (i = 0; i < NB_VWARGS; i+=4) {
+ if (isLE)
+ vec_inB_wd = (vector unsigned int){ vwargs[i+3], vwargs[i+2], vwargs[i+1], vwargs[i] };
+ else
+ vec_inB_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
+ vec_out = (vector unsigned long long){ 0, 0 };
+
+ (*func)();
+ dst = (unsigned long long *)&vec_out;
+ printf("%s: ", name);
+ if (isLE)
+ printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
+ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[1], dst[0]);
+ else
+ printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
+ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
+ }
+}
+
+
+static void test_int_stq_two_regs_imm16 (const char* name,
+ test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ /* Store quad word from register pair */
+ int offs, k;
+ HWord_t base;
+ Word_t *iargs_priv;
+
+ // private iargs table to store to, note storing pair of regs
+ iargs_priv = memalign16(2 * sizeof(Word_t));
+
+ base = (HWord_t)&iargs_priv[0];
+ for (k = 0; k < 2; k++) // clear array
+ iargs_priv[k] = 0;
+
+ offs = 0;
+
+ /* setup source register pair */
+ r14 = (HWord_t) 0xABCDEF0123456789ULL;
+ r15 = (HWord_t) 0x1133557722446688ULL;
+
+ r16 = base; // store to r16 + offs
+
+ (*func_IN)();
+
+#ifndef __powerpc64__
+ printf("%s %08x,%08x, %2d => "
+#else
+ printf("%s %016llx,%016llx, %3d => "
+#endif
+ "%016llx,%016llx)\n",
+ name, r14, r15, offs, iargs_priv[0], iargs_priv[1]);
+
+ if (verbose) printf("\n");
+ free(iargs_priv);
+}
+
+
+static void test_int_stq_three_regs (const char* name,
+ test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ /* Store quad word from register pair */
+ volatile uint32_t flags, xer;
+ int k;
+ HWord_t base;
+
+ base = (HWord_t)&mem_resv[0];
+ for (k = 0; k < 2; k++) // setup array for lqarx inst
+ mem_resv[k] = k;
+
+ /* setup source register pair for store */
+ r14 = ZERO;
+ r15 = ZERO;
+ r16 = base; // store to r16 + r17
+ r17 = ZERO;
+
+ /* In order for the store to occur, the lqarx instruction must first
+ * be used to load from the address thus creating a reservation at the
+ * memory address. The lqarx instruction is done in the test_stqcx(),
+ * then registers 14, r15 are changed to the data to be stored in memory
+ * by the stqcx instruction.
+ */
+ SET_CR_XER_ZERO;
+ (*func_IN)();
+ GET_CR_XER(flags,xer);
+#ifndef __powerpc64__
+ printf("%s %08x,%08x, => "
+#else
+ printf("%s %016llx,%016llx => "
+#endif
+ "%016llx,%016llx; CR=%08x\n",
+ name, r14, r15, mem_resv[0], mem_resv[1], flags);
+
+ if (verbose) printf("\n");
+}
+
+static void test_int_ldq_two_regs_imm16 (const char* name,
+ test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ /* load quad word from register pair */
+ volatile uint32_t flags, xer;
+ Word_t * mem_priv;
+ HWord_t base;
+
+ // private iargs table to store to, note storing pair of regs
+ mem_priv = memalign16(2 * sizeof(Word_t)); // want 128-bits
+
+ base = (HWord_t)&mem_priv[0];
+
+ mem_priv[0] = 0xAACCEE0011335577ULL;
+ mem_priv[1] = 0xABCDEF0123456789ULL;
+
+ r14 = 0;
+ r15 = 0;
+ r16 = base; // fetch from r16 + offs
+ SET_CR_XER_ZERO;
+ (*func_IN)();
+ GET_CR_XER(flags,xer);
+
+#ifndef __powerpc64__
+ printf("%s (0x%016llx, 0x%016llx) => (reg_pair = %08x,%08x)\n",
+#else
+ printf("%s (0x%016llx, 0x%016llx) => (reg_pair = 0x%016llx, 0x%016llx)\n",
+#endif
+ name, mem_priv[0], mem_priv[1], r14, r15);
+
+ if (verbose) printf("\n");
+
+ free(mem_priv);
+}
+
+static void test_int_ldq_three_regs (const char* name,
+ test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ /* load quad word from register pair */
+ HWord_t base;
+
+ base = (HWord_t)&mem_resv[0];
+
+ mem_resv[0] = 0xAACCEE0011335577ULL;
+ mem_resv[1] = 0xABCDEF0123456789ULL;
+
+ r14 = 0;
+ r15 = 0;
+ r16 = base; // fetch from r16 + r17
+ r17 = 0;
+
+ (*func_IN)();
+
+#ifndef __powerpc64__
+ printf("%s (0x%016llx, 0x%016llx) => (reg_pair = 0x%08x, 0x%08x)\n",
+#else
+ printf("%s (0x%016llx, 0x%016llx) => (reg_pair = 0x%016llx, 0x%016llx)\n",
+#endif
+ name, mem_resv[0], mem_resv[1], r14, r15);
+ if (verbose) printf("\n");
+
+}
+
+static void test_av_dint_three_args (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+
+ unsigned long long * dst;
+ int i,j, k;
+ int family = test_flags & PPC_FAMILY;
+ unsigned long long cin_vals[] = {
+ // First pair of ULLs have LSB=0, so cin is '0'.
+ // Second pair of ULLs have LSB=1, so cin is '1'.
+ 0xf000000000000000ULL, 0xf000000000000000ULL,
+ 0xf000000000000000ULL, 0xf000000000000001ULL
+ };
+ for (i = 0; i < NB_VDARGS - 1; i+=2) {
+ if (isLE)
+ vec_inA = (vector unsigned long long){ vdargs[i+1], vdargs[i] };
+ else
+ vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
+ for (j = 0; j < NB_VDARGS - 1; j+=2) {
+ if (isLE)
+ vec_inB = (vector unsigned long long){ vdargs[j+1], vdargs[j] };
+ else
+ vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
+ for (k = 0; k < 4 - 1; k+=2) {
+ if (family == PPC_ALTIVECQ) {
+ if (isLE)
+ vec_inC = (vector unsigned long long){ cin_vals[k+1], cin_vals[k] };
+ else
+ vec_inC = (vector unsigned long long){ cin_vals[k], cin_vals[k+1] };
+ } else {
+ if (isLE)
+ vec_inC = (vector unsigned long long){ vdargs[k+1], vdargs[k] };
+ else
+ vec_inC = (vector unsigned long long){ vdargs[k], vdargs[k+1] };
+ }
+ vec_out = (vector unsigned long long){ 0,0 };
+
+ (*func)();
+ dst = (unsigned long long*)&vec_out;
+ printf("%s: ", name);
+ if (family == PPC_ALTIVECQ) {
+ if (isLE)
+ printf("%016llx%016llx @@ %016llx%016llx @@ %llx ==> %016llx%016llx\n",
+ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], cin_vals[k+1],
+ dst[1], dst[0]);
+ else
+ printf("%016llx%016llx @@ %016llx%016llx @@ %llx ==> %016llx%016llx\n",
+ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], cin_vals[k+1],
+ dst[0], dst[1]);
+ } else {
+ printf("%016llx @@ %016llx @@ %016llx ", vdargs[i], vdargs[j], vdargs[k]);
+ if (isLE)
+ printf(" ==> %016llx\n", dst[1]);
+ else
+ printf(" ==> %016llx\n", dst[0]);
+ printf("\t%016llx @@ %016llx @@ %016llx ", vdargs[i+1], vdargs[j+1], vdargs[k+1]);
+ if (isLE)
+ printf(" ==> %016llx\n", dst[0]);
+ else
+ printf(" ==> %016llx\n", dst[1]);
+ }
+ }
+ }
+ }
+}
+
+
+/* The ALTIVEC_LOOPS and altive_loops defined below are used in do_tests.
+ * Add new values to the end; do not change order, since the altivec_loops
+ * array is indexed using the enumerated values defined by ALTIVEC_LOOPS.
+ */
+enum ALTIVEC_LOOPS {
+ ALTV_MOV,
+ ALTV_DINT,
+ ALTV_INT_DRES,
+ ALTV_DINT_IRES,
+ ALTV_ONE_INT_DRES,
+ ALTV_DINT_THREE_ARGS,
+ ALTV_DINT_ONE_ARG,
+ ALTV_SHA,
+ ATLV_BCD
+};
+
+static test_loop_t altivec_loops[] = {
+ &test_move_special,
+ &test_av_dint_two_args,
+ &test_av_wint_two_args_dres,
+ &test_av_dint_to_int_two_args,
+ &test_av_wint_one_arg_dres,
+ &test_av_dint_three_args,
+ &test_av_dint_one_arg,
+ &test_av_dint_one_arg_SHA,
+ &test_av_bcd,
+ NULL
+};
+
+/* Used in do_tests, indexed by flags->nb_args
+ Elements correspond to enum test_flags::num args
+*/
+static test_loop_t int_loops[] = {
+ /* The #defines for the family, number registers need the array
+ * to be properly indexed. This test is for the new ISA 2.0.7
+ * instructions. The infrastructure has been left for the momemnt
+ */
+ NULL, //&test_int_one_arg,
+ NULL, //&test_int_two_args,
+ NULL, //&test_int_three_args,
+ NULL, //&test_int_two_args,
+ NULL, //&test_int_one_reg_imm16,
+ NULL, //&test_int_one_reg_imm16,
+ NULL, //&test_int_special,
+ NULL, //&test_int_ld_one_reg_imm16,
+ NULL, //&test_int_ld_two_regs,
+ NULL, //&test_int_st_two_regs_imm16,
+ NULL, //&test_int_st_three_regs,
+ &test_int_stq_two_regs_imm16,
+ &test_int_ldq_two_regs_imm16,
+ &test_int_stq_three_regs,
+ &test_int_ldq_three_regs,
+};
+
+/* Used in do_tests, indexed by flags->nb_args
+ Elements correspond to enum test_flags::num args
+ Must have NULL for last entry.
+ */
+static test_loop_t float_loops[] = {
+ NULL,
+ &test_float_two_args,
+};
+
+
+static test_t tests_fa_ops_two[] = {
+ { &test_fmrgew , "fmrgew", },
+ { &test_fmrgow , "fmrgow", },
+ { NULL, NULL, },
+};
+
+static test_table_t all_tests[] = {
+ {
+ tests_move_ops_spe,
+ "PPC VSR special move insns",
+ PPC_ALTIVECD | PPC_MOV | PPC_ONE_ARG,
+ },
+ {
+ tests_aa_dbl_ops_two_args,
+ "PPC altivec double word integer insns (arith, compare) with two args",
+ PPC_ALTIVECD | PPC_ARITH | PPC_TWO_ARGS,
+ },
+ {
+ tests_aa_word_ops_two_args_dres,
+ "PPC altivec integer word instructions with two input args, double word result",
+ PPC_ALTIVEC | PPC_ARITH_DRES | PPC_TWO_ARGS,
+ },
+ {
+ tests_aa_dbl_to_int_two_args,
+ "PPC altivec doubleword-to-integer instructions with two input args, saturated integer result",
+ PPC_ALTIVECD | PPC_DOUBLE_IN_IRES | PPC_TWO_ARGS,
+ },
+ {
+ tests_aa_word_ops_one_arg_dres,
+ "PPC altivec integer word instructions with one input arg, double word result",
+ PPC_ALTIVEC | PPC_ARITH_DRES | PPC_ONE_ARG,
+ },
+ {
+ tests_istq_ops_two_i16,
+ "PPC store quadword insns\n with one register + one 16 bits immediate args with flags update",
+ 0x0001050c,
+ },
+ {
+ tests_ildq_ops_two_i16,
+ "PPC load quadword insns\n with one register + one 16 bits immediate args with flags update",
+ 0x0001050d,
+ },
+ {
+ tests_ldq_ops_three,
+ "PPC load quadword insns\n with three register args",
+ 0x0001050f,
+ },
+ {
+ tests_stq_ops_three,
+ "PPC store quadword insns\n with three register args",
+ 0x0001050e,
+ },
+ {
+ tests_fa_ops_two,
+ "PPC floating point arith insns with two args",
+ 0x00020102,
+ },
+ {
+ tests_aa_ops_three ,
+ "PPC altivec integer logical insns with three args",
+ 0x00060203,
+ },
+ {
+ tests_aa_dbl_ops_one_arg,
+ "PPC altivec one vector input arg, hex result",
+ 0x00060201,
+ },
+ {
+ tests_aa_SHA_ops,
+ "PPC altivec SSH insns",
+ 0x00040B01,
+ },
+ {
+ tests_aa_bcd_ops,
+ "PPC altivec BCD insns",
+ 0x00040B02,
+ },
+ {
+ tests_aa_quadword_two_args,
+ "PPC altivec quadword insns, two input args",
+ 0x00070102,
+ },
+ {
+ tests_aa_quadword_three_args,
+ "PPC altivec quadword insns, three input args",
+ 0x00070103
+ },
+ { NULL, NULL, 0x00000000, },
+};
+
+static void do_tests ( insn_sel_flags_t seln_flags,
+ char *filter)
+{
+ test_loop_t *loop;
+ test_t *tests;
+ int nb_args, type, family;
+ int i, j, n;
+ int exact;
+
+ exact = check_filter(filter);
+ n = 0;
+ for (i=0; all_tests[i].name != NULL; i++) {
+ nb_args = all_tests[i].flags & PPC_NB_ARGS;
+
+ /* Check number of arguments */
+ if ((nb_args == 1 && !seln_flags.one_arg) ||
+ (nb_args == 2 && !seln_flags.two_args) ||
+ (nb_args == 3 && !seln_flags.three_args)){
+ continue;
+ }
+ /* Check instruction type */
+ type = all_tests[i].flags & PPC_TYPE;
+ if ((type == PPC_ARITH && !seln_flags.arith) ||
+ (type == PPC_LOGICAL && !seln_flags.logical) ||
+ (type == PPC_COMPARE && !seln_flags.compare) ||
+ (type == PPC_LDST && !seln_flags.ldst) ||
+ (type == PPC_MOV && !seln_flags.ldst) ||
+ (type == PPC_POPCNT && !seln_flags.arith)) {
+ continue;
+ }
+
+ /* Check instruction family */
+ family = all_tests[i].flags & PPC_FAMILY;
+ if ((family == PPC_INTEGER && !seln_flags.integer) ||
+ (family == PPC_FLOAT && !seln_flags.floats) ||
+ (family == PPC_ALTIVEC && !seln_flags.altivec) ||
+ (family == PPC_ALTIVECD && !seln_flags.altivec) ||
+ (family == PPC_ALTIVECQ && !seln_flags.altivec) ||
+ (family == PPC_FALTIVEC && !seln_flags.faltivec)) {
+ continue;
+ }
+ /* Check flags update */
+ if (((all_tests[i].flags & PPC_CR) && seln_flags.cr == 0) ||
+ (!(all_tests[i].flags & PPC_CR) && seln_flags.cr == 1))
+ continue;
+
+ /* All passed, do the tests */
+ tests = all_tests[i].tests;
+
+ loop = NULL;
+
+ /* Select the test loop */
+ switch (family) {
+ case PPC_INTEGER:
+ mem_resv = memalign16(2 * sizeof(HWord_t)); // want 128-bits
+ loop = &int_loops[nb_args - 1];
+ break;
+
+ case PPC_FLOAT:
+ loop = &float_loops[nb_args - 1];
+ break;
+
+ case PPC_ALTIVECQ:
+ if (nb_args == 2)
+ loop = &altivec_loops[ALTV_DINT];
+ else if (nb_args == 3)
+ loop = &altivec_loops[ALTV_DINT_THREE_ARGS];
+ break;
+ case PPC_ALTIVECD:
+ switch (type) {
+ case PPC_MOV:
+ loop = &altivec_loops[ALTV_MOV];
+ break;
+ case PPC_ARITH:
+ loop = &altivec_loops[ALTV_DINT];
+ break;
+ case PPC_DOUBLE_IN_IRES:
+ loop = &altivec_loops[ALTV_DINT_IRES];
+ break;
+ case PPC_LOGICAL:
+ if (nb_args == 3)
+ loop = &altivec_loops[ALTV_DINT_THREE_ARGS];
+ else if (nb_args ==1)
+ loop = &altivec_loops[ALTV_DINT_ONE_ARG];
+ break;
+ default:
+ printf("No altivec test defined for type %x\n", type);
+ }
+ break;
+
+ case PPC_FALTIVEC:
+ printf("Currently there are no floating altivec tests in this testsuite.\n");
+ break;
+
+ case PPC_ALTIVEC:
+ switch (type) {
+ case PPC_ARITH_DRES:
+ {
+ switch (nb_args) {
+ case 1:
+ loop = &altivec_loops[ALTV_ONE_INT_DRES];
+ break;
+ case 2:
+ loop = &altivec_loops[ALTV_INT_DRES];
+ break;
+ default:
+ printf("No altivec test defined for number args %d\n", nb_args);
+ }
+ break;
+ }
+ case PPC_SHA_OR_BCD:
+ if (nb_args == 1)
+ loop = &altivec_loops[ALTV_SHA];
+ else
+ loop = &altivec_loops[ATLV_BCD];
+ break;
+ default:
+ printf("No altivec test defined for type %x\n", type);
+ }
+ break;
+
+ default:
+ printf("ERROR: unknown insn family %08x\n", family);
+ continue;
+ }
+ if (1 || verbose > 0)
+ for (j=0; tests[j].name != NULL; j++) {
+ if (check_name(tests[j].name, filter, exact)) {
+ if (verbose > 1)
+ printf("Test instruction %s\n", tests[j].name);
+ if (loop != NULL)
+ (*loop)(tests[j].name, tests[j].func, all_tests[i].flags);
+ printf("\n");
+ n++;
+ }
+ }
+ if (verbose) printf("\n");
+ }
+ printf("All done. Tested %d different instructions\n", n);
+}
+
+
+static void usage (void)
+{
+ fprintf(stderr,
+ "Usage: jm-insns [OPTION]\n"
+ "\t-i: test integer instructions (default)\n"
+ "\t-f: test floating point instructions\n"
+ "\t-a: test altivec instructions\n"
+ "\t-A: test all (int, fp, altivec) instructions\n"
+ "\t-v: be verbose\n"
+ "\t-h: display this help and exit\n"
+ );
+}
+
+#endif
+
+int main (int argc, char **argv)
+{
+#ifdef HAS_ISA_2_07
+ /* Simple usage:
+ ./jm-insns -i => int insns
+ ./jm-insns -f => fp insns
+ ./jm-insns -a => av insns
+ ./jm-insns -A => int, fp and avinsns
+ */
+ char *filter = NULL;
+ insn_sel_flags_t flags;
+ int c;
+
+ // Args
+ flags.one_arg = 1;
+ flags.two_args = 1;
+ flags.three_args = 1;
+ // Type
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
+ // Family
+ flags.integer = 0;
+ flags.floats = 0;
+ flags.altivec = 0;
+ flags.faltivec = 0;
+ // Flags
+ flags.cr = 2;
+
+ while ((c = getopt(argc, argv, "ifahvA")) != -1) {
+ switch (c) {
+ case 'i':
+ flags.integer = 1;
+ break;
+ case 'f':
+ build_fargs_table();
+ flags.floats = 1;
+ break;
+ case 'a':
+ flags.altivec = 1;
+ flags.faltivec = 1;
+ break;
+ case 'A':
+ flags.integer = 1;
+ flags.floats = 1;
+ flags.altivec = 1;
+ flags.faltivec = 1;
+ break;
+ case 'h':
+ usage();
+ return 0;
+ case 'v':
+ verbose++;
+ break;
+ default:
+ usage();
+ fprintf(stderr, "Unknown argument: '%c'\n", c);
+ return 1;
+ }
+ }
+
+ arg_list_size = 0;
+
+ build_vargs_table();
+ if (verbose > 1) {
+ printf("\nInstruction Selection:\n");
+ printf(" n_args: \n");
+ printf(" one_arg = %d\n", flags.one_arg);
+ printf(" two_args = %d\n", flags.two_args);
+ printf(" three_args = %d\n", flags.three_args);
+ printf(" type: \n");
+ printf(" arith = %d\n", flags.arith);
+ printf(" logical = %d\n", flags.logical);
+ printf(" compare = %d\n", flags.compare);
+ printf(" ldst = %d\n", flags.ldst);
+ printf(" family: \n");
+ printf(" integer = %d\n", flags.integer);
+ printf(" floats = %d\n", flags.floats);
+ printf(" altivec = %d\n", flags.altivec);
+ printf(" faltivec = %d\n", flags.faltivec);
+ printf(" cr update: \n");
+ printf(" cr = %d\n", flags.cr);
+ printf("\n");
+ }
+
+ do_tests( flags, filter );
+#else
+ printf("NO ISA 2.07 SUPPORT\n");
+#endif
+ return 0;
+}
diff --git a/none/tests/ppc32/test_isa_2_07_part2.c b/none/tests/ppc32/test_isa_2_07_part2.c
deleted file mode 120000
index 3eb5caf..0000000
--- a/none/tests/ppc32/test_isa_2_07_part2.c
+++ /dev/null
@@ -1 +0,0 @@
-../ppc64/test_isa_2_07_part2.c
\ No newline at end of file
diff --git a/none/tests/ppc32/test_isa_2_07_part2.c b/none/tests/ppc32/test_isa_2_07_part2.c
new file mode 100644
index 0000000..a2458a9
--- /dev/null
+++ b/none/tests/ppc32/test_isa_2_07_part2.c
@@ -0,0 +1,1455 @@
+/* Copyright (C) 2013 IBM
+
+ Authors: Carl Love <carll@us.ibm.com>
+ Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+
+ This program is based heavily on the test_isa_2_06_part*.c source files.
+ */
+
+#include <stdio.h>
+
+#ifdef HAS_ISA_2_07
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <malloc.h>
+#include <altivec.h>
+#include <math.h>
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif /* __powerpc64__ */
+
+#ifdef VGP_ppc64le_linux
+#define isLE 1
+#else
+#define isLE 0
+#endif
+
+register HWord_t r14 __asm__ ("r14");
+register HWord_t r15 __asm__ ("r15");
+register HWord_t r16 __asm__ ("r16");
+register HWord_t r17 __asm__ ("r17");
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+
+static volatile unsigned int cond_reg;
+
+#define True 1
+#define False 0
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+typedef unsigned char Bool;
+
+
+/* These functions below that construct a table of floating point
+ * values were lifted from none/tests/ppc32/jm-insns.c.
+ */
+
+#if defined (DEBUG_ARGS_BUILD)
+#define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define AB_DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+static inline void register_farg (void *farg,
+ int s, uint16_t _exp, uint64_t mant)
+{
+ uint64_t tmp;
+
+ tmp = ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
+ *(uint64_t *)farg = tmp;
+ AB_DPRINTF("%d %03x %013llx => %016llx %0e\n",
+ s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
+}
+
+static inline void register_sp_farg (void *farg,
+ int s, uint16_t _exp, uint32_t mant)
+{
+ uint32_t tmp;
+ tmp = ((uint32_t)s << 31) | ((uint32_t)_exp << 23) | mant;
+ *(uint32_t *)farg = tmp;
+}
+
+
+typedef struct fp_test_args {
+ int fra_idx;
+ int frb_idx;
+} fp_test_args_t;
+
+static int nb_special_fargs;
+static double * spec_fargs;
+static float * spec_sp_fargs;
+
+static void build_special_fargs_table(void)
+{
+ /*
+ * Double precision:
+ * Sign goes from zero to one (1 bit)
+ * Exponent goes from 0 to ((1 << 12) - 1) (11 bits)
+ * Mantissa goes from 1 to ((1 << 52) - 1) (52 bits)
+ * + special values:
+ * +0.0 : 0 0x000 0x0000000000000 => 0x0000000000000000
+ * -0.0 : 1 0x000 0x0000000000000 => 0x8000000000000000
+ * +infinity : 0 0x7FF 0x0000000000000 => 0x7FF0000000000000
+ * -infinity : 1 0x7FF 0x0000000000000 => 0xFFF0000000000000
+ * +SNaN : 0 0x7FF 0x7FFFFFFFFFFFF => 0x7FF7FFFFFFFFFFFF
+ * -SNaN : 1 0x7FF 0x7FFFFFFFFFFFF => 0xFFF7FFFFFFFFFFFF
+ * +QNaN : 0 0x7FF 0x8000000000000 => 0x7FF8000000000000
+ * -QNaN : 1 0x7FF 0x8000000000000 => 0xFFF8000000000000
+ * (8 values)
+ *
+ * Single precision
+ * Sign: 1 bit
+ * Exponent: 8 bits
+ * Mantissa: 23 bits
+ * +0.0 : 0 0x00 0x000000 => 0x00000000
+ * -0.0 : 1 0x00 0x000000 => 0x80000000
+ * +infinity : 0 0xFF 0x000000 => 0x7F800000
+ * -infinity : 1 0xFF 0x000000 => 0xFF800000
+ * +SNaN : 0 0xFF 0x3FFFFF => 0x7FBFFFFF
+ * -SNaN : 1 0xFF 0x3FFFFF => 0xFFBFFFFF
+ * +QNaN : 0 0xFF 0x400000 => 0x7FC00000
+ * -QNaN : 1 0xFF 0x400000 => 0xFFC00000
+ */
+
+ uint64_t mant;
+ uint32_t mant_sp;
+ uint16_t _exp;
+ int s;
+ int j, i = 0;
+
+ if (spec_fargs)
+ return;
+
+ spec_fargs = malloc( 20 * sizeof(double) );
+ spec_sp_fargs = malloc( 20 * sizeof(float) );
+
+ // #0
+ s = 0;
+ _exp = 0x3fd;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #1
+ s = 0;
+ _exp = 0x404;
+ mant = 0xf000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #2
+ s = 0;
+ _exp = 0x001;
+ mant = 0x8000000b77501ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #3
+ s = 0;
+ _exp = 0x7fe;
+ mant = 0x800000000051bULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #4
+ s = 0;
+ _exp = 0x012;
+ mant = 0x3214569900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* Special values */
+ /* +0.0 : 0 0x000 0x0000000000000 */
+ // #5
+ s = 0;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -0.0 : 1 0x000 0x0000000000000 */
+ // #6
+ s = 1;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +infinity : 0 0x7FF 0x0000000000000 */
+ // #7
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -infinity : 1 0x7FF 0x0000000000000 */
+ // #8
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /*
+ * This comment applies to values #9 and #10 below:
+ * When src is a SNaN, it's converted to a QNaN first before rounding to single-precision,
+ * so we can't just copy the double-precision value to the corresponding slot in the
+ * single-precision array (i.e., in the loop at the end of this function). Instead, we
+ * have to manually set the bits using register_sp_farg().
+ */
+
+ /* +SNaN : 0 0x7FF 0x7FFFFFFFFFFFF */
+ // #9
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+ _exp = 0xff;
+ mant_sp = 0x3FFFFF;
+ register_sp_farg(&spec_sp_fargs[i-1], s, _exp, mant_sp);
+
+ /* -SNaN : 1 0x7FF 0x7FFFFFFFFFFFF */
+ // #10
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+ _exp = 0xff;
+ mant_sp = 0x3FFFFF;
+ register_sp_farg(&spec_sp_fargs[i-1], s, _exp, mant_sp);
+
+ /* +QNaN : 0 0x7FF 0x8000000000000 */
+ // #11
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -QNaN : 1 0x7FF 0x8000000000000 */
+ // #12
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* denormalized value */
+ // #13
+ s = 1;
+ _exp = 0x000;
+ mant = 0x8340000078000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* Negative finite number */
+ // #14
+ s = 1;
+ _exp = 0x40d;
+ mant = 0x0650f5a07b353ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* A few positive finite numbers ... */
+ // #15
+ s = 0;
+ _exp = 0x412;
+ mant = 0x32585a9900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #16
+ s = 0;
+ _exp = 0x413;
+ mant = 0x82511a2000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #17
+ s = 0;
+ _exp = 0x403;
+ mant = 0x12ef5a9300000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #18
+ s = 0;
+ _exp = 0x405;
+ mant = 0x14bf5d2300000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #19
+ s = 0;
+ _exp = 0x409;
+ mant = 0x76bf982440000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+
+ nb_special_fargs = i;
+ for (j = 0; j < i; j++) {
+ if (!(j == 9 || j == 10))
+ spec_sp_fargs[j] = spec_fargs[j];
+ }
+}
+
+static unsigned int vstg[] __attribute__ ((aligned (16))) = { 0, 0, 0,0,
+ 0, 0, 0, 0 };
+
+
+static unsigned int viargs[] __attribute__ ((aligned (16))) = { 0x80000001,
+ 0x89abcdef,
+ 0x00112233,
+ 0x74556677,
+ 0x00001abb,
+ 0x00000001,
+ 0x31929394,
+ 0xa1a2a3a4,
+};
+#define NUM_VIARGS_INTS (sizeof viargs/sizeof viargs[0])
+#define NUM_VIARGS_VECS (NUM_VIARGS_INTS/4)
+
+
+static unsigned long long vdargs[] __attribute__ ((aligned (16))) = {
+ 0x0102030405060708ULL,
+ 0x090A0B0C0E0D0E0FULL,
+ 0xF1F2F3F4F5F6F7F8ULL,
+ 0xF9FAFBFCFEFDFEFFULL
+};
+#define NUM_VDARGS_INTS (sizeof vdargs/sizeof vdargs[0])
+#define NUM_VDARGS_VECS (NUM_VDARGS_INTS/2)
+
+typedef void (*test_func_t)(void);
+
+struct test_table
+{
+ test_func_t test_category;
+ char * name;
+};
+
+
+typedef enum {
+ SINGLE_TEST,
+ SINGLE_TEST_SINGLE_RES,
+ DOUBLE_TEST,
+ DOUBLE_TEST_SINGLE_RES
+} precision_type_t;
+#define IS_DP_RESULT(x) ((x == SINGLE_TEST) || (x == DOUBLE_TEST))
+
+typedef enum {
+ VX_FP_SMAS, // multiply add single precision result
+ VX_FP_SMSS, // multiply sub single precision result
+ VX_FP_SNMAS, // negative multiply add single precision result
+ VX_FP_SNMSS, // negative multiply sub single precision result
+ VX_FP_OTHER,
+ VX_CONV_WORD,
+ VX_ESTIMATE,
+ VX_CONV_TO_SINGLE,
+ VX_CONV_TO_DOUBLE,
+ VX_SCALAR_CONV_TO_WORD,
+ VX_SCALAR_SP_TO_VECTOR_SP,
+ VX_DEFAULT
+} vx_fp_test_type;
+
+typedef enum {
+ VSX_LOAD = 1,
+ VSX_LOAD_SPLAT,
+ VSX_STORE,
+} vsx_ldst_type;
+
+typedef enum {
+ VSX_AND = 1,
+ VSX_NAND,
+ VSX_ANDC,
+ VSX_OR,
+ VSX_ORC,
+ VSX_NOR,
+ VSX_XOR,
+ VSX_EQV,
+} vsx_log_op;
+
+struct vx_fp_test1
+{
+ test_func_t test_func;
+ const char *name;
+ fp_test_args_t * targs;
+ int num_tests;
+ vx_fp_test_type test_type;
+ };
+
+struct ldst_test
+{
+ test_func_t test_func;
+ const char *name;
+ precision_type_t precision;
+ void * base_addr;
+ uint32_t offset;
+ vsx_ldst_type type;
+};
+
+struct vx_fp_test2
+{
+ test_func_t test_func;
+ const char *name;
+ fp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ vx_fp_test_type test_type;
+ const char * op;
+};
+
+struct xs_conv_test
+{
+ test_func_t test_func;
+ const char *name;
+ int num_tests;
+};
+
+struct simple_test
+{
+ test_func_t test_func;
+ const char *name;
+};
+
+struct vsx_logic_test
+{
+ test_func_t test_func;
+ const char *name;
+ vsx_log_op op;
+};
+
+typedef struct vsx_logic_test logic_test_t;
+typedef struct ldst_test ldst_test_t;
+typedef struct simple_test xs_conv_test_t;
+typedef struct vx_fp_test1 vx_fp_test_basic_t;
+typedef struct vx_fp_test2 vx_fp_test2_t;
+typedef struct test_table test_table_t;
+
+
+static vector unsigned int vec_out, vec_inA, vec_inB;
+
+static void test_xscvdpspn(void)
+{
+ __asm__ __volatile__ ("xscvdpspn %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvspdpn(void)
+{
+ __asm__ __volatile__ ("xscvspdpn %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static int do_asp;
+static void test_xsmadds(void)
+{
+ if (do_asp)
+ __asm__ __volatile__ ("xsmaddasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsmaddmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsmsubs(void)
+{
+ if (do_asp)
+ __asm__ __volatile__ ("xsmsubasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsmsubmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xscvsxdsp (void)
+{
+ __asm__ __volatile__ ("xscvsxdsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvuxdsp (void)
+{
+ __asm__ __volatile__ ("xscvuxdsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsnmadds(void)
+{
+ if (do_asp)
+ __asm__ __volatile__ ("xsnmaddasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsnmaddmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsnmsubs(void)
+{
+ if (do_asp)
+ __asm__ __volatile__ ("xsnmsubasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsnmsubmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_stxsspx(void)
+{
+ __asm__ __volatile__ ("stxsspx %x0, %1, %2" : : "wa" (vec_inA), "b" (r14),"r" (r15));
+}
+
+static void test_stxsiwx(void)
+{
+ __asm__ __volatile__ ("stxsiwx %x0, %1, %2" : : "wa" (vec_inA), "b" (r14),"r" (r15));
+}
+
+static void test_lxsiwax(void)
+{
+ __asm__ __volatile__ ("lxsiwax %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void test_lxsiwzx(void)
+{
+ __asm__ __volatile__ ("lxsiwzx %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void test_lxsspx(void)
+{
+ __asm__ __volatile__ ("lxsspx %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void test_xssqrtsp(void)
+{
+ __asm__ __volatile__ ("xssqrtsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrsqrtesp(void)
+{
+ __asm__ __volatile__ ("xsrsqrtesp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+/* Three argument instuctions */
+static void test_xxleqv(void)
+{
+ __asm__ __volatile__ ("xxleqv %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxlorc(void)
+{
+ __asm__ __volatile__ ("xxlorc %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxlnand(void)
+{
+ __asm__ __volatile__ ("xxlnand %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsaddsp(void)
+{
+ __asm__ __volatile__ ("xsaddsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA), "wa" (vec_inB));
+}
+
+static void test_xssubsp(void)
+{
+ __asm__ __volatile__ ("xssubsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA), "wa" (vec_inB));
+}
+
+static void test_xsdivsp(void)
+{
+ __asm__ __volatile__ ("xsdivsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA), "wa" (vec_inB));
+}
+
+static void test_xsmulsp(void)
+{
+ __asm__ __volatile__ ("xsmulsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsresp(void)
+{
+ __asm__ __volatile__ ("xsresp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+static void test_xsrsp(void)
+{
+ __asm__ __volatile__ ("xsrsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+fp_test_args_t vx_math_tests[] = {
+ {8, 8},
+ {8, 14},
+ {8, 6},
+ {8, 5},
+ {8, 4},
+ {8, 7},
+ {8, 9},
+ {8, 11},
+ {14, 8},
+ {14, 14},
+ {14, 6},
+ {14, 5},
+ {14, 4},
+ {14, 7},
+ {14, 9},
+ {14, 11},
+ {6, 8},
+ {6, 14},
+ {6, 6},
+ {6, 5},
+ {6, 4},
+ {6, 7},
+ {6, 9},
+ {6, 11},
+ {5, 8},
+ {5, 14},
+ {5, 6},
+ {5, 5},
+ {5, 4},
+ {5, 7},
+ {5, 9},
+ {5, 11},
+ {4, 8},
+ {4, 14},
+ {4, 6},
+ {4, 5},
+ {4, 1},
+ {4, 7},
+ {4, 9},
+ {4, 11},
+ {7, 8},
+ {7, 14},
+ {7, 6},
+ {7, 5},
+ {7, 4},
+ {7, 7},
+ {7, 9},
+ {7, 11},
+ {10, 8},
+ {10, 14},
+ {10, 6},
+ {10, 5},
+ {10, 4},
+ {10, 7},
+ {10, 9},
+ {10, 11},
+ {12, 8},
+ {12, 14},
+ {12, 6},
+ {12, 5},
+ {12, 4},
+ {12, 7},
+ {12, 9},
+ {12, 11},
+ {8, 8},
+ {8, 14},
+ {8, 6},
+ {8, 5},
+ {8, 4},
+ {8, 7},
+ {8, 9},
+ {8, 11},
+ {14, 8},
+ {14, 14},
+ {14, 6},
+ {14, 5},
+ {14, 4},
+ {14, 7},
+ {14, 9},
+ {14, 11},
+ {6, 8},
+ {6, 14},
+ {6, 6},
+ {6, 5},
+ {6, 4},
+ {6, 7},
+ {6, 9},
+ {6, 11},
+ {5, 8},
+ {5, 14},
+ {5, 6},
+ {5, 5},
+ {5, 4},
+ {5, 7},
+ {5, 9},
+ {5, 11},
+ {4, 8},
+ {4, 14},
+ {4, 6},
+ {4, 5},
+ {4, 1},
+ {4, 7},
+ {4, 9},
+ {4, 11},
+ {7, 8},
+ {7, 14},
+ {7, 6},
+ {7, 5},
+ {7, 4},
+ {7, 7},
+ {7, 9},
+ {7, 11},
+ {10, 8},
+ {10, 14},
+ {10, 6},
+ {10, 5},
+ {10, 4},
+ {10, 7},
+ {10, 9},
+ {10, 11},
+ {12, 8},
+ {12, 14},
+ {12, 6},
+ {12, 5},
+ {12, 4},
+ {12, 7},
+ {12, 9},
+ {12, 11}
+};
+
+// These are all double precision inputs with double word outputs (mostly converted to single precision)
+static vx_fp_test_basic_t vx_fp_tests[] = {
+ { &test_xsmadds, "xsmadd", vx_math_tests, 64, VX_FP_SMAS},
+ { &test_xsmsubs, "xsmsub", vx_math_tests, 64, VX_FP_SMSS},
+ { &test_xsmulsp, "xsmulsp", vx_math_tests, 64, VX_FP_OTHER},
+ { &test_xsdivsp, "xsdivsp", vx_math_tests, 64, VX_FP_OTHER},
+ { &test_xsnmadds, "xsnmadd", vx_math_tests, 64, VX_FP_SNMAS},
+ { &test_xsnmsubs, "xsnmsub", vx_math_tests, 64, VX_FP_SNMSS},
+ { NULL, NULL, NULL, 0, 0 }
+};
+
+static vx_fp_test2_t
+vsx_one_fp_arg_tests[] = {
+ { &test_xscvdpspn, "xscvdpspn", NULL, 20, DOUBLE_TEST_SINGLE_RES, VX_SCALAR_SP_TO_VECTOR_SP, "conv"},
+ { &test_xscvspdpn, "xscvspdpn", NULL, 20, SINGLE_TEST, VX_DEFAULT, "conv"},
+ { &test_xsresp, "xsresp", NULL, 20, DOUBLE_TEST, VX_ESTIMATE, "1/x"},
+ { &test_xsrsp, "xsrsp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "round"},
+ { &test_xsrsqrtesp, "xsrsqrtesp", NULL, 20, DOUBLE_TEST, VX_ESTIMATE, "1/sqrt"},
+ { &test_xssqrtsp, "xssqrtsp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "sqrt"},
+ { NULL, NULL, NULL, 0, 0, 0, NULL}
+};
+
+// These are all double precision inputs with double word outputs (mostly converted to single precision)
+static vx_fp_test_basic_t
+vx_simple_scalar_fp_tests[] = {
+ { &test_xssubsp, "xssubsp", vx_math_tests, 64, VX_DEFAULT},
+ { &test_xsaddsp, "xsaddsp", vx_math_tests, 64, VX_DEFAULT},
+ { NULL, NULL, NULL, 0 , 0}
+};
+
+static ldst_test_t
+ldst_tests[] = {
+ { &test_stxsspx, "stxsspx", DOUBLE_TEST_SINGLE_RES, vstg, 0, VSX_STORE },
+ { &test_stxsiwx, "stxsiwx", SINGLE_TEST_SINGLE_RES, vstg, 4, VSX_STORE },
+ { &test_lxsiwax, "lxsiwax", SINGLE_TEST, viargs, 0, VSX_LOAD },
+ { &test_lxsiwzx, "lxsiwzx", SINGLE_TEST, viargs, 4, VSX_LOAD },
+ { &test_lxsspx, "lxsspx", SINGLE_TEST, NULL, 0, VSX_LOAD },
+ { NULL, NULL, 0, NULL, 0, 0 } };
+
+static xs_conv_test_t
+xs_conv_tests[] = {
+ { &test_xscvsxdsp, "xscvsxdsp"},
+ { &test_xscvuxdsp, "xscvuxdsp"},
+ { NULL, NULL}
+};
+
+static logic_test_t
+logic_tests[] = {
+ { &test_xxleqv, "xxleqv", VSX_EQV },
+ { &test_xxlorc, "xxlorc", VSX_ORC },
+ { &test_xxlnand, "xxlnand", VSX_NAND },
+ { NULL, NULL}
+};
+
+Bool check_reciprocal_estimate(Bool is_rsqrte, int idx, int output_vec_idx)
+{
+ /* NOTE:
+ * This function has been verified only with the xsresp and xsrsqrtes instructions.
+ *
+ * Technically, the number of bits of precision for xsresp and xsrsqrtesp is
+ * 14 bits (14 = log2 16384). However, the VEX emulation of these instructions
+ * does an actual reciprocal calculation versus estimation, so the answer we get back from
+ * valgrind can easily differ from the estimate in the lower bits (within the 14 bits of
+ * precision) and the estimate may still be within expected tolerances. On top of that,
+ * we can't count on these estimates always being the same across implementations.
+ * For example, with the fre[s] instruction (which should be correct to within one part
+ * in 256 -- i.e., 8 bits of precision) . . . When approximating the value 1.0111_1111_1111,
+ * one implementation could return 1.0111_1111_0000 and another implementation could return
+ * 1.1000_0000_0000. Both estimates meet the 1/256 accuracy requirement, but share only a
+ * single bit in common.
+ *
+ * The upshot is we can't validate the VEX output for these instructions by comparing against
+ * stored bit patterns. We must check that the result is within expected tolerances.
+ */
+
+ /* A mask to be used for validation as a last resort.
+ * Only use 12 bits of precision for reasons discussed above.
+ */
+#define VSX_RECIP_ESTIMATE_MASK_SP 0xFFFF8000
+
+
+ Bool result = False;
+ double src_dp, res_dp;
+ float calc_diff = 0;
+ float real_diff = 0;
+ double recip_divisor;
+ float div_result;
+ float calc_diff_tmp;
+
+ src_dp = res_dp = 0;
+ Bool src_is_negative = False;
+ Bool res_is_negative = False;
+ unsigned long long * dst_dp = NULL;
+ unsigned long long * src_dp_ull;
+ dst_dp = (unsigned long long *) &vec_out;
+ src_dp = spec_fargs[idx];
+ src_dp_ull = (unsigned long long *) &src_dp;
+ src_is_negative = (*src_dp_ull & 0x8000000000000000ULL) ? True : False;
+ res_is_negative = (dst_dp[output_vec_idx] & 0x8000000000000000ULL) ? True : False;
+ memcpy(&res_dp, &dst_dp[output_vec_idx], 8);
+
+
+ // Below are common rules
+ if (isnan(src_dp))
+ return isnan(res_dp);
+ if (fpclassify(src_dp) == FP_ZERO)
+ return isinf(res_dp);
+ if (!src_is_negative && isinf(src_dp))
+ return !res_is_negative && (fpclassify(res_dp) == FP_ZERO);
+ if (is_rsqrte) {
+ if (src_is_negative)
+ return isnan(res_dp);
+ } else {
+ if (src_is_negative && isinf(src_dp))
+ return res_is_negative && (fpclassify(res_dp) == FP_ZERO);
+ }
+
+ if (is_rsqrte)
+ recip_divisor = sqrt(src_dp);
+ else
+ recip_divisor = src_dp;
+
+ /* The instructions handled by this function take a double precision
+ * input, perform a reciprocal estimate in double-precision, round
+ * the result to single precision and store into the destination
+ * register in double precision format. So, to check the result
+ * for accuracy, we use float (single precision) values.
+ */
+ div_result = 1.0/recip_divisor;
+ calc_diff_tmp = recip_divisor * 16384.0;
+ if (isnormal(calc_diff_tmp)) {
+ calc_diff = fabs(1.0/calc_diff_tmp);
+ real_diff = fabs((float)res_dp - div_result);
+ result = ( ( res_dp == div_result )
+ || ( real_diff <= calc_diff ) );
+#if FRES_DEBUG
+ unsigned int * dv = (unsigned int *)&div_result;
+ unsigned int * rd = (unsigned int *)&real_diff;
+ unsigned int * cd = (unsigned int *)&calc_diff;
+ printf("\n\t {computed div_result: %08x; real_diff: %08x; calc_diff: %08x}\n",
+ *dv, *rd, *cd);
+#endif
+
+ } else {
+ /* Unable to compute theoretical difference, so we fall back to masking out
+ * un-precise bits.
+ */
+ unsigned int * div_result_sp = (unsigned int *)&div_result;
+ float res_sp = (float)res_dp;
+ unsigned int * dst_sp = (unsigned int *)&res_sp;
+#if FRES_DEBUG
+ unsigned int * calc_diff_tmp_sp = (unsigned int *)&calc_diff_tmp;
+ printf("Unable to compute theoretical difference, so we fall back to masking\n");
+ printf("\tcalc_diff_tmp: %08x; div_result: %08x; vector result (sp): %08x\n",
+ *calc_diff_tmp_sp, *div_result_sp, *dst_sp);
+#endif
+ result = (*dst_sp & VSX_RECIP_ESTIMATE_MASK_SP) == (*div_result_sp & VSX_RECIP_ESTIMATE_MASK_SP);
+ }
+ return result;
+}
+
+static void test_vx_fp_ops(void)
+{
+
+ test_func_t func;
+ int k;
+ char * test_name = (char *)malloc(20);
+ void * vecA_void_ptr, * vecB_void_ptr, * vecOut_void_ptr;
+
+ if (isLE) {
+ vecA_void_ptr = (void *)&vec_inA + 8;
+ vecB_void_ptr = (void *)&vec_inB + 8;
+ vecOut_void_ptr = (void *)&vec_out + 8;
+ } else {
+ vecA_void_ptr = (void *)&vec_inA;
+ vecB_void_ptr = (void *)&vec_inB;
+ vecOut_void_ptr = (void *)&vec_out;
+ }
+
+ k = 0;
+ build_special_fargs_table();
+ while ((func = vx_fp_tests[k].test_func)) {
+ int i, repeat = 0;
+ unsigned long long * frap, * frbp, * dst;
+ vx_fp_test_basic_t test_group = vx_fp_tests[k];
+ vx_fp_test_type test_type = test_group.test_type;
+
+ switch (test_type) {
+ case VX_FP_SMAS:
+ case VX_FP_SMSS:
+ case VX_FP_SNMAS:
+ case VX_FP_SNMSS:
+ if (test_type == VX_FP_SMAS)
+ strcpy(test_name, "xsmadd");
+ else if (test_type == VX_FP_SMSS)
+ strcpy(test_name, "xsmsub");
+ else if (test_type == VX_FP_SNMAS)
+ strcpy(test_name, "xsnmadd");
+ else
+ strcpy(test_name, "xsnmsub");
+
+ if (!repeat) {
+ repeat = 1;
+ strcat(test_name, "asp");
+ do_asp = 1;
+ }
+ break;
+ case VX_FP_OTHER:
+ strcpy(test_name, test_group.name);
+ break;
+ default:
+ printf("ERROR: Invalid VX FP test type %d\n", test_type);
+ exit(1);
+ }
+
+again:
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int * inA, * inB, * pv;
+
+ fp_test_args_t aTest = test_group.targs[i];
+ inA = (unsigned int *)&spec_fargs[aTest.fra_idx];
+ inB = (unsigned int *)&spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ int idx;
+ unsigned long long vsr_XT;
+ pv = (unsigned int *)&vec_out;
+
+ // Only need to copy one doubleword into each vector's element 0
+ memcpy(vecA_void_ptr, inA, 8);
+ memcpy(vecB_void_ptr, inB, 8);
+
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (test_type != VX_FP_OTHER) {
+ /* Then we need a third src argument, which is stored in element 0 of
+ * VSX[XT] -- i.e., vec_out. For the xs<ZZZ>mdp cases, VSX[XT] holds
+ * src3 and VSX[XB] holds src2; for the xs<ZZZ>adp cases, VSX[XT] holds
+ * src2 and VSX[XB] holds src3. The fp_test_args_t that holds the test
+ * data (input args, result) contain only two inputs, so I arbitrarily
+ * use spec_fargs elements 4 and 14 (alternating) for the third source
+ * argument. We can use the same input data for a given pair of
+ * adp/mdp-type instructions by swapping the src2 and src3 arguments; thus
+ * the expected result should be the same.
+ */
+ int extra_arg_idx;
+ if (i % 2)
+ extra_arg_idx = 4;
+ else
+ extra_arg_idx = 14;
+
+ if (repeat) {
+ /* We're on the first time through of one of the VX_FP_SMx
+ * test types, meaning we're testing a xs<ZZZ>adp case, thus
+ * we have to swap inputs as described above:
+ * src2 <= VSX[XT]
+ * src3 <= VSX[XB]
+ */
+ memcpy(vecOut_void_ptr, inB, 8); // src2
+ memcpy(vecB_void_ptr, &spec_fargs[extra_arg_idx], 8); //src3
+ frbp = (unsigned long long *)&spec_fargs[extra_arg_idx];
+ } else {
+ // Don't need to init src2, as it's done before the switch()
+ memcpy(vecOut_void_ptr, &spec_fargs[extra_arg_idx], 8); //src3
+ }
+ memcpy(&vsr_XT, vecOut_void_ptr, 8);
+ }
+
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ if (isLE)
+ dst++;
+
+ if (test_type == VX_FP_OTHER)
+ printf("#%d: %s %016llx %016llx = %016llx\n", i, test_name,
+ *frap, *frbp, *dst);
+ else
+ printf( "#%d: %s %016llx %016llx %016llx = %016llx\n", i,
+ test_name, vsr_XT, *frap, *frbp, *dst );
+
+ }
+ /*
+ {
+ // Debug code. Keep this block commented out except when debugging.
+ double result, expected;
+ memcpy(&result, dst, 8);
+ memcpy(&expected, &aTest.dp_bin_result, 8);
+ printf( "\tFRA + FRB: %e + %e: Expected = %e; Actual = %e\n",
+ spec_fargs[aTest.fra_idx], spec_fargs[aTest.frb_idx],
+ expected, result );
+ }
+ */
+ printf( "\n" );
+
+ if (repeat) {
+ repeat = 0;
+ strcat(test_name, "UNKNOWN");
+ switch (test_type) {
+ case VX_FP_SMAS:
+ case VX_FP_SMSS:
+ case VX_FP_SNMAS:
+ case VX_FP_SNMSS:
+ if (test_type == VX_FP_SMAS)
+ strcpy(test_name, "xsmadd");
+ else if (test_type == VX_FP_SMSS)
+ strcpy(test_name, "xsmsub");
+ else if (test_type == VX_FP_SNMAS)
+ strcpy(test_name, "xsnmadd");
+ else
+ strcpy(test_name, "xsnmsub");
+
+ do_asp = 0;
+ strcat(test_name, "msp");
+ break;
+ default:
+ break;
+ }
+ goto again;
+ }
+ k++;
+ }
+ printf( "\n" );
+ free(test_name);
+}
+
+
+static void test_vsx_one_fp_arg(void)
+{
+ test_func_t func;
+ int k;
+ void * vecB_void_ptr;
+
+ k = 0;
+ build_special_fargs_table();
+
+ while ((func = vsx_one_fp_arg_tests[k].test_func)) {
+ int idx, i;
+ unsigned long long *dst_dp;
+ unsigned int * dst_sp;
+ vx_fp_test2_t test_group = vsx_one_fp_arg_tests[k];
+ /* size of source operands */
+ Bool dp = ((test_group.precision == DOUBLE_TEST) ||
+ (test_group.precision == DOUBLE_TEST_SINGLE_RES)) ? True : False;
+ /* size of result */
+ Bool dp_res = IS_DP_RESULT(test_group.precision);
+ Bool is_sqrt = (strstr(test_group.name, "sqrt")) ? True : False;
+
+ vecB_void_ptr = (void *)&vec_inB;
+ if (isLE) {
+ vecB_void_ptr += dp? 8 : 12;
+ }
+
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int * pv;
+ void * inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (dp) {
+ int vec_out_idx;
+ unsigned long long * frB_dp;
+ if (isLE)
+ vec_out_idx = dp_res ? 1 : 3;
+ else
+ vec_out_idx = 0;
+
+ if (test_group.test_type == VX_SCALAR_SP_TO_VECTOR_SP) {
+ /* Take a single-precision value stored in double word element 0
+ * of src in double-precision format and convert to single-
+ * precision and store in word element 0 of dst.
+ */
+ double input = spec_sp_fargs[i];
+ memcpy(vecB_void_ptr, (void *)&input, 8);
+ } else {
+ inB = (void *)&spec_fargs[i];
+ // copy double precision FP into input vector element 0
+ memcpy(vecB_void_ptr, inB, 8);
+ }
+
+ // execute test insn
+ (*func)();
+ if (dp_res)
+ dst_dp = (unsigned long long *) &vec_out;
+ else
+ dst_sp = (unsigned int *) &vec_out;
+
+ printf("#%d: %s ", i, test_group.name);
+ frB_dp = (unsigned long long *)&spec_fargs[i];
+ printf("%s(%016llx)", test_group.op, *frB_dp);
+ if (test_group.test_type == VX_ESTIMATE)
+ {
+ Bool res;
+ res = check_reciprocal_estimate(is_sqrt, i, vec_out_idx);
+ printf(" ==> %s)", res ? "PASS" : "FAIL");
+ } else if (dp_res) {
+ printf(" = %016llx", dst_dp[vec_out_idx]);
+ } else {
+ printf(" = %08x", dst_sp[vec_out_idx]);
+ }
+
+ printf("\n");
+ } else { // single precision test type
+ int vec_out_idx;
+ if (isLE)
+ vec_out_idx = dp_res ? 1 : 3;
+ else
+ vec_out_idx = 0;
+ // Clear input vector
+ pv = (unsigned int *)&vec_inB;
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+ inB = (void *)&spec_sp_fargs[i];
+ // copy single precision FP into input vector element i
+ memcpy(vecB_void_ptr, inB, 4);
+ // execute test insn
+ (*func)();
+ if (dp_res)
+ dst_dp = (unsigned long long *) &vec_out;
+ else
+ dst_sp = (unsigned int *) &vec_out;
+ // print result
+ printf("#%d: %s ", i, test_group.name);
+ printf("%s(%08x)", test_group.op, *((unsigned int *)&spec_sp_fargs[i]));
+ if (dp_res)
+ printf(" = %016llx", dst_dp[vec_out_idx]);
+ else
+ printf(" = %08x", dst_sp[vec_out_idx]);
+
+ printf("\n");
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+/* This function currently only supports two double precision input arguments. */
+static void test_vsx_two_fp_arg(void)
+{
+ test_func_t func;
+ int k = 0;
+ void * vecA_void_ptr, * vecB_void_ptr;
+
+ if (isLE) {
+ vecA_void_ptr = (void *)&vec_inA + 8;
+ vecB_void_ptr = (void *)&vec_inB + 8;
+ } else {
+ vecA_void_ptr = (void *)&vec_inA;
+ vecB_void_ptr = (void *)&vec_inB;
+ }
+
+ build_special_fargs_table();
+ while ((func = vx_simple_scalar_fp_tests[k].test_func)) {
+ unsigned long long * frap, * frbp, * dst;
+ unsigned int * pv;
+ int idx;
+ vx_fp_test_basic_t test_group = vx_simple_scalar_fp_tests[k];
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ void * inA, * inB;
+ int i;
+ for (i = 0; i < test_group.num_tests; i++) {
+ fp_test_args_t aTest = test_group.targs[i];
+ inA = (void *)&spec_fargs[aTest.fra_idx];
+ inB = (void *)&spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ // Only need to copy one doubleword into each vector's element 0
+ memcpy(vecA_void_ptr, inA, 8);
+ memcpy(vecB_void_ptr, inB, 8);
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ if (isLE)
+ dst++;
+ printf("#%d: %s %016llx,%016llx => %016llx\n", i, test_group.name,
+ *frap, *frbp, *dst);
+ }
+ printf( "\n" );
+ k++;
+ }
+}
+
+/* This function handles the following cases:
+ * 1) Single precision value stored in double-precision
+ * floating-point format in doubleword element 0 of src VSX register
+ * 2) Integer word value stored in word element 1 of src VSX register
+ */
+static void _do_store_test (ldst_test_t storeTest)
+{
+ test_func_t func;
+ unsigned int *dst32;
+ unsigned int i, idx;
+ unsigned int * pv = (unsigned int *) storeTest.base_addr;
+ void * vecA_void_ptr;
+
+ if (isLE) {
+ if (storeTest.precision == SINGLE_TEST_SINGLE_RES)
+ vecA_void_ptr = (void *)&vec_inA + 8;
+ } else {
+ if (storeTest.precision == SINGLE_TEST_SINGLE_RES)
+ vecA_void_ptr = (void *)&vec_inA + 4;
+ else
+ vecA_void_ptr = (void *)&vec_inA;
+ }
+
+ func = storeTest.test_func;
+ r14 = (HWord_t) storeTest.base_addr;
+ r15 = (HWord_t) storeTest.offset;
+
+ /* test some of the pre-defined single precision values */
+ for (i = 0; i < nb_special_fargs; i+=3) {
+ // clear out storage destination
+ for (idx = 0; idx < 4; idx++)
+ *(pv + idx) = 0;
+
+ printf( "%s:", storeTest.name );
+ if (storeTest.precision == SINGLE_TEST_SINGLE_RES)
+ {
+ unsigned int * arg_ptr = (unsigned int *)&spec_sp_fargs[i];
+ memcpy(vecA_void_ptr, arg_ptr, sizeof(unsigned int));
+ printf(" %08x ==> ", *arg_ptr);
+ } else {
+ unsigned long long * dp;
+ double input = spec_sp_fargs[i];
+ dp = (unsigned long long *)&input;
+ memcpy(vecA_void_ptr, dp, sizeof(unsigned long long));
+ printf(" %016llx ==> ", *dp);
+ }
+
+ // execute test insn
+ (*func)();
+ dst32 = (unsigned int*)(storeTest.base_addr);
+ dst32 += (storeTest.offset/sizeof(int));
+ printf( "%08x\n", *dst32);
+ }
+
+ printf("\n");
+}
+
+static void _do_load_test(ldst_test_t loadTest)
+{
+ test_func_t func;
+ unsigned int i;
+ unsigned long long * dst_dp;
+
+ func = loadTest.test_func;
+ r15 = (HWord_t) loadTest.offset;
+
+ if (loadTest.base_addr == NULL) {
+ /* Test lxsspx: source is single precision value, so let's */
+ /* test some of the pre-defined single precision values. */
+ int num_loops = (loadTest.offset == 0) ? nb_special_fargs : (nb_special_fargs - (loadTest.offset/sizeof(int)));
+ for (i = 0; i < num_loops; i+=3) {
+ unsigned int * sp = (unsigned int *)&spec_sp_fargs[i + (loadTest.offset/sizeof(int))];
+ printf( "%s:", loadTest.name );
+ printf(" %08x ==> ", *sp);
+ r14 = (HWord_t)&spec_sp_fargs[i];
+
+ // execute test insn
+ (*func)();
+ dst_dp = (unsigned long long *) &vec_out;
+ if (isLE)
+ dst_dp++;
+ printf("%016llx\n", *dst_dp);
+ }
+ } else {
+ // source is an integer word
+ int num_loops = (loadTest.offset == 0) ? NUM_VIARGS_INTS : (NUM_VIARGS_INTS - (loadTest.offset/sizeof(int)));
+ for (i = 0; i < num_loops; i++) {
+ printf( "%s:", loadTest.name );
+ r14 = (HWord_t)&viargs[i];
+ printf(" %08x ==> ", viargs[i + (loadTest.offset/sizeof(int))]);
+
+ // execute test insn
+ (*func)();
+ dst_dp = (unsigned long long *) &vec_out;
+ if (isLE)
+ dst_dp++;
+ printf("%016llx\n", *dst_dp);
+ }
+ }
+ printf("\n");
+}
+
+static void test_ldst(void)
+{
+ int k = 0;
+
+ while (ldst_tests[k].test_func) {
+ if (ldst_tests[k].type == VSX_STORE)
+ _do_store_test(ldst_tests[k]);
+ else {
+ _do_load_test(ldst_tests[k]);
+ }
+ k++;
+ printf("\n");
+ }
+}
+
+static void test_xs_conv_ops(void)
+{
+
+ test_func_t func;
+ int k = 0;
+ void * vecB_void_ptr;
+
+ if (isLE)
+ vecB_void_ptr = (void *)&vec_inB + 8;
+ else
+ vecB_void_ptr = (void *)&vec_inB;
+
+ build_special_fargs_table();
+ while ((func = xs_conv_tests[k].test_func)) {
+ int i;
+ unsigned long long * dst;
+ xs_conv_test_t test_group = xs_conv_tests[k];
+ for (i = 0; i < NUM_VDARGS_INTS; i++) {
+ unsigned long long * inB, * pv;
+ int idx;
+ inB = (unsigned long long *)&vdargs[i];
+ memcpy(vecB_void_ptr, inB, 8);
+ pv = (unsigned long long *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 2; idx++, pv++)
+ *pv = 0ULL;
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ if (isLE)
+ dst++;
+ printf("#%d: %s %016llx => %016llx\n", i, test_group.name, vdargs[i], *dst);
+ }
+ k++;
+ printf("\n");
+ }
+ printf( "\n" );
+}
+
+
+static void test_vsx_logic(void)
+{
+ logic_test_t aTest;
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = logic_tests[k].test_func)) {
+
+ unsigned int * pv;
+ unsigned int * inA, * inB, * dst;
+ int idx, i;
+ aTest = logic_tests[k];
+ for (i = 0; i <= NUM_VIARGS_VECS; i+=4) {
+ pv = (unsigned int *)&vec_out;
+ inA = &viargs[i];
+ inB = &viargs[i];
+ memcpy(&vec_inA, inA, sizeof(vector unsigned int));
+ memcpy(&vec_inB, inB, sizeof(vector unsigned int));
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ // execute test insn
+ (*func)();
+ dst = (unsigned int*) &vec_out;
+
+ printf( "#%d: %10s ", k, aTest.name);
+ printf( " (%08x %08x %08x %08x, ", inA[0], inA[1], inA[2], inA[3]);
+ printf( " %08x %08x %08x %08x)", inB[0], inB[1], inB[2], inB[3]);
+ printf(" ==> %08x %08x %08x %08x\n", dst[0], dst[1], dst[2], dst[3]);
+ }
+ k++;
+ }
+ printf( "\n" );
+}
+
+
+//----------------------------------------------------------
+
+static test_table_t all_tests[] = {
+ { &test_vx_fp_ops,
+ "Test VSX floating point instructions"},
+ { &test_vsx_one_fp_arg,
+ "Test VSX vector and scalar single argument instructions"} ,
+ { &test_vsx_logic,
+ "Test VSX logic instructions" },
+ { &test_xs_conv_ops,
+ "Test VSX scalar integer conversion instructions" },
+ { &test_ldst,
+ "Test VSX load/store dp to sp instructions" },
+ { &test_vsx_two_fp_arg,
+ "Test VSX vector and scalar two argument instructions"} ,
+ { NULL, NULL }
+};
+
+#endif
+
+int main(int argc, char *argv[])
+{
+
+#ifdef HAS_ISA_2_07
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+#else
+ printf("NO ISA 2.07 SUPPORT\n");
+#endif
+ return 0;
+}
diff --git a/none/tests/ppc32/test_tm.c b/none/tests/ppc32/test_tm.c
deleted file mode 120000
index afe15af..0000000
--- a/none/tests/ppc32/test_tm.c
+++ /dev/null
@@ -1 +0,0 @@
-../ppc64/test_tm.c
\ No newline at end of file
diff --git a/none/tests/ppc32/test_tm.c b/none/tests/ppc32/test_tm.c
new file mode 100644
index 0000000..c829384
--- /dev/null
+++ b/none/tests/ppc32/test_tm.c
@@ -0,0 +1,25 @@
+#include <stdio.h>
+#ifdef SUPPORTS_HTM
+int __attribute__ ((noinline)) htm_begin (int r3, int r4)
+{
+ int ret;
+
+ if (__builtin_tbegin (0)) {
+ ret = r3;
+ __builtin_tend (0);
+ } else {
+ ret = r4;
+ } return ret;
+}
+#endif
+
+int main (void) {
+#ifdef SUPPORTS_HTM
+ int ret;
+ ret = htm_begin (10, 20);
+ printf ("ret = %d, expected = 10\n", ret);
+#else
+ printf ("No HTM support.");
+#endif
+ return 0;
+}
diff --git a/none/tests/ppc32/test_touch_tm.c b/none/tests/ppc32/test_touch_tm.c
deleted file mode 120000
index b2f43c0..0000000
--- a/none/tests/ppc32/test_touch_tm.c
+++ /dev/null
@@ -1 +0,0 @@
-../ppc64/test_touch_tm.c
\ No newline at end of file
diff --git a/none/tests/ppc32/test_touch_tm.c b/none/tests/ppc32/test_touch_tm.c
new file mode 100644
index 0000000..57f89bb
--- /dev/null
+++ b/none/tests/ppc32/test_touch_tm.c
@@ -0,0 +1,27 @@
+#include <stdio.h>
+
+int main (void) {
+#ifdef SUPPORTS_HTM
+ /* Just get the compiler to generate each of the TM instructions
+ * so we can verify that valgrind recognizes them.
+ * For now, only the tbegin instruction does anything in valgrind.
+ * The rest are just treated as NOPS.
+ */
+ __builtin_tabort (0);
+#ifdef __PPC64__
+ __builtin_tabortdc (0,0,0);
+ __builtin_tabortdci (0,0,0);
+#endif
+ __builtin_tabortwc (0,0,0);
+ __builtin_tabortwci (0,0,0);
+ __builtin_tbegin (0);
+ __builtin_tend (0);
+ // __builtin_tcheck (0); tcheck not recognized by compiler
+ __builtin_trechkpt (); // not recognized by early HW
+ __builtin_treclaim (0); // not recognized by early HW
+ __builtin_tsr (0);
+#else
+ printf ("No HTM support.");
+#endif
+ return 0;
+}
diff --git a/none/tests/ppc32/tw.c b/none/tests/ppc32/tw.c
deleted file mode 120000
index 3685442..0000000
--- a/none/tests/ppc32/tw.c
+++ /dev/null
@@ -1 +0,0 @@
-../ppc64/tw_td.c
\ No newline at end of file
diff --git a/none/tests/ppc32/tw.c b/none/tests/ppc32/tw.c
new file mode 100644
index 0000000..2365a4e
--- /dev/null
+++ b/none/tests/ppc32/tw.c
@@ -0,0 +1,375 @@
+
+#include <stdio.h>
+#include <signal.h>
+#include <setjmp.h>
+#include <string.h>
+#include <assert.h>
+
+static jmp_buf env_sigtrap;
+static void handler_sigtrap ( int x ) { longjmp(env_sigtrap,1); }
+
+void try ( char* who, void(*maybe_traps)(long,long), long arg1, long arg2 )
+{
+ struct sigaction tmp_act;
+ int r, trapped = 0;
+ memset(&tmp_act, 0, sizeof(tmp_act));
+ tmp_act.sa_handler = handler_sigtrap;
+ sigemptyset(&tmp_act.sa_mask);
+ tmp_act.sa_flags = SA_NODEFER;
+ r = sigaction(SIGTRAP, &tmp_act, NULL);
+ assert(r == 0);
+ if (setjmp(env_sigtrap)) {
+ trapped = 1;
+ } else {
+ maybe_traps(arg1, arg2);
+ }
+ signal(SIGTRAP, SIG_DFL);
+
+ printf("%s(%4lld,%4lld) -> %s\n", who, (long long int)arg1,
+ (long long int)arg2,
+ trapped ? "TRAP" : "no trap" );
+}
+
+static void tw_0 ( long n, long m ) {
+ __asm__ __volatile__("tw 0, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_1 ( long n, long m ) {
+ __asm__ __volatile__("tw 1, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_2 ( long n, long m ) {
+ __asm__ __volatile__("tw 2, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_3 ( long n, long m ) {
+ __asm__ __volatile__("tw 3, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_4 ( long n, long m ) {
+ __asm__ __volatile__("tw 4, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_5 ( long n, long m ) {
+ __asm__ __volatile__("tw 5, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_6 ( long n, long m ) {
+ __asm__ __volatile__("tw 6, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_7 ( long n, long m ) {
+ __asm__ __volatile__("tw 7, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_8 ( long n, long m ) {
+ __asm__ __volatile__("tw 8, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_9 ( long n, long m ) {
+ __asm__ __volatile__("tw 9, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_10 ( long n, long m ) {
+ __asm__ __volatile__("tw 10, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_11 ( long n, long m ) {
+ __asm__ __volatile__("tw 11, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_12 ( long n, long m ) {
+ __asm__ __volatile__("tw 12, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_13 ( long n, long m ) {
+ __asm__ __volatile__("tw 13, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_14 ( long n, long m ) {
+ __asm__ __volatile__("tw 14, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_15 ( long n, long m ) {
+ __asm__ __volatile__("tw 15, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_16 ( long n, long m ) {
+ __asm__ __volatile__("tw 16, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_17 ( long n, long m ) {
+ __asm__ __volatile__("tw 17, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_18 ( long n, long m ) {
+ __asm__ __volatile__("tw 18, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_19 ( long n, long m ) {
+ __asm__ __volatile__("tw 19, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_20 ( long n, long m ) {
+ __asm__ __volatile__("tw 20, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_21 ( long n, long m ) {
+ __asm__ __volatile__("tw 21, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_22 ( long n, long m ) {
+ __asm__ __volatile__("tw 22, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_23 ( long n, long m ) {
+ __asm__ __volatile__("tw 23, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_24 ( long n, long m ) {
+ __asm__ __volatile__("tw 24, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_25 ( long n, long m ) {
+ __asm__ __volatile__("tw 25, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_26 ( long n, long m ) {
+ __asm__ __volatile__("tw 26, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_27 ( long n, long m ) {
+ __asm__ __volatile__("tw 27, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_28 ( long n, long m ) {
+ __asm__ __volatile__("tw 28, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_29 ( long n, long m ) {
+ __asm__ __volatile__("tw 29, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_30 ( long n, long m ) {
+ __asm__ __volatile__("tw 30, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void tw_31 ( long n, long m ) {
+ __asm__ __volatile__("tw 31, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+
+#if defined(__powerpc64__)
+
+static void td_0 ( long n, long m ) {
+ __asm__ __volatile__("td 0, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_1 ( long n, long m ) {
+ __asm__ __volatile__("td 1, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_2 ( long n, long m ) {
+ __asm__ __volatile__("td 2, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_3 ( long n, long m ) {
+ __asm__ __volatile__("td 3, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_4 ( long n, long m ) {
+ __asm__ __volatile__("td 4, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_5 ( long n, long m ) {
+ __asm__ __volatile__("td 5, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_6 ( long n, long m ) {
+ __asm__ __volatile__("td 6, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_7 ( long n, long m ) {
+ __asm__ __volatile__("td 7, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_8 ( long n, long m ) {
+ __asm__ __volatile__("td 8, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_9 ( long n, long m ) {
+ __asm__ __volatile__("td 9, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_10 ( long n, long m ) {
+ __asm__ __volatile__("td 10, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_11 ( long n, long m ) {
+ __asm__ __volatile__("td 11, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_12 ( long n, long m ) {
+ __asm__ __volatile__("td 12, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_13 ( long n, long m ) {
+ __asm__ __volatile__("td 13, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_14 ( long n, long m ) {
+ __asm__ __volatile__("td 14, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_15 ( long n, long m ) {
+ __asm__ __volatile__("td 15, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_16 ( long n, long m ) {
+ __asm__ __volatile__("td 16, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_17 ( long n, long m ) {
+ __asm__ __volatile__("td 17, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_18 ( long n, long m ) {
+ __asm__ __volatile__("td 18, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_19 ( long n, long m ) {
+ __asm__ __volatile__("td 19, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_20 ( long n, long m ) {
+ __asm__ __volatile__("td 20, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_21 ( long n, long m ) {
+ __asm__ __volatile__("td 21, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_22 ( long n, long m ) {
+ __asm__ __volatile__("td 22, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_23 ( long n, long m ) {
+ __asm__ __volatile__("td 23, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_24 ( long n, long m ) {
+ __asm__ __volatile__("td 24, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_25 ( long n, long m ) {
+ __asm__ __volatile__("td 25, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_26 ( long n, long m ) {
+ __asm__ __volatile__("td 26, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_27 ( long n, long m ) {
+ __asm__ __volatile__("td 27, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_28 ( long n, long m ) {
+ __asm__ __volatile__("td 28, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_29 ( long n, long m ) {
+ __asm__ __volatile__("td 29, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_30 ( long n, long m ) {
+ __asm__ __volatile__("td 30, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+static void td_31 ( long n, long m ) {
+ __asm__ __volatile__("td 31, %0,%1"
+ : /*out*/ : /*in*/ "r" (n), "r" (m) );
+}
+
+#endif
+
+
+int main ( void )
+{
+#define TW_GROUP(cmp) \
+ try("tw_" #cmp "", tw_##cmp, -150, -100); \
+ try("tw_" #cmp "", tw_##cmp, -100, -100); \
+ try("tw_" #cmp "", tw_##cmp, -50, -100);
+
+ TW_GROUP(0);
+ TW_GROUP(1);
+ TW_GROUP(2);
+ TW_GROUP(3);
+ TW_GROUP(4);
+ TW_GROUP(5);
+ TW_GROUP(6);
+ TW_GROUP(7);
+ TW_GROUP(8);
+ TW_GROUP(9);
+ TW_GROUP(10);
+ TW_GROUP(11);
+ TW_GROUP(12);
+ TW_GROUP(13);
+ TW_GROUP(14);
+ TW_GROUP(15);
+ TW_GROUP(16);
+ TW_GROUP(17);
+ TW_GROUP(18);
+ TW_GROUP(19);
+ TW_GROUP(20);
+ TW_GROUP(21);
+ TW_GROUP(22);
+ TW_GROUP(23);
+ TW_GROUP(24);
+ TW_GROUP(25);
+ TW_GROUP(26);
+ TW_GROUP(27);
+ TW_GROUP(28);
+ TW_GROUP(29);
+ TW_GROUP(30);
+ TW_GROUP(31);
+#if defined(__powerpc64__)
+#define TD_GROUP(cmp) \
+ try("td_" #cmp "", td_##cmp, -150, -100); \
+ try("td_" #cmp "", td_##cmp, -100, -100); \
+ try("td_" #cmp "", td_##cmp, -50, -100);
+
+ TD_GROUP(0);
+ TD_GROUP(1);
+ TD_GROUP(2);
+ TD_GROUP(3);
+ TD_GROUP(4);
+ TD_GROUP(5);
+ TD_GROUP(6);
+ TD_GROUP(7);
+ TD_GROUP(8);
+ TD_GROUP(9);
+ TD_GROUP(10);
+ TD_GROUP(11);
+ TD_GROUP(12);
+ TD_GROUP(13);
+ TD_GROUP(14);
+ TD_GROUP(15);
+ TD_GROUP(16);
+ TD_GROUP(17);
+ TD_GROUP(18);
+ TD_GROUP(19);
+ TD_GROUP(20);
+ TD_GROUP(21);
+ TD_GROUP(22);
+ TD_GROUP(23);
+ TD_GROUP(24);
+ TD_GROUP(25);
+ TD_GROUP(26);
+ TD_GROUP(27);
+ TD_GROUP(28);
+ TD_GROUP(29);
+ TD_GROUP(30);
+ TD_GROUP(31);
+#endif
+ return 0;
+}
diff --git a/none/tests/ppc32/twi.c b/none/tests/ppc32/twi.c
deleted file mode 120000
index e753fa9..0000000
--- a/none/tests/ppc32/twi.c
+++ /dev/null
@@ -1 +0,0 @@
-../ppc64/twi_tdi.c
\ No newline at end of file
diff --git a/none/tests/ppc32/twi.c b/none/tests/ppc32/twi.c
new file mode 100644
index 0000000..fb42870
--- /dev/null
+++ b/none/tests/ppc32/twi.c
@@ -0,0 +1,374 @@
+
+#include <stdio.h>
+#include <signal.h>
+#include <setjmp.h>
+#include <string.h>
+#include <assert.h>
+
+static jmp_buf env_sigtrap;
+static void handler_sigtrap ( int x ) { longjmp(env_sigtrap,1); }
+
+void try ( char* who, void(*maybe_traps)(long), long arg )
+{
+ struct sigaction tmp_act;
+ int r, trapped = 0;
+ memset(&tmp_act, 0, sizeof(tmp_act));
+ tmp_act.sa_handler = handler_sigtrap;
+ sigemptyset(&tmp_act.sa_mask);
+ tmp_act.sa_flags = SA_NODEFER;
+ r = sigaction(SIGTRAP, &tmp_act, NULL);
+ assert(r == 0);
+ if (setjmp(env_sigtrap)) {
+ trapped = 1;
+ } else {
+ maybe_traps(arg);
+ }
+ signal(SIGTRAP, SIG_DFL);
+
+ printf("%s(%4lld) -> %s\n", who, (long long int)arg,
+ trapped ? "TRAP" : "no trap" );
+}
+
+static void twi_0_neg100 ( long n ) {
+ __asm__ __volatile__("twi 0, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_1_neg100 ( long n ) {
+ __asm__ __volatile__("twi 1, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_2_neg100 ( long n ) {
+ __asm__ __volatile__("twi 2, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_3_neg100 ( long n ) {
+ __asm__ __volatile__("twi 3, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_4_neg100 ( long n ) {
+ __asm__ __volatile__("twi 4, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_5_neg100 ( long n ) {
+ __asm__ __volatile__("twi 5, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_6_neg100 ( long n ) {
+ __asm__ __volatile__("twi 6, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_7_neg100 ( long n ) {
+ __asm__ __volatile__("twi 7, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_8_neg100 ( long n ) {
+ __asm__ __volatile__("twi 8, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_9_neg100 ( long n ) {
+ __asm__ __volatile__("twi 9, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_10_neg100 ( long n ) {
+ __asm__ __volatile__("twi 10, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_11_neg100 ( long n ) {
+ __asm__ __volatile__("twi 11, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_12_neg100 ( long n ) {
+ __asm__ __volatile__("twi 12, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_13_neg100 ( long n ) {
+ __asm__ __volatile__("twi 13, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_14_neg100 ( long n ) {
+ __asm__ __volatile__("twi 14, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_15_neg100 ( long n ) {
+ __asm__ __volatile__("twi 15, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_16_neg100 ( long n ) {
+ __asm__ __volatile__("twi 16, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_17_neg100 ( long n ) {
+ __asm__ __volatile__("twi 17, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_18_neg100 ( long n ) {
+ __asm__ __volatile__("twi 18, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_19_neg100 ( long n ) {
+ __asm__ __volatile__("twi 19, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_20_neg100 ( long n ) {
+ __asm__ __volatile__("twi 20, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_21_neg100 ( long n ) {
+ __asm__ __volatile__("twi 21, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_22_neg100 ( long n ) {
+ __asm__ __volatile__("twi 22, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_23_neg100 ( long n ) {
+ __asm__ __volatile__("twi 23, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_24_neg100 ( long n ) {
+ __asm__ __volatile__("twi 24, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_25_neg100 ( long n ) {
+ __asm__ __volatile__("twi 25, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_26_neg100 ( long n ) {
+ __asm__ __volatile__("twi 26, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_27_neg100 ( long n ) {
+ __asm__ __volatile__("twi 27, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_28_neg100 ( long n ) {
+ __asm__ __volatile__("twi 28, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_29_neg100 ( long n ) {
+ __asm__ __volatile__("twi 29, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_30_neg100 ( long n ) {
+ __asm__ __volatile__("twi 30, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void twi_31_neg100 ( long n ) {
+ __asm__ __volatile__("twi 31, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+
+#if defined(__powerpc64__)
+
+static void tdi_0_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 0, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_1_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 1, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_2_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 2, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_3_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 3, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_4_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 4, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_5_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 5, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_6_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 6, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_7_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 7, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_8_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 8, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_9_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 9, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_10_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 10, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_11_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 11, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_12_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 12, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_13_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 13, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_14_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 14, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_15_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 15, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_16_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 16, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_17_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 17, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_18_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 18, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_19_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 19, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_20_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 20, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_21_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 21, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_22_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 22, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_23_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 23, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_24_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 24, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_25_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 25, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_26_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 26, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_27_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 27, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_28_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 28, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_29_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 29, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_30_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 30, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+static void tdi_31_neg100 ( long n ) {
+ __asm__ __volatile__("tdi 31, %0,-100"
+ : /*out*/ : /*in*/ "r" (n) );
+}
+
+#endif
+
+
+int main ( void )
+{
+#define TWI_GROUP(cmp) \
+ try("twi_" #cmp "_neg100", twi_##cmp##_neg100, -150); \
+ try("twi_" #cmp "_neg100", twi_##cmp##_neg100, -100); \
+ try("twi_" #cmp "_neg100", twi_##cmp##_neg100, -50);
+
+ TWI_GROUP(0);
+ TWI_GROUP(1);
+ TWI_GROUP(2);
+ TWI_GROUP(3);
+ TWI_GROUP(4);
+ TWI_GROUP(5);
+ TWI_GROUP(6);
+ TWI_GROUP(7);
+ TWI_GROUP(8);
+ TWI_GROUP(9);
+ TWI_GROUP(10);
+ TWI_GROUP(11);
+ TWI_GROUP(12);
+ TWI_GROUP(13);
+ TWI_GROUP(14);
+ TWI_GROUP(15);
+ TWI_GROUP(16);
+ TWI_GROUP(17);
+ TWI_GROUP(18);
+ TWI_GROUP(19);
+ TWI_GROUP(20);
+ TWI_GROUP(21);
+ TWI_GROUP(22);
+ TWI_GROUP(23);
+ TWI_GROUP(24);
+ TWI_GROUP(25);
+ TWI_GROUP(26);
+ TWI_GROUP(27);
+ TWI_GROUP(28);
+ TWI_GROUP(29);
+ TWI_GROUP(30);
+ TWI_GROUP(31);
+#if defined(__powerpc64__)
+#define TDI_GROUP(cmp) \
+ try("tdi_" #cmp "_neg100", tdi_##cmp##_neg100, -150); \
+ try("tdi_" #cmp "_neg100", tdi_##cmp##_neg100, -100); \
+ try("tdi_" #cmp "_neg100", tdi_##cmp##_neg100, -50);
+
+ TDI_GROUP(0);
+ TDI_GROUP(1);
+ TDI_GROUP(2);
+ TDI_GROUP(3);
+ TDI_GROUP(4);
+ TDI_GROUP(5);
+ TDI_GROUP(6);
+ TDI_GROUP(7);
+ TDI_GROUP(8);
+ TDI_GROUP(9);
+ TDI_GROUP(10);
+ TDI_GROUP(11);
+ TDI_GROUP(12);
+ TDI_GROUP(13);
+ TDI_GROUP(14);
+ TDI_GROUP(15);
+ TDI_GROUP(16);
+ TDI_GROUP(17);
+ TDI_GROUP(18);
+ TDI_GROUP(19);
+ TDI_GROUP(20);
+ TDI_GROUP(21);
+ TDI_GROUP(22);
+ TDI_GROUP(23);
+ TDI_GROUP(24);
+ TDI_GROUP(25);
+ TDI_GROUP(26);
+ TDI_GROUP(27);
+ TDI_GROUP(28);
+ TDI_GROUP(29);
+ TDI_GROUP(30);
+ TDI_GROUP(31);
+#endif
+ return 0;
+}
diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am
index a4f71e2..a79d35a 100644
--- a/none/tests/ppc64/Makefile.am
+++ b/none/tests/ppc64/Makefile.am
@@ -3,6 +3,8 @@
dist_noinst_SCRIPTS = filter_stderr
+noinst_HEADERS = ppc64_helpers.h
+
EXTRA_DIST = \
jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest jm-int.stdout.exp-LE \
jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-LE jm-fp.stdout.exp-LE2 jm-fp.stdout.exp-BE2 \
@@ -35,7 +37,11 @@
test_tm.stderr.exp test_tm.stdout.exp test_tm.vgtest \
test_touch_tm.stderr.exp test_touch_tm.stdout.exp test_touch_tm.vgtest \
ldst_multiple.stderr.exp ldst_multiple.stdout.exp ldst_multiple.vgtest \
- data-cache-instructions.stderr.exp data-cache-instructions.stdout.exp data-cache-instructions.vgtest
+ data-cache-instructions.stderr.exp data-cache-instructions.stdout.exp data-cache-instructions.vgtest \
+ test_isa_3_0_altivec.stderr.exp test_isa_3_0_altivec.stdout.exp \
+ test_isa_3_0_altivec.stdout.exp-LE test_isa_3_0_altivec.vgtest \
+ test_isa_3_0_other.stderr.exp test_isa_3_0_other.stdout.exp \
+ test_isa_3_0_other.stdout.exp-LE test_isa_3_0_other.vgtest
check_PROGRAMS = \
allexec \
@@ -43,6 +49,7 @@
test_isa_2_06_part1 test_isa_2_06_part2 test_isa_2_06_part3 \
test_dfp1 test_dfp2 test_dfp3 test_dfp4 test_dfp5 \
test_isa_2_07_part1 test_isa_2_07_part2 \
+ test_isa_3_0 \
test_tm test_touch_tm ldst_multiple data-cache-instructions \
power6_mf_gpr std_reg_imm \
twi_tdi tw_td power6_bcmp
@@ -88,11 +95,21 @@
if SUPPORTS_HTM
HTM_FLAG = -mhtm -DSUPPORTS_HTM
+else
+HTM_FLAG =
endif
-jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames \
+jm_insns_CFLAGS = $(AM_CFLAGS) -Wl,-z,norelro -Winline -Wall -O -g -mregnames \
@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_ALTIVEC)
+if HAS_ISA_3_00
+BUILD_FLAGS_ISA_3_00 = -mcpu=power8
+ISA_3_00_FLAG = -DHAS_ISA_3_00
+else
+BUILD_FLAGS_ISA_3_00 =
+ISA_3_00_FLAG =
+endif
+
test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
@@ -123,6 +140,9 @@
test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_2_07_FLAG) \
@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
+test_isa_3_0_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_00_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_ISA_3_00)
+
test_isa_2_06_part3_LDADD = -lm
test_dfp1_LDADD = -lm
test_dfp2_LDADD = -lm
@@ -133,4 +153,5 @@
test_isa_2_07_part2_LDADD = -lm
test_tm_LDADD = -lm
test_touch_tm_LDADD = -lm
+test_isa_3_0_LDADD = -lm
diff --git a/none/tests/ppc64/Makefile.in b/none/tests/ppc64/Makefile.in
new file mode 100644
index 0000000..0794d4f
--- /dev/null
+++ b/none/tests/ppc64/Makefile.in
@@ -0,0 +1,1490 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+VPATH = @srcdir@
+am__is_gnu_make = { \
+ if test -z '$(MAKELEVEL)'; then \
+ false; \
+ elif test -n '$(MAKE_HOST)'; then \
+ true; \
+ elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
+ true; \
+ else \
+ false; \
+ fi; \
+}
+am__make_running_with_option = \
+ case $${target_option-} in \
+ ?) ;; \
+ *) echo "am__make_running_with_option: internal error: invalid" \
+ "target option '$${target_option-}' specified" >&2; \
+ exit 1;; \
+ esac; \
+ has_opt=no; \
+ sane_makeflags=$$MAKEFLAGS; \
+ if $(am__is_gnu_make); then \
+ sane_makeflags=$$MFLAGS; \
+ else \
+ case $$MAKEFLAGS in \
+ *\\[\ \ ]*) \
+ bs=\\; \
+ sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
+ | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \
+ esac; \
+ fi; \
+ skip_next=no; \
+ strip_trailopt () \
+ { \
+ flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
+ }; \
+ for flg in $$sane_makeflags; do \
+ test $$skip_next = yes && { skip_next=no; continue; }; \
+ case $$flg in \
+ *=*|--*) continue;; \
+ -*I) strip_trailopt 'I'; skip_next=yes;; \
+ -*I?*) strip_trailopt 'I';; \
+ -*O) strip_trailopt 'O'; skip_next=yes;; \
+ -*O?*) strip_trailopt 'O';; \
+ -*l) strip_trailopt 'l'; skip_next=yes;; \
+ -*l?*) strip_trailopt 'l';; \
+ -[dEDm]) skip_next=yes;; \
+ -[JT]) skip_next=yes;; \
+ esac; \
+ case $$flg in \
+ *$$target_option*) has_opt=yes; break;; \
+ esac; \
+ done; \
+ test $$has_opt = yes
+am__make_dryrun = (target_option=n; $(am__make_running_with_option))
+am__make_keepgoing = (target_option=k; $(am__make_running_with_option))
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+@COMPILER_IS_CLANG_TRUE@am__append_1 = -Wno-cast-align -Wno-self-assign \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-compare
+
+@SOLARIS_XPG_SYMBOLS_PRESENT_TRUE@am__append_2 = -Wl,-M,$(top_srcdir)/solaris/vgpreload-solaris.mapfile
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_3 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+
+# Make sure that all test programs have threaded errno.
+# Disable largefile support as there are test cases explictly enabling it.
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
+@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
+@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-constant-out-of-range-compare \
+@COMPILER_IS_CLANG_TRUE@ -Wno-self-assign -Wno-string-plus-int \
+@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
+@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
+@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
+check_PROGRAMS = allexec$(EXEEXT) lsw$(EXEEXT) jm-insns$(EXEEXT) \
+ round$(EXEEXT) test_isa_2_06_part1$(EXEEXT) \
+ test_isa_2_06_part2$(EXEEXT) test_isa_2_06_part3$(EXEEXT) \
+ test_dfp1$(EXEEXT) test_dfp2$(EXEEXT) test_dfp3$(EXEEXT) \
+ test_dfp4$(EXEEXT) test_dfp5$(EXEEXT) \
+ test_isa_2_07_part1$(EXEEXT) test_isa_2_07_part2$(EXEEXT) \
+ test_isa_3_0$(EXEEXT) test_tm$(EXEEXT) test_touch_tm$(EXEEXT) \
+ ldst_multiple$(EXEEXT) data-cache-instructions$(EXEEXT) \
+ power6_mf_gpr$(EXEEXT) std_reg_imm$(EXEEXT) twi_tdi$(EXEEXT) \
+ tw_td$(EXEEXT) power6_bcmp$(EXEEXT)
+subdir = none/tests/ppc64
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.ac
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+DIST_COMMON = $(srcdir)/Makefile.am $(dist_noinst_SCRIPTS) \
+ $(noinst_HEADERS) $(am__DIST_COMMON)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+allexec_SOURCES = allexec.c
+allexec_OBJECTS = allexec-allexec.$(OBJEXT)
+allexec_LDADD = $(LDADD)
+allexec_LINK = $(CCLD) $(allexec_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+data_cache_instructions_SOURCES = data-cache-instructions.c
+data_cache_instructions_OBJECTS = data-cache-instructions.$(OBJEXT)
+data_cache_instructions_LDADD = $(LDADD)
+jm_insns_SOURCES = jm-insns.c
+jm_insns_OBJECTS = jm_insns-jm-insns.$(OBJEXT)
+jm_insns_LDADD = $(LDADD)
+jm_insns_LINK = $(CCLD) $(jm_insns_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+ldst_multiple_SOURCES = ldst_multiple.c
+ldst_multiple_OBJECTS = ldst_multiple.$(OBJEXT)
+ldst_multiple_LDADD = $(LDADD)
+lsw_SOURCES = lsw.c
+lsw_OBJECTS = lsw.$(OBJEXT)
+lsw_LDADD = $(LDADD)
+power6_bcmp_SOURCES = power6_bcmp.c
+power6_bcmp_OBJECTS = power6_bcmp.$(OBJEXT)
+power6_bcmp_LDADD = $(LDADD)
+power6_mf_gpr_SOURCES = power6_mf_gpr.c
+power6_mf_gpr_OBJECTS = power6_mf_gpr.$(OBJEXT)
+power6_mf_gpr_LDADD = $(LDADD)
+round_SOURCES = round.c
+round_OBJECTS = round.$(OBJEXT)
+round_LDADD = $(LDADD)
+std_reg_imm_SOURCES = std_reg_imm.c
+std_reg_imm_OBJECTS = std_reg_imm.$(OBJEXT)
+std_reg_imm_LDADD = $(LDADD)
+test_dfp1_SOURCES = test_dfp1.c
+test_dfp1_OBJECTS = test_dfp1-test_dfp1.$(OBJEXT)
+test_dfp1_DEPENDENCIES =
+test_dfp1_LINK = $(CCLD) $(test_dfp1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp2_SOURCES = test_dfp2.c
+test_dfp2_OBJECTS = test_dfp2-test_dfp2.$(OBJEXT)
+test_dfp2_DEPENDENCIES =
+test_dfp2_LINK = $(CCLD) $(test_dfp2_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp3_SOURCES = test_dfp3.c
+test_dfp3_OBJECTS = test_dfp3-test_dfp3.$(OBJEXT)
+test_dfp3_DEPENDENCIES =
+test_dfp3_LINK = $(CCLD) $(test_dfp3_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp4_SOURCES = test_dfp4.c
+test_dfp4_OBJECTS = test_dfp4-test_dfp4.$(OBJEXT)
+test_dfp4_DEPENDENCIES =
+test_dfp4_LINK = $(CCLD) $(test_dfp4_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_dfp5_SOURCES = test_dfp5.c
+test_dfp5_OBJECTS = test_dfp5-test_dfp5.$(OBJEXT)
+test_dfp5_DEPENDENCIES =
+test_dfp5_LINK = $(CCLD) $(test_dfp5_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_isa_2_06_part1_SOURCES = test_isa_2_06_part1.c
+test_isa_2_06_part1_OBJECTS = \
+ test_isa_2_06_part1-test_isa_2_06_part1.$(OBJEXT)
+test_isa_2_06_part1_LDADD = $(LDADD)
+test_isa_2_06_part1_LINK = $(CCLD) $(test_isa_2_06_part1_CFLAGS) \
+ $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+test_isa_2_06_part2_SOURCES = test_isa_2_06_part2.c
+test_isa_2_06_part2_OBJECTS = \
+ test_isa_2_06_part2-test_isa_2_06_part2.$(OBJEXT)
+test_isa_2_06_part2_LDADD = $(LDADD)
+test_isa_2_06_part2_LINK = $(CCLD) $(test_isa_2_06_part2_CFLAGS) \
+ $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+test_isa_2_06_part3_SOURCES = test_isa_2_06_part3.c
+test_isa_2_06_part3_OBJECTS = \
+ test_isa_2_06_part3-test_isa_2_06_part3.$(OBJEXT)
+test_isa_2_06_part3_DEPENDENCIES =
+test_isa_2_06_part3_LINK = $(CCLD) $(test_isa_2_06_part3_CFLAGS) \
+ $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+test_isa_2_07_part1_SOURCES = test_isa_2_07_part1.c
+test_isa_2_07_part1_OBJECTS = \
+ test_isa_2_07_part1-test_isa_2_07_part1.$(OBJEXT)
+test_isa_2_07_part1_DEPENDENCIES =
+test_isa_2_07_part1_LINK = $(CCLD) $(test_isa_2_07_part1_CFLAGS) \
+ $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+test_isa_2_07_part2_SOURCES = test_isa_2_07_part2.c
+test_isa_2_07_part2_OBJECTS = \
+ test_isa_2_07_part2-test_isa_2_07_part2.$(OBJEXT)
+test_isa_2_07_part2_DEPENDENCIES =
+test_isa_2_07_part2_LINK = $(CCLD) $(test_isa_2_07_part2_CFLAGS) \
+ $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+test_isa_3_0_SOURCES = test_isa_3_0.c
+test_isa_3_0_OBJECTS = test_isa_3_0-test_isa_3_0.$(OBJEXT)
+test_isa_3_0_DEPENDENCIES =
+test_isa_3_0_LINK = $(CCLD) $(test_isa_3_0_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+test_tm_SOURCES = test_tm.c
+test_tm_OBJECTS = test_tm-test_tm.$(OBJEXT)
+test_tm_DEPENDENCIES =
+test_tm_LINK = $(CCLD) $(test_tm_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+test_touch_tm_SOURCES = test_touch_tm.c
+test_touch_tm_OBJECTS = test_touch_tm-test_touch_tm.$(OBJEXT)
+test_touch_tm_DEPENDENCIES =
+test_touch_tm_LINK = $(CCLD) $(test_touch_tm_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+tw_td_SOURCES = tw_td.c
+tw_td_OBJECTS = tw_td.$(OBJEXT)
+tw_td_LDADD = $(LDADD)
+twi_tdi_SOURCES = twi_tdi.c
+twi_tdi_OBJECTS = twi_tdi.$(OBJEXT)
+twi_tdi_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+AM_V_P = $(am__v_P_@AM_V@)
+am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
+am__v_P_0 = false
+am__v_P_1 = :
+AM_V_GEN = $(am__v_GEN_@AM_V@)
+am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@)
+am__v_GEN_0 = @echo " GEN " $@;
+am__v_GEN_1 =
+AM_V_at = $(am__v_at_@AM_V@)
+am__v_at_ = $(am__v_at_@AM_DEFAULT_V@)
+am__v_at_0 = @
+am__v_at_1 =
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+AM_V_lt = $(am__v_lt_@AM_V@)
+am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)
+am__v_lt_0 = --silent
+am__v_lt_1 =
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+AM_V_CC = $(am__v_CC_@AM_V@)
+am__v_CC_ = $(am__v_CC_@AM_DEFAULT_V@)
+am__v_CC_0 = @echo " CC " $@;
+am__v_CC_1 =
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+AM_V_CCLD = $(am__v_CCLD_@AM_V@)
+am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
+am__v_CCLD_0 = @echo " CCLD " $@;
+am__v_CCLD_1 =
+SOURCES = allexec.c data-cache-instructions.c jm-insns.c \
+ ldst_multiple.c lsw.c power6_bcmp.c power6_mf_gpr.c round.c \
+ std_reg_imm.c test_dfp1.c test_dfp2.c test_dfp3.c test_dfp4.c \
+ test_dfp5.c test_isa_2_06_part1.c test_isa_2_06_part2.c \
+ test_isa_2_06_part3.c test_isa_2_07_part1.c \
+ test_isa_2_07_part2.c test_isa_3_0.c test_tm.c test_touch_tm.c \
+ tw_td.c twi_tdi.c
+DIST_SOURCES = allexec.c data-cache-instructions.c jm-insns.c \
+ ldst_multiple.c lsw.c power6_bcmp.c power6_mf_gpr.c round.c \
+ std_reg_imm.c test_dfp1.c test_dfp2.c test_dfp3.c test_dfp4.c \
+ test_dfp5.c test_isa_2_06_part1.c test_isa_2_06_part2.c \
+ test_isa_2_06_part3.c test_isa_2_07_part1.c \
+ test_isa_2_07_part2.c test_isa_3_0.c test_tm.c test_touch_tm.c \
+ tw_td.c twi_tdi.c
+am__can_run_installinfo = \
+ case $$AM_UPDATE_INFO_DIR in \
+ n|no|NO) false;; \
+ *) (install-info --version) >/dev/null 2>&1;; \
+ esac
+HEADERS = $(noinst_HEADERS)
+am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) $(LISP)
+# Read a list of newline-separated strings from the standard input,
+# and print each of them once, without duplicates. Input order is
+# *not* preserved.
+am__uniquify_input = $(AWK) '\
+ BEGIN { nonempty = 0; } \
+ { items[$$0] = 1; nonempty = 1; } \
+ END { if (nonempty) { for (i in items) print i; }; } \
+'
+# Make sure the list of sources is unique. This is necessary because,
+# e.g., the same source file might be shared among _SOURCES variables
+# for different programs/libraries.
+am__define_uniq_tagged_files = \
+ list='$(am__tagged_files)'; \
+ unique=`for i in $$list; do \
+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+ done | $(am__uniquify_input)`
+ETAGS = etags
+CTAGS = ctags
+am__DIST_COMMON = $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/depcomp
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AM_DEFAULT_VERBOSITY = @AM_DEFAULT_VERBOSITY@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+DIS_PATH = @DIS_PATH@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_IPA_ICF = @FLAG_FNO_IPA_ICF@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_FSANITIZE = @FLAG_FSANITIZE@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MIPS32 = @FLAG_MIPS32@
+FLAG_MIPS64 = @FLAG_MIPS64@
+FLAG_MLONG_DOUBLE_128 = @FLAG_MLONG_DOUBLE_128@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_OCTEON = @FLAG_OCTEON@
+FLAG_OCTEON2 = @FLAG_OCTEON2@
+FLAG_T_TEXT = @FLAG_T_TEXT@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_CAST_ALIGN = @FLAG_W_CAST_ALIGN@
+FLAG_W_CAST_QUAL = @FLAG_W_CAST_QUAL@
+FLAG_W_EMPTY_BODY = @FLAG_W_EMPTY_BODY@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_FORMAT = @FLAG_W_FORMAT@
+FLAG_W_FORMAT_SECURITY = @FLAG_W_FORMAT_SECURITY@
+FLAG_W_FORMAT_SIGNEDNESS = @FLAG_W_FORMAT_SIGNEDNESS@
+FLAG_W_IGNORED_QUALIFIERS = @FLAG_W_IGNORED_QUALIFIERS@
+FLAG_W_MISSING_PARAMETER_TYPE = @FLAG_W_MISSING_PARAMETER_TYPE@
+FLAG_W_NO_INFINITE_RECURSION = @FLAG_W_NO_INFINITE_RECURSION@
+FLAG_W_NO_MEMSET_TRANSPOSED_ARGS = @FLAG_W_NO_MEMSET_TRANSPOSED_ARGS@
+FLAG_W_NO_MISMATCHED_NEW_DELETE = @FLAG_W_NO_MISMATCHED_NEW_DELETE@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_POINTER_SIGN = @FLAG_W_NO_POINTER_SIGN@
+FLAG_W_NO_STATIC_LOCAL_IN_INLINE = @FLAG_W_NO_STATIC_LOCAL_IN_INLINE@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+FLAG_W_NO_UNUSED_FUNCTION = @FLAG_W_NO_UNUSED_FUNCTION@
+FLAG_W_OLD_STYLE_DECLARATION = @FLAG_W_OLD_STYLE_DECLARATION@
+FLAG_W_WRITE_STRINGS = @FLAG_W_WRITE_STRINGS@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+HWCAP_HAS_ALTIVEC = @HWCAP_HAS_ALTIVEC@
+HWCAP_HAS_DFP = @HWCAP_HAS_DFP@
+HWCAP_HAS_HTM = @HWCAP_HAS_HTM@
+HWCAP_HAS_ISA_2_05 = @HWCAP_HAS_ISA_2_05@
+HWCAP_HAS_ISA_2_06 = @HWCAP_HAS_ISA_2_06@
+HWCAP_HAS_ISA_2_07 = @HWCAP_HAS_ISA_2_07@
+HWCAP_HAS_ISA_3_00 = @HWCAP_HAS_ISA_3_00@
+HWCAP_HAS_VSX = @HWCAP_HAS_VSX@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LIB_UBSAN = @LIB_UBSAN@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY_2 = @PREFERRED_STACK_BOUNDARY_2@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+SOLARIS_UNDEF_LARGESOURCE = @SOLARIS_UNDEF_LARGESOURCE@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+VG_TMPDIR = @VG_TMPDIR@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = -O2 -g -std=gnu99 -Wall -Wmissing-prototypes -Wshadow \
+ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \
+ @FLAG_W_CAST_ALIGN@ @FLAG_W_CAST_QUAL@ @FLAG_W_WRITE_STRINGS@ \
+ @FLAG_W_EMPTY_BODY@ @FLAG_W_FORMAT@ @FLAG_W_FORMAT_SIGNEDNESS@ \
+ @FLAG_W_FORMAT_SECURITY@ @FLAG_W_IGNORED_QUALIFIERS@ \
+ @FLAG_W_MISSING_PARAMETER_TYPE@ @FLAG_W_OLD_STYLE_DECLARATION@ \
+ @FLAG_FNO_STACK_PROTECTOR@ @FLAG_FSANITIZE@ \
+ -fno-strict-aliasing -fno-builtin $(am__append_1)
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fpic -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# These flags are used for building the preload shared objects (PSOs).
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads. Also, we must use any
+# -mpreferred-stack-boundary flag to build the preload shared
+# objects, since that risks misaligning the client's stack and
+# results in segfaults like (eg) #324050.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \
+@VGCONF_OS_IS_DARWIN_TRUE@ -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
+ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
+AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
+AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ @FLAG_M64@ $(am__empty)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) @FLAG_M64@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_stderr
+noinst_HEADERS = ppc64_helpers.h
+EXTRA_DIST = \
+ jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest jm-int.stdout.exp-LE \
+ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-LE jm-fp.stdout.exp-LE2 jm-fp.stdout.exp-BE2 \
+ jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan jm-vmx.stdout.exp-LE \
+ jm-vmx.vgtest \
+ jm-misc.stderr.exp jm-misc.stdout.exp jm-misc.vgtest \
+ lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
+ std_reg_imm.vgtest std_reg_imm.stderr.exp std_reg_imm.stdout.exp std_reg_imm.stdout.exp-LE \
+ round.stderr.exp round.stdout.exp round.vgtest \
+ twi_tdi.stderr.exp twi_tdi.stdout.exp twi_tdi.vgtest \
+ tw_td.stderr.exp tw_td.stdout.exp tw_td.vgtest \
+ opcodes.h \
+ power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \
+ power6_mf_gpr.stderr.exp power6_mf_gpr.stdout.exp power6_mf_gpr.vgtest \
+ test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
+ test_isa_2_06_part1.stdout.exp-LE \
+ test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
+ test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
+ test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
+ test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
+ test_dfp2.stdout.exp_Without_dcffix \
+ test_dfp3.stderr.exp test_dfp3.stdout.exp test_dfp3.vgtest \
+ test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \
+ test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest \
+ jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.vgtest \
+ jm_fp_isa_2_07.stderr.exp jm_fp_isa_2_07.stdout.exp jm_fp_isa_2_07.vgtest \
+ jm_int_isa_2_07.stderr.exp jm_int_isa_2_07.vgtest \
+ jm_int_isa_2_07.stdout.exp jm_int_isa_2_07.stdout.exp-LE \
+ test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest \
+ test_tm.stderr.exp test_tm.stdout.exp test_tm.vgtest \
+ test_touch_tm.stderr.exp test_touch_tm.stdout.exp test_touch_tm.vgtest \
+ ldst_multiple.stderr.exp ldst_multiple.stdout.exp ldst_multiple.vgtest \
+ data-cache-instructions.stderr.exp data-cache-instructions.stdout.exp data-cache-instructions.vgtest \
+ test_isa_3_0_altivec.stderr.exp test_isa_3_0_altivec.stdout.exp \
+ test_isa_3_0_altivec.stdout.exp-LE test_isa_3_0_altivec.vgtest \
+ test_isa_3_0_other.stderr.exp test_isa_3_0_other.stdout.exp \
+ test_isa_3_0_other.stdout.exp-LE test_isa_3_0_other.vgtest
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+@HAS_ALTIVEC_FALSE@BUILD_FLAG_ALTIVEC =
+@HAS_ALTIVEC_TRUE@BUILD_FLAG_ALTIVEC = -maltivec
+@HAS_ALTIVEC_FALSE@ALTIVEC_FLAG =
+@HAS_ALTIVEC_TRUE@ALTIVEC_FLAG = -DHAS_ALTIVEC
+@HAS_VSX_FALSE@BUILD_FLAG_VSX =
+@HAS_VSX_TRUE@BUILD_FLAG_VSX = -mvsx
+@HAS_VSX_FALSE@VSX_FLAG =
+@HAS_VSX_TRUE@VSX_FLAG = -DHAS_VSX
+@HAS_DFP_FALSE@BUILD_FLAGS_DFP =
+@HAS_DFP_TRUE@BUILD_FLAGS_DFP = -mhard-dfp -mcpu=power6
+@HAS_DFP_FALSE@DFP_FLAG =
+@HAS_DFP_TRUE@DFP_FLAG = -DHAS_DFP
+@HAS_ISA_2_07_FALSE@BUILD_FLAGS_ISA_2_07 =
+@HAS_ISA_2_07_TRUE@BUILD_FLAGS_ISA_2_07 = -mcpu=power8
+@HAS_ISA_2_07_FALSE@ISA_2_07_FLAG =
+@HAS_ISA_2_07_TRUE@ISA_2_07_FLAG = -DHAS_ISA_2_07
+@SUPPORTS_HTM_FALSE@HTM_FLAG =
+@SUPPORTS_HTM_TRUE@HTM_FLAG = -mhtm -DSUPPORTS_HTM
+jm_insns_CFLAGS = $(AM_CFLAGS) -Wl,-z,norelro -Winline -Wall -O -g -mregnames \
+ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_ALTIVEC)
+
+@HAS_ISA_3_00_FALSE@BUILD_FLAGS_ISA_3_00 =
+@HAS_ISA_3_00_TRUE@BUILD_FLAGS_ISA_3_00 = -mcpu=power8
+@HAS_ISA_3_00_FALSE@ISA_3_00_FLAG =
+@HAS_ISA_3_00_TRUE@ISA_3_00_FLAG = -DHAS_ISA_3_00
+test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
+ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
+ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
+ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
+
+test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
+
+test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_2_07_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
+
+test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_2_07_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
+
+test_isa_3_0_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_00_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_ISA_3_00)
+
+test_isa_2_06_part3_LDADD = -lm
+test_dfp1_LDADD = -lm
+test_dfp2_LDADD = -lm
+test_dfp3_LDADD = -lm
+test_dfp4_LDADD = -lm
+test_dfp5_LDADD = -lm
+test_isa_2_07_part1_LDADD = -lm
+test_isa_2_07_part2_LDADD = -lm
+test_tm_LDADD = -lm
+test_touch_tm_LDADD = -lm
+test_isa_3_0_LDADD = -lm
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/ppc64/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/ppc64/Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+$(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__empty):
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES) $(EXTRA_allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(AM_V_CCLD)$(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+
+data-cache-instructions$(EXEEXT): $(data_cache_instructions_OBJECTS) $(data_cache_instructions_DEPENDENCIES) $(EXTRA_data_cache_instructions_DEPENDENCIES)
+ @rm -f data-cache-instructions$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(data_cache_instructions_OBJECTS) $(data_cache_instructions_LDADD) $(LIBS)
+
+jm-insns$(EXEEXT): $(jm_insns_OBJECTS) $(jm_insns_DEPENDENCIES) $(EXTRA_jm_insns_DEPENDENCIES)
+ @rm -f jm-insns$(EXEEXT)
+ $(AM_V_CCLD)$(jm_insns_LINK) $(jm_insns_OBJECTS) $(jm_insns_LDADD) $(LIBS)
+
+ldst_multiple$(EXEEXT): $(ldst_multiple_OBJECTS) $(ldst_multiple_DEPENDENCIES) $(EXTRA_ldst_multiple_DEPENDENCIES)
+ @rm -f ldst_multiple$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(ldst_multiple_OBJECTS) $(ldst_multiple_LDADD) $(LIBS)
+
+lsw$(EXEEXT): $(lsw_OBJECTS) $(lsw_DEPENDENCIES) $(EXTRA_lsw_DEPENDENCIES)
+ @rm -f lsw$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(lsw_OBJECTS) $(lsw_LDADD) $(LIBS)
+
+power6_bcmp$(EXEEXT): $(power6_bcmp_OBJECTS) $(power6_bcmp_DEPENDENCIES) $(EXTRA_power6_bcmp_DEPENDENCIES)
+ @rm -f power6_bcmp$(EXEEXT)
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+# shouldn't be needed any more, though.
+
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+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
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+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
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+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
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+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
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+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
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+ rm -rf $$f.dSYM; \
+ done
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+# Otherwise a system limit (for SysV at least) may be exceeded.
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diff --git a/none/tests/ppc64/allexec.c b/none/tests/ppc64/allexec.c
deleted file mode 120000
index 6d6a9cf..0000000
--- a/none/tests/ppc64/allexec.c
+++ /dev/null
@@ -1 +0,0 @@
-../allexec.c
\ No newline at end of file
diff --git a/none/tests/allexec.c b/none/tests/ppc64/allexec.c
similarity index 100%
copy from none/tests/allexec.c
copy to none/tests/ppc64/allexec.c
diff --git a/none/tests/ppc64/data-cache-instructions.c b/none/tests/ppc64/data-cache-instructions.c
deleted file mode 120000
index d2b3df0..0000000
--- a/none/tests/ppc64/data-cache-instructions.c
+++ /dev/null
@@ -1 +0,0 @@
-../ppc32/data-cache-instructions.c
\ No newline at end of file
diff --git a/none/tests/ppc64/data-cache-instructions.c b/none/tests/ppc64/data-cache-instructions.c
new file mode 100644
index 0000000..566f5c9
--- /dev/null
+++ b/none/tests/ppc64/data-cache-instructions.c
@@ -0,0 +1,96 @@
+/*******************************************************************************
+ * Derived from the test case for the "dcbzl" instruction support by
+ * Dave Goodell * <goodell@mcs.anl.gov>
+ * (see: Bug 135264 - dcbzl instruction missing)
+ * and: coregrind/m_machine.c/find_ppc_dcbz_sz()
+ ******************************************************************************/
+
+/* ensure we have posix_memalign */
+#define _POSIX_C_SOURCE 200112L
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <assert.h>
+
+static int query_block_size(void)
+{
+#define MAX_DCBZL_SZB (128) /* largest known effect of dcbzl */
+ char *test_block = NULL;
+ register char *rb asm ("r14");
+ int block_size, test_block_size = 4 * MAX_DCBZL_SZB, err;
+ char *p;
+
+ err = posix_memalign ((void **)&test_block, MAX_DCBZL_SZB, test_block_size);
+ if (err) {
+ fprintf(stderr, "posix_memalign() failed (err = %d [%s])\n", err, strerror(err));
+ return err;
+ }
+
+ rb = test_block;
+
+ memset(rb, 0xff, test_block_size);
+ asm volatile ("dcbzl 0, %[RB]" : : [RB] "r" (rb));
+ for (block_size = 0, p = rb; (p - rb) < test_block_size; p++)
+ if (!*p)
+ block_size++;
+ assert(block_size == 16 || block_size == 32 || block_size == 64 || block_size == 128);
+
+ free(test_block);
+ return block_size;
+}
+
+/* Test dcbzl at addr in buffer given dcbzl_block_size */
+static void test_dcbzl_at(char *addr, char *buffer, int block_size)
+{
+ int i;
+
+ /* Note: Assumption is that the length of buffer is three times the block_size. */
+ memset(buffer, 0xff, 3 * block_size);
+ asm volatile ("dcbzl %[RA], %[RB]" : : [RA] "r" (0), [RB] "r" (addr));
+ for (i = 0; i < block_size; i++) {
+ assert(buffer[i] == 0xff);
+ assert(buffer[block_size + i] == 0x00);
+ assert(buffer[2 * block_size + i] == 0xff);
+ }
+}
+
+/* Test for insn: dcbzl */
+static int test_dcbzl(void)
+{
+ int err;
+ char *buffer = NULL;
+ int buffer_size;
+ int block_size;
+
+ block_size = query_block_size();
+ assert(block_size == 16 || block_size == 32 || block_size == 64 || block_size == 128);
+ buffer_size = 3 * block_size;
+ err = posix_memalign((void **) &buffer, block_size, buffer_size);
+ if (err) {
+ fprintf(stderr, "posix_memalign() failed (err = %d [%s])\n", err, strerror(err));
+ return err;
+ }
+
+ /* check at aligned address within the test block */
+ test_dcbzl_at(&buffer[block_size], buffer, block_size);
+ fprintf(stdout, "Passed dcbzl test at aligned address within the test block.\n");
+
+ /* check at un-aligned (1 modulo block_size) address within the test block */
+ test_dcbzl_at(&buffer[block_size+1], buffer, block_size);
+ fprintf(stdout, "Passed dcbzl test at un-aligned (1 modulo block_size) address within the test block.\n");
+
+ /* check at un-aligned ((block_size - 1) modulo block_size) address within the test block */
+ test_dcbzl_at(&buffer[2 * block_size - 1], buffer, block_size);
+ fprintf(stdout, "Passed dcbzl test at un-aligned ((block_size - 1) modulo block_size) address within the test block.\n");
+
+ free(buffer);
+ return 0;
+}
+
+int main(int argc, char **argv)
+{
+ int status;
+ status = test_dcbzl ();
+ return status;
+}
diff --git a/none/tests/ppc64/jm-insns.c b/none/tests/ppc64/jm-insns.c
deleted file mode 120000
index 2b42362..0000000
--- a/none/tests/ppc64/jm-insns.c
+++ /dev/null
@@ -1 +0,0 @@
-../ppc32/jm-insns.c
\ No newline at end of file
diff --git a/none/tests/ppc64/jm-insns.c b/none/tests/ppc64/jm-insns.c
new file mode 100644
index 0000000..27f9712
--- /dev/null
+++ b/none/tests/ppc64/jm-insns.c
@@ -0,0 +1,7883 @@
+
+/* HOW TO COMPILE:
+
+* 32bit build:
+ gcc -Winline -Wall -g -O -mregnames -maltivec
+* 64bit build:
+ gcc -Winline -Wall -g -O -mregnames -maltivec -m64
+
+This program is useful, but the register usage conventions in
+it are a complete dog. In particular, _patch_op_imm has to
+be inlined, else you wind up with it segfaulting in
+completely different places due to corruption (of r20 in the
+case I chased).
+*/
+
+/*
+ * test-ppc.c:
+ * PPC tests for qemu-PPC CPU emulation checks
+ *
+ * Copyright (c) 2005 Jocelyn Mayer
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License V2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ * Theory of operations:
+ * a few registers are reserved for the test program:
+ * r14 => r18
+ * f14 => f18
+ * I do preload test values in r14 thru r17 (or less, depending on the number
+ * of register operands needed), patch the test opcode if any immediate
+ * operands are required, execute the tested opcode.
+ * XER, CCR and FPSCR are cleared before every test.
+ * I always get the result in r17 and also save XER and CCR for fixed-point
+ * operations. I also check FPSCR for floating points operations.
+ *
+ * Improvments:
+ * a more clever FPSCR management is needed: for now, I always test
+ * the round-to-zero case. Other rounding modes also need to be tested.
+ */
+
+/*
+ * Operation details
+ * -----------------
+ * The 'test' functions (via all_tests[]) are wrappers of single asm instns
+ *
+ * The 'loops' (e.g. int_loops) do the actual work:
+ * - loops over as many arguments as the instn needs (regs | imms)
+ * - sets up the environment (reset cr,xer, assign src regs...)
+ * - maybe modifies the asm instn to test different imm args
+ * - calls the test function
+ * - retrieves relevant register data (rD,cr,xer,...)
+ * - prints argument and result data.
+ *
+ * More specifically...
+ *
+ * all_tests[i] holds insn tests
+ * - of which each holds: {instn_test_arr[], description, flags}
+ *
+ * flags hold 3 instn classifiers: {family, type, arg_type}
+ *
+ * // The main test loop:
+ * do_tests( user_ctl_flags ) {
+ * foreach(curr_test = all_test[i]) {
+ *
+ * // flags are used to control what tests are run:
+ * if (curr_test->flags && !user_ctl_flags)
+ * continue;
+ *
+ * // a 'loop_family_arr' is chosen based on the 'family' flag...
+ * switch(curr_test->flags->family) {
+ * case x: loop_family_arr = int_loops;
+ * ...
+ * }
+ *
+ * // ...and the actual test_loop to run is found by indexing into
+ * // the loop_family_arr with the 'arg_type' flag:
+ * test_loop = loop_family[curr_test->flags->arg_type]
+ *
+ * // finally, loop over all instn tests for this test:
+ * foreach (instn_test = curr_test->instn_test_arr[i]) {
+ *
+ * // and call the test_loop with the current instn_test function,name
+ * test_loop( instn_test->func, instn_test->name )
+ * }
+ * }
+ * }
+ *
+ *
+ * Details of intruction patching for immediate operands
+ * -----------------------------------------------------
+ * All the immediate insn test functions are of the form {imm_insn, blr}
+ * In order to patch one of these functions, we simply copy both insns
+ * to a stack buffer, and rewrite the immediate part of imm_insn.
+ * We then execute our stack buffer.
+ * All ppc instructions are 32bits wide, which makes this fairly easy.
+ *
+ * Example:
+ * extern void test_addi (void);
+ * asm(".section \".text\"\n"
+ * " .align 2\n"
+ * " .type test_addi,@function\n"
+ * "test_addi:\n"
+ * " addi\n"
+ * " blr\n"
+ * " .previous\n"
+ * );
+ *
+ * We are interested only in:
+ * " addi 17, 14, 0\n"
+ * " blr\n"
+ *
+ * In a loop test, we may see:
+ * uint32_t func_buf[2]; // our new stack based 'function'
+ * for imm... // loop over imm
+ * init_function( &func, func_buf ); // copy insns, set func ptr
+ * patch_op_imm16(&func_buf[0], imm); // patch 'addi' insn
+ * ...
+ * (*func)(); // exec our rewritten code
+ *
+ * patch_op_imm16() itself simply takes the uint32_t insn and overwrites
+ * the immediate field with the new value (which, for 'addi', is the
+ * low 16 bits).
+ *
+ * So in the loop test, if 'imm' is currently 9, and p[0] is:
+ * 0x3A2E0000 => addi 17, 14, 0
+ *
+ * after patch_op_imm16(), func_buf[0] becomes:
+ * 0x3A2E0009 => addi 17, 14, 9
+ *
+ * Note: init_function() needs to be called on every iteration
+ * - don't ask me why!
+*/
+
+
+/**********************************************************************/
+/* Uncomment to enable many arguments for altivec insns */
+#define USAGE_SIMPLE
+
+/* Uncomment to enable many arguments for altivec insns */
+//#define ALTIVEC_ARGS_LARGE
+
+/* Uncomment to enable output of CR flags for float tests */
+//#define TEST_FLOAT_FLAGS
+
+/* Uncomment to enable debug output */
+//#define DEBUG_ARGS_BUILD
+//#define DEBUG_FILTER
+
+/* These should be set at build time */
+//#define NO_FLOAT
+//#define HAS_ALTIVEC // CFLAGS += -maltivec
+//#define IS_PPC405
+/**********************************************************************/
+
+
+#include <stdint.h>
+#include "tests/sys_mman.h"
+#include "tests/malloc.h" // memalign16
+#include "./opcodes.h"
+
+#define STATIC_ASSERT(e) sizeof(struct { int:-!(e); })
+
+/* Something of the same size as void*, so can be safely be coerced
+ * to/from a pointer type. Also same size as the host's gp registers.
+ * According to the AltiVec section of the GCC manual, the syntax does
+ * not allow the use of a typedef name as a type specifier in conjunction
+ * with the vector keyword, so typedefs uint[32|64]_t are #undef'ed here
+ * and redefined using #define.
+ */
+#undef uint32_t
+#undef uint64_t
+#define uint32_t unsigned int
+#define uint64_t unsigned long long int
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif /* __powerpc64__ */
+
+enum {
+ compile_time_test1 = STATIC_ASSERT(sizeof(uint32_t) == 4),
+ compile_time_test2 = STATIC_ASSERT(sizeof(uint64_t) == 8),
+};
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+
+/* XXXX these must all be callee-save regs! */
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+register HWord_t r14 __asm__ ("r14");
+register HWord_t r15 __asm__ ("r15");
+register HWord_t r16 __asm__ ("r16");
+register HWord_t r17 __asm__ ("r17");
+
+#include "config.h" // HAS_ALTIVEC
+#if defined (HAS_ALTIVEC)
+# include <altivec.h>
+#endif
+#include <assert.h>
+#include <ctype.h> // isspace
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h> // getopt
+
+
+#ifndef __powerpc64__
+#define ASSEMBLY_FUNC(__fname, __insn) \
+asm(".section \".text\"\n" \
+ "\t.align 2\n" \
+ "\t.type "__fname",@function\n" \
+ __fname":\n" \
+ "\t"__insn"\n" \
+ "\tblr\n" \
+ "\t.previous\n" \
+ )
+#else
+#if defined(VGP_ppc64be_linux)
+#define ASSEMBLY_FUNC(__fname, __insn) \
+asm(".section \".text\"\n" \
+ "\t.align 2\n" \
+ "\t.global "__fname"\n" \
+ "\t.section \".opd\",\"aw\"\n" \
+ "\t.align 3\n" \
+ ""__fname":\n" \
+ "\t.quad ."__fname",.TOC.@tocbase,0\n" \
+ "\t.previous\n" \
+ "\t.type ."__fname",@function\n" \
+ "\t.global ."__fname"\n" \
+ "."__fname":\n" \
+ "\t"__insn"\n" \
+ "\tblr\n" \
+ )
+#elif defined(VGP_ppc64le_linux)
+#define ASSEMBLY_FUNC(__fname, __insn) \
+asm(".section \".text\"\n" \
+ "\t.align 2\n" \
+ "\t.global "__fname"\n" \
+ ""__fname":\n" \
+ "\t"__insn"\n" \
+ "\tblr\n" \
+ )
+#endif // VGP_ppc64 or VGP_ppc64le
+#endif // #ifndef __powerpc64__
+
+
+/* Return a pointer to a 1-page area where is is safe to both write
+ and execute instructions. Area is filled with 'trap' insns. */
+static
+uint32_t* get_rwx_area ( void )
+{
+ int i;
+ static uint32_t* p = NULL;
+ if (p == NULL) {
+ p = mmap(NULL, 4096, PROT_READ|PROT_WRITE|PROT_EXEC,
+ MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
+ assert(p != MAP_FAILED);
+ }
+
+ for (i = 0; i < 4096/sizeof(uint32_t); i++)
+ p[i] = 0x7fe00008; /* trap */
+
+ return p;
+}
+
+
+/* -------------- BEGIN #include "test-ppc.h" -------------- */
+/*
+ * test-ppc.h:
+ * PPC tests for qemu-PPC CPU emulation checks - definitions
+ *
+ * Copyright (c) 2005 Jocelyn Mayer
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License V2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#if !defined (__TEST_PPC_H__)
+#define __TEST_PPC_H__
+
+#include <stdint.h>
+
+typedef void (*test_func_t) (void);
+typedef struct test_t test_t;
+typedef struct test_table_t test_table_t;
+struct test_t {
+ test_func_t func;
+ const char *name;
+};
+
+struct test_table_t {
+ test_t *tests;
+ const char *name;
+ uint32_t flags;
+};
+
+typedef void (*test_loop_t) (const char *name, test_func_t func,
+ uint32_t flags);
+
+enum test_flags {
+ /* Nb arguments */
+ PPC_ONE_ARG = 0x00000001,
+ PPC_TWO_ARGS = 0x00000002,
+ PPC_THREE_ARGS = 0x00000003,
+ PPC_CMP_ARGS = 0x00000004, // family: compare
+ PPC_CMPI_ARGS = 0x00000005, // family: compare
+ PPC_TWO_I16 = 0x00000006, // family: arith/logical
+ PPC_SPECIAL = 0x00000007, // family: logical
+ PPC_LD_ARGS = 0x00000008, // family: ldst
+ PPC_LDX_ARGS = 0x00000009, // family: ldst
+ PPC_ST_ARGS = 0x0000000A, // family: ldst
+ PPC_STX_ARGS = 0x0000000B, // family: ldst
+ PPC_ONE_IMM = 0x0000000C, // PPC_MISC family
+ PPC_NB_ARGS = 0x0000000F,
+ /* Type */
+ PPC_ARITH = 0x00000100,
+ PPC_LOGICAL = 0x00000200,
+ PPC_COMPARE = 0x00000300,
+ PPC_CROP = 0x00000400,
+ PPC_LDST = 0x00000500,
+ PPC_POPCNT = 0x00000600,
+ PPC_ANY = 0x00000700,
+ PPC_TYPE = 0x00000F00,
+ /* Family */
+ PPC_INTEGER = 0x00010000,
+ PPC_FLOAT = 0x00020000,
+ PPC_405 = 0x00030000,
+ PPC_ALTIVEC = 0x00040000,
+ PPC_FALTIVEC = 0x00050000,
+ PPC_MISC = 0x00060000,
+ PPC_FAMILY = 0x000F0000,
+ /* Flags: these may be combined, so use separate bitfields. */
+ PPC_CR = 0x01000000,
+ PPC_XER_CA = 0x02000000,
+};
+
+#endif /* !defined (__TEST_PPC_H__) */
+
+/* -------------- END #include "test-ppc.h" -------------- */
+
+
+
+
+#if defined (DEBUG_ARGS_BUILD)
+#define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define AB_DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+#if defined (DEBUG_FILTER)
+#define FDPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define FDPRINTF(fmt, args...) do { } while (0)
+#endif
+
+
+/* Produce the 64-bit pattern corresponding to the supplied double. */
+static uint64_t double_to_bits ( double d )
+{
+ union { uint64_t i; double d; } u;
+ assert(8 == sizeof(uint64_t));
+ assert(8 == sizeof(double));
+ assert(8 == sizeof(u));
+ u.d = d;
+ return u.i;
+}
+
+#if 0
+static float bits_to_float ( uint32_t i )
+{
+ union { uint32_t i; float f; } u;
+ assert(4 == sizeof(uint32_t));
+ assert(4 == sizeof(float));
+ assert(4 == sizeof(u));
+ u.i = i;
+ return u.f;
+}
+#endif
+
+
+#if defined (HAS_ALTIVEC)
+static void AB_DPRINTF_VEC32x4 ( vector unsigned int v )
+{
+#if defined (DEBUG_ARGS_BUILD)
+ int i;
+ unsigned int* p_int = (unsigned int*)&v;
+ AB_DPRINTF("val");
+ for (i=0; i<4; i++) {
+ AB_DPRINTF(" %08x", p_int[i]);
+ }
+ AB_DPRINTF("\n");
+#endif
+}
+#endif
+
+
+#define unused __attribute__ (( unused ))
+
+
+/* -------------- BEGIN #include "ops-ppc.c" -------------- */
+
+/* #include "test-ppc.h" */
+
+static void test_add (void)
+{
+ __asm__ __volatile__ ("add 17, 14, 15");
+}
+
+static void test_addo (void)
+{
+ __asm__ __volatile__ ("addo 17, 14, 15");
+}
+
+static void test_addc (void)
+{
+ __asm__ __volatile__ ("addc 17, 14, 15");
+}
+
+static void test_addco (void)
+{
+ __asm__ __volatile__ ("addco 17, 14, 15");
+}
+
+static void test_divw (void)
+{
+ __asm__ __volatile__ ("divw 17, 14, 15");
+}
+
+static void test_divwo (void)
+{
+ __asm__ __volatile__ ("divwo 17, 14, 15");
+}
+
+static void test_divwu (void)
+{
+ __asm__ __volatile__ ("divwu 17, 14, 15");
+}
+
+static void test_divwuo (void)
+{
+ __asm__ __volatile__ ("divwuo 17, 14, 15");
+}
+
+static void test_mulhw (void)
+{
+ __asm__ __volatile__ ("mulhw 17, 14, 15");
+}
+
+static void test_mulhwu (void)
+{
+ __asm__ __volatile__ ("mulhwu 17, 14, 15");
+}
+
+static void test_mullw (void)
+{
+ __asm__ __volatile__ ("mullw 17, 14, 15");
+}
+
+static void test_mullwo (void)
+{
+ __asm__ __volatile__ ("mullwo 17, 14, 15");
+}
+
+static void test_subf (void)
+{
+ __asm__ __volatile__ ("subf 17, 14, 15");
+}
+
+static void test_subfo (void)
+{
+ __asm__ __volatile__ ("subfo 17, 14, 15");
+}
+
+static void test_subfc (void)
+{
+ __asm__ __volatile__ ("subfc 17, 14, 15");
+}
+
+static void test_subfco (void)
+{
+ __asm__ __volatile__ ("subfco 17, 14, 15");
+}
+
+#ifdef __powerpc64__
+static void test_mulld (void)
+{
+ __asm__ __volatile__ ("mulld 17, 14, 15");
+}
+
+static void test_mulldo (void)
+{
+ __asm__ __volatile__ ("mulldo 17, 14, 15");
+}
+
+static void test_mulhd (void)
+{
+ __asm__ __volatile__ ("mulhd 17, 14, 15");
+}
+
+static void test_mulhdu (void)
+{
+ __asm__ __volatile__ ("mulhdu 17, 14, 15");
+}
+
+static void test_divd (void)
+{
+ __asm__ __volatile__ ("divd 17, 14, 15");
+}
+
+static void test_divdu (void)
+{
+ __asm__ __volatile__ ("divdu 17, 14, 15");
+}
+
+static void test_divdo (void)
+{
+ __asm__ __volatile__ ("divdo 17, 14, 15");
+}
+
+static void test_divduo (void)
+{
+ __asm__ __volatile__ ("divduo 17, 14, 15");
+}
+#endif // #ifdef __powerpc64__
+
+static test_t tests_ia_ops_two[] = {
+ { &test_add , " add", },
+ { &test_addo , " addo", },
+ { &test_addc , " addc", },
+ { &test_addco , " addco", },
+ { &test_divw , " divw", },
+ { &test_divwo , " divwo", },
+ { &test_divwu , " divwu", },
+ { &test_divwuo , " divwuo", },
+ { &test_mulhw , " mulhw", },
+ { &test_mulhwu , " mulhwu", },
+ { &test_mullw , " mullw", },
+ { &test_mullwo , " mullwo", },
+ { &test_subf , " subf", },
+ { &test_subfo , " subfo", },
+ { &test_subfc , " subfc", },
+ { &test_subfco , " subfco", },
+#ifdef __powerpc64__
+ { &test_mulhd , " mulhd", },
+ { &test_mulhdu , " mulhdu", },
+ { &test_mulld , " mulld", },
+ { &test_mulldo , " mulldo", },
+ { &test_divd , " divd", },
+ { &test_divdu , " divdu", },
+ { &test_divdo , " divdo", },
+ { &test_divduo , " divduo", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+
+static void test_add_ (void)
+{
+ __asm__ __volatile__ ("add. 17, 14, 15");
+}
+
+static void test_addo_ (void)
+{
+ __asm__ __volatile__ ("addo. 17, 14, 15");
+}
+
+static void test_addc_ (void)
+{
+ __asm__ __volatile__ ("addc. 17, 14, 15");
+}
+
+static void test_addco_ (void)
+{
+ __asm__ __volatile__ ("addco. 17, 14, 15");
+}
+
+static void test_divw_ (void)
+{
+ __asm__ __volatile__ ("divw. 17, 14, 15");
+}
+
+static void test_divwo_ (void)
+{
+ __asm__ __volatile__ ("divwo. 17, 14, 15");
+}
+
+static void test_divwu_ (void)
+{
+ __asm__ __volatile__ ("divwu. 17, 14, 15");
+}
+
+static void test_divwuo_ (void)
+{
+ __asm__ __volatile__ ("divwuo. 17, 14, 15");
+}
+
+static void test_mulhw_ (void)
+{
+ __asm__ __volatile__ ("mulhw. 17, 14, 15");
+}
+
+static void test_mulhwu_ (void)
+{
+ __asm__ __volatile__ ("mulhwu. 17, 14, 15");
+}
+
+static void test_mullw_ (void)
+{
+ __asm__ __volatile__ ("mullw. 17, 14, 15");
+}
+
+static void test_mullwo_ (void)
+{
+ __asm__ __volatile__ ("mullwo. 17, 14, 15");
+}
+
+static void test_subf_ (void)
+{
+ __asm__ __volatile__ ("subf. 17, 14, 15");
+}
+
+static void test_subfo_ (void)
+{
+ __asm__ __volatile__ ("subfo. 17, 14, 15");
+}
+
+static void test_subfc_ (void)
+{
+ __asm__ __volatile__ ("subfc. 17, 14, 15");
+}
+
+static void test_subfco_ (void)
+{
+ __asm__ __volatile__ ("subfco. 17, 14, 15");
+}
+
+#ifdef __powerpc64__
+static void test_mulhd_ (void)
+{
+ __asm__ __volatile__ ("mulhd. 17, 14, 15");
+}
+
+static void test_mulhdu_ (void)
+{
+ __asm__ __volatile__ ("mulhdu. 17, 14, 15");
+}
+
+static void test_mulld_ (void)
+{
+ __asm__ __volatile__ ("mulld. 17, 14, 15");
+}
+
+static void test_mulldo_ (void)
+{
+ __asm__ __volatile__ ("mulldo. 17, 14, 15");
+}
+
+static void test_divd_ (void)
+{
+ __asm__ __volatile__ ("divd. 17, 14, 15");
+}
+
+static void test_divdu_ (void)
+{
+ __asm__ __volatile__ ("divdu. 17, 14, 15");
+}
+
+static void test_divdo_ (void)
+{
+ __asm__ __volatile__ ("divdo. 17, 14, 15");
+}
+
+static void test_divduo_ (void)
+{
+ __asm__ __volatile__ ("divduo. 17, 14, 15");
+}
+#endif // #ifdef __powerpc64__
+
+static test_t tests_iar_ops_two[] = {
+ { &test_add_ , " add.", },
+ { &test_addo_ , " addo.", },
+ { &test_addc_ , " addc.", },
+ { &test_addco_ , " addco.", },
+ { &test_divw_ , " divw.", },
+ { &test_divwo_ , " divwo.", },
+ { &test_divwu_ , " divwu.", },
+ { &test_divwuo_ , " divwuo.", },
+ { &test_mulhw_ , " mulhw.", },
+ { &test_mulhwu_ , " mulhwu.", },
+ { &test_mullw_ , " mullw.", },
+ { &test_mullwo_ , " mullwo.", },
+ { &test_subf_ , " subf.", },
+ { &test_subfo_ , " subfo.", },
+ { &test_subfc_ , " subfc.", },
+ { &test_subfco_ , " subfco.", },
+#ifdef __powerpc64__
+ { &test_mulhd_ , " mulhd.", },
+ { &test_mulhdu_ , " mulhdu.", },
+ { &test_mulld_ , " mulld.", },
+ { &test_mulldo_ , " mulldo.", },
+ { &test_divd_ , " divd.", },
+ { &test_divdu_ , " divdu.", },
+ { &test_divdo_ , " divdo.", },
+ { &test_divduo_ , " divduo.", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+
+static void test_adde (void)
+{
+ __asm__ __volatile__ ("adde 17, 14, 15");
+}
+
+static void test_addeo (void)
+{
+ __asm__ __volatile__ ("addeo 17, 14, 15");
+}
+
+static void test_subfe (void)
+{
+ __asm__ __volatile__ ("subfe 17, 14, 15");
+}
+
+static void test_subfeo (void)
+{
+ __asm__ __volatile__ ("subfeo 17, 14, 15");
+}
+
+static test_t tests_iac_ops_two[] = {
+ { &test_adde , " adde", },
+ { &test_addeo , " addeo", },
+ { &test_subfe , " subfe", },
+ { &test_subfeo , " subfeo", },
+ { NULL, NULL, },
+};
+
+static void test_adde_ (void)
+{
+ __asm__ __volatile__ ("adde. 17, 14, 15");
+}
+
+static void test_addeo_ (void)
+{
+ __asm__ __volatile__ ("addeo. 17, 14, 15");
+}
+
+static void test_subfe_ (void)
+{
+ __asm__ __volatile__ ("subfe. 17, 14, 15");
+}
+
+static void test_subfeo_ (void)
+{
+ __asm__ __volatile__ ("subfeo. 17, 14, 15");
+}
+
+static test_t tests_iacr_ops_two[] = {
+ { &test_adde_ , " adde.", },
+ { &test_addeo_ , " addeo.", },
+ { &test_subfe_ , " subfe.", },
+ { &test_subfeo_ , " subfeo.", },
+ { NULL, NULL, },
+};
+
+static void test_and (void)
+{
+ __asm__ __volatile__ ("and 17, 14, 15");
+}
+
+static void test_andc (void)
+{
+ __asm__ __volatile__ ("andc 17, 14, 15");
+}
+
+static void test_eqv (void)
+{
+ __asm__ __volatile__ ("eqv 17, 14, 15");
+}
+
+static void test_nand (void)
+{
+ __asm__ __volatile__ ("nand 17, 14, 15");
+}
+
+static void test_nor (void)
+{
+ __asm__ __volatile__ ("nor 17, 14, 15");
+}
+
+static void test_or (void)
+{
+ __asm__ __volatile__ ("or 17, 14, 15");
+}
+
+static void test_orc (void)
+{
+ __asm__ __volatile__ ("orc 17, 14, 15");
+}
+
+static void test_xor (void)
+{
+ __asm__ __volatile__ ("xor 17, 14, 15");
+}
+
+static void test_slw (void)
+{
+ __asm__ __volatile__ ("slw 17, 14, 15");
+}
+
+static void test_sraw (void)
+{
+ __asm__ __volatile__ ("sraw 17, 14, 15");
+}
+
+static void test_srw (void)
+{
+ __asm__ __volatile__ ("srw 17, 14, 15");
+}
+
+#ifdef __powerpc64__
+static void test_sld (void)
+{
+ __asm__ __volatile__ ("sld 17, 14, 15");
+}
+
+static void test_srad (void)
+{
+ __asm__ __volatile__ ("srad 17, 14, 15");
+}
+
+static void test_srd (void)
+{
+ __asm__ __volatile__ ("srd 17, 14, 15");
+}
+#endif // #ifdef __powerpc64__
+
+static test_t tests_il_ops_two[] = {
+ { &test_and , " and", },
+ { &test_andc , " andc", },
+ { &test_eqv , " eqv", },
+ { &test_nand , " nand", },
+ { &test_nor , " nor", },
+ { &test_or , " or", },
+ { &test_orc , " orc", },
+ { &test_xor , " xor", },
+ { &test_slw , " slw", },
+ { &test_sraw , " sraw", },
+ { &test_srw , " srw", },
+#ifdef __powerpc64__
+ { &test_sld , " sld", },
+ { &test_srad , " srad", },
+ { &test_srd , " srd", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+
+static void test_and_ (void)
+{
+ __asm__ __volatile__ ("and. 17, 14, 15");
+}
+
+static void test_andc_ (void)
+{
+ __asm__ __volatile__ ("andc. 17, 14, 15");
+}
+
+static void test_eqv_ (void)
+{
+ __asm__ __volatile__ ("eqv. 17, 14, 15");
+}
+
+static void test_nand_ (void)
+{
+ __asm__ __volatile__ ("nand. 17, 14, 15");
+}
+
+static void test_nor_ (void)
+{
+ __asm__ __volatile__ ("nor. 17, 14, 15");
+}
+
+static void test_or_ (void)
+{
+ __asm__ __volatile__ ("or. 17, 14, 15");
+}
+
+static void test_orc_ (void)
+{
+ __asm__ __volatile__ ("orc. 17, 14, 15");
+}
+
+static void test_xor_ (void)
+{
+ __asm__ __volatile__ ("xor. 17, 14, 15");
+}
+
+static void test_slw_ (void)
+{
+ __asm__ __volatile__ ("slw. 17, 14, 15");
+}
+
+static void test_sraw_ (void)
+{
+ __asm__ __volatile__ ("sraw. 17, 14, 15");
+}
+
+static void test_srw_ (void)
+{
+ __asm__ __volatile__ ("srw. 17, 14, 15");
+}
+
+#ifdef __powerpc64__
+static void test_sld_ (void)
+{
+ __asm__ __volatile__ ("sld. 17, 14, 15");
+}
+
+static void test_srad_ (void)
+{
+ __asm__ __volatile__ ("srad. 17, 14, 15");
+}
+
+static void test_srd_ (void)
+{
+ __asm__ __volatile__ ("srd. 17, 14, 15");
+}
+#endif // #ifdef __powerpc64__
+
+static test_t tests_ilr_ops_two[] = {
+ { &test_and_ , " and.", },
+ { &test_andc_ , " andc.", },
+ { &test_eqv_ , " eqv.", },
+ { &test_nand_ , " nand.", },
+ { &test_nor_ , " nor.", },
+ { &test_or_ , " or.", },
+ { &test_orc_ , " orc.", },
+ { &test_xor_ , " xor.", },
+ { &test_slw_ , " slw.", },
+ { &test_sraw_ , " sraw.", },
+ { &test_srw_ , " srw.", },
+#ifdef __powerpc64__
+ { &test_sld_ , " sld.", },
+ { &test_srad_ , " srad.", },
+ { &test_srd_ , " srd.", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+
+static void test_cmpw (void)
+{
+ __asm__ __volatile__ ("cmpw 2, 14, 15");
+}
+
+static void test_cmplw (void)
+{
+ __asm__ __volatile__ ("cmplw 2, 14, 15");
+}
+
+#ifdef __powerpc64__
+static void test_cmpd (void)
+{
+ __asm__ __volatile__ ("cmpd 2, 14, 15");
+}
+
+static void test_cmpld (void)
+{
+ __asm__ __volatile__ ("cmpld 2, 14, 15");
+}
+#endif // #ifdef __powerpc64__
+
+static test_t tests_icr_ops_two[] = {
+ { &test_cmpw , " cmpw", },
+ { &test_cmplw , " cmplw", },
+#ifdef __powerpc64__
+ { &test_cmpd , " cmpd", },
+ { &test_cmpld , " cmpld", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+
+extern void test_cmpwi (void);
+ASSEMBLY_FUNC("test_cmpwi", "cmpwi 2, 14, 0");
+
+extern void test_cmplwi (void);
+ASSEMBLY_FUNC("test_cmplwi", "cmplwi 2, 14, 0");
+
+#ifdef __powerpc64__
+extern void test_cmpdi (void);
+ASSEMBLY_FUNC("test_cmpdi", "cmpdi 2, 14, 0");
+
+extern void test_cmpldi (void);
+ASSEMBLY_FUNC("test_cmpldi", "cmpldi 2, 14, 0");
+#endif // #ifdef __powerpc64__
+
+static test_t tests_icr_ops_two_i16[] = {
+ { &test_cmpwi , " cmpwi", },
+ { &test_cmplwi , " cmplwi", },
+#ifdef __powerpc64__
+ { &test_cmpdi , " cmpdi", },
+ { &test_cmpldi , " cmpldi", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+
+extern void test_addi (void);
+ASSEMBLY_FUNC("test_addi", "addi 17, 14, 0");
+
+extern void test_addic (void);
+ASSEMBLY_FUNC("test_addic", "addic 17, 14, 0");
+
+extern void test_addis (void);
+ASSEMBLY_FUNC("test_addis", "addis 17, 14, 0");
+
+extern void test_mulli (void);
+ASSEMBLY_FUNC("test_mulli", "mulli 17, 14, 0");
+
+extern void test_subfic (void);
+ASSEMBLY_FUNC("test_subfic", "subfic 17, 14, 0");
+
+static test_t tests_ia_ops_two_i16[] = {
+ { &test_addi , " addi", },
+ { &test_addic , " addic", },
+ { &test_addis , " addis", },
+ { &test_mulli , " mulli", },
+ { &test_subfic , " subfic", },
+ { NULL, NULL, },
+};
+
+extern void test_addic_ (void);
+ASSEMBLY_FUNC("test_addic_", "addic. 17, 14, 0");
+
+static test_t tests_iar_ops_two_i16[] = {
+ { &test_addic_ , " addic.", },
+ { NULL, NULL, },
+};
+
+extern void test_ori (void);
+ASSEMBLY_FUNC("test_ori", "ori 17, 14, 0");
+
+extern void test_oris (void);
+ASSEMBLY_FUNC("test_oris", "oris 17, 14, 0");
+
+extern void test_xori (void);
+ASSEMBLY_FUNC("test_xori", "xori 17, 14, 0");
+
+extern void test_xoris (void);
+ASSEMBLY_FUNC("test_xoris", "xoris 17, 14, 0");
+
+static test_t tests_il_ops_two_i16[] = {
+ { &test_ori , " ori", },
+ { &test_oris , " oris", },
+ { &test_xori , " xori", },
+ { &test_xoris , " xoris", },
+ { NULL, NULL, },
+};
+
+extern void test_andi_ (void);
+ASSEMBLY_FUNC("test_andi_", "andi. 17, 14, 0");
+
+extern void test_andis_ (void);
+ASSEMBLY_FUNC("test_andis_", "andis. 17, 14, 0");
+
+static test_t tests_ilr_ops_two_i16[] = {
+ { &test_andi_ , " andi.", },
+ { &test_andis_ , " andis.", },
+ { NULL, NULL, },
+};
+
+static void test_crand (void)
+{
+ __asm__ __volatile__ ("crand 17, 14, 15");
+}
+
+static void test_crandc (void)
+{
+ __asm__ __volatile__ ("crandc 17, 14, 15");
+}
+
+static void test_creqv (void)
+{
+ __asm__ __volatile__ ("creqv 17, 14, 15");
+}
+
+static void test_crnand (void)
+{
+ __asm__ __volatile__ ("crnand 17, 14, 15");
+}
+
+static void test_crnor (void)
+{
+ __asm__ __volatile__ ("crnor 17, 14, 15");
+}
+
+static void test_cror (void)
+{
+ __asm__ __volatile__ ("cror 17, 14, 15");
+}
+
+static void test_crorc (void)
+{
+ __asm__ __volatile__ ("crorc 17, 14, 15");
+}
+
+static void test_crxor (void)
+{
+ __asm__ __volatile__ ("crxor 17, 14, 15");
+}
+
+static test_t tests_crl_ops_two[] = {
+ { &test_crand , " crand", },
+ { &test_crandc , " crandc", },
+ { &test_creqv , " creqv", },
+ { &test_crnand , " crnand", },
+ { &test_crnor , " crnor", },
+ { &test_cror , " cror", },
+ { &test_crorc , " crorc", },
+ { &test_crxor , " crxor", },
+ { NULL, NULL, },
+};
+
+static void test_addme (void)
+{
+ __asm__ __volatile__ ("addme 17, 14");
+}
+
+static void test_addmeo (void)
+{
+ __asm__ __volatile__ ("addmeo 17, 14");
+}
+
+static void test_addze (void)
+{
+ __asm__ __volatile__ ("addze 17, 14");
+}
+
+static void test_addzeo (void)
+{
+ __asm__ __volatile__ ("addzeo 17, 14");
+}
+
+static void test_subfme (void)
+{
+ __asm__ __volatile__ ("subfme 17, 14");
+}
+
+static void test_subfmeo (void)
+{
+ __asm__ __volatile__ ("subfmeo 17, 14");
+}
+
+static void test_subfze (void)
+{
+ __asm__ __volatile__ ("subfze 17, 14");
+}
+
+static void test_subfzeo (void)
+{
+ __asm__ __volatile__ ("subfzeo 17, 14");
+}
+
+static test_t tests_iac_ops_one[] = {
+ { &test_addme , " addme", },
+ { &test_addmeo , " addmeo", },
+ { &test_addze , " addze", },
+ { &test_addzeo , " addzeo", },
+ { &test_subfme , " subfme", },
+ { &test_subfmeo , " subfmeo", },
+ { &test_subfze , " subfze", },
+ { &test_subfzeo , " subfzeo", },
+ { NULL, NULL, },
+};
+
+static void test_addme_ (void)
+{
+ __asm__ __volatile__ ("addme. 17, 14");
+}
+
+static void test_addmeo_ (void)
+{
+ __asm__ __volatile__ ("addmeo. 17, 14");
+}
+
+static void test_addze_ (void)
+{
+ __asm__ __volatile__ ("addze. 17, 14");
+}
+
+static void test_addzeo_ (void)
+{
+ __asm__ __volatile__ ("addzeo. 17, 14");
+}
+
+static void test_subfme_ (void)
+{
+ __asm__ __volatile__ ("subfme. 17, 14");
+}
+
+static void test_subfmeo_ (void)
+{
+ __asm__ __volatile__ ("subfmeo. 17, 14");
+}
+
+static void test_subfze_ (void)
+{
+ __asm__ __volatile__ ("subfze. 17, 14");
+}
+
+static void test_subfzeo_ (void)
+{
+ __asm__ __volatile__ ("subfzeo. 17, 14");
+}
+
+static test_t tests_iacr_ops_one[] = {
+ { &test_addme_ , " addme.", },
+ { &test_addmeo_ , " addmeo.", },
+ { &test_addze_ , " addze.", },
+ { &test_addzeo_ , " addzeo.", },
+ { &test_subfme_ , " subfme.", },
+ { &test_subfmeo_ , " subfmeo.", },
+ { &test_subfze_ , " subfze.", },
+ { &test_subfzeo_ , " subfzeo.", },
+ { NULL, NULL, },
+};
+
+static void test_cntlzw (void)
+{
+ __asm__ __volatile__ ("cntlzw 17, 14");
+}
+
+static void test_extsb (void)
+{
+ __asm__ __volatile__ ("extsb 17, 14");
+}
+
+static void test_extsh (void)
+{
+ __asm__ __volatile__ ("extsh 17, 14");
+}
+
+static void test_neg (void)
+{
+ __asm__ __volatile__ ("neg 17, 14");
+}
+
+static void test_nego (void)
+{
+ __asm__ __volatile__ ("nego 17, 14");
+}
+
+#ifdef __powerpc64__
+static void test_cntlzd (void)
+{
+ __asm__ __volatile__ ("cntlzd 17, 14");
+}
+
+static void test_extsw (void)
+{
+ __asm__ __volatile__ ("extsw 17, 14");
+}
+#endif // #ifdef __powerpc64__
+
+static test_t tests_il_ops_one[] = {
+ { &test_cntlzw , " cntlzw", },
+ { &test_extsb , " extsb", },
+ { &test_extsh , " extsh", },
+ { &test_neg , " neg", },
+ { &test_nego , " nego", },
+#ifdef __powerpc64__
+ { &test_cntlzd , " cntlzd", },
+ { &test_extsw , " extsw", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+
+static void test_cntlzw_ (void)
+{
+ __asm__ __volatile__ ("cntlzw. 17, 14");
+}
+
+static void test_extsb_ (void)
+{
+ __asm__ __volatile__ ("extsb. 17, 14");
+}
+
+static void test_extsh_ (void)
+{
+ __asm__ __volatile__ ("extsh. 17, 14");
+}
+
+static void test_neg_ (void)
+{
+ __asm__ __volatile__ ("neg. 17, 14");
+}
+
+static void test_nego_ (void)
+{
+ __asm__ __volatile__ ("nego. 17, 14");
+}
+
+#ifdef __powerpc64__
+static void test_cntlzd_ (void)
+{
+ __asm__ __volatile__ ("cntlzd. 17, 14");
+}
+
+static void test_extsw_ (void)
+{
+ __asm__ __volatile__ ("extsw. 17, 14");
+}
+#endif // #ifdef __powerpc64__
+
+static test_t tests_ilr_ops_one[] = {
+ { &test_cntlzw_ , " cntlzw.", },
+ { &test_extsb_ , " extsb.", },
+ { &test_extsh_ , " extsh.", },
+ { &test_neg_ , " neg.", },
+ { &test_nego_ , " nego.", },
+#ifdef __powerpc64__
+ { &test_cntlzd_ , " cntlzd.", },
+ { &test_extsw_ , " extsw.", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+
+extern void test_rlwimi (void);
+ASSEMBLY_FUNC("test_rlwimi", "rlwimi 17, 14, 0, 0, 0");
+
+extern void test_rlwinm (void);
+ASSEMBLY_FUNC("test_rlwinm", "rlwinm 17, 14, 0, 0, 0");
+
+extern void test_rlwnm (void);
+ASSEMBLY_FUNC("test_rlwnm", "rlwnm 17, 14, 15, 0, 0");
+
+extern void test_srawi (void);
+ASSEMBLY_FUNC("test_srawi", "srawi 17, 14, 0");
+
+static void test_mfcr (void)
+{
+ __asm__ __volatile__ ("mfcr 17");
+}
+
+static void test_mfspr (void)
+{
+ __asm__ __volatile__ ("mfspr 17, 1");
+}
+
+static void test_mtspr (void)
+{
+ __asm__ __volatile__ ("mtspr 1, 14");
+}
+
+#ifdef __powerpc64__
+extern void test_rldcl (void);
+ASSEMBLY_FUNC("test_rldcl", "rldcl 17, 14, 15, 0");
+
+extern void test_rldcr (void);
+ASSEMBLY_FUNC("test_rldcr", "rldcr 17, 14, 15, 0");
+
+extern void test_rldic (void);
+ASSEMBLY_FUNC("test_rldic", "rldic 17, 14, 0, 0");
+
+extern void test_rldicl (void);
+ASSEMBLY_FUNC("test_rldicl", "rldicl 17, 14, 0, 0");
+
+extern void test_rldicr (void);
+ASSEMBLY_FUNC("test_rldicr", "rldicr 17, 14, 0, 0");
+
+extern void test_rldimi (void);
+ASSEMBLY_FUNC("test_rldimi", "rldimi 17, 14, 0, 0");
+
+extern void test_sradi (void);
+ASSEMBLY_FUNC("test_sradi", "sradi 17, 14, 0");
+#endif // #ifdef __powerpc64__
+
+static test_t tests_il_ops_spe[] = {
+ { &test_rlwimi , " rlwimi", },
+ { &test_rlwinm , " rlwinm", },
+ { &test_rlwnm , " rlwnm", },
+ { &test_srawi , " srawi", },
+ { &test_mfcr , " mfcr", },
+ { &test_mfspr , " mfspr", },
+ { &test_mtspr , " mtspr", },
+#ifdef __powerpc64__
+ { &test_rldcl , " rldcl", },
+ { &test_rldcr , " rldcr", },
+ { &test_rldic , " rldic", },
+ { &test_rldicl , " rldicl", },
+ { &test_rldicr , " rldicr", },
+ { &test_rldimi , " rldimi", },
+ { &test_sradi , " sradi", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+
+extern void test_rlwimi_ (void);
+ASSEMBLY_FUNC("test_rlwimi_", "rlwimi. 17, 14, 0, 0, 0");
+
+extern void test_rlwinm_ (void);
+ASSEMBLY_FUNC("test_rlwinm_", "rlwinm. 17, 14, 0, 0, 0");
+
+extern void test_rlwnm_ (void);
+ASSEMBLY_FUNC("test_rlwnm_", "rlwnm. 17, 14, 15, 0, 0");
+
+extern void test_srawi_ (void);
+ASSEMBLY_FUNC("test_srawi_", "srawi. 17, 14, 0");
+
+extern void test_mcrf (void);
+ASSEMBLY_FUNC("test_mcrf", "mcrf 0, 0");
+
+extern void test_mcrxr (void);
+ASSEMBLY_FUNC("test_mcrxr", "mcrxr 0");
+
+extern void test_mtcrf (void);
+ASSEMBLY_FUNC("test_mtcrf", "mtcrf 0, 14");
+
+#ifdef __powerpc64__
+extern void test_rldcl_ (void);
+ASSEMBLY_FUNC("test_rldcl_", "rldcl. 17, 14, 15, 0");
+
+extern void test_rldcr_ (void);
+ASSEMBLY_FUNC("test_rldcr_", "rldcr. 17, 14, 15, 0");
+
+extern void test_rldic_ (void);
+ASSEMBLY_FUNC("test_rldic_", "rldic. 17, 14, 0, 0");
+
+extern void test_rldicl_ (void);
+ASSEMBLY_FUNC("test_rldicl_", "rldicl. 17, 14, 0, 0");
+
+extern void test_rldicr_ (void);
+ASSEMBLY_FUNC("test_rldicr_", "rldicr. 17, 14, 0, 0");
+
+extern void test_rldimi_ (void);
+ASSEMBLY_FUNC("test_rldimi_", "rldimi. 17, 14, 0, 0");
+
+extern void test_sradi_ (void);
+ASSEMBLY_FUNC("test_sradi_", "sradi. 17, 14, 0");
+#endif // #ifdef __powerpc64__
+
+static test_t tests_ilr_ops_spe[] = {
+ { &test_rlwimi_ , " rlwimi.", },
+ { &test_rlwinm_ , " rlwinm.", },
+ { &test_rlwnm_ , " rlwnm.", },
+ { &test_srawi_ , " srawi.", },
+ { &test_mcrf , " mcrf", },
+ { &test_mcrxr , " mcrxr", },
+ { &test_mtcrf , " mtcrf", },
+#ifdef __powerpc64__
+ { &test_rldcl_ , " rldcl.", },
+ { &test_rldcr_ , " rldcr.", },
+ { &test_rldic_ , " rldic.", },
+ { &test_rldicl_ , " rldicl.", },
+ { &test_rldicr_ , " rldicr.", },
+ { &test_rldimi_ , " rldimi.", },
+ { &test_sradi_ , " sradi.", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+
+extern void test_lbz (void);
+ASSEMBLY_FUNC("test_lbz", "lbz 17,0(14)");
+
+extern void test_lbzu (void);
+ASSEMBLY_FUNC("test_lbzu", "lbzu 17,0(14)");
+
+extern void test_lha (void);
+ASSEMBLY_FUNC("test_lha", "lha 17,0(14)");
+
+extern void test_lhau (void);
+ASSEMBLY_FUNC("test_lhau", "lhau 17,0(14)");
+
+extern void test_lhz (void);
+ASSEMBLY_FUNC("test_lhz", "lhz 17,0(14)");
+
+extern void test_lhzu (void);
+ASSEMBLY_FUNC("test_lhzu", "lhzu 17,0(14)");
+
+extern void test_lwz (void);
+ASSEMBLY_FUNC("test_lwz", "lwz 17,0(14)");
+
+extern void test_lwzu (void);
+ASSEMBLY_FUNC("test_lwzu", "lwzu 17,0(14)");
+
+#ifdef __powerpc64__
+extern void test_ld (void);
+ASSEMBLY_FUNC("test_ld", "ld 17,0(14)");
+
+extern void test_ldu (void);
+ASSEMBLY_FUNC("test_ldu", "ldu 17,0(14)");
+
+extern void test_lwa (void);
+ASSEMBLY_FUNC("test_lwa", "lwa 17,0(14)");
+#endif // #ifdef __powerpc64__
+
+static test_t tests_ild_ops_two_i16[] = {
+ { &test_lbz , " lbz", },
+ { &test_lbzu , " lbzu", },
+ { &test_lha , " lha", },
+ { &test_lhau , " lhau", },
+ { &test_lhz , " lhz", },
+ { &test_lhzu , " lhzu", },
+ { &test_lwz , " lwz", },
+ { &test_lwzu , " lwzu", },
+#ifdef __powerpc64__
+ { &test_ld , " ld", },
+ { &test_ldu , " ldu", },
+ { &test_lwa , " lwa", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+
+static void test_lbzx (void)
+{
+ __asm__ __volatile__ ("lbzx 17,14,15");
+}
+
+static void test_lbzux (void)
+{
+ __asm__ __volatile__ ("lbzux 17,14,15");
+}
+
+static void test_lhax (void)
+{
+ __asm__ __volatile__ ("lhax 17,14,15");
+}
+
+static void test_lhaux (void)
+{
+ __asm__ __volatile__ ("lhaux 17,14,15");
+}
+
+static void test_lhzx (void)
+{
+ __asm__ __volatile__ ("lhzx 17,14,15");
+}
+
+static void test_lhzux (void)
+{
+ __asm__ __volatile__ ("lhzux 17,14,15");
+}
+
+static void test_lwzx (void)
+{
+ __asm__ __volatile__ ("lwzx 17,14,15");
+}
+
+static void test_lwzux (void)
+{
+ __asm__ __volatile__ ("lwzux 17,14,15");
+}
+
+#ifdef __powerpc64__
+static void test_ldx (void)
+{
+ __asm__ __volatile__ ("ldx 17,14,15");
+}
+
+static void test_ldux (void)
+{
+ __asm__ __volatile__ ("ldux 17,14,15");
+}
+
+static void test_lwax (void)
+{
+ __asm__ __volatile__ ("lwax 17,14,15");
+}
+
+static void test_lwaux (void)
+{
+ __asm__ __volatile__ ("lwaux 17,14,15");
+}
+#endif // #ifdef __powerpc64__
+
+static test_t tests_ild_ops_two[] = {
+ { &test_lbzx , " lbzx", },
+ { &test_lbzux , " lbzux", },
+ { &test_lhax , " lhax", },
+ { &test_lhaux , " lhaux", },
+ { &test_lhzx , " lhzx", },
+ { &test_lhzux , " lhzux", },
+ { &test_lwzx , " lwzx", },
+ { &test_lwzux , " lwzux", },
+#ifdef __powerpc64__
+ { &test_ldx , " ldx", },
+ { &test_ldux , " ldux", },
+ { &test_lwax , " lwax", },
+ { &test_lwaux , " lwaux", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+
+extern void test_stb (void);
+ASSEMBLY_FUNC("test_stb", "stb 14,0(15)");
+
+extern void test_stbu (void);
+ASSEMBLY_FUNC("test_stbu", "stbu 14,0(15)");
+
+extern void test_sth (void);
+ASSEMBLY_FUNC("test_sth", "sth 14,0(15)");
+
+extern void test_sthu (void);
+ASSEMBLY_FUNC("test_sthu", "sthu 14,0(15)");
+
+extern void test_stw (void);
+ASSEMBLY_FUNC("test_stw", "stw 14,0(15)");
+
+extern void test_stwu (void);
+ASSEMBLY_FUNC("test_stwu", "stwu 14,0(15)");
+
+#ifdef __powerpc64__
+extern void test_std (void);
+ASSEMBLY_FUNC("test_std", "std 14,0(15)");
+
+extern void test_stdu (void);
+ASSEMBLY_FUNC("test_stdu", "stdu 14,0(15)");
+#endif // #ifdef __powerpc64__
+
+static test_t tests_ist_ops_three_i16[] = {
+ { &test_stb , " stb", },
+ { &test_stbu , " stbu", },
+ { &test_sth , " sth", },
+ { &test_sthu , " sthu", },
+ { &test_stw , " stw", },
+ { &test_stwu , " stwu", },
+#ifdef __powerpc64__
+ { &test_std , " std", },
+ { &test_stdu , " stdu", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+
+static void test_stbx (void)
+{
+ __asm__ __volatile__ ("stbx 14,15,16");
+}
+
+static void test_stbux (void)
+{
+ __asm__ __volatile__ ("stbux 14,15,16");
+}
+
+static void test_sthx (void)
+{
+ __asm__ __volatile__ ("sthx 14,15,16");
+}
+
+static void test_sthux (void)
+{
+ __asm__ __volatile__ ("sthux 14,15,16");
+}
+
+static void test_stwx (void)
+{
+ __asm__ __volatile__ ("stwx 14,15,16");
+}
+
+static void test_stwux (void)
+{
+ __asm__ __volatile__ ("stwux 14,15,16");
+}
+
+#ifdef __powerpc64__
+static void test_stdx (void)
+{
+ __asm__ __volatile__ ("stdx 14,15,16");
+}
+
+static void test_stdux (void)
+{
+ __asm__ __volatile__ ("stdux 14,15,16");
+}
+#endif // #ifdef __powerpc64__
+
+static test_t tests_ist_ops_three[] = {
+ { &test_stbx , " stbx", },
+ { &test_stbux , " stbux", },
+ { &test_sthx , " sthx", },
+ { &test_sthux , " sthux", },
+ { &test_stwx , " stwx", },
+ { &test_stwux , " stwux", },
+#ifdef __powerpc64__
+ { &test_stdx , " stdx", },
+ { &test_stdux , " stdux", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+
+static void
+tests_popcnt_one(void)
+{
+ __asm__ __volatile__ ("popcntb 17, 14");
+}
+
+static test_t tests_popcnt_ops_one[] = {
+ { &tests_popcnt_one , " popcntb", },
+ { NULL, NULL, },
+};
+
+#if !defined (NO_FLOAT)
+static void test_fsel (void)
+{
+ __asm__ __volatile__ ("fsel 17, 14, 15, 16");
+}
+
+static void test_fmadd (void)
+{
+ __asm__ __volatile__ ("fmadd 17, 14, 15, 16");
+}
+
+static void test_fmadds (void)
+{
+ __asm__ __volatile__ ("fmadds 17, 14, 15, 16");
+}
+
+static void test_fmsub (void)
+{
+ __asm__ __volatile__ ("fmsub 17, 14, 15, 16");
+}
+
+static void test_fmsubs (void)
+{
+ __asm__ __volatile__ ("fmsubs 17, 14, 15, 16");
+}
+
+static void test_fnmadd (void)
+{
+ __asm__ __volatile__ ("fnmadd 17, 14, 15, 16");
+}
+
+static void test_fnmadds (void)
+{
+ __asm__ __volatile__ ("fnmadds 17, 14, 15, 16");
+}
+
+static void test_fnmsub (void)
+{
+ __asm__ __volatile__ ("fnmsub 17, 14, 15, 16");
+}
+
+static void test_fnmsubs (void)
+{
+ __asm__ __volatile__ ("fnmsubs 17, 14, 15, 16");
+}
+
+static test_t tests_fa_ops_three[] = {
+ { &test_fsel , " fsel", },
+ { &test_fmadd , " fmadd", },
+ { &test_fmadds , " fmadds", },
+ { &test_fmsub , " fmsub", },
+ { &test_fmsubs , " fmsubs", },
+ { &test_fnmadd , " fnmadd", },
+ { &test_fnmadds , " fnmadds", },
+ { &test_fnmsub , " fnmsub", },
+ { &test_fnmsubs , " fnmsubs", },
+ { NULL, NULL, },
+};
+#endif /* !defined (NO_FLOAT) */
+
+#if !defined (NO_FLOAT)
+static void test_fsel_ (void)
+{
+ __asm__ __volatile__ ("fsel. 17, 14, 15, 16");
+}
+
+static void test_fmadd_ (void)
+{
+ __asm__ __volatile__ ("fmadd. 17, 14, 15, 16");
+}
+
+static void test_fmadds_ (void)
+{
+ __asm__ __volatile__ ("fmadds. 17, 14, 15, 16");
+}
+
+static void test_fmsub_ (void)
+{
+ __asm__ __volatile__ ("fmsub. 17, 14, 15, 16");
+}
+
+static void test_fmsubs_ (void)
+{
+ __asm__ __volatile__ ("fmsubs. 17, 14, 15, 16");
+}
+
+static void test_fnmadd_ (void)
+{
+ __asm__ __volatile__ ("fnmadd. 17, 14, 15, 16");
+}
+
+static void test_fnmadds_ (void)
+{
+ __asm__ __volatile__ ("fnmadds. 17, 14, 15, 16");
+}
+
+static void test_fnmsub_ (void)
+{
+ __asm__ __volatile__ ("fnmsub. 17, 14, 15, 16");
+}
+
+static void test_fnmsubs_ (void)
+{
+ __asm__ __volatile__ ("fnmsubs. 17, 14, 15, 16");
+}
+
+static test_t tests_far_ops_three[] = {
+ { &test_fsel_ , " fsel.", },
+ { &test_fmadd_ , " fmadd.", },
+ { &test_fmadds_ , " fmadds.", },
+ { &test_fmsub_ , " fmsub.", },
+ { &test_fmsubs_ , " fmsubs.", },
+ { &test_fnmadd_ , " fnmadd.", },
+ { &test_fnmadds_ , " fnmadds.", },
+ { &test_fnmsub_ , " fnmsub.", },
+ { &test_fnmsubs_ , " fnmsubs.", },
+ { NULL, NULL, },
+};
+#endif /* !defined (NO_FLOAT) */
+
+#if !defined (NO_FLOAT)
+static void test_fadd (void)
+{
+ __asm__ __volatile__ ("fadd 17, 14, 15");
+}
+
+static void test_fadds (void)
+{
+ __asm__ __volatile__ ("fadds 17, 14, 15");
+}
+
+static void test_fsub (void)
+{
+ __asm__ __volatile__ ("fsub 17, 14, 15");
+}
+
+static void test_fsubs (void)
+{
+ __asm__ __volatile__ ("fsubs 17, 14, 15");
+}
+
+static void test_fmul (void)
+{
+ __asm__ __volatile__ ("fmul 17, 14, 15");
+}
+
+static void test_fmuls (void)
+{
+ __asm__ __volatile__ ("fmuls 17, 14, 15");
+}
+
+static void test_fdiv (void)
+{
+ __asm__ __volatile__ ("fdiv 17, 14, 15");
+}
+
+static void test_fdivs (void)
+{
+ __asm__ __volatile__ ("fdivs 17, 14, 15");
+}
+
+static test_t tests_fa_ops_two[] = {
+ { &test_fadd , " fadd", },
+ { &test_fadds , " fadds", },
+ { &test_fsub , " fsub", },
+ { &test_fsubs , " fsubs", },
+ { &test_fmul , " fmul", },
+ { &test_fmuls , " fmuls", },
+ { &test_fdiv , " fdiv", },
+ { &test_fdivs , " fdivs", },
+ { NULL, NULL, },
+};
+#endif /* !defined (NO_FLOAT) */
+
+#if !defined (NO_FLOAT)
+static void test_fadd_ (void)
+{
+ __asm__ __volatile__ ("fadd. 17, 14, 15");
+}
+
+static void test_fadds_ (void)
+{
+ __asm__ __volatile__ ("fadds. 17, 14, 15");
+}
+
+static void test_fsub_ (void)
+{
+ __asm__ __volatile__ ("fsub. 17, 14, 15");
+}
+
+static void test_fsubs_ (void)
+{
+ __asm__ __volatile__ ("fsubs. 17, 14, 15");
+}
+
+static void test_fmul_ (void)
+{
+ __asm__ __volatile__ ("fmul. 17, 14, 15");
+}
+
+static void test_fmuls_ (void)
+{
+ __asm__ __volatile__ ("fmuls. 17, 14, 15");
+}
+
+static void test_fdiv_ (void)
+{
+ __asm__ __volatile__ ("fdiv. 17, 14, 15");
+}
+
+static void test_fdivs_ (void)
+{
+ __asm__ __volatile__ ("fdivs. 17, 14, 15");
+}
+
+static test_t tests_far_ops_two[] = {
+ { &test_fadd_ , " fadd.", },
+ { &test_fadds_ , " fadds.", },
+ { &test_fsub_ , " fsub.", },
+ { &test_fsubs_ , " fsubs.", },
+ { &test_fmul_ , " fmul.", },
+ { &test_fmuls_ , " fmuls.", },
+ { &test_fdiv_ , " fdiv.", },
+ { &test_fdivs_ , " fdivs.", },
+ { NULL, NULL, },
+};
+#endif /* !defined (NO_FLOAT) */
+
+#if !defined (NO_FLOAT)
+static void test_fcmpo (void)
+{
+ __asm__ __volatile__ ("fcmpo 2, 14, 15");
+}
+
+static void test_fcmpu (void)
+{
+ __asm__ __volatile__ ("fcmpu 2, 14, 15");
+}
+
+static test_t tests_fcr_ops_two[] = {
+ { &test_fcmpo , " fcmpo", },
+ { &test_fcmpu , " fcmpu", },
+ { NULL, NULL, },
+};
+#endif /* !defined (NO_FLOAT) */
+
+#if !defined (NO_FLOAT)
+
+static void test_fres (void)
+{
+ __asm__ __volatile__ ("fres 17, 14");
+}
+
+static void test_frsqrte (void)
+{
+ __asm__ __volatile__ ("frsqrte 17, 14");
+}
+
+static void test_frsp (void)
+{
+ __asm__ __volatile__ ("frsp 17, 14");
+}
+
+static void test_fctiw (void)
+{
+ __asm__ __volatile__ ("fctiw 17, 14");
+}
+
+static void test_fctiwz (void)
+{
+ __asm__ __volatile__ ("fctiwz 17, 14");
+}
+
+static void test_fmr (void)
+{
+ __asm__ __volatile__ ("fmr 17, 14");
+}
+
+static void test_fneg (void)
+{
+ __asm__ __volatile__ ("fneg 17, 14");
+}
+
+static void test_fabs (void)
+{
+ __asm__ __volatile__ ("fabs 17, 14");
+}
+
+static void test_fnabs (void)
+{
+ __asm__ __volatile__ ("fnabs 17, 14");
+}
+
+static void test_fsqrt (void)
+{
+ __asm__ __volatile__ ("fsqrt 17, 14");
+}
+
+#ifdef __powerpc64__
+static void test_fcfid (void)
+{
+ __asm__ __volatile__ ("fcfid 17, 14");
+}
+
+static void test_fctid (void)
+{
+ __asm__ __volatile__ ("fctid 17, 14");
+}
+
+static void test_fctidz (void)
+{
+ __asm__ __volatile__ ("fctidz 17, 14");
+}
+#endif // #ifdef __powerpc64__
+
+static test_t tests_fa_ops_one[] = {
+ { &test_fres , " fres", },
+ { &test_frsqrte , " frsqrte", },
+ { &test_frsp , " frsp", },
+ { &test_fctiw , " fctiw", },
+ { &test_fctiwz , " fctiwz", },
+ { &test_fmr , " fmr", },
+ { &test_fneg , " fneg", },
+ { &test_fabs , " fabs", },
+ { &test_fnabs , " fnabs", },
+ { &test_fsqrt , " fsqrt", },
+#ifdef __powerpc64__
+ { &test_fcfid , " fcfid", },
+ { &test_fctid , " fctid", },
+ { &test_fctidz , " fctidz", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+#endif /* !defined (NO_FLOAT) */
+
+#if !defined (NO_FLOAT)
+
+static void test_fres_ (void)
+{
+ __asm__ __volatile__ ("fres. 17, 14");
+}
+
+static void test_frsqrte_ (void)
+{
+ __asm__ __volatile__ ("frsqrte. 17, 14");
+}
+
+static void test_frsp_ (void)
+{
+ __asm__ __volatile__ ("frsp. 17, 14");
+}
+
+static void test_fctiw_ (void)
+{
+ __asm__ __volatile__ ("fctiw. 17, 14");
+}
+
+static void test_fctiwz_ (void)
+{
+ __asm__ __volatile__ ("fctiwz. 17, 14");
+}
+
+static void test_fmr_ (void)
+{
+ __asm__ __volatile__ ("fmr. 17, 14");
+}
+
+static void test_fneg_ (void)
+{
+ __asm__ __volatile__ ("fneg. 17, 14");
+}
+
+static void test_fabs_ (void)
+{
+ __asm__ __volatile__ ("fabs. 17, 14");
+}
+
+static void test_fnabs_ (void)
+{
+ __asm__ __volatile__ ("fnabs. 17, 14");
+}
+
+#ifdef __powerpc64__
+static void test_fcfid_ (void)
+{
+ __asm__ __volatile__ ("fcfid. 17, 14");
+}
+
+static void test_fctid_ (void)
+{
+ __asm__ __volatile__ ("fctid. 17, 14");
+}
+
+static void test_fctidz_ (void)
+{
+ __asm__ __volatile__ ("fctidz. 17, 14");
+}
+#endif // #ifdef __powerpc64__
+
+static test_t tests_far_ops_one[] = {
+ { &test_fres_ , " fres.", },
+ { &test_frsqrte_ , " frsqrte.", },
+ { &test_frsp_ , " frsp.", },
+ { &test_fctiw_ , " fctiw.", },
+ { &test_fctiwz_ , " fctiwz.", },
+ { &test_fmr_ , " fmr.", },
+ { &test_fneg_ , " fneg.", },
+ { &test_fabs_ , " fabs.", },
+ { &test_fnabs_ , " fnabs.", },
+#ifdef __powerpc64__
+ { &test_fcfid_ , " fcfid.", },
+ { &test_fctid_ , " fctid.", },
+ { &test_fctidz_ , " fctidz.", },
+#endif // #ifdef __powerpc64__
+ { NULL, NULL, },
+};
+#endif /* !defined (NO_FLOAT) */
+
+#if !defined (NO_FLOAT)
+static test_t tests_fl_ops_spe[] = {
+ { NULL, NULL, },
+};
+#endif /* !defined (NO_FLOAT) */
+
+#if !defined (NO_FLOAT)
+static test_t tests_flr_ops_spe[] = {
+ { NULL, NULL, },
+};
+#endif /* !defined (NO_FLOAT) */
+
+
+#if !defined (NO_FLOAT)
+extern void test_lfs (void);
+ASSEMBLY_FUNC("test_lfs", "lfs 17,0(14)");
+
+extern void test_lfsu (void);
+ASSEMBLY_FUNC("test_lfsu", "lfsu 17,0(14)");
+
+extern void test_lfd (void);
+ASSEMBLY_FUNC("test_lfd", "lfd 17,0(14)");
+
+extern void test_lfdu (void);
+ASSEMBLY_FUNC("test_lfdu", "lfdu 17,0(14)");
+
+static test_t tests_fld_ops_two_i16[] = {
+ { &test_lfs , " lfs", },
+ { &test_lfsu , " lfsu", },
+ { &test_lfd , " lfd", },
+ { &test_lfdu , " lfdu", },
+ { NULL, NULL, },
+};
+#endif /* !defined (NO_FLOAT) */
+
+#if !defined (NO_FLOAT)
+static void test_lfsx (void)
+{
+ __asm__ __volatile__ ("lfsx 17,14,15");
+}
+
+static void test_lfsux (void)
+{
+ __asm__ __volatile__ ("lfsux 17,14,15");
+}
+
+static void test_lfdx (void)
+{
+ __asm__ __volatile__ ("lfdx 17,14,15");
+}
+
+static void test_lfdux (void)
+{
+ __asm__ __volatile__ ("lfdux 17,14,15");
+}
+
+static test_t tests_fld_ops_two[] = {
+ { &test_lfsx , " lfsx", },
+ { &test_lfsux , " lfsux", },
+ { &test_lfdx , " lfdx", },
+ { &test_lfdux , " lfdux", },
+ { NULL, NULL, },
+};
+#endif /* !defined (NO_FLOAT) */
+
+#if !defined (NO_FLOAT)
+extern void test_stfs (void);
+ASSEMBLY_FUNC("test_stfs", "stfs 14,0(15)");
+
+extern void test_stfsu (void);
+ASSEMBLY_FUNC("test_stfsu", "stfsu 14,0(15)");
+
+extern void test_stfd (void);
+ASSEMBLY_FUNC("test_stfd", "stfd 14,0(15)");
+
+extern void test_stfdu (void);
+ASSEMBLY_FUNC("test_stfdu", "stfdu 14,0(15)");
+
+static test_t tests_fst_ops_three_i16[] = {
+ { &test_stfs , " stfs", },
+ { &test_stfsu , " stfsu", },
+ { &test_stfd , " stfd", },
+ { &test_stfdu , " stfdu", },
+ { NULL, NULL, },
+};
+#endif /* !defined (NO_FLOAT) */
+
+#if !defined (NO_FLOAT)
+static void test_stfsx (void)
+{
+ __asm__ __volatile__ ("stfsx 14,15,16");
+}
+
+static void test_stfsux (void)
+{
+ __asm__ __volatile__ ("stfsux 14,15,16");
+}
+
+static void test_stfdx (void)
+{
+ __asm__ __volatile__ ("stfdx 14,15,16");
+}
+
+static void test_stfdux (void)
+{
+ __asm__ __volatile__ ("stfdux 14,15,16");
+}
+
+static test_t tests_fst_ops_three[] = {
+ { &test_stfsx , " stfsx", },
+ { &test_stfsux , " stfsux", },
+ { &test_stfdx , " stfdx", },
+ { &test_stfdux , " stfdux", },
+ { NULL, NULL, },
+};
+#endif /* !defined (NO_FLOAT) */
+
+
+#if defined (HAS_ALTIVEC)
+static void test_vmhaddshs (void)
+{
+ __asm__ __volatile__ ("vmhaddshs 17, 14, 15, 16");
+}
+
+static void test_vmhraddshs (void)
+{
+ __asm__ __volatile__ ("vmhraddshs 17, 14, 15, 16");
+}
+
+static void test_vmladduhm (void)
+{
+ __asm__ __volatile__ ("vmladduhm 17, 14, 15, 16");
+}
+
+static void test_vmsumubm (void)
+{
+ __asm__ __volatile__ ("vmsumubm 17, 14, 15, 16");
+}
+
+static void test_vmsumuhm (void)
+{
+ __asm__ __volatile__ ("vmsumuhm 17, 14, 15, 16");
+}
+
+static void test_vmsumshs (void)
+{
+ __asm__ __volatile__ ("vmsumshs 17, 14, 15, 16");
+}
+
+static void test_vmsumuhs (void)
+{
+ __asm__ __volatile__ ("vmsumuhs 17, 14, 15, 16");
+}
+
+static void test_vmsummbm (void)
+{
+ __asm__ __volatile__ ("vmsummbm 17, 14, 15, 16");
+}
+
+static void test_vmsumshm (void)
+{
+ __asm__ __volatile__ ("vmsumshm 17, 14, 15, 16");
+}
+
+static test_t tests_aa_ops_three[] = {
+ { &test_vmhaddshs , " vmhaddshs", },
+ { &test_vmhraddshs , " vmhraddshs", },
+ { &test_vmladduhm , " vmladduhm", },
+ { &test_vmsumubm , " vmsumubm", },
+ { &test_vmsumuhm , " vmsumuhm", },
+ { &test_vmsumshs , " vmsumshs", },
+ { &test_vmsumuhs , " vmsumuhs", },
+ { &test_vmsummbm , " vmsummbm", },
+ { &test_vmsumshm , " vmsumshm", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+static void test_vperm (void)
+{
+ __asm__ __volatile__ ("vperm 17, 14, 15, 16");
+}
+
+static void test_vsel (void)
+{
+ __asm__ __volatile__ ("vsel 17, 14, 15, 16");
+}
+
+static test_t tests_al_ops_three[] = {
+ { &test_vperm , " vperm", },
+ { &test_vsel , " vsel", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+static void test_vaddubm (void)
+{
+ __asm__ __volatile__ ("vaddubm 17, 14, 15");
+}
+
+static void test_vadduhm (void)
+{
+ __asm__ __volatile__ ("vadduhm 17, 14, 15");
+}
+
+static void test_vadduwm (void)
+{
+ __asm__ __volatile__ ("vadduwm 17, 14, 15");
+}
+
+static void test_vaddubs (void)
+{
+ __asm__ __volatile__ ("vaddubs 17, 14, 15");
+}
+
+static void test_vadduhs (void)
+{
+ __asm__ __volatile__ ("vadduhs 17, 14, 15");
+}
+
+static void test_vadduws (void)
+{
+ __asm__ __volatile__ ("vadduws 17, 14, 15");
+}
+
+static void test_vaddsbs (void)
+{
+ __asm__ __volatile__ ("vaddsbs 17, 14, 15");
+}
+
+static void test_vaddshs (void)
+{
+ __asm__ __volatile__ ("vaddshs 17, 14, 15");
+}
+
+static void test_vaddsws (void)
+{
+ __asm__ __volatile__ ("vaddsws 17, 14, 15");
+}
+
+static void test_vaddcuw (void)
+{
+ __asm__ __volatile__ ("vaddcuw 17, 14, 15");
+}
+
+static void test_vsububm (void)
+{
+ __asm__ __volatile__ ("vsububm 17, 14, 15");
+}
+
+static void test_vsubuhm (void)
+{
+ __asm__ __volatile__ ("vsubuhm 17, 14, 15");
+}
+
+static void test_vsubuwm (void)
+{
+ __asm__ __volatile__ ("vsubuwm 17, 14, 15");
+}
+
+static void test_vsububs (void)
+{
+ __asm__ __volatile__ ("vsububs 17, 14, 15");
+}
+
+static void test_vsubuhs (void)
+{
+ __asm__ __volatile__ ("vsubuhs 17, 14, 15");
+}
+
+static void test_vsubuws (void)
+{
+ __asm__ __volatile__ ("vsubuws 17, 14, 15");
+}
+
+static void test_vsubsbs (void)
+{
+ __asm__ __volatile__ ("vsubsbs 17, 14, 15");
+}
+
+static void test_vsubshs (void)
+{
+ __asm__ __volatile__ ("vsubshs 17, 14, 15");
+}
+
+static void test_vsubsws (void)
+{
+ __asm__ __volatile__ ("vsubsws 17, 14, 15");
+}
+
+static void test_vsubcuw (void)
+{
+ __asm__ __volatile__ ("vsubcuw 17, 14, 15");
+}
+
+static void test_vmuloub (void)
+{
+ __asm__ __volatile__ ("vmuloub 17, 14, 15");
+}
+
+static void test_vmulouh (void)
+{
+ __asm__ __volatile__ ("vmulouh 17, 14, 15");
+}
+
+static void test_vmulosb (void)
+{
+ __asm__ __volatile__ ("vmulosb 17, 14, 15");
+}
+
+static void test_vmulosh (void)
+{
+ __asm__ __volatile__ ("vmulosh 17, 14, 15");
+}
+
+static void test_vmuleub (void)
+{
+ __asm__ __volatile__ ("vmuleub 17, 14, 15");
+}
+
+static void test_vmuleuh (void)
+{
+ __asm__ __volatile__ ("vmuleuh 17, 14, 15");
+}
+
+static void test_vmulesb (void)
+{
+ __asm__ __volatile__ ("vmulesb 17, 14, 15");
+}
+
+static void test_vmulesh (void)
+{
+ __asm__ __volatile__ ("vmulesh 17, 14, 15");
+}
+
+static void test_vsumsws (void)
+{
+ __asm__ __volatile__ ("vsumsws 17, 14, 15");
+}
+
+static void test_vsum2sws (void)
+{
+ __asm__ __volatile__ ("vsum2sws 17, 14, 15");
+}
+
+static void test_vsum4ubs (void)
+{
+ __asm__ __volatile__ ("vsum4ubs 17, 14, 15");
+}
+
+static void test_vsum4sbs (void)
+{
+ __asm__ __volatile__ ("vsum4sbs 17, 14, 15");
+}
+
+static void test_vsum4shs (void)
+{
+ __asm__ __volatile__ ("vsum4shs 17, 14, 15");
+}
+
+static void test_vavgub (void)
+{
+ __asm__ __volatile__ ("vavgub 17, 14, 15");
+}
+
+static void test_vavguh (void)
+{
+ __asm__ __volatile__ ("vavguh 17, 14, 15");
+}
+
+static void test_vavguw (void)
+{
+ __asm__ __volatile__ ("vavguw 17, 14, 15");
+}
+
+static void test_vavgsb (void)
+{
+ __asm__ __volatile__ ("vavgsb 17, 14, 15");
+}
+
+static void test_vavgsh (void)
+{
+ __asm__ __volatile__ ("vavgsh 17, 14, 15");
+}
+
+static void test_vavgsw (void)
+{
+ __asm__ __volatile__ ("vavgsw 17, 14, 15");
+}
+
+static void test_vmaxub (void)
+{
+ __asm__ __volatile__ ("vmaxub 17, 14, 15");
+}
+
+static void test_vmaxuh (void)
+{
+ __asm__ __volatile__ ("vmaxuh 17, 14, 15");
+}
+
+static void test_vmaxuw (void)
+{
+ __asm__ __volatile__ ("vmaxuw 17, 14, 15");
+}
+
+static void test_vmaxsb (void)
+{
+ __asm__ __volatile__ ("vmaxsb 17, 14, 15");
+}
+
+static void test_vmaxsh (void)
+{
+ __asm__ __volatile__ ("vmaxsh 17, 14, 15");
+}
+
+static void test_vmaxsw (void)
+{
+ __asm__ __volatile__ ("vmaxsw 17, 14, 15");
+}
+
+static void test_vminub (void)
+{
+ __asm__ __volatile__ ("vminub 17, 14, 15");
+}
+
+static void test_vminuh (void)
+{
+ __asm__ __volatile__ ("vminuh 17, 14, 15");
+}
+
+static void test_vminuw (void)
+{
+ __asm__ __volatile__ ("vminuw 17, 14, 15");
+}
+
+static void test_vminsb (void)
+{
+ __asm__ __volatile__ ("vminsb 17, 14, 15");
+}
+
+static void test_vminsh (void)
+{
+ __asm__ __volatile__ ("vminsh 17, 14, 15");
+}
+
+static void test_vminsw (void)
+{
+ __asm__ __volatile__ ("vminsw 17, 14, 15");
+}
+
+static test_t tests_aa_ops_two[] = {
+ { &test_vaddubm , " vaddubm", },
+ { &test_vadduhm , " vadduhm", },
+ { &test_vadduwm , " vadduwm", },
+ { &test_vaddubs , " vaddubs", },
+ { &test_vadduhs , " vadduhs", },
+ { &test_vadduws , " vadduws", },
+ { &test_vaddsbs , " vaddsbs", },
+ { &test_vaddshs , " vaddshs", },
+ { &test_vaddsws , " vaddsws", },
+ { &test_vaddcuw , " vaddcuw", },
+ { &test_vsububm , " vsububm", },
+ { &test_vsubuhm , " vsubuhm", },
+ { &test_vsubuwm , " vsubuwm", },
+ { &test_vsububs , " vsububs", },
+ { &test_vsubuhs , " vsubuhs", },
+ { &test_vsubuws , " vsubuws", },
+ { &test_vsubsbs , " vsubsbs", },
+ { &test_vsubshs , " vsubshs", },
+ { &test_vsubsws , " vsubsws", },
+ { &test_vsubcuw , " vsubcuw", },
+ { &test_vmuloub , " vmuloub", },
+ { &test_vmulouh , " vmulouh", },
+ { &test_vmulosb , " vmulosb", },
+ { &test_vmulosh , " vmulosh", },
+ { &test_vmuleub , " vmuleub", },
+ { &test_vmuleuh , " vmuleuh", },
+ { &test_vmulesb , " vmulesb", },
+ { &test_vmulesh , " vmulesh", },
+ { &test_vsumsws , " vsumsws", },
+ { &test_vsum2sws , " vsum2sws", },
+ { &test_vsum4ubs , " vsum4ubs", },
+ { &test_vsum4sbs , " vsum4sbs", },
+ { &test_vsum4shs , " vsum4shs", },
+ { &test_vavgub , " vavgub", },
+ { &test_vavguh , " vavguh", },
+ { &test_vavguw , " vavguw", },
+ { &test_vavgsb , " vavgsb", },
+ { &test_vavgsh , " vavgsh", },
+ { &test_vavgsw , " vavgsw", },
+ { &test_vmaxub , " vmaxub", },
+ { &test_vmaxuh , " vmaxuh", },
+ { &test_vmaxuw , " vmaxuw", },
+ { &test_vmaxsb , " vmaxsb", },
+ { &test_vmaxsh , " vmaxsh", },
+ { &test_vmaxsw , " vmaxsw", },
+ { &test_vminub , " vminub", },
+ { &test_vminuh , " vminuh", },
+ { &test_vminuw , " vminuw", },
+ { &test_vminsb , " vminsb", },
+ { &test_vminsh , " vminsh", },
+ { &test_vminsw , " vminsw", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+static void test_vand (void)
+{
+ __asm__ __volatile__ ("vand 17, 14, 15");
+}
+
+static void test_vor (void)
+{
+ __asm__ __volatile__ ("vor 17, 14, 15");
+}
+
+static void test_vxor (void)
+{
+ __asm__ __volatile__ ("vxor 17, 14, 15");
+}
+
+static void test_vandc (void)
+{
+ __asm__ __volatile__ ("vandc 17, 14, 15");
+}
+
+static void test_vnor (void)
+{
+ __asm__ __volatile__ ("vnor 17, 14, 15");
+}
+
+static void test_vrlb (void)
+{
+ __asm__ __volatile__ ("vrlb 17, 14, 15");
+}
+
+static void test_vrlh (void)
+{
+ __asm__ __volatile__ ("vrlh 17, 14, 15");
+}
+
+static void test_vrlw (void)
+{
+ __asm__ __volatile__ ("vrlw 17, 14, 15");
+}
+
+static void test_vslb (void)
+{
+ __asm__ __volatile__ ("vslb 17, 14, 15");
+}
+
+static void test_vslh (void)
+{
+ __asm__ __volatile__ ("vslh 17, 14, 15");
+}
+
+static void test_vslw (void)
+{
+ __asm__ __volatile__ ("vslw 17, 14, 15");
+}
+
+static void test_vsrb (void)
+{
+ __asm__ __volatile__ ("vsrb 17, 14, 15");
+}
+
+static void test_vsrh (void)
+{
+ __asm__ __volatile__ ("vsrh 17, 14, 15");
+}
+
+static void test_vsrw (void)
+{
+ __asm__ __volatile__ ("vsrw 17, 14, 15");
+}
+
+static void test_vsrab (void)
+{
+ __asm__ __volatile__ ("vsrab 17, 14, 15");
+}
+
+static void test_vsrah (void)
+{
+ __asm__ __volatile__ ("vsrah 17, 14, 15");
+}
+
+static void test_vsraw (void)
+{
+ __asm__ __volatile__ ("vsraw 17, 14, 15");
+}
+
+static void test_vpkuhum (void)
+{
+ __asm__ __volatile__ ("vpkuhum 17, 14, 15");
+}
+
+static void test_vpkuwum (void)
+{
+ __asm__ __volatile__ ("vpkuwum 17, 14, 15");
+}
+
+static void test_vpkuhus (void)
+{
+ __asm__ __volatile__ ("vpkuhus 17, 14, 15");
+}
+
+static void test_vpkuwus (void)
+{
+ __asm__ __volatile__ ("vpkuwus 17, 14, 15");
+}
+
+static void test_vpkshus (void)
+{
+ __asm__ __volatile__ ("vpkshus 17, 14, 15");
+}
+
+static void test_vpkswus (void)
+{
+ __asm__ __volatile__ ("vpkswus 17, 14, 15");
+}
+
+static void test_vpkshss (void)
+{
+ __asm__ __volatile__ ("vpkshss 17, 14, 15");
+}
+
+static void test_vpkswss (void)
+{
+ __asm__ __volatile__ ("vpkswss 17, 14, 15");
+}
+
+static void test_vpkpx (void)
+{
+ __asm__ __volatile__ ("vpkpx 17, 14, 15");
+}
+
+static void test_vmrghb (void)
+{
+ __asm__ __volatile__ ("vmrghb 17, 14, 15");
+}
+
+static void test_vmrghh (void)
+{
+ __asm__ __volatile__ ("vmrghh 17, 14, 15");
+}
+
+static void test_vmrghw (void)
+{
+ __asm__ __volatile__ ("vmrghw 17, 14, 15");
+}
+
+static void test_vmrglb (void)
+{
+ __asm__ __volatile__ ("vmrglb 17, 14, 15");
+}
+
+static void test_vmrglh (void)
+{
+ __asm__ __volatile__ ("vmrglh 17, 14, 15");
+}
+
+static void test_vmrglw (void)
+{
+ __asm__ __volatile__ ("vmrglw 17, 14, 15");
+}
+
+static void test_vslo (void)
+{
+ __asm__ __volatile__ ("vslo 17, 14, 15");
+}
+
+static void test_vsro (void)
+{
+ __asm__ __volatile__ ("vsro 17, 14, 15");
+}
+
+static test_t tests_al_ops_two[] = {
+ { &test_vand , " vand", },
+ { &test_vor , " vor", },
+ { &test_vxor , " vxor", },
+ { &test_vandc , " vandc", },
+ { &test_vnor , " vnor", },
+ { &test_vrlb , " vrlb", },
+ { &test_vrlh , " vrlh", },
+ { &test_vrlw , " vrlw", },
+ { &test_vslb , " vslb", },
+ { &test_vslh , " vslh", },
+ { &test_vslw , " vslw", },
+ { &test_vsrb , " vsrb", },
+ { &test_vsrh , " vsrh", },
+ { &test_vsrw , " vsrw", },
+ { &test_vsrab , " vsrab", },
+ { &test_vsrah , " vsrah", },
+ { &test_vsraw , " vsraw", },
+ { &test_vpkuhum , " vpkuhum", },
+ { &test_vpkuwum , " vpkuwum", },
+ { &test_vpkuhus , " vpkuhus", },
+ { &test_vpkuwus , " vpkuwus", },
+ { &test_vpkshus , " vpkshus", },
+ { &test_vpkswus , " vpkswus", },
+ { &test_vpkshss , " vpkshss", },
+ { &test_vpkswss , " vpkswss", },
+ { &test_vpkpx , " vpkpx", },
+ { &test_vmrghb , " vmrghb", },
+ { &test_vmrghh , " vmrghh", },
+ { &test_vmrghw , " vmrghw", },
+ { &test_vmrglb , " vmrglb", },
+ { &test_vmrglh , " vmrglh", },
+ { &test_vmrglw , " vmrglw", },
+ { &test_vslo , " vslo", },
+ { &test_vsro , " vsro", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+static void test_vupkhsb (void)
+{
+ __asm__ __volatile__ ("vupkhsb 17, 14");
+}
+
+static void test_vupkhsh (void)
+{
+ __asm__ __volatile__ ("vupkhsh 17, 14");
+}
+
+static void test_vupkhpx (void)
+{
+ __asm__ __volatile__ ("vupkhpx 17, 14");
+}
+
+static void test_vupklsb (void)
+{
+ __asm__ __volatile__ ("vupklsb 17, 14");
+}
+
+static void test_vupklsh (void)
+{
+ __asm__ __volatile__ ("vupklsh 17, 14");
+}
+
+static void test_vupklpx (void)
+{
+ __asm__ __volatile__ ("vupklpx 17, 14");
+}
+
+static test_t tests_al_ops_one[] = {
+ { &test_vupkhsb , " vupkhsb", },
+ { &test_vupkhsh , " vupkhsh", },
+ { &test_vupkhpx , " vupkhpx", },
+ { &test_vupklsb , " vupklsb", },
+ { &test_vupklsh , " vupklsh", },
+ { &test_vupklpx , " vupklpx", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+static void test_vcmpgtub (void)
+{
+ __asm__ __volatile__ ("vcmpgtub 17, 14, 15");
+}
+
+static void test_vcmpgtuh (void)
+{
+ __asm__ __volatile__ ("vcmpgtuh 17, 14, 15");
+}
+
+static void test_vcmpgtuw (void)
+{
+ __asm__ __volatile__ ("vcmpgtuw 17, 14, 15");
+}
+
+static void test_vcmpgtsb (void)
+{
+ __asm__ __volatile__ ("vcmpgtsb 17, 14, 15");
+}
+
+static void test_vcmpgtsh (void)
+{
+ __asm__ __volatile__ ("vcmpgtsh 17, 14, 15");
+}
+
+static void test_vcmpgtsw (void)
+{
+ __asm__ __volatile__ ("vcmpgtsw 17, 14, 15");
+}
+
+static void test_vcmpequb (void)
+{
+ __asm__ __volatile__ ("vcmpequb 17, 14, 15");
+}
+
+static void test_vcmpequh (void)
+{
+ __asm__ __volatile__ ("vcmpequh 17, 14, 15");
+}
+
+static void test_vcmpequw (void)
+{
+ __asm__ __volatile__ ("vcmpequw 17, 14, 15");
+}
+
+static test_t tests_ac_ops_two[] = {
+ { &test_vcmpgtub , " vcmpgtub", },
+ { &test_vcmpgtuh , " vcmpgtuh", },
+ { &test_vcmpgtuw , " vcmpgtuw", },
+ { &test_vcmpgtsb , " vcmpgtsb", },
+ { &test_vcmpgtsh , " vcmpgtsh", },
+ { &test_vcmpgtsw , " vcmpgtsw", },
+ { &test_vcmpequb , " vcmpequb", },
+ { &test_vcmpequh , " vcmpequh", },
+ { &test_vcmpequw , " vcmpequw", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+static void test_vcmpgtub_ (void)
+{
+ __asm__ __volatile__ ("vcmpgtub. 17, 14, 15");
+}
+
+static void test_vcmpgtuh_ (void)
+{
+ __asm__ __volatile__ ("vcmpgtuh. 17, 14, 15");
+}
+
+static void test_vcmpgtuw_ (void)
+{
+ __asm__ __volatile__ ("vcmpgtuw. 17, 14, 15");
+}
+
+static void test_vcmpgtsb_ (void)
+{
+ __asm__ __volatile__ ("vcmpgtsb. 17, 14, 15");
+}
+
+static void test_vcmpgtsh_ (void)
+{
+ __asm__ __volatile__ ("vcmpgtsh. 17, 14, 15");
+}
+
+static void test_vcmpgtsw_ (void)
+{
+ __asm__ __volatile__ ("vcmpgtsw. 17, 14, 15");
+}
+
+static void test_vcmpequb_ (void)
+{
+ __asm__ __volatile__ ("vcmpequb. 17, 14, 15");
+}
+
+static void test_vcmpequh_ (void)
+{
+ __asm__ __volatile__ ("vcmpequh. 17, 14, 15");
+}
+
+static void test_vcmpequw_ (void)
+{
+ __asm__ __volatile__ ("vcmpequw. 17, 14, 15");
+}
+
+static test_t tests_acr_ops_two[] = {
+ { &test_vcmpgtub_ , " vcmpgtub.", },
+ { &test_vcmpgtuh_ , " vcmpgtuh.", },
+ { &test_vcmpgtuw_ , " vcmpgtuw.", },
+ { &test_vcmpgtsb_ , " vcmpgtsb.", },
+ { &test_vcmpgtsh_ , " vcmpgtsh.", },
+ { &test_vcmpgtsw_ , " vcmpgtsw.", },
+ { &test_vcmpequb_ , " vcmpequb.", },
+ { &test_vcmpequh_ , " vcmpequh.", },
+ { &test_vcmpequw_ , " vcmpequw.", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+static void test_vsl (void)
+{
+ __asm__ __volatile__ ("vsl 17, 14, 15");
+}
+
+static void test_vsr (void)
+{
+ __asm__ __volatile__ ("vsr 17, 14, 15");
+}
+
+extern void test_vspltb (void);
+ASSEMBLY_FUNC("test_vspltb", "vspltb 17, 14, 0");
+
+extern void test_vsplth (void);
+ASSEMBLY_FUNC("test_vsplth", "vsplth 17, 14, 0");
+
+extern void test_vspltw (void);
+ASSEMBLY_FUNC("test_vspltw", "vspltw 17, 14, 0");
+
+extern void test_vspltisb (void);
+ASSEMBLY_FUNC("test_vspltisb", "vspltisb 17, 0");
+
+extern void test_vspltish (void);
+ASSEMBLY_FUNC("test_vspltish", "vspltish 17, 0");
+
+extern void test_vspltisw (void);
+ASSEMBLY_FUNC("test_vspltisw", "vspltisw 17, 0");
+
+extern void test_vsldoi (void);
+ASSEMBLY_FUNC("test_vsldoi", "vsldoi 17, 14, 15, 0");
+
+static void test_lvsl (void)
+{
+ __asm__ __volatile__ ("lvsl 17, 14, 15");
+}
+
+static void test_lvsr (void)
+{
+ __asm__ __volatile__ ("lvsr 17, 14, 15");
+}
+
+static test_t tests_av_int_ops_spe[] = {
+ { &test_vsl , " vsl", },
+ { &test_vsr , " vsr", },
+ { &test_vspltb , " vspltb", },
+ { &test_vsplth , " vsplth", },
+ { &test_vspltw , " vspltw", },
+ { &test_vspltisb , " vspltisb", },
+ { &test_vspltish , " vspltish", },
+ { &test_vspltisw , " vspltisw", },
+ { &test_vsldoi , " vsldoi", },
+ { &test_lvsl , " lvsl", },
+ { &test_lvsr , " lvsr", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+static void test_lvebx (void)
+{
+ __asm__ __volatile__ ("lvebx 17,14,15");
+}
+
+static void test_lvehx (void)
+{
+ __asm__ __volatile__ ("lvehx 17,14,15");
+}
+
+static void test_lvewx (void)
+{
+ __asm__ __volatile__ ("lvewx 17,14,15");
+}
+
+static void test_lvx (void)
+{
+ __asm__ __volatile__ ("lvx 17,14,15");
+}
+
+static void test_lvxl (void)
+{
+ __asm__ __volatile__ ("lvxl 17,14,15");
+}
+
+static test_t tests_ald_ops_two[] = {
+ { &test_lvebx , " lvebx", },
+ { &test_lvehx , " lvehx", },
+ { &test_lvewx , " lvewx", },
+ { &test_lvx , " lvx", },
+ { &test_lvxl , " lvxl", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+static void test_stvebx (void)
+{
+ __asm__ __volatile__ ("stvebx 14,15,16");
+}
+
+static void test_stvehx (void)
+{
+ __asm__ __volatile__ ("stvehx 14,15,16");
+}
+
+static void test_stvewx (void)
+{
+ __asm__ __volatile__ ("stvewx 14,15,16");
+}
+
+static void test_stvx (void)
+{
+ __asm__ __volatile__ ("stvx 14,15,16");
+}
+
+static void test_stvxl (void)
+{
+ __asm__ __volatile__ ("stvxl 14,15,16");
+}
+
+static test_t tests_ast_ops_three[] = {
+ { &test_stvebx , " stvebx", },
+ { &test_stvehx , " stvehx", },
+ { &test_stvewx , " stvewx", },
+ { &test_stvx , " stvx", },
+ { &test_stvxl , " stvxl", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+#if 1
+static void test_vmaddfp (void)
+{
+ __asm__ __volatile__ ("vmaddfp 17, 14, 15, 16");
+}
+
+static void test_vnmsubfp (void)
+{
+ __asm__ __volatile__ ("vnmsubfp 17, 14, 15, 16");
+}
+#endif
+
+static test_t tests_afa_ops_three[] = {
+ { &test_vmaddfp , " vmaddfp", },
+ { &test_vnmsubfp , " vnmsubfp", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+static void test_vaddfp (void)
+{
+ __asm__ __volatile__ ("vaddfp 17, 14, 15");
+}
+
+static void test_vsubfp (void)
+{
+ __asm__ __volatile__ ("vsubfp 17, 14, 15");
+}
+
+static void test_vmaxfp (void)
+{
+ __asm__ __volatile__ ("vmaxfp 17, 14, 15");
+}
+
+static void test_vminfp (void)
+{
+ __asm__ __volatile__ ("vminfp 17, 14, 15");
+}
+
+static test_t tests_afa_ops_two[] = {
+ { &test_vaddfp , " vaddfp", },
+ { &test_vsubfp , " vsubfp", },
+ { &test_vmaxfp , " vmaxfp", },
+ { &test_vminfp , " vminfp", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+static void test_vrfin (void)
+{
+ __asm__ __volatile__ ("vrfin 17, 14");
+}
+
+static void test_vrfiz (void)
+{
+ __asm__ __volatile__ ("vrfiz 17, 14");
+}
+
+static void test_vrfip (void)
+{
+ __asm__ __volatile__ ("vrfip 17, 14");
+}
+
+static void test_vrfim (void)
+{
+ __asm__ __volatile__ ("vrfim 17, 14");
+}
+
+static void test_vrefp (void)
+{
+ __asm__ __volatile__ ("vrefp 17, 14");
+}
+
+static void test_vrsqrtefp (void)
+{
+ __asm__ __volatile__ ("vrsqrtefp 17, 14");
+}
+
+#if 0 // TODO: Not yet supported
+static void test_vlogefp (void)
+{
+ __asm__ __volatile__ ("vlogefp 17, 14");
+}
+
+static void test_vexptefp (void)
+{
+ __asm__ __volatile__ ("vexptefp 17, 14");
+}
+#endif
+
+static test_t tests_afa_ops_one[] = {
+ { &test_vrfin , " vrfin", },
+ { &test_vrfiz , " vrfiz", },
+ { &test_vrfip , " vrfip", },
+ { &test_vrfim , " vrfim", },
+ { &test_vrefp , " vrefp", },
+ { &test_vrsqrtefp , " vrsqrtefp", },
+ // { &test_vlogefp , " vlogefp", }, // TODO: Not yet supported
+ // { &test_vexptefp , " vexptefp", }, // TODO: Not yet supported
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+static void test_vcmpgtfp (void)
+{
+ __asm__ __volatile__ ("vcmpgtfp 17, 14, 15");
+}
+
+static void test_vcmpeqfp (void)
+{
+ __asm__ __volatile__ ("vcmpeqfp 17, 14, 15");
+}
+
+static void test_vcmpgefp (void)
+{
+ __asm__ __volatile__ ("vcmpgefp 17, 14, 15");
+}
+
+static void test_vcmpbfp (void)
+{
+ __asm__ __volatile__ ("vcmpbfp 17, 14, 15");
+}
+
+static test_t tests_afc_ops_two[] = {
+ { &test_vcmpgtfp , " vcmpgtfp", },
+ { &test_vcmpeqfp , " vcmpeqfp", },
+ { &test_vcmpgefp , " vcmpgefp", },
+ { &test_vcmpbfp , " vcmpbfp", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+static void test_vcmpgtfp_ (void)
+{
+ __asm__ __volatile__ ("vcmpgtfp. 17, 14, 15");
+}
+
+static void test_vcmpeqfp_ (void)
+{
+ __asm__ __volatile__ ("vcmpeqfp. 17, 14, 15");
+}
+
+static void test_vcmpgefp_ (void)
+{
+ __asm__ __volatile__ ("vcmpgefp. 17, 14, 15");
+}
+
+static void test_vcmpbfp_ (void)
+{
+ __asm__ __volatile__ ("vcmpbfp. 17, 14, 15");
+}
+
+static test_t tests_afcr_ops_two[] = {
+ { &test_vcmpgtfp_ , " vcmpgtfp.", },
+ { &test_vcmpeqfp_ , " vcmpeqfp.", },
+ { &test_vcmpgefp_ , " vcmpgefp.", },
+ { &test_vcmpbfp_ , " vcmpbfp.", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+#if defined (HAS_ALTIVEC)
+extern void test_vcfux (void);
+ASSEMBLY_FUNC("test_vcfux", "vcfux 17, 14, 0");
+
+extern void test_vcfsx (void);
+ASSEMBLY_FUNC("test_vcfsx", "vcfsx 17, 14, 0");
+
+extern void test_vctuxs (void);
+ASSEMBLY_FUNC("test_vctuxs", "vctuxs 17, 14, 0");
+
+extern void test_vctsxs (void);
+ASSEMBLY_FUNC("test_vctsxs", "vctsxs 17, 14, 0");
+
+static test_t tests_av_float_ops_spe[] = {
+ { &test_vcfux , " vcfux", },
+ { &test_vcfsx , " vcfsx", },
+ { &test_vctuxs , " vctuxs", },
+ { &test_vctsxs , " vctsxs", },
+ { NULL, NULL, },
+};
+#endif /* defined (HAS_ALTIVEC) */
+
+/* Power ISA 2.03 support dcbtct and dcbtstct with valid hint values b00000 - 0b00111.
+ * The ISA 2.06 added support for more valid hint values, but rather than tie ourselves
+ * in knots trying to test all permuations of ISAs and valid hint values, we'll just
+ * verify some of the base hint values from ISA 2.03.
+ *
+ * In a similar vein, in ISA 2.03, dcbtds had valid values of 0b01000 - 0b01010, whereas
+ * ISA 2.06 expanded the range of valid hint values to 0b01000 - 0b01111. We just test
+ * one of the ISA 2.03-supported values for dcbtds.
+ */
+static void test_dcbtct (void)
+{
+ /* dcbt RA, RB, TH */
+ ASM_DCBT(17, 14, 1);
+ ASM_DCBT(17, 14, 7);
+}
+
+static void test_dcbtds (void)
+{
+ /* dcbt RA, RB, TH */
+ ASM_DCBT(17, 14, 10);
+ ASM_DCBT(17, 14, 0);
+ ASM_DCBT(17, 14, 16);
+}
+
+static void test_dcbtst (void)
+{
+ /* dcbtst RA, RB, TH */
+ ASM_DCBTST(17, 14, 6);
+ ASM_DCBTST(17, 14, 15);
+}
+
+
+static test_t tests_dcbt[] = {
+ { &test_dcbtct , " dcbtct", },
+ { &test_dcbtds , " dcbtds", },
+ { &test_dcbtst , " dcbtst", },
+ { NULL, NULL, },
+};
+
+
+#if defined (IS_PPC405)
+static void test_macchw (void)
+{
+ __asm__ __volatile__ ("macchw 17, 14, 15");
+}
+
+static void test_macchwo (void)
+{
+ __asm__ __volatile__ ("macchwo 17, 14, 15");
+}
+
+static void test_macchws (void)
+{
+ __asm__ __volatile__ ("macchws 17, 14, 15");
+}
+
+static void test_macchwso (void)
+{
+ __asm__ __volatile__ ("macchwso 17, 14, 15");
+}
+
+static void test_macchwsu (void)
+{
+ __asm__ __volatile__ ("macchwsu 17, 14, 15");
+}
+
+static void test_macchwsuo (void)
+{
+ __asm__ __volatile__ ("macchwsuo 17, 14, 15");
+}
+
+static void test_macchwu (void)
+{
+ __asm__ __volatile__ ("macchwu 17, 14, 15");
+}
+
+static void test_macchwuo (void)
+{
+ __asm__ __volatile__ ("macchwuo 17, 14, 15");
+}
+
+static void test_machhw (void)
+{
+ __asm__ __volatile__ ("machhw 17, 14, 15");
+}
+
+static void test_machhwo (void)
+{
+ __asm__ __volatile__ ("machhwo 17, 14, 15");
+}
+
+static void test_machhws (void)
+{
+ __asm__ __volatile__ ("machhws 17, 14, 15");
+}
+
+static void test_machhwso (void)
+{
+ __asm__ __volatile__ ("machhwso 17, 14, 15");
+}
+
+static void test_machhwsu (void)
+{
+ __asm__ __volatile__ ("machhwsu 17, 14, 15");
+}
+
+static void test_machhwsuo (void)
+{
+ __asm__ __volatile__ ("machhwsuo 17, 14, 15");
+}
+
+static void test_machhwu (void)
+{
+ __asm__ __volatile__ ("machhwu 17, 14, 15");
+}
+
+static void test_machhwuo (void)
+{
+ __asm__ __volatile__ ("machhwuo 17, 14, 15");
+}
+
+static void test_maclhw (void)
+{
+ __asm__ __volatile__ ("maclhw 17, 14, 15");
+}
+
+static void test_maclhwo (void)
+{
+ __asm__ __volatile__ ("maclhwo 17, 14, 15");
+}
+
+static void test_maclhws (void)
+{
+ __asm__ __volatile__ ("maclhws 17, 14, 15");
+}
+
+static void test_maclhwso (void)
+{
+ __asm__ __volatile__ ("maclhwso 17, 14, 15");
+}
+
+static void test_maclhwsu (void)
+{
+ __asm__ __volatile__ ("maclhwsu 17, 14, 15");
+}
+
+static void test_maclhwsuo (void)
+{
+ __asm__ __volatile__ ("maclhwsuo 17, 14, 15");
+}
+
+static void test_maclhwu (void)
+{
+ __asm__ __volatile__ ("maclhwu 17, 14, 15");
+}
+
+static void test_maclhwuo (void)
+{
+ __asm__ __volatile__ ("maclhwuo 17, 14, 15");
+}
+
+static void test_mulchw (void)
+{
+ __asm__ __volatile__ ("mulchw 17, 14, 15");
+}
+
+static void test_mulchwu (void)
+{
+ __asm__ __volatile__ ("mulchwu 17, 14, 15");
+}
+
+static void test_mulhhw (void)
+{
+ __asm__ __volatile__ ("mulhhw 17, 14, 15");
+}
+
+static void test_mulhhwu (void)
+{
+ __asm__ __volatile__ ("mulhhwu 17, 14, 15");
+}
+
+static void test_mullhw (void)
+{
+ __asm__ __volatile__ ("mullhw 17, 14, 15");
+}
+
+static void test_mullhwu (void)
+{
+ __asm__ __volatile__ ("mullhwu 17, 14, 15");
+}
+
+static void test_nmacchw (void)
+{
+ __asm__ __volatile__ ("nmacchw 17, 14, 15");
+}
+
+static void test_nmacchwo (void)
+{
+ __asm__ __volatile__ ("nmacchwo 17, 14, 15");
+}
+
+static void test_nmacchws (void)
+{
+ __asm__ __volatile__ ("nmacchws 17, 14, 15");
+}
+
+static void test_nmacchwso (void)
+{
+ __asm__ __volatile__ ("nmacchwso 17, 14, 15");
+}
+
+static void test_nmachhw (void)
+{
+ __asm__ __volatile__ ("nmachhw 17, 14, 15");
+}
+
+static void test_nmachhwo (void)
+{
+ __asm__ __volatile__ ("nmachhwo 17, 14, 15");
+}
+
+static void test_nmachhws (void)
+{
+ __asm__ __volatile__ ("nmachhws 17, 14, 15");
+}
+
+static void test_nmachhwso (void)
+{
+ __asm__ __volatile__ ("nmachhwso 17, 14, 15");
+}
+
+static void test_nmaclhw (void)
+{
+ __asm__ __volatile__ ("nmaclhw 17, 14, 15");
+}
+
+static void test_nmaclhwo (void)
+{
+ __asm__ __volatile__ ("nmaclhwo 17, 14, 15");
+}
+
+static void test_nmaclhws (void)
+{
+ __asm__ __volatile__ ("nmaclhws 17, 14, 15");
+}
+
+static void test_nmaclhwso (void)
+{
+ __asm__ __volatile__ ("nmaclhwso 17, 14, 15");
+}
+
+static test_t tests_p4m_ops_two[] = {
+ { &test_macchw , " macchw", },
+ { &test_macchwo , " macchwo", },
+ { &test_macchws , " macchws", },
+ { &test_macchwso , " macchwso", },
+ { &test_macchwsu , " macchwsu", },
+ { &test_macchwsuo , " macchwsuo", },
+ { &test_macchwu , " macchwu", },
+ { &test_macchwuo , " macchwuo", },
+ { &test_machhw , " machhw", },
+ { &test_machhwo , " machhwo", },
+ { &test_machhws , " machhws", },
+ { &test_machhwso , " machhwso", },
+ { &test_machhwsu , " machhwsu", },
+ { &test_machhwsuo , " machhwsuo", },
+ { &test_machhwu , " machhwu", },
+ { &test_machhwuo , " machhwuo", },
+ { &test_maclhw , " maclhw", },
+ { &test_maclhwo , " maclhwo", },
+ { &test_maclhws , " maclhws", },
+ { &test_maclhwso , " maclhwso", },
+ { &test_maclhwsu , " maclhwsu", },
+ { &test_maclhwsuo , " maclhwsuo", },
+ { &test_maclhwu , " maclhwu", },
+ { &test_maclhwuo , " maclhwuo", },
+ { &test_mulchw , " mulchw", },
+ { &test_mulchwu , " mulchwu", },
+ { &test_mulhhw , " mulhhw", },
+ { &test_mulhhwu , " mulhhwu", },
+ { &test_mullhw , " mullhw", },
+ { &test_mullhwu , " mullhwu", },
+ { &test_nmacchw , " nmacchw", },
+ { &test_nmacchwo , " nmacchwo", },
+ { &test_nmacchws , " nmacchws", },
+ { &test_nmacchwso , " nmacchwso", },
+ { &test_nmachhw , " nmachhw", },
+ { &test_nmachhwo , " nmachhwo", },
+ { &test_nmachhws , " nmachhws", },
+ { &test_nmachhwso , " nmachhwso", },
+ { &test_nmaclhw , " nmaclhw", },
+ { &test_nmaclhwo , " nmaclhwo", },
+ { &test_nmaclhws , " nmaclhws", },
+ { &test_nmaclhwso , " nmaclhwso", },
+ { NULL, NULL, },
+};
+#endif /* defined (IS_PPC405) */
+
+#if defined (IS_PPC405)
+static void test_macchw_ (void)
+{
+ __asm__ __volatile__ ("macchw. 17, 14, 15");
+}
+
+static void test_macchwo_ (void)
+{
+ __asm__ __volatile__ ("macchwo. 17, 14, 15");
+}
+
+static void test_macchws_ (void)
+{
+ __asm__ __volatile__ ("macchws. 17, 14, 15");
+}
+
+static void test_macchwso_ (void)
+{
+ __asm__ __volatile__ ("macchwso. 17, 14, 15");
+}
+
+static void test_macchwsu_ (void)
+{
+ __asm__ __volatile__ ("macchwsu. 17, 14, 15");
+}
+
+static void test_macchwsuo_ (void)
+{
+ __asm__ __volatile__ ("macchwsuo. 17, 14, 15");
+}
+
+static void test_macchwu_ (void)
+{
+ __asm__ __volatile__ ("macchwu. 17, 14, 15");
+}
+
+static void test_macchwuo_ (void)
+{
+ __asm__ __volatile__ ("macchwuo. 17, 14, 15");
+}
+
+static void test_machhw_ (void)
+{
+ __asm__ __volatile__ ("machhw. 17, 14, 15");
+}
+
+static void test_machhwo_ (void)
+{
+ __asm__ __volatile__ ("machhwo. 17, 14, 15");
+}
+
+static void test_machhws_ (void)
+{
+ __asm__ __volatile__ ("machhws. 17, 14, 15");
+}
+
+static void test_machhwso_ (void)
+{
+ __asm__ __volatile__ ("machhwso. 17, 14, 15");
+}
+
+static void test_machhwsu_ (void)
+{
+ __asm__ __volatile__ ("machhwsu. 17, 14, 15");
+}
+
+static void test_machhwsuo_ (void)
+{
+ __asm__ __volatile__ ("machhwsuo. 17, 14, 15");
+}
+
+static void test_machhwu_ (void)
+{
+ __asm__ __volatile__ ("machhwu. 17, 14, 15");
+}
+
+static void test_machhwuo_ (void)
+{
+ __asm__ __volatile__ ("machhwuo. 17, 14, 15");
+}
+
+static void test_maclhw_ (void)
+{
+ __asm__ __volatile__ ("maclhw. 17, 14, 15");
+}
+
+static void test_maclhwo_ (void)
+{
+ __asm__ __volatile__ ("maclhwo. 17, 14, 15");
+}
+
+static void test_maclhws_ (void)
+{
+ __asm__ __volatile__ ("maclhws. 17, 14, 15");
+}
+
+static void test_maclhwso_ (void)
+{
+ __asm__ __volatile__ ("maclhwso. 17, 14, 15");
+}
+
+static void test_maclhwsu_ (void)
+{
+ __asm__ __volatile__ ("maclhwsu. 17, 14, 15");
+}
+
+static void test_maclhwsuo_ (void)
+{
+ __asm__ __volatile__ ("maclhwsuo. 17, 14, 15");
+}
+
+static void test_maclhwu_ (void)
+{
+ __asm__ __volatile__ ("maclhwu. 17, 14, 15");
+}
+
+static void test_maclhwuo_ (void)
+{
+ __asm__ __volatile__ ("maclhwuo. 17, 14, 15");
+}
+
+static void test_mulchw_ (void)
+{
+ __asm__ __volatile__ ("mulchw. 17, 14, 15");
+}
+
+static void test_mulchwu_ (void)
+{
+ __asm__ __volatile__ ("mulchwu. 17, 14, 15");
+}
+
+static void test_mulhhw_ (void)
+{
+ __asm__ __volatile__ ("mulhhw. 17, 14, 15");
+}
+
+static void test_mulhhwu_ (void)
+{
+ __asm__ __volatile__ ("mulhhwu. 17, 14, 15");
+}
+
+static void test_mullhw_ (void)
+{
+ __asm__ __volatile__ ("mullhw. 17, 14, 15");
+}
+
+static void test_mullhwu_ (void)
+{
+ __asm__ __volatile__ ("mullhwu. 17, 14, 15");
+}
+
+static void test_nmacchw_ (void)
+{
+ __asm__ __volatile__ ("nmacchw. 17, 14, 15");
+}
+
+static void test_nmacchwo_ (void)
+{
+ __asm__ __volatile__ ("nmacchwo. 17, 14, 15");
+}
+
+static void test_nmacchws_ (void)
+{
+ __asm__ __volatile__ ("nmacchws. 17, 14, 15");
+}
+
+static void test_nmacchwso_ (void)
+{
+ __asm__ __volatile__ ("nmacchwso. 17, 14, 15");
+}
+
+static void test_nmachhw_ (void)
+{
+ __asm__ __volatile__ ("nmachhw. 17, 14, 15");
+}
+
+static void test_nmachhwo_ (void)
+{
+ __asm__ __volatile__ ("nmachhwo. 17, 14, 15");
+}
+
+static void test_nmachhws_ (void)
+{
+ __asm__ __volatile__ ("nmachhws. 17, 14, 15");
+}
+
+static void test_nmachhwso_ (void)
+{
+ __asm__ __volatile__ ("nmachhwso. 17, 14, 15");
+}
+
+static void test_nmaclhw_ (void)
+{
+ __asm__ __volatile__ ("nmaclhw. 17, 14, 15");
+}
+
+static void test_nmaclhwo_ (void)
+{
+ __asm__ __volatile__ ("nmaclhwo. 17, 14, 15");
+}
+
+static void test_nmaclhws_ (void)
+{
+ __asm__ __volatile__ ("nmaclhws. 17, 14, 15");
+}
+
+static void test_nmaclhwso_ (void)
+{
+ __asm__ __volatile__ ("nmaclhwso. 17, 14, 15");
+}
+
+static test_t tests_p4mc_ops_two[] = {
+ { &test_macchw_ , " macchw.", },
+ { &test_macchwo_ , " macchwo.", },
+ { &test_macchws_ , " macchws.", },
+ { &test_macchwso_ , " macchwso.", },
+ { &test_macchwsu_ , " macchwsu.", },
+ { &test_macchwsuo_ , " macchwsuo.", },
+ { &test_macchwu_ , " macchwu.", },
+ { &test_macchwuo_ , " macchwuo.", },
+ { &test_machhw_ , " machhw.", },
+ { &test_machhwo_ , " machhwo.", },
+ { &test_machhws_ , " machhws.", },
+ { &test_machhwso_ , " machhwso.", },
+ { &test_machhwsu_ , " machhwsu.", },
+ { &test_machhwsuo_ , " machhwsuo.", },
+ { &test_machhwu_ , " machhwu.", },
+ { &test_machhwuo_ , " machhwuo.", },
+ { &test_maclhw_ , " maclhw.", },
+ { &test_maclhwo_ , " maclhwo.", },
+ { &test_maclhws_ , " maclhws.", },
+ { &test_maclhwso_ , " maclhwso.", },
+ { &test_maclhwsu_ , " maclhwsu.", },
+ { &test_maclhwsuo_ , " maclhwsuo.", },
+ { &test_maclhwu_ , " maclhwu.", },
+ { &test_maclhwuo_ , " maclhwuo.", },
+ { &test_mulchw_ , " mulchw.", },
+ { &test_mulchwu_ , " mulchwu.", },
+ { &test_mulhhw_ , " mulhhw.", },
+ { &test_mulhhwu_ , " mulhhwu.", },
+ { &test_mullhw_ , " mullhw.", },
+ { &test_mullhwu_ , " mullhwu.", },
+ { &test_nmacchw_ , " nmacchw.", },
+ { &test_nmacchwo_ , " nmacchwo.", },
+ { &test_nmacchws_ , " nmacchws.", },
+ { &test_nmacchwso_ , " nmacchwso.", },
+ { &test_nmachhw_ , " nmachhw.", },
+ { &test_nmachhwo_ , " nmachhwo.", },
+ { &test_nmachhws_ , " nmachhws.", },
+ { &test_nmachhwso_ , " nmachhwso.", },
+ { &test_nmaclhw_ , " nmaclhw.", },
+ { &test_nmaclhwo_ , " nmaclhwo.", },
+ { &test_nmaclhws_ , " nmaclhws.", },
+ { &test_nmaclhwso_ , " nmaclhwso.", },
+ { NULL, NULL, },
+};
+#endif /* defined (IS_PPC405) */
+
+static test_table_t all_tests[] = {
+ {
+ tests_ia_ops_two ,
+ "PPC integer arith insns with two args",
+ 0x00010102,
+ },
+ {
+ tests_iar_ops_two ,
+ "PPC integer arith insns with two args with flags update",
+ 0x01010102,
+ },
+ {
+ tests_iac_ops_two ,
+ "PPC integer arith insns with two args and carry",
+ 0x02010102,
+ },
+ {
+ tests_iacr_ops_two ,
+ "PPC integer arith insns with two args and carry with flags update",
+ 0x03010102,
+ },
+ {
+ tests_il_ops_two ,
+ "PPC integer logical insns with two args",
+ 0x00010202,
+ },
+ {
+ tests_ilr_ops_two ,
+ "PPC integer logical insns with two args with flags update",
+ 0x01010202,
+ },
+ {
+ tests_icr_ops_two ,
+ "PPC integer compare insns (two args)",
+ 0x01010304,
+ },
+ {
+ tests_icr_ops_two_i16 ,
+ "PPC integer compare with immediate insns (two args)",
+ 0x01010305,
+ },
+ {
+ tests_ia_ops_two_i16 ,
+ "PPC integer arith insns\n with one register + one 16 bits immediate args",
+ 0x00010106,
+ },
+ {
+ tests_iar_ops_two_i16 ,
+ "PPC integer arith insns\n with one register + one 16 bits immediate args with flags update",
+ 0x01010106,
+ },
+ {
+ tests_il_ops_two_i16 ,
+ "PPC integer logical insns\n with one register + one 16 bits immediate args",
+ 0x00010206,
+ },
+ {
+ tests_ilr_ops_two_i16 ,
+ "PPC integer logical insns\n with one register + one 16 bits immediate args with flags update",
+ 0x01010206,
+ },
+ {
+ tests_crl_ops_two ,
+ "PPC condition register logical insns - two operands",
+ 0x01010202,
+ },
+ {
+ tests_iac_ops_one ,
+ "PPC integer arith insns with one arg and carry",
+ 0x02010101,
+ },
+ {
+ tests_iacr_ops_one ,
+ "PPC integer arith insns with one arg and carry with flags update",
+ 0x03010101,
+ },
+ {
+ tests_il_ops_one ,
+ "PPC integer logical insns with one arg",
+ 0x00010201,
+ },
+ {
+ tests_ilr_ops_one ,
+ "PPC integer logical insns with one arg with flags update",
+ 0x01010201,
+ },
+ {
+ tests_il_ops_spe ,
+ "PPC logical insns with special forms",
+ 0x00010207,
+ },
+ {
+ tests_ilr_ops_spe ,
+ "PPC logical insns with special forms with flags update",
+ 0x01010207,
+ },
+ {
+ tests_ild_ops_two_i16 ,
+ "PPC integer load insns\n with one register + one 16 bits immediate args with flags update",
+ 0x00010508,
+ },
+ {
+ tests_ild_ops_two ,
+ "PPC integer load insns with two register args",
+ 0x00010509,
+ },
+ {
+ tests_ist_ops_three_i16,
+ "PPC integer store insns\n with one register + one 16 bits immediate args with flags update",
+ 0x0001050a,
+ },
+ {
+ tests_ist_ops_three ,
+ "PPC integer store insns with three register args",
+ 0x0001050b,
+ },
+ {
+ tests_popcnt_ops_one ,
+ "PPC integer population count with one register args, no flags",
+ 0x00010601,
+ },
+#if !defined (NO_FLOAT)
+ {
+ tests_fa_ops_three ,
+ "PPC floating point arith insns with three args",
+ 0x00020103,
+ },
+#endif /* !defined (NO_FLOAT) */
+#if !defined (NO_FLOAT)
+ {
+ tests_far_ops_three ,
+ "PPC floating point arith insns\n with three args with flags update",
+ 0x01020103,
+ },
+#endif /* !defined (NO_FLOAT) */
+#if !defined (NO_FLOAT)
+ {
+ tests_fa_ops_two ,
+ "PPC floating point arith insns with two args",
+ 0x00020102,
+ },
+#endif /* !defined (NO_FLOAT) */
+#if !defined (NO_FLOAT)
+ {
+ tests_far_ops_two ,
+ "PPC floating point arith insns\n with two args with flags update",
+ 0x01020102,
+ },
+#endif /* !defined (NO_FLOAT) */
+#if !defined (NO_FLOAT)
+ {
+ tests_fcr_ops_two ,
+ "PPC floating point compare insns (two args)",
+ 0x01020304,
+ },
+#endif /* !defined (NO_FLOAT) */
+#if !defined (NO_FLOAT)
+ {
+ tests_fa_ops_one ,
+ "PPC floating point arith insns with one arg",
+ 0x00020101,
+ },
+#endif /* !defined (NO_FLOAT) */
+#if !defined (NO_FLOAT)
+ {
+ tests_far_ops_one ,
+ "PPC floating point arith insns\n with one arg with flags update",
+ 0x01020101,
+ },
+#endif /* !defined (NO_FLOAT) */
+#if !defined (NO_FLOAT)
+ {
+ tests_fl_ops_spe ,
+ "PPC floating point status register manipulation insns",
+ 0x00020207,
+ },
+#endif /* !defined (NO_FLOAT) */
+#if !defined (NO_FLOAT)
+ {
+ tests_flr_ops_spe ,
+ "PPC floating point status register manipulation insns\n with flags update",
+ 0x01020207,
+ },
+#endif /* !defined (NO_FLOAT) */
+#if !defined (NO_FLOAT)
+ {
+ tests_fld_ops_two_i16 ,
+ "PPC float load insns\n with one register + one 16 bits immediate args with flags update",
+ 0x00020508,
+ },
+#endif /* !defined (NO_FLOAT) */
+#if !defined (NO_FLOAT)
+ {
+ tests_fld_ops_two ,
+ "PPC float load insns with two register args",
+ 0x00020509,
+ },
+#endif /* !defined (NO_FLOAT) */
+#if !defined (NO_FLOAT)
+ {
+ tests_fst_ops_three_i16,
+ "PPC float store insns\n with one register + one 16 bits immediate args with flags update",
+ 0x0002050a,
+ },
+#endif /* !defined (NO_FLOAT) */
+#if !defined (NO_FLOAT)
+ {
+ tests_fst_ops_three ,
+ "PPC float store insns with three register args",
+ 0x0002050b,
+ },
+#endif /* !defined (NO_FLOAT) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_aa_ops_three ,
+ "PPC altivec integer arith insns with three args",
+ 0x00040103,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_al_ops_three ,
+ "PPC altivec integer logical insns with three args",
+ 0x00040203,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_aa_ops_two ,
+ "PPC altivec integer arith insns with two args",
+ 0x00040102,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_al_ops_two ,
+ "PPC altivec integer logical insns with two args",
+ 0x00040202,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_al_ops_one ,
+ "PPC altivec integer logical insns with one arg",
+ 0x00040201,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_ac_ops_two ,
+ "Altivec integer compare insns",
+ 0x00040302,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_acr_ops_two ,
+ "Altivec integer compare insns with flags update",
+ 0x01040302,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_av_int_ops_spe ,
+ "Altivec integer special insns",
+ 0x00040207,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_ald_ops_two ,
+ "Altivec load insns with two register args",
+ 0x00040509,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_ast_ops_three ,
+ "Altivec store insns with three register args",
+ 0x0004050b,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_afa_ops_two ,
+ "Altivec floating point arith insns with two args",
+ 0x00050102,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_afa_ops_three ,
+ "Altivec floating point arith insns with three args",
+ 0x00050103,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_afa_ops_one ,
+ "Altivec floating point arith insns with one arg",
+ 0x00050101,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_afc_ops_two ,
+ "Altivec floating point compare insns",
+ 0x00050302,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_afcr_ops_two ,
+ "Altivec floating point compare insns with flags update",
+ 0x01050302,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+#if defined (HAS_ALTIVEC)
+ {
+ tests_av_float_ops_spe,
+ "Altivec float special insns",
+ 0x00050207,
+ },
+#endif /* defined (HAS_ALTIVEC) */
+ {
+ tests_dcbt,
+ "Miscellaneous test: Data cache insns",
+ 0x0006070C,
+ },
+#if defined (IS_PPC405)
+ {
+ tests_p4m_ops_two ,
+ "PPC 405 mac insns with three args",
+ 0x00030102,
+ },
+#endif /* defined (IS_PPC405) */
+#if defined (IS_PPC405)
+ {
+ tests_p4mc_ops_two ,
+ "PPC 405 mac insns with three args with flags update",
+ 0x01030102,
+ },
+#endif /* defined (IS_PPC405) */
+ { NULL, NULL, 0x00000000, },
+};
+
+/* -------------- END #include "ops-ppc.c" -------------- */
+
+static int verbose = 0;
+static int arg_list_size = 0;
+
+static double *fargs = NULL;
+static int nb_fargs = 0;
+static int nb_normal_fargs = 0;
+static HWord_t *iargs = NULL;
+static int nb_iargs = 0;
+static uint16_t *ii16 = NULL;
+static int nb_ii16 = 0;
+
+#if defined (HAS_ALTIVEC)
+static vector unsigned int* viargs = NULL;
+static int nb_viargs = 0;
+static vector float* vfargs = NULL;
+static int nb_vfargs = 0;
+
+//#define TEST_VSCR_SAT
+#endif
+
+static inline void register_farg (void *farg,
+ int s, uint16_t _exp, uint64_t mant)
+{
+ uint64_t tmp;
+
+ tmp = ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
+ *(uint64_t *)farg = tmp;
+#ifndef __powerpc64__
+ AB_DPRINTF("%d %03x %013llx => %016llx %0e\n",
+#else
+ AB_DPRINTF("%d %03x %013lx => %016lx %0e\n",
+#endif
+ s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
+}
+
+static void build_fargs_table (void)
+{
+ /* Double precision:
+ * Sign goes from zero to one (1 bit)
+ * Exponent goes from 0 to ((1 << 12) - 1) (11 bits)
+ * Mantissa goes from 1 to ((1 << 52) - 1) (52 bits)
+ * + special values:
+ * +0.0 : 0 0x000 0x0000000000000 => 0x0000000000000000
+ * -0.0 : 1 0x000 0x0000000000000 => 0x8000000000000000
+ * +infinity : 0 0x7FF 0x0000000000000 => 0x7FF0000000000000
+ * -infinity : 1 0x7FF 0x0000000000000 => 0xFFF0000000000000
+ * +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF => 0x7FF7FFFFFFFFFFFF
+ * -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF => 0xFFF7FFFFFFFFFFFF
+ * +SNaN : 0 0x7FF 0x8000000000000 => 0x7FF8000000000000
+ * -SNaN : 1 0x7FF 0x8000000000000 => 0xFFF8000000000000
+ * (8 values)
+
+ * Ref only:
+ * Single precision
+ * Sign: 1 bit
+ * Exponent: 8 bits
+ * Mantissa: 23 bits
+ * +0.0 : 0 0x00 0x000000 => 0x00000000
+ * -0.0 : 1 0x00 0x000000 => 0x80000000
+ * +infinity : 0 0xFF 0x000000 => 0x7F800000
+ * -infinity : 1 0xFF 0x000000 => 0xFF800000
+ * +QNaN : 0 0xFF 0x3FFFFF => 0x7FBFFFFF
+ * -QNaN : 1 0xFF 0x3FFFFF => 0xFFBFFFFF
+ * +SNaN : 0 0xFF 0x400000 => 0x7FC00000
+ * -SNaN : 1 0xFF 0x400000 => 0xFFC00000
+ */
+ uint64_t mant;
+ uint16_t _exp, e0, e1;
+ int s;
+ int i=0;
+
+ /* Note: VEX isn't so hot with denormals, so don't bother
+ testing them: set _exp > 0
+ */
+
+ if ( arg_list_size == 1 ) { // Large
+ fargs = malloc(200 * sizeof(double));
+ for (s=0; s<2; s++) {
+ for (e0=0; e0<2; e0++) {
+ for (e1=0x001; ; e1 = ((e1 + 1) << 2) + 6) {
+ if (e1 >= 0x400)
+ e1 = 0x3fe;
+ _exp = (e0 << 10) | e1;
+ for (mant = 0x0000000000001ULL; mant < (1ULL << 52);
+ /* Add 'random' bits */
+ mant = ((mant + 0x4A6) << 13) + 0x359) {
+ register_farg(&fargs[i++], s, _exp, mant);
+ }
+ if (e1 == 0x3fe)
+ break;
+ }
+ }
+ }
+ } else { // Default
+ fargs = malloc(16 * sizeof(double));
+ for (s=0; s<2; s++) { // x2
+// for (e0=0; e0<2; e0++) {
+ for (e1=0x001; ; e1 = ((e1 + 1) << 13) + 7) { // x2
+// for (e1=0x001; ; e1 = ((e1 + 1) << 5) + 7) { // x3
+ if (e1 >= 0x400)
+ e1 = 0x3fe;
+// _exp = (e0 << 10) | e1;
+ _exp = e1;
+ for (mant = 0x0000000000001ULL; mant < (1ULL << 52);
+ /* Add 'random' bits */
+ mant = ((mant + 0x4A6) << 29) + 0x359) { // x2
+ register_farg(&fargs[i++], s, _exp, mant);
+ }
+ if (e1 == 0x3fe)
+ break;
+ }
+// }
+ }
+ }
+
+ /* To iterate over non-special values only */
+ nb_normal_fargs = i;
+
+
+ /* Special values */
+ /* +0.0 : 0 0x000 0x0000000000000 */
+ s = 0;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* -0.0 : 1 0x000 0x0000000000000 */
+ s = 1;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* +infinity : 0 0x7FF 0x0000000000000 */
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* -infinity : 1 0x7FF 0x0000000000000 */
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF */
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF */
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* +SNaN : 0 0x7FF 0x8000000000000 */
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ /* -SNaN : 1 0x7FF 0x8000000000000 */
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+ AB_DPRINTF("Registered %d fargs values\n", i);
+
+ nb_fargs = i;
+}
+
+static void build_iargs_table (void)
+{
+ uint64_t tmp;
+ int i=0;
+
+#ifndef __powerpc64__
+ if (arg_list_size == 1) { // Large
+ iargs = malloc(400 * sizeof(HWord_t));
+ for (tmp=0; ; tmp = tmp + 1 + (tmp >> 1)) {
+ if (tmp >= 0x100000000ULL)
+ tmp = 0xFFFFFFFF;
+ iargs[i++] = (HWord_t)tmp;
+ AB_DPRINTF("val %08x\n", (HWord_t)tmp);
+ if (tmp == 0xFFFFFFFF)
+ break;
+ }
+ } else { // Default
+ iargs = malloc(10 * sizeof(HWord_t));
+ // for (tmp = 0; ; tmp = 71*tmp + 1 + (tmp>>1)) { // gives 8
+ // for (tmp = 0; ; tmp = 100000*tmp + 1 + (tmp>>1)) { // gives 4
+ for (tmp=0; ; tmp = 999999*tmp + 999999) { // gives 3
+ if (tmp >= 0x100000000ULL)
+ tmp = 0xFFFFFFFF;
+ iargs[i++] = (HWord_t)tmp;
+ AB_DPRINTF("val %08x\n", (HWord_t)tmp);
+ if (tmp == 0xFFFFFFFF)
+ break;
+ }
+ }
+#else
+ if (arg_list_size == 1) { // Large
+ iargs = malloc(800 * sizeof(HWord_t));
+ for (tmp=0; ; tmp = 2*tmp + 1 + (tmp >> 2)) {
+ if ((long)tmp < 0 )
+ tmp = 0xFFFFFFFFFFFFFFFFULL;
+ iargs[i++] = tmp;
+ AB_DPRINTF("val %016lx\n", tmp);
+ if (tmp == 0xFFFFFFFFFFFFFFFFULL)
+ break;
+ }
+ } else { // Default
+ iargs = malloc(20 * sizeof(HWord_t));
+ // for (tmp=0; ; tmp = 9999*tmp + 999999) { // gives 6
+ for (tmp = 0; ; tmp = 123456789*tmp + 123456789999) { // gives 3
+ if ((long)tmp < 0 )
+ tmp = 0xFFFFFFFFFFFFFFFFULL;
+ iargs[i++] = tmp;
+ AB_DPRINTF("val %016lx\n", tmp);
+ if (tmp == 0xFFFFFFFFFFFFFFFFULL)
+ break;
+ }
+ }
+#endif // #ifndef __powerpc64__
+
+ AB_DPRINTF("Registered %d iargs values\n", i);
+ nb_iargs = i;
+}
+
+static void build_ii16_table (void)
+{
+ uint32_t tmp;
+ int i=0;
+
+ if (arg_list_size == 1) { // Large
+ ii16 = malloc(200 * sizeof(uint32_t));
+ for (tmp=0; ; tmp = tmp + 1 + (tmp >> 2)) {
+ if (tmp >= 0x10000)
+ tmp = 0xFFFF;
+ ii16[i++] = tmp;
+ AB_DPRINTF("val %04x\n", tmp);
+ if (tmp == 0xFFFF)
+ break;
+ }
+ } else { // Default
+ ii16 = malloc(10 * sizeof(uint32_t));
+ for (tmp=0; ; tmp = 999*tmp + 999) { // gives 3
+ if (tmp >= 0x10000)
+ tmp = 0xFFFF;
+ ii16[i++] = tmp;
+ AB_DPRINTF("val %04x\n", tmp);
+ if (tmp == 0xFFFF)
+ break;
+ }
+ }
+ AB_DPRINTF("Registered %d ii16 values\n", i);
+ nb_ii16 = i;
+}
+
+#if defined (HAS_ALTIVEC)
+static void build_viargs_table (void)
+{
+#if !defined (ALTIVEC_ARGS_LARGE)
+ unsigned int i=2;
+ viargs = memalign16(i * sizeof(vector unsigned int));
+ viargs[0] = (vector unsigned int) { 0x01020304,0x05060708,0x090A0B0C,0x0E0D0E0F };
+ AB_DPRINTF_VEC32x4( viargs[0] );
+ viargs[1] = (vector unsigned int) { 0xF1F2F3F4,0xF5F6F7F8,0xF9FAFBFC,0xFEFDFEFF };
+ AB_DPRINTF_VEC32x4( viargs[1] );
+#else
+ unsigned int i,j;
+ // build from iargs table (large/default already set)
+ viargs = malloc(nb_iargs * sizeof(vector unsigned int));
+ for (i=0; i<nb_iargs; i++) {
+ j = iargs[i];
+ viargs[i] = (vector unsigned int){ j, j*2, j*3, j*4 };
+ AB_DPRINTF_VEC32x4( viargs[i] );
+ }
+#endif
+
+ AB_DPRINTF("Registered %d viargs values\n", i);
+ nb_viargs = i;
+}
+
+static inline void register_vfarg (vector float* vfarg,
+ int s, uint8_t _exp, uint32_t mant)
+{
+ uint32_t tmp;
+ vector uint32_t* vfargI = (vector uint32_t*)vfarg;
+
+ tmp = ((uint64_t)s << 31) | ((uint64_t)_exp << 23) | mant;
+ *vfargI = (vector uint32_t){ tmp,tmp,tmp,tmp };
+ AB_DPRINTF("%d %02x %06x => %08x %0e\n",
+ s, _exp, mant, *((uint32_t*)&tmp), *(float*)&tmp);
+}
+
+static void build_vfargs_table (void)
+{
+ /* Sign goes from zero to one
+ * Exponent goes from 0 to ((1 << 9) - 1)
+ * Mantissa goes from 1 to ((1 << 24) - 1)
+ * + special values:
+ * +0.0 : 0 0x00 0x000000 => 0x00000000
+ * -0.0 : 1 0x00 0x000000 => 0x80000000
+ * +infinity : 0 0xFF 0x000000 => 0x7F800000
+ * -infinity : 1 0xFF 0x000000 => 0xFF800000
+ * +SNaN : 0 0xFF 0x7FFFFF (non-zero) => 0x7FFFFFFF
+ * -SNaN : 1 0xFF 0x7FFFFF (non-zero) => 0xFFFFFFFF
+ * +QNaN : 0 0xFF 0x3FFFFF (non-zero) => 0x7FBFFFFF
+ * -QNaN : 1 0xFF 0x3FFFFF (non-zero) => 0xFFBFFFFF
+ * (8 values)
+ */
+ uint32_t mant;
+ uint16_t _exp;
+ int s;
+ int i=0;
+
+
+#if !defined (ALTIVEC_ARGS_LARGE)
+ nb_vfargs = 12;
+ vfargs = memalign16(nb_vfargs * sizeof(vector float));
+
+ // 4 values:
+ for (s=0; s<2; s++) {
+ for (_exp=0x5; ; _exp += 0x9D ) {
+ if (_exp > 0xDF)
+ break;
+ for (mant = 0x3FFFFF; mant < 0x7FFFFF;
+ mant = /* random */ ((mant + 0x1A6) << 31) + 0x159) {
+ register_vfarg(&vfargs[i++], s, (uint8_t)_exp, mant);
+ }
+ }
+ }
+#else
+ nb_vfargs = 50;
+ vfargs = memalign16(nb_vfargs * sizeof(vector float));
+
+ for (s=0; s<2; s++) {
+ for (_exp=0x0; ; _exp += 0x3F ) {
+ // for (_exp=0; ; _exp = ((_exp + 1) << 1) + 3) {
+ if (_exp >= 0xFE)
+ _exp = 0xFE;
+ for (mant = 0x0; mant < 0x7FFFFF;
+ mant = /* random */ ((mant + 0x4A6) << 5) + 0x359) {
+ register_vfarg(&vfargs[i++], s, (uint8_t)_exp, mant);
+ }
+ if (_exp >= 0xFE)
+ break;
+ }
+ }
+#endif
+
+ /* Special values */
+ /* +0.0 : 0 0x00 0x000000 */
+ s = 0;
+ _exp = 0x00;
+ mant = 0x000000;
+ register_vfarg(&vfargs[i++], s, _exp, mant);
+ /* -0.0 : 1 0x00 0x000000 */
+ s = 1;
+ _exp = 0x00;
+ mant = 0x000000;
+ register_vfarg(&vfargs[i++], s, _exp, mant);
+
+ /* +infinity : 0 0xFF 0x000000 */
+ s = 0;
+ _exp = 0xFF;
+ mant = 0x000000;
+ register_vfarg(&vfargs[i++], s, _exp, mant);
+ /* -infinity : 1 0xFF 0x000000 */
+ s = 1;
+ _exp = 0xFF;
+ mant = 0x000000;
+ register_vfarg(&vfargs[i++], s, _exp, mant);
+
+ /* NaN: _exponent all 1s, non-zero fraction */
+ /* SNaN is a NaN with the most significant fraction bit clear.*/
+ /* +SNaN : 0 0xFF 0x7FFFFF */
+ s = 0;
+ _exp = 0xFF;
+ mant = 0x7FFFFF;
+ register_vfarg(&vfargs[i++], s, _exp, mant);
+ /* -SNaN : 1 0xFF 0x7FFFFF */
+ s = 1;
+ _exp = 0xFF;
+ mant = 0x7FFFFF;
+ register_vfarg(&vfargs[i++], s, _exp, mant);
+
+ /* QNaN is a NaN with the most significant fraction bit set */
+ /* +QNaN : 0 0xFF 0x3F0000 */
+ s = 0;
+ _exp = 0xFF;
+ mant = 0x3FFFFF;
+ register_vfarg(&vfargs[i++], s, _exp, mant);
+ /* -QNaN : 1 0xFF 0x3F0000 */
+ s = 1;
+ _exp = 0xFF;
+ mant = 0x3FFFFF;
+ register_vfarg(&vfargs[i++], s, _exp, mant);
+ AB_DPRINTF("Registered %d vfargs values\n", i);
+
+ assert(i <= nb_vfargs);
+ nb_vfargs = i;
+}
+#endif
+
+#if 0
+static void dump_iargs (void)
+{
+ int i;
+ for (i = 0; i < nb_iargs; i++) {
+ printf("iarg %d: %08x %08x %08x\n", i, iargs[i],
+ (unsigned int)&iargs[i], (unsigned int)iargs);
+ }
+}
+
+static void dump_iargs16 (void)
+{
+ int i;
+ for (i = 0; i < nb_ii16; i++) {
+ printf("iarg16 %d: %08x %08x %08x\n", i, ii16[i],
+ (unsigned int)&ii16[i], (unsigned int)ii16);
+ }
+}
+
+static void dump_vfargs (void)
+{
+ vector float vf;
+ float f;
+ int i=0;
+ for (i=0; i<nb_vfargs; i++) {
+ vf = (vector float)vfargs[i];
+ f = ((float*)&vf)[0];
+ printf("vfarg %3d: %24f : %08x\n", i, f, ((unsigned int*)&f)[0]);
+ }
+}
+#endif
+
+static void test_int_three_args (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile HWord_t res;
+ volatile uint32_t flags, xer;
+ int i, j, k;
+
+ for (i=0; i<nb_iargs; i++) {
+ for (j=0; j<nb_iargs; j++) {
+ for (k=0; k<nb_iargs; k++) {
+ r14 = iargs[i];
+ r15 = iargs[j];
+ r16 = iargs[k];
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = r17;
+
+#ifndef __powerpc64__
+ printf("%s %08x, %08x, %08x => %08x (%08x %08x)\n",
+#else
+ printf("%s %016llx, %016llx, %016llx => %016llx (%08x %08x)\n",
+#endif
+ name, iargs[i], iargs[j], iargs[k], res, flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+ }
+}
+
+static void test_int_two_args (const char* name, test_func_t func,
+ uint32_t test_flags)
+{
+ volatile HWord_t res;
+ volatile uint32_t flags, xer, xer_orig;
+ int i, j, is_div;
+#ifdef __powerpc64__
+ int zap_hi32;
+#endif
+
+ // catches div, divwu, divo, divwu, divwuo, and . variants
+ is_div = strstr(name, "divw") != NULL;
+
+#ifdef __powerpc64__
+ zap_hi32 = strstr(name, "mulhw") != NULL;
+#endif
+
+ xer_orig = 0x00000000;
+ redo:
+ for (i=0; i<nb_iargs; i++) {
+ for (j=0; j<nb_iargs; j++) {
+
+ /* result of division by zero is implementation dependent.
+ don't test it. */
+ if (is_div && iargs[j] == 0)
+ continue;
+
+ r14 = iargs[i];
+ r15 = iargs[j];
+
+ SET_XER(xer_orig);
+ SET_CR_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = r17;
+
+#ifndef __powerpc64__
+ printf("%s %08x, %08x => %08x (%08x %08x)\n",
+#else
+ if (zap_hi32) res &= 0xFFFFFFFFULL;
+ printf("%s %016llx, %016llx => %016llx (%08x %08x)\n",
+#endif
+ name, iargs[i], iargs[j], res, flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+ if ((test_flags & PPC_XER_CA) && xer_orig == 0x00000000) {
+ xer_orig = 0x20000000;
+ goto redo;
+ }
+}
+
+static void test_int_one_arg (const char* name, test_func_t func,
+ uint32_t test_flags)
+{
+ volatile HWord_t res;
+ volatile uint32_t flags, xer, xer_orig;
+ int i;
+
+ xer_orig = 0x00000000;
+ redo:
+ for (i=0; i<nb_iargs; i++) {
+ r14 = iargs[i];
+ SET_XER(xer_orig);
+ SET_CR_ZERO;
+ (*func)();
+ res = r17;
+ GET_CR_XER(flags,xer);
+
+#ifndef __powerpc64__
+ printf("%s %08x => %08x (%08x %08x)\n",
+#else
+ printf("%s %016llx => %016llx (%08x %08x)\n",
+#endif
+ name, iargs[i], res, flags, xer);
+ }
+ if ((test_flags & PPC_XER_CA) && xer_orig == 0x00000000) {
+ xer_orig = 0x20000000;
+ goto redo;
+ }
+}
+
+static inline void invalidate_icache ( void *ptr, int nbytes )
+{
+ HWord_t startaddr = (HWord_t) ptr;
+ HWord_t endaddr = startaddr + nbytes;
+ HWord_t cls = 32; /*VG_(cache_line_size_ppc32);*/
+ HWord_t addr;
+
+ startaddr &= ~(cls - 1);
+ for (addr = startaddr; addr < endaddr; addr += cls)
+ asm volatile("dcbst 0,%0" : : "r" (addr));
+ asm volatile("sync");
+ for (addr = startaddr; addr < endaddr; addr += cls)
+ asm volatile("icbi 0,%0" : : "r" (addr));
+ asm volatile("sync; isync");
+}
+
+/* for god knows what reason, if this isn't inlined, the
+ program segfaults. */
+static inline
+void _patch_op_imm (uint32_t *p_insn, uint16_t imm, int sh, int len)
+{
+ uint32_t mask = ((1 << len) - 1) << sh;
+ *p_insn = (*p_insn & ~mask) | ((imm<<sh) & mask);
+}
+
+static inline
+void patch_op_imm (uint32_t* p_insn, uint16_t imm, int sh, int len)
+{
+ _patch_op_imm(p_insn, imm, sh, len);
+ invalidate_icache(p_insn, 4);
+}
+
+static inline
+void patch_op_imm16 (uint32_t *p_insn, uint16_t imm)
+{
+ patch_op_imm(p_insn, imm, 0, 16);
+}
+
+
+/* Copy the 2 insn function starting at p_func_F to func_buf[], and
+ return a possibly different pointer, which, when called, runs the
+ copy in func_buf[]. */
+static inline
+test_func_t init_function( test_func_t p_func_F, uint32_t func_buf[] )
+{
+ uint32_t* p_func = (uint32_t*)p_func_F;
+#if !defined(__powerpc64__) || _CALL_ELF == 2
+ func_buf[0] = p_func[0];
+ func_buf[1] = p_func[1];
+ return (test_func_t)&func_buf[0];
+#else
+ /* p_func points to a function descriptor, the first word of which
+ points to the real code. Copy the code itself but not the
+ descriptor, and just swizzle the descriptor's entry pointer. */
+ uint64_t* descr = (uint64_t*)p_func;
+ uint32_t* entry = (uint32_t*)(descr[0]);
+ func_buf[0] = entry[0];
+ func_buf[1] = entry[1];
+ descr[0] = (uint64_t)&func_buf[0];
+ return (test_func_t)descr;
+#endif // #ifndef __powerpc64__
+}
+
+
+static void test_int_one_reg_imm16 (const char* name,
+ test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile HWord_t res;
+ volatile uint32_t flags, xer;
+ int i, j;
+
+ for (i=0; i<nb_iargs; i++) {
+ for (j=0; j<nb_ii16; j++) {
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ patch_op_imm16(&func_buf[0], ii16[j]);
+
+ r14 = iargs[i];
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = r17;
+
+#ifndef __powerpc64__
+ printf("%s %08x, %08x => %08x (%08x %08x)\n",
+#else
+ printf("%s %016llx, %08x => %016llx (%08x %08x)\n",
+#endif
+ name, iargs[i], ii16[j], res, flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+/* Special test cases for:
+ * rlwimi
+ * rlwinm
+ * rlwnm
+ * srawi
+ * mcrf
+ * mcrfs
+ * mcrxr_cb
+ * mfcr_cb
+ * mfspr_cb
+ * mftb_cb
+ * mtcrf_cb
+ * mtspr_cb
+
+ __powerpc64__ only:
+ * rldcl rA,rS,SH,MB
+ * rldcr rA,rS,SH,ME
+ * rldic rA,rS,SH,MB
+ * rldicl rA,rS,SH,MB
+ * rldicr rA,rS,SH,ME
+ * rldimi rA,rS,SH,MB
+ * sradi rA,rS,SH
+ */
+
+static void rlwi_cb (const char* name, test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile HWord_t res;
+ volatile uint32_t flags, xer;
+ int i, j, k, l, arg_step;
+
+ arg_step = (arg_list_size == 0) ? 31 : 3;
+
+ r17 = 0; // rlwimi takes r17 as input: start with a clean slate.
+
+ for (i=0; i<nb_iargs; i++) {
+ for (j=0; j<32; j+=arg_step) {
+ for (k=0; k<32; k+=arg_step) {
+ for (l=0; l<32; l+=arg_step) {
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ _patch_op_imm(&func_buf[0], j, 11, 5);
+ _patch_op_imm(&func_buf[0], k, 6, 5);
+ patch_op_imm(&func_buf[0], l, 1, 5);
+
+ r14 = iargs[i];
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = r17;
+
+#ifndef __powerpc64__
+ printf("%s %08x, %2d, %2d, %2d => %08x (%08x %08x)\n",
+#else
+ printf("%s %016llx, %2d, %2d, %2d => %016llx (%08x %08x)\n",
+#endif
+ name, iargs[i], j, k, l, res, flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+ }
+ }
+}
+
+static void rlwnm_cb (const char* name, test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile HWord_t res;
+ volatile uint32_t flags, xer;
+ int i, j, k, l, arg_step;
+
+ arg_step = (arg_list_size == 0) ? 31 : 3;
+
+ for (i=0; i<nb_iargs; i++) {
+ for (j=0; j<nb_iargs; j++) {
+ for (k=0; k<32; k+=arg_step) {
+ for (l=0; l<32; l+=arg_step) {
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ _patch_op_imm(&func_buf[0], k, 6, 5);
+ patch_op_imm(&func_buf[0], l, 1, 5);
+
+ r14 = iargs[i];
+ r15 = iargs[j];
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = r17;
+
+#ifndef __powerpc64__
+ printf("%s %08x, %08x, %2d, %2d => %08x (%08x %08x)\n",
+#else
+ printf("%s %016llx, %016llx, %2d, %2d => %016llx (%08x %08x)\n",
+#endif
+ name, iargs[i], iargs[j], k, l, res, flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+ }
+ }
+}
+
+static void srawi_cb (const char* name, test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile HWord_t res;
+ volatile uint32_t flags, xer;
+ int i, j, arg_step;
+
+ arg_step = (arg_list_size == 0) ? 31 : 1;
+
+ for (i=0; i<nb_iargs; i++) {
+ for (j=0; j<32; j+=arg_step) {
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ patch_op_imm(&func_buf[0], j, 11, 5);
+
+ r14 = iargs[i];
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = r17;
+
+#ifndef __powerpc64__
+ printf("%s %08x, %2d => %08x (%08x %08x)\n",
+#else
+ printf("%s %016llx, %2d => %016llx (%08x %08x)\n",
+#endif
+ name, iargs[i], j, res, flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+static void mcrf_cb (const char* name, test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile uint32_t flags, xer;
+ int i, j, k, arg_step;
+
+ arg_step = (arg_list_size == 0) ? 7 : 1;
+
+ for (i=0; i<nb_iargs; i++) {
+ for (j=0; j<8; j+=arg_step) {
+ for (k=0; k<8; k+=arg_step) {
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ _patch_op_imm(&func_buf[0], j, 23, 3);
+ patch_op_imm(&func_buf[0], k, 18, 3);
+
+ r14 = iargs[i];
+
+ SET_CR(r14);
+ SET_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+
+#ifndef __powerpc64__
+ printf("%s %d, %d (%08x) => (%08x %08x)\n",
+#else
+ printf("%s %d, %d (%016llx) => (%08x %08x)\n",
+#endif
+ name, j, k, iargs[i], flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+ }
+}
+
+static void mcrxr_cb (const char* name, test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile uint32_t flags, xer;
+ int i, j, k, arg_step;
+
+ arg_step = 1; //(arg_list_size == 0) ? 7 : 1;
+
+ for (i=0; i<16; i+=arg_step) {
+ j = i << 28;
+ for (k=0; k<8; k+=arg_step) {
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ patch_op_imm(&func_buf[0], k, 23, 3);
+
+ r14 = j;
+
+ SET_CR_ZERO;
+ SET_XER(r14);
+ (*func)();
+ GET_CR_XER(flags,xer);
+
+ printf("%s %d (%08x) => (%08x %08x)\n",
+ name, k, j, flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+static void mfcr_cb (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile HWord_t res;
+ volatile uint32_t flags, xer;
+ int i;
+
+ for (i=0; i<nb_iargs; i++) {
+ r14 = iargs[i];
+
+ /* Set up flags for test */
+ SET_CR(r14);
+ SET_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = r17;
+
+#ifndef __powerpc64__
+ printf("%s (%08x) => %08x (%08x %08x)\n",
+#else
+ printf("%s (%016llx) => %016llx (%08x %08x)\n",
+#endif
+ name, iargs[i], res, flags, xer);
+ }
+}
+
+// NOTE: Not using func: calling function kills lr
+static void mfspr_cb (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ //volatile uint32_t res, flags, xer, ctr, lr, tmpcr, tmpxer;
+ volatile HWord_t res;
+ int j, k;
+ func = func; // just to stop compiler complaining
+
+ // mtxer followed by mfxer
+ for (k=0; k<nb_iargs; k++) {
+ j = iargs[k];
+ __asm__ __volatile__(
+ "mtxer %1\n"
+ "\tmfxer %0"
+ : /*out*/"=b"(res) : /*in*/"b"(j) : /*trashed*/"xer"
+ );
+ res &= 0xE000007F; /* rest of the bits are undefined */
+
+#ifndef __powerpc64__
+ printf("%s 1 (%08x) -> mtxer -> mfxer => %08x\n",
+#else
+ printf("%s 1 (%08x) -> mtxer -> mfxer => %016llx\n",
+#endif
+ name, j, res);
+ }
+
+ // mtlr followed by mflr
+ for (k=0; k<nb_iargs; k++) {
+ j = iargs[k];
+ __asm__ __volatile__(
+ "mtlr %1\n"
+ "\tmflr %0"
+ : /*out*/"=b"(res) : /*in*/"b"(j) : /*trashed*/"lr"
+ );
+
+#ifndef __powerpc64__
+ printf("%s 8 (%08x) -> mtlr -> mflr => %08x\n",
+#else
+ printf("%s 8 (%08x) -> mtlr -> mflr => %016llx\n",
+#endif
+ name, j, res);
+ }
+
+ // mtctr followed by mfctr
+ for (k=0; k<nb_iargs; k++) {
+ j = iargs[k];
+ __asm__ __volatile__(
+ "mtctr %1\n"
+ "\tmfctr %0"
+ : /*out*/"=b"(res) : /*in*/"b"(j) : /*trashed*/"ctr"
+ );
+
+#ifndef __powerpc64__
+ printf("%s 9 (%08x) -> mtctr -> mfctr => %08x\n",
+#else
+ printf("%s 9 (%08x) -> mtctr -> mfctr => %016llx\n",
+#endif
+ name, j, res);
+ }
+}
+
+static void mtcrf_cb (const char* name, test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile uint32_t flags, xer;
+ int i, j, arg_step;
+
+ arg_step = (arg_list_size == 0) ? 99 : 1;
+
+ for (i=0; i<nb_iargs; i++) {
+ for (j=0; j<256; j+=arg_step) {
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ patch_op_imm(&func_buf[0], j, 12, 8);
+
+ r14 = iargs[i];
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+
+#ifndef __powerpc64__
+ printf("%s %3d, %08x => (%08x %08x)\n",
+#else
+ printf("%s %3d, %016llx => (%08x %08x)\n",
+#endif
+ name, j, iargs[i], flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+// NOTE: Not using func: calling function kills lr
+static void mtspr_cb (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+}
+
+#ifdef __powerpc64__
+static void rldc_cb (const char* name, test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile HWord_t res;
+ volatile uint32_t flags, xer;
+ int i, j, k, arg_step;
+
+ arg_step = (arg_list_size == 0) ? 7 : 3;
+
+ for (i=0; i<nb_iargs; i++) {
+ for (j=0; j<nb_iargs; j++) {
+ for (k=0; k<64; k+=arg_step) {
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ patch_op_imm(&func_buf[0], (((k & 0x1F)<<1) | ((k>>5)&1)), 5, 6);
+
+ r14 = iargs[i];
+ r15 = iargs[j];
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = r17;
+
+ printf("%s %016llx, %016llx, %2d => %016llx (%08x %08x)\n",
+ name, iargs[i], iargs[j], k, res, flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+ }
+}
+
+static void rldi_cb (const char* name, test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile HWord_t res;
+ volatile uint32_t flags, xer;
+ int i, j, k, arg_step;
+
+ arg_step = (arg_list_size == 0) ? 7 : 3;
+
+ for (i=0; i<nb_iargs; i++) {
+ for (j=0; j<64; j+=arg_step) { // SH
+ for (k=0; k<64; k+=arg_step) { // MB|ME
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ _patch_op_imm(&func_buf[0], (j & 0x1F), 11, 5);
+ _patch_op_imm(&func_buf[0], ((j>>5)&1), 1, 1);
+ patch_op_imm(&func_buf[0], (((k & 0x1F)<<1) | ((k>>5)&1)), 5, 6);
+
+ r14 = iargs[i];
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = r17;
+
+ printf("%s %016llx, %2d, %2d => %016llx (%08x %08x)\n",
+ name, iargs[i], j, k, res, flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+ }
+}
+
+static void sradi_cb (const char* name, test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile HWord_t res;
+ volatile uint32_t flags, xer;
+ int i, j, arg_step;
+
+ arg_step = (arg_list_size == 0) ? 7 : 3;
+
+ for (i=0; i<nb_iargs; i++) {
+ for (j=0; j<64; j+=arg_step) { // SH
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ _patch_op_imm(&func_buf[0], (j & 0x1F), 11, 5);
+ patch_op_imm(&func_buf[0], ((j>>5)&1), 1, 1);
+
+ r14 = iargs[i];
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = r17;
+
+ printf("%s %016llx, %2d => %016llx (%08x %08x)\n",
+ name, iargs[i], j, res, flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+}
+#endif // #ifdef __powerpc64__
+
+
+typedef struct special_t special_t;
+
+struct special_t {
+ const char *name;
+ void (*test_cb)(const char* name, test_func_t func,
+ unused uint32_t test_flags);
+};
+
+static void test_special (special_t *table,
+ const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ const char *tmp;
+ int i;
+
+ for (tmp = name; isspace(*tmp); tmp++)
+ continue;
+ for (i=0; table[i].name != NULL; i++) {
+#if 0
+ fprintf(stderr, "look for handler for '%s' (%s)\n", name,
+ table[i].name);
+#endif
+ if (strcmp(table[i].name, tmp) == 0) {
+ (*table[i].test_cb)(name, func, test_flags);
+ return;
+ }
+ }
+ fprintf(stderr, "ERROR: no test found for op '%s'\n", name);
+}
+
+static special_t special_int_ops[] = {
+ {
+ "rlwimi", /* One register + 3 5 bits immediate arguments */
+ &rlwi_cb,
+ },
+ {
+ "rlwimi.", /* One register + 3 5 bits immediate arguments */
+ &rlwi_cb,
+ },
+ {
+ "rlwinm", /* One register + 3 5 bits immediate arguments */
+ &rlwi_cb,
+ },
+ {
+ "rlwinm.", /* One register + 3 5 bits immediate arguments */
+ &rlwi_cb,
+ },
+ {
+ "rlwnm", /* Two registers + 2 5 bits immediate arguments */
+ &rlwnm_cb,
+ },
+ {
+ "rlwnm.", /* Two registers + 2 5 bits immediate arguments */
+ &rlwnm_cb,
+ },
+ {
+ "srawi", /* One register + 1 5 bits immediate arguments */
+ &srawi_cb,
+ },
+ {
+ "srawi.", /* One register + 1 5 bits immediate arguments */
+ &srawi_cb,
+ },
+ {
+ "mcrf", /* 2 3 bits immediate arguments */
+ &mcrf_cb,
+ },
+#if 0
+ {
+ "mcrfs", /* 2 3 bits immediate arguments */
+ &mcrfs_cb,
+ },
+#endif
+ {
+ "mcrxr", /* 1 3 bits immediate argument */
+ &mcrxr_cb,
+ },
+ {
+ "mfcr", /* No arguments */
+ &mfcr_cb,
+ },
+ {
+ "mfspr", /* 1 10 bits immediate argument */
+ &mfspr_cb,
+ },
+#if 0
+ { // Move from time base
+ "mftb", /* 1 10 bits immediate arguments */
+ &mftb_cb,
+ },
+#endif
+ {
+ "mtcrf", /* One register + 1 8 bits immediate arguments */
+ &mtcrf_cb,
+ },
+ {
+ "mtspr", /* One register + 1 10 bits immediate arguments */
+ &mtspr_cb,
+ },
+#ifdef __powerpc64__
+ {
+ "rldcl", /* Two registers + 1 6 bit immediate argument */
+ &rldc_cb,
+ },
+ {
+ "rldcl.", /* Two registers + 1 6 bit immediate argument */
+ &rldc_cb,
+ },
+ {
+ "rldcr", /* Two registers + 1 6 bit immediate argument */
+ &rldc_cb,
+ },
+ {
+ "rldcr.", /* Two registers + 1 6 bit immediate argument */
+ &rldc_cb,
+ },
+ {
+ "rldic", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "rldic.", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "rldicl", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "rldicl.", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "rldicr", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "rldicr.", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "rldimi", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "rldimi.", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "sradi", /* One register + 1 6 bit immediate argument */
+ &sradi_cb,
+ },
+ {
+ "sradi.", /* One register + 1 6 bit immediate argument */
+ &sradi_cb,
+ },
+#endif // #ifdef __powerpc64__
+ {
+ NULL,
+ NULL,
+ },
+};
+
+static void test_int_special (const char* name, test_func_t func,
+ uint32_t test_flags)
+{
+ test_special(special_int_ops, name, func, test_flags);
+}
+
+
+static void test_int_ld_one_reg_imm16 (const char* name,
+ test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile HWord_t res, base;
+ volatile uint32_t flags, xer;
+ int i, offs, shift_offset = 0;
+
+#ifdef __powerpc64__
+ if (strstr(name, "lwa") || strstr(name, "ld") || strstr(name, "ldu"))
+ shift_offset = 1;
+#endif
+
+ // +ve d
+ base = (HWord_t)&iargs[0];
+ for (i=0; i<nb_iargs; i++) {
+ offs = (i == 0) ? i : (i * sizeof(HWord_t)) - 1;
+
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ if (shift_offset)
+ patch_op_imm(&func_buf[0], offs>>2, 2, 14);
+ else
+ patch_op_imm16(&func_buf[0], offs);
+
+ r14 = base;
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = r17;
+
+#ifndef __powerpc64__
+ printf("%s %2d, (%08x) => %08x, %2d (%08x %08x)\n",
+#else
+ printf("%s %3d, (%016llx) => %016llx, %3lld (%08x %08x)\n",
+#endif
+ name, offs, iargs[i], res, r14-base, flags, xer);
+ }
+ if (verbose) printf("\n");
+
+ // -ve d
+ base = (HWord_t)&iargs[nb_iargs-1];
+ for (i = 0; i > -nb_iargs; i--) {
+ offs = (i * sizeof(HWord_t)) + 1;
+
+ /* Patch up the instruction */
+ func = init_function( func, func_buf );
+ patch_op_imm16(&func_buf[0], offs);
+
+ r14 = base;
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = r17;
+
+#ifndef __powerpc64__
+ printf("%s %2d, (%08x) => %08x, %2d (%08x %08x)\n",
+#else
+ printf("%s %3d, (%016llx) => %016llx, %3lld (%08x %08x)\n",
+#endif
+ name, offs, iargs[nb_iargs-1 + i], res, r14-base, flags, xer);
+ }
+}
+
+static void test_int_ld_two_regs (const char* name,
+ test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile HWord_t res, base;
+ volatile uint32_t flags, xer;
+ int i, offs;
+
+ // +ve d
+ base = (HWord_t)&iargs[0];
+ for (i=0; i<nb_iargs; i++) {
+ offs = i * sizeof(HWord_t);
+ r14 = base;
+ r15 = offs;
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = r17;
+
+#ifndef __powerpc64__
+ printf("%s %d (%08x) => %08x, %d (%08x %08x)\n",
+#else
+ printf("%s %3d, (%016llx) => %016llx, %2lld (%08x %08x)\n",
+#endif
+ name, offs, iargs[i], res, r14-base, flags, xer);
+ }
+}
+
+static void test_int_st_two_regs_imm16 (const char* name,
+ test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile uint32_t flags, xer;
+ int i, offs, k;
+ HWord_t *iargs_priv, base;
+
+ // private iargs table to store to
+ iargs_priv = malloc(nb_iargs * sizeof(HWord_t));
+
+ // +ve d
+ base = (HWord_t)&iargs_priv[0];
+ for (i=0; i<nb_iargs; i++) {
+ for (k=0; k<nb_iargs; k++) // clear array
+ iargs_priv[k] = 0;
+
+ offs = i * sizeof(HWord_t);
+
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ patch_op_imm16(&func_buf[0], offs);
+
+ r14 = iargs[i]; // read from iargs
+ r15 = base; // store to r15 + offs
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+
+#ifndef __powerpc64__
+ printf("%s %08x, %2d => %08x, %2d (%08x %08x)\n",
+#else
+ printf("%s %016llx, %3d => %016llx, %3lld (%08x %08x)\n",
+#endif
+ name, iargs[i], offs, iargs_priv[i], r15-base, flags, xer);
+ }
+ if (verbose) printf("\n");
+
+ // -ve d
+ base = (HWord_t)&iargs_priv[nb_iargs-1];
+ for (i = -nb_iargs+1; i<=0; i++) {
+ for (k=0; k<nb_iargs; k++) // clear array
+ iargs_priv[k] = 0;
+
+ offs = i * sizeof(HWord_t);
+
+ /* Patch up the instruction */
+ func = init_function( func, func_buf );
+ patch_op_imm16(&func_buf[0], offs);
+
+ r14 = iargs[nb_iargs-1+i]; // read from iargs
+ r15 = base; // store to r15 + offs
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+
+#ifndef __powerpc64__
+ printf("%s %08x, %2d => %08x, %2d (%08x %08x)\n",
+#else
+ printf("%s %016llx, %3d => %016llx, %3lld (%08x %08x)\n",
+#endif
+ name, iargs[nb_iargs-1+i], offs, iargs_priv[nb_iargs-1+i],
+ r15-base, flags, xer);
+ }
+ free(iargs_priv);
+}
+
+static void test_int_st_three_regs (const char* name,
+ test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile uint32_t flags, xer;
+ int i, offs, k;
+ HWord_t *iargs_priv, base;
+
+ // private iargs table to store to
+ iargs_priv = malloc(nb_iargs * sizeof(HWord_t));
+
+ base = (HWord_t)&iargs_priv[0];
+ for (i=0; i<nb_iargs; i++) {
+ for (k=0; k<nb_iargs; k++) // clear array
+ iargs_priv[k] = 0;
+
+ offs = i * sizeof(HWord_t);
+ r14 = iargs[i]; // read from iargs
+ r15 = base; // store to r15 + offs
+ r16 = offs;
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+
+#ifndef __powerpc64__
+ printf("%s %08x, %d => %08x, %d (%08x %08x)\n",
+#else
+ printf("%s %016llx, %3d => %016llx, %2lld (%08x %08x)\n",
+#endif
+ name, iargs[i], offs, iargs_priv[i], r15-base, flags, xer);
+ }
+ free(iargs_priv);
+}
+
+
+/* Used in do_tests, indexed by flags->nb_args
+ Elements correspond to enum test_flags::num args
+*/
+static test_loop_t int_loops[] = {
+ &test_int_one_arg,
+ &test_int_two_args,
+ &test_int_three_args,
+ &test_int_two_args,
+ &test_int_one_reg_imm16,
+ &test_int_one_reg_imm16,
+ &test_int_special,
+ &test_int_ld_one_reg_imm16,
+ &test_int_ld_two_regs,
+ &test_int_st_two_regs_imm16,
+ &test_int_st_three_regs,
+};
+
+static void test_dcbt_ops (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ unsigned long * data = (unsigned long *)malloc(4096 * sizeof(unsigned long));
+ HWord_t base;
+
+ base = (HWord_t)data;
+ size_t offs = 100 * sizeof(unsigned long); // some arbitrary offset)
+
+ r17 = base;
+ r14 = offs;
+
+ (*func)();
+
+ printf("%s with various hint values completes with no exceptions\n", name);
+ free(data);
+}
+
+static test_loop_t misc_loops[] = {
+ &test_dcbt_ops,
+};
+
+#if !defined (NO_FLOAT)
+static void test_float_three_args (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ double res;
+ uint64_t u0, u1, u2, ur;
+ volatile uint32_t flags;
+ int i, j, k;
+
+ /* Note: using nb_normal_fargs:
+ - not testing special values for these insns
+ */
+ for (i=0; i<nb_normal_fargs; i+=3) {
+ for (j=0; j<nb_normal_fargs; j+=5) {
+ for (k=0; k<nb_normal_fargs; k+=7) {
+ u0 = *(uint64_t *)(&fargs[i]);
+ u1 = *(uint64_t *)(&fargs[j]);
+ u2 = *(uint64_t *)(&fargs[k]);
+ f14 = fargs[i];
+ f15 = fargs[j];
+ f16 = fargs[k];
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ res = f17;
+ ur = *(uint64_t *)(&res);
+
+ /* Note: zapping the bottom byte of the result,
+ as vex's accuracy isn't perfect */
+ ur &= 0xFFFFFFFFFFFFFF00ULL;
+
+#ifndef __powerpc64__
+ printf("%s %016llx, %016llx, %016llx => %016llx",
+#else
+ printf("%s %016llx, %016llx, %016llx => %016llx",
+#endif
+ name, u0, u1, u2, ur);
+#if defined TEST_FLOAT_FLAGS
+ printf(" (%08x)", flags);
+#endif
+ printf("\n");
+ }
+ if (verbose) printf("\n");
+ }
+ }
+}
+
+static void test_float_two_args (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ double res;
+ uint64_t u0, u1, ur;
+ volatile uint32_t flags;
+ int i, j;
+
+ for (i=0; i<nb_fargs; i+=3) {
+ for (j=0; j<nb_fargs; j+=5) {
+ u0 = *(uint64_t *)(&fargs[i]);
+ u1 = *(uint64_t *)(&fargs[j]);
+ f14 = fargs[i];
+ f15 = fargs[j];
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ res = f17;
+ ur = *(uint64_t *)(&res);
+
+#ifndef __powerpc64__
+ printf("%s %016llx, %016llx => %016llx",
+#else
+ printf("%s %016llx, %016llx => %016llx",
+#endif
+ name, u0, u1, ur);
+#if defined TEST_FLOAT_FLAGS
+ printf(" (%08x)", flags);
+#endif
+ printf("\n");
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+static void test_float_one_arg (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ double res;
+ uint64_t u0, ur;
+ volatile uint32_t flags;
+ int i;
+ unsigned zap_hi_32bits, zap_lo_44bits, zap_lo_47bits;
+
+ /* if we're testing fctiw or fctiwz, zap the hi 32bits,
+ as they're undefined */
+ zap_hi_32bits = strstr(name, " fctiw") != NULL ? 1 : 0;
+ zap_lo_44bits = strstr(name, " fres") != NULL ? 1 : 0;
+ zap_lo_47bits = strstr(name, " frsqrte") != NULL ? 1 : 0;
+
+ assert(zap_hi_32bits + zap_lo_44bits + zap_lo_47bits <= 1);
+
+ for (i=0; i<nb_fargs; i++) {
+ u0 = *(uint64_t *)(&fargs[i]);
+ f14 = fargs[i];
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ res = f17;
+ ur = *(uint64_t *)(&res);
+
+ if (strstr(name, " frsqrte") != NULL)
+ /* The 32-bit frsqrte instruction is the Floatig Reciprical Square
+ * Root Estimate instruction. The precision of the estimate will
+ * vary from Proceesor implementation. The approximation varies in
+ * bottom two bytes of the 32-bit result.
+ */
+ ur &= 0xFFFF000000000000ULL;
+
+ if (zap_hi_32bits)
+ ur &= 0x00000000FFFFFFFFULL;
+ if (zap_lo_44bits)
+ ur &= 0xFFFFF00000000000ULL;
+ if (zap_lo_47bits)
+ ur &= 0xFFFF800000000000ULL;
+
+#ifndef __powerpc64__
+ printf("%s %016llx => %016llx",
+#else
+ printf("%s %016llx => %016llx",
+#endif
+ name, u0, ur);
+#if defined TEST_FLOAT_FLAGS
+ printf(" (%08x)", flags);
+#endif
+ printf("\n");
+ }
+}
+
+/* Special test cases for:
+ * mffs
+ * mtfsb0
+ * mtfsb1
+ */
+static special_t special_float_ops[] = {
+#if 0
+ {
+ "mffs", /* One 5 bits immediate argument */
+ &mffs_cb,
+ },
+ {
+ "mffs.", /* One 5 bits immediate argument */
+ &mffs_cb,
+ },
+ {
+ "mtfsb0", /* One 5 bits immediate argument */
+ &mffs_cb,
+ },
+ {
+ "mtfsb0.", /* One 5 bits immediate argument */
+ &mffs_cb,
+ },
+ {
+ "mtfsb1", /* One 5 bits immediate argument */
+ &mffs_cb,
+ },
+ {
+ "mtfsb1.", /* One 5 bits immediate argument */
+ &mffs_cb,
+ },
+ {
+ "mtfsf", /* One register + 1 8 bits immediate argument */
+ &mtfsf_cb,
+ },
+ {
+ "mtfsf.", /* One register + 1 8 bits immediate argument */
+ &mtfsf_cb,
+ },
+ {
+ "mtfsfi", /* One 5 bits argument + 1 5 bits argument */
+ &mtfsfi_cb,
+ },
+ {
+ "mtfsfi.", /* One 5 bits argument + 1 5 bits argument */
+ &mtfsfi_cb,
+ },
+#endif
+ {
+ NULL,
+ NULL,
+ },
+};
+
+static void test_float_special (const char* name, test_func_t func,
+ uint32_t test_flags)
+{
+ test_special(special_float_ops, name, func, test_flags);
+}
+
+
+static void test_float_ld_one_reg_imm16 (const char* name,
+ test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ HWord_t base;
+ volatile uint32_t flags, xer;
+ volatile double src, res;
+ int i;
+ uint16_t offs;
+
+ /* offset within [1-nb_fargs:nb_fargs] */
+ for (i=1-nb_fargs; i<nb_fargs; i++) {
+ offs = i * 8; // offset = i * sizeof(double)
+ if (i < 0) {
+ src = fargs[nb_fargs-1 + i];
+ base = (HWord_t)&fargs[nb_fargs-1];
+ } else {
+ src = fargs[i];
+ base = (HWord_t)&fargs[0];
+ }
+
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ patch_op_imm16(&func_buf[0], offs);
+
+ // load from fargs[idx] => r14 + offs
+ r14 = base;
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = f17;
+
+#ifndef __powerpc64__
+ printf("%s %016llx, %4d => %016llx, %4d",
+#else
+ printf("%s %016llx, %4d => %016llx, %4lld",
+#endif
+ name, double_to_bits(src), offs,
+ double_to_bits(res), r14-base);
+#if defined TEST_FLOAT_FLAGS
+ printf(" (%08x %08x)", flags, xer);
+#endif
+ printf("\n");
+ }
+ if (verbose) printf("\n");
+}
+
+static void test_float_ld_two_regs (const char* name,
+ test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile HWord_t base;
+ volatile uint32_t flags, xer;
+ volatile double src, res;
+ int i, offs;
+
+ /* offset within [1-nb_fargs:nb_fargs] */
+ for (i=1-nb_fargs; i<nb_fargs; i++) {
+ offs = i * 8; // offset = i * sizeof(double)
+ if (i < 0) { // base reg = start of array
+ src = fargs[nb_fargs-1 + i];
+ base = (HWord_t)&fargs[nb_fargs-1];
+ } else {
+ src = fargs[i];
+ base = (HWord_t)&fargs[0];
+ }
+
+ r14 = base;
+ r15 = offs;
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+ res = f17;
+
+#ifndef __powerpc64__
+ printf("%s %016llx, %4d => %016llx, %4d",
+#else
+ printf("%s %016llx, %4lld => %016llx, %4lld",
+#endif
+ name, double_to_bits(src), r15/*offs*/,
+ double_to_bits(res), r14-base);
+#if defined TEST_FLOAT_FLAGS
+ printf(" (%08x %08x)", flags, xer);
+#endif
+ printf("\n");
+ }
+}
+
+static void test_float_st_two_regs_imm16 (const char* name,
+ test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ HWord_t base;
+ volatile uint32_t flags, xer;
+ double src, *p_dst;
+ int i, offs;
+ double *fargs_priv;
+ int nb_tmp_fargs = nb_fargs;
+
+
+ /* if we're storing an fp single-precision, don't want nans
+ - the vex implementation doesn't like them (yet)
+ Note: This is actually a bigger problem: the vex implementation
+ rounds these insns twice. This leads to many rounding errors.
+ For the small fargs set, however, this doesn't show up.
+ */
+ if (strstr(name, "stfs") != NULL)
+ nb_tmp_fargs = nb_normal_fargs;
+
+
+ // private fargs table to store to
+ fargs_priv = malloc(nb_tmp_fargs * sizeof(double));
+
+ /* offset within [1-nb_tmp_fargs:nb_tmp_fargs] */
+ for (i=1-nb_tmp_fargs; i<nb_tmp_fargs; i++) {
+ offs = i * 8; // offset = i * sizeof(double)
+ if (i < 0) {
+ src = fargs [nb_tmp_fargs-1 + i];
+ p_dst = &fargs_priv[nb_tmp_fargs-1 + i];
+ base = (HWord_t)&fargs_priv[nb_tmp_fargs-1];
+ } else {
+ src = fargs [i];
+ p_dst = &fargs_priv[i];
+ base = (HWord_t)&fargs_priv[0];
+ }
+ *p_dst = 0; // clear dst
+
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ patch_op_imm16(&func_buf[0], offs);
+
+ // read from fargs[idx] => f14
+ // store to fargs_priv[idx] => r15 + offs
+ f14 = src;
+ r15 = base;
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+
+#ifndef __powerpc64__
+ printf("%s %016llx, %4d => %016llx, %4d",
+#else
+ printf("%s %016llx, %4d => %016llx, %4lld",
+#endif
+ name, double_to_bits(src), offs,
+ double_to_bits(*p_dst), r15-base);
+#if defined TEST_FLOAT_FLAGS
+ printf(" (%08x %08x)", flags, xer);
+#endif
+ printf("\n");
+ }
+ free(fargs_priv);
+}
+
+static void test_float_st_three_regs (const char* name,
+ test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile HWord_t base;
+ volatile uint32_t flags, xer;
+ double src, *p_dst;
+ int i, offs;
+ double *fargs_priv;
+ int nb_tmp_fargs = nb_fargs;
+
+
+ /* if we're storing an fp single-precision, don't want nans
+ - the vex implementation doesn't like them (yet)
+ Note: This is actually a bigger problem: the vex implementation
+ rounds these insns twice. This leads to many rounding errors.
+ For the small fargs set, however, this doesn't show up.
+ */
+ if (strstr(name, "stfs") != NULL) // stfs(u)(x)
+ nb_tmp_fargs = nb_normal_fargs;
+
+
+ // private fargs table to store to
+ fargs_priv = malloc(nb_tmp_fargs * sizeof(double));
+
+ // /* offset within [1-nb_tmp_fargs:nb_tmp_fargs] */
+ // for (i=1-nb_tmp_fargs; i<nb_tmp_fargs; i++) {
+ for (i=0; i<nb_tmp_fargs; i++) {
+ offs = i * 8; // offset = i * sizeof(double)
+ if (i < 0) {
+ src = fargs [nb_tmp_fargs-1 + i];
+ p_dst = &fargs_priv[nb_tmp_fargs-1 + i];
+ base = (HWord_t)&fargs_priv[nb_tmp_fargs-1];
+ } else {
+ src = fargs [i];
+ p_dst = &fargs_priv[i];
+ base = (HWord_t)&fargs_priv[0];
+ }
+ *p_dst = 0; // clear dst
+
+ f14 = src; // read from fargs
+ r15 = base; // store to r15 + offs
+ r16 = offs;
+
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR_XER(flags,xer);
+
+#ifndef __powerpc64__
+ printf("%s %016llx, %4d => %016llx, %4d",
+#else
+ printf("%s %016llx, %4lld => %016llx, %4lld",
+#endif
+ name, double_to_bits(src), r16/*offs*/,
+ double_to_bits(*p_dst), r15-base);
+#if defined TEST_FLOAT_FLAGS
+ printf(" (%08x %08x)", flags, xer);
+#endif
+ printf("\n");
+
+
+#if 0
+ // print double precision result
+#ifndef __powerpc64__
+ printf("%s %016llx (%014e), %4d => %016llx (%014e), %08x (%08x %08x)\n",
+#else
+ printf("%s %016llx (%014e), %4d => %016llx (%014e), %08x (%08x %08x)\n",
+#endif
+ name, double_to_bits(src), src, offs,
+ double_to_bits(*p_dst), *p_dst, r15, flags, xer);
+
+ // print single precision result
+#ifndef __powerpc64__
+ printf("%s %016llx (%014e), %4d => %08x (%f), %08x (%08x %08x)\n",
+#else
+ printf("%s %016llx (%014e), %4d => %08x (%f), %08x (%08x %08x)\n",
+#endif
+ name, double_to_bits(src), src, offs,
+ (uint32_t)(double_to_bits(*p_dst) >> 32),
+ bits_to_float( (uint32_t)(double_to_bits(*p_dst) >> 32) ),
+ r15, flags, xer);
+#endif
+ }
+ free(fargs_priv);
+}
+
+
+/* Used in do_tests, indexed by flags->nb_args
+ Elements correspond to enum test_flags::num args
+*/
+static test_loop_t float_loops[] = {
+ &test_float_one_arg,
+ &test_float_two_args,
+ &test_float_three_args,
+ &test_float_two_args,
+ NULL,
+ NULL,
+ &test_float_special,
+ &test_float_ld_one_reg_imm16,
+ &test_float_ld_two_regs,
+ &test_float_st_two_regs_imm16,
+ &test_float_st_three_regs,
+};
+#endif /* !defined (NO_FLOAT) */
+
+
+#if defined (HAS_ALTIVEC)
+
+/* Ref: vector insns to test setting CR, VSCR:
+ volatile vector unsigned int v1 =
+ // (vector unsigned int){ 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF };
+ (vector unsigned int){ 0x80808080,0x80808080,0x80808080,0x80808080 };
+ volatile vector unsigned int v2 =
+ // (vector unsigned int){ 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF };
+ (vector unsigned int){ 0x01010101,0x01010101,0x01010101,0x01010101 };
+ //__asm__ __volatile__ ("vcmpequw. 31,%0,%1" : : "v" (v1), "v" (v2)); // sets CR[6]
+ //__asm__ __volatile__ ("vpkswss 31,%0,%1" : : "v" (v1), "v" (v2)); // sets VSCR[SAT]
+ __asm__ __volatile__ ("vsubsbs 31,%0,%1" : : "v" (v1), "v" (v2)); // sets VSCR[SAT]
+*/
+
+//#define DEFAULT_VSCR 0x00010000
+#define DEFAULT_VSCR 0x0
+
+static void test_av_int_one_arg (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector unsigned int vec_in, vec_out, vscr;
+ unsigned int *src, *dst;
+ int i;
+#if defined TEST_VSCR_SAT
+ unsigned int* p_vscr;
+#endif
+
+ for (i=0; i<nb_viargs; i++) {
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
+
+ vec_in = (vector unsigned int)viargs[i];
+ vec_out = (vector unsigned int){ 0,0,0,0 };
+
+ // reset VSCR and CR
+ vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+ flags = 0;
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
+ __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
+
+ // load input -> r14
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in));
+
+ // do stuff
+ (*func)();
+
+ // retrieve output <- r17
+ __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
+
+ // get CR,VSCR flags
+ __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
+
+ /* Restore flags */
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+ src = (unsigned int*)&vec_in;
+ dst = (unsigned int*)&vec_out;
+
+ printf("%s: %08x %08x %08x %08x\n", name,
+ src[0], src[1], src[2], src[3]);
+ printf("%s: => %08x %08x %08x %08x ", name,
+ dst[0], dst[1], dst[2], dst[3]);
+#if defined TEST_VSCR_SAT
+ p_vscr = (unsigned int*)𝓋
+ printf("(%08x, %08x)\n", flags, p_vscr[3]);
+#else
+ printf("(%08x)\n", flags);
+#endif
+ }
+}
+
+static void test_av_int_two_args (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector unsigned int vec_in1, vec_in2, vec_out, vscr;
+ unsigned int *src1, *src2, *dst;
+ int i,j;
+#if defined TEST_VSCR_SAT
+ unsigned int* p_vscr;
+#endif
+
+ for (i=0; i<nb_viargs; i++) {
+ vec_in1 = (vector unsigned int)viargs[i];
+ for (j=0; j<nb_viargs; j++) {
+ vec_in2 = (vector unsigned int)viargs[j];
+ vec_out = (vector unsigned int){ 0,0,0,0 };
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
+
+ // reset VSCR and CR
+ vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+ flags = 0;
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
+ __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
+
+ // load inputs -> r14,r15
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
+ __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
+
+ // do stuff
+ (*func)();
+
+ // retrieve output <- r17
+ __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
+
+ // get CR,VSCR flags
+ __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
+
+ /* Restore flags */
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+ src1 = (unsigned int*)&vec_in1;
+ src2 = (unsigned int*)&vec_in2;
+ dst = (unsigned int*)&vec_out;
+
+ printf("%s: ", name);
+ printf("%08x%08x%08x%08x, ", src1[0], src1[1], src1[2], src1[3]);
+ printf("%08x%08x%08x%08x\n", src2[0], src2[1], src2[2], src2[3]);
+ printf("%s: => %08x %08x %08x %08x ", name,
+ dst[0], dst[1], dst[2], dst[3]);
+#if defined TEST_VSCR_SAT
+ p_vscr = (unsigned int*)𝓋
+ printf("(%08x, %08x)\n", flags, p_vscr[3]);
+#else
+ printf("(%08x)\n", flags);
+#endif
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+static void test_av_int_three_args (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector unsigned int vec_in1, vec_in2, vec_in3, vec_out, vscr;
+ unsigned int *src1, *src2, *src3, *dst;
+ int i,j,k;
+#if defined TEST_VSCR_SAT
+ unsigned int* p_vscr;
+#endif
+
+ for (i=0; i<nb_viargs; i++) {
+ vec_in1 = (vector unsigned int)viargs[i];
+ for (j=0; j<nb_viargs; j++) {
+ vec_in2 = (vector unsigned int)viargs[j];
+ for (k=0; k<nb_viargs; k++) {
+ vec_in3 = (vector unsigned int)viargs[k];
+ vec_out = (vector unsigned int){ 0,0,0,0 };
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
+
+ // reset VSCR and CR
+ vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+ flags = 0;
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
+ __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
+
+ // load inputs -> r14,r15,r16
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
+ __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
+ __asm__ __volatile__ ("vor 16,%0,%0" : : "v" (vec_in3));
+
+ // do stuff
+ (*func)();
+
+ // retrieve output <- r17
+ __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
+
+ // get CR,VSCR flags
+ __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
+
+ /* Restore flags */
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+ src1 = (unsigned int*)&vec_in1;
+ src2 = (unsigned int*)&vec_in2;
+ src3 = (unsigned int*)&vec_in3;
+ dst = (unsigned int*)&vec_out;
+
+ printf("%s: %08x%08x%08x%08x, %08x%08x%08x%08x, %08x%08x%08x%08x\n", name,
+ src1[0], src1[1], src1[2], src1[3],
+ src2[0], src2[1], src2[2], src2[3],
+ src3[0], src3[1], src3[2], src3[3]);
+
+ printf("%s: => %08x%08x%08x%08x ", name,
+ dst[0], dst[1], dst[2], dst[3]);
+#if defined TEST_VSCR_SAT
+ p_vscr = (unsigned int*)𝓋
+ printf("(%08x, %08x)\n", flags, p_vscr[3]);
+#else
+ printf("(%08x)\n", flags);
+#endif
+ }
+ if (verbose) printf("\n");
+ }
+ }
+}
+
+
+static void vs128_cb (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector unsigned char vec_shft;
+ volatile vector unsigned int vec_in1, vec_out, vscr;
+ unsigned int *src1, *src2, *dst;
+ int i,j;
+#if defined TEST_VSCR_SAT
+ unsigned int* p_vscr;
+#endif
+
+ for (i=0; i<nb_viargs; i++) {
+ vec_in1 = (vector unsigned int)viargs[i];
+ for (j=0; j<8; j++) {
+ /* low-order 3bits of every byte must be the same for the shift vector */
+ vec_shft = (vector unsigned char) { j,j,j,j, j,j,j,j, j,j,j,j, j,j,j,j };
+ vec_out = (vector unsigned int){ 0,0,0,0 };
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
+
+ // reset VSCR and CR
+ vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+ flags = 0;
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
+ __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
+
+ // load inputs -> r14,r15
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
+ __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_shft));
+
+ // do stuff
+ (*func)();
+
+ // retrieve output <- r17
+ __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
+
+ // get CR,VSCR flags
+ __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
+
+ /* Restore flags */
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+ src1 = (unsigned int*)&vec_in1;
+ src2 = (unsigned int*)&vec_shft;
+ dst = (unsigned int*)&vec_out;
+
+ printf("%s: ", name);
+ printf("%08x%08x%08x%08x, ", src1[0], src1[1], src1[2], src1[3]);
+ printf("%08x%08x%08x%08x\n", src2[0], src2[1], src2[2], src2[3]);
+
+ printf("%s: => %08x %08x %08x %08x ", name,
+ dst[0], dst[1], dst[2], dst[3]);
+#if defined TEST_VSCR_SAT
+ p_vscr = (unsigned int*)𝓋
+ printf("(%08x, %08x)\n", flags, p_vscr[3]);
+#else
+ printf("(%08x)\n", flags);
+#endif
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+static void vsplt_cb (const char* name, test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector unsigned int vec_in1, vec_out, vscr;
+ unsigned int *src1, *dst;
+ int i,j;
+#if defined TEST_VSCR_SAT
+ unsigned int* p_vscr;
+#endif
+
+ for (i=0; i<nb_viargs; i++) {
+ vec_in1 = (vector unsigned int)viargs[i];
+
+ for (j=0; j<16; j+=3) {
+ vec_out = (vector unsigned int){ 0,0,0,0 };
+
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ patch_op_imm(&func_buf[0], j, 16, 5);
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
+
+ // reset VSCR and CR
+ vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+ flags = 0;
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
+ __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
+
+ // load input -> r14
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
+
+ // do stuff
+ (*func)();
+
+ // retrieve output <- r17
+ __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
+
+ // get CR,VSCR flags
+ __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
+
+ /* Restore flags */
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+ src1 = (unsigned int*)&vec_in1;
+ dst = (unsigned int*)&vec_out;
+
+ printf("%s: ", name);
+ printf("%08x %08x %08x %08x, %u\n", src1[0], src1[1], src1[2], src1[3], j);
+
+ printf("%s: => %08x %08x %08x %08x ", name,
+ dst[0], dst[1], dst[2], dst[3]);
+#if defined TEST_VSCR_SAT
+ p_vscr = (unsigned int*)𝓋
+ printf("(%08x, %08x)\n", flags, p_vscr[3]);
+#else
+ printf("(%08x)\n", flags);
+#endif
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+static void vspltis_cb (const char* name, test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector unsigned int vec_out, vscr;
+ unsigned int *dst;
+ int i;
+#if defined TEST_VSCR_SAT
+ unsigned int* p_vscr;
+#endif
+
+ for (i=0; i<32; i++) {
+ vec_out = (vector unsigned int){ 0,0,0,0 };
+
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ patch_op_imm(&func_buf[0], i, 16, 5);
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
+
+ // reset VSCR and CR
+ vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+ flags = 0;
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
+ __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
+
+ // do stuff
+ (*func)();
+
+ // retrieve output <- r17
+ __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
+
+ // get CR,VSCR flags
+ __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
+
+ /* Restore flags */
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+ dst = (unsigned int*)&vec_out;
+
+ printf("%s: %2d => ", name, i);
+ printf("%08x %08x %08x %08x ", dst[0], dst[1], dst[2], dst[3]);
+#if defined TEST_VSCR_SAT
+ p_vscr = (unsigned int*)𝓋
+ printf("(%08x, %08x)\n", flags, p_vscr[3]);
+#else
+ printf("(%08x)\n", flags);
+#endif
+ }
+}
+
+static void vsldoi_cb (const char* name, test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector unsigned int vec_in1, vec_in2, vec_out, vscr;
+ unsigned int *src1, *src2, *dst;
+ int i,j,k;
+#if defined TEST_VSCR_SAT
+ unsigned int* p_vscr;
+#endif
+
+ for (i=0; i<nb_viargs; i++) {
+ vec_in1 = (vector unsigned int)viargs[i];
+ for (j=0; j<nb_viargs; j++) {
+ vec_in2 = (vector unsigned int)viargs[j];
+ for (k=0; k<16; k+=14) {
+ vec_out = (vector unsigned int){ 0,0,0,0 };
+
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ patch_op_imm(&func_buf[0], k, 6, 4);
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
+
+ // reset VSCR and CR
+ vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+ flags = 0;
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
+ __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
+
+ // load inputs -> r14,r15
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
+ __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
+
+ // do stuff
+ (*func)();
+
+ // retrieve output <- r17
+ __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
+
+ // get CR,VSCR flags
+ __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
+
+ /* Restore flags */
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+ src1 = (unsigned int*)&vec_in1;
+ src2 = (unsigned int*)&vec_in2;
+ dst = (unsigned int*)&vec_out;
+
+ printf("%s: ", name);
+ printf("%08x%08x%08x%08x, %08x%08x%08x%08x, %u\n",
+ src1[0], src1[1], src1[2], src1[3],
+ src2[0], src2[1], src2[2], src2[3], k);
+
+ printf("%s: => %08x %08x %08x %08x] ", name,
+ dst[0], dst[1], dst[2], dst[3]);
+#if defined TEST_VSCR_SAT
+ p_vscr = (unsigned int*)𝓋
+ printf("(%08x, %08x)\n", flags, p_vscr[3]);
+#else
+ printf("(%08x)\n", flags);
+#endif
+ }
+ if (verbose) printf("\n");
+ }
+ }
+}
+
+/* lvsl, lvsr */
+static void lvs_cb (const char *name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector unsigned int vec_out, vscr;
+ unsigned shift;
+ unsigned char * dst;
+ int i, j;
+#if defined TEST_VSCR_SAT
+ unsigned int* p_vscr;
+#endif
+
+ for (i=-1; i<17; i++) {
+ vec_out = (vector unsigned int){ 0,0,0,0 };
+
+ // make sure start address is 16 aligned - use viargs[0]
+ HWord_t * r15_in_ptr = (HWord_t *)&viargs[0];
+ r15 = *r15_in_ptr;
+ r14 = i;
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
+
+ // reset VSCR and CR
+ vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+ flags = 0;
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
+ __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
+
+ // do stuff
+ (*func)();
+
+ // retrieve output <- r17
+ __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
+
+ // get CR,VSCR flags
+ __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
+
+ /* Restore flags */
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+ dst = (unsigned char*)&vec_out;
+
+ shift = ((unsigned int)i + *r15_in_ptr) & 0xf;
+ printf("%s %x, %3d", name, shift, 0);
+ printf(" => 0x");
+ for (j = 0; j < 16; j++) {
+ printf("%02x", dst[j]);
+ if (j == 7)
+ printf(" 0x");
+ }
+
+ printf(" (%08x)\n", flags);
+ }
+ if (verbose) printf("\n");
+}
+
+static special_t special_av_int_ops[] = {
+ {
+ "vsr", /* Two registers arguments */
+ &vs128_cb,
+ },
+ {
+ "vsl", /* Two registers arguments */
+ &vs128_cb,
+ },
+ {
+ "vspltb", /* One reg, one 5-bit uimm arguments */
+ &vsplt_cb,
+ },
+ {
+ "vsplth", /* One reg, one 5-bit uimm arguments */
+ &vsplt_cb,
+ },
+ {
+ "vspltw", /* One reg, one 5-bit uimm arguments */
+ &vsplt_cb,
+ },
+ {
+ "vspltisb", /* One reg, one 5-bit uimm arguments */
+ &vspltis_cb,
+ },
+ {
+ "vspltish", /* One reg, one 5-bit uimm arguments */
+ &vspltis_cb,
+ },
+ {
+ "vspltisw", /* One reg, one 5-bit uimm arguments */
+ &vspltis_cb,
+ },
+ {
+ "vsldoi", /* Two regs, one 4-bit uimm arguments */
+ &vsldoi_cb,
+ },
+ {
+ "lvsl", /* Two regs */
+ &lvs_cb,
+ },
+ {
+ "lvsr", /* Two regs */
+ &lvs_cb,
+ },
+ {
+ NULL,
+ NULL,
+ },
+};
+
+static void test_av_int_special (const char* name, test_func_t func,
+ uint32_t test_flags)
+{
+ test_special(special_av_int_ops, name, func, test_flags);
+}
+
+static void test_av_int_ld_two_regs (const char *name,
+ test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector unsigned int vec_in, vec_out, vscr;
+ unsigned int *src, *dst;
+ int i,j, k, do_mask;
+
+ do_mask = 0;
+ if (strstr(name, "lvebx") != NULL) do_mask = 1;
+ if (strstr(name, "lvehx") != NULL) do_mask = 2;
+ if (strstr(name, "lvewx") != NULL) do_mask = 4;
+
+ for (i=0; i<nb_viargs; i++) {
+ for (j=0; j<16; j+=7) {
+ vec_out = (vector unsigned int){ 0,0,0,0 };
+
+ // load from viargs array + some dis-alignment
+ r15 = (HWord_t)&viargs[0];
+ r14 = i*16 + j;
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
+
+ // reset VSCR and CR
+ vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+ flags = 0;
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
+ __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
+
+ // do stuff
+ (*func)();
+
+ // retrieve output <- r17
+ __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
+
+ // get CR,VSCR flags
+ __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
+
+ /* Restore flags */
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+ vec_in = (vector unsigned int)viargs[i];
+ src = (unsigned int*)&vec_in;
+ dst = (unsigned int*)&vec_out;
+
+ /* For lvebx/lvehx/lvewx, as per the documentation, all of
+ the dest reg except the loaded bits are undefined
+ afterwards. And different CPUs really do produce
+ different results. So mask out bits of the result that
+ are undefined so as to make the test work reliably. */
+ if (do_mask == 1) {
+ char* p = (char*)dst;
+ for (k = 0; k < 16; k++)
+ if (k != j)
+ p[k] = (char)0;
+ }
+ if (do_mask == 2) {
+ short* p = (short*)dst;
+ for (k = 0; k < 8; k++)
+ if (k != (j>>1))
+ p[k] = (short)0;
+ }
+ if (do_mask == 4) {
+ int* p = (int*)dst;
+ for (k = 0; k < 4; k++)
+ if (k != (j>>2))
+ p[k] = (int)0;
+ }
+
+ printf("%s %3d, %08x %08x %08x %08x", name, j, src[0], src[1], src[2], src[3]);
+ printf(" => %08x %08x %08x %08x ", dst[0], dst[1], dst[2], dst[3]);
+ printf("(%08x)\n", flags);
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+
+static void test_av_int_st_three_regs (const char *name,
+ test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector unsigned int vec_in, vec_out, vscr;
+ unsigned int *src, *dst;
+ int i,j;
+ vector unsigned int* viargs_priv;
+
+ // private viargs table to store to
+ viargs_priv = memalign16(nb_viargs * sizeof(vector unsigned int));
+ for (i=0; i<nb_viargs; i++)
+ viargs_priv[i] = (vector unsigned int) { 0,0,0,0 };
+
+ for (i=0; i<nb_viargs; i++) {
+ for (j=0; j<16; j+=7) {
+ // read from viargs
+ vec_in = (vector unsigned int)viargs[i];
+
+ // store to viargs_priv[0] + some dis-alignment
+ r16 = (HWord_t)&viargs_priv[0];
+ r15 = i*16 + j;
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
+
+ // reset VSCR and CR
+ vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+ flags = 0;
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
+ __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
+
+ // load inputs -> r14
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in));
+
+ // do stuff
+ (*func)();
+
+ // Output stored in viargs_priv
+
+ // get CR,VSCR flags
+ __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
+
+ /* Restore flags */
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+ vec_out = (vector unsigned int)viargs_priv[i];
+ src = (unsigned int*)&vec_in;
+ dst = (unsigned int*)&vec_out;
+
+ printf("%s %3d, %08x %08x %08x %08x", name, j, src[0], src[1], src[2], src[3]);
+ printf(" => %08x %08x %08x %08x ", dst[0], dst[1], dst[2], dst[3]);
+ printf("(%08x)\n", flags);
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+/* Used in do_tests, indexed by flags->nb_args
+ Elements correspond to enum test_flags::num args
+*/
+static test_loop_t altivec_int_loops[] = {
+ &test_av_int_one_arg,
+ &test_av_int_two_args,
+ &test_av_int_three_args,
+ &test_av_int_two_args,
+ NULL,
+ NULL,
+ &test_av_int_special,
+ NULL,
+ &test_av_int_ld_two_regs,
+ NULL,
+ test_av_int_st_three_regs,
+};
+
+
+static void test_av_float_one_arg (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector float vec_in, vec_out;
+ volatile vector unsigned int vscr;
+ unsigned int *src, *dst;
+ int i;
+#if defined TEST_VSCR_SAT
+ unsigned int* p_vscr;
+#endif
+
+ /* if we're doing an estimation operation, arrange to zap the
+ bottom 10-bits of the result as it's basically garbage, and differs
+ between cpus */
+ unsigned int mask
+ = (strstr(name,"vrsqrtefp") != NULL ||
+ strstr(name, "vrefp") != NULL)
+ ? 0xFFFFC000 : 0xFFFFFFFF;
+
+ for (i=0; i<nb_vfargs; i++) {
+ vec_in = (vector float)vfargs[i];
+ vec_out = (vector float){ 0.0, 0.0, 0.0, 0.0 };
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
+
+ // reset VSCR and CR
+ vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+ flags = 0;
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
+ __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
+
+ // load input -> r14
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in));
+
+ // do stuff
+ (*func)();
+
+ // retrieve output <- r17
+ __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
+
+ // get CR,VSCR flags
+ __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
+
+ /* Restore flags */
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+ src = (unsigned int*)&vec_in;
+ dst = (unsigned int*)&vec_out;
+
+ printf("%s: %08x %08x %08x %08x\n", name,
+ src[0], src[1], src[2], src[3]);
+ printf("%s: => %08x %08x %08x %08x ", name,
+ dst[0] & mask, dst[1] & mask, dst[2] & mask, dst[3] & mask);
+#if defined TEST_VSCR_SAT
+ p_vscr = (unsigned int*)𝓋
+ printf("(%08x, %08x)\n", flags, p_vscr[3]);
+#else
+ printf("(%08x)\n", flags);
+#endif
+ }
+}
+
+static void test_av_float_two_args (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector float vec_in1, vec_in2, vec_out;
+ volatile vector unsigned int vscr;
+ unsigned int *src1, *src2, *dst;
+ int i,j;
+#if defined TEST_VSCR_SAT
+ unsigned int* p_vscr;
+#endif
+
+ for (i=0; i<nb_vfargs; i++) {
+ for (j=0; j<nb_vfargs; j+=3) {
+ vec_in1 = (vector float)vfargs[i];
+ vec_in2 = (vector float)vfargs[j];
+ vec_out = (vector float){ 0.0, 0.0, 0.0, 0.0 };
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
+
+ // reset VSCR and CR
+ vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+ flags = 0;
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
+ __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
+
+ // load inputs -> r14,r15
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
+ __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
+
+ // do stuff
+ (*func)();
+
+ // retrieve output <- r17
+ __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
+
+ // get CR,VSCR flags
+ __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
+
+ /* Restore flags */
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+ src1 = (unsigned int*)&vec_in1;
+ src2 = (unsigned int*)&vec_in2;
+ dst = (unsigned int*)&vec_out;
+
+ printf("%s: %08x%08x%08x%08x, %08x%08x%08x%08x\n", name,
+ src1[0], src1[1], src1[2], src1[3],
+ src2[0], src2[1], src2[2], src2[3]);
+ printf("%s: => %08x %08x %08x %08x ", name,
+ dst[0], dst[1], dst[2], dst[3]);
+#if defined TEST_VSCR_SAT
+ p_vscr = (unsigned int*)𝓋
+ printf("(%08x, %08x)\n", flags, p_vscr[3]);
+#else
+ printf("(%08x)\n", flags);
+#endif
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+static void test_av_float_three_args (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector float vec_in1, vec_in2, vec_in3, vec_out;
+ volatile vector unsigned int vscr;
+ unsigned int *src1, *src2, *src3, *dst;
+ int i,j,k,n;
+#if defined TEST_VSCR_SAT
+ unsigned int* p_vscr;
+#endif
+
+ for (i=0; i<nb_vfargs; i++) {
+ for (j=0; j<nb_vfargs; j+=3) {
+ for (k=0; k<nb_vfargs; k+=5) {
+ vec_in1 = (vector float)vfargs[i];
+ vec_in2 = (vector float)vfargs[j];
+ vec_in3 = (vector float)vfargs[k];
+ vec_out = (vector float){ 0.0, 0.0, 0.0, 0.0 };
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
+
+ // reset VSCR and CR
+ vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+ flags = 0;
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
+ __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
+
+ // load inputs -> r14,r15,r16
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
+ __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
+ __asm__ __volatile__ ("vor 16,%0,%0" : : "v" (vec_in3));
+
+ // do stuff
+ (*func)();
+
+ // retrieve output <- r17
+ __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
+
+ // get CR,VSCR flags
+ __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
+
+ /* Restore flags */
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+ src1 = (unsigned int*)&vec_in1;
+ src2 = (unsigned int*)&vec_in2;
+ src3 = (unsigned int*)&vec_in3;
+ dst = (unsigned int*)&vec_out;
+
+ /* Valgrind emulation for vmaddfp and vnmsubfp generates negative
+ * NAN. Technically, NAN is not positive or negative so mask off
+ * the sign bit to eliminate false errors.
+ *
+ * Valgrind emulation is creating negative zero. Mask off negative
+ * from zero result.
+ *
+ * These are only an issue as we are printing the result in hex.
+ *
+ * The VEX emulation accuracy for the vmaddfp and vnmsubfp
+ * instructions is off by a single bit in the least significant
+ * bit position of the result. Mask off the LSB.
+ */
+
+ for (n=0; n<4; n++) {
+ /* NAN result*/
+ if (((dst[n] & 0x7F800000) == 0x7F800000) &&
+ ((dst[n] & 0x7FFFFF) != 0))
+ dst[n] &= 0x7FFFFFFF;
+
+ /* Negative zero result */
+ else if (dst[n] == 0x80000000)
+ dst[n] = 0x0;
+
+ else
+ /* The actual result and the emulated result for the
+ * vmaddfp and vnmsubfp instructions sometimes differ
+ * in the least significant bit. Mask off the bit.
+ */
+ dst[n] &= 0xFFFFFFFE;
+ }
+
+ printf("%s: %08x%08x%08x%08x, %08x%08x%08x%08x, %08x%08x%08x%08x\n", name,
+ src1[0], src1[1], src1[2], src1[3],
+ src2[0], src2[1], src2[2], src2[3],
+ src3[0], src3[1], src3[2], src3[3]);
+ printf("%s: => %08x %08x %08x %08x ", name,
+ dst[0], dst[1], dst[2], dst[3]);
+#if defined TEST_VSCR_SAT
+ p_vscr = (unsigned int*)𝓋
+ printf("(%08x, %08x)\n", flags, p_vscr[3]);
+#else
+ printf("(%08x)\n", flags);
+#endif
+ }
+ if (verbose) printf("\n");
+ }
+ }
+}
+
+static void vcvt_cb (const char* name, test_func_t func_IN,
+ unused uint32_t test_flags)
+{
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector unsigned int vec_in, vec_out, vscr;
+ unsigned int *src, *dst;
+ int i,j;
+#if defined TEST_VSCR_SAT
+ unsigned int* p_vscr;
+#endif
+
+ for (i=0; i<nb_vfargs; i++) {
+ vec_in = (vector unsigned int)vfargs[i];
+
+ for (j=0; j<32; j+=9) {
+ vec_out = (vector unsigned int){ 0,0,0,0 };
+
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+ patch_op_imm(&func_buf[0], j, 16, 5);
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (tmpvscr));
+
+ // reset VSCR and CR
+ vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
+ flags = 0;
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
+ __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
+
+ // load input -> r14
+ __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in));
+
+ // do stuff
+ (*func)();
+
+ // retrieve output <- r17
+ __asm__ __volatile__ ("vor %0,17,17" : "=vr" (vec_out));
+
+ // get CR,VSCR flags
+ __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
+ __asm__ __volatile__ ("mfvscr %0" : "=vr" (vscr));
+
+ /* Restore flags */
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+ src = (unsigned int*)&vec_in;
+ dst = (unsigned int*)&vec_out;
+
+ printf("%s: %08x (%13e), %2u", name, src[0], *(float*)(&src[0]), j);
+ printf(" => %08x (%13e) ", dst[0], *(float*)(&dst[0]));
+// printf(" => %08x ", dst[0]);
+#if defined TEST_VSCR_SAT
+ p_vscr = (unsigned int*)𝓋
+ printf("(%08x, %08x)\n", flags, p_vscr[3]);
+#else
+ printf("(%08x)\n", flags);
+#endif
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+static special_t special_av_float_ops[] = {
+ {
+ "vcfux", /* One reg, one 5-bit uimm argument */
+ &vcvt_cb,
+ },
+ {
+ "vcfsx", /* One reg, one 5-bit uimm argument */
+ &vcvt_cb,
+ },
+ {
+ "vctuxs", /* One reg, one 5-bit uimm argument */
+ &vcvt_cb,
+ },
+ {
+ "vcfux", /* One reg, one 5-bit uimm argument */
+ &vcvt_cb,
+ },
+ {
+ "vctsxs", /* One reg, one 5-bit uimm argument */
+ &vcvt_cb,
+ },
+ {
+ NULL,
+ NULL,
+ },
+};
+
+static void test_av_float_special (const char* name, test_func_t func,
+ uint32_t test_flags)
+{
+ test_special(special_av_float_ops, name, func, test_flags);
+}
+
+/* Used in do_tests, indexed by flags->nb_args
+ Elements correspond to enum test_flags::num args
+*/
+static test_loop_t altivec_float_loops[] = {
+ &test_av_float_one_arg,
+ &test_av_float_two_args,
+ &test_av_float_three_args,
+ &test_av_float_two_args,
+ NULL,
+ NULL,
+ &test_av_float_special,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+};
+
+#endif /* defined (HAS_ALTIVEC) */
+
+
+#if defined (IS_PPC405)
+static void test_ppc405 (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ volatile uint32_t res, flags, xer, tmpcr, tmpxer;
+ int i, j, k;
+
+ for (i=0; i<nb_iargs; i++) {
+ for (j=0; j<nb_iargs; j++) {
+ for (k=0; k<nb_iargs; k++) {
+ r14 = iargs[i];
+ r15 = iargs[j];
+ /* Beware: the third argument and the result
+ * are in the same register
+ */
+ r17 = iargs[k];
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr 18");
+ tmpcr = r18;
+ __asm__ __volatile__ ("mfxer 18");
+ tmpxer = r18;
+
+ /* Set up flags for test */
+ r18 = 0;
+ __asm__ __volatile__ ("mtcr 18");
+ __asm__ __volatile__ ("mtxer 18");
+ (*func)();
+ __asm__ __volatile__ ("mfcr 18");
+ flags = r18;
+ __asm__ __volatile__ ("mfxer 18");
+ xer = r18;
+ res = r17;
+
+ /* Restore flags */
+ r18 = tmpcr;
+ __asm__ __volatile__ ("mtcr 18");
+ r18 = tmpxer;
+ __asm__ __volatile__ ("mtxer 18");
+
+ printf("%s %08x, %08x, %08x => %08x (%08x %08x)\n",
+ name, iargs[i], iargs[j], iargs[k], res, flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+ }
+}
+#endif /* defined (IS_PPC405) */
+
+static int check_filter (char *filter)
+{
+ char *c;
+ int ret = 1;
+
+ if (filter != NULL) {
+ c = strchr(filter, '*');
+ if (c != NULL) {
+ *c = '\0';
+ ret = 0;
+ }
+ }
+
+ return ret;
+}
+
+static int check_name (const char* name, const char *filter,
+ int exact)
+{
+ int nlen, flen;
+ int ret = 0;
+
+ if (filter != NULL) {
+ for (; isspace(*name); name++)
+ continue;
+ FDPRINTF("Check '%s' againt '%s' (%s match)\n",
+ name, filter, exact ? "exact" : "starting");
+ nlen = strlen(name);
+ flen = strlen(filter);
+ if (exact) {
+ if (nlen == flen && memcmp(name, filter, flen) == 0)
+ ret = 1;
+ } else {
+ if (flen <= nlen && memcmp(name, filter, flen) == 0)
+ ret = 1;
+ }
+ } else {
+ ret = 1;
+ }
+ return ret;
+}
+
+
+
+typedef struct insn_sel_flags_t_struct {
+ int one_arg, two_args, three_args;
+ int arith, logical, compare, ldst;
+ int integer, floats, p405, altivec, faltivec, misc;
+ int cr;
+} insn_sel_flags_t;
+
+static void do_tests ( insn_sel_flags_t seln_flags,
+ char *filter)
+{
+#if defined (IS_PPC405)
+ test_loop_t tmpl;
+#endif
+ test_loop_t *loop;
+ test_t *tests;
+ int nb_args, type, family;
+ int i, j, n;
+ int exact;
+
+ exact = check_filter(filter);
+ n = 0;
+ for (i=0; all_tests[i].name != NULL; i++) {
+ nb_args = all_tests[i].flags & PPC_NB_ARGS;
+ /* Check number of arguments */
+ if ((nb_args == 1 && !seln_flags.one_arg) ||
+ (nb_args == 2 && !seln_flags.two_args) ||
+ (nb_args == 3 && !seln_flags.three_args))
+ continue;
+ /* Check instruction type */
+ type = all_tests[i].flags & PPC_TYPE;
+ if ((type == PPC_ARITH && !seln_flags.arith) ||
+ (type == PPC_LOGICAL && !seln_flags.logical) ||
+ (type == PPC_COMPARE && !seln_flags.compare) ||
+ (type == PPC_LDST && !seln_flags.ldst) ||
+ (type == PPC_POPCNT && !seln_flags.arith))
+ continue;
+ /* Check instruction family */
+ family = all_tests[i].flags & PPC_FAMILY;
+ if ((family == PPC_INTEGER && !seln_flags.integer) ||
+ (family == PPC_FLOAT && !seln_flags.floats) ||
+ (family == PPC_405 && !seln_flags.p405) ||
+ (family == PPC_ALTIVEC && !seln_flags.altivec) ||
+ (family == PPC_MISC && !seln_flags.misc) ||
+ (family == PPC_FALTIVEC && !seln_flags.faltivec))
+ continue;
+ /* Check flags update */
+ if (((all_tests[i].flags & PPC_CR) && seln_flags.cr == 0) ||
+ (!(all_tests[i].flags & PPC_CR) && seln_flags.cr == 1))
+ continue;
+ /* All passed, do the tests */
+ tests = all_tests[i].tests;
+ /* Select the test loop */
+ switch (family) {
+ case PPC_INTEGER:
+ loop = &int_loops[nb_args - 1];
+ break;
+ case PPC_MISC:
+ loop = &misc_loops[0];
+ break;
+ case PPC_FLOAT:
+#if !defined (NO_FLOAT)
+ loop = &float_loops[nb_args - 1];
+ break;
+#else
+ fprintf(stderr, "Sorry. "
+ "PPC floating point instructions tests "
+ "are disabled on your host\n");
+#endif /* !defined (NO_FLOAT) */
+
+ case PPC_405:
+#if defined (IS_PPC405)
+ tmpl = &test_ppc405;
+ loop = &tmpl;
+ break;
+#else
+ fprintf(stderr, "Sorry. "
+ "PPC405 instructions tests are disabled on your host\n");
+ continue;
+#endif /* defined (IS_PPC405) */
+ case PPC_ALTIVEC:
+#if defined (HAS_ALTIVEC)
+ loop = &altivec_int_loops[nb_args - 1];
+ break;
+#else
+ fprintf(stderr, "Sorry. "
+ "Altivec instructions tests are disabled on your host\n");
+ continue;
+#endif
+ case PPC_FALTIVEC:
+#if defined (HAS_ALTIVEC)
+ loop = &altivec_float_loops[nb_args - 1];
+ break;
+#else
+ fprintf(stderr, "Sorry. "
+ "Altivec float instructions tests "
+ "are disabled on your host\n");
+#endif
+ continue;
+ default:
+ printf("ERROR: unknown insn family %08x\n", family);
+ continue;
+ }
+ if (1 || verbose > 0)
+ printf("%s:\n", all_tests[i].name);
+ for (j=0; tests[j].name != NULL; j++) {
+ if (check_name(tests[j].name, filter, exact)) {
+ if (verbose > 1)
+ printf("Test instruction %s\n", tests[j].name);
+ (*loop)(tests[j].name, tests[j].func, all_tests[i].flags);
+ printf("\n");
+ n++;
+ }
+ }
+ if (verbose) printf("\n");
+ }
+ printf("All done. Tested %d different instructions\n", n);
+}
+
+
+static void usage (void)
+{
+#if !defined (USAGE_SIMPLE)
+ fprintf(stderr,
+ "jm-insns [-1] [-2] [-3] [-*] [-t <type>] [-f <family>] [-u] "
+ "[-n <filter>] [-r <test_rigour>] [-h]\n"
+ "\t-1: test opcodes with one argument\n"
+ "\t-2: test opcodes with two arguments\n"
+ "\t-3: test opcodes with three arguments\n"
+ "\t-*: launch test without checking the number of arguments\n"
+ "\t-t: launch test for instructions of type <type>\n"
+ "\t recognized types:\n"
+ "\t\tarith (or a)\n"
+ "\t\tlogical (or l)\n"
+ "\t\tcompare (or c)\n"
+ "\t\tstoreload (or s)\n"
+ "\t-f: launch test for instructions of family <family>\n"
+ "\t recognized families:\n"
+ "\t\tinteger (or i)\n"
+ "\t\tfloat (or f)\n"
+ "\t\tppc405 (or mac)\n"
+ "\t\taltivec (or a)\n"
+ "\t-u: test instructions that update flags\n"
+ "\t-n: filter instructions with <filter>\n"
+ "\t <filter> can be in two forms:\n"
+ "\t\tname : filter functions that exactly match <name>\n"
+ "\t\tname* : filter functions that start with <name>\n"
+ "\t-r: set size of arg tables to use to define <test_rigour>\n"
+ "\t recognized types:\n"
+ "\t\tlarge (or l)\n"
+ "\t\tsmall (or s) - default\n"
+ "\t-v: verbose (-v -v for more)\n"
+ "\t-h: print this help\n"
+ );
+#else // #if !defined (USAGE_SIMPLE)
+ fprintf(stderr,
+ "Usage: jm-insns [OPTION]\n"
+ "\t-i: test integer instructions (default)\n"
+ "\t-f: test floating point instructions\n"
+ "\t-a: test altivec instructions\n"
+ "\t-m: test miscellaneous instructions\n"
+ "\t-A: test all (int, fp, altivec) instructions\n"
+ "\t-v: be verbose\n"
+ "\t-h: display this help and exit\n"
+ );
+#endif // #if !defined (USAGE_SIMPLE)
+}
+
+
+
+int main (int argc, char **argv)
+{
+#if !defined (USAGE_SIMPLE)
+////////////////////////////////////////////////////////////////////////
+ unsigned char *tmp, *filter = NULL;
+ insn_sel_flags_t flags;
+ int c;
+
+ // check HWord_t really is a host word
+ assert(sizeof(void*) == sizeof(HWord_t));
+
+ flags.one_arg = 0;
+ flags.two_args = 0;
+ flags.three_args = 0;
+ flags.arith = 0;
+ flags.logical = 0;
+ flags.compare = 0;
+ flags.ldst = 0;
+ flags.integer = 0;
+ flags.floats = 0;
+ flags.p405 = 0;
+ flags.altivec = 0;
+ flags.faltivec = 0;
+ flags.cr = -1;
+
+ while ((c = getopt(argc, argv, "123t:f:n:r:uvh")) != -1) {
+ switch (c) {
+ case '1':
+ flags.one_arg = 1;
+ break;
+ case '2':
+ flags.two_args = 1;
+ break;
+ case '3':
+ flags.three_args = 1;
+ break;
+ case 't':
+ tmp = optarg;
+ if (strcmp(tmp, "arith") == 0 || strcmp(tmp, "a") == 0) {
+ flags.arith = 1;
+ } else if (strcmp(tmp, "logical") == 0 || strcmp(tmp, "l") == 0) {
+ flags.logical = 1;
+ } else if (strcmp(tmp, "compare") == 0 || strcmp(tmp, "c") == 0) {
+ flags.compare = 1;
+ } else if (strcmp(tmp, "storeload") == 0 || strcmp(tmp, "s") == 0) {
+ flags.ldst = 1;
+ } else {
+ goto bad_arg;
+ }
+ break;
+ case 'f':
+ tmp = optarg;
+ if (strcmp(tmp, "integer") == 0 || strcmp(tmp, "i") == 0) {
+ flags.integer = 1;
+ } else if (strcmp(tmp, "float") == 0 || strcmp(tmp, "f") == 0) {
+ flags.floats = 1;
+ } else if (strcmp(tmp, "ppc405") == 0 || strcmp(tmp, "mac") == 0) {
+ flags.p405 = 1;
+ } else if (strcmp(tmp, "altivec") == 0 || strcmp(tmp, "a") == 0) {
+ flags.altivec = 1;
+ flags.faltivec = 1;
+ } else {
+ goto bad_arg;
+ }
+ break;
+ case 'n':
+ filter = optarg;
+ break;
+ case 'r':
+ tmp = optarg;
+ if (strcmp(tmp, "large") == 0 || strcmp(tmp, "l") == 0) {
+ arg_list_size = 1;
+ } else if (strcmp(tmp, "small") == 0 || strcmp(tmp, "s") == 0) {
+ arg_list_size = 0;
+ } else {
+ goto bad_arg;
+ }
+ break;
+
+ case 'u':
+ flags.cr = 1;
+ break;
+ case 'h':
+ usage();
+ return 0;
+ case 'v':
+ verbose++;
+ break;
+ default:
+ usage();
+ fprintf(stderr, "Unknown argument: '%c'\n", c);
+ return 1;
+ bad_arg:
+ usage();
+ fprintf(stderr, "Bad argument for '%c': '%s'\n", c, tmp);
+ return 1;
+ }
+ }
+ if (argc != optind) {
+ usage();
+ fprintf(stderr, "Bad number of arguments\n");
+ return 1;
+ }
+
+ // Default n_args
+ if (flags.one_arg == 0 && flags.two_args == 0 && flags.three_args == 0) {
+ flags.one_arg = 1;
+ flags.two_args = 1;
+ flags.three_args = 1;
+ }
+ // Default type
+ if (flags.arith == 0 && flags.logical == 0 &&
+ flags.compare == 0 && flags.ldst == 0) {
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
+ }
+ // Default family
+ if (flags.integer == 0 && flags.floats == 0 &&
+ flags.p405 == 0 && flags.altivec == 0 && flags.faltivec == 0) {
+ flags.integer = 1;
+ flags.floats = 1;
+ flags.p405 = 1;
+ flags.altivec = 1;
+ flags.faltivec = 1;
+ }
+ // Default cr update
+ if (flags.cr == -1)
+ flags.cr = 2; // both
+
+#else // #if !defined (USAGE_SIMPLE)
+////////////////////////////////////////////////////////////////////////
+ /* Simple usage:
+ ./jm-insns -i => int insns
+ ./jm-insns -f => fp insns
+ ./jm-insns -a => av insns
+ ./jm-insns -m => miscellaneous insns
+ ./jm-insns -A => int, fp and avinsns
+ */
+ char *filter = NULL;
+ insn_sel_flags_t flags;
+ int c;
+
+ // Args
+ flags.one_arg = 1;
+ flags.two_args = 1;
+ flags.three_args = 1;
+ // Type
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
+ // Family
+ flags.integer = 0;
+ flags.floats = 0;
+ flags.misc = 0;
+ flags.p405 = 0;
+ flags.altivec = 0;
+ flags.faltivec = 0;
+ // Flags
+ flags.cr = 2;
+
+ while ((c = getopt(argc, argv, "ifmahvA")) != -1) {
+ switch (c) {
+ case 'i':
+ flags.integer = 1;
+ break;
+ case 'f':
+ flags.floats = 1;
+ break;
+ case 'a':
+ flags.altivec = 1;
+ flags.faltivec = 1;
+ break;
+ case 'm':
+ flags.misc = 1;
+ break;
+ case 'A':
+ flags.integer = 1;
+ flags.floats = 1;
+ flags.altivec = 1;
+ flags.faltivec = 1;
+ break;
+ case 'h':
+ usage();
+ return 0;
+ case 'v':
+ verbose++;
+ break;
+ default:
+ usage();
+ fprintf(stderr, "Unknown argument: '%c'\n", c);
+ return 1;
+ }
+ }
+
+ arg_list_size = 0;
+#endif // #if !defined (USAGE_SIMPLE)
+
+
+ build_iargs_table();
+ build_fargs_table();
+ build_ii16_table();
+#if defined (HAS_ALTIVEC)
+ if (flags.altivec || flags.faltivec) {
+ build_viargs_table();
+ build_vfargs_table();
+ }
+#endif
+ // dump_iargs();
+ // dump_iargs16();
+ // dump_vfargs();
+
+ if (verbose > 1) {
+ printf("\nInstruction Selection:\n");
+ printf(" n_args: \n");
+ printf(" one_arg = %d\n", flags.one_arg);
+ printf(" two_args = %d\n", flags.two_args);
+ printf(" three_args = %d\n", flags.three_args);
+ printf(" type: \n");
+ printf(" arith = %d\n", flags.arith);
+ printf(" logical = %d\n", flags.logical);
+ printf(" compare = %d\n", flags.compare);
+ printf(" ldst = %d\n", flags.ldst);
+ printf(" family: \n");
+ printf(" integer = %d\n", flags.integer);
+ printf(" floats = %d\n", flags.floats);
+ printf(" p405 = %d\n", flags.p405);
+ printf(" altivec = %d\n", flags.altivec);
+ printf(" faltivec = %d\n", flags.faltivec);
+ printf(" cr update: \n");
+ printf(" cr = %d\n", flags.cr);
+ printf("\n");
+ printf(" num args: \n");
+ printf(" iargs - %d\n", nb_iargs);
+ printf(" fargs - %d\n", nb_fargs);
+#if defined (HAS_ALTIVEC)
+ printf(" viargs - %d\n", nb_viargs);
+ printf(" vfargs - %d\n", nb_vfargs);
+#endif
+ printf("\n");
+ }
+
+ do_tests( flags, filter );
+
+ return 0;
+}
diff --git a/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp b/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp
index 9b5c24f..40d32d6 100644
--- a/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp
+++ b/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp
@@ -2,224 +2,777 @@
mfvsrd: 090a0b0c0e0d0e0f => 090a0b0c0e0d0e0f
mfvsrd: f1f2f3f4f5f6f7f8 => f1f2f3f4f5f6f7f8
mfvsrd: f9fafbfcfefdfeff => f9fafbfcfefdfeff
+mfvsrd: 00007fffffffffff => 00007fffffffffff
+mfvsrd: ffff000000000000 => ffff000000000000
+mfvsrd: 0000800000000000 => 0000800000000000
+mfvsrd: 0000000000000000 => 0000000000000000
+mfvsrd: ffffffffffffffff => ffffffffffffffff
mfvsrwz: 0102030405060708 => 0000000005060708
mfvsrwz: 090a0b0c0e0d0e0f => 000000000e0d0e0f
mfvsrwz: f1f2f3f4f5f6f7f8 => 00000000f5f6f7f8
mfvsrwz: f9fafbfcfefdfeff => 00000000fefdfeff
+mfvsrwz: 00007fffffffffff => 00000000ffffffff
+mfvsrwz: ffff000000000000 => 0000000000000000
+mfvsrwz: 0000800000000000 => 0000000000000000
+mfvsrwz: 0000000000000000 => 0000000000000000
+mfvsrwz: ffffffffffffffff => 00000000ffffffff
mtvsrd: 0102030405060708 => 0102030405060708
mtvsrd: 090a0b0c0e0d0e0f => 090a0b0c0e0d0e0f
mtvsrd: f1f2f3f4f5f6f7f8 => f1f2f3f4f5f6f7f8
mtvsrd: f9fafbfcfefdfeff => f9fafbfcfefdfeff
+mtvsrd: 00007fffffffffff => 00007fffffffffff
+mtvsrd: ffff000000000000 => ffff000000000000
+mtvsrd: 0000800000000000 => 0000800000000000
+mtvsrd: 0000000000000000 => 0000000000000000
+mtvsrd: ffffffffffffffff => ffffffffffffffff
mtvsrwz: 05060708 => 0000000005060708
mtvsrwz: 0e0d0e0f => 000000000e0d0e0f
mtvsrwz: f5f6f7f8 => 00000000f5f6f7f8
mtvsrwz: fefdfeff => 00000000fefdfeff
+mtvsrwz: ffffffff => 00000000ffffffff
+mtvsrwz: 00000000 => 0000000000000000
+mtvsrwz: 00000000 => 0000000000000000
+mtvsrwz: 00000000 => 0000000000000000
+mtvsrwz: ffffffff => 00000000ffffffff
mtfprwa: 05060708 => 0000000005060708
mtfprwa: 0e0d0e0f => 000000000e0d0e0f
mtfprwa: f5f6f7f8 => fffffffff5f6f7f8
mtfprwa: fefdfeff => fffffffffefdfeff
+mtfprwa: ffffffff => ffffffffffffffff
+mtfprwa: 00000000 => 0000000000000000
+mtfprwa: 00000000 => 0000000000000000
+mtfprwa: 00000000 => 0000000000000000
+mtfprwa: ffffffff => ffffffffffffffff
vaddudm: 0102030405060708 @@ 0102030405060708 ==> 020406080a0c0e10
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 121416181c1a1c1e
vaddudm: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> f2f4f6f8fafcff00
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 030507090d0b0d0e
+vaddudm: 0102030405060708 @@ 00007fffffffffff ==> 0102830405060707
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 09090b0c0e0d0e0f
+vaddudm: 0102030405060708 @@ 0000800000000000 ==> 0102830405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vaddudm: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f2f4f6f8fafcff00
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 030507090d0b0d0e
vaddudm: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> e3e5e7e9ebedeff0
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f3f5f7f9fdfbfdfe
+vaddudm: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> f1f373f4f5f6f7f7
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9f9fbfcfefdfeff
+vaddudm: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f373f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vaddudm: 00007fffffffffff @@ 0102030405060708 ==> 0102830405060707
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 09090b0c0e0d0e0f
+vaddudm: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> f1f373f4f5f6f7f7
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> f9f9fbfcfefdfeff
+vaddudm: 00007fffffffffff @@ 00007fffffffffff ==> 0000fffffffffffe
+ ffff000000000000 @@ ffff000000000000 ==> fffe000000000000
+vaddudm: 00007fffffffffff @@ 0000800000000000 ==> 0000ffffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vaddudm: 0000800000000000 @@ 0102030405060708 ==> 0102830405060708
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vaddudm: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> f1f373f4f5f6f7f8
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vaddudm: 0000800000000000 @@ 00007fffffffffff ==> 0000ffffffffffff
+ 0000000000000000 @@ ffff000000000000 ==> ffff000000000000
+vaddudm: 0000800000000000 @@ 0000800000000000 ==> 0001000000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vsubudm: 0102030405060708 @@ 0102030405060708 ==> 0000000000000000
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000000000000000
vsubudm: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0f0f0f0f0f0f0f10
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0f0f0f0f0f0f0f10
+vsubudm: 0102030405060708 @@ 00007fffffffffff ==> 0101830405060709
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090b0b0c0e0d0e0f
+vsubudm: 0102030405060708 @@ 0000800000000000 ==> 0101830405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vsubudm: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f0f0f0f0f0f0f0f0
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> f0f0f0f0f0f0f0f0
vsubudm: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsubudm: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> f1f273f4f5f6f7f9
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fbfbfcfefdfeff
+vsubudm: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f273f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vsubudm: 00007fffffffffff @@ 0102030405060708 ==> fefe7cfbfaf9f8f7
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> f6f4f4f3f1f2f1f1
+vsubudm: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0e0d8c0b0a090807
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 0604040301020101
+vsubudm: 00007fffffffffff @@ 00007fffffffffff ==> 0000000000000000
+ ffff000000000000 @@ ffff000000000000 ==> 0000000000000000
+vsubudm: 00007fffffffffff @@ 0000800000000000 ==> ffffffffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vsubudm: 0000800000000000 @@ 0102030405060708 ==> fefe7cfbfaf9f8f8
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> f6f5f4f3f1f2f1f1
+vsubudm: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0e0d8c0b0a090808
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0605040301020101
+vsubudm: 0000800000000000 @@ 00007fffffffffff ==> 0000000000000001
+ 0000000000000000 @@ ffff000000000000 ==> 0001000000000000
+vsubudm: 0000800000000000 @@ 0000800000000000 ==> 0000000000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vmaxud: 0102030405060708 @@ 0102030405060708 ==> 0102030405060708
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
vmaxud: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vmaxud: 0102030405060708 @@ 00007fffffffffff ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> ffff000000000000
+vmaxud: 0102030405060708 @@ 0000800000000000 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vmaxud: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f1f2f3f4f5f6f7f8
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> f9fafbfcfefdfeff
vmaxud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vmaxud: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> ffff000000000000
+vmaxud: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vmaxud: 00007fffffffffff @@ 0102030405060708 ==> 0102030405060708
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> ffff000000000000
+vmaxud: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> ffff000000000000
+vmaxud: 00007fffffffffff @@ 00007fffffffffff ==> 00007fffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vmaxud: 00007fffffffffff @@ 0000800000000000 ==> 0000800000000000
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vmaxud: 0000800000000000 @@ 0102030405060708 ==> 0102030405060708
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vmaxud: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vmaxud: 0000800000000000 @@ 00007fffffffffff ==> 0000800000000000
+ 0000000000000000 @@ ffff000000000000 ==> ffff000000000000
+vmaxud: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vmaxsd: 0102030405060708 @@ 0102030405060708 ==> 0102030405060708
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
vmaxsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0102030405060708
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 090a0b0c0e0d0e0f
+vmaxsd: 0102030405060708 @@ 00007fffffffffff ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090a0b0c0e0d0e0f
+vmaxsd: 0102030405060708 @@ 0000800000000000 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vmaxsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0102030405060708
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
vmaxsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vmaxsd: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 00007fffffffffff
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> ffff000000000000
+vmaxsd: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 0000800000000000
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 0000000000000000
+vmaxsd: 00007fffffffffff @@ 0102030405060708 ==> 0102030405060708
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vmaxsd: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 00007fffffffffff
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> ffff000000000000
+vmaxsd: 00007fffffffffff @@ 00007fffffffffff ==> 00007fffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vmaxsd: 00007fffffffffff @@ 0000800000000000 ==> 0000800000000000
+ ffff000000000000 @@ 0000000000000000 ==> 0000000000000000
+vmaxsd: 0000800000000000 @@ 0102030405060708 ==> 0102030405060708
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vmaxsd: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000800000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vmaxsd: 0000800000000000 @@ 00007fffffffffff ==> 0000800000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vmaxsd: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vminud: 0102030405060708 @@ 0102030405060708 ==> 0102030405060708
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
vminud: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0102030405060708
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 090a0b0c0e0d0e0f
+vminud: 0102030405060708 @@ 00007fffffffffff ==> 00007fffffffffff
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090a0b0c0e0d0e0f
+vminud: 0102030405060708 @@ 0000800000000000 ==> 0000800000000000
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 0000000000000000
vminud: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0102030405060708
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
vminud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vminud: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 00007fffffffffff
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fafbfcfefdfeff
+vminud: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 0000800000000000
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 0000000000000000
+vminud: 00007fffffffffff @@ 0102030405060708 ==> 00007fffffffffff
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
+vminud: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 00007fffffffffff
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vminud: 00007fffffffffff @@ 00007fffffffffff ==> 00007fffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vminud: 00007fffffffffff @@ 0000800000000000 ==> 00007fffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> 0000000000000000
+vminud: 0000800000000000 @@ 0102030405060708 ==> 0000800000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vminud: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000800000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vminud: 0000800000000000 @@ 00007fffffffffff ==> 00007fffffffffff
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vminud: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vminsd: 0102030405060708 @@ 0102030405060708 ==> 0102030405060708
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 090a0b0c0e0d0e0f
vminsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vminsd: 0102030405060708 @@ 00007fffffffffff ==> 00007fffffffffff
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> ffff000000000000
+vminsd: 0102030405060708 @@ 0000800000000000 ==> 0000800000000000
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 0000000000000000
vminsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f1f2f3f4f5f6f7f8
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> f9fafbfcfefdfeff
vminsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vminsd: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fafbfcfefdfeff
+vminsd: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vminsd: 00007fffffffffff @@ 0102030405060708 ==> 00007fffffffffff
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> ffff000000000000
+vminsd: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vminsd: 00007fffffffffff @@ 00007fffffffffff ==> 00007fffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vminsd: 00007fffffffffff @@ 0000800000000000 ==> 00007fffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vminsd: 0000800000000000 @@ 0102030405060708 ==> 0000800000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vminsd: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> f1f2f3f4f5f6f7f8
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> f9fafbfcfefdfeff
+vminsd: 0000800000000000 @@ 00007fffffffffff ==> 00007fffffffffff
+ 0000000000000000 @@ ffff000000000000 ==> ffff000000000000
+vminsd: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vcmpequd: 0102030405060708 @@ 0102030405060708 ==> ffffffffffffffff
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
vcmpequd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpequd: 0102030405060708 @@ 00007fffffffffff ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 0000000000000000
+vcmpequd: 0102030405060708 @@ 0000800000000000 ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 0000000000000000
vcmpequd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0000000000000000
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0000000000000000
vcmpequd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vcmpequd: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 0000000000000000
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 0000000000000000
+vcmpequd: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 0000000000000000
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 0000000000000000
+vcmpequd: 00007fffffffffff @@ 0102030405060708 ==> 0000000000000000
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vcmpequd: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpequd: 00007fffffffffff @@ 00007fffffffffff ==> ffffffffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffffffffffffffff
+vcmpequd: 00007fffffffffff @@ 0000800000000000 ==> 0000000000000000
+ ffff000000000000 @@ 0000000000000000 ==> 0000000000000000
+vcmpequd: 0000800000000000 @@ 0102030405060708 ==> 0000000000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vcmpequd: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpequd: 0000800000000000 @@ 00007fffffffffff ==> 0000000000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vcmpequd: 0000800000000000 @@ 0000800000000000 ==> ffffffffffffffff
+ 0000000000000000 @@ 0000000000000000 ==> ffffffffffffffff
vcmpgtud: 0102030405060708 @@ 0102030405060708 ==> 0000000000000000
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000000000000000
vcmpgtud: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpgtud: 0102030405060708 @@ 00007fffffffffff ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 0000000000000000
+vcmpgtud: 0102030405060708 @@ 0000800000000000 ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> ffffffffffffffff
vcmpgtud: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> ffffffffffffffff
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
vcmpgtud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpgtud: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 0000000000000000
+vcmpgtud: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> ffffffffffffffff
+vcmpgtud: 00007fffffffffff @@ 0102030405060708 ==> 0000000000000000
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
+vcmpgtud: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vcmpgtud: 00007fffffffffff @@ 00007fffffffffff ==> 0000000000000000
+ ffff000000000000 @@ ffff000000000000 ==> 0000000000000000
+vcmpgtud: 00007fffffffffff @@ 0000800000000000 ==> 0000000000000000
+ ffff000000000000 @@ 0000000000000000 ==> ffffffffffffffff
+vcmpgtud: 0000800000000000 @@ 0102030405060708 ==> 0000000000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vcmpgtud: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpgtud: 0000800000000000 @@ 00007fffffffffff ==> ffffffffffffffff
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vcmpgtud: 0000800000000000 @@ 0000800000000000 ==> 0000000000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vcmpgtsd: 0102030405060708 @@ 0102030405060708 ==> 0000000000000000
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000000000000000
vcmpgtsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vcmpgtsd: 0102030405060708 @@ 00007fffffffffff ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> ffffffffffffffff
+vcmpgtsd: 0102030405060708 @@ 0000800000000000 ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> ffffffffffffffff
vcmpgtsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0000000000000000
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0000000000000000
vcmpgtsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0000000000000000
+vcmpgtsd: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 0000000000000000
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 0000000000000000
+vcmpgtsd: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 0000000000000000
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 0000000000000000
+vcmpgtsd: 00007fffffffffff @@ 0102030405060708 ==> 0000000000000000
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vcmpgtsd: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vcmpgtsd: 00007fffffffffff @@ 00007fffffffffff ==> 0000000000000000
+ ffff000000000000 @@ ffff000000000000 ==> 0000000000000000
+vcmpgtsd: 00007fffffffffff @@ 0000800000000000 ==> 0000000000000000
+ ffff000000000000 @@ 0000000000000000 ==> 0000000000000000
+vcmpgtsd: 0000800000000000 @@ 0102030405060708 ==> 0000000000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vcmpgtsd: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vcmpgtsd: 0000800000000000 @@ 00007fffffffffff ==> ffffffffffffffff
+ 0000000000000000 @@ ffff000000000000 ==> ffffffffffffffff
+vcmpgtsd: 0000800000000000 @@ 0000800000000000 ==> 0000000000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vrld: 0102030405060708 @@ 0102030405060708 ==> 0203040506070801
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0586070687078485
vrld: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0801020304050607
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 8485058607068707
+vrld: 0102030405060708 @@ 00007fffffffffff ==> 0081018202830384
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090a0b0c0e0d0e0f
+vrld: 0102030405060708 @@ 0000800000000000 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vrld: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f2f3f4f5f6f7f8f1
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 7dfe7f7eff7ffcfd
vrld: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f8f1f2f3f4f5f6f7
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> fcfd7dfe7f7eff7f
+vrld: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 78f979fa7afb7bfc
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fafbfcfefdfeff
+vrld: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vrld: 00007fffffffffff @@ 0102030405060708 ==> 007fffffffffff00
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 8000000000007fff
+vrld: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> ff00007fffffffff
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 7fff800000000000
+vrld: 00007fffffffffff @@ 00007fffffffffff ==> 80003fffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vrld: 00007fffffffffff @@ 0000800000000000 ==> 00007fffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vrld: 0000800000000000 @@ 0102030405060708 ==> 0080000000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vrld: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000008000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vrld: 0000800000000000 @@ 00007fffffffffff ==> 0000400000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vrld: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vsld: 0102030405060708 @@ 0102030405060708 ==> 0203040506070800
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0586070687078000
vsld: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0800000000000000
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 8000000000000000
+vsld: 0102030405060708 @@ 00007fffffffffff ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090a0b0c0e0d0e0f
+vsld: 0102030405060708 @@ 0000800000000000 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vsld: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f2f3f4f5f6f7f800
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 7dfe7f7eff7f8000
vsld: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f800000000000000
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 8000000000000000
+vsld: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 0000000000000000
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fafbfcfefdfeff
+vsld: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vsld: 00007fffffffffff @@ 0102030405060708 ==> 007fffffffffff00
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 8000000000000000
+vsld: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> ff00000000000000
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsld: 00007fffffffffff @@ 00007fffffffffff ==> 8000000000000000
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vsld: 00007fffffffffff @@ 0000800000000000 ==> 00007fffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vsld: 0000800000000000 @@ 0102030405060708 ==> 0080000000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vsld: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsld: 0000800000000000 @@ 00007fffffffffff ==> 0000000000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vsld: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vsrad: 0102030405060708 @@ 0102030405060708 ==> 0001020304050607
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000121416181c1a
vsrad: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000001
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsrad: 0102030405060708 @@ 00007fffffffffff ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090a0b0c0e0d0e0f
+vsrad: 0102030405060708 @@ 0000800000000000 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vsrad: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> fff1f2f3f4f5f6f7
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> fffff3f5f7f9fdfb
vsrad: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> fffffffffffffff1
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vsrad: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fafbfcfefdfeff
+vsrad: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vsrad: 00007fffffffffff @@ 0102030405060708 ==> 0000007fffffffff
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> fffffffe00000000
+vsrad: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vsrad: 00007fffffffffff @@ 00007fffffffffff ==> 0000000000000000
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vsrad: 00007fffffffffff @@ 0000800000000000 ==> 00007fffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vsrad: 0000800000000000 @@ 0102030405060708 ==> 0000008000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vsrad: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsrad: 0000800000000000 @@ 00007fffffffffff ==> 0000000000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vsrad: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vsrd: 0102030405060708 @@ 0102030405060708 ==> 0001020304050607
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0000121416181c1a
vsrd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000001
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsrd: 0102030405060708 @@ 00007fffffffffff ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090a0b0c0e0d0e0f
+vsrd: 0102030405060708 @@ 0000800000000000 ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 090a0b0c0e0d0e0f
vsrd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 00f1f2f3f4f5f6f7
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0001f3f5f7f9fdfb
vsrd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 00000000000000f1
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0000000000000001
+vsrd: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 0000000000000001
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fafbfcfefdfeff
+vsrd: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> f9fafbfcfefdfeff
+vsrd: 00007fffffffffff @@ 0102030405060708 ==> 0000007fffffffff
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 0001fffe00000000
+vsrd: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000001
+vsrd: 00007fffffffffff @@ 00007fffffffffff ==> 0000000000000000
+ ffff000000000000 @@ ffff000000000000 ==> ffff000000000000
+vsrd: 00007fffffffffff @@ 0000800000000000 ==> 00007fffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff000000000000
+vsrd: 0000800000000000 @@ 0102030405060708 ==> 0000008000000000
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vsrd: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0000000000000000
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vsrd: 0000800000000000 @@ 00007fffffffffff ==> 0000000000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000000000000000
+vsrd: 0000800000000000 @@ 0000800000000000 ==> 0000800000000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vpkudum: Inputs: 05060708 0e0d0e0f 05060708 0e0d0e0f
Output: 05060708 0e0d0e0f 05060708 0e0d0e0f
vpkudum: Inputs: 05060708 0e0d0e0f f5f6f7f8 fefdfeff
Output: 05060708 0e0d0e0f f5f6f7f8 fefdfeff
+vpkudum: Inputs: 05060708 0e0d0e0f ffffffff 00000000
+ Output: 05060708 0e0d0e0f ffffffff 00000000
+vpkudum: Inputs: 05060708 0e0d0e0f 00000000 00000000
+ Output: 05060708 0e0d0e0f 00000000 00000000
vpkudum: Inputs: f5f6f7f8 fefdfeff 05060708 0e0d0e0f
Output: f5f6f7f8 fefdfeff 05060708 0e0d0e0f
vpkudum: Inputs: f5f6f7f8 fefdfeff f5f6f7f8 fefdfeff
Output: f5f6f7f8 fefdfeff f5f6f7f8 fefdfeff
+vpkudum: Inputs: f5f6f7f8 fefdfeff ffffffff 00000000
+ Output: f5f6f7f8 fefdfeff ffffffff 00000000
+vpkudum: Inputs: f5f6f7f8 fefdfeff 00000000 00000000
+ Output: f5f6f7f8 fefdfeff 00000000 00000000
+vpkudum: Inputs: ffffffff 00000000 05060708 0e0d0e0f
+ Output: ffffffff 00000000 05060708 0e0d0e0f
+vpkudum: Inputs: ffffffff 00000000 f5f6f7f8 fefdfeff
+ Output: ffffffff 00000000 f5f6f7f8 fefdfeff
+vpkudum: Inputs: ffffffff 00000000 ffffffff 00000000
+ Output: ffffffff 00000000 ffffffff 00000000
+vpkudum: Inputs: ffffffff 00000000 00000000 00000000
+ Output: ffffffff 00000000 00000000 00000000
+vpkudum: Inputs: 00000000 00000000 05060708 0e0d0e0f
+ Output: 00000000 00000000 05060708 0e0d0e0f
+vpkudum: Inputs: 00000000 00000000 f5f6f7f8 fefdfeff
+ Output: 00000000 00000000 f5f6f7f8 fefdfeff
+vpkudum: Inputs: 00000000 00000000 ffffffff 00000000
+ Output: 00000000 00000000 ffffffff 00000000
+vpkudum: Inputs: 00000000 00000000 00000000 00000000
+ Output: 00000000 00000000 00000000 00000000
vpmsumd: 0102030405060708 @@ 0102030405060708 ==> 0040004000400040
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0045004500410015
vpmsumd: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 07c007c006d00735
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> a260a260a374a2c5
+vpmsumd: 0102030405060708 @@ 00007fffffffffff ==> 07060182fc7efe7f
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 0478fefc030202f8
+vpmsumd: 0102030405060708 @@ 0000800000000000 ==> 0000008101820283
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 0384000000000000
vpmsumd: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 07c007c006d00735
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> a260a260a374a2c5
vpmsumd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0040004000400040
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0045004500410015
+vpmsumd: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 575629aad456d657
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 2c50aeac535252a8
+vpmsumd: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 000078f979fa7afb
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 7bfc000000000000
+vpmsumd: 00007fffffffffff @@ 0102030405060708 ==> 07060182fc7efe7f
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 0478fefc030202f8
+vpmsumd: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 575629aad456d657
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 2c50aeac535252a8
+vpmsumd: 00007fffffffffff @@ 00007fffffffffff ==> 5555555515555555
+ ffff000000000000 @@ ffff000000000000 ==> 5555555555555555
+vpmsumd: 00007fffffffffff @@ 0000800000000000 ==> 000000003fffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffff800000000000
+vpmsumd: 0000800000000000 @@ 0102030405060708 ==> 0000008101820283
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0384000000000000
+vpmsumd: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 000078f979fa7afb
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 7bfc000000000000
+vpmsumd: 0000800000000000 @@ 00007fffffffffff ==> 000000003fffffff
+ 0000000000000000 @@ ffff000000000000 ==> ffff800000000000
+vpmsumd: 0000800000000000 @@ 0000800000000000 ==> 0000000040000000
+ 0000000000000000 @@ 0000000000000000 ==> 0000000000000000
vnand: 0102030405060708 @@ 0102030405060708 ==> fefdfcfbfaf9f8f7
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> f6f5f4f3f1f2f1f0
vnand: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> fefdfcfbfaf9f8f7
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> f6f5f4f3f1f2f1f0
+vnand: 0102030405060708 @@ 00007fffffffffff ==> fffffcfbfaf9f8f7
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> f6f5ffffffffffff
+vnand: 0102030405060708 @@ 0000800000000000 ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> ffffffffffffffff
vnand: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> fefdfcfbfaf9f8f7
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> f6f5f4f3f1f2f1f0
vnand: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0e0d0c0b0a090807
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0605040301020100
+vnand: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> ffff8c0b0a090807
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 0605ffffffffffff
+vnand: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> ffff7fffffffffff
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> ffffffffffffffff
+vnand: 00007fffffffffff @@ 0102030405060708 ==> fffffcfbfaf9f8f7
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> f6f5ffffffffffff
+vnand: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> ffff8c0b0a090807
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 0605ffffffffffff
+vnand: 00007fffffffffff @@ 00007fffffffffff ==> ffff800000000000
+ ffff000000000000 @@ ffff000000000000 ==> 0000ffffffffffff
+vnand: 00007fffffffffff @@ 0000800000000000 ==> ffffffffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffffffffffffffff
+vnand: 0000800000000000 @@ 0102030405060708 ==> ffffffffffffffff
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
+vnand: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> ffff7fffffffffff
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vnand: 0000800000000000 @@ 00007fffffffffff ==> ffffffffffffffff
+ 0000000000000000 @@ ffff000000000000 ==> ffffffffffffffff
+vnand: 0000800000000000 @@ 0000800000000000 ==> ffff7fffffffffff
+ 0000000000000000 @@ 0000000000000000 ==> ffffffffffffffff
vorc: 0102030405060708 @@ 0102030405060708 ==> ffffffffffffffff
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
vorc: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0f0f0f0f0f0f0f0f
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0f0f0f0f0f0f0f0f
+vorc: 0102030405060708 @@ 00007fffffffffff ==> ffff830405060708
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090affffffffffff
+vorc: 0102030405060708 @@ 0000800000000000 ==> ffff7fffffffffff
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> ffffffffffffffff
vorc: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> ffffffffffffffff
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
vorc: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vorc: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> fffff3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9faffffffffffff
+vorc: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> ffffffffffffffff
+vorc: 00007fffffffffff @@ 0102030405060708 ==> fefdffffffffffff
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> fffff4f3f1f2f1f0
+vorc: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0e0d7fffffffffff
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> ffff040301020100
+vorc: 00007fffffffffff @@ 00007fffffffffff ==> ffffffffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffffffffffffffff
+vorc: 00007fffffffffff @@ 0000800000000000 ==> ffff7fffffffffff
+ ffff000000000000 @@ 0000000000000000 ==> ffffffffffffffff
+vorc: 0000800000000000 @@ 0102030405060708 ==> fefdfcfbfaf9f8f7
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> f6f5f4f3f1f2f1f0
+vorc: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0e0d8c0b0a090807
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0605040301020100
+vorc: 0000800000000000 @@ 00007fffffffffff ==> ffff800000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000ffffffffffff
+vorc: 0000800000000000 @@ 0000800000000000 ==> ffffffffffffffff
+ 0000000000000000 @@ 0000000000000000 ==> ffffffffffffffff
veqv: 0102030405060708 @@ 0102030405060708 ==> ffffffffffffffff
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> ffffffffffffffff
veqv: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0f0f0f0f0f0f0f0f
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0f0f0f0f0f0f0f0f
+veqv: 0102030405060708 @@ 00007fffffffffff ==> fefd830405060708
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 090af4f3f1f2f1f0
+veqv: 0102030405060708 @@ 0000800000000000 ==> fefd7cfbfaf9f8f7
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> f6f5f4f3f1f2f1f0
veqv: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 0f0f0f0f0f0f0f0f
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0f0f0f0f0f0f0f0f
veqv: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> ffffffffffffffff
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+veqv: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 0e0d73f4f5f6f7f8
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> f9fa040301020100
+veqv: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 0e0d8c0b0a090807
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 0605040301020100
+veqv: 00007fffffffffff @@ 0102030405060708 ==> fefd830405060708
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 090af4f3f1f2f1f0
+veqv: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0e0d73f4f5f6f7f8
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> f9fa040301020100
+veqv: 00007fffffffffff @@ 00007fffffffffff ==> ffffffffffffffff
+ ffff000000000000 @@ ffff000000000000 ==> ffffffffffffffff
+veqv: 00007fffffffffff @@ 0000800000000000 ==> ffff000000000000
+ ffff000000000000 @@ 0000000000000000 ==> 0000ffffffffffff
+veqv: 0000800000000000 @@ 0102030405060708 ==> fefd7cfbfaf9f8f7
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> f6f5f4f3f1f2f1f0
+veqv: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0e0d8c0b0a090807
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0605040301020100
+veqv: 0000800000000000 @@ 00007fffffffffff ==> ffff000000000000
+ 0000000000000000 @@ ffff000000000000 ==> 0000ffffffffffff
+veqv: 0000800000000000 @@ 0000800000000000 ==> ffffffffffffffff
+ 0000000000000000 @@ 0000000000000000 ==> ffffffffffffffff
vcipher: 0102030405060708 @@ 0102030405060708 ==> 15abdc2823b74b86
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 22037bc3e1e25abc
vcipher: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> e55b2cd8d347bb76
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> d2f38b331112aa4c
+vcipher: 0102030405060708 @@ 00007fffffffffff ==> 14a9a0d3d94eb371
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> d4f670cfefef54b3
+vcipher: 0102030405060708 @@ 0000800000000000 ==> 14a95f2c26b14c8e
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 2b0970cfefef54b3
vcipher: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 8720c49da1d37bca
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 906d1f673bb72743
vcipher: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 77d0346d51238b3a
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 609def97cb47d7b3
+vcipher: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 8622b8665b2a833d
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 6698146b35ba294c
+vcipher: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 86224799a4d57cc2
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 9967146b35ba294c
+vcipher: 00007fffffffffff @@ 0102030405060708 ==> fd8b1512668ffb6b
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 44a1fbab18f18719
+vcipher: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0d7be5e2967f0b9b
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> b4510b5be80177e9
+vcipher: 00007fffffffffff @@ 00007fffffffffff ==> fc8969e99c76039c
+ ffff000000000000 @@ ffff000000000000 ==> b254f0a716fc8916
+vcipher: 00007fffffffffff @@ 0000800000000000 ==> fc8996166389fc63
+ ffff000000000000 @@ 0000000000000000 ==> 4dabf0a716fc8916
+vcipher: 0000800000000000 @@ 0102030405060708 ==> 626160676665646b
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> c4802fc16d6e6d6c
+vcipher: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 929190979695949b
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 3470df319d9e9d9c
+vcipher: 0000800000000000 @@ 00007fffffffffff ==> 63631c9c9c9c9c9c
+ 0000000000000000 @@ ffff000000000000 ==> 327524cd63636363
+vcipher: 0000800000000000 @@ 0000800000000000 ==> 6363e36363636363
+ 0000000000000000 @@ 0000000000000000 ==> cd8a24cd63636363
vcipherlast: 0102030405060708 @@ 0102030405060708 ==> 7d6d28726e61acfa
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 08dd703ca57acbf1
vcipherlast: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 8d9dd8829e915c0a
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> f82d80cc558a3b01
+vcipherlast: 0102030405060708 @@ 00007fffffffffff ==> 7c6f54899498540d
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> fe287b30ab77c5fe
+vcipherlast: 0102030405060708 @@ 0000800000000000 ==> 7c6fab766b67abf2
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 01d77b30ab77c5fe
vcipherlast: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> a0400c12e32bbcb7
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 905e064db58466bf
vcipherlast: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 50b0fce213db4c47
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 60aef6bd4574964f
+vcipherlast: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> a14270e919d24440
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 66ab0d41bb8968b0
+vcipherlast: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> a1428f16e62dbbbf
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 99540d41bb8968b0
+vcipherlast: 00007fffffffffff @@ 0102030405060708 ==> 621460671310641e
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 1f69d91a6d6e186c
+vcipherlast: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 92e49097e3e094ee
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> ef9929ea9d9ee89c
+vcipherlast: 00007fffffffffff @@ 00007fffffffffff ==> 63161c9ce9e99ce9
+ ffff000000000000 @@ ffff000000000000 ==> e99cd21663631663
+vcipherlast: 00007fffffffffff @@ 0000800000000000 ==> 6316e36316166316
+ ffff000000000000 @@ 0000000000000000 ==> 1663d21663631663
+vcipherlast: 0000800000000000 @@ 0102030405060708 ==> 626160676665646b
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 6a69c66f6d6e6d6c
+vcipherlast: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 929190979695949b
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 9a99369f9d9e9d9c
+vcipherlast: 0000800000000000 @@ 00007fffffffffff ==> 63631c9c9c9c9c9c
+ 0000000000000000 @@ ffff000000000000 ==> 9c9ccd6363636363
+vcipherlast: 0000800000000000 @@ 0000800000000000 ==> 6363e36363636363
+ 0000000000000000 @@ 0000000000000000 ==> 6363cd6363636363
vncipher: 0102030405060708 @@ 0102030405060708 ==> fe67ce881a80f569
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 19db0b0605541639
vncipher: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0e973e78ea700599
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> e92bfbf6f5a4e6c9
+vncipher: 0102030405060708 @@ 00007fffffffffff ==> de98809d822f77d0
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> 1424f3081f45082e
+vncipher: 0102030405060708 @@ 0000800000000000 ==> 0facae567dd0882f
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 3aef223c1f45082e
vncipher: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 8b10c2d5607a5569
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 581826de46277b9c
vncipher: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 7be03225908aa599
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> a8e8d62eb6d78b6c
+vncipher: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> abef8cc0f8d5d7d0
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 55e7ded05c36658b
+vncipher: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 7adba20b072a282f
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 7b2c0fe45c36658b
+vncipher: 00007fffffffffff @@ 0102030405060708 ==> 359e61e1b44edf06
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> ec338260e6209378
+vncipher: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> c56e911144be2ff6
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 1cc3729016d06388
+vncipher: 00007fffffffffff @@ 00007fffffffffff ==> 15612ff42ce15dbf
+ ffff000000000000 @@ ffff000000000000 ==> e1cc7a6efc318d6f
+vncipher: 00007fffffffffff @@ 0000800000000000 ==> c455013fd31ea240
+ ffff000000000000 @@ 0000000000000000 ==> cf07ab5afc318d6f
+vncipher: 0000800000000000 @@ 0102030405060708 ==> 796e736035022f14
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> cfb37d6d48434c45
+vncipher: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 899e8390c5f2dfe4
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> 3f438d9db8b3bcb5
+vncipher: 0000800000000000 @@ 00007fffffffffff ==> 59913d75adadadad
+ 0000000000000000 @@ ffff000000000000 ==> c24c856352525252
+vncipher: 0000800000000000 @@ 0000800000000000 ==> 88a513be52525252
+ 0000000000000000 @@ 0000000000000000 ==> ec87545752525252
vncipherlast: 0102030405060708 @@ 0102030405060708 ==> 08f19dbb336cd089
090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 49afdef7d9ae363f
vncipherlast: 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> f8016d4bc39c2079
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> b95f2e07295ec6cf
+vncipherlast: 0102030405060708 @@ 00007fffffffffff ==> 09f3e140c995287e
+ 090a0b0c0e0d0e0f @@ ffff000000000000 ==> bf5ad5fbd7a33830
+vncipherlast: 0102030405060708 @@ 0000800000000000 ==> 09f31ebf366ad781
+ 090a0b0c0e0d0e0f @@ 0000000000000000 ==> 40a5d5fbd7a33830
vncipherlast: f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> 2a2360e572020b5d
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 60dc7571021928b5
vncipherlast: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> dad3901582f2fbad
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 902c8581f2e9d845
+vncipherlast: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff ==> 2b211c1e88fbf3aa
+ f9fafbfcfefdfeff @@ ffff000000000000 ==> 96297e7d0c1426ba
+vncipherlast: f1f2f3f4f5f6f7f8 @@ 0000800000000000 ==> 2b21e3e177040c55
+ f9fafbfcfefdfeff @@ 0000000000000000 ==> 69d67e7d0c1426ba
+vncipherlast: 00007fffffffffff @@ 0102030405060708 ==> 535051797854555a
+ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 7477605e5c707372
+vncipherlast: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> a3a0a18988a4a5aa
+ ffff000000000000 @@ f9fafbfcfefdfeff ==> 848790aeac808382
+vncipherlast: 00007fffffffffff @@ 00007fffffffffff ==> 52522d8282adadad
+ ffff000000000000 @@ ffff000000000000 ==> 82826b52527d7d7d
+vncipherlast: 00007fffffffffff @@ 0000800000000000 ==> 5252d27d7d525252
+ ffff000000000000 @@ 0000000000000000 ==> 7d7d6b52527d7d7d
+vncipherlast: 0000800000000000 @@ 0102030405060708 ==> 535051565754555a
+ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 5b58315e5c5f5c5d
+vncipherlast: 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> a3a0a1a6a7a4a5aa
+ 0000000000000000 @@ f9fafbfcfefdfeff ==> aba8c1aeacafacad
+vncipherlast: 0000800000000000 @@ 00007fffffffffff ==> 52522dadadadadad
+ 0000000000000000 @@ ffff000000000000 ==> adad3a5252525252
+vncipherlast: 0000800000000000 @@ 0000800000000000 ==> 5252d25252525252
+ 0000000000000000 @@ 0000000000000000 ==> 52523a5252525252
vmulouw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 00193c6aa4917040 00c56e34124ba4e1
vmulouw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 04d39d63184f87c0 0dfee4d8b9c6e2f1
@@ -300,6 +853,14 @@
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> fbfafdfffffcfffe
vpermxor: 0102030405060708 @@ f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> fdfcfbfaf9f8f7f6
090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> f5f4f3f1f1f2f1f0
+vpermxor: 0102030405060708 @@ 00007fffffffffff @@ 0102030405060708 ==> 017efefefefefefe
+ 090a0b0c0e0d0e0f @@ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> fe01010101010101
+vpermxor: 0102030405060708 @@ 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 0f70f0f0f0f0f0f0
+ 090a0b0c0e0d0e0f @@ ffff000000000000 @@ f9fafbfcfefdfeff ==> f00f0f0f0f0f0f0f
+vpermxor: 0102030405060708 @@ 0000800000000000 @@ 0102030405060708 ==> 0181010101010101
+ 090a0b0c0e0d0e0f @@ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0101010101010101
+vpermxor: 0102030405060708 @@ 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0f8f0f0f0f0f0f0f
+ 090a0b0c0e0d0e0f @@ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0f0f0f0f0f0f0f0f
vpermxor: f1f2f3f4f5f6f7f8 @@ 0102030405060708 @@ 0102030405060708 ==> f3f2f5f4f7f6f9f8
f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> fbfafdfffffcfffe
vpermxor: f1f2f3f4f5f6f7f8 @@ 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> fdfcfbfaf9f8f7f6
@@ -308,36 +869,96 @@
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> 0b0a0d0f0f0c0f0e
vpermxor: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> 0d0c0b0a09080706
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> 0504030101020100
+vpermxor: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff @@ 0102030405060708 ==> f18e0e0e0e0e0e0e
+ f9fafbfcfefdfeff @@ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> 0ef1f1f1f1f1f1f1
+vpermxor: f1f2f3f4f5f6f7f8 @@ 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> ff80000000000000
+ f9fafbfcfefdfeff @@ ffff000000000000 @@ f9fafbfcfefdfeff ==> 00ffffffffffffff
+vpermxor: f1f2f3f4f5f6f7f8 @@ 0000800000000000 @@ 0102030405060708 ==> f171f1f1f1f1f1f1
+ f9fafbfcfefdfeff @@ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> f1f1f1f1f1f1f1f1
+vpermxor: f1f2f3f4f5f6f7f8 @@ 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> ff7fffffffffffff
+ f9fafbfcfefdfeff @@ 0000000000000000 @@ f9fafbfcfefdfeff ==> ffffffffffffffff
+vpermxor: 00007fffffffffff @@ 0102030405060708 @@ 0102030405060708 ==> 0203040506070809
+ ffff000000000000 @@ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0a0b0c0e0e0d0e0f
+vpermxor: 00007fffffffffff @@ 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0203040506070809
+ ffff000000000000 @@ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0a0b0c0e0e0d0e0f
+vpermxor: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f2f3f4f5f6f7f8f9
+ ffff000000000000 @@ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> fafbfcfefefdfeff
+vpermxor: 00007fffffffffff @@ f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f2f3f4f5f6f7f8f9
+ ffff000000000000 @@ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> fafbfcfefefdfeff
+vpermxor: 00007fffffffffff @@ 00007fffffffffff @@ 0102030405060708 ==> 007fffffffffffff
+ ffff000000000000 @@ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> ff00000000000000
+vpermxor: 00007fffffffffff @@ 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 007fffffffffffff
+ ffff000000000000 @@ ffff000000000000 @@ f9fafbfcfefdfeff ==> ff00000000000000
+vpermxor: 00007fffffffffff @@ 0000800000000000 @@ 0102030405060708 ==> 0080000000000000
+ ffff000000000000 @@ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vpermxor: 00007fffffffffff @@ 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0080000000000000
+ ffff000000000000 @@ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
+vpermxor: 0000800000000000 @@ 0102030405060708 @@ 0102030405060708 ==> 0203040506070809
+ 0000000000000000 @@ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f ==> 0a0b0c0e0e0d0e0f
+vpermxor: 0000800000000000 @@ 0102030405060708 @@ f1f2f3f4f5f6f7f8 ==> 0203040506070809
+ 0000000000000000 @@ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff ==> 0a0b0c0e0e0d0e0f
+vpermxor: 0000800000000000 @@ f1f2f3f4f5f6f7f8 @@ 0102030405060708 ==> f2f3f4f5f6f7f8f9
+ 0000000000000000 @@ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f ==> fafbfcfefefdfeff
+vpermxor: 0000800000000000 @@ f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8 ==> f2f3f4f5f6f7f8f9
+ 0000000000000000 @@ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff ==> fafbfcfefefdfeff
+vpermxor: 0000800000000000 @@ 00007fffffffffff @@ 0102030405060708 ==> 007fffffffffffff
+ 0000000000000000 @@ ffff000000000000 @@ 090a0b0c0e0d0e0f ==> ff00000000000000
+vpermxor: 0000800000000000 @@ 00007fffffffffff @@ f1f2f3f4f5f6f7f8 ==> 007fffffffffffff
+ 0000000000000000 @@ ffff000000000000 @@ f9fafbfcfefdfeff ==> ff00000000000000
+vpermxor: 0000800000000000 @@ 0000800000000000 @@ 0102030405060708 ==> 0080000000000000
+ 0000000000000000 @@ 0000000000000000 @@ 090a0b0c0e0d0e0f ==> 0000000000000000
+vpermxor: 0000800000000000 @@ 0000800000000000 @@ f1f2f3f4f5f6f7f8 ==> 0080000000000000
+ 0000000000000000 @@ 0000000000000000 @@ f9fafbfcfefdfeff ==> 0000000000000000
vclzb: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 07060605050505040404040404040404
vclzb: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 00000000000000000000000000000000
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vclzw: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 00000000000000000000000000000000
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vclzh: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 00070006000500050004000400040004
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vpopcntb: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 05050605060607050606070607070708
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vpopcnth: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 000a000b000c000c000c000d000e000f
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vpopcntw: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 0000000500000008000000090000000d
vpopcntw: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 0000001500000018000000190000001d
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vsbox: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 7c777bf26b6fc53001672bfeabd7ab76
vsbox: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> a1890dbfe6426841992d0fb0bb54bb16
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vgbbd: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 00000000011e66aa00000000ff1f6ba5
vgbbd: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> ffffffff011e66aaffffffffff1f6ba5
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vshasigmad: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 986700cc8f5613df || 7a3f676a2ef03935
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vshasigmaw: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 88e344269168cdae || 9bf057355c5e785e
vshasigmaw: 0102030405060708 @@ 090a0b0c0e0d0e0f ==> 41e2c021c36443a2 || 44e5c72626c5e584
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vshasigmaw: f1f2f3f4f5f6f7f8 @@ f9fafbfcfefdfeff ==> 54200fe9e7b2997b || 71052acc5efb57bb
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+vaddecuq: 00008000000000000000000000000000 @@ 00008000000000000000000000000000 @@ f000000000000000 ==> 00000000000000000000000000000000
+vaddecuq: 00008000000000000000000000000000 @@ 00008000000000000000000000000000 @@ f000000000000001 ==> 00000000000000000000000000000000
vaddeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 020406080a0c0e10121416181c1a1c1e
vaddeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> 020406080a0c0e10121416181c1a1c1f
vaddeuqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> f2f4f6f8fafcff01030507090d0b0d0e
vaddeuqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> f2f4f6f8fafcff01030507090d0b0d0f
+vaddeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> 010283040506070809090b0c0e0d0e0f
+vaddeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> 010283040506070809090b0c0e0d0e10
+vaddeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 00008000000000000000000000000000 @@ f000000000000000 ==> 0102830405060708090a0b0c0e0d0e0f
+vaddeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 00008000000000000000000000000000 @@ f000000000000001 ==> 0102830405060708090a0b0c0e0d0e10
vaddeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> f2f4f6f8fafcff01030507090d0b0d0e
vaddeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> f2f4f6f8fafcff01030507090d0b0d0f
vaddeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> e3e5e7e9ebedeff1f3f5f7f9fdfbfdfe
vaddeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> e3e5e7e9ebedeff1f3f5f7f9fdfbfdff
+vaddeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> f1f373f4f5f6f7f8f9f9fbfcfefdfeff
+vaddeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> f1f373f4f5f6f7f8f9f9fbfcfefdff00
+vaddeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00008000000000000000000000000000 @@ f000000000000000 ==> f1f373f4f5f6f7f8f9fafbfcfefdfeff
+vaddeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00008000000000000000000000000000 @@ f000000000000001 ==> f1f373f4f5f6f7f8f9fafbfcfefdff00
+vaddeuqm: 00007fffffffffffffff000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 010283040506070809090b0c0e0d0e0f
+vaddeuqm: 00007fffffffffffffff000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> 010283040506070809090b0c0e0d0e10
+vaddeuqm: 00007fffffffffffffff000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> f1f373f4f5f6f7f8f9f9fbfcfefdfeff
+vaddeuqm: 00007fffffffffffffff000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> f1f373f4f5f6f7f8f9f9fbfcfefdff00
+vaddeuqm: 00007fffffffffffffff000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> 0000fffffffffffffffe000000000000
+vaddeuqm: 00007fffffffffffffff000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> 0000fffffffffffffffe000000000001
+vaddeuqm: 00007fffffffffffffff000000000000 @@ 00008000000000000000000000000000 @@ f000000000000000 ==> 0000ffffffffffffffff000000000000
+vaddeuqm: 00007fffffffffffffff000000000000 @@ 00008000000000000000000000000000 @@ f000000000000001 ==> 0000ffffffffffffffff000000000001
+vaddeuqm: 00008000000000000000000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 0102830405060708090a0b0c0e0d0e0f
+vaddeuqm: 00008000000000000000000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> 0102830405060708090a0b0c0e0d0e10
+vaddeuqm: 00008000000000000000000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> f1f373f4f5f6f7f8f9fafbfcfefdfeff
+vaddeuqm: 00008000000000000000000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> f1f373f4f5f6f7f8f9fafbfcfefdff00
+vaddeuqm: 00008000000000000000000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> 0000ffffffffffffffff000000000000
+vaddeuqm: 00008000000000000000000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> 0000ffffffffffffffff000000000001
+vaddeuqm: 00008000000000000000000000000000 @@ 00008000000000000000000000000000 @@ f000000000000000 ==> 00010000000000000000000000000000
+vaddeuqm: 00008000000000000000000000000000 @@ 00008000000000000000000000000000 @@ f000000000000001 ==> 00010000000000000000000000000001
vsubecuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000000
vsubecuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> 00000000000000000000000000000001
vsubecuq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> 00000000000000000000000000000000
vsubecuq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 00000000000000000000000000000000
+vsubecuq: 0102030405060708090a0b0c0e0d0e0f @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> 00000000000000000000000000000001
+vsubecuq: 0102030405060708090a0b0c0e0d0e0f @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> 00000000000000000000000000000001
+vsubecuq: 0102030405060708090a0b0c0e0d0e0f @@ 00008000000000000000000000000000 @@ f000000000000000 ==> 00000000000000000000000000000001
+vsubecuq: 0102030405060708090a0b0c0e0d0e0f @@ 00008000000000000000000000000000 @@ f000000000000001 ==> 00000000000000000000000000000001
vsubecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000001
vsubecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> 00000000000000000000000000000001
vsubecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> 00000000000000000000000000000000
vsubecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 00000000000000000000000000000001
+vsubecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> 00000000000000000000000000000001
+vsubecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> 00000000000000000000000000000001
+vsubecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00008000000000000000000000000000 @@ f000000000000000 ==> 00000000000000000000000000000001
+vsubecuq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00008000000000000000000000000000 @@ f000000000000001 ==> 00000000000000000000000000000001
+vsubecuq: 00007fffffffffffffff000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000000
+vsubecuq: 00007fffffffffffffff000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> 00000000000000000000000000000000
+vsubecuq: 00007fffffffffffffff000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> 00000000000000000000000000000000
+vsubecuq: 00007fffffffffffffff000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 00000000000000000000000000000000
+vsubecuq: 00007fffffffffffffff000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> 00000000000000000000000000000000
+vsubecuq: 00007fffffffffffffff000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> 00000000000000000000000000000001
+vsubecuq: 00007fffffffffffffff000000000000 @@ 00008000000000000000000000000000 @@ f000000000000000 ==> 00000000000000000000000000000000
+vsubecuq: 00007fffffffffffffff000000000000 @@ 00008000000000000000000000000000 @@ f000000000000001 ==> 00000000000000000000000000000000
+vsubecuq: 00008000000000000000000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000000
+vsubecuq: 00008000000000000000000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> 00000000000000000000000000000000
+vsubecuq: 00008000000000000000000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> 00000000000000000000000000000000
+vsubecuq: 00008000000000000000000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 00000000000000000000000000000000
+vsubecuq: 00008000000000000000000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> 00000000000000000000000000000001
+vsubecuq: 00008000000000000000000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> 00000000000000000000000000000001
+vsubecuq: 00008000000000000000000000000000 @@ 00008000000000000000000000000000 @@ f000000000000000 ==> 00000000000000000000000000000000
+vsubecuq: 00008000000000000000000000000000 @@ 00008000000000000000000000000000 @@ f000000000000001 ==> 00000000000000000000000000000001
vsubeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> ffffffffffffffffffffffffffffffff
vsubeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> 00000000000000000000000000000000
vsubeuqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> 0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f
vsubeuqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f10
+vsubeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> 0101830405060708090b0b0c0e0d0e0e
+vsubeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> 0101830405060708090b0b0c0e0d0e0f
+vsubeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 00008000000000000000000000000000 @@ f000000000000000 ==> 0101830405060708090a0b0c0e0d0e0e
+vsubeuqm: 0102030405060708090a0b0c0e0d0e0f @@ 00008000000000000000000000000000 @@ f000000000000001 ==> 0101830405060708090a0b0c0e0d0e0f
vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0ef
vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0
vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> ffffffffffffffffffffffffffffffff
vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 00000000000000000000000000000000
+vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> f1f273f4f5f6f7f8f9fbfbfcfefdfefe
+vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> f1f273f4f5f6f7f8f9fbfbfcfefdfeff
+vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00008000000000000000000000000000 @@ f000000000000000 ==> f1f273f4f5f6f7f8f9fafbfcfefdfefe
+vsubeuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 00008000000000000000000000000000 @@ f000000000000001 ==> f1f273f4f5f6f7f8f9fafbfcfefdfeff
+vsubeuqm: 00007fffffffffffffff000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> fefe7cfbfaf9f8f7f6f4f4f3f1f2f1f0
+vsubeuqm: 00007fffffffffffffff000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> fefe7cfbfaf9f8f7f6f4f4f3f1f2f1f1
+vsubeuqm: 00007fffffffffffffff000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> 0e0d8c0b0a0908070604040301020100
+vsubeuqm: 00007fffffffffffffff000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 0e0d8c0b0a0908070604040301020101
+vsubeuqm: 00007fffffffffffffff000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> ffffffffffffffffffffffffffffffff
+vsubeuqm: 00007fffffffffffffff000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> 00000000000000000000000000000000
+vsubeuqm: 00007fffffffffffffff000000000000 @@ 00008000000000000000000000000000 @@ f000000000000000 ==> fffffffffffffffffffeffffffffffff
+vsubeuqm: 00007fffffffffffffff000000000000 @@ 00008000000000000000000000000000 @@ f000000000000001 ==> ffffffffffffffffffff000000000000
+vsubeuqm: 00008000000000000000000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> fefe7cfbfaf9f8f7f6f5f4f3f1f2f1f0
+vsubeuqm: 00008000000000000000000000000000 @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000001 ==> fefe7cfbfaf9f8f7f6f5f4f3f1f2f1f1
+vsubeuqm: 00008000000000000000000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000000 ==> 0e0d8c0b0a0908070605040301020100
+vsubeuqm: 00008000000000000000000000000000 @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f000000000000001 ==> 0e0d8c0b0a0908070605040301020101
+vsubeuqm: 00008000000000000000000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000000 ==> 00000000000000000000ffffffffffff
+vsubeuqm: 00008000000000000000000000000000 @@ 00007fffffffffffffff000000000000 @@ f000000000000001 ==> 00000000000000000001000000000000
+vsubeuqm: 00008000000000000000000000000000 @@ 00008000000000000000000000000000 @@ f000000000000000 ==> ffffffffffffffffffffffffffffffff
+vsubeuqm: 00008000000000000000000000000000 @@ 00008000000000000000000000000000 @@ f000000000000001 ==> 00000000000000000000000000000000
All done. Tested 66 different instructions
diff --git a/none/tests/ppc64/ldst_multiple.c b/none/tests/ppc64/ldst_multiple.c
deleted file mode 120000
index d155824..0000000
--- a/none/tests/ppc64/ldst_multiple.c
+++ /dev/null
@@ -1 +0,0 @@
-../ppc32/ldst_multiple.c
\ No newline at end of file
diff --git a/none/tests/ppc64/ldst_multiple.c b/none/tests/ppc64/ldst_multiple.c
new file mode 100644
index 0000000..90f4c57
--- /dev/null
+++ b/none/tests/ppc64/ldst_multiple.c
@@ -0,0 +1,195 @@
+#include <stdio.h>
+#include <stdint.h>
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif
+
+typedef void (*test_func_t)();
+
+typedef struct test_table {
+ test_func_t func;
+ char *name;
+} test_table_t;
+
+static uint32_t values[] = {
+ 0x6efbcfdf,
+ 0xd16c2fd4,
+ 0xf9dc1743,
+ 0xa5aa0bd4,
+ 0x6c8f0c14,
+ 0x69a24188,
+ 0x53b57f1b,
+};
+
+register HWord_t r27 asm("r27");
+register HWord_t r28 asm("r28");
+register HWord_t r29 asm("r29");
+register HWord_t r30 asm("r30");
+register HWord_t r31 asm("r31");
+
+register HWord_t r14 asm("r14");
+
+HWord_t temp[5];
+
+#ifdef __powerpc64__
+
+#define SAVE_REGS(addr) \
+ asm volatile( \
+ " std 27, 0(%0) \n" \
+ " std 28, 8(%0) \n" \
+ " std 29, 16(%0) \n" \
+ " std 30, 24(%0) \n" \
+ " std 31, 32(%0) \n" \
+ ::"b"(addr))
+
+#define RESTORE_REGS(addr) \
+ asm volatile( \
+ " ld 27, 0(%0) \n" \
+ " ld 28, 8(%0) \n" \
+ " ld 29, 16(%0) \n" \
+ " ld 30, 24(%0) \n" \
+ " ld 31, 32(%0) \n" \
+ ::"b"(addr))
+
+#else /* !__powerpc64__ */
+
+#define SAVE_REGS(addr) \
+ asm volatile( \
+ " stw 27, 0(%0) \n" \
+ " stw 28, 4(%0) \n" \
+ " stw 29, 8(%0) \n" \
+ " stw 30, 12(%0) \n" \
+ " stw 31, 16(%0) \n" \
+ ::"b"(addr))
+
+#define RESTORE_REGS(addr) \
+ asm volatile( \
+ " lwz 27, 0(%0) \n" \
+ " lwz 28, 4(%0) \n" \
+ " lwz 29, 8(%0) \n" \
+ " lwz 30, 12(%0) \n" \
+ " lwz 31, 16(%0) \n" \
+ ::"b"(addr))
+
+#endif /* __powerpc64__ */
+
+/*
+ * gcc is not happy if we modify r31 (the frame pointer) behind its back
+ * so we omit it
+ */
+static void __attribute__((optimize("-fomit-frame-pointer"))) test_lmw(void)
+{
+ r14 = (HWord_t)values;
+
+ /* save r27 - r31 */
+ SAVE_REGS(temp);
+
+ /* load r27 - r31 */
+ asm volatile(
+ " lmw %r27, 0(%r14) \n");
+
+#ifdef __powerpc64__
+ printf("lmw => %016lx %016lx %016lx %016lx %016lx\n",
+#else
+ printf("lmw => %08x %08x %08x %08x %08x\n",
+#endif
+ r27, r28, r29, r30, r31);
+
+ /*
+ * test load multiple with nonzero immediate offset
+ * load the last two values into r30 - r31.
+ * r27 - r29 should remain the same
+ */
+ asm volatile(
+ " lmw %r30, 20(%r14) \n");
+
+#ifdef __powerpc64__
+ printf("lmw => %016lx %016lx %016lx %016lx %016lx\n",
+#else
+ printf("lmw => %08x %08x %08x %08x %08x\n",
+#endif
+ r27, r28, r29, r30, r31);
+
+ /* restore r27 - r31 */
+ RESTORE_REGS(temp);
+}
+
+/*
+ * gcc is not happy if we modify r31 (the frame pointer) behind its back
+ * so we omit it
+ */
+static void __attribute__((optimize("-fomit-frame-pointer"))) test_stmw(void)
+{
+ uint32_t result[7] = { 0 };
+ int i;
+
+ SAVE_REGS(temp);
+
+#ifdef __powerpc64__
+ asm volatile(
+ " lwz 27, 0(%0) \n" \
+ " lwz 28, 4(%0) \n" \
+ " lwz 29, 8(%0) \n" \
+ " lwz 30, 12(%0) \n" \
+ " lwz 31, 16(%0) \n" \
+ ::"b"(values));
+#else
+ RESTORE_REGS(values);
+#endif
+
+ r14 = (HWord_t)&result;
+
+ /* store r27 - r31 */
+ asm volatile(
+ " stmw %r27, 0(%r14) \n");
+
+ printf("stmw => ");
+ for (i = 0; i < sizeof(result) / sizeof(result[0]); i++)
+ printf("%08x ", result[i]);
+
+ printf("\n");
+
+ /*
+ * test store multiple with nonzero immediate offset
+ * store r30 - r31 into the last two places in the array
+ * the rest of the array should remain the same
+ */
+ asm volatile(
+ " stmw %r30, 20(%r14) \n");
+
+ printf("stmw => ");
+ for (i = 0; i < sizeof(result) / sizeof(result[0]); i++)
+ printf("%08x ", result[i]);
+
+ printf("\n");
+
+ RESTORE_REGS(temp);
+}
+
+static test_table_t all_tests[] = {
+ { &test_lmw,
+ "Test Load Multiple instruction" },
+ { &test_stmw,
+ "Test Store Multiple instruction" },
+ { NULL, NULL },
+};
+
+/*
+ * gcc is not happy if we modify r31 (the frame pointer) behind its back
+ * so we omit it
+ */
+int __attribute__((optimize("-fomit-frame-pointer"))) main(void)
+{
+ test_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].func)) {
+ (*func)();
+ i++;
+ }
+
+ return 0;
+}
diff --git a/none/tests/ppc64/opcodes.h b/none/tests/ppc64/opcodes.h
deleted file mode 120000
index dcedf47..0000000
--- a/none/tests/ppc64/opcodes.h
+++ /dev/null
@@ -1 +0,0 @@
-../ppc32/opcodes.h
\ No newline at end of file
diff --git a/none/tests/ppc64/opcodes.h b/none/tests/ppc64/opcodes.h
new file mode 100644
index 0000000..fea9210
--- /dev/null
+++ b/none/tests/ppc64/opcodes.h
@@ -0,0 +1,56 @@
+#ifndef OPCODES_H
+#define OPCODES_H
+
+/* (Along the lines of ../s390x/opcodes.h) Macro definitions to hand-assemble
+ * instructions known to cause problems with assemblers or across assembler
+ * versions.
+ *
+ * Notes:
+ *
+ * 0. Offsets used in encodings are in Valgrind (Right to Left) ordering.
+ * 1. Use register numbers, not register names in macro invocations.
+ * 2. Insert the definitions for a new instruction/instruction format in
+ * the order of the appearance of its definition in the Power ISA.
+ */
+
+/* Instruction formats:
+ */
+
+/* Power ISA Version 2.07 (May 3, 2013). pp. 15: X-FORM */
+#define X20_ASM_DIRECTIVE ".long"
+#define X20_OPCODE_OFFSET "26"
+#define X20_TH_OFFSET "21"
+#define X20_RA_OFFSET "16"
+#define X20_RB_OFFSET "11"
+#define X20_XO_OFFSET "1"
+#define X20_RES_OFFSET "0"
+
+#define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \
+ X20_ASM_DIRECTIVE " " \
+ "(" #OPCODE "<<" X20_OPCODE_OFFSET ")" "+" \
+ "(" #TH "<<" X20_TH_OFFSET ")" "+" \
+ "(" #RA "<<" X20_RA_OFFSET ")" "+" \
+ "(" #RB "<<" X20_RB_OFFSET ")" "+" \
+ "(" #XO "<<" X20_XO_OFFSET ")" "+" \
+ "(" #RES "<<" X20_RES_OFFSET ")"
+
+#define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES)
+
+/* Instruction specifics:
+ */
+
+/* Power ISA Version 2.07 (May 3, 2013). pp. 770: dcbt (Category: Server Syntax) */
+#define DCBT_OPCODE 31
+#define DCBT_XO 278
+#define DCBT_RES 0
+#define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES)
+#define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH))
+
+/* Power ISA Version 2.07 (May 3, 2013). pp. 771: dcbtst (Category: Server Syntax) */
+#define DCBTST_OPCODE 31
+#define DCBTST_XO 246
+#define DCBTST_RES 0
+#define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, RB, DCBTST_XO, DCBTST_RES)
+#define ASM_DCBTST(RA, RB, TH) __asm__ __volatile__ (DCBTST_S(RA, RB, TH))
+
+#endif /* OPCODES_H */
diff --git a/none/tests/ppc64/ppc64_helpers.h b/none/tests/ppc64/ppc64_helpers.h
new file mode 100644
index 0000000..8dca231
--- /dev/null
+++ b/none/tests/ppc64/ppc64_helpers.h
@@ -0,0 +1,2408 @@
+/*
+ * ppc64_helpers.h
+ * Copyright (c) 2016 Will Schmidt <will_schmidt@vnet.ibm.com>
+ *
+ * This file contains helper functions for the ISA 3.0 test suite.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License V2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include "tests/malloc.h" // memalign32
+
+typedef uint64_t HWord_t;
+
+#if defined (DEBUG_ARGS_BUILD)
+#define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define AB_DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+/* Exhaustive tests?
+ * Due to the excessive size of the test results, allow a #ifdef to
+ * enable/disable most of the input values.
+ * Off by default.
+ */
+// #define EXHAUSTIVE_TESTS 1
+
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_CR0_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x80,%0 " : : "b" (_arg):"cr0");
+#define SET_CR1_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x40,%0 " : : "b" (_arg):"cr1");
+#define SET_CR2_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x20,%0 " : : "b" (_arg):"cr2");
+#define SET_CR3_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x10,%0 " : : "b" (_arg):"cr3");
+#define SET_CR4_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x08,%0 " : : "r" (_arg):"cr4");
+#define SET_CR5_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x04,%0 " : : "r" (_arg):"cr5");
+#define SET_CR6_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x02,%0 " : : "r" (_arg):"cr6");
+#define SET_CR7_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x01,%0 " : : "r" (_arg):"cr7");
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_FPSCR_ZERO \
+ do { \
+ double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0);
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) );
+
+/* The bit definitions for the FPSCR are as follows.
+Bit(s) Description
+0:31 Reserved
+32 Floating-Point Exception Summary (FX)
+33 Floating-Point Enabled Exception Summary (FEX)
+34 Floating-Point Invalid Operation Exception Summary (VX)
+35 Floating-Point Overflow Exception (OX)
+36 Floating-Point Underflow Exception (UX)
+37 Floating-Point Zero Divide Exception (ZX)
+38 Floating-Point Inexact Exception (XX)
+39 Floating-Point Invalid Operation Exception (SNaN) (VXSNAN)
+40 Floating-Point Invalid Operation Exception (∞ - ∞) (VXISI)
+41 Floating-Point Invalid Operation Exception (∞ ÷ ∞) (VXIDI)
+42 Floating-Point Invalid Operation Exception (0 ÷ 0) (VXZDZ)
+43 Floating-Point Invalid Operation Exception (∞ × 0) (VXIMZ)
+44 Floating-Point Invalid Operation Exception (Invalid Compare) (VXVC)
+45 Floating-Point Fraction Rounded (FR)
+46 Floating-Point Fraction Inexact (FI)
+47:51 Floating-Point Result Flags (FPRF)
+47 Floating-Point Result Class Descriptor (C)
+48:51 Floating-Point Condition Code (FPCC)
+ 48 Floating-Point Less Than or Negative (FL or <)
+ 49 Floating-Point Greater Than or Positive (FG or >)
+ 50 Floating-Point Equal or Zero (FE or =)
+ 51 Floating-Point Unordered or NaN (FU or ?)
+52 Reserved
+53 Floating-Point Invalid Operation Exception (Software-Defined Condition) (VXSOFT)
+54 Floating-Point Invalid Operation Exception (Invalid Square Root) (VXSQRT)
+55 Floating-Point Invalid Operation Exception (Invalid Integer Convert) (VXCVI)
+56 Floating-Point Invalid Operation Exception Enable (VE)
+57 Floating-Point Overflow Exception Enable (OE)
+58 Floating-Point Underflow Exception Enable (UE)
+59 Floating-Point Zero Divide Exception Enable (ZE)
+60 Floating-Point Inexact Exception Enable (XE)
+61 Floating-Point Non-IEEE Mode (NI)
+62:63 Floating-Point Rounding Control (RN)
+ 00 Round to Nearest
+ 01 Round toward Zero
+ 10 Round toward +Infinity
+ 11 Round toward -Infinity
+*/
+/* NOTE, currently Valgrind only tracks the rounding mode, C and FPCC fields in the
+ * FPSCR register.
+ */
+
+static char * fpscr_strings[] = {
+" 0-RSVD", " 1-RSVD", " 2-RSVD", " 3-RSVD", " 4-RSVD", " 5-RSVD", " 6-RSVD",
+" 7-RSVD", " 8-RSVD", " 9-RSVD", "10-RSVD", "11-RSVD", "12-RSVD", "13-RSVD",
+"14-RSVD", "15-RSVD", "16-RSVD", "17-RSVD", "18-RSVD", "19-RSVD", "20-RSVD",
+"21-RSVD", "22-RSVD", "23-RSVD", "24-RSVD", "25-RSVD", "26-RSVD", "27-RSVD",
+"28-RSVD", "29-RSVD", "30-RSVD", "31-RSVD",
+/* 32 */ "FX", "FEX", "VX",
+/* 35 */ "OX", "UX", "ZX", "XX", "VXSNAN",
+/* 40 */ "VXISI (inf-inf)", "VXIDI (inf/inf)", "VXZDZ (0/0)",
+/* 43 */ "VXIMZ (inf*0)", "VXVC",
+/* 45 */ "FR", "FI",
+/* 47 */ "FPRF-C", "FPCC-FL", "FPCC-FG",
+/* 50 */ "FPCC-FE", "FPCC-FU",
+/* 52 */ "52-RSVD", "FXSOFT", "VXSQRT",
+/* 55 */ "VXCVI", "VE", "OE", "UE", "ZE",
+/* 60 */ "XE", "NI", "RN-bit62", "RN-bit63"
+};
+
+#define FPCC_C_BIT (0x1 << (63-47))
+#define FPCC_FL_BIT (0x1 << (63-48))
+#define FPCC_FG_BIT (0x1 << (63-49))
+#define FPCC_FE_BIT (0x1 << (63-50))
+#define FPCC_FU_BIT (0x1 << (63-51))
+#define FPCC_FPRF_MASK FPCC_C_BIT|FPCC_FL_BIT|FPCC_FG_BIT|FPCC_FE_BIT|FPCC_FU_BIT
+
+#define FPSCR_RN_BIT62 (0x1 << (63-62))
+#define FPSCR_RN_BIT63 (0x1 << (63-63))
+
+#define CRFIELD_BIT0 0x8
+#define CRFIELD_BIT1 0x4
+#define CRFIELD_BIT2 0x2
+#define CRFIELD_BIT3 0x1
+
+/* dissect_cr*:
+ * display the condition register bits in a
+ * human readable format.
+ */
+
+inline int cr_overflow_set(unsigned this_cr) {
+ return (this_cr & CRFIELD_BIT3);
+}
+
+inline int cr_zero_set(unsigned this_cr) {
+ return (this_cr & CRFIELD_BIT2);
+}
+
+inline int cr_positive_set(unsigned this_cr) {
+ return (this_cr & CRFIELD_BIT1);
+}
+
+inline int cr_negative_set(unsigned this_cr) {
+ return (this_cr & CRFIELD_BIT0);
+}
+
+/* __dissect_cr takes a bitfield directly, not the full condition register.
+ * This is a helper for dissect_cr_rn.
+ */
+inline static void __dissect_cr(unsigned this_cr) {
+if (cr_negative_set(this_cr))
+ printf("%s(LT)", verbose ? " 0x1=Negative" : "");
+
+if (cr_positive_set(this_cr))
+ printf("%s(GT)", verbose ? " 0x2=Positive" : "");
+
+if (cr_zero_set(this_cr))
+ printf("%s(EQ)", verbose ? " 0x4=Zero" : "");
+
+if (cr_overflow_set(this_cr))
+ printf("%s(SO)", verbose ? " 0x8=Overflow" : "");
+}
+
+/* Extract one CR field */
+static int extract_cr_rn(unsigned long local_cr,unsigned long rn) {
+ unsigned int masked_cr;
+ unsigned long shifted_value;
+
+ shifted_value = local_cr >> ( ( (7 - rn) * 4 ) );
+ masked_cr = shifted_value & 0xf;
+ return masked_cr;
+}
+
+/* Display one CR field */
+static void dissect_cr_rn(unsigned long local_cr, unsigned long rn) {
+ unsigned int masked_cr;
+
+ masked_cr = extract_cr_rn(local_cr, rn);
+ __dissect_cr(masked_cr);
+}
+
+/* Display all of the CR fields... */
+static void dissect_cr(unsigned long local_cr) {
+ unsigned int crn;
+
+ for (crn = 0; crn < 8; crn++) {
+ dissect_cr_rn(local_cr, crn);
+ }
+}
+
+/* dissect the fpscr bits that are valid under valgrind.
+ * Valgrind itself only tracks the C and FPCC fields from the
+ * FPSCR.
+ */
+static void dissect_fpscr_valgrind(unsigned long local_fpscr) {
+ int i;
+ int mybit;
+
+ for (i = 47; i < 52; i++) {
+ mybit = 1 << (63 - i);
+ if (mybit & local_fpscr) {
+ printf(" %s",fpscr_strings[i]);
+ }
+ }
+}
+
+/* dissect the fpscr bits.
+ * This prints the entire FPSCR field. This is only called under higher
+ * verbosities, as valgrind does not track most of these bits.
+ */
+static void dissect_fpscr_raw(unsigned long local_fpscr) {
+/* Due to the additional involved logic, the rounding mode (RN) bits 61-62
+ * are handled within dissect_fpscr_rounding_mode(). */
+ int i;
+ int mybit;
+
+ for (i = 0; i < 61; i++) {
+ /* also note that the bit numbering is backwards. */
+ mybit = 1 << (63 - i);
+ if (mybit & local_fpscr) {
+ printf(" %s", fpscr_strings[i]);
+ }
+ }
+}
+
+static void dissect_fpscr(unsigned long local_fpscr) {
+ if (verbose > 1) {
+ printf(" [[ fpscr:%lx ]] ", local_fpscr);
+ dissect_fpscr_raw(local_fpscr);
+ } else {
+ dissect_fpscr_valgrind(local_fpscr);
+ }
+}
+
+/* Display the rounding mode */
+static void dissect_fpscr_rounding_mode(unsigned long local_fpscr) {
+ /* special case handing for the rounding mode round-nearest (RN) bits. 62:63 */
+ printf("Rounding Mode: ");
+
+ if (local_fpscr & FPSCR_RN_BIT62)
+ if (local_fpscr & FPSCR_RN_BIT63)
+ /* 0b11 */ printf("RN-to--INF");
+ else
+ /* 0b10 */ printf("RN-to-+INF");
+ else
+ if (local_fpscr & FPSCR_RN_BIT63)
+ /* 0b01 */ printf("RN-to-Nearest");
+ else
+ /* 0b00 */ printf("RN-to-Zero");
+}
+
+/*
+ * Arithmetic, rounding, and Convert From Integer instructions will set
+ * bits in the FPCC field to indicate the class of the result.
+ * The table is described as follows;
+ flags / Result value class
+ C < > = ?
+ 1 0 0 0 1 Quiet NaN
+ 0 1 0 0 1 -Infinity
+ 0 1 0 0 0 -Normalized Number
+ 1 1 0 0 0 -Denormalized Number
+ 1 0 0 1 0 -Zero
+ 0 0 0 1 0 +Zero
+ 1 0 1 0 0 +Denormalized Number
+ 0 0 1 0 0 +Normalized Number
+ 0 0 1 0 1 +Infinity
+*/
+
+static void dissect_fpscr_result_value_class(unsigned long local_fpscr) {
+ if (local_fpscr & FPCC_C_BIT) {
+ if (local_fpscr & FPCC_FL_BIT)
+ printf("-Denormalized");
+
+ else if (local_fpscr & FPCC_FG_BIT)
+ printf("+Denormalized");
+
+ else if (local_fpscr & FPCC_FE_BIT)
+ printf("-Zero ");
+
+ else if (local_fpscr & FPCC_FU_BIT)
+ printf("Quiet NaN ");
+
+ } else {
+ if (local_fpscr & FPCC_FL_BIT) {
+ if (local_fpscr & FPCC_FU_BIT)
+ printf("-Infinity ");
+
+ else
+ printf("-Normalized ");
+
+ } else if (local_fpscr & FPCC_FG_BIT) {
+ if (local_fpscr & FPCC_FU_BIT)
+ printf("+Infinity ");
+
+ else
+ printf("+Normalized ");
+
+ if (local_fpscr & FPCC_FE_BIT)
+ printf("+Zero ");
+ }
+ }
+}
+
+/* Interpret the fields in the FPCC as they apply to the DCMX checks.
+ * The 'Match' indicator will typically be evaluated by the caller.
+ *
+ * DMCX:
+ * DCMX bit / 0x value / Data Class
+ * 0 0x01 NaN
+ * 1 0x02 +Infinity
+ * 2 0x04 -Infinity
+ * 3 0x08 +Zero
+ * 4 0x10 -Zero
+ * 5 0x20 +Denormal
+ * 6 0x40 -Denormal
+ * 7 0x7f ALL bits set.
+*/
+
+static void dissect_fpscr_dcmx_indicator(unsigned long local_fpscr) {
+ if (verbose > 2) printf("fpscr_cc:%lx ", local_fpscr & (FPCC_FPRF_MASK) );
+
+ // See if the data class of the src value matches the set DCMX bits.
+ if (verbose > 1) printf("%s ", (local_fpscr&FPCC_FE_BIT) ? "Match":"");
+
+ // Display the sign bit of the src value.
+ if (verbose > 1) printf("SRC sign:%s ", (local_fpscr&FPCC_FL_BIT) ? "-" : "+");
+
+ // The src value can be either a SP or DP value, this indicates
+ // if it is a valid SP value.
+ if (verbose > 1) printf("%s ", (local_fpscr&FPCC_FE_BIT) ? "SP" : "");
+}
+
+/* DFP helpers for bcd-to-dpd, dpd-to-bcd, misc.
+ * pulled from vex/.../host_generic_simd64.c
+ */
+/*------------------------------------------------------------------*/
+/* Decimal Floating Point (DFP) helper functions */
+/*------------------------------------------------------------------*/
+#define NOT( x ) ( ( ( x ) == 0) ? 1 : 0)
+#define GET( x, y ) ( ( ( x ) & ( 0x1UL << ( y ) ) ) >> ( y ) )
+#define PUT( x, y ) ( ( x )<< ( y ) )
+
+static unsigned long dpb_to_bcd( unsigned long chunk )
+{
+ int a, b, c, d, e, f, g, h, i, j, k, m;
+ int p, q, r, s, t, u, v, w, x, y;
+ unsigned long value;
+
+ /* convert 10 bit densely packed BCD to BCD */
+ p = GET( chunk, 9 );
+ q = GET( chunk, 8 );
+ r = GET( chunk, 7 );
+ s = GET( chunk, 6 );
+ t = GET( chunk, 5 );
+ u = GET( chunk, 4 );
+ v = GET( chunk, 3 );
+ w = GET( chunk, 2 );
+ x = GET( chunk, 1 );
+ y = GET( chunk, 0 );
+
+ /* The BCD bit values are given by the following boolean equations.*/
+ a = ( NOT(s) & v & w ) | ( t & v & w & s ) | ( v & w & NOT(x) );
+ b = ( p & s & x & NOT(t) ) | ( p & NOT(w) ) | ( p & NOT(v) );
+ c = ( q & s & x & NOT(t) ) | ( q & NOT(w) ) | ( q & NOT(v) );
+ d = r;
+ e = ( v & NOT(w) & x ) | ( s & v & w & x ) | ( NOT(t) & v & x & w );
+ f = ( p & t & v & w & x & NOT(s) ) | ( s & NOT(x) & v ) | ( s & NOT(v) );
+ g = ( q & t & w & v & x & NOT(s) ) | ( t & NOT(x) & v ) | ( t & NOT(v) );
+ h = u;
+ i = ( t & v & w & x ) | ( s & v & w & x ) | ( v & NOT(w) & NOT(x) );
+ j = ( p & NOT(s) & NOT(t) & w & v ) | ( s & v & NOT(w) & x )
+ | ( p & w & NOT(x) & v ) | ( w & NOT(v) );
+ k = ( q & NOT(s) & NOT(t) & v & w ) | ( t & v & NOT(w) & x )
+ | ( q & v & w & NOT(x) ) | ( x & NOT(v) );
+ m = y;
+
+ value = PUT(a, 11) | PUT(b, 10) | PUT(c, 9) | PUT(d, 8) | PUT(e, 7)
+ | PUT(f, 6) | PUT(g, 5) | PUT(h, 4) | PUT(i, 3) | PUT(j, 2)
+ | PUT(k, 1) | PUT(m, 0);
+ return value;
+}
+#undef NOT
+#undef GET
+#undef PUT
+
+
+typedef union dfp_union {
+ _Decimal128 dec_val128;
+ struct {
+#if defined(VGP_ppc64le_linux)
+ unsigned long vall;
+ unsigned long valu;
+#else
+ unsigned long valu;
+ unsigned long vall;
+#endif
+ } u128;
+} dfp_val_t;
+
+/* Based on and enhanced from the dfp128_vals table in test_dfp5.c.
+ * Todo: Refine/refactor and turn into a build_table function.
+ */
+
+static unsigned long dfp128_vals[] = {
+#ifdef EXHAUSTIVE_TESTS
+ // Some finite numbers
+ 0x2208000000000000ULL, 0x0000000000000001ULL, // 1 *10^0
+ 0xa208800000000000ULL, 0x0000000000000001ULL, // -1 *10^1
+ 0x0000000000000000ULL, 0x0000000000000001ULL, // 1 *10^-6176. (smallest exp)
+ 0x43ffc00000000000ULL, 0x0000000000000001ULL, // 1 *10^6111
+ 0x6fffc00000000000ULL, 0x0000000000000001ULL, // foo *10^2015.
+ 0x67ffc00000000000ULL, 0x0000000000000001ULL, // foo *10^-2081.
+ 0x77ffc00000000000ULL, 0x0000000000000001ULL, // 1 *10^6111 (largest exp)
+ 0x77ffffffffffffffULL, 0xffffffffffffffffULL, // max possible value *10^6111 (largest exp)
+ 0x0000000000000000ULL, 0x0000000000000001ULL, // min possible value 1 *10^-6176. (smallest exp)
+ 0x8000000000000000ULL, 0x0000000000000001ULL, // -1 *10^-6176. (smallest exp)
+
+ /* data bits sprinkled across the significand field. */
+ 0xa208800001000000ULL, 0x0000000000010000ULL, //-foo *10^1
+ 0xa208800000000100ULL, 0x0000000000000100ULL, //-foo *10^1
+ 0xa208800000000000ULL, 0x0000100000000000ULL, //-foo *10^1
+ 0xa208800000000000ULL, 0x0000000001000000ULL, //-foo *10^1
+ 0xa208800000000000ULL, 0x0000000000000001ULL, //-foo *10^1
+
+ // pre-existing dfp128 values:
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL, // foo * 10^-1
+ 0x2207c00000000000ULL, 0x000000000014c000ULL, // foo * 10^-1
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL, // foo * 10^-1
+ 0x2206c00000000000ULL, 0x00000000000000cfULL, // foo * 10^-5
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL, // foo * 10^-9
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // foo * 10^-4091
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number // foo * 10^-6160
+
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL, // 0*10^256
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // -0*10^0
+ 0xa248000000000000ULL, 0x0000000000000000ULL, // 0*10^256
+
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL, // NAN
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling NAN
+
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL, // +inf
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // -inf
+ 0xf900000000000000ULL, 0x0000000000000000ULL // -inf
+#else
+ 0x2208000000000000ULL, 0x0000000000000001ULL, // 1 *10^0
+ 0x77ffffffffffffffULL, 0xffffffffffffffffULL, // max possible value *10^6111 (largest exp)
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // -0*10^0
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL, // NAN
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling NAN
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // -inf
+#endif
+};
+
+#define NUM_DFP128_VALS (sizeof(dfp128_vals) / 8)
+unsigned long nb_dfp128_vals = NUM_DFP128_VALS;
+
+/* Todo: update dfp64_vals to match dfp128_vals content. */
+
+static unsigned long dfp64_vals[] = {
+#ifdef EXHAUSTIVE_TESTS
+ 0x77fcffffffffffffULL, // max possible value 9..9 *10^369 (largest exp)
+ 0x0000000000000001ULL, // min possible nonzero value 1 *10^-398. (smallest exp)
+ 0x4248000000000001ULL, // 1*10^260
+ 0x2234000000000e50ULL, // foo*10^-1
+ 0x223400000014c000ULL, //
+ 0xa2340000000000e0ULL, //
+ 0x22240000000000cfULL, // foo*10^-5
+ 0xa21400010a395bcfULL, // negative -foo*10^-9
+ 0x6e4d3f1f534acdd4ULL, // huge number foo*10^5
+ 0x000400000089b000ULL, // very small number foo*10^-397
+
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL, // 0 * 10 ^0
+ 0x4248000000000000ULL, // 0 * 10 ^260
+
+ // flavors of NAN
+ 0x7e34000000000111ULL, //signaling NaN
+ 0xfe000000d0e0a0d0ULL, //signaling NaN
+ 0xfc00000000000000ULL, //quiet NaN
+
+ // flavors of Infinity
+ 0x7800000000000000ULL, //+Inf
+ 0xf800000000000000ULL, //-Inf
+ 0x7a34000000000000ULL, //+Inf
+#else
+ 0x77fcffffffffffffULL, // max possible value 9..9 *10^369 (largest exp)
+ 0x4248000000000000ULL, // 0 * 10 ^260
+ 0xfe000000d0e0a0d0ULL, //signaling NaN
+ 0xf800000000000000ULL, //-Inf
+#endif
+};
+
+#define NUM_DFP64_VALS (sizeof(dfp64_vals) / 8)
+unsigned long nb_dfp64_vals = NUM_DFP64_VALS;
+
+/* shift helpers */
+#define SH_0 0
+#define SH_1 1
+#define SH_2 15
+#define SH_3 63
+
+static uint64_t shift_amounts[] = {
+ SH_0,
+ SH_1,
+ SH_2,
+ SH_3,
+#define SHIFT_ARRAY_SIZE 4
+};
+
+/* vector splat helpers */
+#define SPLAT0 0
+#define SPLAT1 1
+#define SPLAT2 0xaa
+#define SPLAT3 0x55
+#define SPLAT4 0xff
+
+static uint64_t splat_values[] = {
+ SPLAT0,
+ SPLAT1,
+ SPLAT2,
+ SPLAT3,
+ SPLAT4,
+#define SPLAT_ARRAY_SIZE 5
+};
+
+/* a small memory range used to test load-from and store-to vsx */
+#define BUFFER_SIZE 4
+#define MAX_BUFFER_PATTERNS 6
+unsigned long buffer[BUFFER_SIZE];
+
+static void initialize_buffer(int t)
+{
+ int x;
+
+ for (x = 0; x < BUFFER_SIZE; x++)
+ /* Don't want each of the 32-bit chunks to be identical. Loads of a
+ * byte from the wrong 32-bit chuck are not detectable if the chunks
+ * are identical.
+ */
+ switch((t+x)%BUFFER_SIZE) {
+ case 0:
+ buffer[x] = 0xffffffffffffffff;
+ break;
+ case 1:
+ buffer[x] = 0x0001020304050607;
+ break;
+ case 2:
+ buffer[x] = 0x5555555555555555;
+ break;
+ case 3:
+ buffer[x] = 0x0000000000000000;
+ break;
+ case 4:
+ buffer[x] = 0x5a05a05a05a05a05;
+ break;
+ case 5:
+ buffer[x] = 0x0102030405060708;
+ break;
+ default:
+ buffer[x] = 0x1010101010101010;
+ break;
+ }
+}
+
+#define PATTERN_SIZE 5
+unsigned long pattern[PATTERN_SIZE] = {
+ 0xffffffffffffffff,
+ 0xaaaaaaaaaaaaaaaa,
+ 0x5152535455565758,
+ 0x0000000000000000,
+ 0xffaa5599113377cc,
+};
+
+
+static void dump_small_buffer(void) {
+ int x;
+
+ printf("[ ");
+
+ for (x = 0; x < BUFFER_SIZE; x++)
+ printf("%016lx ", buffer[x] );
+
+ printf("]");
+}
+
+/* value to be shifted */
+static uint64_t values_to_shift[] = {
+ 0x0,
+ 0x1,
+ 0x10,
+ 0x100,
+ 0x1000,
+ 0x10000,
+ 0x100000,
+ 0x1000000,
+ 0x10000000,
+ 0x100000000,
+ 0x1000000000,
+ 0x10000000000,
+ 0x100000000000,
+ 0x1000000000000,
+ 0x10000000000000,
+ 0x100000000000000,
+ 0x1000000000000000,
+ 0xf,
+ 0x1f,
+ 0x10f,
+ 0x100f,
+ 0x1000f,
+ 0x10000f,
+ 0x100000f,
+ 0x1000000f,
+ 0x10000000f,
+ 0x100000000f,
+ 0x1000000000f,
+ 0x10000000000f,
+ 0x100000000000f,
+ 0x1000000000000f,
+ 0x10000000000000f,
+ 0x100000000000000f,
+ 0x7,
+ 0x70,
+ 0x700,
+ 0x7000,
+ 0x70000,
+ 0x700000,
+ 0x7000000,
+ 0x70000000,
+ 0x700000000,
+ 0x7000000000,
+ 0x70000000000,
+ 0x700000000000,
+ 0x7000000000000,
+ 0x70000000000000,
+ 0x700000000000000,
+ 0x7000000000000000,
+ 0x8,
+ 0x80,
+ 0x800,
+ 0x8000,
+ 0x80000,
+ 0x800000,
+ 0x8000000,
+ 0x80000000,
+ 0x800000000,
+ 0x8000000000,
+ 0x80000000000,
+ 0x800000000000,
+ 0x8000000000000,
+ 0x80000000000000,
+ 0x800000000000000,
+ 0x8000000000000000,
+ 0xffffffffffffffff,
+ 0
+#define SHIFT_VALUES_SIZE 66
+};
+
+/* DFP related helper functions: */
+
+/* For DFP finite numbers, the combination field (G field) is a
+ * combination of the exponent and the LMD (Left Most Digit) of the
+ * significand. The fields are encoded/decoded as described in the
+ * table here.
+ * 00 01 10 -< Exponent bits.
+ * 0: 00000 01000 10000
+ * ...
+ * 7: 00111 01111 10111
+ * 8: 11000 11010 11100
+ * 9: 11001 11011 11101 (encoded special field).
+ * |
+ * ^ LMD value.
+*/
+#define DFP_GFIELD_MASK 0x7c00000000000000UL
+#define DFP_GFIELD_SHIFT 58
+
+static unsigned int special_field_LMD(uint64_t dword1) {
+ unsigned long g_field_specials;
+ int left_two_bits;
+ int right_three_bits;
+
+ g_field_specials = (dword1 & DFP_GFIELD_MASK) >> DFP_GFIELD_SHIFT;
+ left_two_bits = (g_field_specials & 0x18) >> 3;
+ right_three_bits = g_field_specials & 0x07;
+
+ /* The LMD result maps directly to the right_three_bits value as
+ * long as the left two bits are 0b00,0b01,0b10. So a compare
+ * against 3 is sufficient to determine if we can return the right
+ * three bits directly. (LMD values 0..7).
+ */
+ if (left_two_bits < 3) {
+ return (right_three_bits);
+ }
+
+ /* LMD values of 8 or 9 require a bit of swizzle, but a check of
+ * the right-most bit is sufficient to determine whether LMD value
+ * is 8 or 9.
+ */
+ if (right_three_bits & 0x1)
+ return 9;
+ else
+ return 8;
+}
+
+/* Returns the exponent bits, as decoded from the G field. */
+static inline int special_field_exponent_bits(unsigned long dword1) {
+ unsigned long g_field_specials;
+ int left_two_bits;
+ int right_three_bits;
+
+ g_field_specials = (dword1 & DFP_GFIELD_MASK) >> DFP_GFIELD_SHIFT;
+ left_two_bits = (g_field_specials & 0x18) >> 3;
+ right_three_bits = g_field_specials & 0x07;
+
+ /* The special field exponent bits maps directly to the left_two_bits
+ * value as long as the left two bits are 0b00,0b01,0b10. So a compare
+ * against 3 is sufficient for those values.
+ */
+ if (left_two_bits < 3) {
+ return (left_two_bits);
+ }
+
+ switch(right_three_bits) {
+ case 0:
+ case 1: return 0x0;
+ case 2:
+ case 3: return 0x1;
+ case 4:
+ case 5: return 0x2;
+ case 6: /* Infinity */ return 0x0;
+ case 7: /* NaN */ return 0x0;
+ }
+ return -1; /* should never hit this */
+}
+
+/* get_declet(). Return a 10-bit declet, beginning at the 'start'
+ * offset.
+ *
+ * | dword1 | dword0 |
+ * | 0 63|64 127|
+ */
+#define TEN_BITS 0x03ffULL
+
+static inline int get_declet(int start, uint64_t dword1, uint64_t dword0) {
+ unsigned long local_declet;
+ unsigned int dword0_shift;
+ unsigned int dword1_shift;
+
+ dword1_shift = 63 - (start + 9);
+ dword0_shift = 127 - (start + 9);
+
+ if (verbose>5) printf("\n%s (%d) %016lx %016lx",
+ __FUNCTION__, start, dword1, dword0);
+
+ if ((start + 9) < 63) { /* fully within dword1 */
+ local_declet = (dword1 >> dword1_shift) & TEN_BITS;
+
+ } else if (start >= 65) {/* fully within dword0 */
+ local_declet = (dword0 >> dword0_shift) & TEN_BITS;
+
+ } else { /* straddling the two dwords*/
+ unsigned long mask_dword0;
+ unsigned long mask_dword1;
+
+ mask_dword1 = TEN_BITS >> (64 - dword0_shift);
+ mask_dword0 = TEN_BITS << (dword0_shift);
+ local_declet =
+ ((dword1 & mask_dword1) << (64-dword0_shift)) +
+ ((dword0 & mask_dword0) >> dword0_shift);
+ }
+ return local_declet;
+}
+
+static int get_bcd_digit_from_dpd(int start, uint64_t dword1,
+ uint64_t dword0) {
+ long bcd_digit;
+ long declet;
+
+ declet = get_declet(start, dword1, dword0);
+ bcd_digit = dpb_to_bcd(declet);
+ return bcd_digit;
+}
+
+
+/* The 'exponent left' shift is for moving the leftmost two bits
+ * of the exponent down to where they can be easily merged with the
+ * rest of the exponent.
+ */
+#define DFP128_EXPONENT_RIGHT_MASK 0x03ffc00000000000
+#define DFP64_EXPONENT_RIGHT_MASK 0x03fc000000000000
+#define DFP128_EXPONENT_RIGHT_MASK_SHIFT 46
+#define DFP64_EXPONENT_RIGHT_MASK_SHIFT 50
+#define DFP128_EXPONENT_LEFT_SHIFT 12
+#define DFP64_EXPONENT_LEFT_SHIFT 8
+
+#define DFP_NAN 0x1f
+#define DFP_INF 0x1e
+#define DFP_SIGNALING_NAN_BIT 0x0200000000000000
+
+/* Start of the Trailing Significand field is at bit # .. */
+#define DFP128_T_START 18
+#define DFP64_T_START 14
+
+//The exponent bias value is 101 for DFP Short, 398
+//for DFP Long, and 6176 for DFP Extended.
+#define DFP128_EXPONENT_BIAS 6176
+#define DFP64_EXPONENT_BIAS 398
+
+/* return the dfp exponent from the leading dword. */
+static inline signed long dfp128_exponent(unsigned long dword1) {
+ unsigned long exponent_left;
+ unsigned long exponent_right;
+ unsigned long biased_exponent;
+ signed long exponent;
+
+ exponent_left = special_field_exponent_bits(dword1);
+ exponent_right = (dword1 & DFP128_EXPONENT_RIGHT_MASK);
+ biased_exponent = (exponent_left << DFP128_EXPONENT_LEFT_SHIFT) +
+ (exponent_right >> DFP128_EXPONENT_RIGHT_MASK_SHIFT);
+
+ /* Unbias the exponent. */
+ exponent = biased_exponent - DFP128_EXPONENT_BIAS;
+
+ return exponent;
+}
+
+/* Interpret the paired 64-bit values as a extended (quad) 128 bit DFP.
+ *
+ * | Significand | Combination Field/ | |
+ * | sign bit | Encoded Exponent | remainder of significand |
+ * |0 |1 17|18 127|
+ * ^ (bit0) Significand sign bit.
+ * ^ (bit 1:17) Combination field. Contains high bits of
+ * exponent (encoded), LMD of significand (encoded),
+ * and the remainder of the exponent. First five bits
+ * will indicate special cases NAN or INF.
+ * ^ (bit 18:127) Remainder of the
+ * significand.
+ */
+
+#define DFP128_COMBINATION_MASK 0x7fffc
+#define DFP64_COMBINATION_MASK 0x7ffc
+#define DFP128_COMBINATION_SHIFT 46
+#define DFP64_COMBINATION_SHIFT 50
+#define DFP_SPECIAL_SYMBOLS_MASK 0x1f
+#define DFP_SPECIAL_SYMBOLS_SHIFT 58
+
+static inline void dissect_dfp128_float(uint64_t dword1, uint64_t dword0) {
+ long signbit;
+ signed long exponent;
+ unsigned long gfield_special_symbols;
+ unsigned long lmd_digit;
+ unsigned long bcd_digits[13];
+ int i;
+ int silent=0; // suppress leading zeros from the output.
+
+ if (verbose > 5) printf("RAW128: %016lx %016lx ", dword1, dword0);
+
+ signbit = (dword1 >> 63);
+
+ if (signbit) printf("-");
+ else printf("+");
+
+ gfield_special_symbols =
+ ((dword1 >> DFP_SPECIAL_SYMBOLS_SHIFT) & DFP_SPECIAL_SYMBOLS_MASK);
+
+ switch (gfield_special_symbols) {
+ case DFP_INF:
+ printf( "inf ");
+ break;
+
+ case DFP_NAN:
+ if (dword1 & DFP_SIGNALING_NAN_BIT)
+ printf("SNaN ");
+ else
+ printf("QNaN ");
+ break;
+
+ default:
+ printf( "Finite ");
+ exponent = dfp128_exponent(dword1);
+ lmd_digit = special_field_LMD(dword1);
+
+ for (i = 0; i < 11; i++) {
+ bcd_digits[i] = get_bcd_digit_from_dpd((DFP128_T_START
+ + 10 * i), dword1, dword0);
+ }
+
+ if (lmd_digit) {
+ silent++;
+ printf("%01lx", lmd_digit);
+
+ } else {
+ printf(" ");
+ }
+
+ for (i = 0; i < 11; i++) {
+ if (bcd_digits[i] || silent ) {
+ silent++;
+ printf("%03lx", bcd_digits[i]);
+
+ } else {
+ /* always print at least the last zero */
+ if (i == 10)
+ printf(" 0");
+
+ else
+ printf(" ");
+ }
+ }
+ printf(" * 10 ^ ");
+ printf("%ld ", exponent);
+ }
+}
+
+/* Interpret the 64-bit values as a 64 bit DFP.
+*
+* | Significand | Combination Field/ | |
+* | sign bit | Encoded Exponent | remainder of significand |
+* |0 |1 13|14 63|
+* ^ (bit0) Significand sign bit.
+* ^ (bit 1:13) Combination field. Contains high bits of
+* exponent (encoded), LMD of significand (encoded),
+* and the remainder of the exponent. First five bits
+* will indicate special cases NAN or INF.
+* ^ (bit 14:63) Remainder of the
+* significand.
+*/
+
+/* return the dfp exponent from the leading dword. */
+static inline signed long dfp64_exponent(unsigned long dword1) {
+ unsigned long exponent_left;
+ unsigned long exponent_right;
+ unsigned long biased_exponent;
+ signed long exponent;
+
+ exponent_left = special_field_exponent_bits(dword1);
+ exponent_right = (dword1 & DFP64_EXPONENT_RIGHT_MASK);
+ biased_exponent = (exponent_left << DFP64_EXPONENT_LEFT_SHIFT) +
+ (exponent_right >> DFP64_EXPONENT_RIGHT_MASK_SHIFT);
+
+ /* Unbias the exponent. */
+ exponent = biased_exponent - DFP64_EXPONENT_BIAS;
+ return exponent;
+}
+
+static inline void dissect_dfp64_float(uint64_t dword1) {
+ long signbit;
+ signed long exponent;
+ unsigned long gfield_special_symbols;
+ unsigned long lmd_digit;
+ unsigned long bcd_digits[13];
+ int i;
+ int silent=0; // suppress leading zeros from the output.
+
+ if (verbose > 5) printf("RAW64: %016lx ", dword1);
+
+ signbit = (dword1 >> 63);
+
+ if (signbit) printf("-");
+ else printf("+");
+
+ gfield_special_symbols =
+ ((dword1 >> DFP_SPECIAL_SYMBOLS_SHIFT) & DFP_SPECIAL_SYMBOLS_MASK);
+
+ switch (gfield_special_symbols) {
+ case DFP_INF:
+ printf( "inf ");
+ break;
+
+ case DFP_NAN:
+ if (dword1 & DFP_SIGNALING_NAN_BIT)
+ printf("SNaN ");
+ else
+ printf("QNaN ");
+ break;
+
+ default:
+ printf( "Finite ");
+ exponent = dfp64_exponent(dword1);
+ lmd_digit = special_field_LMD(dword1);
+
+ for (i = 0; i < 5; i++)
+ bcd_digits[i] = get_bcd_digit_from_dpd((DFP64_T_START + 10 * i),
+ dword1, 0);
+
+ if (lmd_digit) {
+ silent++;
+ printf("%01lx", lmd_digit);
+
+ } else {
+ printf(" ");
+ }
+
+ for (i = 0; i < 5; i++) {
+ if (bcd_digits[i] || silent) {
+ silent++;
+ printf("%03lx", bcd_digits[i]);
+
+ } else { // suppress leading zeros.
+ /* always print at least the last zero */
+ if (i == 4)
+ printf(" 0");
+
+ else
+ printf(" ");
+ }
+ }
+ printf(" * 10 ^ ");
+ printf("%ld ", exponent);
+ }
+}
+
+static void dump_dfp128_table(void) {
+ int i;
+
+ printf("DFP 128 table:\n");
+
+ for (i = 0; i < nb_dfp128_vals; i += 2) {
+ printf("i=:%2d ", i);
+ dissect_dfp128_float(dfp128_vals[i], dfp128_vals[i+1]);
+ printf("\n");
+ }
+}
+
+static void dump_dfp64_table(void) {
+ int i;
+
+ printf("DFP 64 table:\n");
+
+ for (i = 0; i<nb_dfp64_vals; i++) {
+ printf("i=:%2d ", i);
+ dissect_dfp64_float(dfp64_vals[i]);
+ printf("\n");
+ }
+}
+
+
+/* Data Formats for floating point.
+ * Floating point values include the following:
+ * -INF -NOR -DEN -0 +0 +DEN +NOR +INF
+ * INFinite: When the biased exponent is the MAX possible value, and
+ * the fraction field is 0.
+ * ZERo. biased exponent is zero, fraction is 0.
+ * DENormalized. biased exponent is 0, and fraction is non-zero.
+ * NORmalized. All other values that are neither Zero, Denormalized,
+ * or Infinite. Biased exponent=1..MAX-1.
+ */
+
+/* Quad (128bit):
+ * | Sign | EXPonent+Bias | FRACTION/Mantissa |
+ * 0 1 15 16 127
+ * exponent is 15 bits. ranging from: 0x0000 .. 0x7fff
+ * 0 = (zero if fraction==0, DeNormal if fraction !=0 )
+ * 1...0x7ffe = normalized
+ * 7fff = (infinite if fraction==0, NaN if fraction !=0)
+ */
+#define QUAD_EXP_MASK 0x7fff
+
+/* This assumes we are working on the top half of a quad stored in a 64-bit
+ * register.
+ */
+#define QUAD_EXP_SHIFT 48
+#define QUAD_MANTISSA_MASK 0x0000ffffffffffff
+static inline unsigned long build_binary128_float(unsigned long signbit,
+ unsigned long exponent,
+ unsigned long mantissa) {
+ unsigned long thevalue;
+
+ thevalue = (unsigned long) (signbit << 63) |
+ ((exponent & QUAD_EXP_MASK) << QUAD_EXP_SHIFT) |
+ (mantissa & QUAD_MANTISSA_MASK);
+
+ if (verbose > 3)
+ printf("%s %lx \n", __FUNCTION__, (unsigned long)thevalue);
+
+ return thevalue;
+}
+
+ /* double (64bit):
+ * | Sign | EXPonent+Bias | FRACTION/Mantissa |
+ * 0 1 11 12 63
+ * exponent is 11 bits. ranging from: 0x000 .. 0x7ff
+ * 0 = (zero if fraction==0, DeNormal if fraction !=0 )
+ * 1...0x7fe = normalized
+ * 7ff = (infinite if fraction==0, NaN if fraction !=0)
+*/
+#define DOUBLE_EXP_MASK 0x7ff
+#define DOUBLE_EXP_SHIFT 52
+#define DOUBLE_MANTISSA_MASK 0x000fffffffffffff
+
+static inline unsigned long build_binary64_float(unsigned long signbit,
+ unsigned long exponent,
+ unsigned long mantissa) {
+ unsigned long thevalue;
+
+ thevalue = (unsigned long ) (signbit << 63) |
+ ((exponent & DOUBLE_EXP_MASK) << DOUBLE_EXP_SHIFT) |
+ (mantissa & DOUBLE_MANTISSA_MASK );
+
+ if (verbose > 3)
+ printf("%s %lx \n", __FUNCTION__, (unsigned long)thevalue);
+
+ return thevalue;
+}
+
+ /* floating point single (32bit):
+ * | Sign | EXPonent+Bias | FRACTION/Mantissa |
+ * 0 1 8 9 31
+ * exponent is 8 bits. ranging from: 0x00 .. 0xff
+ * 0 = (zero if fraction==0, DeNormal if fraction !=0 )
+ * 1...0x7e = normalized
+ * 7f = (infinite if fraction==0, NaN if fraction !=0) */
+#define SINGLE_EXP_MASK 0xff
+#define SINGLE_EXP_SHIFT 23
+#define SINGLE_MANTISSA_MASK 0x007fffff
+
+/* This is building the 32-bit float. */
+static inline unsigned long build_binary32_float(unsigned long signbit,
+ unsigned long exponent,
+ unsigned long mantissa) {
+ unsigned long thevalue;
+ unsigned long local_signbit;
+ unsigned long local_exponent;
+ unsigned long local_mantissa;
+
+ local_signbit = (signbit != 0) << 31;
+ local_exponent = ((exponent & SINGLE_EXP_MASK) << SINGLE_EXP_SHIFT);
+ local_mantissa = (mantissa & SINGLE_MANTISSA_MASK);
+
+ thevalue = (unsigned long) (local_signbit) |
+ (local_exponent) |
+ (local_mantissa);
+
+ if (verbose > 3)
+ printf("%s %lx \n", __FUNCTION__, (unsigned long)thevalue);
+
+ return thevalue;
+}
+
+/* floating point half (16bit):
+ * | Sign | EXPonent+Bias | FRACTION/Mantissa |
+ * 0 1 6 7 15
+ * exponent is 6 bits. 0x00 .. 0x7e masked with EXP_MASK
+ * 0 = (zero if fraction==0, DeNormal if fraction !=0 )
+ * 1...0x7d = normalized
+ * 7e = (infinite if fraction==0, NaN if fraction !=0) */
+/* when extracting the exponent from the 16-bit half-word, use this mask. */
+#define HALF_EXP_MASK 0x7e00
+
+/* when building the 16-bit half-word, mask against this,
+ * then shift into place
+ */
+#define HALF_EXP_MASK_NORMALIZED 0x3f
+#define HALF_EXP_SHIFT 9
+#define HALF_MANTISSA_MASK 0x01ff
+
+/* This is building the 16-bit float. */
+static inline unsigned long build_binary16_float(unsigned long in_signbit,
+ unsigned long exponent,
+ unsigned mantissa) {
+ unsigned long thevalue;
+ unsigned long local_signbit;
+ unsigned long local_exponent;
+ unsigned long local_mantissa;
+
+ local_signbit = (in_signbit != 0) << 15;
+
+ local_exponent= ((exponent & HALF_EXP_MASK_NORMALIZED) << HALF_EXP_SHIFT);
+ local_mantissa = (mantissa & HALF_MANTISSA_MASK);
+
+ thevalue = (unsigned long) (local_signbit) | (local_exponent)
+ | (local_mantissa);
+
+ if (verbose > 3)
+ printf("%s %lx \n", __FUNCTION__, (unsigned long)thevalue);
+
+ return thevalue;
+}
+
+/* dissect_binary128_float:
+ * Interpret the (high half) 64-bit value as normal/denormal/inf/NaN.
+ * This is as it would be interpreted as the MSB portion of
+ * a 128-bit wide QUAD.
+ */
+static inline void dissect_binary128_float(uint64_t value) {
+ unsigned long signbit;
+ unsigned long exponent;
+ unsigned long mantissa;
+
+ signbit = (value >> 63);
+ exponent = ( QUAD_EXP_MASK & (value >> QUAD_EXP_SHIFT));
+ mantissa = ( QUAD_MANTISSA_MASK & value);
+
+ if (verbose > 4) printf("128 bit:");
+
+ if (signbit) printf("-");
+ else printf("+");
+
+ switch (exponent) {
+ case 0x0:
+ if (mantissa == 0) printf("zero ");
+ else printf("denormal ");
+ break;
+
+ case QUAD_EXP_MASK:
+ if (mantissa == 0) printf("inf ");
+ else printf("NaN ");
+ break;
+
+ default: printf("Normal ");
+ }
+
+ if (verbose > 4)
+ printf("%lx %4lx %16lx %16lx \n", signbit, exponent, mantissa, value);
+}
+
+/* Interpret the 64-bit value as normal/denormal/inf/NaN
+ * this is as interpreted as the 64-bit float
+ */
+static inline void dissect_binary64_float(uint64_t value) {
+ unsigned long signbit;
+ unsigned long exponent;
+ unsigned long mantissa;
+
+ signbit = (value >> 63); // bit0
+ exponent = ( DOUBLE_EXP_MASK & (value >> DOUBLE_EXP_SHIFT));
+ mantissa = ( DOUBLE_MANTISSA_MASK & value);
+
+ if (verbose > 4) printf(" 64 bit:");
+
+ if (signbit) printf("-");
+ else printf("+");
+
+ switch (exponent) {
+ case 0x0:
+ if (mantissa == 0) printf("zero ");
+ else printf("denormal ");
+ break;
+
+ case DOUBLE_EXP_MASK:
+ if (mantissa == 0) printf("inf ");
+ else printf("NaN ");
+ break;
+
+ default: printf("Normal ");
+ }
+
+ if (verbose>4)
+ printf("%lx %4lx %16lx %16lx\n", signbit, exponent, mantissa, value);
+}
+
+/* interpret the 32-bit value as normal/denormal/inf/NaN.
+ * Note that the value is stored in the upper half of a
+ * 64-bit, which is itself in the upper half of a quad.
+ */
+static inline void dissect_binary32_float(uint64_t value) {
+ unsigned long signbit;
+ unsigned long exponent;
+ unsigned long mantissa;
+ unsigned long adj_value;
+
+ /* shift down to where the offsets make more sense.*/
+ adj_value = value; //>>32;
+ signbit = (adj_value >> 31);
+ exponent = ( SINGLE_EXP_MASK & (adj_value >> SINGLE_EXP_SHIFT));
+ mantissa = ( SINGLE_MANTISSA_MASK & adj_value);
+
+ if (verbose > 4) printf(" 32 bit:");
+
+ if (signbit) printf("-");
+ else printf("+");
+
+ switch (exponent) {
+ case 0x0:
+ if (mantissa == 0) printf("zero ");
+ else printf("denormal ");
+ break;
+
+ case SINGLE_EXP_MASK:
+ if (mantissa == 0) printf("inf ");
+ else printf("NaN ");
+ break;
+
+ default: printf("Normal ");
+ }
+
+ if (verbose>4)
+ printf("%lx %4lx %16lx %16lx \n", signbit, exponent, mantissa, adj_value);
+}
+
+/* Interpret the 16-bit value as normal/denormal/inf/NaN. */
+static inline void dissect_binary16_float(uint64_t value) {
+ unsigned long signbit;
+ unsigned long exponent;
+ unsigned long mantissa;
+ unsigned long adj_value;
+
+ adj_value = (value & 0xffff);
+ signbit = ((adj_value & 0x8000) > 1);
+ exponent = ((adj_value & HALF_EXP_MASK ) >> HALF_EXP_SHIFT) ;
+ mantissa = (adj_value & HALF_MANTISSA_MASK);
+
+ if (verbose > 4) printf(" 16 bit:");
+
+ if (signbit) printf("-");
+ else printf("+");
+
+ switch (exponent) {
+ case 0x0:
+ if (mantissa == 0) printf("zero ");
+ else printf("denormal ");
+ break;
+
+ case HALF_EXP_MASK:
+ if (mantissa == 0) printf("inf ");
+ else printf("NaN ");
+ break;
+
+ default: printf("Normal ");
+ }
+
+ if (verbose > 4)
+ printf("%lx %4lx %16lx %16lx \n",
+ signbit, exponent>>HALF_EXP_SHIFT, mantissa, adj_value);
+}
+
+#define dissect_double_as_32s(vec_foo) \
+ printf(" "); \
+ dissect_binary16_float((vec_foo & 0xffffffff)); \
+ printf(" "); \
+ dissect_binary16_float((vec_foo >> 32) & 0xffffffff);
+
+#define dissect_double_as_16s(vec_foo) \
+ printf(" "); \
+ dissect_binary16_float((vec_foo&0xffff)); \
+ printf(" "); \
+ dissect_binary16_float((vec_foo>>16)&0xffff); \
+ printf(" "); \
+ dissect_binary16_float((vec_foo>>32)&0xffff); \
+ printf(" "); \
+ dissect_binary16_float((vec_foo>>48)&0xffff);
+
+/* a table of exponent values for use in the float precision tests. */
+unsigned long exponent_table[] = {
+#ifdef EXHAUSTIVE_TESTS
+ 0x0000, /* +/-0 or +/-DENormalized, depending on associated mantissa. */
+ 0x1a, /* within NORmalized for 16,32,64,128-bit. */
+ 0x1f, /* +/-INF or +/-NaN for 16bit, NORmalized for 32,64,128 */
+ 0xff, /* +/-INF or +/-NaN for 32bit, NORmalized for 64,128 */
+ 0x7ff, /* +/-INF or +/-NaN for 32 and 64bit, NORmalized for 128 */
+ 0x7fff, /* +/-INF or +/-NaN for 128bit. */
+#else
+ 0x0000, /* +/-0 or +/-DENormalized, depending on associated mantissa. */
+ 0xff, /* +/-INF or +/-NaN for 32bit, NORmalized for 64,128 */
+ 0x7ff, /* +/-INF or +/-NaN for 32 and 64bit, NORmalized for 128 */
+ 0x7fff, /* +/-INF or +/-NaN for 128bit. */
+#endif
+};
+#define MAX_EXPONENTS (sizeof(exponent_table) / sizeof(unsigned long))
+
+unsigned long mantissa_table[] = {
+#ifdef EXHAUSTIVE_TESTS
+ 0xbeefbeefbeef, /* NOR or DEN or NaN */
+ 0x000000000000, /* ZERO or INF */
+ 0x7fffffffffff, /* NOR or DEN or NaN */
+#else
+ 0x000000000000, /* ZERO or INF */
+ 0x7fffffffffff, /* NOR or DEN or NaN */
+#endif
+};
+#define MAX_MANTISSAS (sizeof(mantissa_table) / sizeof(unsigned long))
+
+/* build in 64-bit chunks, low doubleword is zero. */
+static unsigned long * float_vsxargs;
+static unsigned long * binary128_float_vsxargs = NULL;
+static unsigned long * binary64_float_vsxargs = NULL;
+static unsigned long * binary32_float_vsxargs = NULL;
+static unsigned long * binary16_float_vsxargs = NULL;
+
+unsigned long nb_float_vsxargs;
+
+#define MAX_FLOAT_VSX_ARRAY_SIZE (((MAX_EXPONENTS * MAX_MANTISSAS) * 2 + 1) * 2)
+
+void build_float_vsx_tables (void)
+{
+ long i = 0;
+ unsigned long signbit;
+ unsigned long exponent;
+ unsigned long mantissa;/* also referred to as FRACTION in the ISA.*/
+ unsigned long exponent_index;
+ unsigned long mantissa_index;
+
+ if (verbose > 2) printf("%s\n", __FUNCTION__);
+
+ binary128_float_vsxargs = malloc(MAX_FLOAT_VSX_ARRAY_SIZE
+ * sizeof(unsigned long));
+
+ float_vsxargs = binary128_float_vsxargs;
+
+ binary64_float_vsxargs = malloc(MAX_FLOAT_VSX_ARRAY_SIZE
+ * sizeof(unsigned long));
+
+ binary32_float_vsxargs = malloc(MAX_FLOAT_VSX_ARRAY_SIZE
+ * sizeof(unsigned long));
+ binary16_float_vsxargs = malloc(MAX_FLOAT_VSX_ARRAY_SIZE
+ * sizeof(unsigned long));
+
+ for (signbit = 0; signbit < 2; signbit++) {
+ for (exponent_index = 0; exponent_index < MAX_EXPONENTS;
+ exponent_index++) {
+
+ for (mantissa_index = 0; mantissa_index < MAX_MANTISSAS;
+ mantissa_index++) {
+
+ exponent = exponent_table[exponent_index];
+ mantissa = mantissa_table[mantissa_index];
+
+ if (verbose > 2) {
+ printf("signbit:%lx ", signbit);
+ printf("exponent:%4lx ", exponent);
+ printf("mantissa:%lx ", mantissa);
+ printf("\n");
+ }
+
+ binary128_float_vsxargs[i] = build_binary128_float(signbit, exponent,
+ mantissa);
+
+ binary128_float_vsxargs[i+1] = 0;
+
+ binary64_float_vsxargs[i] = build_binary64_float(signbit, exponent,
+ mantissa);
+
+ binary64_float_vsxargs[i+1] = build_binary64_float(signbit, exponent,
+ mantissa);
+
+ binary32_float_vsxargs[i] = build_binary32_float(signbit, exponent,
+ mantissa);
+
+ binary32_float_vsxargs[i+1] = build_binary32_float(signbit, exponent,
+ mantissa);
+
+ binary16_float_vsxargs[i] = build_binary16_float(signbit, exponent,
+ mantissa);
+
+ binary16_float_vsxargs[i+1] = build_binary16_float(signbit, exponent,
+ mantissa);
+ i += 2;
+ }
+ }
+ }
+ nb_float_vsxargs = i;
+}
+
+/* Display entries stored in the float_vsx table. These are used as
+ * quad/double/singles, stored as quads. */
+void dump_float_vsx_table (void) {
+ int i;
+
+ printf("Float VSX Table:");
+ printf("128-bit (quad):\n");
+
+ for (i = 0; i < nb_float_vsxargs; i += 2) {
+ printf("i =: %2d ", i);
+ dissect_binary128_float(binary128_float_vsxargs[i]);
+ }
+
+ printf("64-bit (double):\n");
+
+ for (i = 0; i< nb_float_vsxargs; i += 2) {
+ printf("i = %2d ", i);
+ dissect_binary64_float(binary64_float_vsxargs[i]);
+ }
+
+ printf("32-bit (single):\n");
+
+ for (i = 0; i < nb_float_vsxargs; i += 2) {
+ printf("i = %2d ", i);
+ dissect_binary32_float(binary32_float_vsxargs[i]);
+ }
+
+ printf("16-bit (half):\n");
+
+ for (i = 0; i < nb_float_vsxargs; i += 2) {
+ printf("i =% 2d ", i);
+ dissect_binary16_float(binary16_float_vsxargs[i]);
+ }
+
+ printf("\n");
+}
+
+static void print_dcmx_field(unsigned long local_dcmx) {
+ /* Note - this splats out the local_dxmc field from the form used to
+ * globally pass it, with a single set bit, into the functions that use
+ * it. The actual DCMX field is a bit-field from 0x00 to 0x3f. If
+ * multiple bits are ever set, this function and the way it is passed
+ * into the users will need to be updated. This does not handle
+ * multiple bits being set.
+ */
+
+ printf(" DCMX=[");
+
+ switch(local_dcmx) {
+ case 0: printf("ALL"); break;
+ case 1: printf("NaN"); break;
+ case 2: printf("+inf"); break;
+ case 3: printf("-inf"); break;
+ case 4: printf("+zero"); break;
+ case 5: printf("-zero"); break;
+ case 6: printf("+denormal"); break;
+ case 7: printf("-denormal"); break;
+ default: printf("other"); break;
+ }
+
+ if (verbose > 3)
+ printf(" %lx", local_dcmx);
+
+ printf("] ");
+}
+
+#define MAX_CHAR_ARGS_ARRAY_SIZE 128
+
+static unsigned char * char_args;
+unsigned long nb_char_args;
+
+static void build_char_table(void) {
+ long i = 0;
+ char ichar;
+
+ char_args = memalign(32, MAX_CHAR_ARGS_ARRAY_SIZE * sizeof(char));
+
+#ifdef EXHAUSTIVE_TESTS
+ for (ichar = 'a'; ichar <= 'z'; ichar++) { char_args[i++] = ichar; }
+ for (ichar = '0'; ichar <= '9'; ichar++) { char_args[i++] = ichar; }
+ for (ichar = 'A'; ichar <= 'Z'; ichar++) { char_args[i++] = ichar; }
+#else
+ for (ichar = 'a'; ichar <= 'z'; ichar+=6) { char_args[i++] = ichar; }
+ for (ichar = '0'; ichar <= '9'; ichar+=6) { char_args[i++] = ichar; }
+ for (ichar = 'A'; ichar <= 'Z'; ichar+=6) { char_args[i++] = ichar; }
+#endif
+
+ char_args[i++] = ' ';
+ char_args[i++] = '+';
+ char_args[i++] = '-';
+ char_args[i++] = '/';
+ char_args[i++] = '[';
+ char_args[i++] = ']';
+ char_args[i++] = '`';
+ char_args[i++] = '_';
+ nb_char_args = i;
+}
+
+static void dump_char_table() {
+ int i;
+
+ printf("Char Table:");
+
+ for (i = 0; i<nb_char_args; i++)
+ printf("%c ", char_args[i]);
+
+ printf("\n");
+}
+
+#define MAX_CHAR_RANGES_SIZE 128
+
+static unsigned char * char_ranges;
+unsigned long nb_char_ranges;
+
+static void build_char_range_table(void) {
+/* ... in groups of four. */
+
+ long i = 0;
+ char char_start, char_end;
+
+ char_ranges = memalign(32, MAX_CHAR_RANGES_SIZE * sizeof(char));
+ char_start = 'a';
+ char_end = 'z';
+ char_ranges[i++] = char_start;
+ char_ranges[i++] = char_end;
+
+ char_start = 'A';
+ char_end = 'Z';
+ char_ranges[i++] = char_start;
+ char_ranges[i++] = char_end;
+
+ char_start = '0';
+ char_end = '9';
+ char_ranges[i++] = char_start;
+ char_ranges[i++] = char_end;
+
+ char_start = 'f';
+ char_end = 'z';
+ char_ranges[i++] = char_start;
+ char_ranges[i++] = char_end;
+
+ char_start = 'a';
+ char_end = 'e';
+ char_ranges[i++] = char_start;
+ char_ranges[i++] = char_end;
+
+ char_start = 'A';
+ char_end = 'E';
+ char_ranges[i++] = char_start;
+ char_ranges[i++] = char_end;
+
+ nb_char_ranges = i;
+}
+
+static void dump_char_range_table()
+{
+ int i;
+
+ printf("Char Range Table:");
+
+ for (i = 0; i < nb_char_ranges; i += 4) {
+ printf(" [ %c-%c %c-%c ] ",
+ char_ranges[i], char_ranges[i+1],
+ char_ranges[i+2], char_ranges[i+3] );
+ }
+
+ printf("\n");
+}
+
+static HWord_t *iargs = NULL;
+static int nb_iargs = 0;
+
+static void build_iargs_table (void) {
+ uint64_t tmp;
+ int i = 0;
+
+ iargs = malloc(20 * sizeof(HWord_t));
+
+ for (tmp = 0; ; tmp = 123456789*tmp + 123456789999) {
+ if ((long)tmp < 0 )
+ tmp = 0xFFFFFFFFFFFFFFFFULL;
+
+ iargs[i++] = tmp;
+ AB_DPRINTF("val %016lx\n", tmp);
+
+ if (tmp == 0xFFFFFFFFFFFFFFFFULL)
+ break;
+ }
+
+ AB_DPRINTF("Registered %d iargs values\n", i);
+ nb_iargs = i;
+}
+
+static unsigned long * vsxargs = NULL;
+unsigned long nb_vargs;
+
+#define MAX_VSX_ARRAY_SIZE 42
+
+static void build_vsx_table (void)
+{
+ long i = 0;
+ // A VSX register is 128-bits wide.
+ // We build contents here using pairs of 64-bit longs.
+ // Permutes work against two (non-paired) VSX regs, so these are
+ // also grouped by twos.
+ vsxargs = memalign(16, MAX_VSX_ARRAY_SIZE * sizeof(unsigned long));
+#ifdef EXHAUSTIVE_TESTS
+ vsxargs[i++] = 0x0000000000000000UL; vsxargs[i++] = 0x0000000000000000UL;
+ vsxargs[i++] = 0x0102030405060708UL; vsxargs[i++] = 0x0102010201020102UL;
+
+ vsxargs[i++] = 0xaaaaaaaaaaaaaaaaUL; vsxargs[i++] = 0xaaaaaaaaaaaaaaaaUL;
+ vsxargs[i++] = 0x5555555555555555UL; vsxargs[i++] = 0x5555555555555555UL;
+
+ vsxargs[i++] = 0x08090a0b0c0d0e0fUL; vsxargs[i++] = 0x0102010201020102UL;
+ vsxargs[i++] = 0xf0f1f2f3f4f5f6f7UL; vsxargs[i++] = 0xf8f9fafbfcfdfeffUL;
+
+ vsxargs[i++] = 0x7ea1a5a7abadb0baUL; vsxargs[i++] = 0x070d111d1e555e70UL;
+ vsxargs[i++] = 0xe5e7ecedeff0f1faUL; vsxargs[i++] = 0xbeb1c0caced0dbdeUL;
+
+ vsxargs[i++] = 0x00115e7eadbabec0UL; vsxargs[i++] = 0xced0deede5ecef00UL;
+ vsxargs[i++] = 0x00111e7ea5abadb1UL; vsxargs[i++] = 0xbecad0deedeffe00UL;
+
+ vsxargs[i++] = 0x0011223344556677UL; vsxargs[i++] = 0x8899aabbccddeeffUL;
+ vsxargs[i++] = 0xf0e0d0c0b0a09080UL; vsxargs[i++] = 0x7060504030201000UL;
+#else
+ vsxargs[i++] = 0x0000000000000000UL; vsxargs[i++] = 0x0000000000000000UL;
+ vsxargs[i++] = 0x0102030405060708UL; vsxargs[i++] = 0x0102010201020102UL;
+
+ vsxargs[i++] = 0x0011223344556677UL; vsxargs[i++] = 0x8899aabbccddeeffUL;
+ vsxargs[i++] = 0xf0e0d0c0b0a09080UL; vsxargs[i++] = 0x7060504030201000UL;
+#endif
+
+ // these next three groups are specific for vector rotate tests.
+ // bits 11:15,19:23,27:31 of each 32-bit word contain mb,me,sh values.
+ vsxargs[i++] = 0x0000100000001002ULL; vsxargs[i++] = 0x0000100800001010ULL;
+ vsxargs[i++] = 0x0010100000101002ULL; vsxargs[i++] = 0x0010100800101010ULL;
+
+ // vector rotate special...
+ vsxargs[i++] = 0x00001c0000001c02ULL; vsxargs[i++] = 0x00001c0800001c10ULL;
+ vsxargs[i++] = 0x00101c0000101c02ULL; vsxargs[i++] = 0x00101c0800101c10ULL;
+
+ // vector rotate special...
+ vsxargs[i++] = 0x00001f0000001f02ULL; vsxargs[i++] = 0x00001f0800001f10ULL;
+ vsxargs[i++] = 0x00101f0000101f02ULL; vsxargs[i++] = 0x00101f0800101f10ULL;
+
+ AB_DPRINTF("Registered %d vargs values\n", i/2);
+ nb_vargs = i;
+}
+
+/* VPCV = Vector Permute Control Vector */
+unsigned long nb_vpcv;
+static unsigned long * vpcv = NULL;
+
+#define MAX_VPCV_SIZE 20
+
+static void build_vector_permute_table(void)
+{
+ int i=0;
+
+ vpcv = memalign(16, MAX_VPCV_SIZE * sizeof(unsigned long));
+
+#ifdef EXHAUSTIVE_TESTS
+ /* These two lines are complementary pairs of each other. */
+ vpcv[i++]=0x12021a0817141317ULL; vpcv[i++]=0x100d1b05070f0205ULL;
+ vpcv[i++]=0x0d1d0517080b0c08ULL; vpcv[i++]=0x0f12041a18101d1cULL;
+ vpcv[i++]=0x100d1b070f020505ULL; vpcv[i++]=0x0e201f1400130105ULL;
+ vpcv[i++]=0x0705030a0b01ea0cULL; vpcv[i++]=0x0e0c09010602080dULL;
+#else
+ vpcv[i++]=0x12021a0817141317ULL; vpcv[i++]=0x100d1b05070f0205ULL;
+ vpcv[i++]=0x0705030a0b01ea0cULL; vpcv[i++]=0x0e0c09010602080dULL;
+#endif
+ nb_vpcv=i;
+ AB_DPRINTF("Registered %d permute control vectors \n", nb_vpcv);
+
+ if (i >= MAX_VPCV_SIZE)
+ printf("Warning! Exceeded size of table building the vector permute control . \n");
+}
+
+/* Decimal Encodings...
+ * Packed, National, Zoned decimal content follows.
+ * Note: Watch the conversions in and out of the
+ * dwords / vectors for reverses with respect to
+ * top/bottom low/high
+ */
+
+/* Packed Decimals:
+ * A valid encoding of a packed decimal integer value requires the following
+ * properties:
+ * – Each of the 31 4-bit digits of the operand’s magnitude (bits 0:123)
+ * must be in the range 0-9.
+ * – The sign code (bits 124:127) must be in the range 10-15. (0xa-0xf).
+ * Source operands with sign codes of 0b1010, 0b1100, 0b1110, and 0b1111 are
+ * interpreted as positive values. Source operands with sign codes of
+ * 0b1011 and 0b1101 are interpreted as negative values.
+ * Positive and zero results are encoded with a either sign code of
+ * 0b1100 or 0b1111, depending on the preferred sign (indicated as an
+ * immediate operand). Negative results are encoded with a sign code
+ * of 0b1101.
+ * PS - This is the 'preferred sign' bit encoded in some BCD associated
+ * instructions.
+ */
+
+// Note: table content is limited to values encoded, not interpreted.
+unsigned int packed_decimal_sign_codes[] = {
+ /* positive operands */
+ 0xc, 0xf, // 0b1100, 0b1111
+
+ /* negative operands */
+ 0xd // 0b1101
+};
+
+#define NR_PACKED_DECIMAL_SIGNS 3
+#define MAX_PACKED_DECIMAL_TABLE_SIZE 8 * 16 * 2 + 20
+
+static unsigned long * packed_decimal_table;
+
+/* build into a pair of doubles */
+unsigned long nb_packed_decimal_entries;
+
+static void dissect_packed_decimal_sign(unsigned long local_sign) {
+ switch(local_sign) {
+ case 0xa: /*0b1010:*/ printf("[ + ]"); break;
+ case 0xb: /*0b1011:*/ printf("[ - ]"); break;
+ case 0xc: /*0b1100:*/ printf("(+|0)"); break;
+ case 0xd: /*0b1101:*/ printf("( - )"); break;
+ case 0xe: /*0b1110:*/ printf("[ + ]"); break;
+ case 0xf: /*0b1111:*/ printf("(+|0)"); break;
+ default: printf("(?%02lx)", local_sign);
+ }
+}
+
+int extract_packed_decimal_sign(unsigned long dword1, unsigned long dword0) {
+ return (dword1 & 0xf);
+}
+
+static void dissect_packed_decimal(unsigned long dword1,unsigned long dword0)
+{
+ int i;
+ int local_sign;
+ int nibble;
+
+ local_sign = extract_packed_decimal_sign(dword1, dword0);
+ printf("packed_decimal: [");
+
+ for (i = 60; i >= 0; i -= 4) {
+ nibble=(dword1 >> (i)) & 0xf;
+ printf(" %x", nibble);
+ }
+
+ for (i = 60; i >= 0; i -= 4) {
+ nibble=(dword0 >> (i)) & 0xf;
+ printf(" %x", nibble);
+ }
+
+ printf(" ");
+ dissect_packed_decimal_sign(local_sign);
+ printf(" ] ");
+}
+
+static void build_packed_decimal_table(void)
+{
+ long sign_index;
+ long sign_value;
+ unsigned long i = 0;
+ unsigned long value;
+ #ifdef EXHAUSTIVE_TESTS
+ int scramble;
+#endif
+
+ if (verbose) printf("%s\n", __FUNCTION__);
+
+ packed_decimal_table = malloc((MAX_PACKED_DECIMAL_TABLE_SIZE + 2)
+ * sizeof (unsigned long));
+
+ for (sign_index = 0; sign_index < NR_PACKED_DECIMAL_SIGNS; sign_index++) {
+ sign_value = packed_decimal_sign_codes[sign_index];
+
+ for (value = 0; value <= 9; value++) {
+ packed_decimal_table[i] = 0x1111111111111111 * value;
+ packed_decimal_table[i+1] = sign_value;
+ packed_decimal_table[i+1] += 0x1111111111111110 * value;
+
+ if (verbose>3) dissect_packed_decimal(packed_decimal_table[i+1],
+ packed_decimal_table[i]);
+ if (verbose>3) printf("\n");
+ i+=2;
+ }
+
+#ifdef EXHAUSTIVE_TESTS
+ for (scramble = 1; scramble <= 4; scramble++) {
+ packed_decimal_table[i] = 0x3210321032103210 * scramble;
+ packed_decimal_table[i+1] = sign_value;
+ packed_decimal_table[i+1] += 0x0123012301230120 * scramble;
+
+ if (verbose>3) dissect_packed_decimal(packed_decimal_table[i+1],
+ packed_decimal_table[i]);
+ if (verbose>3) printf("\n");
+ i+=2;
+ }
+#endif
+
+ /* Add some entries that will provide interesting output from
+ * the convert TO tests.
+ */
+ packed_decimal_table[i] = 0x0000000000000000;
+ packed_decimal_table[i+1] = sign_value;
+ packed_decimal_table[i+1] += 0x0000000012345670;
+
+ if (verbose > 3) dissect_packed_decimal(packed_decimal_table[i+1],
+ packed_decimal_table[i]);
+
+ if (verbose>3) printf("\n");
+
+ i += 2;
+
+#ifdef EXHAUSTIVE_TESTS
+ packed_decimal_table[i] = 0x0000000000000000;
+ packed_decimal_table[i+1] = sign_value;
+ packed_decimal_table[i+1] += 0x0000000098765430;
+
+ if (verbose > 3) dissect_packed_decimal(packed_decimal_table[i+1],
+ packed_decimal_table[i]);
+
+ if (verbose > 3) printf("\n");
+
+ i += 2;
+
+ packed_decimal_table[i] = 0x000000000000000b;
+ packed_decimal_table[i+1] = sign_value;
+ packed_decimal_table[i+1] += 0x0000000000000000;
+
+ if (verbose > 3) dissect_packed_decimal(packed_decimal_table[i+1],
+ packed_decimal_table[i]);
+
+ if (verbose>3) printf("\n");
+
+ i += 2;
+#endif
+
+ packed_decimal_table[i] = 0x0030000000000000;
+ packed_decimal_table[i+1] = sign_value;
+ packed_decimal_table[i+1] += 0x0000000000000000;
+
+ if (verbose > 3) dissect_packed_decimal(packed_decimal_table[i+1],
+ packed_decimal_table[i]);
+
+ if (verbose > 3) printf("\n");
+
+ i += 2;
+ }
+
+ if (verbose>2) printf("\n");
+
+ nb_packed_decimal_entries = i;
+}
+
+static void dump_packed_decimal_table(void) {
+ int i;
+
+ printf("packed_decimal_table:\n");
+
+ for (i = 0; i < nb_packed_decimal_entries; i += 2) {
+ printf("i =: %2d ", i);
+ dissect_packed_decimal(packed_decimal_table[i+1],
+ packed_decimal_table[i]);
+ printf("\n");
+ }
+}
+
+/* National decimals:
+ * A valid encoding of a national decimal value requires the following.
+ * – The contents of halfword 7 (sign code) must be
+ * either 0x002B or 0x002D.
+ * – The contents of halfwords 0 to 6 must be in the
+ * range 0x0030 to 0x0039.
+ * National decimal values having a sign code of 0x002B
+ * are interpreted as positive values.
+ * National decimal values having a sign code of 0x002D
+ * are interpreted as negative values.
+ */
+unsigned int national_decimal_sign_codes[] = {
+ /* positive */ 0x002b,
+ /* negative */ 0x002d
+};
+
+#define NR_NATIONAL_DECIMAL_SIGNS 2
+
+unsigned int national_decimal_values[] = {
+#ifdef EXHAUSTIVE_TESTS
+ 0x0030, 0x0031, 0x0032, 0x0033, 0x0034,
+ 0x0035, 0x0036, 0x0037, 0x0038, 0x0039
+#else
+ 0x0030, 0x0031,
+ 0x0035, 0x0039
+#endif
+};
+
+#define NR_NATIONAL_DECIMAL_VALUES (sizeof(national_decimal_values) / sizeof(unsigned int))
+
+static unsigned long * national_decimal_table;
+
+#define MAX_NATIONAL_DECIMAL_TABLE_SIZE 10 * NR_NATIONAL_DECIMAL_VALUES * NR_NATIONAL_DECIMAL_SIGNS
+
+unsigned long nb_national_decimal_entries;
+
+static void dissect_national_decimal_sign(unsigned long local_sign) {
+ switch(local_sign) {
+ case 0x002b:
+ printf("( + )");
+ break;
+
+ case 0x002d:
+ printf("( - )");
+ break;
+
+ default: printf("unhandled sign value: %lx", local_sign);
+ }
+}
+
+int extract_national_decimal_sign(unsigned long dword1, unsigned long dword0) {
+ return (dword1 & 0x0ff);
+}
+
+static void dissect_national_decimal(unsigned long dword1,
+ unsigned long dword0)
+{
+ int i;
+ int local_sign;
+ long hword;
+
+ printf("national_decimal: [");
+
+ if (verbose>4) printf("raw: [%016lx %016lx] ", dword1, dword0);
+
+ for (i = 48;i >= 0; i -= 16) {
+ hword = dword1 >> (i) & 0x00ff;
+
+ /* validity of national decimal value */
+ /* the i>0 clause skips the validity check against the sign value. */
+ if (((i > 0) && (hword < 0x30)) || (hword > 0x39)) printf("!");
+
+ printf("%04lx ", hword);
+ }
+
+ for (i = 48; i >= 0; i -= 16) {
+ hword = dword0 >> (i) & 0x00ff;
+
+ if ((hword < 0x30) || (hword > 0x39)) printf("!");
+
+ printf("%04lx ", hword);
+ }
+
+ local_sign = extract_national_decimal_sign(dword1, dword0);
+ dissect_national_decimal_sign(local_sign);
+ printf(" ] ");
+}
+
+static void build_national_decimal_table(void)
+{
+ long sign_index;
+ long sign_value;
+ unsigned long i = 0;
+ int index;
+ unsigned long value;
+
+ if (verbose) printf("%s\n",__FUNCTION__);
+ national_decimal_table = malloc(MAX_NATIONAL_DECIMAL_TABLE_SIZE
+ * sizeof (unsigned long));
+
+ for (sign_index = 0; sign_index < NR_NATIONAL_DECIMAL_SIGNS; sign_index++) {
+ sign_value = national_decimal_sign_codes[sign_index];
+
+ for (index = 0; index < NR_NATIONAL_DECIMAL_VALUES; index++) {
+ value = national_decimal_values[index];
+
+ national_decimal_table[i] = 0x0001000100010001 * value;
+ national_decimal_table[i+1] = 0x0001000100010000 * value;
+ national_decimal_table[i+1] += sign_value ;
+
+ if (verbose > 3) {
+ dissect_national_decimal(national_decimal_table[i+1],
+ national_decimal_table[i]);
+ printf("\n");
+ }
+ i += 2;
+ }
+#ifdef EXHAUSTIVE_TESTS
+ { /* a few more for fun */
+ national_decimal_table[i] = 0x0031003200330034;
+ national_decimal_table[i+1] = 0x0035003600370000;
+ national_decimal_table[i+1] += sign_value ;
+
+ if (verbose > 3) {
+ dissect_national_decimal(national_decimal_table[i+1],
+ national_decimal_table[i]);
+ printf("\n");
+ }
+
+ i += 2;
+ national_decimal_table[i] = 0x0031003200330034;
+ national_decimal_table[i+1] = 0x0035003600370000;
+ national_decimal_table[i+1] += sign_value ;
+
+ if (verbose > 3) {
+ dissect_national_decimal(national_decimal_table[i+1],
+ national_decimal_table[i]);
+ printf("\n");
+ }
+ i += 2;
+ }
+#endif
+ }
+
+ if (verbose > 2) printf("\n");
+
+ nb_national_decimal_entries = i;
+}
+
+static void dump_national_decimal_table(void) {
+ int i;
+
+ printf("national_decimal_table:\n");
+
+ for (i = 0; i < nb_national_decimal_entries; i += 2) {
+ printf("#%2d ", i);
+ dissect_national_decimal(national_decimal_table[i+1],
+ national_decimal_table[i]);
+ printf("\n");
+ }
+}
+
+
+/* Zoned Decimals:
+ *
+ * When PS=0, do the following.
+ * A valid encoding of a zoned decimal value requires the following.
+ * – The contents of bits 0:3 of byte 15 (sign code) can be any
+ * value in the range 0x0 to 0xF.
+ * – The contents of bits 0:3 of bytes 0 to 14 (zone) must
+ * be the value 0x3.
+ * – The contents of bits 4:7 of bytes 0 to 15 must
+ * be a value in the range 0x0 to 0x9.
+ * Zoned decimal values having a sign code of 0x0, 0x1, 0x2, 0x3,
+ * 0x8, 0x9, 0xA, or 0xB are interpreted as positive values.
+ * Zoned decimal values having a sign code of 0x4, 0x5, 0x6, 0x7,
+ * 0xC, 0xD, 0xE, or 0xF are interpreted as negative values.
+ :: 0,1,2,3, 8,9,a,b, are interpreted as positive.
+ :: 4,5,6,7, c,d,e,f are interpreted as negative.
+ * When PS=1, do the following.
+ * A valid encoding of a zoned decimal source operand requires the following.
+ * – The contents of bits 0:3 of byte 15 (sign code) must be a value in the
+ * range 0xA to 0xF.
+ * – The contents of bits 0:3 of bytes 0 to 14 (zone) must be the value 0xF.
+ * – The contents of bits 4:7 of bytes 0 to 15 must be a value in the
+ * range 0x0 to 0x9.
+ * Zoned decimal source operands having a sign code of 0xA, 0xC, 0xE,
+ * or 0xF are interpreted as positive values.
+ * Zoned decimal source operands having a sign code of 0xB or 0xD are
+ * interpreted as negative values.
+ :: a, c, e,f are interpreted as positive.
+ :: b, d, are interpreted as negative.
+ */
+
+/* a valid sign is anything in range 0-9,a-f,
+ * For coverage that does not overwhelm, we have chosen to use 0,1,4,a,b,f. */
+#define NM_ZONED_DECIMAL_SIGNS 6
+#define NM_ZONED_VALUES 5 /* 0,2,4,6,9 */
+#define NM_PS_VALUES 2 /* 0,1 */
+#define NM_ZONED_ADDITIONAL_PATTERNS 4
+#define MAX_ZONED_DECIMAL_TABLE_SIZE NM_ZONED_DECIMAL_SIGNS * NM_ZONED_VALUES * NM_ZONED_ADDITIONAL_PATTERNS * NM_PS_VALUES + 10
+
+static unsigned long zoned_decimal_table_[MAX_ZONED_DECIMAL_TABLE_SIZE];
+static unsigned long * zoned_decimal_table;
+unsigned long nb_zoned_decimal_entries;
+
+static void dissect_zoned_decimal_sign(unsigned long local_sign, int ps) {
+ if (ps == 0) {
+ switch(local_sign) {
+ case 0x0: case 0x1: case 0x2: case 0x3:
+ case 0x8: case 0x9: case 0xa: case 0xb:
+ printf("( + )");
+ break;
+
+ case 0x4: case 0x5: case 0x6: case 0x7:
+ case 0xc: case 0xd: case 0xe: case 0xf:
+ printf("( - )");
+ break;
+ default: printf("zoned decimal (ps=%d). Unhandled sign value: %lx",
+ ps, local_sign);
+ }
+ }
+
+ if (ps == 1) {
+ switch(local_sign) {
+ case 0xa: case 0xc: case 0xe: case 0xf:
+ printf("( + )");
+ break;
+
+ case 0xb: case 0xd:
+ printf("( - )");
+ break;
+
+ default: printf("zoned decimal (ps=%d). Unhandled sign value: %lx",
+ ps, local_sign);
+ }
+ }
+}
+
+/* Valid byte values within a zoned decimal are in the ranges of
+ * 0x30..0x39 when PS==0, or 0xf0..0xff when PS==1.
+ */
+static void check_zoned_byte_validity(int byte, int ps) {
+ if (ps == 0) {
+ /* check the zone */
+ if (((byte & 0x30) != 0x30))
+ printf("!=30");
+
+ } else { /* ps==1 */
+ if (((byte & 0xf0) != 0xf0))
+ printf("%x !=f0 ", byte );
+ }
+
+ /* check the numeric value */
+ if ((byte & 0x0f) > 0x9)
+ printf("!(0..9)");
+}
+
+int extract_zoned_decimal_sign(unsigned long dword1, unsigned long dword0) {
+ return ((dword1 & 0xf0) >> 4);
+}
+
+static void dissect_zoned_decimal(unsigned long dword1, unsigned long dword0,
+ int ps)
+{
+ int i;
+ int local_sign;
+ int byte;
+
+ printf("zoned_decimal: [");
+
+ for (i = 56; i >= 0; i -= 8) {
+ byte = (dword1 >> (i)) & 0xff;
+ check_zoned_byte_validity(byte, ps);
+ printf(" %02x", byte);
+ }
+
+ for (i = 56; i >= 0; i -= 8) {
+ byte = (dword0 >> (i)) & 0x00ff;
+ check_zoned_byte_validity(byte, ps);
+
+ if ((byte & 0xf) > 0x9) printf(" !(>9)");
+ printf(" %02x", byte);
+ }
+
+ local_sign = extract_zoned_decimal_sign(dword1, dword0);
+ dissect_zoned_decimal_sign(local_sign, ps);
+ printf(" ]");
+}
+
+#ifdef EXHAUSTIVE_TESTS
+// Randomly chosen exhaustive coverage for k includes values: 0,2,4,7,9
+# define SELECTIVE_INCREMENT_ZONED(k) \
+ if (k == 7) k = 9; \
+ else if (k == 4) k = 7; \
+ else if (k == 2) k = 4; \
+ else if (k == 0) k = 2; \
+ else k++;
+// Randomly chosen exhaustive coverage for signs includes values: 0,1,4,a,b,f
+# define SELECTIVE_INCREMENT_SIGNS(signs) \
+ if (signs == 0x0) signs = 0x1; \
+ else if (signs == 0x1) signs = 0x4; \
+ else if (signs == 0x4) signs = 0xa; \
+ else if (signs == 0xa) signs = 0xb; \
+ else if (signs == 0xb) signs = 0xf; \
+ else signs++;
+#else
+// Randomly chosen coverage for k includes values: 0,7,9
+# define SELECTIVE_INCREMENT_ZONED(k) \
+ if (k == 7) k = 9; \
+ else if (k == 0) k = 7; \
+ else k++;
+// Randomly chosen coverage for signs includes values: 0,4,b,f
+# define SELECTIVE_INCREMENT_SIGNS(signs) \
+ if (signs == 0x0) signs = 0x4; \
+ else if (signs == 0x4) signs = 0xb; \
+ else if (signs == 0xb) signs = 0xf; \
+ else signs++;
+#endif
+
+
+static void build_zoned_decimal_table(void)
+{
+ unsigned long signs;
+ unsigned long i;
+ int k;
+ int ps;
+ int signs_start,signs_end;
+
+ if (verbose) printf("%s\n", __FUNCTION__);
+
+ zoned_decimal_table = zoned_decimal_table_;
+ i = 0;
+
+ for (ps = 0; ps <= 1; ps++) {
+ if (ps == 0) {
+ signs_start = 0;
+ signs_end = 0xf;
+
+ } else {
+ signs_start = 0xa;
+ signs_end = 0xf;
+ }
+
+ for (signs = signs_start;
+ signs <= signs_end; /* signs selectively updated below */) {
+
+ if (verbose > 2) printf("ps=%d sign:%lx\n", ps, signs);
+
+ for (k = 0 ; k < 9; /* k selectively updated below */) {
+ if (ps == 0) {
+ zoned_decimal_table[i] = 0x3030303030303030; // set bits 0:3 of bytes 0..7.
+ zoned_decimal_table[i+1] = 0x3030303030303000; // bits 0:3 of bytes 8..14 must be 0x3
+
+ } else {
+ zoned_decimal_table[i] = 0xf0f0f0f0f0f0f0f0; // set bits 0:3 of bytes 0..7.
+ zoned_decimal_table[i+1] = 0xf0f0f0f0f0f0f000; // bits 0:3 of bytes 8..14 must be 0x3
+ }
+
+ zoned_decimal_table[i] += 0x010101010101010 * k; // set bits 4..7 of bytes 0..7.
+ zoned_decimal_table[i+1] += 0x010101010101000 * k; // bits 4:7 of bytes 8..15 must be 0..9.
+ zoned_decimal_table[i+1] += (signs << 4); // bits 0:3 of byte 15 is the sign.
+ if (verbose > 3) {
+ dissect_zoned_decimal(zoned_decimal_table[i+1],
+ zoned_decimal_table[i], ps);
+ printf("\n");
+ }
+ i += 2;
+ SELECTIVE_INCREMENT_ZONED(k)
+ }
+
+ /* add a few more patterns outside of the k patterns. */
+ if (ps == 0) {
+ zoned_decimal_table[i] = 0x3030303030303030;
+ zoned_decimal_table[i+1] = 0x3030303030303000;
+
+ } else {
+ zoned_decimal_table[i] = 0xf0f0f0f0f0f0f0f0;
+ zoned_decimal_table[i+1] = 0xf0f0f0f0f0f0f000;
+ }
+
+ zoned_decimal_table[i] += 0x0908070605040302;
+ zoned_decimal_table[i+1] += 0x0102030405060700;
+ zoned_decimal_table[i+1] += (signs<<4); // bits 0:3 of byte 15.
+
+ if (verbose > 3) {
+ dissect_zoned_decimal(zoned_decimal_table[i+1],
+ zoned_decimal_table[i], ps);
+ printf("\n");
+ }
+
+ i += 2;
+ SELECTIVE_INCREMENT_SIGNS(signs)
+ } /* signs loop */
+ } /* ps loop */
+
+ nb_zoned_decimal_entries = i;
+}
+
+static void dump_zoned_decimal_table(void) {
+ int i;
+ int ps;
+
+ for (ps = 0; ps <= 1; ps++) {
+ printf("zoned_decimal_table ps=%d:\n", ps);
+
+ for (i = 0; i < nb_zoned_decimal_entries; i += 2) {
+ printf("#%2d ", i);
+ dissect_zoned_decimal(zoned_decimal_table[i+1],
+ zoned_decimal_table[i], ps);
+ printf("\n");
+ }
+ }
+}
+
+/* Build table containing shift and truncate values */
+#define MAX_DECIMAL_SHIFT_TABLE_SIZE 64
+
+static unsigned long * decimal_shift_table;
+unsigned long nb_decimal_shift_entries;
+
+static void build_decimal_shift_table(void) {
+ unsigned long i = 0;
+ unsigned long value;
+
+ if (verbose) printf("%s\n",__FUNCTION__);
+
+ decimal_shift_table = malloc(MAX_DECIMAL_SHIFT_TABLE_SIZE
+ * sizeof (unsigned long));
+
+ for (value = 0; value <= 31; value++) {
+ decimal_shift_table[i] = value;
+ decimal_shift_table[i+1] = 0;
+ i += 2;
+ }
+
+ if (verbose>2) printf("\n");
+
+ nb_decimal_shift_entries = i;
+}
+
+static void dump_decimal_shift_table(void) {
+ int i;
+
+ printf("decimal_shift_table:\n");
+
+ for (i = 0; i < nb_decimal_shift_entries; i += 2) {
+ printf("i=:%2d ", i);
+ printf(" 0x%2lx 0x%2lx ", decimal_shift_table[i],
+ decimal_shift_table[i+1]);
+ printf("\n");
+ }
+}
diff --git a/none/tests/ppc64/round.c b/none/tests/ppc64/round.c
deleted file mode 120000
index eb50244..0000000
--- a/none/tests/ppc64/round.c
+++ /dev/null
@@ -1 +0,0 @@
-../ppc32/round.c
\ No newline at end of file
diff --git a/none/tests/ppc64/round.c b/none/tests/ppc64/round.c
new file mode 100644
index 0000000..a92440a
--- /dev/null
+++ b/none/tests/ppc64/round.c
@@ -0,0 +1,1232 @@
+
+/* Copyright (C) 2006 Dave Nomura
+ dcnltc@us.ibm.com
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <limits.h>
+
+typedef enum { FALSE=0, TRUE } bool_t;
+
+typedef enum {
+ FADDS, FSUBS, FMULS, FDIVS,
+ FMADDS, FMSUBS, FNMADDS, FNMSUBS,
+ FADD, FSUB, FMUL, FDIV, FMADD,
+ FMSUB, FNMADD, FNMSUB, FSQRT
+} flt_op_t;
+
+typedef enum {
+ TO_NEAREST=0, TO_ZERO, TO_PLUS_INFINITY, TO_MINUS_INFINITY } round_mode_t;
+char *round_mode_name[] = { "near", "zero", "+inf", "-inf" };
+
+const char *flt_op_names[] = {
+ "fadds", "fsubs", "fmuls", "fdivs",
+ "fmadds", "fmsubs", "fnmadds", "fnmsubs",
+ "fadd", "fsub", "fmul", "fdiv", "fmadd", "fmsub", "fnmadd",
+ "fnmsub", "fsqrt"
+};
+
+typedef unsigned int fpscr_t;
+
+typedef union {
+ float flt;
+ struct {
+#if defined(VGP_ppc64le_linux)
+ unsigned int frac:23;
+ unsigned int exp:8;
+ unsigned int sign:1;
+#else
+ unsigned int sign:1;
+ unsigned int exp:8;
+ unsigned int frac:23;
+#endif
+ } layout;
+} flt_overlay;
+
+typedef union {
+ double dbl;
+ struct {
+#if defined(VGP_ppc64le_linux)
+ unsigned int frac_lo:32;
+ unsigned int frac_hi:20;
+ unsigned int exp:11;
+ unsigned int sign:1;
+#else
+ unsigned int sign:1;
+ unsigned int exp:11;
+ unsigned int frac_hi:20;
+ unsigned int frac_lo:32;
+#endif
+ } layout;
+ struct {
+ unsigned int hi;
+ unsigned int lo;
+ } dbl_pair;
+} dbl_overlay;
+
+void assert_fail(const char *msg,
+ const char* expr, const char* file, int line, const char*fn);
+
+#define STRING(__str) #__str
+#define assert(msg, expr) \
+ ((void) ((expr) ? 0 : \
+ (assert_fail (msg, STRING(expr), \
+ __FILE__, __LINE__, \
+ __PRETTY_FUNCTION__), 0)))
+float denorm_small;
+double dbl_denorm_small;
+float norm_small;
+bool_t debug = FALSE;
+bool_t long_is_64_bits = sizeof(long) == 8;
+
+void assert_fail (msg, expr, file, line, fn)
+const char* msg;
+const char* expr;
+const char* file;
+int line;
+const char*fn;
+{
+ printf( "\n%s: %s:%d (%s): Assertion `%s' failed.\n",
+ msg, file, line, fn, expr );
+ exit( 1 );
+}
+void set_rounding_mode(round_mode_t mode)
+{
+ switch(mode) {
+ case TO_NEAREST:
+ asm volatile("mtfsfi 7, 0");
+ break;
+ case TO_ZERO:
+ asm volatile("mtfsfi 7, 1");
+ break;
+ case TO_PLUS_INFINITY:
+ asm volatile("mtfsfi 7, 2");
+ break;
+ case TO_MINUS_INFINITY:
+ asm volatile("mtfsfi 7, 3");
+ break;
+ }
+}
+
+void print_double(char *msg, double dbl)
+{
+ dbl_overlay D;
+ D.dbl = dbl;
+
+ printf("%15s : dbl %-20a = %c(%4d, %05x%08x)\n",
+ msg, D.dbl, (D.layout.sign == 0 ? '+' : '-'),
+ D.layout.exp, D.layout.frac_hi, D.layout.frac_lo);
+}
+
+void print_single(char *msg, float *flt)
+{
+ flt_overlay F;
+ F.flt = *flt;
+
+ /* NOTE: for the purposes of comparing the fraction of a single with
+ ** a double left shift the .frac so that hex digits are grouped
+ ** from left to right. this is necessary because the size of a
+ ** single mantissa (23) bits is not a multiple of 4
+ */
+ printf("%15s : flt %-20a = %c(%4d, %06x)\n",
+ msg, F.flt, (F.layout.sign == 0 ? '+' : '-'), F.layout.exp, F.layout.frac << 1);
+}
+
+int check_dbl_to_flt_round(round_mode_t mode, double dbl, float *expected)
+{
+ int status = 0;
+ flt_overlay R, E;
+ char *result;
+
+ set_rounding_mode(mode);
+
+ E.flt = *expected;
+ R.flt = (float)dbl;
+
+ if ((R.layout.sign != E.layout.sign) ||
+ (R.layout.exp != E.layout.exp) ||
+ (R.layout.frac != E.layout.frac)) {
+ result = "FAILED";
+ status = 1;
+ } else {
+ result = "PASSED";
+ status = 0;
+ }
+ printf("%s:%s:(double)(%-20a) = %20a",
+ round_mode_name[mode], result, R.flt, dbl);
+ if (status) {
+ print_single("\n\texpected", &E.flt);
+ print_single("\n\trounded ", &R.flt);
+ }
+ putchar('\n');
+ return status;
+}
+
+int test_dbl_to_float_convert(char *msg, float *base)
+{
+ int status = 0;
+ double half = (double)denorm_small/2;
+ double qtr = half/2;
+ double D_hi = (double)*base + half + qtr;
+ double D_lo = (double)*base + half - qtr;
+ float F_lo = *base;
+ float F_hi = F_lo + denorm_small;
+
+
+ /*
+ ** .....+-----+-----+-----+-----+---....
+ ** ^F_lo ^ ^ ^
+ ** D_lo
+ ** D_hi
+ ** F_hi
+ ** F_lo and F_hi are two consecutive single float model numbers
+ ** denorm_small distance apart. D_lo and D_hi are two numbers
+ ** within that range that are not representable as single floats
+ ** and will be rounded to either F_lo or F_hi.
+ */
+ printf("-------------------------- %s --------------------------\n", msg);
+ if (debug) {
+ print_double("D_lo", D_lo);
+ print_double("D_hi", D_hi);
+ print_single("F_lo", &F_lo);
+ print_single("F_hi", &F_hi);
+ }
+
+ /* round to nearest */
+ status |= check_dbl_to_flt_round(TO_NEAREST, D_hi, &F_hi);
+ status |= check_dbl_to_flt_round(TO_NEAREST, D_lo, &F_lo);
+
+ /* round to zero */
+ status |= check_dbl_to_flt_round(TO_ZERO, D_hi, (D_hi > 0 ? &F_lo : &F_hi));
+ status |= check_dbl_to_flt_round(TO_ZERO, D_lo, (D_hi > 0 ? &F_lo : &F_hi));
+
+ /* round to +inf */
+ status |= check_dbl_to_flt_round(TO_PLUS_INFINITY, D_hi, &F_hi);
+ status |= check_dbl_to_flt_round(TO_PLUS_INFINITY, D_lo, &F_hi);
+
+ /* round to -inf */
+ status |= check_dbl_to_flt_round(TO_MINUS_INFINITY, D_hi, &F_lo);
+ status |= check_dbl_to_flt_round(TO_MINUS_INFINITY, D_lo, &F_lo);
+ return status;
+}
+
+void
+init()
+{
+ flt_overlay F;
+ dbl_overlay D;
+
+ /* small is the smallest denormalized single float number */
+ F.layout.sign = 0;
+ F.layout.exp = 0;
+ F.layout.frac = 1;
+ denorm_small = F.flt; /* == 2^(-149) */
+ if (debug) {
+ print_single("float small", &F.flt);
+ }
+
+ D.layout.sign = 0;
+ D.layout.exp = 0;
+ D.layout.frac_hi = 0;
+ D.layout.frac_lo = 1;
+ dbl_denorm_small = D.dbl; /* == 2^(-1022) */
+ if (debug) {
+ print_double("double small", D.dbl);
+ }
+
+ /* n_small is the smallest normalized single precision float */
+ F.layout.exp = 1;
+ norm_small = F.flt;
+}
+
+int check_int_to_flt_round(round_mode_t mode, long L, float *expected)
+{
+ int status = 0;
+ int I = L;
+ char *int_name = "int";
+ flt_overlay R, E;
+ char *result;
+ int iter;
+
+ set_rounding_mode(mode);
+ E.flt = *expected;
+
+ for (iter = 0; iter < 2; iter++) {
+ int stat = 0;
+ R.flt = (iter == 0 ? (float)I : (float)L);
+
+ if ((R.layout.sign != E.layout.sign) ||
+ (R.layout.exp != E.layout.exp) ||
+ (R.layout.frac != E.layout.frac)) {
+ result = "FAILED";
+ stat = 1;
+ } else {
+ result = "PASSED";
+ stat = 0;
+ }
+ printf("%s:%s:(float)(%4s)%9d = %11.1f",
+ round_mode_name[mode], result, int_name, I, R.flt);
+ if (stat) {
+ print_single("\n\texpected: %.1f ", &E.flt);
+ print_single("\n\trounded ", &R.flt);
+ }
+ putchar('\n');
+ status |= stat;
+
+ if (!long_is_64_bits) break;
+ int_name = "long";
+ }
+ return status;
+}
+
+int check_long_to_dbl_round(round_mode_t mode, long L, double *expected)
+{
+ int status = 0;
+ dbl_overlay R, E;
+ char *result;
+
+ set_rounding_mode(mode);
+ E.dbl = *expected;
+
+ R.dbl = (double)L;
+
+ if ((R.layout.sign != E.layout.sign) ||
+ (R.layout.exp != E.layout.exp) ||
+ (R.layout.frac_lo != E.layout.frac_lo) ||
+ (R.layout.frac_hi != E.layout.frac_hi)) {
+ result = "FAILED";
+ status = 1;
+ } else {
+ result = "PASSED";
+ status = 0;
+ }
+ printf("%s:%s:(double)(%18ld) = %20.1f",
+ round_mode_name[mode], result, L, R.dbl);
+ if (status) {
+ printf("\n\texpected %.1f : ", E.dbl);
+ }
+ putchar('\n');
+ return status;
+}
+
+int test_int_to_float_convert(char *msg)
+{
+ int status = 0;
+ int int24_hi = 0x03ff0fff;
+ int int24_lo = 0x03ff0ffd;
+ float pos_flt_lo = 67047420.0;
+ float pos_flt_hi = 67047424.0;
+ float neg_flt_lo = -67047420.0;
+ float neg_flt_hi = -67047424.0;
+
+ printf("-------------------------- %s --------------------------\n", msg);
+ status |= check_int_to_flt_round(TO_NEAREST, int24_lo, &pos_flt_lo);
+ status |= check_int_to_flt_round(TO_NEAREST, int24_hi, &pos_flt_hi);
+ status |= check_int_to_flt_round(TO_ZERO, int24_lo, &pos_flt_lo);
+ status |= check_int_to_flt_round(TO_ZERO, int24_hi, &pos_flt_lo);
+ status |= check_int_to_flt_round(TO_PLUS_INFINITY, int24_lo, &pos_flt_hi);
+ status |= check_int_to_flt_round(TO_PLUS_INFINITY, int24_hi, &pos_flt_hi);
+ status |= check_int_to_flt_round(TO_MINUS_INFINITY, int24_lo, &pos_flt_lo);
+ status |= check_int_to_flt_round(TO_MINUS_INFINITY, int24_hi, &pos_flt_lo);
+
+ status |= check_int_to_flt_round(TO_NEAREST, -int24_lo, &neg_flt_lo);
+ status |= check_int_to_flt_round(TO_NEAREST, -int24_hi, &neg_flt_hi);
+ status |= check_int_to_flt_round(TO_ZERO, -int24_lo, &neg_flt_lo);
+ status |= check_int_to_flt_round(TO_ZERO, -int24_hi, &neg_flt_lo);
+ status |= check_int_to_flt_round(TO_PLUS_INFINITY, -int24_lo, &neg_flt_lo);
+ status |= check_int_to_flt_round(TO_PLUS_INFINITY, -int24_hi, &neg_flt_lo);
+ status |= check_int_to_flt_round(TO_MINUS_INFINITY, -int24_lo, &neg_flt_hi);
+ status |= check_int_to_flt_round(TO_MINUS_INFINITY, -int24_hi, &neg_flt_hi);
+ return status;
+}
+
+#ifdef __powerpc64__
+int test_long_to_double_convert(char *msg)
+{
+ int status = 0;
+ long long55_hi = 0x07ff0ffffffffff;
+ long long55_lo = 0x07ff0fffffffffd;
+ double pos_dbl_lo = 36012304344547324.0;
+ double pos_dbl_hi = 36012304344547328.0;
+ double neg_dbl_lo = -36012304344547324.0;
+ double neg_dbl_hi = -36012304344547328.0;
+
+ printf("-------------------------- %s --------------------------\n", msg);
+ status |= check_long_to_dbl_round(TO_NEAREST, long55_lo, &pos_dbl_lo);
+ status |= check_long_to_dbl_round(TO_NEAREST, long55_hi, &pos_dbl_hi);
+ status |= check_long_to_dbl_round(TO_ZERO, long55_lo, &pos_dbl_lo);
+ status |= check_long_to_dbl_round(TO_ZERO, long55_hi, &pos_dbl_lo);
+ status |= check_long_to_dbl_round(TO_PLUS_INFINITY, long55_lo, &pos_dbl_hi);
+ status |= check_long_to_dbl_round(TO_PLUS_INFINITY, long55_hi, &pos_dbl_hi);
+ status |= check_long_to_dbl_round(TO_MINUS_INFINITY, long55_lo, &pos_dbl_lo);
+ status |= check_long_to_dbl_round(TO_MINUS_INFINITY, long55_hi, &pos_dbl_lo);
+
+ status |= check_long_to_dbl_round(TO_NEAREST, -long55_lo, &neg_dbl_lo);
+ status |= check_long_to_dbl_round(TO_NEAREST, -long55_hi, &neg_dbl_hi);
+ status |= check_long_to_dbl_round(TO_ZERO, -long55_lo, &neg_dbl_lo);
+ status |= check_long_to_dbl_round(TO_ZERO, -long55_hi, &neg_dbl_lo);
+ status |= check_long_to_dbl_round(TO_PLUS_INFINITY, -long55_lo, &neg_dbl_lo);
+ status |= check_long_to_dbl_round(TO_PLUS_INFINITY, -long55_hi, &neg_dbl_lo);
+ status |= check_long_to_dbl_round(TO_MINUS_INFINITY, -long55_lo, &neg_dbl_hi);
+ status |= check_long_to_dbl_round(TO_MINUS_INFINITY, -long55_hi, &neg_dbl_hi);
+ return status;
+}
+#endif
+
+int check_single_arithmetic_op(flt_op_t op)
+{
+ char *result;
+ int status = 0;
+ dbl_overlay R, E;
+ double qtr, half, fA, fB, fD;
+ round_mode_t mode;
+ int q, s;
+ bool_t two_args = TRUE;
+ float whole = denorm_small;
+
+#define BINOP(op) \
+ __asm__ volatile( \
+ op" %0, %1, %2\n\t" \
+ : "=f"(fD) : "f"(fA) , "f"(fB));
+#define UNOP(op) \
+ __asm__ volatile( \
+ op" %0, %1\n\t" \
+ : "=f"(fD) : "f"(fA));
+
+ half = (double)whole/2;
+ qtr = half/2;
+
+ if (debug) {
+ print_double("qtr", qtr);
+ print_double("whole", whole);
+ print_double("2*whole", 2*whole);
+ }
+
+ for (mode = TO_NEAREST; mode <= TO_MINUS_INFINITY; mode++)
+ for (s = -1; s < 2; s += 2)
+ for (q = 1; q < 4; q += 2) {
+ double expected;
+ double lo = s*whole;
+ double hi = s*2*whole;
+
+ switch(op) {
+ case FADDS:
+ fA = s*whole;
+ fB = s*q*qtr;
+ break;
+ case FSUBS:
+ fA = s*2*whole;
+ fB = s*(q == 1 ? 3 : 1)*qtr;
+ break;
+ case FMULS:
+ fA = 0.5;
+ fB = s*(4+q)*half;
+ break;
+ case FDIVS:
+ fA = s*(4+q)*half;
+ fB = 2.0;
+ break;
+ default:
+ assert("check_single_arithmetic_op: unexpected op",
+ FALSE);
+ break;
+ }
+
+ switch(mode) {
+ case TO_NEAREST:
+ expected = (q == 1 ? lo : hi);
+ break;
+ case TO_ZERO:
+ expected = lo;
+ break;
+ case TO_PLUS_INFINITY:
+ expected = (s == 1 ? hi : lo);
+ break;
+ case TO_MINUS_INFINITY:
+ expected = (s == 1 ? lo : hi);
+ break;
+ }
+
+ set_rounding_mode(mode);
+
+ /*
+ ** do the double precision dual operation just for comparison
+ ** when debugging
+ */
+ switch(op) {
+ case FADDS:
+ BINOP("fadds");
+ R.dbl = fD;
+ BINOP("fadd");
+ break;
+ case FSUBS:
+ BINOP("fsubs");
+ R.dbl = fD;
+ BINOP("fsub");
+ break;
+ case FMULS:
+ BINOP("fmuls");
+ R.dbl = fD;
+ BINOP("fmul");
+ break;
+ case FDIVS:
+ BINOP("fdivs");
+ R.dbl = fD;
+ BINOP("fdiv");
+ break;
+ default:
+ assert("check_single_arithmetic_op: unexpected op",
+ FALSE);
+ break;
+ }
+#undef UNOP
+#undef BINOP
+
+ E.dbl = expected;
+
+ if ((R.layout.sign != E.layout.sign) ||
+ (R.layout.exp != E.layout.exp) ||
+ (R.layout.frac_lo != E.layout.frac_lo) ||
+ (R.layout.frac_hi != E.layout.frac_hi)) {
+ result = "FAILED";
+ status = 1;
+ } else {
+ result = "PASSED";
+ status = 0;
+ }
+
+ printf("%s:%s:%s(%-13a",
+ round_mode_name[mode], result, flt_op_names[op], fA);
+ if (two_args) printf(", %-13a", fB);
+ printf(") = %-13a", R.dbl);
+ if (status) printf("\n\texpected %a", E.dbl);
+ putchar('\n');
+
+ if (debug) {
+ print_double("hi", hi);
+ print_double("lo", lo);
+ print_double("expected", expected);
+ print_double("got", R.dbl);
+ print_double("double result", fD);
+ }
+ }
+
+ return status;
+}
+
+int check_single_guarded_arithmetic_op(flt_op_t op)
+{
+ typedef struct {
+ int num, den, frac;
+ } fdivs_t;
+
+ char *result;
+ int status = 0;
+ flt_overlay A, B, Z;
+ dbl_overlay Res, Exp;
+ double fA, fB, fC, fD;
+ round_mode_t mode;
+ int g, s;
+ int arg_count;
+
+ fdivs_t divs_guard_cases[16] = {
+ { 105, 56, 0x700000 }, /* : 0 */
+ { 100, 57, 0x608FB8 }, /* : 1 */
+ { 000, 00, 0x000000 }, /* : X */
+ { 100, 52, 0x762762 }, /* : 3 */
+ { 000, 00, 0x000000 }, /* : X */
+ { 100, 55, 0x68BA2E }, /* : 5 */
+ { 000, 00, 0x000000 }, /* : X */
+ { 100, 51, 0x7AFAFA }, /* : 7 */
+ { 000, 00, 0x000000 }, /* : X */
+ { 100, 56, 0x649249 }, /* : 9 */
+ { 000, 00, 0x000000 }, /* : X */
+ { 100, 54, 0x6D097B }, /* : B */
+ { 000, 00, 0x000000 }, /* : X */
+ { 100, 59, 0x58F2FB }, /* : D */
+ { 000, 00, 0x000000 }, /* : X */
+ { 101, 52, 0x789D89 } /* : F */
+ };
+
+ /* 0x1.00000 00000000p-3 */
+ /* set up the invariant fields of B, the arg to cause rounding */
+ B.flt = 0.0;
+ B.layout.exp = 124; /* -3 */
+
+ /* set up args so result is always Z = 1.200000000000<g>p+0 */
+ Z.flt = 1.0;
+ Z.layout.sign = 0;
+
+#define TERNOP(op) \
+ arg_count = 3; \
+ __asm__ volatile( \
+ op" %0, %1, %2, %3\n\t" \
+ : "=f"(fD) : "f"(fA) , "f"(fB), "f"(fC));
+#define BINOP(op) \
+ arg_count = 2; \
+ __asm__ volatile( \
+ op" %0, %1, %2\n\t" \
+ : "=f"(fD) : "f"(fA) , "f"(fB));
+#define UNOP(op) \
+ arg_count = 1; \
+ __asm__ volatile( \
+ op" %0, %1\n\t" \
+ : "=f"(fD) : "f"(fA));
+
+ for (mode = TO_NEAREST; mode <= TO_MINUS_INFINITY; mode++)
+ for (s = -1; s < 2; s += 2)
+ for (g = 0; g < 16; g += 1) {
+ double lo, hi, expected;
+ int LSB;
+ int guard = 0;
+ int z_sign = s;
+
+ /*
+ ** one argument will have exponent = 0 as will the result (by
+ ** design) so choose the other argument with exponent -3 to
+ ** force a 3 bit shift for scaling leaving us with 3 guard bits
+ ** and the LSB bit at the bottom of the manitssa.
+ */
+ switch(op) {
+ case FADDS:
+ /* 1p+0 + 1.00000<g>p-3 */
+ B.layout.frac = g;
+
+ fB = s*B.flt;
+ fA = s*1.0;
+
+ /* set up Z to be truncated result */
+
+ /* mask off LSB from resulting guard bits */
+ guard = g & 7;
+
+ Z.layout.frac = 0x100000 | (g >> 3);
+ break;
+ case FSUBS:
+ /* 1.200002p+0 - 1.000000000000<g>p-3 */
+ A.flt = 1.125;
+ /* add enough to avoid scaling of the result */
+ A.layout.frac |= 0x2;
+ fA = s*A.flt;
+
+ B.layout.frac = g;
+ fB = s*B.flt;
+
+ /* set up Z to be truncated result */
+ guard = (0x10-g);
+ Z.layout.frac = guard>>3;
+
+ /* mask off LSB from resulting guard bits */
+ guard &= 7;
+ break;
+ case FMULS:
+ /* 1 + g*2^-23 */
+ A.flt = 1.0;
+ A.layout.frac = g;
+ fA = s*A.flt;
+ fB = 1.125;
+
+ /* set up Z to be truncated result */
+ Z.flt = 1.0;
+ Z.layout.frac = 0x100000;
+ Z.layout.frac |= g + (g>>3);
+ guard = g & 7;
+ break;
+ case FDIVS:
+ /* g >> 3 == LSB, g & 7 == guard bits */
+ guard = g & 7;
+ if ((guard & 1) == 0) {
+ /* special case: guard bit X = 0 */
+ A.flt = denorm_small;
+ A.layout.frac = g;
+ fA = A.flt;
+ fB = s*8.0;
+ Z.flt = 0.0;
+ Z.layout.frac |= (g >> 3);
+ } else {
+ fA = s*divs_guard_cases[g].num;
+ fB = divs_guard_cases[g].den;
+
+ Z.flt = 1.0;
+ Z.layout.frac = divs_guard_cases[g].frac;
+ }
+ break;
+ case FMADDS:
+ case FMSUBS:
+ case FNMADDS:
+ case FNMSUBS:
+ /* 1 + g*2^-23 */
+ A.flt = 1.0;
+ A.layout.frac = g;
+ fA = s*A.flt;
+ fB = 1.125;
+
+ /* 1.000001p-1 */
+ A.flt = 0.5;
+ A.layout.frac = 1;
+ fC = (op == FMADDS || op == FNMADDS ? s : -s)*A.flt;
+
+ /* set up Z to be truncated result */
+ z_sign = (op == FNMADDS || op == FNMSUBS ? -s : s);
+ guard = ((g & 7) + 0x4) & 7;
+ Z.flt = 1.0;
+ Z.layout.frac = 0x500000;
+ Z.layout.frac |= g + (g>>3) + ((g & 7)>> 2 ? 1 : 0);
+ break;
+ default:
+ assert("check_single_arithmetic_op: unexpected op",
+ FALSE);
+ break;
+ }
+
+ /* get LSB for tie breaking */
+ LSB = Z.layout.frac & 1;
+
+ /* set up hi and lo */
+ lo = z_sign*Z.flt;
+ Z.layout.frac += 1;
+ hi = z_sign*Z.flt;
+
+ switch(mode) {
+ case TO_NEAREST:
+ /* look at 3 guard bits to determine expected rounding */
+ switch(guard) {
+ case 0:
+ case 1: case 2: case 3:
+ expected = lo;
+ break;
+ case 4: /* tie: round to even */
+ if (debug) printf("tie: LSB = %d\n", LSB);
+ expected = (LSB == 0 ? lo : hi);
+ break;
+ case 5: case 6: case 7:
+ expected = hi;
+ break;
+ default:
+ assert("check_single_guarded_arithmetic_op: unexpected guard",
+ FALSE);
+ }
+ break;
+ case TO_ZERO:
+ expected = lo;
+ break;
+ case TO_PLUS_INFINITY:
+ if (guard == 0) {
+ /* no rounding */
+ expected = lo;
+ } else {
+ expected = (s == 1 ? hi : lo);
+ }
+ break;
+ case TO_MINUS_INFINITY:
+ if (guard == 0) {
+ /* no rounding */
+ expected = lo;
+ } else {
+ expected = (s == 1 ? lo : hi);
+ }
+ break;
+ }
+
+ set_rounding_mode(mode);
+
+ /*
+ ** do the double precision dual operation just for comparison
+ ** when debugging
+ */
+ switch(op) {
+ case FADDS:
+ BINOP("fadds");
+ Res.dbl = fD;
+ break;
+ case FSUBS:
+ BINOP("fsubs");
+ Res.dbl = fD;
+ break;
+ case FMULS:
+ BINOP("fmuls");
+ Res.dbl = fD;
+ break;
+ case FDIVS:
+ BINOP("fdivs");
+ Res.dbl = fD;
+ break;
+ case FMADDS:
+ TERNOP("fmadds");
+ Res.dbl = fD;
+ break;
+ case FMSUBS:
+ TERNOP("fmsubs");
+ Res.dbl = fD;
+ break;
+ case FNMADDS:
+ TERNOP("fnmadds");
+ Res.dbl = fD;
+ break;
+ case FNMSUBS:
+ TERNOP("fnmsubs");
+ Res.dbl = fD;
+ break;
+ default:
+ assert("check_single_guarded_arithmetic_op: unexpected op",
+ FALSE);
+ break;
+ }
+#undef UNOP
+#undef BINOP
+#undef TERNOP
+
+ Exp.dbl = expected;
+
+ if ((Res.layout.sign != Exp.layout.sign) ||
+ (Res.layout.exp != Exp.layout.exp) ||
+ (Res.layout.frac_lo != Exp.layout.frac_lo) ||
+ (Res.layout.frac_hi != Exp.layout.frac_hi)) {
+ result = "FAILED";
+ status = 1;
+ } else {
+ result = "PASSED";
+ status = 0;
+ }
+
+ /* There seems to be some noise in the lower bits. The value
+ * on the least significant digit seems to vary when printing
+ * based on the rounding mode of the compiler. Just trying
+ * to get rid of the noise in the least significant bits when
+ * printing the operand.
+ */
+
+ fA = ((long int)(fA*10000))/10000.0;
+ /* Change -0.0 to a positive 0.0. Some compilers print -0.0
+ * others do not. Make it consistent.
+ */
+ if (fA == -0.0)
+ fA = 0.0;
+
+ printf("%s:%s:%s(%-13.6f",
+ round_mode_name[mode], result, flt_op_names[op], fA);
+ if (arg_count > 1) printf(", %-13a", fB);
+ if (arg_count > 2) printf(", %-13a", fC);
+ printf(") = %-13a", Res.dbl);
+ if (status) printf("\n\texpected %a", Exp.dbl);
+ putchar('\n');
+
+ if (debug) {
+ print_double("hi", hi);
+ print_double("lo", lo);
+ print_double("expected", expected);
+ print_double("got", Res.dbl);
+ }
+ }
+
+ return status;
+}
+
+int check_double_guarded_arithmetic_op(flt_op_t op)
+{
+ typedef struct {
+ int num, den, hi, lo;
+ } fdiv_t;
+ typedef struct {
+ double arg;
+ int exp, hi, lo;
+ } fsqrt_t;
+
+ char *result;
+ int status = 0;
+ dbl_overlay A, B, Z;
+ dbl_overlay Res, Exp;
+ double fA, fB, fC, fD;
+ round_mode_t mode;
+ int g, s;
+ int arg_count;
+ fdiv_t div_guard_cases[16] = {
+ { 62, 62, 0x00000, 0x00000000 }, /* 0 */
+ { 64, 62, 0x08421, 0x08421084 }, /* 1 */
+ { 66, 62, 0x10842, 0x10842108 }, /* 2 */
+ { 100, 62, 0x9ce73, 0x9ce739ce }, /* 3 */
+ { 100, 62, 0x9ce73, 0x9ce739ce }, /* X */
+ { 102, 62, 0xa5294, 0xa5294a52 }, /* 5 */
+ { 106, 62, 0xb5ad6, 0xb5ad6b5a }, /* 6 */
+ { 108, 62, 0xbdef7, 0xbdef7bde }, /* 7 */
+ { 108, 108, 0x00000, 0x00000000 }, /* 8 */
+ { 112, 62, 0xce739, 0xce739ce7 }, /* 9 */
+ { 114, 62, 0xd6b5a, 0xd6b5ad6b }, /* A */
+ { 116, 62, 0xdef7b, 0xdef7bdef }, /* B */
+ { 84, 62, 0x5ad6b, 0x5ad6b5ad }, /* X */
+ { 118, 62, 0xe739c, 0xe739ce73 }, /* D */
+ { 90, 62, 0x739ce, 0x739ce739 }, /* E */
+ { 92, 62, 0x7bdef, 0x7bdef7bd } /* F */
+ };
+
+
+ fsqrt_t sqrt_guard_cases[16] = {
+ { 0x1.08800p0, 0, 0x04371, 0xd9ab72fb}, /* :0 B8.8440 */
+ { 0x0.D2200p0, -1, 0xcfdca, 0xf353049e}, /* :1 A4.6910 */
+ { 0x1.A8220p0, 0, 0x49830, 0x2b49cd6d}, /* :2 E9.D411 */
+ { 0x1.05A20p0, 0, 0x02cd1, 0x3b44f3bf}, /* :3 B7.82D1 */
+ { 0x0.CA820p0, -1, 0xc7607, 0x3cec0937}, /* :4 A1.6541 */
+ { 0x1.DCA20p0, 0, 0x5d4f8, 0xd4e4c2b2}, /* :5 F7.EE51 */
+ { 0x1.02C80p0, 0, 0x01630, 0x9cde7483}, /* :6 B6.8164 */
+ { 0x0.DC800p0, -1, 0xdb2cf, 0xe686fe7c}, /* :7 A8.6E40 */
+ { 0x0.CF920p0, -1, 0xcd089, 0xb6860626}, /* :8 A3.67C9 */
+ { 0x1.1D020p0, 0, 0x0e1d6, 0x2e78ed9d}, /* :9 BF.8E81 */
+ { 0x0.E1C80p0, -1, 0xe0d52, 0x6020fb6b}, /* :A AA.70E4 */
+ { 0x0.C8000p0, -1, 0xc48c6, 0x001f0abf}, /* :B A0.6400 */
+ { 0x1.48520p0, 0, 0x21e9e, 0xd813e2e2}, /* :C CD.A429 */
+ { 0x0.F4C20p0, -1, 0xf4a1b, 0x09bbf0b0}, /* :D B1.7A61 */
+ { 0x0.CD080p0, -1, 0xca348, 0x79b907ae}, /* :E A2.6684 */
+ { 0x1.76B20p0, 0, 0x35b67, 0x81aed827} /* :F DB.BB59 */
+ };
+
+ /* 0x1.00000 00000000p-3 */
+ /* set up the invariant fields of B, the arg to cause rounding */
+ B.dbl = 0.0;
+ B.layout.exp = 1020;
+
+ /* set up args so result is always Z = 1.200000000000<g>p+0 */
+ Z.dbl = 1.0;
+ Z.layout.sign = 0;
+
+#define TERNOP(op) \
+ arg_count = 3; \
+ __asm__ volatile( \
+ op" %0, %1, %2, %3\n\t" \
+ : "=f"(fD) : "f"(fA) , "f"(fB), "f"(fC));
+#define BINOP(op) \
+ arg_count = 2; \
+ __asm__ volatile( \
+ op" %0, %1, %2\n\t" \
+ : "=f"(fD) : "f"(fA) , "f"(fB));
+#define UNOP(op) \
+ arg_count = 1; \
+ __asm__ volatile( \
+ op" %0, %1\n\t" \
+ : "=f"(fD) : "f"(fA));
+
+ for (mode = TO_NEAREST; mode <= TO_MINUS_INFINITY; mode++)
+ for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2)
+ for (g = 0; g < 16; g += 1) {
+ double lo, hi, expected;
+ int LSB;
+ int guard;
+ int z_sign = s;
+
+ /*
+ ** one argument will have exponent = 0 as will the result (by
+ ** design) so choose the other argument with exponent -3 to
+ ** force a 3 bit shift for scaling leaving us with 3 guard bits
+ ** and the LSB bit at the bottom of the manitssa.
+ */
+ switch(op) {
+ case FADD:
+ /* 1p+0 + 1.000000000000<g>p-3 */
+ B.layout.frac_lo = g;
+
+ fB = s*B.dbl;
+ fA = s*1.0;
+
+ /* set up Z to be truncated result */
+
+ /* mask off LSB from resulting guard bits */
+ guard = g & 7;
+
+ Z.layout.frac_hi = 0x20000;
+ Z.layout.frac_lo = g >> 3;
+
+ break;
+ case FSUB:
+ /* 1.2000000000002p+0 - 1.000000000000<g>p-3 */
+ A.dbl = 1.125;
+ /* add enough to avoid scaling of the result */
+ A.layout.frac_lo = 0x2;
+ fA = s*A.dbl;
+
+ B.layout.frac_lo = g;
+ fB = s*B.dbl;
+
+ /* set up Z to be truncated result */
+ guard = (0x10-g);
+ Z.layout.frac_hi = 0x0;
+ Z.layout.frac_lo = guard>>3;
+
+ /* mask off LSB from resulting guard bits */
+ guard &= 7;
+ break;
+ case FMUL:
+ /* 1 + g*2^-52 */
+ A.dbl = 1.0;
+ A.layout.frac_lo = g;
+ fA = s*A.dbl;
+ fB = 1.125;
+
+ /* set up Z to be truncated result */
+ Z.dbl = 1.0;
+ Z.layout.frac_hi = 0x20000;
+ Z.layout.frac_lo = g + (g>>3);
+ guard = g & 7;
+ break;
+ case FMADD:
+ case FMSUB:
+ case FNMADD:
+ case FNMSUB:
+ /* 1 + g*2^-52 */
+ A.dbl = 1.0;
+ A.layout.frac_lo = g;
+ fA = s*A.dbl;
+ fB = 1.125;
+
+ /* 1.0000000000001p-1 */
+ A.dbl = 0.5;
+ A.layout.frac_lo = 1;
+ fC = (op == FMADD || op == FNMADD ? s : -s)*A.dbl;
+
+ /* set up Z to be truncated result */
+ z_sign = (op == FNMADD || op == FNMSUB ? -s : s);
+ guard = ((g & 7) + 0x4) & 7;
+ Z.dbl = 1.0;
+ Z.layout.frac_hi = 0xa0000;
+ Z.layout.frac_lo = g + (g>>3) + ((g & 7)>> 2 ? 1 : 0);
+ break;
+ case FDIV:
+ /* g >> 3 == LSB, g & 7 == guard bits */
+ guard = g & 7;
+ if (guard == 0x4) {
+ /* special case guard bits == 4, inexact tie */
+ fB = s*2.0;
+ Z.dbl = 0.0;
+ if (g >> 3) {
+ fA = dbl_denorm_small + 2*dbl_denorm_small;
+ Z.layout.frac_lo = 0x1;
+ } else {
+ fA = dbl_denorm_small;
+ }
+ } else {
+ fA = s*div_guard_cases[g].num;
+ fB = div_guard_cases[g].den;
+
+ printf("%d/%d\n",
+ s*div_guard_cases[g].num,
+ div_guard_cases[g].den);
+ Z.dbl = 1.0;
+ Z.layout.frac_hi = div_guard_cases[g].hi;
+ Z.layout.frac_lo = div_guard_cases[g].lo;
+ }
+ break;
+ case FSQRT:
+ fA = s*sqrt_guard_cases[g].arg;
+ Z.dbl = 1.0;
+ Z.layout.exp = sqrt_guard_cases[g].exp + 1023;
+ Z.layout.frac_hi = sqrt_guard_cases[g].hi;
+ Z.layout.frac_lo = sqrt_guard_cases[g].lo;
+ guard = g >> 1;
+ if (g & 1) guard |= 1;
+ /* don't have test cases for when X bit = 0 */
+ if (guard == 0 || guard == 4) continue;
+ break;
+ default:
+ assert("check_double_guarded_arithmetic_op: unexpected op",
+ FALSE);
+ break;
+ }
+
+ /* get LSB for tie breaking */
+ LSB = Z.layout.frac_lo & 1;
+
+ /* set up hi and lo */
+ lo = z_sign*Z.dbl;
+ Z.layout.frac_lo += 1;
+ hi = z_sign*Z.dbl;
+
+ switch(mode) {
+ case TO_NEAREST:
+ /* look at 3 guard bits to determine expected rounding */
+ switch(guard) {
+ case 0:
+ case 1: case 2: case 3:
+ expected = lo;
+ break;
+ case 4: /* tie: round to even */
+ if (debug) printf("tie: LSB = %d\n", LSB);
+ expected = (LSB == 0 ? lo : hi);
+ break;
+ case 5: case 6: case 7:
+ expected = hi;
+ break;
+ default:
+ assert("check_double_guarded_arithmetic_op: unexpected guard",
+ FALSE);
+ }
+ break;
+ case TO_ZERO:
+ expected = lo;
+ break;
+ case TO_PLUS_INFINITY:
+ if (guard == 0) {
+ /* no rounding */
+ expected = lo;
+ } else {
+ expected = (s == 1 ? hi : lo);
+ }
+ break;
+ case TO_MINUS_INFINITY:
+ if (guard == 0) {
+ /* no rounding */
+ expected = lo;
+ } else {
+ expected = (s == 1 ? lo : hi);
+ }
+ break;
+ }
+
+ set_rounding_mode(mode);
+
+ /*
+ ** do the double precision dual operation just for comparison
+ ** when debugging
+ */
+ switch(op) {
+ case FADD:
+ BINOP("fadd");
+ Res.dbl = fD;
+ break;
+ case FSUB:
+ BINOP("fsub");
+ Res.dbl = fD;
+ break;
+ case FMUL:
+ BINOP("fmul");
+ Res.dbl = fD;
+ break;
+ case FMADD:
+ TERNOP("fmadd");
+ Res.dbl = fD;
+ break;
+ case FMSUB:
+ TERNOP("fmsub");
+ Res.dbl = fD;
+ break;
+ case FNMADD:
+ TERNOP("fnmadd");
+ Res.dbl = fD;
+ break;
+ case FNMSUB:
+ TERNOP("fnmsub");
+ Res.dbl = fD;
+ break;
+ case FDIV:
+ BINOP("fdiv");
+ Res.dbl = fD;
+ break;
+ case FSQRT:
+ UNOP("fsqrt");
+ Res.dbl = fD;
+ break;
+ default:
+ assert("check_double_guarded_arithmetic_op: unexpected op",
+ FALSE);
+ break;
+ }
+#undef UNOP
+#undef BINOP
+#undef TERNOP
+
+ Exp.dbl = expected;
+
+ if ((Res.layout.sign != Exp.layout.sign) ||
+ (Res.layout.exp != Exp.layout.exp) ||
+ (Res.layout.frac_lo != Exp.layout.frac_lo) ||
+ (Res.layout.frac_hi != Exp.layout.frac_hi)) {
+ result = "FAILED";
+ status = 1;
+ } else {
+ result = "PASSED";
+ status = 0;
+ }
+
+ printf("%s:%s:%s(%-13a",
+ round_mode_name[mode], result, flt_op_names[op], fA);
+ if (arg_count > 1) printf(", %-13a", fB);
+ if (arg_count > 2) printf(", %-13a", fC);
+ printf(") = %-13a", Res.dbl);
+ if (status) printf("\n\texpected %a", Exp.dbl);
+ putchar('\n');
+
+ if (debug) {
+ print_double("hi", hi);
+ print_double("lo", lo);
+ print_double("expected", expected);
+ print_double("got", Res.dbl);
+ }
+ }
+
+ return status;
+}
+
+int test_float_arithmetic_ops()
+{
+ int status = 0;
+ flt_op_t op;
+
+ /*
+ ** choose FP operands whose result should be rounded to either
+ ** lo or hi.
+ */
+
+ printf("-------------------------- %s --------------------------\n",
+ "test rounding of float operators without guard bits");
+ for (op = FADDS; op <= FDIVS; op++) {
+ status |= check_single_arithmetic_op(op);
+ }
+
+ printf("-------------------------- %s --------------------------\n",
+ "test rounding of float operators with guard bits");
+ for (op = FADDS; op <= FNMSUBS; op++) {
+ status |= check_single_guarded_arithmetic_op(op);
+ }
+
+ printf("-------------------------- %s --------------------------\n",
+ "test rounding of double operators with guard bits");
+ for (op = FADD; op <= FSQRT; op++) {
+ status |= check_double_guarded_arithmetic_op(op);
+ }
+ return status;
+}
+
+
+int
+main()
+{
+ int status = 0;
+
+ init();
+
+ status |= test_dbl_to_float_convert("test denormalized convert", &denorm_small);
+ status |= test_dbl_to_float_convert("test normalized convert", &norm_small);
+ status |= test_int_to_float_convert("test (float)int convert");
+ status |= test_int_to_float_convert("test (float)int convert");
+
+#ifdef __powerpc64__
+ status |= test_long_to_double_convert("test (double)long convert");
+#endif
+ status |= test_float_arithmetic_ops();
+ return status;
+}
diff --git a/none/tests/ppc64/test_dfp1.c b/none/tests/ppc64/test_dfp1.c
deleted file mode 120000
index dc077d4..0000000
--- a/none/tests/ppc64/test_dfp1.c
+++ /dev/null
@@ -1 +0,0 @@
-../../../none/tests/ppc32/test_dfp1.c
\ No newline at end of file
diff --git a/none/tests/ppc64/test_dfp1.c b/none/tests/ppc64/test_dfp1.c
new file mode 100644
index 0000000..40c3a10
--- /dev/null
+++ b/none/tests/ppc64/test_dfp1.c
@@ -0,0 +1,504 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#if defined(HAS_DFP)
+
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+register double f18 __asm__ ("fr18");
+register double f19 __asm__ ("fr19");
+
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+
+// The assembly-level instructions being tested
+static Bool do_dot;
+static void _test_dadd (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dadd. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dadd %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dsub (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dsub. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dsub %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dmul (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dmul. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dmul %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_ddiv (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("ddiv. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("ddiv %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+// Quad DFP arith instructions
+static void _test_daddq (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("daddq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("daddq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dsubq (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dsubq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dsubq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dmulq (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("dmulq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("dmulq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_ddivq (void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("ddivq. %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+ else
+ __asm__ __volatile__ ("ddivq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_mffs (void)
+{
+ __asm__ __volatile__ ("mffs %0" : "=f"(f14));
+}
+
+static void _test_mtfsf (int upper)
+{
+ if (upper)
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) );
+ else
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 0" : : "f"(f14) );
+}
+
+typedef void (*test_func_t)(void);
+typedef struct test_table
+{
+ test_func_t test_category;
+ char * name;
+} test_table_t;
+
+/*
+ * 345.0DD (0x2207c00000000000 0xe50)
+ * 1.2300e+5DD (0x2207c00000000000 0x14c000)
+ * -16.0DD (0xa207c00000000000 0xe0)
+ * 0.00189DD (0x2206c00000000000 0xcf)
+ * -4.1235DD (0xa205c00000000000 0x10a395bcf)
+ * 9.8399e+20DD (0x2209400000000000 0x253f1f534acdd4)
+ * 0DD (0x2208000000000000 0x0)
+ * 0DD (0x2208000000000000 0x0)
+ * infDD (0x7800000000000000 0x0)
+ * nanDD (0x7c00000000000000 0x0
+ */
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2207c00000000000ULL, 0x000000000014c000ULL,
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // huge number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// huge number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+
+typedef struct dfp_test_args {
+ int fra_idx;
+ int frb_idx;
+} dfp_test_args_t;
+
+
+// Index pairs from dfp64_vals or dfp128_vals array to be used with dfp_two_arg_tests
+static dfp_test_args_t dfp_2args_x2[] = {
+ {0, 1},
+ {2, 1},
+ {3, 4},
+ {0, 6},
+ {2, 4},
+ {5, 1},
+ {5, 2},
+ {7, 8},
+ {7, 1},
+ {9, 15},
+ {8, 12},
+ {7, 11},
+ {13, 2},
+ {13, 14},
+ {15, 12},
+ {14, 11},
+ {12, 12},
+ {12, 11},
+ {11, 11}
+};
+
+// Index pairs from dfp64_vals array to be used with dfp_two_arg_tests
+static dfp_test_args_t dfp_2args_x1[] = {
+ {0, 1},
+ {2, 1},
+ {3, 4},
+ {0, 6},
+ {2, 4},
+ {5, 1},
+ {5, 2},
+ {7, 1},
+ {7, 2},
+ {8, 0},
+ {8, 1},
+ {8, 2},
+ {7, 8},
+ {12, 14},
+ {12, 1},
+ {12, 13},
+ {12, 12},
+ {12, 11},
+ {11, 14},
+ {11, 0},
+ {11, 13},
+ {11, 11},
+ {14, 14},
+ {14, 3},
+ {14, 15},
+};
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_test
+{
+ test_func_t test_func;
+ const char * name;
+ dfp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ const char * op;
+ Bool cr_supported;
+} dfp_test_t;
+
+
+static dfp_test_t
+dfp_two_arg_tests[] = {
+ { &_test_dadd, "dadd", dfp_2args_x1, 25, LONG_TEST, "+", False},
+ { &_test_dsub, "dsub", dfp_2args_x1, 25, LONG_TEST, "-", False},
+ { &_test_dmul, "dmul", dfp_2args_x2, 19, LONG_TEST, "*", False},
+ { &_test_ddiv, "ddiv", dfp_2args_x2, 19, LONG_TEST, "/", False},
+ { &_test_daddq, "daddq", dfp_2args_x1, 25, QUAD_TEST, "+", False},
+ { &_test_dsubq, "dsubq", dfp_2args_x1, 25, QUAD_TEST, "-", False},
+ { &_test_dmulq, "dmulq", dfp_2args_x2, 19, QUAD_TEST, "*", False},
+ { &_test_ddivq, "ddivq", dfp_2args_x2, 19, QUAD_TEST, "/", False},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+static void test_dfp_two_arg_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x, u1, u1x;
+ double res, d0, d1, *d0p, *d1p;
+ double d0x, d1x, *d0xp, *d1xp;
+ int k = 0;
+ u0x = u1x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ d1p = &d1;
+ d1xp = &d1x;
+
+ while ((func = dfp_two_arg_tests[k].test_func)) {
+ int i, repeat = 1;
+ dfp_test_t test_group = dfp_two_arg_tests[k];
+ do_dot = False;
+
+again:
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int condreg;
+ unsigned int flags;
+
+ if (test_group.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_group.targs[i].fra_idx];
+ u1 = dfp64_vals[test_group.targs[i].frb_idx];
+ } else {
+ u0 = dfp128_vals[test_group.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_group.targs[i].fra_idx * 2) + 1];
+ u1 = dfp128_vals[test_group.targs[i].frb_idx * 2];
+ u1x = dfp128_vals[(test_group.targs[i].frb_idx * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ *(unsigned long long *)d1p = u1;
+ f14 = d0;
+ f16 = d1;
+ if (test_group.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ *(unsigned long long *)d1xp = u1x;
+ f15 = d0x;
+ f17 = d1x;
+ }
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ res = f18;
+
+ condreg = (flags & 0x000000f0) >> 4;
+ printf("%s%s %016llx", test_group.name, do_dot? "." : "", u0);
+ if (test_group.precision == LONG_TEST) {
+ printf(" %s %016llx => %016llx",
+ test_group.op, u1, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx %s %016llx %016llx ==> %016llx %016llx",
+ u0x, test_group.op, u1, u1x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ if (test_group.cr_supported)
+ printf(" (cr = %08x)\n", condreg);
+ else
+ printf("\n");
+
+ }
+ printf("\n");
+ if (repeat) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+void test_move_toFrom_fpscr(void)
+{
+#define BFP_MAX_RM 3
+ int shift = 0;
+ unsigned long long i, max_rm, expected_val;
+ double fpscr_in, fpscr_out;
+ unsigned long long * hex_fpscr_in = (unsigned long long *)&fpscr_in;
+ unsigned long long * hex_fpscr_out = (unsigned long long *)&fpscr_out;
+
+
+ max_rm = 4;
+again:
+ /* NOTE: The first time through this loop is for setting the binary
+ * floating point rounding mode (bits 62:63 of FPSCR). The second time
+ * through is for setting the decimal floating point rounding mode
+ * (bits 29:31 of FPSCR). In the second time through this loop, the value
+ * returned should include the final binary FP rounding mode, along with
+ * the decimal FP rounding modes.
+ */
+ for (i = 0; i < max_rm; i++) {
+ *hex_fpscr_in = (i << shift);
+ f14 = fpscr_in;
+ _test_mtfsf(max_rm/8);
+ *hex_fpscr_in = 0ULL;
+ f14= fpscr_in;
+ _test_mffs();
+ fpscr_out = f14;
+ if (max_rm == 4) {
+ *hex_fpscr_out &= (max_rm - 1) << shift;
+ expected_val = i << shift;
+ } else {
+ *hex_fpscr_out &= BFP_MAX_RM | ((max_rm - 1) << shift);
+ expected_val = (i << shift) | BFP_MAX_RM;
+ }
+
+ printf("FPSCR %s floating point rounding mode %016llx == %016llx? %s\n",
+ (max_rm == 8) ? "decimal" : "binary",
+ *hex_fpscr_out, expected_val,
+ (expected_val == *hex_fpscr_out) ? "yes" : "no");
+ }
+ if (max_rm == 4) {
+ max_rm = 8;
+ shift = 32;
+ goto again;
+ }
+}
+
+void test_rounding_modes(void)
+{
+ int j;
+ unsigned long long u0, u1, rm_idx;
+ double res, d0, d1, *d0p, *d1p, fpscr;
+ unsigned long long * hex_fpscr = (unsigned long long *)&fpscr;
+ u0 = 0x26cc3f1f534acdd4ULL;
+ u1 = 0x27feff197a42ba06ULL;
+ d0p = &d0;
+ d1p = &d1;
+
+ for (j = 0; j < 12; j++) {
+ for (rm_idx = 0; rm_idx < 8; rm_idx++) {
+ *hex_fpscr = 0ULL;
+ __asm__ __volatile__ ("mffs %0" : "=f"(f14));
+ fpscr = f14;
+ *hex_fpscr &= 0xFFFFFFF0FFFFFFFFULL;
+ *hex_fpscr |= (rm_idx << 32);
+ f14 = fpscr;
+ SET_FPSCR_DRN;
+ *(unsigned long long *)d0p = u0;
+ *(unsigned long long *)d1p = u1;
+ f14 = d0;
+ f16 = d1;
+ _test_dmul();
+ res = f18;
+ printf("test #%d: dmul with rounding mode %d: %016llx * %016llx => %016llx\n",
+ j, (int)rm_idx, u0, u1, *((unsigned long long *)(&res)));
+ printf("\n");
+ }
+ // Changing the least significant bit of one of the dmul arguments give us more
+ // opportunities for different rounding modes to yield different results which
+ // can then be validated.
+ u0++;
+ }
+}
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_dfp_two_arg_ops,
+ "Test DFP arithmetic instructions"},
+ { &test_rounding_modes,
+ "Test DFP rounding modes"},
+ { &test_move_toFrom_fpscr,
+ "Test move to/from FPSCR"},
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main() {
+#if defined(HAS_DFP)
+
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/none/tests/ppc64/test_dfp2.c b/none/tests/ppc64/test_dfp2.c
deleted file mode 120000
index 635ad7b..0000000
--- a/none/tests/ppc64/test_dfp2.c
+++ /dev/null
@@ -1 +0,0 @@
-../../../none/tests/ppc32/test_dfp2.c
\ No newline at end of file
diff --git a/none/tests/ppc64/test_dfp2.c b/none/tests/ppc64/test_dfp2.c
new file mode 100644
index 0000000..31bdae9
--- /dev/null
+++ b/none/tests/ppc64/test_dfp2.c
@@ -0,0 +1,675 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+ Carl Love <carll@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <elf.h>
+#include <link.h>
+
+#define PPC_FEATURE_HAS_VSX 0x00000080 /* Vector Scalar Extension. */
+
+#if defined(HAS_DFP)
+
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+register double f18 __asm__ ("fr18");
+register double f19 __asm__ ("fr19");
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+#define SH_0 0
+#define SH_1 1
+#define SH_2 15
+#define SH_3 63
+
+#define NUM_RND_MODES 8
+#define CONDREG_MASK 0x0f000000
+#define CONDREG_SHIFT 24
+
+static char ** my_envp;
+static inline char** __auxv_find(void)
+{
+ char **result = my_envp;
+ /* Scan over the env vector looking for the ending NULL */
+ for (; *result != NULL; ++result) {
+ }
+ /* Bump the pointer one more step, which should be the auxv. */
+ return ++result;
+}
+
+static unsigned long fetch_at_hwcap(void)
+{
+ static unsigned long auxv_hwcap = 0;
+ int i;
+ ElfW(auxv_t) * auxv_buf = NULL;
+
+ if (auxv_hwcap)
+ return auxv_hwcap;
+
+ auxv_buf = (ElfW(auxv_t)*) __auxv_find();
+ for (i = 0; auxv_buf[i].a_type != AT_NULL; i++)
+ if (auxv_buf[i].a_type == AT_HWCAP) {
+ auxv_hwcap = auxv_buf[i].a_un.a_val;
+ break;
+ }
+
+ return auxv_hwcap;
+}
+
+int get_vsx(void)
+{
+ /* Check to see if the AUX vector has the bit set indicating the HW
+ * supports the vsx instructions. This implies the processor is
+ * at least a POWER 7.
+ */
+ unsigned long hwcap;
+
+ hwcap = fetch_at_hwcap();
+ if ((hwcap & PPC_FEATURE_HAS_VSX) == PPC_FEATURE_HAS_VSX)
+ return 1;
+
+ return 0;
+}
+
+/* The assembly-level instructions being tested */
+static void _test_dscri (int shift)
+{
+ switch(shift) {
+ case SH_0:
+ __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
+ break;
+
+ case SH_1:
+ __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
+ break;
+
+ case SH_2:
+ __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
+ break;
+
+ case SH_3:
+ __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
+ break;
+ default:
+ printf(" dscri, unsupported shift case %d\n", shift);
+ }
+}
+
+static void _test_dscli (int shift)
+{
+ switch(shift) {
+ case SH_0:
+ __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
+ break;
+
+ case SH_1:
+ __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
+ break;
+
+ case SH_2:
+ __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
+ break;
+
+ case SH_3:
+ __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
+ break;
+ default:
+ printf(" dscli, unsupported shift case %d\n", shift);
+ }
+}
+
+static void _test_dctdp (void)
+{
+ __asm__ __volatile__ ("dctdp %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_drsp (void)
+{
+ __asm__ __volatile__ ("drsp %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_dctfix (void)
+{
+ __asm__ __volatile__ ("dctfix %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+/* Power 7 and newer processors support this instruction */
+static void _test_dcffix (void)
+{
+ __asm__ __volatile__ ("dcffix %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_dscriq (int shift)
+{
+ switch(shift) {
+ case SH_0:
+ __asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
+ break;
+ case SH_1:
+ __asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
+ break;
+ case SH_2:
+ __asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
+ break;
+ case SH_3:
+ __asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
+ break;
+ default:
+ printf(" dscriq, unsupported shift case %d\n", shift);
+ }
+}
+
+static void _test_dscliq (int shift)
+{
+ switch(shift) {
+ case SH_0:
+ __asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
+ break;
+ case SH_1:
+ __asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
+ break;
+ case SH_2:
+ __asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
+ break;
+ case SH_3:
+ __asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
+ break;
+ default:
+ printf(" dscliq, unsupported shift case %d\n", shift);
+ }
+}
+
+static void _test_dctqpq (void)
+{
+ __asm__ __volatile__ ("dctqpq %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_dctfixq (void)
+{
+ __asm__ __volatile__ ("dctfixq %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_drdpq (void)
+{
+ __asm__ __volatile__ ("drdpq %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+static void _test_dcffixq (void)
+{
+ __asm__ __volatile__ ("dcffixq %0, %1" : "=f" (f18) : "f" (f14));
+}
+
+typedef void (*test_func_t)();
+typedef void (*test_func_main_t)(int);
+typedef void (*test_func_shift_t)(int);
+typedef struct test_table
+{
+ test_func_main_t test_category;
+ char * name;
+} test_table_t;
+
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2f07c00000000000ULL, 0x000000000014c000ULL, //large number
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // a small number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long int64_vals[] = {
+ // I64 values
+ 0x0ULL, // zero
+ 0x1ULL, // one
+ 0xffffffffffffffffULL, // minus one
+ 0x2386f26fc0ffffULL, // 9999999999999999
+ 0xffdc790d903f0001ULL, // -9999999999999999
+ 0x462d53c8abac0ULL, // 1234567890124567
+ 0xfffb9d2ac3754540ULL, // -1234567890124567
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// large number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+
+typedef struct dfp_test_args {
+ int fra_idx;
+ int frb_idx;
+} dfp_test_args_t;
+
+
+/* Index pairs from dfp64_vals or dfp128_vals array to be used with
+ * dfp_two_arg_tests */
+static dfp_test_args_t int64_args_x1[] = {
+ /* {int64 input val, unused } */
+ {0, 0},
+ {1, 0},
+ {2, 0},
+ {3, 0},
+ {4, 0},
+ {5, 0},
+ {6, 0},
+};
+
+static dfp_test_args_t dfp_2args_x1[] = {
+ /* {dfp_arg, shift_arg} */
+ {0, SH_0},
+ {0, SH_1},
+ {0, SH_2},
+ {0, SH_3},
+ {5, SH_0},
+ {5, SH_1},
+ {5, SH_2},
+ {5, SH_3},
+ {6, SH_0},
+ {6, SH_1},
+ {6, SH_2},
+ {6, SH_3},
+ {7, SH_0},
+ {7, SH_1},
+ {7, SH_2},
+ {7, SH_3},
+ {10, SH_0},
+ {10, SH_1},
+ {10, SH_2},
+ {10, SH_3},
+ {13, SH_0},
+ {13, SH_1},
+ {13, SH_2},
+ {13, SH_3},
+};
+
+/* Index pairs from dfp64_vals array to be used with dfp_one_arg_tests */
+static dfp_test_args_t dfp_1args_x1[] = {
+ /* {dfp_arg, unused} */
+ {0, 0},
+ {1, 0},
+ {2, 0},
+ {3, 0},
+ {4, 0},
+ {5, 0},
+ {6, 0},
+ {7, 0},
+ {8, 0},
+ {9, 0},
+ {10, 0},
+ {11, 0},
+ {12, 0},
+ {13, 0},
+ {14, 0},
+};
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_test
+{
+ test_func_t test_func;
+ const char * name;
+ dfp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ const char * op;
+ Bool cr_supported;
+} dfp_test_t;
+
+/* The dcffix and dcffixq tests are a little different in that they both take
+ * an I64 input.
+ */
+static dfp_test_t
+dfp_dcffix_dcffixq_tests[] = {
+ { &_test_dcffixq,"dcffixq", int64_args_x1, 7, QUAD_TEST, "I64S->D128", True},
+ /* Power 7 instruction */
+ { &_test_dcffix, "dcffix", int64_args_x1, 7, LONG_TEST, "I64S->D64", True},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+static dfp_test_t
+dfp_one_arg_tests[] = {
+ { &_test_dctdp, "dctdp", dfp_1args_x1, 15, LONG_TEST, "D32->D64", True},
+ { &_test_drsp, "drsp", dfp_1args_x1, 15, LONG_TEST, "D64->D32", True},
+ { &_test_dctfix, "dctfix", dfp_1args_x1, 15, LONG_TEST, "D64->I64S", True},
+ { &_test_dctqpq, "dctqpq", dfp_1args_x1, 15, QUAD_TEST, "D64->D128", True},
+ { &_test_dctfixq,"dctfixq", dfp_1args_x1, 15, QUAD_TEST, "D128->I64S", True},
+ { &_test_drdpq, "drdpq", dfp_1args_x1, 15, QUAD_TEST, "D128->D64", True},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+
+static dfp_test_t
+dfp_two_arg_tests[] = {
+ { &_test_dscri, "dscri", dfp_2args_x1, 20, LONG_TEST, ">>", True},
+ { &_test_dscli, "dscli", dfp_2args_x1, 20, LONG_TEST, "<<", True},
+ { &_test_dscriq, "dscriq", dfp_2args_x1, 20, QUAD_TEST, ">>", True},
+ { &_test_dscliq, "dscliq", dfp_2args_x1, 20, QUAD_TEST, "<<", True},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+void set_rounding_mode(unsigned long long rnd_mode)
+{
+ double fpscr;
+ unsigned long long * hex_fpscr = (unsigned long long *)&fpscr;
+
+ *hex_fpscr = 0ULL;
+ __asm__ __volatile__ ("mffs %0" : "=f"(f14));
+ fpscr = f14;
+ *hex_fpscr &= 0xFFFFFFF0FFFFFFFFULL;
+ *hex_fpscr |= (rnd_mode << 32);
+ f14 = fpscr;
+ SET_FPSCR_DRN;
+}
+
+static void test_dfp_one_arg_ops(int unused)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p;
+ double d0x, *d0xp;
+ unsigned long round_mode;
+ int k = 0;
+
+ u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+
+ while ((func = dfp_one_arg_tests[k].test_func)) {
+ int i;
+
+ for (round_mode = 0; round_mode < NUM_RND_MODES; round_mode++) {
+ /* Do each test with each of the possible rounding modes */
+ dfp_test_t test_group = dfp_one_arg_tests[k];
+
+ printf("\ntest with rounding mode %lu \n", round_mode);
+ /* The set_rounding_mode() uses the global value f14. Call the
+ * function before setting up the test for the specific instruction
+ * to avoid avoid conflicts using f14.
+ */
+ set_rounding_mode(round_mode);
+
+ for (i = 0; i < test_group.num_tests; i++) {
+
+ if (test_group.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_group.targs[i].fra_idx];
+ } else {
+ u0 = dfp128_vals[test_group.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_group.targs[i].fra_idx * 2) + 1];
+ }
+
+ *(unsigned long long *)d0p = u0;
+ f14 = d0;
+ if (test_group.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f15 = d0x;
+ }
+
+ (*func)();
+ res = f18;
+
+ printf("%s %016llx", test_group.name, u0);
+
+ if (test_group.precision == LONG_TEST) {
+ printf(" %s => %016llx",
+ test_group.op, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx %s ==> %016llx %016llx",
+ u0x, test_group.op,
+ *((unsigned long long *)(&res)),
+ *((unsigned long long *)(&resx)));
+ }
+ printf("\n");
+ }
+ }
+
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_dfp_two_arg_ops(int unused)
+/* Shift instructions: first argument is the DFP source, second argument
+ * is 6 bit shift amount.
+ */
+{
+ test_func_shift_t func;
+ unsigned long long u0, u0x;
+ unsigned int shift_by;
+ double res, d0, *d0p;
+ double d0x, *d0xp;
+ unsigned long round_mode;
+ int k = 0;
+
+ u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+
+ while ((func = dfp_two_arg_tests[k].test_func)) {
+ int i;
+
+ for (round_mode = 0; round_mode < NUM_RND_MODES; round_mode++) {
+ /* Do each test with each of the possible rounding modes */
+ dfp_test_t test_group = dfp_two_arg_tests[k];
+
+ printf("\ntest with rounding mode %lu \n", round_mode);
+
+ /* The set_rounding_mode() uses the global value f14. Call the
+ * function before setting up the test for the specific instruction
+ * to avoid avoid conflicts using f14.
+ */
+ set_rounding_mode(round_mode);
+
+ for (i = 0; i < test_group.num_tests; i++) {
+
+ shift_by = test_group.targs[i].frb_idx;
+
+ if (test_group.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_group.targs[i].fra_idx];
+ } else {
+ u0 = dfp128_vals[test_group.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_group.targs[i].fra_idx * 2) + 1];
+ }
+
+ *(unsigned long long *)d0p = u0;
+ f14 = d0;
+ if (test_group.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f15 = d0x;
+ }
+
+ (*func)(shift_by);
+ res = f18;
+
+ printf("%s %016llx", test_group.name, u0);
+
+ if (test_group.precision) {
+ printf(" %s %-3d => %016llx",
+ test_group.op, shift_by, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx %s %-3d ==> %016llx %016llx",
+ u0x, test_group.op, shift_by,
+ *((unsigned long long *)(&res)),
+ *((unsigned long long *)(&resx)));
+ }
+ printf("\n" );
+ }
+ }
+
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_dcffix_dcffixq(int has_vsx)
+{
+ test_func_t func;
+ unsigned long long u0;
+ double res, d0, *d0p;
+ int k = 0, round_mode;
+
+ d0p = &d0;
+
+
+ while ((func = dfp_dcffix_dcffixq_tests[k].test_func)) {
+ int i;
+
+ if ((!has_vsx) && (!strcmp("dcffix", dfp_dcffix_dcffixq_tests[k].name))) {
+ k++;
+ /* The test instruction is dcffix it is supported on POWER 7
+ * and newer processors. Skip if not POWER 7 or newer.
+ */
+ continue;
+ }
+
+ for (round_mode = 0; round_mode < NUM_RND_MODES; round_mode++) {
+ /* Do each test with each of the possible rounding modes */
+ dfp_test_t test_group = dfp_dcffix_dcffixq_tests[k];
+
+ printf("\ntest with rounding mode %u \n", round_mode);
+
+ /* The set_rounding_mode() uses the global value f14. Call the
+ * function before setting up the test for the specific instruction
+ * to avoid avoid conflicts using f14.
+ */
+ set_rounding_mode(round_mode);
+
+ for (i = 0; i < test_group.num_tests; i++) {
+
+ /* The instructions take I64 inputs */
+ u0 = int64_vals[test_group.targs[i].fra_idx];
+
+ *(unsigned long long *)d0p = u0;
+ f14 = d0;
+
+ (*func)();
+ res = f18;
+
+ printf("%s %016llx", test_group.name, u0);
+
+ if (test_group.precision) {
+ printf(" %s => %016llx",
+ test_group.op, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %s ==> %016llx %016llx",
+ test_group.op,
+ *((unsigned long long *)(&res)),
+ *((unsigned long long *)(&resx)));
+ }
+ printf("\n" );
+ }
+ }
+
+ k++;
+ printf( "\n" );
+ }
+}
+
+static test_table_t
+all_tests[] =
+{
+ { &test_dfp_one_arg_ops,
+ "Test DFP fomat conversion instructions" },
+ { &test_dfp_two_arg_ops,
+ "Test DFP shift instructions" },
+ { test_dcffix_dcffixq,
+ "Test DCFFIX and DCFFIXQ instructions" },
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main(int argc, char ** argv, char ** envp) {
+#if defined(HAS_DFP)
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0, has_vsx;
+
+ /* If the processor has the VSX functionality then it is POWER 7
+ * or newer.
+ */
+ my_envp = envp;
+ has_vsx = get_vsx();
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)(has_vsx);
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/none/tests/ppc64/test_dfp2.stdout.exp b/none/tests/ppc64/test_dfp2.stdout.exp
deleted file mode 120000
index c4912cb..0000000
--- a/none/tests/ppc64/test_dfp2.stdout.exp
+++ /dev/null
@@ -1 +0,0 @@
-../../../none/tests/ppc32/test_dfp2.stdout.exp
\ No newline at end of file
diff --git a/none/tests/ppc64/test_dfp2.stdout.exp b/none/tests/ppc64/test_dfp2.stdout.exp
new file mode 100644
index 0000000..50c3540
--- /dev/null
+++ b/none/tests/ppc64/test_dfp2.stdout.exp
@@ -0,0 +1,1679 @@
+Test DFP fomat conversion instructions
+
+test with rounding mode 0
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 1
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 2
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 3
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 4
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 5
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 6
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 7
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+
+test with rounding mode 0
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 1
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 2
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fd7c
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 3
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 4
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 5
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 6
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fd7c
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 7
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+
+test with rounding mode 0
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 1
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 2
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 3
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffb
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 4
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 5
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 6
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffb
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 7
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+
+test with rounding mode 0
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 1
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 2
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 3
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 4
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 5
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 6
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 7
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+
+test with rounding mode 0
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 1
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 2
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 3
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffb 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 4
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 5
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 6
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffb 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 7
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+
+test with rounding mode 0
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 1
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 2
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 3
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 4
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 5
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 6
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 7
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+Test DFP shift instructions
+
+test with rounding mode 0
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 1
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 2
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 3
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 4
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 5
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 6
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 7
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+
+test with rounding mode 0
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 1
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 2
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 3
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 4
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 5
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 6
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 7
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+
+test with rounding mode 0
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 1
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 2
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 3
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 4
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 5
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 6
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 7
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+
+test with rounding mode 0
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 1
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 2
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 3
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 4
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 5
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 6
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 7
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+Test DCFFIX and DCFFIXQ instructions
+
+test with rounding mode 0
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 1
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 2
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 3
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 4
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 5
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 6
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 7
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+
+test with rounding mode 0
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 1
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 2
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 3
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 4
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 5
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 6
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
+test with rounding mode 7
+dcffix 0000000000000000 I64S->D64 ==> 2238000000000000 000534b9c1e28e56
+dcffix 0000000000000001 I64S->D64 ==> 2238000000000001 000534b9c1e28e56
+dcffix ffffffffffffffff I64S->D64 ==> a238000000000001 000534b9c1e28e56
+dcffix 002386f26fc0ffff I64S->D64 ==> 6e38ff3fcff3fcff 000534b9c1e28e56
+dcffix ffdc790d903f0001 I64S->D64 ==> ee38ff3fcff3fcff 000534b9c1e28e56
+dcffix 000462d53c8abac0 I64S->D64 ==> 263934b9c1e28e56 000534b9c1e28e56
+dcffix fffb9d2ac3754540 I64S->D64 ==> a63934b9c1e28e56 000534b9c1e28e56
+
diff --git a/none/tests/ppc64/test_dfp2.stdout.exp_Without_dcffix b/none/tests/ppc64/test_dfp2.stdout.exp_Without_dcffix
deleted file mode 120000
index 19bfcb1..0000000
--- a/none/tests/ppc64/test_dfp2.stdout.exp_Without_dcffix
+++ /dev/null
@@ -1 +0,0 @@
-../../../none/tests/ppc32/test_dfp2.stdout.exp_Without_dcffix
\ No newline at end of file
diff --git a/none/tests/ppc64/test_dfp2.stdout.exp_Without_dcffix b/none/tests/ppc64/test_dfp2.stdout.exp_Without_dcffix
new file mode 100644
index 0000000..419a036
--- /dev/null
+++ b/none/tests/ppc64/test_dfp2.stdout.exp_Without_dcffix
@@ -0,0 +1,1606 @@
+Test DFP fomat conversion instructions
+
+test with rounding mode 0
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 1
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 2
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 3
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 4
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 5
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 6
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+test with rounding mode 7
+dctdp 2234000000000e50 D32->D64 => 20a4000000000e50
+dctdp 223400000014c000 D32->D64 => 20a800000004c000
+dctdp a2340000000000e0 D32->D64 => 20a40000000000e0
+dctdp 22240000000000cf D32->D64 => 20a40000000000cf
+dctdp a21400010a395bcf D32->D64 => 2130000000295bcf
+dctdp 6e4d3f1f534acdd4 D32->D64 => 23740000004acdd4
+dctdp 000400000089b000 D32->D64 => 20c400000009b000
+dctdp 2238000000000000 D32->D64 => 20a4000000000000
+dctdp a238000000000000 D32->D64 => 20a4000000000000
+dctdp 4248000000000000 D32->D64 => 20a4000000000000
+dctdp 7e34000000000111 D32->D64 => 20a4000000000111
+dctdp fe000000d0e0a0d0 D32->D64 => a2dc00000040a0d0
+dctdp fc00000000000000 D32->D64 => 20a4000000000000
+dctdp 7800000000000000 D32->D64 => 20a4000000000000
+dctdp f800000000000000 D32->D64 => 20a4000000000000
+
+
+test with rounding mode 0
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 1
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 2
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fd7c
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 3
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 4
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 5
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000000
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 6
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e57
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fd7c
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+test with rounding mode 7
+drsp 2234000000000e50 D64->D32 => 0000000022400e50
+drsp 223400000014c000 D64->D32 => 000000002644c000
+drsp a2340000000000e0 D64->D32 => 00000000a24000e0
+drsp 22240000000000cf D64->D32 => 00000000220000cf
+drsp a21400010a395bcf D64->D32 => 00000000b1f28e56
+drsp 6e4d3f1f534acdd4 D64->D32 => 000000006f34fc7d
+drsp 000400000089b000 D64->D32 => 0000000000000001
+drsp 2238000000000000 D64->D32 => 0000000022500000
+drsp a238000000000000 D64->D32 => 00000000a2500000
+drsp 4248000000000000 D64->D32 => 0000000043f00000
+drsp 7e34000000000111 D64->D32 => 000000007e000111
+drsp fe000000d0e0a0d0 D64->D32 => 00000000fe00a0d0
+drsp fc00000000000000 D64->D32 => 00000000fc000000
+drsp 7800000000000000 D64->D32 => 0000000078000000
+drsp f800000000000000 D64->D32 => 00000000f8000000
+
+
+test with rounding mode 0
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 1
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 2
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 3
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffb
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 4
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 5
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000000
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000000
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 6
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffb
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+test with rounding mode 7
+dctfix 2234000000000e50 D64->I64S => 0000000000000159
+dctfix 223400000014c000 D64->I64S => 000000000001e078
+dctfix a2340000000000e0 D64->I64S => fffffffffffffff0
+dctfix 22240000000000cf D64->I64S => 0000000000000001
+dctfix a21400010a395bcf D64->I64S => fffffffffffffffc
+dctfix 6e4d3f1f534acdd4 D64->I64S => 7fffffffffffffff
+dctfix 000400000089b000 D64->I64S => 0000000000000001
+dctfix 2238000000000000 D64->I64S => 0000000000000000
+dctfix a238000000000000 D64->I64S => 0000000000000000
+dctfix 4248000000000000 D64->I64S => 0000000000000000
+dctfix 7e34000000000111 D64->I64S => 8000000000000000
+dctfix fe000000d0e0a0d0 D64->I64S => 8000000000000000
+dctfix fc00000000000000 D64->I64S => 8000000000000000
+dctfix 7800000000000000 D64->I64S => 7fffffffffffffff
+dctfix f800000000000000 D64->I64S => 8000000000000000
+
+
+test with rounding mode 0
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 1
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 2
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 3
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 4
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 5
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 6
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+test with rounding mode 7
+dctqpq 2207c00000000000 0000000000000e50 D64->D128 ==> 2204c00000000000 0003c00000000000
+dctqpq 2f07c00000000000 000000000014c000 D64->D128 ==> 2214c00000000000 000fc00000000000
+dctqpq a207c00000000000 00000000000000e0 D64->D128 ==> a204c00000000000 0003c00000000000
+dctqpq 2206c00000000000 00000000000000cf D64->D128 ==> 2204c00000000000 0002c00000000000
+dctqpq a205c00000000000 000000010a395bcf D64->D128 ==> a204c00000000000 0001c00000000000
+dctqpq 6209400000fd0000 00253f1f534acdd4 D64->D128 ==> 21c5000000000000 0021400000fd0000
+dctqpq 000400000089b000 0a6000d000000049 D64->D128 ==> 21a4c00000000000 000000000089b000
+dctqpq 2208000000000000 0000000000000000 D64->D128 ==> 2205000000000000 0000000000000000
+dctqpq a208000000000000 0000000000000000 D64->D128 ==> a205000000000000 0000000000000000
+dctqpq a248000000000000 0000000000000000 D64->D128 ==> a209000000000000 0000000000000000
+dctqpq 7c00000000000000 0000000000000000 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq fc00000000000000 c00100035b007700 D64->D128 ==> fc00000000000000 0000000000000000
+dctqpq 7e00000000000000 fe000000d0e0a0d0 D64->D128 ==> 7c00000000000000 0000000000000000
+dctqpq 7800000000000000 0000000000000000 D64->D128 ==> 7800000000000000 0000000000000000
+dctqpq f800000000000000 0000000000000000 D64->D128 ==> f800000000000000 0000000000000000
+
+
+test with rounding mode 0
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 1
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 2
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 3
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffb 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 4
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 5
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 6
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffb 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+test with rounding mode 7
+dctfixq 2207c00000000000 0000000000000e50 D128->I64S ==> 0000000000000159 0000000000000000
+dctfixq 2f07c00000000000 000000000014c000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq a207c00000000000 00000000000000e0 D128->I64S ==> fffffffffffffff0 0000000000000000
+dctfixq 2206c00000000000 00000000000000cf D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq a205c00000000000 000000010a395bcf D128->I64S ==> fffffffffffffffc 0000000000000000
+dctfixq 6209400000fd0000 00253f1f534acdd4 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 000400000089b000 0a6000d000000049 D128->I64S ==> 0000000000000001 0000000000000000
+dctfixq 2208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a208000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq a248000000000000 0000000000000000 D128->I64S ==> 0000000000000000 0000000000000000
+dctfixq 7c00000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq fc00000000000000 c00100035b007700 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7e00000000000000 fe000000d0e0a0d0 D128->I64S ==> 8000000000000000 0000000000000000
+dctfixq 7800000000000000 0000000000000000 D128->I64S ==> 7fffffffffffffff 0000000000000000
+dctfixq f800000000000000 0000000000000000 D128->I64S ==> 8000000000000000 0000000000000000
+
+
+test with rounding mode 0
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 1
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 2
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 3
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 4
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 5
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000000 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 6
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+test with rounding mode 7
+drdpq 2207c00000000000 0000000000000e50 D128->D64 ==> 2234000000000e50 0000000000000000
+drdpq 2f07c00000000000 000000000014c000 D128->D64 ==> 77fcff3fcff3fcff 0000000000000000
+drdpq a207c00000000000 00000000000000e0 D128->D64 ==> a2340000000000e0 0000000000000000
+drdpq 2206c00000000000 00000000000000cf D128->D64 ==> 22240000000000cf 0000000000000000
+drdpq a205c00000000000 000000010a395bcf D128->D64 ==> a21400010a395bcf 0000000000000000
+drdpq 6209400000fd0000 00253f1f534acdd4 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 000400000089b000 0a6000d000000049 D128->D64 ==> 0000000000000001 0000000000000000
+drdpq 2208000000000000 0000000000000000 D128->D64 ==> 2238000000000000 0000000000000000
+drdpq a208000000000000 0000000000000000 D128->D64 ==> a238000000000000 0000000000000000
+drdpq a248000000000000 0000000000000000 D128->D64 ==> c238000000000000 0000000000000000
+drdpq 7c00000000000000 0000000000000000 D128->D64 ==> 7c00000000000000 0000000000000000
+drdpq fc00000000000000 c00100035b007700 D128->D64 ==> fc0100035b007700 0000000000000000
+drdpq 7e00000000000000 fe000000d0e0a0d0 D128->D64 ==> 7c000000d0e0a0d0 0000000000000000
+drdpq 7800000000000000 0000000000000000 D128->D64 ==> 7800000000000000 0000000000000000
+drdpq f800000000000000 0000000000000000 D128->D64 ==> f800000000000000 0000000000000000
+
+Test DFP shift instructions
+
+test with rounding mode 0
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 1
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 2
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 3
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 4
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 5
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 6
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 7
+dscri 2234000000000e50 0000000000000000 >> 0 ==> 2234000000000e50 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 1 ==> 22340000000001c5 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 15 ==> 2234000000000000 0000000000000000
+dscri 2234000000000e50 0000000000000000 >> 63 ==> 2234000000000000 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 1 ==> 224d8fe3ca394db5 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 15 ==> 224c000000000009 0000000000000000
+dscri 6e4d3f1f534acdd4 0000000000000000 >> 63 ==> 224c000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 0 ==> 000400000089b000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 1 ==> 00040000000c3a00 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 15 ==> 0004000000000000 0000000000000000
+dscri 000400000089b000 0000000000000000 >> 63 ==> 0004000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 0 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 1 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 15 ==> 2238000000000000 0000000000000000
+dscri 2238000000000000 0000000000000000 >> 63 ==> 2238000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 0 ==> 7e00000000000111 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 1 ==> 7e00000000000021 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 15 ==> 7e00000000000000 0000000000000000
+dscri 7e34000000000111 0000000000000000 >> 63 ==> 7e00000000000000 0000000000000000
+
+
+test with rounding mode 0
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 1
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 2
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 3
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 4
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 5
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 6
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+test with rounding mode 7
+dscli 2234000000000e50 0000000000000000 << 0 ==> 2234000000000e50 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 1 ==> 223400000000d280 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 15 ==> 2234000000000000 0000000000000000
+dscli 2234000000000e50 0000000000000000 << 63 ==> 2234000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 0 ==> 6e4d3f1f534acdd4 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 1 ==> 6a4ddee49c56cec0 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 15 ==> 324c000000000000 0000000000000000
+dscli 6e4d3f1f534acdd4 0000000000000000 << 63 ==> 224c000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 0 ==> 000400000089b000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 1 ==> 0004000004ed0000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 15 ==> 0004000000000000 0000000000000000
+dscli 000400000089b000 0000000000000000 << 63 ==> 0004000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 0 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 1 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 15 ==> 2238000000000000 0000000000000000
+dscli 2238000000000000 0000000000000000 << 63 ==> 2238000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 0 ==> 7e00000000000111 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 1 ==> 7e00000000000890 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 15 ==> 7e00000000000000 0000000000000000
+dscli 7e34000000000111 0000000000000000 << 63 ==> 7e00000000000000 0000000000000000
+
+
+test with rounding mode 0
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 1
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 2
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 3
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 4
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 5
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 6
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+test with rounding mode 7
+dscriq 2207c00000000000 >> 0 => 2207c00000000000
+dscriq 2207c00000000000 >> 1 => 2207c00000000000
+dscriq 2207c00000000000 >> 15 => 2207c00000000000
+dscriq 2207c00000000000 >> 63 => 2207c00000000000
+dscriq 6209400000fd0000 >> 0 => 6209400000fd0000
+dscriq 6209400000fd0000 >> 1 => 020940c0007b2000
+dscriq 6209400000fd0000 >> 15 => 0209400000000000
+dscriq 6209400000fd0000 >> 63 => 0209400000000000
+dscriq 000400000089b000 >> 0 => 000400000089b000
+dscriq 000400000089b000 >> 1 => 000400000010b700
+dscriq 000400000089b000 >> 15 => 0004000000000000
+dscriq 000400000089b000 >> 63 => 0004000000000000
+dscriq 2208000000000000 >> 0 => 2208000000000000
+dscriq 2208000000000000 >> 1 => 2208000000000000
+dscriq 2208000000000000 >> 15 => 2208000000000000
+dscriq 2208000000000000 >> 63 => 2208000000000000
+dscriq 7c00000000000000 >> 0 => 7c00000000000000
+dscriq 7c00000000000000 >> 1 => 7c00000000000000
+dscriq 7c00000000000000 >> 15 => 7c00000000000000
+dscriq 7c00000000000000 >> 63 => 7c00000000000000
+
+
+test with rounding mode 0
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 1
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 2
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 3
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 4
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 5
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 6
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+test with rounding mode 7
+dscliq 2207c00000000000 << 0 => 2207c00000000000
+dscliq 2207c00000000000 << 1 => 2207c00000000000
+dscliq 2207c00000000000 << 15 => 2207c00000000000
+dscliq 2207c00000000000 << 63 => 2207c00000000000
+dscliq 6209400000fd0000 << 0 => 6209400000fd0000
+dscliq 6209400000fd0000 << 1 => 0209400027900000
+dscliq 6209400000fd0000 << 15 => 02094094fc7d4d2b
+dscliq 6209400000fd0000 << 63 => 0209400000000000
+dscliq 000400000089b000 << 0 => 000400000089b000
+dscliq 000400000089b000 << 1 => 00040000045b8000
+dscliq 000400000089b000 << 15 => 0004298003400000
+dscliq 000400000089b000 << 63 => 0004000000000000
+dscliq 2208000000000000 << 0 => 2208000000000000
+dscliq 2208000000000000 << 1 => 2208000000000000
+dscliq 2208000000000000 << 15 => 2208000000000000
+dscliq 2208000000000000 << 63 => 2208000000000000
+dscliq 7c00000000000000 << 0 => 7c00000000000000
+dscliq 7c00000000000000 << 1 => 7c00000000000000
+dscliq 7c00000000000000 << 15 => 7c00000000000000
+dscliq 7c00000000000000 << 63 => 7c00000000000000
+
+Test DCFFIX and DCFFIXQ instructions
+
+test with rounding mode 0
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 1
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 2
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 3
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 4
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 5
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 6
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
+test with rounding mode 7
+dcffixq 0000000000000000 I64S->D128 => 2208000000000000
+dcffixq 0000000000000001 I64S->D128 => 2208000000000000
+dcffixq ffffffffffffffff I64S->D128 => a208000000000000
+dcffixq 002386f26fc0ffff I64S->D128 => 2208000000000000
+dcffixq ffdc790d903f0001 I64S->D128 => a208000000000000
+dcffixq 000462d53c8abac0 I64S->D128 => 2208000000000000
+dcffixq fffb9d2ac3754540 I64S->D128 => a208000000000000
+
diff --git a/none/tests/ppc64/test_dfp3.c b/none/tests/ppc64/test_dfp3.c
deleted file mode 120000
index a1404ce..0000000
--- a/none/tests/ppc64/test_dfp3.c
+++ /dev/null
@@ -1 +0,0 @@
-../../../none/tests/ppc32/test_dfp3.c
\ No newline at end of file
diff --git a/none/tests/ppc64/test_dfp3.c b/none/tests/ppc64/test_dfp3.c
new file mode 100644
index 0000000..4fe3137
--- /dev/null
+++ b/none/tests/ppc64/test_dfp3.c
@@ -0,0 +1,1263 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+
+#if defined(HAS_DFP)
+
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+register double f18 __asm__ ("fr18");
+register double f19 __asm__ ("fr19");
+
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+
+// The assembly-level instructions being tested
+static void _test_drintx(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintx 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintx 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drintn(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintn 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintn 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+
+static void _test_diex(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("diex %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dxex(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("dxex %0, %1" : "=f" (f18) : "f" (f16));
+}
+
+static void _test_dcmpo(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpo 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpo 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpo 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpo 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpo 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpo 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpo 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpo 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dcmpu(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpu 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpu 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpu 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpu 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpu 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpu 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpu 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpu 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+// Quad instruction testing
+static void _test_drintxq(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintxq 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintxq 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drintnq(int R, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || R < 0 || R > 1) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", R, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 1:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 2:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 3:
+ if (R)
+ __asm__ __volatile__ ("drintnq 1, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ else
+ __asm__ __volatile__ ("drintnq 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_diexq(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("diexq %0, %1, %2" : "=f" (f18) : "f" (f14),"f" (f16));
+}
+
+static void _test_dxexq(int a __attribute__((unused)), int b __attribute__((unused)))
+{
+ __asm__ __volatile__ ("dxexq %0, %1" : "=f" (f18) : "f" (f16));
+}
+
+static void _test_dcmpoq(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF );
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpoq 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpoq 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpoq 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpoq 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpoq 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpoq 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpoq 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpoq 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dcmpuq(int BF, int x __attribute__((unused)))
+{
+ if (BF < 0 || BF > 7) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 0:
+ __asm__ __volatile__ ("dcmpuq 0, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dcmpuq 1, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dcmpuq 2, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dcmpuq 3, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 4:
+ __asm__ __volatile__ ("dcmpuq 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dcmpuq 5, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 6:
+ __asm__ __volatile__ ("dcmpuq 6, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dcmpuq 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drrnd(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 31) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("drrnd %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_drrndq(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 3) {
+ fprintf(stderr, "Invalid input to asm test: a=%dn", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("drrndq %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dqua(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 3) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dqua %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dquaq(int x __attribute__((unused)), int RMC)
+{
+ if (RMC < 0 || RMC > 3) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 0" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 1" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 2" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("dquaq %0, %1, %2, 3" : "=f" (f18) : "f" (f14), "f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static int TE_vals[] = { -16, -2, 0, 5};
+#define TE_VAL_LEN sizeof(TE_vals)/sizeof(int)
+static Bool __is_TE_val(int x)
+{
+ int i;
+ for (i = 0; i < TE_VAL_LEN; i++) {
+ if (x==TE_vals[i])
+ return True;
+ }
+ return False;
+}
+
+static void _test_dquai(int TE, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || !__is_TE_val(TE)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", TE, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 1:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 2:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 3:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquai -16, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquai -2, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquai 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquai 5, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dquaiq(int TE, int RMC)
+{
+ if (RMC < 0 || RMC > 3 || !__is_TE_val(TE)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", TE, RMC);
+ return;
+ }
+ switch (RMC) {
+ case 0:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 0" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 1:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 1" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 2:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 2" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ case 3:
+ switch (TE) {
+ case -16:
+ __asm__ __volatile__ ("dquaiq -16, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case -2:
+ __asm__ __volatile__ ("dquaiq -2, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 0:
+ __asm__ __volatile__ ("dquaiq 0, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ case 5:
+ __asm__ __volatile__ ("dquaiq 5, %0, %1, 3" : "=f" (f18) : "f" (f16));
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+
+typedef void (*test_func_t)(int a, int b);
+typedef void (*test_driver_func_t)(void);
+typedef struct test_table
+{
+ test_driver_func_t test_category;
+ char * name;
+} test_table_t;
+
+/*
+ * 345.0DD (0x2207c00000000000 0xe50)
+ * 1.2300e+5DD (0x2207c00000000000 0x14c000)
+ * -16.0DD (0xa207c00000000000 0xe0)
+ * 0.00189DD (0x2206c00000000000 0xcf)
+ * -4.1235DD (0xa205c00000000000 0x10a395bcf)
+ * 9.8399e+20DD (0x2209400000000000 0x253f1f534acdd4)
+ * 0DD (0x2208000000000000 0x0)
+ * 0DD (0x2208000000000000 0x0)
+ * infDD (0x7800000000000000 0x0)
+ * nanDD (0x7c00000000000000 0x0
+ */
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2207c00000000000ULL, 0x000000000014c000ULL,
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // huge number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// huge number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+// Both Long and Quad arrays of DFP values should have the same length.
+// If that length is changed, t
+#define NUM_DFP_VALS (sizeof(dfp64_vals)/8)
+
+typedef struct dfp_test_args {
+ int fra_idx;
+ int frb_idx;
+} dfp_test_args_t;
+
+
+// Index pairs from dfp64_vals array to be used with dfp_two_arg_tests
+static dfp_test_args_t dfp_2args_x1[] = {
+ {0, 1},
+ {2, 1},
+ {3, 4},
+ {0, 6},
+ {2, 4},
+ {5, 1},
+ {5, 2},
+ {7, 1},
+ {7, 2},
+ {8, 0},
+ {8, 1},
+ {8, 2},
+ {7, 8},
+ {12, 14},
+ {12, 1},
+ {12, 13},
+ {12, 12},
+ {12, 11},
+ {11, 14},
+ {11, 0},
+ {11, 13},
+ {11, 11},
+ {14, 14},
+ {14, 3},
+ {14, 15},
+};
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_test
+{
+ test_func_t test_func;
+ const char * name;
+ dfp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ const char * op;
+} dfp_test_t;
+
+typedef struct dfp_one_arg_test
+{
+ test_func_t test_func;
+ const char * name;
+ precision_type_t precision;
+ const char * op;
+} dfp_one_arg_test_t;
+
+
+static dfp_one_arg_test_t
+dfp_quai_tests[] = {
+ { &_test_dquai, "dquai", LONG_TEST, "[QI]"},
+ { &_test_dquaiq, "dquaiq", QUAD_TEST, "[QI]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_quai_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp;
+
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+
+ while ((func = dfp_quai_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_test_t test_def = dfp_quai_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int TE, RMC;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[i];
+ } else {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ for (TE = 0; TE < TE_VAL_LEN; TE++) {
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(TE_vals[TE], RMC);
+ res = f18;
+ printf("%s (RMC=%2d, TE=%3d) %s %016llx", test_def.name, RMC,
+ TE_vals[TE], test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" => %016llx\n",
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx ==> %016llx %016llx\n",
+ u0x, *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_test_t
+dfp_qua_tests[] = {
+ { &_test_dqua, "dqua", dfp_2args_x1, 25, LONG_TEST, "[Q]"},
+ { &_test_dquaq, "dquaq", dfp_2args_x1, 25, QUAD_TEST, "[Q]"},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+static void test_dfp_qua_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x, u1, u1x;
+ double res, d0, d1, *d0p, *d1p;
+ double d0x, d1x, *d0xp, *d1xp;
+ int k = 0;
+ u0x = u1x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ d1p = &d1;
+ d1xp = &d1x;
+
+ while ((func = dfp_qua_tests[k].test_func)) {
+ int i, RMC;
+ dfp_test_t test_def = dfp_qua_tests[k];
+
+ for (i = 0; i < test_def.num_tests; i++) {
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_def.targs[i].fra_idx];
+ u1 = dfp64_vals[test_def.targs[i].frb_idx];
+ } else {
+ u0 = dfp128_vals[test_def.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
+ u1 = dfp128_vals[test_def.targs[i].frb_idx * 2];
+ u1x = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ *(unsigned long long *)d1p = u1;
+ f14 = d0;
+ f16 = d1;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ *(unsigned long long *)d1xp = u1x;
+ f15 = d0x;
+ f17 = d1x;
+ }
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(-1, RMC);
+ res = f18;
+ printf("%s (RMC=%2d) %s %016llx", test_def.name, RMC, test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(", %016llx => %016llx\n", u1, *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx, %016llx %016llx ==> %016llx %016llx\n",u0x, u1, u1x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_one_arg_test_t
+dfp_rrnd_tests[] = {
+ { &_test_drrnd, "drrnd", LONG_TEST, "[RR]"},
+ { &_test_drrndq, "drrndq", QUAD_TEST, "[RR]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_rrnd_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp, reference_sig, *reference_sig_p;
+ long long reference_sig_vals[] = {0ULL, 2ULL, 6ULL, 63ULL};
+ int num_reference_sig_vals = sizeof(reference_sig_vals)/sizeof(long long);
+
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ reference_sig_p = &reference_sig;
+
+ while ((func = dfp_rrnd_tests[k].test_func)) {
+ int i, j;
+ dfp_one_arg_test_t test_def = dfp_rrnd_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int RMC;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[i];
+ } else {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ for (j = 0; j < num_reference_sig_vals; j++) {
+ *(long long *)reference_sig_p = reference_sig_vals[j];
+ f14 = reference_sig;
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(-1, RMC);
+ res = f18;
+ printf("%s (RMC=%d, ref sig=%d) %s%016llx", test_def.name, RMC,
+ (int)reference_sig_vals[j], test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" => %016llx\n",
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx ==> %016llx %016llx\n",
+ u0x, *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_one_arg_test_t
+dfp_xiex_tests[] = {
+ { &_test_diex, "diex", LONG_TEST, ">>"},
+ { &_test_diexq, "diexq", QUAD_TEST, ">>"},
+ { &_test_dxex, "dxex", LONG_TEST, "<<"},
+ { &_test_dxexq, "dxexq", QUAD_TEST, "<<"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_xiex_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp, target_exp, *target_exp_p;
+ /* The first two positions are placeholders and will be filled in later,
+ * based on the precision of the DFP argument.
+ */
+ long long target_exp_vals[] = {0ULL, 0ULL, 0ULL, -1ULL, -2ULL, -3ULL, -4ULL, -5ULL};
+ int num_exp_vals = sizeof(target_exp_vals)/sizeof(long long);
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ target_exp_p = &target_exp;
+
+ while ((func = dfp_xiex_tests[k].test_func)) {
+ int i;
+ Bool insert_insn = False;
+ dfp_one_arg_test_t test_def = dfp_xiex_tests[k];
+
+ if (!strncmp(test_def.name, "di", 2))
+ insert_insn = True;
+
+ if (test_def.precision == QUAD_TEST) {
+ target_exp_vals[0] = 12288ULL; // > max biased exponent
+ target_exp_vals[1] = 5235ULL;
+ } else {
+ target_exp_vals[0] = 768ULL; // > max biased exponent
+ target_exp_vals[1] = 355ULL;
+ }
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ unsigned int j;
+
+ if (test_def.precision == QUAD_TEST) {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ } else {
+ u0 = dfp64_vals[i];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ if (!insert_insn) {
+ // This is just for extract insns (dexex[q])
+ (*func)(0, 0);
+ res = f18;
+ printf("%s %s ", test_def.name, test_def.op);
+ if (test_def.precision == LONG_TEST) {
+ printf("%016llx => %016llx\n", u0,
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf("%016llx %016llx ==> %016llx %016llx\n", u0, u0x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ continue;
+ }
+ // The following for-loop is just for insert insns (diex[q])
+ for (j = 0; j < num_exp_vals; j++) {
+ *(long long *)target_exp_p = target_exp_vals[j];
+ f14 = target_exp;
+ (*func)(0, 0);
+ res = f18;
+ printf("%s %s %5d, ", test_def.name, test_def.op, (int)target_exp_vals[j]);
+
+ if (test_def.precision == LONG_TEST) {
+ printf("%016llx => %016llx\n", u0,
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf("%016llx %016llx ==> %016llx %016llx\n", u0, u0x,
+ *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static dfp_one_arg_test_t
+dfp_rint_tests[] = {
+ { &_test_drintn, "drintn", LONG_TEST, "~"},
+ { &_test_drintnq, "drintnq", QUAD_TEST, "~"},
+ { &_test_drintx, "drintx", LONG_TEST, "~"},
+ { &_test_drintxq, "drintxq", QUAD_TEST, "~"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_rint_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x;
+ double res, d0, *d0p, d0x, *d0xp;
+ int k = 0;
+ u0 = u0x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+
+ while ((func = dfp_rint_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_test_t test_def = dfp_rint_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int R, RMC;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[i];
+ } else {
+ u0 = dfp128_vals[i * 2];
+ u0x = dfp128_vals[(i * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ f16 = d0;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ f17 = d0x;
+ }
+
+ for (R = 0; R < 2; R++) {
+ for (RMC = 0; RMC < 4; RMC++) {
+ (*func)(R, RMC);
+ res = f18;
+ printf("%s (RM=%d) %s%016llx", test_def.name, (RMC + (R << 2)), test_def.op, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" => %016llx\n",
+ *((unsigned long long *)(&res)));
+ } else {
+ double resx = f19;
+ printf(" %016llx ==> %016llx %016llx\n",
+ u0x, *((unsigned long long *)(&res)), *((unsigned long long *)(&resx)));
+ }
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static dfp_test_t
+dfp_cmp_tests[] = {
+ { &_test_dcmpo, "dcmpo", dfp_2args_x1, 25, LONG_TEST, "<>"},
+ { &_test_dcmpoq, "dcmpoq", dfp_2args_x1, 25, QUAD_TEST, "<>"},
+ { &_test_dcmpu, "dcmpu", dfp_2args_x1, 25, LONG_TEST, "<>"},
+ { &_test_dcmpuq, "dcmpuq", dfp_2args_x1, 25, QUAD_TEST, "<>"},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+static void test_dfp_cmp_ops(void)
+{
+ test_func_t func;
+ unsigned long long u0, u0x, u1, u1x;
+ double d0, d1, *d0p, *d1p;
+ double d0x, d1x, *d0xp, *d1xp;
+ /* BF is a 3-bit instruction field that indicates the CR field in which the
+ * result of the compare should be placed. We won't iterate through all
+ * 8 possible BF values since storing compare results to a given field is
+ * a well-tested mechanism in VEX. But we will test two BF values, just as
+ * a sniff-test.
+ */
+ int k = 0, BF;
+ u0x = u1x = 0;
+ d0p = &d0;
+ d0xp = &d0x;
+ d1p = &d1;
+ d1xp = &d1x;
+
+ while ((func = dfp_cmp_tests[k].test_func)) {
+ int i, repeat = 1;
+ dfp_test_t test_def = dfp_cmp_tests[k];
+ BF = 0;
+
+again:
+ for (i = 0; i < test_def.num_tests; i++) {
+ unsigned int condreg;
+ unsigned int flags;
+
+ if (test_def.precision == LONG_TEST) {
+ u0 = dfp64_vals[test_def.targs[i].fra_idx];
+ u1 = dfp64_vals[test_def.targs[i].frb_idx];
+ } else {
+ u0 = dfp128_vals[test_def.targs[i].fra_idx * 2];
+ u0x = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
+ u1 = dfp128_vals[test_def.targs[i].frb_idx * 2];
+ u1x = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
+ }
+ *(unsigned long long *)d0p = u0;
+ *(unsigned long long *)d1p = u1;
+ f14 = d0;
+ f16 = d1;
+ if (test_def.precision == QUAD_TEST) {
+ *(unsigned long long *)d0xp = u0x;
+ *(unsigned long long *)d1xp = u1x;
+ f15 = d0x;
+ f17 = d1x;
+ }
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)(BF, 0);
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+ printf("%s %016llx", test_def.name, u0);
+ if (test_def.precision == LONG_TEST) {
+ printf(" %s %016llx => %x (BF=%d)\n",
+ test_def.op, u1, condreg, BF);
+ } else {
+ printf(" %016llx %s %016llx %016llx ==> %x (BF=%d)\n",
+ u0x, test_def.op, u1, u1x,
+ condreg, BF);
+ }
+ }
+ if (repeat) {
+ repeat = 0;
+ BF = 5;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_dfp_cmp_ops,
+ "Test DFP compare instructions"},
+ { &test_dfp_rint_ops,
+ "Test DFP round instructions"},
+ { &test_dfp_xiex_ops,
+ "Test DFP insert/extract instructions"},
+ { &test_dfp_rrnd_ops,
+ "Test DFP reround instructions"},
+ { &test_dfp_qua_ops,
+ "Test DFP quantize instructions"},
+ { &test_dfp_quai_ops,
+ "Test DFP quantize immediate instructions"},
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main() {
+#if defined(HAS_DFP)
+
+ test_table_t aTest;
+ test_driver_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/none/tests/ppc64/test_dfp3.stdout.exp b/none/tests/ppc64/test_dfp3.stdout.exp
deleted file mode 120000
index 9d8c3c6..0000000
--- a/none/tests/ppc64/test_dfp3.stdout.exp
+++ /dev/null
@@ -1 +0,0 @@
-../../../none/tests/ppc32/test_dfp3.stdout.exp
\ No newline at end of file
diff --git a/none/tests/ppc64/test_dfp3.stdout.exp b/none/tests/ppc64/test_dfp3.stdout.exp
new file mode 100644
index 0000000..5c21dc0
--- /dev/null
+++ b/none/tests/ppc64/test_dfp3.stdout.exp
@@ -0,0 +1,2248 @@
+Test DFP compare instructions
+dcmpo 2234000000000e50 <> 223400000014c000 => 8 (BF=0)
+dcmpo a2340000000000e0 <> 223400000014c000 => 8 (BF=0)
+dcmpo 22240000000000cf <> a21400010a395bcf => 4 (BF=0)
+dcmpo 2234000000000e50 <> 000400000089b000 => 4 (BF=0)
+dcmpo a2340000000000e0 <> a21400010a395bcf => 8 (BF=0)
+dcmpo 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=0)
+dcmpo 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=0)
+dcmpo 2238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpo 2238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpo a238000000000000 <> 2234000000000e50 => 8 (BF=0)
+dcmpo a238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpo a238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpo 2238000000000000 <> a238000000000000 => 2 (BF=0)
+dcmpo fc00000000000000 <> f800000000000000 => 1 (BF=0)
+dcmpo fc00000000000000 <> 223400000014c000 => 1 (BF=0)
+dcmpo fc00000000000000 <> 7800000000000000 => 1 (BF=0)
+dcmpo fc00000000000000 <> fc00000000000000 => 1 (BF=0)
+dcmpo fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=0)
+dcmpo fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpo f800000000000000 <> f800000000000000 => 2 (BF=0)
+dcmpo f800000000000000 <> 22240000000000cf => 8 (BF=0)
+dcmpo f800000000000000 <> 7a34000000000000 => 8 (BF=0)
+dcmpo 2234000000000e50 <> 223400000014c000 => 8 (BF=5)
+dcmpo a2340000000000e0 <> 223400000014c000 => 8 (BF=5)
+dcmpo 22240000000000cf <> a21400010a395bcf => 4 (BF=5)
+dcmpo 2234000000000e50 <> 000400000089b000 => 4 (BF=5)
+dcmpo a2340000000000e0 <> a21400010a395bcf => 8 (BF=5)
+dcmpo 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=5)
+dcmpo 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=5)
+dcmpo 2238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpo 2238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpo a238000000000000 <> 2234000000000e50 => 8 (BF=5)
+dcmpo a238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpo a238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpo 2238000000000000 <> a238000000000000 => 2 (BF=5)
+dcmpo fc00000000000000 <> f800000000000000 => 1 (BF=5)
+dcmpo fc00000000000000 <> 223400000014c000 => 1 (BF=5)
+dcmpo fc00000000000000 <> 7800000000000000 => 1 (BF=5)
+dcmpo fc00000000000000 <> fc00000000000000 => 1 (BF=5)
+dcmpo fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=5)
+dcmpo fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpo f800000000000000 <> f800000000000000 => 2 (BF=5)
+dcmpo f800000000000000 <> 22240000000000cf => 8 (BF=5)
+dcmpo f800000000000000 <> 7a34000000000000 => 8 (BF=5)
+
+dcmpoq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=0)
+dcmpoq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=0)
+dcmpoq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=0)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpoq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=0)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpoq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpoq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=0)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpoq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpoq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpoq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=0)
+dcmpoq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpoq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=5)
+dcmpoq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=5)
+dcmpoq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=5)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpoq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=5)
+dcmpoq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpoq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpoq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=5)
+dcmpoq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpoq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpoq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpoq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=5)
+dcmpoq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=5)
+
+dcmpu 2234000000000e50 <> 223400000014c000 => 8 (BF=0)
+dcmpu a2340000000000e0 <> 223400000014c000 => 8 (BF=0)
+dcmpu 22240000000000cf <> a21400010a395bcf => 4 (BF=0)
+dcmpu 2234000000000e50 <> 000400000089b000 => 4 (BF=0)
+dcmpu a2340000000000e0 <> a21400010a395bcf => 8 (BF=0)
+dcmpu 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=0)
+dcmpu 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=0)
+dcmpu 2238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpu 2238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpu a238000000000000 <> 2234000000000e50 => 8 (BF=0)
+dcmpu a238000000000000 <> 223400000014c000 => 8 (BF=0)
+dcmpu a238000000000000 <> a2340000000000e0 => 4 (BF=0)
+dcmpu 2238000000000000 <> a238000000000000 => 2 (BF=0)
+dcmpu fc00000000000000 <> f800000000000000 => 1 (BF=0)
+dcmpu fc00000000000000 <> 223400000014c000 => 1 (BF=0)
+dcmpu fc00000000000000 <> 7800000000000000 => 1 (BF=0)
+dcmpu fc00000000000000 <> fc00000000000000 => 1 (BF=0)
+dcmpu fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=0)
+dcmpu fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=0)
+dcmpu f800000000000000 <> f800000000000000 => 2 (BF=0)
+dcmpu f800000000000000 <> 22240000000000cf => 8 (BF=0)
+dcmpu f800000000000000 <> 7a34000000000000 => 8 (BF=0)
+dcmpu 2234000000000e50 <> 223400000014c000 => 8 (BF=5)
+dcmpu a2340000000000e0 <> 223400000014c000 => 8 (BF=5)
+dcmpu 22240000000000cf <> a21400010a395bcf => 4 (BF=5)
+dcmpu 2234000000000e50 <> 000400000089b000 => 4 (BF=5)
+dcmpu a2340000000000e0 <> a21400010a395bcf => 8 (BF=5)
+dcmpu 6e4d3f1f534acdd4 <> 223400000014c000 => 4 (BF=5)
+dcmpu 6e4d3f1f534acdd4 <> a2340000000000e0 => 4 (BF=5)
+dcmpu 2238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpu 2238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpu a238000000000000 <> 2234000000000e50 => 8 (BF=5)
+dcmpu a238000000000000 <> 223400000014c000 => 8 (BF=5)
+dcmpu a238000000000000 <> a2340000000000e0 => 4 (BF=5)
+dcmpu 2238000000000000 <> a238000000000000 => 2 (BF=5)
+dcmpu fc00000000000000 <> f800000000000000 => 1 (BF=5)
+dcmpu fc00000000000000 <> 223400000014c000 => 1 (BF=5)
+dcmpu fc00000000000000 <> 7800000000000000 => 1 (BF=5)
+dcmpu fc00000000000000 <> fc00000000000000 => 1 (BF=5)
+dcmpu fc00000000000000 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> f800000000000000 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> 2234000000000e50 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> 7800000000000000 => 1 (BF=5)
+dcmpu fe000000d0e0a0d0 <> fe000000d0e0a0d0 => 1 (BF=5)
+dcmpu f800000000000000 <> f800000000000000 => 2 (BF=5)
+dcmpu f800000000000000 <> 22240000000000cf => 8 (BF=5)
+dcmpu f800000000000000 <> 7a34000000000000 => 8 (BF=5)
+
+dcmpuq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=0)
+dcmpuq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=0)
+dcmpuq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=0)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpuq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=0)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=0)
+dcmpuq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=0)
+dcmpuq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=0)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=0)
+dcmpuq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=0)
+dcmpuq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpuq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=0)
+dcmpuq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=0)
+dcmpuq 2207c00000000000 0000000000000e50 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq a207c00000000000 00000000000000e0 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq 2206c00000000000 00000000000000cf <> a205c00000000000 000000010a395bcf ==> 4 (BF=5)
+dcmpuq 2207c00000000000 0000000000000e50 <> 000400000089b000 0a6000d000000049 ==> 4 (BF=5)
+dcmpuq a207c00000000000 00000000000000e0 <> a205c00000000000 000000010a395bcf ==> 8 (BF=5)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq 6209400000fd0000 00253f1f534acdd4 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpuq 2208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq 2208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 0000000000000e50 ==> 8 (BF=5)
+dcmpuq a208000000000000 0000000000000000 <> 2207c00000000000 000000000014c000 ==> 8 (BF=5)
+dcmpuq a208000000000000 0000000000000000 <> a207c00000000000 00000000000000e0 ==> 4 (BF=5)
+dcmpuq 2208000000000000 0000000000000000 <> a208000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 2207c00000000000 000000000014c000 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> 7e00000000000000 fe000000d0e0a0d0 ==> 1 (BF=5)
+dcmpuq 7e00000000000000 fe000000d0e0a0d0 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> f800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> 2207c00000000000 0000000000000e50 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> 7800000000000000 0000000000000000 ==> 1 (BF=5)
+dcmpuq fc00000000000000 c00100035b007700 <> fc00000000000000 c00100035b007700 ==> 1 (BF=5)
+dcmpuq f800000000000000 0000000000000000 <> f800000000000000 0000000000000000 ==> 2 (BF=5)
+dcmpuq f800000000000000 0000000000000000 <> 2206c00000000000 00000000000000cf ==> 8 (BF=5)
+dcmpuq f800000000000000 0000000000000000 <> f900000000000000 0000000000000000 ==> 2 (BF=5)
+
+Test DFP round instructions
+drintn (RM=0) ~2234000000000e50 => 22380000000001c5
+drintn (RM=1) ~2234000000000e50 => 22380000000001c5
+drintn (RM=2) ~2234000000000e50 => 22380000000001c5
+drintn (RM=3) ~2234000000000e50 => 22380000000001c5
+drintn (RM=4) ~2234000000000e50 => 22380000000001c5
+drintn (RM=5) ~2234000000000e50 => 22380000000001c5
+drintn (RM=6) ~2234000000000e50 => 22380000000001c5
+drintn (RM=7) ~2234000000000e50 => 22380000000001c5
+drintn (RM=0) ~223400000014c000 => 2238000000028c00
+drintn (RM=1) ~223400000014c000 => 2238000000028c00
+drintn (RM=2) ~223400000014c000 => 2238000000028c00
+drintn (RM=3) ~223400000014c000 => 2238000000028c00
+drintn (RM=4) ~223400000014c000 => 2238000000028c00
+drintn (RM=5) ~223400000014c000 => 2238000000028c00
+drintn (RM=6) ~223400000014c000 => 2238000000028c00
+drintn (RM=7) ~223400000014c000 => 2238000000028c00
+drintn (RM=0) ~a2340000000000e0 => a238000000000016
+drintn (RM=1) ~a2340000000000e0 => a238000000000016
+drintn (RM=2) ~a2340000000000e0 => a238000000000016
+drintn (RM=3) ~a2340000000000e0 => a238000000000016
+drintn (RM=4) ~a2340000000000e0 => a238000000000016
+drintn (RM=5) ~a2340000000000e0 => a238000000000016
+drintn (RM=6) ~a2340000000000e0 => a238000000000016
+drintn (RM=7) ~a2340000000000e0 => a238000000000016
+drintn (RM=0) ~22240000000000cf => 2238000000000000
+drintn (RM=1) ~22240000000000cf => 2238000000000000
+drintn (RM=2) ~22240000000000cf => 2238000000000000
+drintn (RM=3) ~22240000000000cf => 2238000000000000
+drintn (RM=4) ~22240000000000cf => 2238000000000001
+drintn (RM=5) ~22240000000000cf => 2238000000000000
+drintn (RM=6) ~22240000000000cf => 2238000000000001
+drintn (RM=7) ~22240000000000cf => 2238000000000000
+drintn (RM=0) ~a21400010a395bcf => a238000000000004
+drintn (RM=1) ~a21400010a395bcf => a238000000000004
+drintn (RM=2) ~a21400010a395bcf => a238000000000004
+drintn (RM=3) ~a21400010a395bcf => a238000000000004
+drintn (RM=4) ~a21400010a395bcf => a238000000000004
+drintn (RM=5) ~a21400010a395bcf => a238000000000005
+drintn (RM=6) ~a21400010a395bcf => a238000000000005
+drintn (RM=7) ~a21400010a395bcf => a238000000000004
+drintn (RM=0) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=1) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=2) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=3) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=4) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=5) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=6) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=7) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintn (RM=0) ~000400000089b000 => 2238000000000000
+drintn (RM=1) ~000400000089b000 => 2238000000000000
+drintn (RM=2) ~000400000089b000 => 2238000000000000
+drintn (RM=3) ~000400000089b000 => 2238000000000000
+drintn (RM=4) ~000400000089b000 => 2238000000000001
+drintn (RM=5) ~000400000089b000 => 2238000000000000
+drintn (RM=6) ~000400000089b000 => 2238000000000001
+drintn (RM=7) ~000400000089b000 => 2238000000000000
+drintn (RM=0) ~2238000000000000 => 2238000000000000
+drintn (RM=1) ~2238000000000000 => 2238000000000000
+drintn (RM=2) ~2238000000000000 => 2238000000000000
+drintn (RM=3) ~2238000000000000 => 2238000000000000
+drintn (RM=4) ~2238000000000000 => 2238000000000000
+drintn (RM=5) ~2238000000000000 => 2238000000000000
+drintn (RM=6) ~2238000000000000 => 2238000000000000
+drintn (RM=7) ~2238000000000000 => 2238000000000000
+drintn (RM=0) ~a238000000000000 => a238000000000000
+drintn (RM=1) ~a238000000000000 => a238000000000000
+drintn (RM=2) ~a238000000000000 => a238000000000000
+drintn (RM=3) ~a238000000000000 => a238000000000000
+drintn (RM=4) ~a238000000000000 => a238000000000000
+drintn (RM=5) ~a238000000000000 => a238000000000000
+drintn (RM=6) ~a238000000000000 => a238000000000000
+drintn (RM=7) ~a238000000000000 => a238000000000000
+drintn (RM=0) ~4248000000000000 => 4248000000000000
+drintn (RM=1) ~4248000000000000 => 4248000000000000
+drintn (RM=2) ~4248000000000000 => 4248000000000000
+drintn (RM=3) ~4248000000000000 => 4248000000000000
+drintn (RM=4) ~4248000000000000 => 4248000000000000
+drintn (RM=5) ~4248000000000000 => 4248000000000000
+drintn (RM=6) ~4248000000000000 => 4248000000000000
+drintn (RM=7) ~4248000000000000 => 4248000000000000
+drintn (RM=0) ~7e34000000000111 => 7c00000000000111
+drintn (RM=1) ~7e34000000000111 => 7c00000000000111
+drintn (RM=2) ~7e34000000000111 => 7c00000000000111
+drintn (RM=3) ~7e34000000000111 => 7c00000000000111
+drintn (RM=4) ~7e34000000000111 => 7c00000000000111
+drintn (RM=5) ~7e34000000000111 => 7c00000000000111
+drintn (RM=6) ~7e34000000000111 => 7c00000000000111
+drintn (RM=7) ~7e34000000000111 => 7c00000000000111
+drintn (RM=0) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=1) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=2) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=3) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=4) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=5) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=6) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=7) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintn (RM=0) ~fc00000000000000 => fc00000000000000
+drintn (RM=1) ~fc00000000000000 => fc00000000000000
+drintn (RM=2) ~fc00000000000000 => fc00000000000000
+drintn (RM=3) ~fc00000000000000 => fc00000000000000
+drintn (RM=4) ~fc00000000000000 => fc00000000000000
+drintn (RM=5) ~fc00000000000000 => fc00000000000000
+drintn (RM=6) ~fc00000000000000 => fc00000000000000
+drintn (RM=7) ~fc00000000000000 => fc00000000000000
+drintn (RM=0) ~7800000000000000 => 7800000000000000
+drintn (RM=1) ~7800000000000000 => 7800000000000000
+drintn (RM=2) ~7800000000000000 => 7800000000000000
+drintn (RM=3) ~7800000000000000 => 7800000000000000
+drintn (RM=4) ~7800000000000000 => 7800000000000000
+drintn (RM=5) ~7800000000000000 => 7800000000000000
+drintn (RM=6) ~7800000000000000 => 7800000000000000
+drintn (RM=7) ~7800000000000000 => 7800000000000000
+drintn (RM=0) ~f800000000000000 => f800000000000000
+drintn (RM=1) ~f800000000000000 => f800000000000000
+drintn (RM=2) ~f800000000000000 => f800000000000000
+drintn (RM=3) ~f800000000000000 => f800000000000000
+drintn (RM=4) ~f800000000000000 => f800000000000000
+drintn (RM=5) ~f800000000000000 => f800000000000000
+drintn (RM=6) ~f800000000000000 => f800000000000000
+drintn (RM=7) ~f800000000000000 => f800000000000000
+drintn (RM=0) ~7a34000000000000 => 7800000000000000
+drintn (RM=1) ~7a34000000000000 => 7800000000000000
+drintn (RM=2) ~7a34000000000000 => 7800000000000000
+drintn (RM=3) ~7a34000000000000 => 7800000000000000
+drintn (RM=4) ~7a34000000000000 => 7800000000000000
+drintn (RM=5) ~7a34000000000000 => 7800000000000000
+drintn (RM=6) ~7a34000000000000 => 7800000000000000
+drintn (RM=7) ~7a34000000000000 => 7800000000000000
+
+drintnq (RM=0) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=1) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=2) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=3) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=4) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=5) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=6) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=7) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintnq (RM=0) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=1) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=2) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=3) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=4) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=5) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=6) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=7) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintnq (RM=0) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=1) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=2) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=3) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=4) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=5) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=6) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=7) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintnq (RM=0) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintnq (RM=5) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintnq (RM=7) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=1) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=2) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=3) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=4) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=5) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintnq (RM=6) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintnq (RM=7) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintnq (RM=0) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintnq (RM=5) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintnq (RM=7) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintnq (RM=5) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintnq (RM=7) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=1) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=2) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=3) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=4) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=5) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=6) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=7) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintnq (RM=0) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=1) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=2) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=3) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=4) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=5) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=6) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=7) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintnq (RM=0) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=1) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=2) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=3) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=4) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=5) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=6) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=7) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintnq (RM=0) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=1) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=2) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=3) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=4) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=5) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=6) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=7) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintnq (RM=0) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=1) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=2) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=3) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=4) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=5) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=6) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=7) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintnq (RM=0) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=1) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=2) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=3) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=4) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=5) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=6) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=7) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintnq (RM=0) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=1) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=2) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=3) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=4) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=5) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=6) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=7) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintnq (RM=0) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=1) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=2) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=3) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=4) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=5) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=6) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=7) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=0) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=1) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=2) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=3) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=4) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=5) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=6) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintnq (RM=7) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+drintx (RM=0) ~2234000000000e50 => 22380000000001c5
+drintx (RM=1) ~2234000000000e50 => 22380000000001c5
+drintx (RM=2) ~2234000000000e50 => 22380000000001c5
+drintx (RM=3) ~2234000000000e50 => 22380000000001c5
+drintx (RM=4) ~2234000000000e50 => 22380000000001c5
+drintx (RM=5) ~2234000000000e50 => 22380000000001c5
+drintx (RM=6) ~2234000000000e50 => 22380000000001c5
+drintx (RM=7) ~2234000000000e50 => 22380000000001c5
+drintx (RM=0) ~223400000014c000 => 2238000000028c00
+drintx (RM=1) ~223400000014c000 => 2238000000028c00
+drintx (RM=2) ~223400000014c000 => 2238000000028c00
+drintx (RM=3) ~223400000014c000 => 2238000000028c00
+drintx (RM=4) ~223400000014c000 => 2238000000028c00
+drintx (RM=5) ~223400000014c000 => 2238000000028c00
+drintx (RM=6) ~223400000014c000 => 2238000000028c00
+drintx (RM=7) ~223400000014c000 => 2238000000028c00
+drintx (RM=0) ~a2340000000000e0 => a238000000000016
+drintx (RM=1) ~a2340000000000e0 => a238000000000016
+drintx (RM=2) ~a2340000000000e0 => a238000000000016
+drintx (RM=3) ~a2340000000000e0 => a238000000000016
+drintx (RM=4) ~a2340000000000e0 => a238000000000016
+drintx (RM=5) ~a2340000000000e0 => a238000000000016
+drintx (RM=6) ~a2340000000000e0 => a238000000000016
+drintx (RM=7) ~a2340000000000e0 => a238000000000016
+drintx (RM=0) ~22240000000000cf => 2238000000000000
+drintx (RM=1) ~22240000000000cf => 2238000000000000
+drintx (RM=2) ~22240000000000cf => 2238000000000000
+drintx (RM=3) ~22240000000000cf => 2238000000000000
+drintx (RM=4) ~22240000000000cf => 2238000000000001
+drintx (RM=5) ~22240000000000cf => 2238000000000000
+drintx (RM=6) ~22240000000000cf => 2238000000000001
+drintx (RM=7) ~22240000000000cf => 2238000000000000
+drintx (RM=0) ~a21400010a395bcf => a238000000000004
+drintx (RM=1) ~a21400010a395bcf => a238000000000004
+drintx (RM=2) ~a21400010a395bcf => a238000000000004
+drintx (RM=3) ~a21400010a395bcf => a238000000000004
+drintx (RM=4) ~a21400010a395bcf => a238000000000004
+drintx (RM=5) ~a21400010a395bcf => a238000000000005
+drintx (RM=6) ~a21400010a395bcf => a238000000000005
+drintx (RM=7) ~a21400010a395bcf => a238000000000004
+drintx (RM=0) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=1) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=2) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=3) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=4) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=5) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=6) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=7) ~6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drintx (RM=0) ~000400000089b000 => 2238000000000000
+drintx (RM=1) ~000400000089b000 => 2238000000000000
+drintx (RM=2) ~000400000089b000 => 2238000000000000
+drintx (RM=3) ~000400000089b000 => 2238000000000000
+drintx (RM=4) ~000400000089b000 => 2238000000000001
+drintx (RM=5) ~000400000089b000 => 2238000000000000
+drintx (RM=6) ~000400000089b000 => 2238000000000001
+drintx (RM=7) ~000400000089b000 => 2238000000000000
+drintx (RM=0) ~2238000000000000 => 2238000000000000
+drintx (RM=1) ~2238000000000000 => 2238000000000000
+drintx (RM=2) ~2238000000000000 => 2238000000000000
+drintx (RM=3) ~2238000000000000 => 2238000000000000
+drintx (RM=4) ~2238000000000000 => 2238000000000000
+drintx (RM=5) ~2238000000000000 => 2238000000000000
+drintx (RM=6) ~2238000000000000 => 2238000000000000
+drintx (RM=7) ~2238000000000000 => 2238000000000000
+drintx (RM=0) ~a238000000000000 => a238000000000000
+drintx (RM=1) ~a238000000000000 => a238000000000000
+drintx (RM=2) ~a238000000000000 => a238000000000000
+drintx (RM=3) ~a238000000000000 => a238000000000000
+drintx (RM=4) ~a238000000000000 => a238000000000000
+drintx (RM=5) ~a238000000000000 => a238000000000000
+drintx (RM=6) ~a238000000000000 => a238000000000000
+drintx (RM=7) ~a238000000000000 => a238000000000000
+drintx (RM=0) ~4248000000000000 => 4248000000000000
+drintx (RM=1) ~4248000000000000 => 4248000000000000
+drintx (RM=2) ~4248000000000000 => 4248000000000000
+drintx (RM=3) ~4248000000000000 => 4248000000000000
+drintx (RM=4) ~4248000000000000 => 4248000000000000
+drintx (RM=5) ~4248000000000000 => 4248000000000000
+drintx (RM=6) ~4248000000000000 => 4248000000000000
+drintx (RM=7) ~4248000000000000 => 4248000000000000
+drintx (RM=0) ~7e34000000000111 => 7c00000000000111
+drintx (RM=1) ~7e34000000000111 => 7c00000000000111
+drintx (RM=2) ~7e34000000000111 => 7c00000000000111
+drintx (RM=3) ~7e34000000000111 => 7c00000000000111
+drintx (RM=4) ~7e34000000000111 => 7c00000000000111
+drintx (RM=5) ~7e34000000000111 => 7c00000000000111
+drintx (RM=6) ~7e34000000000111 => 7c00000000000111
+drintx (RM=7) ~7e34000000000111 => 7c00000000000111
+drintx (RM=0) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=1) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=2) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=3) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=4) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=5) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=6) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=7) ~fe000000d0e0a0d0 => fc000000d0e0a0d0
+drintx (RM=0) ~fc00000000000000 => fc00000000000000
+drintx (RM=1) ~fc00000000000000 => fc00000000000000
+drintx (RM=2) ~fc00000000000000 => fc00000000000000
+drintx (RM=3) ~fc00000000000000 => fc00000000000000
+drintx (RM=4) ~fc00000000000000 => fc00000000000000
+drintx (RM=5) ~fc00000000000000 => fc00000000000000
+drintx (RM=6) ~fc00000000000000 => fc00000000000000
+drintx (RM=7) ~fc00000000000000 => fc00000000000000
+drintx (RM=0) ~7800000000000000 => 7800000000000000
+drintx (RM=1) ~7800000000000000 => 7800000000000000
+drintx (RM=2) ~7800000000000000 => 7800000000000000
+drintx (RM=3) ~7800000000000000 => 7800000000000000
+drintx (RM=4) ~7800000000000000 => 7800000000000000
+drintx (RM=5) ~7800000000000000 => 7800000000000000
+drintx (RM=6) ~7800000000000000 => 7800000000000000
+drintx (RM=7) ~7800000000000000 => 7800000000000000
+drintx (RM=0) ~f800000000000000 => f800000000000000
+drintx (RM=1) ~f800000000000000 => f800000000000000
+drintx (RM=2) ~f800000000000000 => f800000000000000
+drintx (RM=3) ~f800000000000000 => f800000000000000
+drintx (RM=4) ~f800000000000000 => f800000000000000
+drintx (RM=5) ~f800000000000000 => f800000000000000
+drintx (RM=6) ~f800000000000000 => f800000000000000
+drintx (RM=7) ~f800000000000000 => f800000000000000
+drintx (RM=0) ~7a34000000000000 => 7800000000000000
+drintx (RM=1) ~7a34000000000000 => 7800000000000000
+drintx (RM=2) ~7a34000000000000 => 7800000000000000
+drintx (RM=3) ~7a34000000000000 => 7800000000000000
+drintx (RM=4) ~7a34000000000000 => 7800000000000000
+drintx (RM=5) ~7a34000000000000 => 7800000000000000
+drintx (RM=6) ~7a34000000000000 => 7800000000000000
+drintx (RM=7) ~7a34000000000000 => 7800000000000000
+
+drintxq (RM=0) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=1) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=2) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=3) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=4) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=5) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=6) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=7) ~2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+drintxq (RM=0) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=1) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=2) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=3) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=4) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=5) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=6) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=7) ~2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drintxq (RM=0) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=1) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=2) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=3) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=4) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=5) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=6) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=7) ~a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drintxq (RM=0) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintxq (RM=5) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000001
+drintxq (RM=7) ~2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=1) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=2) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=3) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=4) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=5) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintxq (RM=6) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000005
+drintxq (RM=7) ~a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+drintxq (RM=0) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintxq (RM=5) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000001
+drintxq (RM=7) ~6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintxq (RM=5) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000001
+drintxq (RM=7) ~000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=1) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=2) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=3) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=4) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=5) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=6) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=7) ~2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+drintxq (RM=0) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=1) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=2) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=3) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=4) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=5) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=6) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=7) ~a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+drintxq (RM=0) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=1) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=2) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=3) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=4) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=5) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=6) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=7) ~a248000000000000 0000000000000000 ==> a248000000000000 0000000000000000
+drintxq (RM=0) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=1) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=2) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=3) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=4) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=5) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=6) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=7) ~7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+drintxq (RM=0) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=1) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=2) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=3) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=4) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=5) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=6) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=7) ~fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+drintxq (RM=0) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=1) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=2) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=3) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=4) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=5) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=6) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=7) ~7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+drintxq (RM=0) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=1) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=2) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=3) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=4) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=5) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=6) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=7) ~7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+drintxq (RM=0) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=1) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=2) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=3) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=4) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=5) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=6) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=7) ~f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=0) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=1) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=2) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=3) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=4) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=5) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=6) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drintxq (RM=7) ~f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+Test DFP insert/extract instructions
+diex >> 768, 2234000000000e50 => 7c00000000000e50
+diex >> 355, 2234000000000e50 => 218c000000000e50
+diex >> 0, 2234000000000e50 => 0000000000000e50
+diex >> -1, 2234000000000e50 => 7800000000000e50
+diex >> -2, 2234000000000e50 => 7c00000000000e50
+diex >> -3, 2234000000000e50 => 7e00000000000e50
+diex >> -4, 2234000000000e50 => 7c00000000000e50
+diex >> -5, 2234000000000e50 => 7c00000000000e50
+diex >> 768, 223400000014c000 => 7c0000000014c000
+diex >> 355, 223400000014c000 => 218c00000014c000
+diex >> 0, 223400000014c000 => 000000000014c000
+diex >> -1, 223400000014c000 => 780000000014c000
+diex >> -2, 223400000014c000 => 7c0000000014c000
+diex >> -3, 223400000014c000 => 7e0000000014c000
+diex >> -4, 223400000014c000 => 7c0000000014c000
+diex >> -5, 223400000014c000 => 7c0000000014c000
+diex >> 768, a2340000000000e0 => fc000000000000e0
+diex >> 355, a2340000000000e0 => a18c0000000000e0
+diex >> 0, a2340000000000e0 => 80000000000000e0
+diex >> -1, a2340000000000e0 => f8000000000000e0
+diex >> -2, a2340000000000e0 => fc000000000000e0
+diex >> -3, a2340000000000e0 => fe000000000000e0
+diex >> -4, a2340000000000e0 => fc000000000000e0
+diex >> -5, a2340000000000e0 => fc000000000000e0
+diex >> 768, 22240000000000cf => 7c000000000000cf
+diex >> 355, 22240000000000cf => 218c0000000000cf
+diex >> 0, 22240000000000cf => 00000000000000cf
+diex >> -1, 22240000000000cf => 78000000000000cf
+diex >> -2, 22240000000000cf => 7c000000000000cf
+diex >> -3, 22240000000000cf => 7e000000000000cf
+diex >> -4, 22240000000000cf => 7c000000000000cf
+diex >> -5, 22240000000000cf => 7c000000000000cf
+diex >> 768, a21400010a395bcf => fc0000010a395bcf
+diex >> 355, a21400010a395bcf => a18c00010a395bcf
+diex >> 0, a21400010a395bcf => 800000010a395bcf
+diex >> -1, a21400010a395bcf => f80000010a395bcf
+diex >> -2, a21400010a395bcf => fc0000010a395bcf
+diex >> -3, a21400010a395bcf => fe0000010a395bcf
+diex >> -4, a21400010a395bcf => fc0000010a395bcf
+diex >> -5, a21400010a395bcf => fc0000010a395bcf
+diex >> 768, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> 355, 6e4d3f1f534acdd4 => 6d8d3f1f534acdd4
+diex >> 0, 6e4d3f1f534acdd4 => 64013f1f534acdd4
+diex >> -1, 6e4d3f1f534acdd4 => 78013f1f534acdd4
+diex >> -2, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> -3, 6e4d3f1f534acdd4 => 7e013f1f534acdd4
+diex >> -4, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> -5, 6e4d3f1f534acdd4 => 7c013f1f534acdd4
+diex >> 768, 000400000089b000 => 7c0000000089b000
+diex >> 355, 000400000089b000 => 218c00000089b000
+diex >> 0, 000400000089b000 => 000000000089b000
+diex >> -1, 000400000089b000 => 780000000089b000
+diex >> -2, 000400000089b000 => 7c0000000089b000
+diex >> -3, 000400000089b000 => 7e0000000089b000
+diex >> -4, 000400000089b000 => 7c0000000089b000
+diex >> -5, 000400000089b000 => 7c0000000089b000
+diex >> 768, 2238000000000000 => 7c00000000000000
+diex >> 355, 2238000000000000 => 218c000000000000
+diex >> 0, 2238000000000000 => 0000000000000000
+diex >> -1, 2238000000000000 => 7800000000000000
+diex >> -2, 2238000000000000 => 7c00000000000000
+diex >> -3, 2238000000000000 => 7e00000000000000
+diex >> -4, 2238000000000000 => 7c00000000000000
+diex >> -5, 2238000000000000 => 7c00000000000000
+diex >> 768, a238000000000000 => fc00000000000000
+diex >> 355, a238000000000000 => a18c000000000000
+diex >> 0, a238000000000000 => 8000000000000000
+diex >> -1, a238000000000000 => f800000000000000
+diex >> -2, a238000000000000 => fc00000000000000
+diex >> -3, a238000000000000 => fe00000000000000
+diex >> -4, a238000000000000 => fc00000000000000
+diex >> -5, a238000000000000 => fc00000000000000
+diex >> 768, 4248000000000000 => 7c00000000000000
+diex >> 355, 4248000000000000 => 218c000000000000
+diex >> 0, 4248000000000000 => 0000000000000000
+diex >> -1, 4248000000000000 => 7800000000000000
+diex >> -2, 4248000000000000 => 7c00000000000000
+diex >> -3, 4248000000000000 => 7e00000000000000
+diex >> -4, 4248000000000000 => 7c00000000000000
+diex >> -5, 4248000000000000 => 7c00000000000000
+diex >> 768, 7e34000000000111 => 7c00000000000111
+diex >> 355, 7e34000000000111 => 218c000000000111
+diex >> 0, 7e34000000000111 => 0000000000000111
+diex >> -1, 7e34000000000111 => 7800000000000111
+diex >> -2, 7e34000000000111 => 7c00000000000111
+diex >> -3, 7e34000000000111 => 7e00000000000111
+diex >> -4, 7e34000000000111 => 7c00000000000111
+diex >> -5, 7e34000000000111 => 7c00000000000111
+diex >> 768, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> 355, fe000000d0e0a0d0 => a18c0000d0e0a0d0
+diex >> 0, fe000000d0e0a0d0 => 80000000d0e0a0d0
+diex >> -1, fe000000d0e0a0d0 => f8000000d0e0a0d0
+diex >> -2, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> -3, fe000000d0e0a0d0 => fe000000d0e0a0d0
+diex >> -4, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> -5, fe000000d0e0a0d0 => fc000000d0e0a0d0
+diex >> 768, fc00000000000000 => fc00000000000000
+diex >> 355, fc00000000000000 => a18c000000000000
+diex >> 0, fc00000000000000 => 8000000000000000
+diex >> -1, fc00000000000000 => f800000000000000
+diex >> -2, fc00000000000000 => fc00000000000000
+diex >> -3, fc00000000000000 => fe00000000000000
+diex >> -4, fc00000000000000 => fc00000000000000
+diex >> -5, fc00000000000000 => fc00000000000000
+diex >> 768, 7800000000000000 => 7c00000000000000
+diex >> 355, 7800000000000000 => 218c000000000000
+diex >> 0, 7800000000000000 => 0000000000000000
+diex >> -1, 7800000000000000 => 7800000000000000
+diex >> -2, 7800000000000000 => 7c00000000000000
+diex >> -3, 7800000000000000 => 7e00000000000000
+diex >> -4, 7800000000000000 => 7c00000000000000
+diex >> -5, 7800000000000000 => 7c00000000000000
+diex >> 768, f800000000000000 => fc00000000000000
+diex >> 355, f800000000000000 => a18c000000000000
+diex >> 0, f800000000000000 => 8000000000000000
+diex >> -1, f800000000000000 => f800000000000000
+diex >> -2, f800000000000000 => fc00000000000000
+diex >> -3, f800000000000000 => fe00000000000000
+diex >> -4, f800000000000000 => fc00000000000000
+diex >> -5, f800000000000000 => fc00000000000000
+diex >> 768, 7a34000000000000 => 7c00000000000000
+diex >> 355, 7a34000000000000 => 218c000000000000
+diex >> 0, 7a34000000000000 => 0000000000000000
+diex >> -1, 7a34000000000000 => 7800000000000000
+diex >> -2, 7a34000000000000 => 7c00000000000000
+diex >> -3, 7a34000000000000 => 7e00000000000000
+diex >> -4, 7a34000000000000 => 7c00000000000000
+diex >> -5, 7a34000000000000 => 7c00000000000000
+
+diexq >> 12288, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> 5235, 2207c00000000000 0000000000000e50 ==> 211cc00000000000 0000000000000e50
+diexq >> 0, 2207c00000000000 0000000000000e50 ==> 0000000000000000 0000000000000e50
+diexq >> -1, 2207c00000000000 0000000000000e50 ==> 7800000000000000 0000000000000e50
+diexq >> -2, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> -3, 2207c00000000000 0000000000000e50 ==> 7e00000000000000 0000000000000e50
+diexq >> -4, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> -5, 2207c00000000000 0000000000000e50 ==> 7c00000000000000 0000000000000e50
+diexq >> 12288, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> 5235, 2207c00000000000 000000000014c000 ==> 211cc00000000000 000000000014c000
+diexq >> 0, 2207c00000000000 000000000014c000 ==> 0000000000000000 000000000014c000
+diexq >> -1, 2207c00000000000 000000000014c000 ==> 7800000000000000 000000000014c000
+diexq >> -2, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> -3, 2207c00000000000 000000000014c000 ==> 7e00000000000000 000000000014c000
+diexq >> -4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> -5, 2207c00000000000 000000000014c000 ==> 7c00000000000000 000000000014c000
+diexq >> 12288, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> 5235, a207c00000000000 00000000000000e0 ==> a11cc00000000000 00000000000000e0
+diexq >> 0, a207c00000000000 00000000000000e0 ==> 8000000000000000 00000000000000e0
+diexq >> -1, a207c00000000000 00000000000000e0 ==> f800000000000000 00000000000000e0
+diexq >> -2, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> -3, a207c00000000000 00000000000000e0 ==> fe00000000000000 00000000000000e0
+diexq >> -4, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> -5, a207c00000000000 00000000000000e0 ==> fc00000000000000 00000000000000e0
+diexq >> 12288, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> 5235, 2206c00000000000 00000000000000cf ==> 211cc00000000000 00000000000000cf
+diexq >> 0, 2206c00000000000 00000000000000cf ==> 0000000000000000 00000000000000cf
+diexq >> -1, 2206c00000000000 00000000000000cf ==> 7800000000000000 00000000000000cf
+diexq >> -2, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> -3, 2206c00000000000 00000000000000cf ==> 7e00000000000000 00000000000000cf
+diexq >> -4, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> -5, 2206c00000000000 00000000000000cf ==> 7c00000000000000 00000000000000cf
+diexq >> 12288, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> 5235, a205c00000000000 000000010a395bcf ==> a11cc00000000000 000000010a395bcf
+diexq >> 0, a205c00000000000 000000010a395bcf ==> 8000000000000000 000000010a395bcf
+diexq >> -1, a205c00000000000 000000010a395bcf ==> f800000000000000 000000010a395bcf
+diexq >> -2, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> -3, a205c00000000000 000000010a395bcf ==> fe00000000000000 000000010a395bcf
+diexq >> -4, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> -5, a205c00000000000 000000010a395bcf ==> fc00000000000000 000000010a395bcf
+diexq >> 12288, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> 5235, 6209400000fd0000 00253f1f534acdd4 ==> 691cc00000fd0000 00253f1f534acdd4
+diexq >> 0, 6209400000fd0000 00253f1f534acdd4 ==> 6000000000fd0000 00253f1f534acdd4
+diexq >> -1, 6209400000fd0000 00253f1f534acdd4 ==> 7800000000fd0000 00253f1f534acdd4
+diexq >> -2, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> -3, 6209400000fd0000 00253f1f534acdd4 ==> 7e00000000fd0000 00253f1f534acdd4
+diexq >> -4, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> -5, 6209400000fd0000 00253f1f534acdd4 ==> 7c00000000fd0000 00253f1f534acdd4
+diexq >> 12288, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> 5235, 000400000089b000 0a6000d000000049 ==> 211cc0000089b000 0a6000d000000049
+diexq >> 0, 000400000089b000 0a6000d000000049 ==> 000000000089b000 0a6000d000000049
+diexq >> -1, 000400000089b000 0a6000d000000049 ==> 780000000089b000 0a6000d000000049
+diexq >> -2, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> -3, 000400000089b000 0a6000d000000049 ==> 7e0000000089b000 0a6000d000000049
+diexq >> -4, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> -5, 000400000089b000 0a6000d000000049 ==> 7c0000000089b000 0a6000d000000049
+diexq >> 12288, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 5235, 2208000000000000 0000000000000000 ==> 211cc00000000000 0000000000000000
+diexq >> 0, 2208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+diexq >> -1, 2208000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+diexq >> -2, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -3, 2208000000000000 0000000000000000 ==> 7e00000000000000 0000000000000000
+diexq >> -4, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -5, 2208000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 12288, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, a208000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, a208000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, a208000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, a208000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, a208000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 12288, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, a248000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, a248000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, a248000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, a248000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, a248000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 12288, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 5235, 7c00000000000000 0000000000000000 ==> 211cc00000000000 0000000000000000
+diexq >> 0, 7c00000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+diexq >> -1, 7c00000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+diexq >> -2, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -3, 7c00000000000000 0000000000000000 ==> 7e00000000000000 0000000000000000
+diexq >> -4, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -5, 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 12288, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> 5235, fc00000000000000 c00100035b007700 ==> a11cc00000000000 c00100035b007700
+diexq >> 0, fc00000000000000 c00100035b007700 ==> 8000000000000000 c00100035b007700
+diexq >> -1, fc00000000000000 c00100035b007700 ==> f800000000000000 c00100035b007700
+diexq >> -2, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> -3, fc00000000000000 c00100035b007700 ==> fe00000000000000 c00100035b007700
+diexq >> -4, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> -5, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+diexq >> 12288, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> 5235, 7e00000000000000 fe000000d0e0a0d0 ==> 211cc00000000000 fe000000d0e0a0d0
+diexq >> 0, 7e00000000000000 fe000000d0e0a0d0 ==> 0000000000000000 fe000000d0e0a0d0
+diexq >> -1, 7e00000000000000 fe000000d0e0a0d0 ==> 7800000000000000 fe000000d0e0a0d0
+diexq >> -2, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> -3, 7e00000000000000 fe000000d0e0a0d0 ==> 7e00000000000000 fe000000d0e0a0d0
+diexq >> -4, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> -5, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+diexq >> 12288, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 5235, 7800000000000000 0000000000000000 ==> 211cc00000000000 0000000000000000
+diexq >> 0, 7800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+diexq >> -1, 7800000000000000 0000000000000000 ==> 7800000000000000 0000000000000000
+diexq >> -2, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -3, 7800000000000000 0000000000000000 ==> 7e00000000000000 0000000000000000
+diexq >> -4, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> -5, 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+diexq >> 12288, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, f800000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, f800000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, f800000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, f800000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 12288, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> 5235, f900000000000000 0000000000000000 ==> a11cc00000000000 0000000000000000
+diexq >> 0, f900000000000000 0000000000000000 ==> 8000000000000000 0000000000000000
+diexq >> -1, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+diexq >> -2, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -3, f900000000000000 0000000000000000 ==> fe00000000000000 0000000000000000
+diexq >> -4, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+diexq >> -5, f900000000000000 0000000000000000 ==> fc00000000000000 0000000000000000
+
+dxex << 2234000000000e50 => 000000000000018d
+dxex << 223400000014c000 => 000000000000018d
+dxex << a2340000000000e0 => 000000000000018d
+dxex << 22240000000000cf => 0000000000000189
+dxex << a21400010a395bcf => 0000000000000185
+dxex << 6e4d3f1f534acdd4 => 0000000000000193
+dxex << 000400000089b000 => 0000000000000001
+dxex << 2238000000000000 => 000000000000018e
+dxex << a238000000000000 => 000000000000018e
+dxex << 4248000000000000 => 0000000000000292
+dxex << 7e34000000000111 => fffffffffffffffd
+dxex << fe000000d0e0a0d0 => fffffffffffffffd
+dxex << fc00000000000000 => fffffffffffffffe
+dxex << 7800000000000000 => ffffffffffffffff
+dxex << f800000000000000 => ffffffffffffffff
+dxex << 7a34000000000000 => ffffffffffffffff
+
+dxexq << 2207c00000000000 0000000000000e50 ==> 000000000000181f 0000000000000000
+dxexq << 2207c00000000000 000000000014c000 ==> 000000000000181f 0000000000000000
+dxexq << a207c00000000000 00000000000000e0 ==> 000000000000181f 0000000000000000
+dxexq << 2206c00000000000 00000000000000cf ==> 000000000000181b 0000000000000000
+dxexq << a205c00000000000 000000010a395bcf ==> 0000000000001817 0000000000000000
+dxexq << 6209400000fd0000 00253f1f534acdd4 ==> 0000000000000825 0000000000000000
+dxexq << 000400000089b000 0a6000d000000049 ==> 0000000000000010 0000000000000000
+dxexq << 2208000000000000 0000000000000000 ==> 0000000000001820 0000000000000000
+dxexq << a208000000000000 0000000000000000 ==> 0000000000001820 0000000000000000
+dxexq << a248000000000000 0000000000000000 ==> 0000000000001920 0000000000000000
+dxexq << 7c00000000000000 0000000000000000 ==> fffffffffffffffe 0000000000000000
+dxexq << fc00000000000000 c00100035b007700 ==> fffffffffffffffe 0000000000000000
+dxexq << 7e00000000000000 fe000000d0e0a0d0 ==> fffffffffffffffd 0000000000000000
+dxexq << 7800000000000000 0000000000000000 ==> ffffffffffffffff 0000000000000000
+dxexq << f800000000000000 0000000000000000 ==> ffffffffffffffff 0000000000000000
+dxexq << f900000000000000 0000000000000000 ==> ffffffffffffffff 0000000000000000
+
+Test DFP reround instructions
+drrnd (RMC=0, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=1, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=2, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=3, ref sig=0) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=0, ref sig=2) [RR]2234000000000e50 => 223c000000000034
+drrnd (RMC=1, ref sig=2) [RR]2234000000000e50 => 223c000000000034
+drrnd (RMC=2, ref sig=2) [RR]2234000000000e50 => 223c000000000035
+drrnd (RMC=3, ref sig=2) [RR]2234000000000e50 => 223c000000000034
+drrnd (RMC=0, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=1, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=2, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=3, ref sig=6) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=0, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=1, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=2, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=3, ref sig=63) [RR]2234000000000e50 => 2234000000000e50
+drrnd (RMC=0, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=1, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=2, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=3, ref sig=0) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=0, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=1, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=2, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=3, ref sig=2) [RR]223400000014c000 => 2248000000000012
+drrnd (RMC=0, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=1, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=2, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=3, ref sig=6) [RR]223400000014c000 => 2238000000028c00
+drrnd (RMC=0, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=1, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=2, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=3, ref sig=63) [RR]223400000014c000 => 223400000014c000
+drrnd (RMC=0, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=1, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=2, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=3, ref sig=0) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=0, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=1, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=2, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=3, ref sig=2) [RR]a2340000000000e0 => a238000000000016
+drrnd (RMC=0, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=1, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=2, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=3, ref sig=6) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=0, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=1, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=2, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=3, ref sig=63) [RR]a2340000000000e0 => a2340000000000e0
+drrnd (RMC=0, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=1, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=2, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=3, ref sig=0) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=0, ref sig=2) [RR]22240000000000cf => 2228000000000019
+drrnd (RMC=1, ref sig=2) [RR]22240000000000cf => 2228000000000018
+drrnd (RMC=2, ref sig=2) [RR]22240000000000cf => 2228000000000019
+drrnd (RMC=3, ref sig=2) [RR]22240000000000cf => 2228000000000019
+drrnd (RMC=0, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=1, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=2, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=3, ref sig=6) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=0, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=1, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=2, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=3, ref sig=63) [RR]22240000000000cf => 22240000000000cf
+drrnd (RMC=0, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=1, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=2, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=3, ref sig=0) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=0, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=1, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=2, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=3, ref sig=2) [RR]a21400010a395bcf => a234000000000041
+drrnd (RMC=0, ref sig=6) [RR]a21400010a395bcf => a2240000000849c6
+drrnd (RMC=1, ref sig=6) [RR]a21400010a395bcf => a2240000000849c5
+drrnd (RMC=2, ref sig=6) [RR]a21400010a395bcf => a2240000000849c6
+drrnd (RMC=3, ref sig=6) [RR]a21400010a395bcf => a2240000000849c6
+drrnd (RMC=0, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=1, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=2, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=3, ref sig=63) [RR]a21400010a395bcf => a21400010a395bcf
+drrnd (RMC=0, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=1, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=2, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=3, ref sig=0) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=0, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=1, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=2, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=3, ref sig=2) [RR]6e4d3f1f534acdd4 => 228400000000005e
+drrnd (RMC=0, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=1, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=2, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=3, ref sig=6) [RR]6e4d3f1f534acdd4 => 2274000000063f8f
+drrnd (RMC=0, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=1, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=2, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=3, ref sig=63) [RR]6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+drrnd (RMC=0, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=1, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=2, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=3, ref sig=0) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=0, ref sig=2) [RR]000400000089b000 => 001800000000004f
+drrnd (RMC=1, ref sig=2) [RR]000400000089b000 => 001800000000004e
+drrnd (RMC=2, ref sig=2) [RR]000400000089b000 => 001800000000004f
+drrnd (RMC=3, ref sig=2) [RR]000400000089b000 => 001800000000004f
+drrnd (RMC=0, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=1, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=2, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=3, ref sig=6) [RR]000400000089b000 => 00080000000c3a00
+drrnd (RMC=0, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=1, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=2, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=3, ref sig=63) [RR]000400000089b000 => 000400000089b000
+drrnd (RMC=0, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=0) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=2) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=6) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=1, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=2, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=3, ref sig=63) [RR]2238000000000000 => 2238000000000000
+drrnd (RMC=0, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=0) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=2) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=6) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=1, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=2, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=3, ref sig=63) [RR]a238000000000000 => a238000000000000
+drrnd (RMC=0, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=0) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=2) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=6) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=1, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=2, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=3, ref sig=63) [RR]4248000000000000 => 4248000000000000
+drrnd (RMC=0, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=0) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=2) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=6) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=1, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=2, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=3, ref sig=63) [RR]7e34000000000111 => 7c00000000000111
+drrnd (RMC=0, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=0) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=2) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=6) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=1, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=2, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=3, ref sig=63) [RR]fe000000d0e0a0d0 => fc000000d0e0a0d0
+drrnd (RMC=0, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=0) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=2) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=6) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=1, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=2, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=3, ref sig=63) [RR]fc00000000000000 => fc00000000000000
+drrnd (RMC=0, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=0) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=2) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=6) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=63) [RR]7800000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=0) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=2) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=6) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=1, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=2, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=3, ref sig=63) [RR]f800000000000000 => f800000000000000
+drrnd (RMC=0, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=0) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=2) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=6) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=0, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=1, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=2, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+drrnd (RMC=3, ref sig=63) [RR]7a34000000000000 => 7800000000000000
+
+drrndq (RMC=0, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=1, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=2, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=3, ref sig=0) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=0, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000034
+drrndq (RMC=1, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000034
+drrndq (RMC=2, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000035
+drrndq (RMC=3, ref sig=2) [RR]2207c00000000000 0000000000000e50 ==> 2208400000000000 0000000000000034
+drrndq (RMC=0, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=1, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=2, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=3, ref sig=6) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=0, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=1, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=2, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=3, ref sig=63) [RR]2207c00000000000 0000000000000e50 ==> 2207c00000000000 0000000000000e50
+drrndq (RMC=0, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=1, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=2, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=3, ref sig=0) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=0, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=1, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=2, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=3, ref sig=2) [RR]2207c00000000000 000000000014c000 ==> 2209000000000000 0000000000000012
+drrndq (RMC=0, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=1, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=2, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=3, ref sig=6) [RR]2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+drrndq (RMC=0, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=1, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=2, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=3, ref sig=63) [RR]2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+drrndq (RMC=0, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=1, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=2, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=3, ref sig=0) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=0, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=1, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=2, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=3, ref sig=2) [RR]a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+drrndq (RMC=0, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=1, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=2, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=3, ref sig=6) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=0, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=1, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=2, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=3, ref sig=63) [RR]a207c00000000000 00000000000000e0 ==> a207c00000000000 00000000000000e0
+drrndq (RMC=0, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=1, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=2, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=3, ref sig=0) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=0, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000019
+drrndq (RMC=1, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000018
+drrndq (RMC=2, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000019
+drrndq (RMC=3, ref sig=2) [RR]2206c00000000000 00000000000000cf ==> 2207000000000000 0000000000000019
+drrndq (RMC=0, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=1, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=2, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=3, ref sig=6) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=0, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=1, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=2, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=3, ref sig=63) [RR]2206c00000000000 00000000000000cf ==> 2206c00000000000 00000000000000cf
+drrndq (RMC=0, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=1, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=2, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
+drrndq (RMC=3, ref sig=0) [RR]a205c00000000000 000000010a395bcf ==> a205c00000000000 000000010a395bcf
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+drrndq (RMC=2, ref sig=6) [RR]a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
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+drrndq (RMC=1, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=0) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=2) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=6) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=0, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=1, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=2, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+drrndq (RMC=3, ref sig=63) [RR]f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+Test DFP quantize instructions
+dqua (RMC= 0) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 1) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 2) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 3) [Q] 2234000000000e50, 223400000014c000 => 223400000014c000
+dqua (RMC= 0) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 1) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 2) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 3) [Q] a2340000000000e0, 223400000014c000 => 223400000014c000
+dqua (RMC= 0) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c6
+dqua (RMC= 1) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c5
+dqua (RMC= 2) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c6
+dqua (RMC= 3) [Q] 22240000000000cf, a21400010a395bcf => a2240000000849c6
+dqua (RMC= 0) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 1) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 2) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 3) [Q] 2234000000000e50, 000400000089b000 => 2234000000000000
+dqua (RMC= 0) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 1) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 2) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 3) [Q] a2340000000000e0, a21400010a395bcf => a234000000000041
+dqua (RMC= 0) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 1) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 2) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 3) [Q] 6e4d3f1f534acdd4, 223400000014c000 => 224c000000000001
+dqua (RMC= 0) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 1) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 2) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 3) [Q] 6e4d3f1f534acdd4, a2340000000000e0 => a24c000000000000
+dqua (RMC= 0) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 1) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 2) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 3) [Q] 2238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 0) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 1) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 2) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 3) [Q] 2238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 0) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 1) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 2) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 3) [Q] a238000000000000, 2234000000000e50 => 22380000000001c5
+dqua (RMC= 0) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 1) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 2) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 3) [Q] a238000000000000, 223400000014c000 => 2238000000028c00
+dqua (RMC= 0) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 1) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 2) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 3) [Q] a238000000000000, a2340000000000e0 => a238000000000016
+dqua (RMC= 0) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 1) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 2) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 3) [Q] 2238000000000000, a238000000000000 => a238000000000000
+dqua (RMC= 0) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, f800000000000000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, 223400000014c000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, 7800000000000000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 1) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 2) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 3) [Q] fc00000000000000, fc00000000000000 => fc00000000000000
+dqua (RMC= 0) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fc00000000000000, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, f800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, 2234000000000e50 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, 7800000000000000 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 1) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 2) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 3) [Q] fe000000d0e0a0d0, fe000000d0e0a0d0 => fc000000d0e0a0d0
+dqua (RMC= 0) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 1) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 2) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 3) [Q] f800000000000000, f800000000000000 => f800000000000000
+dqua (RMC= 0) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 1) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 2) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 3) [Q] f800000000000000, 22240000000000cf => 7c00000000000000
+dqua (RMC= 0) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+dqua (RMC= 1) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+dqua (RMC= 2) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+dqua (RMC= 3) [Q] f800000000000000, 7a34000000000000 => 7800000000000000
+
+dquaq (RMC= 0) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 1) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 2) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 3) [Q] 2207c00000000000 0000000000000e50, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 0) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 1) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 2) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 3) [Q] a207c00000000000 00000000000000e0, 2207c00000000000 000000000014c000 ==> 2207c00000000000 000000000014c000
+dquaq (RMC= 0) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+dquaq (RMC= 1) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c5
+dquaq (RMC= 2) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+dquaq (RMC= 3) [Q] 2206c00000000000 00000000000000cf, a205c00000000000 000000010a395bcf ==> a206c00000000000 00000000000849c6
+dquaq (RMC= 0) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 1) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 2) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 3) [Q] 2207c00000000000 0000000000000e50, 000400000089b000 0a6000d000000049 ==> 2207c00000000000 0000000000000000
+dquaq (RMC= 0) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 1) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 2) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 3) [Q] a207c00000000000 00000000000000e0, a205c00000000000 000000010a395bcf ==> a207c00000000000 0000000000000041
+dquaq (RMC= 0) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 1) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 2) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 3) [Q] 6209400000fd0000 00253f1f534acdd4, 2207c00000000000 000000000014c000 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 0) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 1) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 2) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 3) [Q] 6209400000fd0000 00253f1f534acdd4, a207c00000000000 00000000000000e0 ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 0) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 1) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 2) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 3) [Q] 2208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 0) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 1) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 2) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 3) [Q] 2208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 0) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 1) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 2) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 3) [Q] a208000000000000 0000000000000000, 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaq (RMC= 0) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 1) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 2) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 3) [Q] a208000000000000 0000000000000000, 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaq (RMC= 0) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 1) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 2) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 3) [Q] a208000000000000 0000000000000000, a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaq (RMC= 0) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 1) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 2) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 3) [Q] 2208000000000000 0000000000000000, a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, f800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, 2207c00000000000 000000000014c000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, 7800000000000000 0000000000000000 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 1) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 2) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 3) [Q] 7e00000000000000 fe000000d0e0a0d0, fc00000000000000 c00100035b007700 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, f800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, 2207c00000000000 0000000000000e50 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, 7800000000000000 0000000000000000 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 1) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 2) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 3) [Q] fc00000000000000 c00100035b007700, fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaq (RMC= 0) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 1) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 2) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 3) [Q] f800000000000000 0000000000000000, f800000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 0) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 1) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 2) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 3) [Q] f800000000000000 0000000000000000, 2206c00000000000 00000000000000cf ==> 7c00000000000000 0000000000000000
+dquaq (RMC= 0) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 1) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 2) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+dquaq (RMC= 3) [Q] f800000000000000 0000000000000000, f900000000000000 0000000000000000 ==> f800000000000000 0000000000000000
+
+Test DFP quantize immediate instructions
+dquai (RMC= 0, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 2234000000000e50 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 1, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 2, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 3, TE= -2) [QI] 2234000000000e50 => 223000000000d280
+dquai (RMC= 0, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 1, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 2, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 3, TE= 0) [QI] 2234000000000e50 => 22380000000001c5
+dquai (RMC= 0, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 2234000000000e50 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 223400000014c000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 1, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 2, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 3, TE= -2) [QI] 223400000014c000 => 2230000001260000
+dquai (RMC= 0, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 1, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 2, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 3, TE= 0) [QI] 223400000014c000 => 2238000000028c00
+dquai (RMC= 0, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 1, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 2, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 3, TE= 5) [QI] 223400000014c000 => 224c000000000001
+dquai (RMC= 0, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] a2340000000000e0 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 1, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 2, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 3, TE= -2) [QI] a2340000000000e0 => a230000000000700
+dquai (RMC= 0, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 1, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 2, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 3, TE= 0) [QI] a2340000000000e0 => a238000000000016
+dquai (RMC= 0, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 1, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 2, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 3, TE= 5) [QI] a2340000000000e0 => a24c000000000000
+dquai (RMC= 0, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 1, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 2, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 3, TE=-16) [QI] 22240000000000cf => 21f8182300000000
+dquai (RMC= 0, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 22240000000000cf => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 22240000000000cf => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 22240000000000cf => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] a21400010a395bcf => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 1, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 2, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 3, TE= -2) [QI] a21400010a395bcf => a230000000000212
+dquai (RMC= 0, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 1, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 2, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 3, TE= 0) [QI] a21400010a395bcf => a238000000000004
+dquai (RMC= 0, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 1, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 2, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 3, TE= 5) [QI] a21400010a395bcf => a24c000000000000
+dquai (RMC= 0, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] 6e4d3f1f534acdd4 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 1, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 2, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 3, TE= 5) [QI] 6e4d3f1f534acdd4 => 6e4d3f1f534acdd4
+dquai (RMC= 0, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 1, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 2, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 3, TE=-16) [QI] 000400000089b000 => 21f8000000000000
+dquai (RMC= 0, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 000400000089b000 => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 000400000089b000 => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 000400000089b000 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 1, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 2, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 3, TE=-16) [QI] 2238000000000000 => 21f8000000000000
+dquai (RMC= 0, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 2238000000000000 => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 2238000000000000 => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 2238000000000000 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 1, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 2, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 3, TE=-16) [QI] a238000000000000 => a1f8000000000000
+dquai (RMC= 0, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 1, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 2, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 3, TE= -2) [QI] a238000000000000 => a230000000000000
+dquai (RMC= 0, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 1, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 2, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 3, TE= 0) [QI] a238000000000000 => a238000000000000
+dquai (RMC= 0, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 1, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 2, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 3, TE= 5) [QI] a238000000000000 => a24c000000000000
+dquai (RMC= 0, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 1, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 2, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 3, TE=-16) [QI] 4248000000000000 => 21f8000000000000
+dquai (RMC= 0, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 1, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 2, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 3, TE= -2) [QI] 4248000000000000 => 2230000000000000
+dquai (RMC= 0, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 1, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 2, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 3, TE= 0) [QI] 4248000000000000 => 2238000000000000
+dquai (RMC= 0, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 1, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 2, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 3, TE= 5) [QI] 4248000000000000 => 224c000000000000
+dquai (RMC= 0, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE=-16) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE= -2) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE= 0) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 1, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 2, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 3, TE= 5) [QI] 7e34000000000111 => 7c00000000000111
+dquai (RMC= 0, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE=-16) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE= -2) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE= 0) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 1, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 2, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 3, TE= 5) [QI] fe000000d0e0a0d0 => fc000000d0e0a0d0
+dquai (RMC= 0, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE=-16) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE= -2) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE= 0) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 1, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 2, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 3, TE= 5) [QI] fc00000000000000 => fc00000000000000
+dquai (RMC= 0, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 5) [QI] 7800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 5) [QI] f800000000000000 => 7c00000000000000
+dquai (RMC= 0, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE=-16) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= -2) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 0) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 0, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 1, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 2, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+dquai (RMC= 3, TE= 5) [QI] 7a34000000000000 => 7c00000000000000
+
+dquaiq (RMC= 0, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 2207c00000000000 0000000000000e50 ==> 2204000000000000 3940000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 1, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 2, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 3, TE= -2) [QI] 2207c00000000000 0000000000000e50 ==> 2207800000000000 000000000000d280
+dquaiq (RMC= 0, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 1, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 2, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 3, TE= 0) [QI] 2207c00000000000 0000000000000e50 ==> 2208000000000000 00000000000001c5
+dquaiq (RMC= 0, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 2207c00000000000 0000000000000e50 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 2207c00000000000 000000000014c000 ==> 2204000000000053 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 1, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 2, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 3, TE= -2) [QI] 2207c00000000000 000000000014c000 ==> 2207800000000000 0000000001260000
+dquaiq (RMC= 0, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 1, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 2, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 3, TE= 0) [QI] 2207c00000000000 000000000014c000 ==> 2208000000000000 0000000000028c00
+dquaiq (RMC= 0, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 1, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 2, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 3, TE= 5) [QI] 2207c00000000000 000000000014c000 ==> 2209400000000000 0000000000000001
+dquaiq (RMC= 0, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 1, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 2, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 3, TE=-16) [QI] a207c00000000000 00000000000000e0 ==> a204000000000000 0380000000000000
+dquaiq (RMC= 0, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 1, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 2, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 3, TE= -2) [QI] a207c00000000000 00000000000000e0 ==> a207800000000000 0000000000000700
+dquaiq (RMC= 0, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 1, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 2, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 3, TE= 0) [QI] a207c00000000000 00000000000000e0 ==> a208000000000000 0000000000000016
+dquaiq (RMC= 0, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] a207c00000000000 00000000000000e0 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 1, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 2, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 3, TE=-16) [QI] 2206c00000000000 00000000000000cf ==> 2204000000000000 0000182300000000
+dquaiq (RMC= 0, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 2206c00000000000 00000000000000cf ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 2206c00000000000 00000000000000cf ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 2206c00000000000 00000000000000cf ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 1, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 2, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 3, TE=-16) [QI] a205c00000000000 000000010a395bcf ==> a204000000000000 010534b9c1e00000
+dquaiq (RMC= 0, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 1, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 2, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 3, TE= -2) [QI] a205c00000000000 000000010a395bcf ==> a207800000000000 0000000000000212
+dquaiq (RMC= 0, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 1, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 2, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 3, TE= 0) [QI] a205c00000000000 000000010a395bcf ==> a208000000000000 0000000000000004
+dquaiq (RMC= 0, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] a205c00000000000 000000010a395bcf ==> a209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 6209400000fd0000 00253f1f534acdd4 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 000400000089b000 0a6000d000000049 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 000400000089b000 0a6000d000000049 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 000400000089b000 0a6000d000000049 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 000400000089b000 0a6000d000000049 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 000400000089b000 0a6000d000000049 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 000400000089b000 0a6000d000000049 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 000400000089b000 0a6000d000000049 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 000400000089b000 0a6000d000000049 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 000400000089b000 0a6000d000000049 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 000400000089b000 0a6000d000000049 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 000400000089b000 0a6000d000000049 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 000400000089b000 0a6000d000000049 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 000400000089b000 0a6000d000000049 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 2208000000000000 0000000000000000 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 2208000000000000 0000000000000000 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 2208000000000000 0000000000000000 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 2208000000000000 0000000000000000 ==> 2204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 2208000000000000 0000000000000000 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 2208000000000000 0000000000000000 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 2208000000000000 0000000000000000 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 2208000000000000 0000000000000000 ==> 2207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 2208000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 2208000000000000 0000000000000000 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 2208000000000000 0000000000000000 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 2208000000000000 0000000000000000 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 2208000000000000 0000000000000000 ==> 2209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] a208000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] a208000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] a208000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] a208000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] a208000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] a208000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] a208000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] a208000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] a208000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] a208000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] a208000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] a208000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] a208000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] a248000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] a248000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] a248000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] a248000000000000 0000000000000000 ==> a204000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] a248000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] a248000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] a248000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] a248000000000000 0000000000000000 ==> a207800000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] a248000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] a248000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] a248000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] a248000000000000 0000000000000000 ==> a208000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] a248000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] a248000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] a248000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] a248000000000000 0000000000000000 ==> a209400000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 7c00000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 1, TE=-16) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 2, TE=-16) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 3, TE=-16) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 0, TE= -2) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 1, TE= -2) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 2, TE= -2) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 3, TE= -2) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 0, TE= 0) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 1, TE= 0) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 2, TE= 0) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 3, TE= 0) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 0, TE= 5) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 1, TE= 5) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 2, TE= 5) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 3, TE= 5) [QI] fc00000000000000 c00100035b007700 ==> fc00000000000000 c00100035b007700
+dquaiq (RMC= 0, TE=-16) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 1, TE=-16) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 2, TE=-16) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 3, TE=-16) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 0, TE= -2) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 1, TE= -2) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 2, TE= -2) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 3, TE= -2) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 0, TE= 0) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 1, TE= 0) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 2, TE= 0) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 3, TE= 0) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 0, TE= 5) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 1, TE= 5) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 2, TE= 5) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 3, TE= 5) [QI] 7e00000000000000 fe000000d0e0a0d0 ==> 7c00000000000000 fe000000d0e0a0d0
+dquaiq (RMC= 0, TE=-16) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] 7800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] f800000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE=-16) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE=-16) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE=-16) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE=-16) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= -2) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= -2) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= -2) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= -2) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 0) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 0) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 0) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 0) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 0, TE= 5) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 1, TE= 5) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 2, TE= 5) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+dquaiq (RMC= 3, TE= 5) [QI] f900000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+
diff --git a/none/tests/ppc64/test_dfp4.c b/none/tests/ppc64/test_dfp4.c
deleted file mode 120000
index 57c85cd..0000000
--- a/none/tests/ppc64/test_dfp4.c
+++ /dev/null
@@ -1 +0,0 @@
-../../../none/tests/ppc32/test_dfp4.c
\ No newline at end of file
diff --git a/none/tests/ppc64/test_dfp4.c b/none/tests/ppc64/test_dfp4.c
new file mode 100644
index 0000000..54ffbb0
--- /dev/null
+++ b/none/tests/ppc64/test_dfp4.c
@@ -0,0 +1,643 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#if defined(HAS_DFP)
+
+typedef union stuff {
+ _Decimal64 dec_val;
+ _Decimal128 dec_val128;
+ unsigned long long u64_val;
+ struct {
+#if defined(VGP_ppc64le_linux)
+ unsigned long long vall;
+ unsigned long long valu;
+#else
+ unsigned long long valu;
+ unsigned long long vall;
+#endif
+ } u128;
+} dfp_val_t;
+
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+
+// The assembly-level instructions being tested
+
+/* In _test_dtstdc[q], DCM can be one of 6 possible data classes, numbered 0-5.
+ * In reality, DCM is a 6-bit mask field. We just test the individual values
+ * and assume that masking multiple values would work OK.
+ * BF is the condition register bit field which can range from 0-7. But for
+ * testing purposes, we only use BF values of '0' and '5'.
+ */
+static void _test_dtstdc(int BF, int DCM, dfp_val_t *val1, dfp_val_t *x1 __attribute__((unused)))
+{
+ _Decimal64 f14 = val1->dec_val;
+ if (DCM < 0 || DCM > 5 || !(BF == 0 || BF == 5)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DCM);
+ return;
+ }
+ switch (DCM) {
+ case 0:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 1" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 1" : : "f" (f14));
+ break;
+ case 1:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 2" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 2" : : "f" (f14));
+ break;
+ case 2:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 4" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 4" : : "f" (f14));
+ break;
+ case 3:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 8" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 8" : : "f" (f14));
+ break;
+ case 4:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 16" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 16" : : "f" (f14));
+ break;
+ case 5:
+ if (BF)
+ __asm__ __volatile__ ("dtstdc 5, %0, 32" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdc 0, %0, 32" : : "f" (f14));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dtstdcq(int BF, int DCM, dfp_val_t *val1, dfp_val_t *x1 __attribute__((unused)))
+{
+ _Decimal128 f14 = val1->dec_val128;
+ if (DCM < 0 || DCM > 5 || !(BF == 0 || BF == 5)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DCM);
+ return;
+ }
+ switch (DCM) {
+ case 0:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 1" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 1" : : "f" (f14));
+ break;
+ case 1:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 2" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 2" : : "f" (f14));
+ break;
+ case 2:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 4" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 4" : : "f" (f14));
+ break;
+ case 3:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 8" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 8" : : "f" (f14));
+ break;
+ case 4:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 16" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 16" : : "f" (f14));
+ break;
+ case 5:
+ if (BF)
+ __asm__ __volatile__ ("dtstdcq 5, %0, 32" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdcq 0, %0, 32" : : "f" (f14));
+ break;
+ default:
+ break;
+ }
+}
+
+/* In _test_dtstdg[q], DGM can be one of 6 possible data groups, numbered 0-5.
+ * In reality, DGM is a 6-bit mask field. We just test the individual values
+ * and assume that masking multiple values would work OK.
+ * BF is the condition register bit field which can range from 0-7. But for
+ * testing purposes, we only use BF values of '0' and '5'.
+ */
+static void _test_dtstdg(int BF, int DGM, dfp_val_t *val1, dfp_val_t *x1 __attribute__((unused)))
+{
+ _Decimal64 f14 = val1->dec_val;
+ if (DGM < 0 || DGM > 5 || !(BF == 0 || BF == 5)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DGM);
+ return;
+ }
+ switch (DGM) {
+ case 0:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 1" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 1" : : "f" (f14));
+ break;
+ case 1:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 2" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 2" : : "f" (f14));
+ break;
+ case 2:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 4" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 4" : : "f" (f14));
+ break;
+ case 3:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 8" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 8" : : "f" (f14));
+ break;
+ case 4:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 16" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 16" : : "f" (f14));
+ break;
+ case 5:
+ if (BF)
+ __asm__ __volatile__ ("dtstdg 5, %0, 32" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdg 0, %0, 32" : : "f" (f14));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dtstdgq(int BF, int DGM, dfp_val_t *val1, dfp_val_t *x1 __attribute__((unused)))
+{
+ _Decimal128 f14 = val1->dec_val128;
+ if (DGM < 0 || DGM > 5 || !(BF == 0 || BF == 5)) {
+ fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DGM);
+ return;
+ }
+ switch (DGM) {
+ case 0:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 1" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 1" : : "f" (f14));
+ break;
+ case 1:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 2" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 2" : : "f" (f14));
+ break;
+ case 2:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 4" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 4" : : "f" (f14));
+ break;
+ case 3:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 8" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 8" : : "f" (f14));
+ break;
+ case 4:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 16" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 16" : : "f" (f14));
+ break;
+ case 5:
+ if (BF)
+ __asm__ __volatile__ ("dtstdgq 5, %0, 32" : : "f" (f14));
+ else
+ __asm__ __volatile__ ("dtstdgq 0, %0, 32" : : "f" (f14));
+ break;
+ default:
+ break;
+ }
+}
+
+/* In _test_dtstex[q], BF is the condition register bit field indicating the
+ * CR field in which the result of the test should be placed. BF can range
+ * from 0-7, but for testing purposes, we only use BF values of '4' and '7'.
+ */
+static void
+_test_dtstex(int BF, int x __attribute__((unused)), dfp_val_t *val1, dfp_val_t *val2)
+{
+ _Decimal64 f14 = val1->dec_val;
+ _Decimal64 f16 = val2->dec_val;
+ if (!(BF == 4 || BF == 7)) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 4:
+ __asm__ __volatile__ ("dtstex 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dtstex 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+static void _test_dtstexq(int BF, int x __attribute__((unused)), dfp_val_t *val1, dfp_val_t *val2)
+{
+ _Decimal128 f14 = val1->dec_val128;
+ _Decimal128 f16 = val2->dec_val128;
+ if (!(BF == 4 || BF == 7)) {
+ fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
+ return;
+ }
+ switch (BF) {
+ case 4:
+ __asm__ __volatile__ ("dtstexq 4, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ case 7:
+ __asm__ __volatile__ ("dtstexq 7, %0, %1" : : "f" (f14),"f" (f16));
+ break;
+ default:
+ break;
+ }
+}
+
+
+
+typedef void (*test_funcp_t)(int a, int b, dfp_val_t *val1, dfp_val_t *val2);
+typedef void (*test_driver_func_t)(void);
+typedef struct test_table
+{
+ test_driver_func_t test_category;
+ char * name;
+} test_table_t;
+
+/*
+ * 345.0DD (0x2207c00000000000 0xe50)
+ * 1.2300e+5DD (0x2207c00000000000 0x14c000)
+ * -16.0DD (0xa207c00000000000 0xe0)
+ * 0.00189DD (0x2206c00000000000 0xcf)
+ * -4.1235DD (0xa205c00000000000 0x10a395bcf)
+ * 9.8399e+20DD (0x2209400000000000 0x253f1f534acdd4)
+ * 0DD (0x2208000000000000 0x0)
+ * 0DD (0x2208000000000000 0x0)
+ * infDD (0x7800000000000000 0x0)
+ * nanDD (0x7c00000000000000 0x0
+ */
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2207c00000000000ULL, 0x000000000014c000ULL,
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // huge number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// huge number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+// Both Long and Quad arrays of DFP values should have the same length, so it
+// doesn't matter which array I use for calculating the following #define.
+#define NUM_DFP_VALS (sizeof(dfp64_vals)/8)
+
+typedef struct dfp_test_args {
+ int fra_idx;
+ int frb_idx;
+} dfp_test_args_t;
+
+
+// Index pairs from dfp64_vals array to be used with dfp_two_arg_tests
+static dfp_test_args_t dfp_2args_x1[] = {
+ {0, 1},
+ {2, 1},
+ {4, 3},
+ {6, 0},
+ {2, 4},
+ {5, 1},
+ {5, 2},
+ {7, 1},
+ {7, 2},
+ {8, 0},
+ {8, 1},
+ {8, 2},
+ {7, 8},
+ {12, 14},
+ {12, 1},
+ {12, 13},
+ {12, 12},
+ {12, 11},
+ {11, 14},
+ {11, 0},
+ {11, 13},
+ {11, 11},
+ {14, 14},
+ {14, 3},
+ {14, 15},
+};
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_test
+{
+ test_funcp_t test_func;
+ const char * name;
+ dfp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ const char * op;
+} dfp_test_t;
+
+typedef struct dfp_one_arg_test
+{
+ test_funcp_t test_func;
+ const char * name;
+ precision_type_t precision;
+ const char * op;
+} dfp_one_arg_test_t;
+
+
+
+static dfp_one_arg_test_t
+dfp_ClassAndGroupTest_tests[] = {
+ { &_test_dtstdc, "dtstdc", LONG_TEST, "[tCls]"},
+ { &_test_dtstdcq, "dtstdcq", QUAD_TEST, "[tCls]"},
+ { &_test_dtstdg, "dtstdg", LONG_TEST, "[tGrp]"},
+ { &_test_dtstdgq, "dtstdgq", QUAD_TEST, "[tGrp]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_ClassAndGroupTest_ops(void)
+{
+ test_funcp_t func;
+ dfp_val_t test_val, dummy;
+
+ int k = 0;
+
+ while ((func = dfp_ClassAndGroupTest_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_test_t test_def = dfp_ClassAndGroupTest_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int data_class_OR_group, BF = 0;
+ Bool repeat = True;
+
+ if (test_def.precision == LONG_TEST) {
+ test_val.u64_val = dfp64_vals[i];
+ } else {
+ test_val.u128.valu = dfp128_vals[i * 2];
+ test_val.u128.vall = dfp128_vals[(i * 2) + 1];
+ }
+
+again:
+ for (data_class_OR_group = 0; data_class_OR_group < 6; data_class_OR_group++) {
+ unsigned int condreg;
+ unsigned int flags;
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+
+ /* There is an ABI change in how 128 bit arguments are aligned
+ * with GCC 5.0. The compiler generates a "note" about this
+ * starting with GCC 4.8. To avoid generating the "note", pass
+ * the address of the 128-bit arguments rather then the value.
+ */
+ (*func)(BF, data_class_OR_group, &test_val, &dummy);
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+ printf("%s (DC/DG=%d) %s", test_def.name, data_class_OR_group,
+ test_def.op);
+ if (test_def.precision == QUAD_TEST) {
+ printf("%016llx %016llx", test_val.u128.valu, test_val.u128.vall);
+ } else {
+ printf("%016llx", test_val.u64_val);
+ }
+
+ //%016llx
+ printf(" => %x (BF=%d)\n", condreg, BF);
+ }
+ if (repeat) {
+ repeat = False;
+ BF = 5;
+ goto again;
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_test_t
+dfp_ExpTest_tests[] = {
+ { &_test_dtstex, "dtstex", dfp_2args_x1, 25, LONG_TEST, "[tExp]"},
+ { &_test_dtstexq, "dtstexq", dfp_2args_x1, 25, QUAD_TEST, "[tExp]"},
+ { NULL, NULL, NULL, 0, 0, NULL}
+};
+
+
+static void test_dfp_ExpTest_ops(void)
+{
+ dfp_val_t test_val1, test_val2;
+ test_funcp_t func;
+ int k = 0;
+
+ while ((func = dfp_ExpTest_tests[k].test_func)) {
+ /* BF is a 3-bit instruction field that indicates the CR field in which the
+ * result of the test should be placed. We won't iterate through all
+ * 8 possible BF values since storing compare results to a given field is
+ * a well-tested mechanism in VEX. But we will test two BF values, just as
+ * a sniff-test.
+ */
+ int i, repeat = 1, BF = 4;
+ dfp_test_t test_def = dfp_ExpTest_tests[k];
+
+again:
+ for (i = 0; i < test_def.num_tests; i++) {
+ unsigned int condreg;
+ unsigned int flags;
+
+ if (test_def.precision == LONG_TEST) {
+ test_val1.u64_val = dfp64_vals[test_def.targs[i].fra_idx];
+ test_val2.u64_val = dfp64_vals[test_def.targs[i].frb_idx];
+ } else {
+ test_val1.u128.valu = dfp128_vals[test_def.targs[i].fra_idx * 2];
+ test_val1.u128.vall = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
+ test_val2.u128.valu = dfp128_vals[test_def.targs[i].frb_idx * 2];
+ test_val2.u128.vall = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
+ }
+
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ /* There is an ABI change in how 128 bit arguments are aligned
+ * with GCC 5.0. The compiler generates a "note" about this
+ * starting with GCC 4.8. To avoid generating the "note", pass
+ * the address of the 128-bit arguments rather then the value.
+ */
+ (*func)(BF, 0, &test_val1, &test_val2);
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+ printf("%s ", test_def.name);
+ if (test_def.precision == LONG_TEST) {
+ printf("%016llx %s %016llx ",
+ test_val1.u64_val, test_def.op, test_val2.u64_val);
+ } else {
+ printf("%016llx %016llx %s %016llx %016llx ",
+ test_val1.u128.valu, test_val1.u128.vall, test_def.op, test_val2.u128.valu, test_val2.u128.vall);
+ }
+ printf(" => %x (BF=%d)\n", condreg, BF);
+ }
+ if (repeat) {
+ repeat = 0;
+ BF = 7;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_dfp_ExpTest_ops,
+ "Test DFP exponent test instructions"},
+ { &test_dfp_ClassAndGroupTest_ops,
+ "Test DFP class and group test instructions"},
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main() {
+#if defined(HAS_DFP)
+
+ test_table_t aTest;
+ test_driver_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/none/tests/ppc64/test_dfp4.stdout.exp b/none/tests/ppc64/test_dfp4.stdout.exp
deleted file mode 120000
index 4f5c1aa..0000000
--- a/none/tests/ppc64/test_dfp4.stdout.exp
+++ /dev/null
@@ -1 +0,0 @@
-../../../none/tests/ppc32/test_dfp4.stdout.exp
\ No newline at end of file
diff --git a/none/tests/ppc64/test_dfp4.stdout.exp b/none/tests/ppc64/test_dfp4.stdout.exp
new file mode 100644
index 0000000..253b2a5
--- /dev/null
+++ b/none/tests/ppc64/test_dfp4.stdout.exp
@@ -0,0 +1,876 @@
+Test DFP exponent test instructions
+dtstex 2234000000000e50 [tExp] 223400000014c000 => 2 (BF=4)
+dtstex a2340000000000e0 [tExp] 223400000014c000 => 2 (BF=4)
+dtstex a21400010a395bcf [tExp] 22240000000000cf => 8 (BF=4)
+dtstex 000400000089b000 [tExp] 2234000000000e50 => 8 (BF=4)
+dtstex a2340000000000e0 [tExp] a21400010a395bcf => 4 (BF=4)
+dtstex 6e4d3f1f534acdd4 [tExp] 223400000014c000 => 4 (BF=4)
+dtstex 6e4d3f1f534acdd4 [tExp] a2340000000000e0 => 4 (BF=4)
+dtstex 2238000000000000 [tExp] 223400000014c000 => 4 (BF=4)
+dtstex 2238000000000000 [tExp] a2340000000000e0 => 4 (BF=4)
+dtstex a238000000000000 [tExp] 2234000000000e50 => 4 (BF=4)
+dtstex a238000000000000 [tExp] 223400000014c000 => 4 (BF=4)
+dtstex a238000000000000 [tExp] a2340000000000e0 => 4 (BF=4)
+dtstex 2238000000000000 [tExp] a238000000000000 => 2 (BF=4)
+dtstex fc00000000000000 [tExp] f800000000000000 => 1 (BF=4)
+dtstex fc00000000000000 [tExp] 223400000014c000 => 1 (BF=4)
+dtstex fc00000000000000 [tExp] 7800000000000000 => 1 (BF=4)
+dtstex fc00000000000000 [tExp] fc00000000000000 => 2 (BF=4)
+dtstex fc00000000000000 [tExp] fe000000d0e0a0d0 => 2 (BF=4)
+dtstex fe000000d0e0a0d0 [tExp] f800000000000000 => 1 (BF=4)
+dtstex fe000000d0e0a0d0 [tExp] 2234000000000e50 => 1 (BF=4)
+dtstex fe000000d0e0a0d0 [tExp] 7800000000000000 => 1 (BF=4)
+dtstex fe000000d0e0a0d0 [tExp] fe000000d0e0a0d0 => 2 (BF=4)
+dtstex f800000000000000 [tExp] f800000000000000 => 2 (BF=4)
+dtstex f800000000000000 [tExp] 22240000000000cf => 1 (BF=4)
+dtstex f800000000000000 [tExp] 7a34000000000000 => 2 (BF=4)
+dtstex 2234000000000e50 [tExp] 223400000014c000 => 2 (BF=7)
+dtstex a2340000000000e0 [tExp] 223400000014c000 => 2 (BF=7)
+dtstex a21400010a395bcf [tExp] 22240000000000cf => 8 (BF=7)
+dtstex 000400000089b000 [tExp] 2234000000000e50 => 8 (BF=7)
+dtstex a2340000000000e0 [tExp] a21400010a395bcf => 4 (BF=7)
+dtstex 6e4d3f1f534acdd4 [tExp] 223400000014c000 => 4 (BF=7)
+dtstex 6e4d3f1f534acdd4 [tExp] a2340000000000e0 => 4 (BF=7)
+dtstex 2238000000000000 [tExp] 223400000014c000 => 4 (BF=7)
+dtstex 2238000000000000 [tExp] a2340000000000e0 => 4 (BF=7)
+dtstex a238000000000000 [tExp] 2234000000000e50 => 4 (BF=7)
+dtstex a238000000000000 [tExp] 223400000014c000 => 4 (BF=7)
+dtstex a238000000000000 [tExp] a2340000000000e0 => 4 (BF=7)
+dtstex 2238000000000000 [tExp] a238000000000000 => 2 (BF=7)
+dtstex fc00000000000000 [tExp] f800000000000000 => 1 (BF=7)
+dtstex fc00000000000000 [tExp] 223400000014c000 => 1 (BF=7)
+dtstex fc00000000000000 [tExp] 7800000000000000 => 1 (BF=7)
+dtstex fc00000000000000 [tExp] fc00000000000000 => 2 (BF=7)
+dtstex fc00000000000000 [tExp] fe000000d0e0a0d0 => 2 (BF=7)
+dtstex fe000000d0e0a0d0 [tExp] f800000000000000 => 1 (BF=7)
+dtstex fe000000d0e0a0d0 [tExp] 2234000000000e50 => 1 (BF=7)
+dtstex fe000000d0e0a0d0 [tExp] 7800000000000000 => 1 (BF=7)
+dtstex fe000000d0e0a0d0 [tExp] fe000000d0e0a0d0 => 2 (BF=7)
+dtstex f800000000000000 [tExp] f800000000000000 => 2 (BF=7)
+dtstex f800000000000000 [tExp] 22240000000000cf => 1 (BF=7)
+dtstex f800000000000000 [tExp] 7a34000000000000 => 2 (BF=7)
+
+dtstexq 2207c00000000000 0000000000000e50 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=4)
+dtstexq a207c00000000000 00000000000000e0 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=4)
+dtstexq a205c00000000000 000000010a395bcf [tExp] 2206c00000000000 00000000000000cf => 8 (BF=4)
+dtstexq 000400000089b000 0a6000d000000049 [tExp] 2207c00000000000 0000000000000e50 => 8 (BF=4)
+dtstexq a207c00000000000 00000000000000e0 [tExp] a205c00000000000 000000010a395bcf => 4 (BF=4)
+dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] 2207c00000000000 000000000014c000 => 8 (BF=4)
+dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] a207c00000000000 00000000000000e0 => 8 (BF=4)
+dtstexq 2208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=4)
+dtstexq 2208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=4)
+dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 0000000000000e50 => 4 (BF=4)
+dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=4)
+dtstexq a208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=4)
+dtstexq 2208000000000000 0000000000000000 [tExp] a208000000000000 0000000000000000 => 2 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] f800000000000000 0000000000000000 => 1 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 2207c00000000000 000000000014c000 => 1 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7800000000000000 0000000000000000 => 1 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7e00000000000000 fe000000d0e0a0d0 => 2 (BF=4)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=4)
+dtstexq fc00000000000000 c00100035b007700 [tExp] f800000000000000 0000000000000000 => 1 (BF=4)
+dtstexq fc00000000000000 c00100035b007700 [tExp] 2207c00000000000 0000000000000e50 => 1 (BF=4)
+dtstexq fc00000000000000 c00100035b007700 [tExp] 7800000000000000 0000000000000000 => 1 (BF=4)
+dtstexq fc00000000000000 c00100035b007700 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=4)
+dtstexq f800000000000000 0000000000000000 [tExp] f800000000000000 0000000000000000 => 2 (BF=4)
+dtstexq f800000000000000 0000000000000000 [tExp] 2206c00000000000 00000000000000cf => 1 (BF=4)
+dtstexq f800000000000000 0000000000000000 [tExp] f900000000000000 0000000000000000 => 2 (BF=4)
+dtstexq 2207c00000000000 0000000000000e50 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=7)
+dtstexq a207c00000000000 00000000000000e0 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=7)
+dtstexq a205c00000000000 000000010a395bcf [tExp] 2206c00000000000 00000000000000cf => 8 (BF=7)
+dtstexq 000400000089b000 0a6000d000000049 [tExp] 2207c00000000000 0000000000000e50 => 8 (BF=7)
+dtstexq a207c00000000000 00000000000000e0 [tExp] a205c00000000000 000000010a395bcf => 4 (BF=7)
+dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] 2207c00000000000 000000000014c000 => 8 (BF=7)
+dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] a207c00000000000 00000000000000e0 => 8 (BF=7)
+dtstexq 2208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=7)
+dtstexq 2208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=7)
+dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 0000000000000e50 => 4 (BF=7)
+dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=7)
+dtstexq a208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=7)
+dtstexq 2208000000000000 0000000000000000 [tExp] a208000000000000 0000000000000000 => 2 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] f800000000000000 0000000000000000 => 1 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 2207c00000000000 000000000014c000 => 1 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7800000000000000 0000000000000000 => 1 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7e00000000000000 fe000000d0e0a0d0 => 2 (BF=7)
+dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=7)
+dtstexq fc00000000000000 c00100035b007700 [tExp] f800000000000000 0000000000000000 => 1 (BF=7)
+dtstexq fc00000000000000 c00100035b007700 [tExp] 2207c00000000000 0000000000000e50 => 1 (BF=7)
+dtstexq fc00000000000000 c00100035b007700 [tExp] 7800000000000000 0000000000000000 => 1 (BF=7)
+dtstexq fc00000000000000 c00100035b007700 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=7)
+dtstexq f800000000000000 0000000000000000 [tExp] f800000000000000 0000000000000000 => 2 (BF=7)
+dtstexq f800000000000000 0000000000000000 [tExp] 2206c00000000000 00000000000000cf => 1 (BF=7)
+dtstexq f800000000000000 0000000000000000 [tExp] f900000000000000 0000000000000000 => 2 (BF=7)
+
+Test DFP class and group test instructions
+dtstdc (DC/DG=0) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]2234000000000e50 => 2 (BF=0)
+dtstdc (DC/DG=4) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]2234000000000e50 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]2234000000000e50 => 2 (BF=5)
+dtstdc (DC/DG=4) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]2234000000000e50 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]223400000014c000 => 2 (BF=0)
+dtstdc (DC/DG=4) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]223400000014c000 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]223400000014c000 => 2 (BF=5)
+dtstdc (DC/DG=4) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]223400000014c000 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]a2340000000000e0 => a (BF=0)
+dtstdc (DC/DG=4) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]a2340000000000e0 => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]a2340000000000e0 => a (BF=5)
+dtstdc (DC/DG=4) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]a2340000000000e0 => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]22240000000000cf => 2 (BF=0)
+dtstdc (DC/DG=4) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]22240000000000cf => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]22240000000000cf => 2 (BF=5)
+dtstdc (DC/DG=4) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]22240000000000cf => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]a21400010a395bcf => a (BF=0)
+dtstdc (DC/DG=4) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]a21400010a395bcf => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]a21400010a395bcf => a (BF=5)
+dtstdc (DC/DG=4) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]a21400010a395bcf => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]6e4d3f1f534acdd4 => 2 (BF=0)
+dtstdc (DC/DG=4) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]6e4d3f1f534acdd4 => 2 (BF=5)
+dtstdc (DC/DG=4) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]000400000089b000 => 2 (BF=0)
+dtstdc (DC/DG=5) [tCls]000400000089b000 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]000400000089b000 => 2 (BF=5)
+dtstdc (DC/DG=5) [tCls]000400000089b000 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]2238000000000000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]2238000000000000 => 2 (BF=0)
+dtstdc (DC/DG=0) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]2238000000000000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]2238000000000000 => 2 (BF=5)
+dtstdc (DC/DG=0) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=4) [tCls]a238000000000000 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]a238000000000000 => a (BF=0)
+dtstdc (DC/DG=0) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=4) [tCls]a238000000000000 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]a238000000000000 => a (BF=5)
+dtstdc (DC/DG=0) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]4248000000000000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]4248000000000000 => 2 (BF=0)
+dtstdc (DC/DG=0) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]4248000000000000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]4248000000000000 => 2 (BF=5)
+dtstdc (DC/DG=0) [tCls]7e34000000000111 => 2 (BF=0)
+dtstdc (DC/DG=1) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=3) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]7e34000000000111 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]7e34000000000111 => 2 (BF=5)
+dtstdc (DC/DG=1) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=3) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]7e34000000000111 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]fe000000d0e0a0d0 => a (BF=0)
+dtstdc (DC/DG=1) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=4) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]fe000000d0e0a0d0 => a (BF=5)
+dtstdc (DC/DG=1) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=4) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]fc00000000000000 => a (BF=0)
+dtstdc (DC/DG=2) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=3) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=4) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]fc00000000000000 => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]fc00000000000000 => a (BF=5)
+dtstdc (DC/DG=2) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=3) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=4) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]fc00000000000000 => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]7800000000000000 => 2 (BF=0)
+dtstdc (DC/DG=3) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]7800000000000000 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]7800000000000000 => 2 (BF=5)
+dtstdc (DC/DG=3) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]7800000000000000 => 0 (BF=5)
+dtstdc (DC/DG=0) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=1) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=2) [tCls]f800000000000000 => a (BF=0)
+dtstdc (DC/DG=3) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=4) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=5) [tCls]f800000000000000 => 8 (BF=0)
+dtstdc (DC/DG=0) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=1) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=2) [tCls]f800000000000000 => a (BF=5)
+dtstdc (DC/DG=3) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=4) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=5) [tCls]f800000000000000 => 8 (BF=5)
+dtstdc (DC/DG=0) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=1) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=2) [tCls]7a34000000000000 => 2 (BF=0)
+dtstdc (DC/DG=3) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=4) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=5) [tCls]7a34000000000000 => 0 (BF=0)
+dtstdc (DC/DG=0) [tCls]7a34000000000000 => 0 (BF=5)
+dtstdc (DC/DG=1) [tCls]7a34000000000000 => 0 (BF=5)
+dtstdc (DC/DG=2) [tCls]7a34000000000000 => 2 (BF=5)
+dtstdc (DC/DG=3) [tCls]7a34000000000000 => 0 (BF=5)
+dtstdc (DC/DG=4) [tCls]7a34000000000000 => 0 (BF=5)
+dtstdc (DC/DG=5) [tCls]7a34000000000000 => 0 (BF=5)
+
+dtstdcq (DC/DG=0) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]2207c00000000000 0000000000000e50 => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]2207c00000000000 0000000000000e50 => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]2207c00000000000 000000000014c000 => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]2207c00000000000 000000000014c000 => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]a207c00000000000 00000000000000e0 => a (BF=0)
+dtstdcq (DC/DG=4) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]a207c00000000000 00000000000000e0 => a (BF=5)
+dtstdcq (DC/DG=4) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdcq (DC/DG=0) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]2206c00000000000 00000000000000cf => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]2206c00000000000 00000000000000cf => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]a205c00000000000 000000010a395bcf => a (BF=0)
+dtstdcq (DC/DG=4) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]a205c00000000000 000000010a395bcf => a (BF=5)
+dtstdcq (DC/DG=4) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdcq (DC/DG=0) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]6209400000fd0000 00253f1f534acdd4 => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]6209400000fd0000 00253f1f534acdd4 => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]000400000089b000 0a6000d000000049 => 2 (BF=0)
+dtstdcq (DC/DG=4) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]000400000089b000 0a6000d000000049 => 2 (BF=5)
+dtstdcq (DC/DG=4) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=4) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]2208000000000000 0000000000000000 => 2 (BF=0)
+dtstdcq (DC/DG=0) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=4) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]2208000000000000 0000000000000000 => 2 (BF=5)
+dtstdcq (DC/DG=0) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]a208000000000000 0000000000000000 => a (BF=0)
+dtstdcq (DC/DG=0) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]a208000000000000 0000000000000000 => a (BF=5)
+dtstdcq (DC/DG=0) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]a248000000000000 0000000000000000 => a (BF=0)
+dtstdcq (DC/DG=0) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]a248000000000000 0000000000000000 => a (BF=5)
+dtstdcq (DC/DG=0) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]7c00000000000000 0000000000000000 => 2 (BF=0)
+dtstdcq (DC/DG=2) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=4) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]7c00000000000000 0000000000000000 => 2 (BF=5)
+dtstdcq (DC/DG=2) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=4) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]fc00000000000000 c00100035b007700 => a (BF=0)
+dtstdcq (DC/DG=2) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=3) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]fc00000000000000 c00100035b007700 => a (BF=5)
+dtstdcq (DC/DG=2) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=3) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdcq (DC/DG=0) [tCls]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=0)
+dtstdcq (DC/DG=1) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=3) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=4) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=5)
+dtstdcq (DC/DG=1) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=3) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=4) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=1) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=2) [tCls]7800000000000000 0000000000000000 => 2 (BF=0)
+dtstdcq (DC/DG=3) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=4) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=5) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdcq (DC/DG=0) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=1) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=2) [tCls]7800000000000000 0000000000000000 => 2 (BF=5)
+dtstdcq (DC/DG=3) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=4) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=5) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdcq (DC/DG=0) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]f800000000000000 0000000000000000 => a (BF=0)
+dtstdcq (DC/DG=3) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]f800000000000000 0000000000000000 => a (BF=5)
+dtstdcq (DC/DG=3) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=0) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=1) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=2) [tCls]f900000000000000 0000000000000000 => a (BF=0)
+dtstdcq (DC/DG=3) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=4) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=5) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdcq (DC/DG=0) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=1) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=2) [tCls]f900000000000000 0000000000000000 => a (BF=5)
+dtstdcq (DC/DG=3) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=4) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdcq (DC/DG=5) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
+
+dtstdg (DC/DG=0) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]2234000000000e50 => 2 (BF=0)
+dtstdg (DC/DG=3) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]2234000000000e50 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]2234000000000e50 => 2 (BF=5)
+dtstdg (DC/DG=3) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]2234000000000e50 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]223400000014c000 => 2 (BF=0)
+dtstdg (DC/DG=3) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]223400000014c000 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]223400000014c000 => 2 (BF=5)
+dtstdg (DC/DG=3) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]223400000014c000 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=1) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]a2340000000000e0 => a (BF=0)
+dtstdg (DC/DG=3) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]a2340000000000e0 => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=1) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]a2340000000000e0 => a (BF=5)
+dtstdg (DC/DG=3) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]a2340000000000e0 => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]22240000000000cf => 2 (BF=0)
+dtstdg (DC/DG=3) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]22240000000000cf => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]22240000000000cf => 2 (BF=5)
+dtstdg (DC/DG=3) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]22240000000000cf => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=1) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]a21400010a395bcf => a (BF=0)
+dtstdg (DC/DG=3) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]a21400010a395bcf => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=1) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]a21400010a395bcf => a (BF=5)
+dtstdg (DC/DG=3) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]a21400010a395bcf => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]6e4d3f1f534acdd4 => 2 (BF=0)
+dtstdg (DC/DG=2) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]6e4d3f1f534acdd4 => 2 (BF=5)
+dtstdg (DC/DG=2) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]000400000089b000 => 2 (BF=0)
+dtstdg (DC/DG=4) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]000400000089b000 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]000400000089b000 => 2 (BF=5)
+dtstdg (DC/DG=4) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]000400000089b000 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]2238000000000000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]2238000000000000 => 2 (BF=0)
+dtstdg (DC/DG=0) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]2238000000000000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]2238000000000000 => 2 (BF=5)
+dtstdg (DC/DG=0) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=1) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=3) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]a238000000000000 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]a238000000000000 => a (BF=0)
+dtstdg (DC/DG=0) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=1) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=3) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]a238000000000000 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]a238000000000000 => a (BF=5)
+dtstdg (DC/DG=0) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=1) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]4248000000000000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]4248000000000000 => 2 (BF=0)
+dtstdg (DC/DG=0) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=1) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]4248000000000000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]4248000000000000 => 2 (BF=5)
+dtstdg (DC/DG=0) [tGrp]7e34000000000111 => 2 (BF=0)
+dtstdg (DC/DG=1) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]7e34000000000111 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]7e34000000000111 => 2 (BF=5)
+dtstdg (DC/DG=1) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]7e34000000000111 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]fe000000d0e0a0d0 => a (BF=0)
+dtstdg (DC/DG=1) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=3) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]fe000000d0e0a0d0 => a (BF=5)
+dtstdg (DC/DG=1) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=3) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]fc00000000000000 => a (BF=0)
+dtstdg (DC/DG=1) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=3) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]fc00000000000000 => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]fc00000000000000 => a (BF=5)
+dtstdg (DC/DG=1) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=3) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]fc00000000000000 => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]7800000000000000 => 2 (BF=0)
+dtstdg (DC/DG=1) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]7800000000000000 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]7800000000000000 => 2 (BF=5)
+dtstdg (DC/DG=1) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]7800000000000000 => 0 (BF=5)
+dtstdg (DC/DG=0) [tGrp]f800000000000000 => a (BF=0)
+dtstdg (DC/DG=1) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=2) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=3) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=4) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=5) [tGrp]f800000000000000 => 8 (BF=0)
+dtstdg (DC/DG=0) [tGrp]f800000000000000 => a (BF=5)
+dtstdg (DC/DG=1) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=2) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=3) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=4) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=5) [tGrp]f800000000000000 => 8 (BF=5)
+dtstdg (DC/DG=0) [tGrp]7a34000000000000 => 2 (BF=0)
+dtstdg (DC/DG=1) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=2) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=3) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=4) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=5) [tGrp]7a34000000000000 => 0 (BF=0)
+dtstdg (DC/DG=0) [tGrp]7a34000000000000 => 2 (BF=5)
+dtstdg (DC/DG=1) [tGrp]7a34000000000000 => 0 (BF=5)
+dtstdg (DC/DG=2) [tGrp]7a34000000000000 => 0 (BF=5)
+dtstdg (DC/DG=3) [tGrp]7a34000000000000 => 0 (BF=5)
+dtstdg (DC/DG=4) [tGrp]7a34000000000000 => 0 (BF=5)
+dtstdg (DC/DG=5) [tGrp]7a34000000000000 => 0 (BF=5)
+
+dtstdgq (DC/DG=0) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]2207c00000000000 0000000000000e50 => 2 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]2207c00000000000 0000000000000e50 => 2 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]2207c00000000000 000000000014c000 => 2 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]2207c00000000000 000000000014c000 => 2 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]a207c00000000000 00000000000000e0 => a (BF=0)
+dtstdgq (DC/DG=3) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]a207c00000000000 00000000000000e0 => a (BF=5)
+dtstdgq (DC/DG=3) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]2206c00000000000 00000000000000cf => 2 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]2206c00000000000 00000000000000cf => 2 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]a205c00000000000 000000010a395bcf => a (BF=0)
+dtstdgq (DC/DG=3) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]a205c00000000000 000000010a395bcf => a (BF=5)
+dtstdgq (DC/DG=3) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]6209400000fd0000 00253f1f534acdd4 => 2 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]6209400000fd0000 00253f1f534acdd4 => 2 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]000400000089b000 0a6000d000000049 => 2 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]000400000089b000 0a6000d000000049 => 2 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]2208000000000000 0000000000000000 => 2 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]2208000000000000 0000000000000000 => 2 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]a208000000000000 0000000000000000 => a (BF=0)
+dtstdgq (DC/DG=0) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]a208000000000000 0000000000000000 => a (BF=5)
+dtstdgq (DC/DG=0) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]a248000000000000 0000000000000000 => a (BF=0)
+dtstdgq (DC/DG=0) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]a248000000000000 0000000000000000 => a (BF=5)
+dtstdgq (DC/DG=0) [tGrp]7c00000000000000 0000000000000000 => 2 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]7c00000000000000 0000000000000000 => 2 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]fc00000000000000 c00100035b007700 => a (BF=0)
+dtstdgq (DC/DG=1) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]fc00000000000000 c00100035b007700 => a (BF=5)
+dtstdgq (DC/DG=1) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]7800000000000000 0000000000000000 => 2 (BF=0)
+dtstdgq (DC/DG=1) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]7800000000000000 0000000000000000 => 2 (BF=5)
+dtstdgq (DC/DG=1) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]f800000000000000 0000000000000000 => a (BF=0)
+dtstdgq (DC/DG=1) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]f800000000000000 0000000000000000 => a (BF=5)
+dtstdgq (DC/DG=1) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=0) [tGrp]f900000000000000 0000000000000000 => a (BF=0)
+dtstdgq (DC/DG=1) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=2) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=3) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=4) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=5) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
+dtstdgq (DC/DG=0) [tGrp]f900000000000000 0000000000000000 => a (BF=5)
+dtstdgq (DC/DG=1) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=2) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=3) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=4) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+dtstdgq (DC/DG=5) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
+
diff --git a/none/tests/ppc64/test_dfp5.c b/none/tests/ppc64/test_dfp5.c
deleted file mode 120000
index ae52602..0000000
--- a/none/tests/ppc64/test_dfp5.c
+++ /dev/null
@@ -1 +0,0 @@
-../../../none/tests/ppc32/test_dfp5.c
\ No newline at end of file
diff --git a/none/tests/ppc64/test_dfp5.c b/none/tests/ppc64/test_dfp5.c
new file mode 100644
index 0000000..b00573f
--- /dev/null
+++ b/none/tests/ppc64/test_dfp5.c
@@ -0,0 +1,612 @@
+/* Copyright (C) 2012 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#if defined(HAS_DFP)
+
+typedef union stuff {
+ _Decimal64 dec_val;
+ _Decimal128 dec_val128;
+ unsigned long long u64_val;
+ struct {
+#if defined(VGP_ppc64le_linux)
+ unsigned long long vall;
+ unsigned long long valu;
+#else
+ unsigned long long valu;
+ unsigned long long vall;
+#endif
+ } u128;
+} dfp_val_t;
+
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+#define GET_FPSCR(_arg) \
+ __asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
+
+#define SET_FPSCR_DRN \
+ __asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif /* __powerpc64__ */
+
+enum BF_vals { BF_val1 = 0, BF_val2 = 1, BF_val3 =6};
+
+// The assembly-level instructions being tested
+static void _test_dtstsf(unsigned int BF, unsigned int ref_sig, dfp_val_t *valB)
+{
+ _Decimal64 f16 = valB->dec_val;
+ register HWord_t r14 __asm__ ("r14");
+ double f14;
+ r14 = (HWord_t)&ref_sig;
+
+ __asm __volatile__ ("lfiwax %0, 0, %1" : "=f" (f14): "r" (r14));
+ switch (BF) {
+ case BF_val1:
+ __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val1), "f" (f14), "f" (f16));
+ break;
+ case BF_val2:
+ __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val2), "f" (f14), "f" (f16));
+ break;
+ case BF_val3:
+ __asm__ __volatile__ ("dtstsf %0, %1, %2" : : "i" (BF_val3), "f" (f14), "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for BF\n", BF);
+ break;
+ }
+}
+
+static void _test_dtstsfq(unsigned int BF, unsigned int ref_sig, dfp_val_t *valB)
+{
+ _Decimal128 f16 = valB->dec_val128;
+ register HWord_t r14 __asm__ ("r14");
+ double f14;
+ r14 = (HWord_t)&ref_sig;
+
+ __asm __volatile__ ("lfiwax %0, 0, %1" : "=f" (f14): "r" (r14));
+ switch (BF) {
+ case BF_val1:
+ __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val1), "f" (f14), "f" (f16));
+ break;
+ case BF_val2:
+ __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val2), "f" (f14), "f" (f16));
+ break;
+ case BF_val3:
+ __asm__ __volatile__ ("dtstsfq %0, %1, %2" : : "i" (BF_val3), "f" (f14), "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for BF\n", BF);
+ break;
+ }
+}
+
+static dfp_val_t _test_ddedpd(unsigned int SP, dfp_val_t *valB)
+{
+ _Decimal64 ret = 0;
+ dfp_val_t result;
+ _Decimal64 f16 = valB->dec_val;
+ switch (SP) {
+ case 0:
+ __asm__ __volatile__ ("ddedpd. 0, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("ddedpd. 1, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("ddedpd. 2, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("ddedpd. 3, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for SP\n", SP);
+ break;
+ }
+ result.dec_val = ret;
+ return result;
+}
+
+
+static dfp_val_t _test_ddedpdq(unsigned int SP, dfp_val_t *valB)
+{
+ _Decimal128 ret = 0;
+ dfp_val_t result;
+ _Decimal128 f16 = valB->dec_val128;
+ switch (SP) {
+ case 0:
+ __asm__ __volatile__ ("ddedpdq 0, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("ddedpdq 1, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 2:
+ __asm__ __volatile__ ("ddedpdq 2, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 3:
+ __asm__ __volatile__ ("ddedpdq 3, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for SP\n", SP);
+ break;
+ }
+ result.dec_val128 = ret;
+ return result;
+}
+
+static dfp_val_t _test_denbcd(unsigned int S, dfp_val_t *valB)
+{
+ _Decimal64 ret = 0;
+ dfp_val_t result;
+ _Decimal64 f16 = valB->dec_val;
+ switch (S) {
+ case 0:
+ __asm__ __volatile__ ("denbcd. 0, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("denbcd. 1, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for S\n", S);
+ break;
+ }
+ result.dec_val = ret;
+ return result;
+}
+
+
+static dfp_val_t _test_denbcdq(unsigned int S, dfp_val_t *valB)
+{
+ _Decimal128 ret = 0;
+ dfp_val_t result;
+ _Decimal128 f16 = valB->dec_val128;
+ switch (S) {
+ case 0:
+ __asm__ __volatile__ ("denbcdq 0, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ case 1:
+ __asm__ __volatile__ ("denbcdq 1, %0, %1" : "=f" (ret) : "f" (f16));
+ break;
+ default:
+ fprintf(stderr, "Invalid value %d for S\n", S);
+ break;
+ }
+ result.dec_val128 = ret;
+ return result;
+}
+
+
+typedef void (*test_funcp_t)(unsigned int imm, unsigned int imm2, dfp_val_t *valB);
+typedef dfp_val_t (*test_func_bcdp_t)(unsigned int imm, dfp_val_t *valB);
+typedef void (*test_driver_func_t)(void);
+typedef struct test_table
+{
+ test_driver_func_t test_category;
+ char * name;
+} test_table_t;
+
+/*
+ * 345.0DD (0x2207c00000000000 0xe50)
+ * 1.2300e+5DD (0x2207c00000000000 0x14c000)
+ * -16.0DD (0xa207c00000000000 0xe0)
+ * 0.00189DD (0x2206c00000000000 0xcf)
+ * -4.1235DD (0xa205c00000000000 0x10a395bcf)
+ * 9.8399e+20DD (0x2209400000000000 0x253f1f534acdd4)
+ * 0DD (0x2208000000000000 0x0)
+ * 0DD (0x2208000000000000 0x0)
+ * infDD (0x7800000000000000 0x0)
+ * nanDD (0x7c00000000000000 0x0
+ */
+static unsigned long long dfp128_vals[] = {
+ // Some finite numbers
+ 0x2207c00000000000ULL, 0x0000000000000e50ULL,
+ 0x2207c00000000000ULL, 0x000000000014c000ULL,
+ 0xa207c00000000000ULL, 0x00000000000000e0ULL,
+ 0x2206c00000000000ULL, 0x00000000000000cfULL,
+ 0xa205c00000000000ULL, 0x000000010a395bcfULL,
+ 0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // huge number
+ 0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
+ // flavors of zero
+ 0x2208000000000000ULL, 0x0000000000000000ULL,
+ 0xa208000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xa248000000000000ULL, 0x0000000000000000ULL,
+ // flavors of NAN
+ 0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
+ 0xfc00000000000000ULL, 0xc00100035b007700ULL,
+ 0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
+ // flavors of Infinity
+ 0x7800000000000000ULL, 0x0000000000000000ULL,
+ 0xf800000000000000ULL, 0x0000000000000000ULL, // negative
+ 0xf900000000000000ULL, 0x0000000000000000ULL
+};
+
+static unsigned long long dfp64_vals[] = {
+ // various finite numbers
+ 0x2234000000000e50ULL,
+ 0x223400000014c000ULL,
+ 0xa2340000000000e0ULL,// negative
+ 0x22240000000000cfULL,
+ 0xa21400010a395bcfULL,// negative
+ 0x6e4d3f1f534acdd4ULL,// huge number
+ 0x000400000089b000ULL,// very small number
+ // flavors of zero
+ 0x2238000000000000ULL,
+ 0xa238000000000000ULL,
+ 0x4248000000000000ULL,
+ // flavors of NAN
+ 0x7e34000000000111ULL,
+ 0xfe000000d0e0a0d0ULL,//signaling
+ 0xfc00000000000000ULL,//quiet
+ // flavors of Infinity
+ 0x7800000000000000ULL,
+ 0xf800000000000000ULL,//negative
+ 0x7a34000000000000ULL,
+};
+
+/* The bcd64_vals and bdc128_vals hold the unique results of executing
+ * the ddedpd instruction on the basic dfp64 and dfp128 array values.
+ * Executing the inverse operation (denbcd) on these values with the
+ * appropriate S (signed) value should yield values approximating the
+ * original dfp values (except being 2^4 in magnitude since the decoding
+ * operation shifted the value one hex digit to the left to make room
+ * for signedness info).
+ */
+static unsigned long long bcd64_vals[] = {
+ 0x0000000000003450ULL,
+ 0x000000000003450cULL,
+ 0x000000000003450fULL,
+ 0x0000000001230000ULL,
+ 0x000000001230000cULL,
+ 0x000000001230000fULL,
+ 0x0000000000000160ULL,
+ 0x000000000000160dULL,
+ 0x0000000000000189ULL,
+ 0x000000000000189cULL,
+ 0x000000000000189fULL,
+ 0x0000004123456789ULL,
+ 0x000004123456789dULL,
+ 0x9839871234533354ULL,
+ 0x839871234533354cULL,
+ 0x839871234533354fULL,
+ 0x0000000008864000ULL,
+ 0x000000008864000cULL,
+ 0x000000008864000fULL,
+ 0x0000000000000000ULL,
+ 0x000000000000000cULL,
+ 0x000000000000000fULL,
+ 0x000000000000000dULL,
+ 0x0000000000000211ULL,
+ 0x000000000000211cULL,
+ 0x000000000000211fULL,
+ 0x0000003882028150ULL,
+ 0x000003882028150dULL
+ };
+
+static unsigned long long bcd128_vals[] = {
+ 0x0000000000000000ULL, 0x0000000000003450ULL,
+ 0x0000000000000000ULL, 0x000000000003450cULL,
+ 0x0000000000000000ULL, 0x000000000003450fULL,
+ 0x0000000000000000ULL, 0x0000000001230000ULL,
+ 0x0000000000000000ULL, 0x000000001230000cULL,
+ 0x0000000000000000ULL, 0x000000001230000fULL,
+ 0x0000000000000000ULL, 0x0000000000000160ULL,
+ 0x0000000000000000ULL, 0x000000000000160dULL,
+ 0x0000000000000000ULL, 0x0000000000000189ULL,
+ 0x0000000000000000ULL, 0x000000000000189cULL,
+ 0x0000000000000000ULL, 0x000000000000189fULL,
+ 0x0000000000000000ULL, 0x0000004123456789ULL,
+ 0x0000000000000000ULL, 0x000004123456789dULL,
+ 0x0000097100000000ULL, 0x9839871234533354ULL,
+ 0x0000971000000009ULL, 0x839871234533354cULL,
+ 0x0000971000000009ULL, 0x839871234533354fULL,
+ 0x0000010954000051ULL, 0x8000640000000049ULL,
+ 0x0000109540000518ULL, 0x000640000000049cULL,
+ 0x0000109540000518ULL, 0x000640000000049fULL,
+ 0x0000000000000000ULL, 0x0000000000000000ULL,
+ 0x0000000000000000ULL, 0x000000000000000cULL,
+ 0x0000000000000000ULL, 0x000000000000000fULL,
+ 0x0000000000000000ULL, 0x000000000000000dULL,
+ 0x0000000000080000ULL, 0x0200801330811600ULL,
+ 0x0000000000800000ULL, 0x200801330811600dULL,
+ 0x0000000000088170ULL, 0x0000003882028150ULL,
+ 0x0000000000881700ULL, 0x000003882028150cULL,
+ 0x0000000000881700ULL, 0x000003882028150fULL
+};
+
+// Both Long and Quad arrays of DFP values should have the same length, so it
+// doesn't matter which array I use for calculating the following #define.
+#define NUM_DFP_VALS (sizeof(dfp64_vals)/8)
+
+typedef enum {
+ LONG_TEST,
+ QUAD_TEST
+} precision_type_t;
+
+typedef struct dfp_one_arg_test
+{
+ test_funcp_t test_func;
+ const char * name;
+ precision_type_t precision;
+ const char * op;
+} dfp_one_arg_test_t;
+
+typedef struct dfp_one_arg_bcd_test
+{
+ test_func_bcdp_t test_func;
+ const char * name;
+ precision_type_t precision;
+ const char * op;
+} dfp_one_arg_bcd_test_t;
+
+static dfp_one_arg_bcd_test_t
+dfp_test_dfp_ddedpd_tests[] = {
+ { &_test_ddedpd, "ddedpd", LONG_TEST, "[D->B]"},
+ { &_test_ddedpdq, "ddedpdq", QUAD_TEST, "[D->B]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_ddedpd_ops(void)
+{
+ test_func_bcdp_t func;
+ dfp_val_t test_val;
+
+ int k = 0;
+
+ while ((func = dfp_test_dfp_ddedpd_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_bcd_test_t test_def = dfp_test_dfp_ddedpd_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ unsigned int SP;
+
+ if (test_def.precision == LONG_TEST) {
+ test_val.u64_val = dfp64_vals[i];
+ } else {
+ test_val.u128.valu = dfp128_vals[i * 2];
+ test_val.u128.vall = dfp128_vals[(i * 2) + 1];
+ }
+
+ for (SP = 0; SP < 4; SP++) {
+ dfp_val_t result;
+
+ /* There is an ABI change in how 128 bit arguments are aligned
+ * with GCC 5.0. The compiler generates a "note" about this
+ * starting with GCC 4.8. To avoid generating the "note", pass
+ * the address of the 128-bit arguments rather then the value.
+ */
+ result = (*func)(SP, &test_val);
+ printf("%s (SP=%d) %s", test_def.name, SP, test_def.op);
+ if (test_def.precision == LONG_TEST) {
+ printf("%016llx ==> %016llx\n", test_val.u64_val, result.u64_val);
+ } else {
+ printf("%016llx %016llx ==> %016llx %016llx\n",
+ test_val.u128.valu, test_val.u128.vall,
+ result.u128.valu, result.u128.vall);
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static dfp_one_arg_bcd_test_t
+dfp_test_dfp_denbcd_tests[] = {
+ { &_test_denbcd, "denbcd", LONG_TEST, "[B->D]"},
+ { &_test_denbcdq, "denbcdq", QUAD_TEST, "[B->D]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_denbcd_ops(void)
+{
+ test_func_bcdp_t func;
+ dfp_val_t test_val;
+ int num_test_vals;
+
+ int k = 0;
+
+ while ((func = dfp_test_dfp_denbcd_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_bcd_test_t test_def = dfp_test_dfp_denbcd_tests[k];
+ if (test_def.precision == LONG_TEST)
+ num_test_vals = sizeof(bcd64_vals)/sizeof(unsigned long long);
+ else
+ num_test_vals = sizeof(bcd128_vals)/(2 * sizeof(unsigned long long));
+
+ for (i = 0; i < num_test_vals; i++) {
+ unsigned int S;
+ dfp_val_t result;
+ /* The DPD-to-BCD decodings may contain up to 3 decodings for each normal DFP
+ * value: the first is an unsigned decoding, and the other two are
+ * signed decodings, with SP[1] set to '0' and '1' respectively at decode
+ * time. But some of the results of decodings were duplicates, so they were
+ * not included in the bcd64_vals and bcd128_vals arrays.
+ *
+ * When doing the encoding operation (denbcd), we'll attempt both S=0 and
+ * S=1; one or the other should encode the BCD value to something close to
+ * its original DFP value (except being 2^4 in magnitude since the decoding
+ * operation shifted the value one hex digit to the left to make room
+ * for signedness info).
+ */
+ for (S = 0; S < 2; S++) {
+ if (test_def.precision == LONG_TEST) {
+ test_val.u64_val = bcd64_vals[i];
+ } else {
+ test_val.u128.valu = bcd128_vals[i * 2];
+ test_val.u128.vall = bcd128_vals[(i * 2) + 1];
+ }
+
+ /* There is an API change in how 128 bit arguments are aligned
+ * with GCC 5.0. The compiler generates a "note" about this
+ * starting with GCC 4.8. To avoid generating the "note", pass
+ * the address of the 128-bit arguments rather then the value.
+ */
+ result = (*func)(S, &test_val);
+ printf("%s (S=%d) %s", test_def.name, S, test_def.op);
+ if (test_def.precision == LONG_TEST) {
+ printf("%016llx ==> %016llx\n", test_val.u64_val, result.u64_val);
+ } else {
+ printf("%016llx %016llx ==> %016llx %016llx\n",
+ test_val.u128.valu, test_val.u128.vall,
+ result.u128.valu, result.u128.vall);
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static dfp_one_arg_test_t
+dfp_test_significance_tests[] = {
+ { &_test_dtstsf, "dtstsf", LONG_TEST, "[tSig]"},
+ { &_test_dtstsfq, "dtstsfq", QUAD_TEST, "[tSig]"},
+ { NULL, NULL, 0, NULL}
+};
+
+static void test_dfp_test_significance_ops(void)
+{
+ test_funcp_t func;
+ dfp_val_t test_valB;
+ int k = 0;
+ unsigned int BF_vals[] = {BF_val1, BF_val2, BF_val3};
+ unsigned int reference_sig, reference_sig_vals[] = {0U, 1U, 2U, 4U, 6U, 63U};
+ int num_reference_sig_vals = sizeof(reference_sig_vals)/sizeof(unsigned int);
+
+ while ((func = dfp_test_significance_tests[k].test_func)) {
+ int i;
+ dfp_one_arg_test_t test_def = dfp_test_significance_tests[k];
+
+ for (i = 0; i < NUM_DFP_VALS; i++) {
+ int j;
+ if (test_def.precision == LONG_TEST) {
+ test_valB.u64_val = dfp64_vals[i];
+ } else {
+ test_valB.u128.valu = dfp128_vals[i * 2];
+ test_valB.u128.vall = dfp128_vals[(i * 2) + 1];
+ }
+
+ for (j = 0; j < num_reference_sig_vals; j++) {
+ int bf_idx, BF;
+ reference_sig = reference_sig_vals[j];
+ for (bf_idx = 0; bf_idx < sizeof(BF_vals)/sizeof(unsigned int); bf_idx++) {
+ unsigned int condreg;
+ unsigned int flags;
+ BF = BF_vals[bf_idx];
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ /* There is an ABI change in how 128 bit arguments are aligned
+ * with GCC 5.0. The compiler generates a "note" about this
+ * starting with GCC 4.9. To avoid generating the "note", pass
+ * the address of the 128-bit arguments rather then the value.
+ */
+ (*func)(BF, reference_sig, &test_valB);
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+ printf("%s (ref_sig=%d) %s", test_def.name, reference_sig, test_def.op);
+ if (test_def.precision == LONG_TEST) {
+ printf("%016llx", test_valB.u64_val);
+ } else {
+ printf("%016llx %016llx", test_valB.u128.valu, test_valB.u128.vall);
+ }
+ printf(" => %x (BF=%d)\n", condreg, BF);
+ }
+ }
+ printf( "\n" );
+ }
+ k++;
+ }
+}
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_dfp_test_significance_ops,
+ "Test DFP test significance instructions"},
+ { &test_dfp_ddedpd_ops,
+ "Test DFP DPD-to-BCD instructions"},
+ { &test_dfp_denbcd_ops,
+ "Test DFP BCD-to-DPD instructions"},
+ { NULL, NULL }
+};
+#endif // HAS_DFP
+
+int main() {
+#if defined(HAS_DFP)
+
+ test_table_t aTest;
+ test_driver_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+
+#endif // HAS_DFP
+ return 0;
+}
diff --git a/none/tests/ppc64/test_dfp5.stdout.exp b/none/tests/ppc64/test_dfp5.stdout.exp
deleted file mode 120000
index 5bc4dc3..0000000
--- a/none/tests/ppc64/test_dfp5.stdout.exp
+++ /dev/null
@@ -1 +0,0 @@
-../../../none/tests/ppc32/test_dfp5.stdout.exp
\ No newline at end of file
diff --git a/none/tests/ppc64/test_dfp5.stdout.exp b/none/tests/ppc64/test_dfp5.stdout.exp
new file mode 100644
index 0000000..0085526
--- /dev/null
+++ b/none/tests/ppc64/test_dfp5.stdout.exp
@@ -0,0 +1,855 @@
+Test DFP test significance instructions
+dtstsf (ref_sig=0) [tSig]2234000000000e50 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]2234000000000e50 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]2234000000000e50 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]2234000000000e50 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]2234000000000e50 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]2234000000000e50 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]2234000000000e50 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]2234000000000e50 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]2234000000000e50 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]2234000000000e50 => 2 (BF=0)
+dtstsf (ref_sig=4) [tSig]2234000000000e50 => 2 (BF=1)
+dtstsf (ref_sig=4) [tSig]2234000000000e50 => 2 (BF=6)
+dtstsf (ref_sig=6) [tSig]2234000000000e50 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]2234000000000e50 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]2234000000000e50 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]2234000000000e50 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]2234000000000e50 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]2234000000000e50 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]223400000014c000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]223400000014c000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]223400000014c000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]223400000014c000 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]223400000014c000 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]223400000014c000 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]223400000014c000 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]223400000014c000 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]223400000014c000 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]223400000014c000 => 8 (BF=0)
+dtstsf (ref_sig=4) [tSig]223400000014c000 => 8 (BF=1)
+dtstsf (ref_sig=4) [tSig]223400000014c000 => 8 (BF=6)
+dtstsf (ref_sig=6) [tSig]223400000014c000 => 8 (BF=0)
+dtstsf (ref_sig=6) [tSig]223400000014c000 => 8 (BF=1)
+dtstsf (ref_sig=6) [tSig]223400000014c000 => 8 (BF=6)
+dtstsf (ref_sig=63) [tSig]223400000014c000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]223400000014c000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]223400000014c000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]a2340000000000e0 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]a2340000000000e0 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]a2340000000000e0 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]a2340000000000e0 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]a2340000000000e0 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]a2340000000000e0 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]a2340000000000e0 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]a2340000000000e0 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]a2340000000000e0 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]a2340000000000e0 => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]a2340000000000e0 => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]a2340000000000e0 => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]a2340000000000e0 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]a2340000000000e0 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]a2340000000000e0 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]a2340000000000e0 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]a2340000000000e0 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]a2340000000000e0 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]22240000000000cf => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]22240000000000cf => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]22240000000000cf => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]22240000000000cf => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]22240000000000cf => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]22240000000000cf => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]22240000000000cf => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]22240000000000cf => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]22240000000000cf => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]22240000000000cf => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]22240000000000cf => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]22240000000000cf => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]22240000000000cf => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]22240000000000cf => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]22240000000000cf => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]22240000000000cf => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]22240000000000cf => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]22240000000000cf => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]a21400010a395bcf => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]a21400010a395bcf => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]a21400010a395bcf => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]a21400010a395bcf => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]a21400010a395bcf => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]a21400010a395bcf => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]a21400010a395bcf => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]a21400010a395bcf => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]a21400010a395bcf => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]a21400010a395bcf => 8 (BF=0)
+dtstsf (ref_sig=4) [tSig]a21400010a395bcf => 8 (BF=1)
+dtstsf (ref_sig=4) [tSig]a21400010a395bcf => 8 (BF=6)
+dtstsf (ref_sig=6) [tSig]a21400010a395bcf => 8 (BF=0)
+dtstsf (ref_sig=6) [tSig]a21400010a395bcf => 8 (BF=1)
+dtstsf (ref_sig=6) [tSig]a21400010a395bcf => 8 (BF=6)
+dtstsf (ref_sig=63) [tSig]a21400010a395bcf => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]a21400010a395bcf => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]a21400010a395bcf => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]6e4d3f1f534acdd4 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]6e4d3f1f534acdd4 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]6e4d3f1f534acdd4 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]6e4d3f1f534acdd4 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]6e4d3f1f534acdd4 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]6e4d3f1f534acdd4 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]6e4d3f1f534acdd4 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]6e4d3f1f534acdd4 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]6e4d3f1f534acdd4 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]6e4d3f1f534acdd4 => 8 (BF=0)
+dtstsf (ref_sig=4) [tSig]6e4d3f1f534acdd4 => 8 (BF=1)
+dtstsf (ref_sig=4) [tSig]6e4d3f1f534acdd4 => 8 (BF=6)
+dtstsf (ref_sig=6) [tSig]6e4d3f1f534acdd4 => 8 (BF=0)
+dtstsf (ref_sig=6) [tSig]6e4d3f1f534acdd4 => 8 (BF=1)
+dtstsf (ref_sig=6) [tSig]6e4d3f1f534acdd4 => 8 (BF=6)
+dtstsf (ref_sig=63) [tSig]6e4d3f1f534acdd4 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]6e4d3f1f534acdd4 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]6e4d3f1f534acdd4 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]000400000089b000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]000400000089b000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]000400000089b000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]000400000089b000 => 8 (BF=0)
+dtstsf (ref_sig=1) [tSig]000400000089b000 => 8 (BF=1)
+dtstsf (ref_sig=1) [tSig]000400000089b000 => 8 (BF=6)
+dtstsf (ref_sig=2) [tSig]000400000089b000 => 8 (BF=0)
+dtstsf (ref_sig=2) [tSig]000400000089b000 => 8 (BF=1)
+dtstsf (ref_sig=2) [tSig]000400000089b000 => 8 (BF=6)
+dtstsf (ref_sig=4) [tSig]000400000089b000 => 8 (BF=0)
+dtstsf (ref_sig=4) [tSig]000400000089b000 => 8 (BF=1)
+dtstsf (ref_sig=4) [tSig]000400000089b000 => 8 (BF=6)
+dtstsf (ref_sig=6) [tSig]000400000089b000 => 8 (BF=0)
+dtstsf (ref_sig=6) [tSig]000400000089b000 => 8 (BF=1)
+dtstsf (ref_sig=6) [tSig]000400000089b000 => 8 (BF=6)
+dtstsf (ref_sig=63) [tSig]000400000089b000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]000400000089b000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]000400000089b000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=1) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=1) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=2) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=2) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=2) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=4) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]2238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]2238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]2238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]2238000000000000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=1) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=1) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=2) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=2) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=2) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=4) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]a238000000000000 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]a238000000000000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]a238000000000000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]a238000000000000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=0) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=0) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=1) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=1) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=1) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=2) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=2) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=2) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=4) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=4) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=4) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=6) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=6) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=6) [tSig]4248000000000000 => 4 (BF=6)
+dtstsf (ref_sig=63) [tSig]4248000000000000 => 4 (BF=0)
+dtstsf (ref_sig=63) [tSig]4248000000000000 => 4 (BF=1)
+dtstsf (ref_sig=63) [tSig]4248000000000000 => 4 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]7e34000000000111 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]7e34000000000111 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]7e34000000000111 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]7e34000000000111 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]fe000000d0e0a0d0 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]fe000000d0e0a0d0 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]fe000000d0e0a0d0 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]fc00000000000000 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]fc00000000000000 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]fc00000000000000 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]fc00000000000000 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]7800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]7800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]7800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]7800000000000000 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]f800000000000000 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]f800000000000000 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]f800000000000000 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]f800000000000000 => 1 (BF=6)
+
+dtstsf (ref_sig=0) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=0) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=0) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=1) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=1) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=1) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=2) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=2) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=2) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=4) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=4) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=4) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=6) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=6) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=6) [tSig]7a34000000000000 => 1 (BF=6)
+dtstsf (ref_sig=63) [tSig]7a34000000000000 => 1 (BF=0)
+dtstsf (ref_sig=63) [tSig]7a34000000000000 => 1 (BF=1)
+dtstsf (ref_sig=63) [tSig]7a34000000000000 => 1 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 0000000000000e50 => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 0000000000000e50 => 2 (BF=0)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 0000000000000e50 => 2 (BF=1)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 0000000000000e50 => 2 (BF=6)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 0000000000000e50 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 000000000014c000 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 000000000014c000 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]2207c00000000000 000000000014c000 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 000000000014c000 => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 000000000014c000 => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]2207c00000000000 000000000014c000 => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 000000000014c000 => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 000000000014c000 => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]2207c00000000000 000000000014c000 => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 000000000014c000 => 8 (BF=0)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 000000000014c000 => 8 (BF=1)
+dtstsfq (ref_sig=4) [tSig]2207c00000000000 000000000014c000 => 8 (BF=6)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 000000000014c000 => 8 (BF=0)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 000000000014c000 => 8 (BF=1)
+dtstsfq (ref_sig=6) [tSig]2207c00000000000 000000000014c000 => 8 (BF=6)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 000000000014c000 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 000000000014c000 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]2207c00000000000 000000000014c000 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]a207c00000000000 00000000000000e0 => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=0)
+dtstsfq (ref_sig=4) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=1)
+dtstsfq (ref_sig=4) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=6)
+dtstsfq (ref_sig=6) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]a207c00000000000 00000000000000e0 => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]2206c00000000000 00000000000000cf => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]2206c00000000000 00000000000000cf => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]2206c00000000000 00000000000000cf => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]2206c00000000000 00000000000000cf => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]2206c00000000000 00000000000000cf => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]2206c00000000000 00000000000000cf => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]2206c00000000000 00000000000000cf => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]2206c00000000000 00000000000000cf => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]2206c00000000000 00000000000000cf => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]2206c00000000000 00000000000000cf => 4 (BF=0)
+dtstsfq (ref_sig=4) [tSig]2206c00000000000 00000000000000cf => 4 (BF=1)
+dtstsfq (ref_sig=4) [tSig]2206c00000000000 00000000000000cf => 4 (BF=6)
+dtstsfq (ref_sig=6) [tSig]2206c00000000000 00000000000000cf => 4 (BF=0)
+dtstsfq (ref_sig=6) [tSig]2206c00000000000 00000000000000cf => 4 (BF=1)
+dtstsfq (ref_sig=6) [tSig]2206c00000000000 00000000000000cf => 4 (BF=6)
+dtstsfq (ref_sig=63) [tSig]2206c00000000000 00000000000000cf => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]2206c00000000000 00000000000000cf => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]2206c00000000000 00000000000000cf => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=0)
+dtstsfq (ref_sig=0) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=1)
+dtstsfq (ref_sig=0) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=6)
+dtstsfq (ref_sig=1) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstsfq (ref_sig=1) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=1)
+dtstsfq (ref_sig=1) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=6)
+dtstsfq (ref_sig=2) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstsfq (ref_sig=2) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=1)
+dtstsfq (ref_sig=2) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=6)
+dtstsfq (ref_sig=4) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstsfq (ref_sig=4) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=1)
+dtstsfq (ref_sig=4) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=6)
+dtstsfq (ref_sig=6) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=0)
+dtstsfq (ref_sig=6) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=1)
+dtstsfq (ref_sig=6) [tSig]a205c00000000000 000000010a395bcf => 8 (BF=6)
+dtstsfq (ref_sig=63) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=0)
+dtstsfq (ref_sig=63) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=1)
+dtstsfq (ref_sig=63) [tSig]a205c00000000000 000000010a395bcf => 4 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]6209400000fd0000 00253f1f534acdd4 => 4 (BF=0)
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+dtstsfq (ref_sig=1) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=1)
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+dtstsfq (ref_sig=4) [tSig]6209400000fd0000 00253f1f534acdd4 => 8 (BF=6)
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+
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+
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+
+dtstsfq (ref_sig=0) [tSig]a208000000000000 0000000000000000 => 4 (BF=0)
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+
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+
+dtstsfq (ref_sig=0) [tSig]fc00000000000000 c00100035b007700 => 1 (BF=0)
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+
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+
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+dtstsfq (ref_sig=2) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=2) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=2) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=4) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=4) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=4) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=6) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=6) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=6) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=63) [tSig]f800000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=63) [tSig]f800000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=63) [tSig]f800000000000000 0000000000000000 => 1 (BF=6)
+
+dtstsfq (ref_sig=0) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=0) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=0) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=1) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=1) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=1) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=2) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=2) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=2) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=4) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=4) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=4) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=6) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=6) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=6) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+dtstsfq (ref_sig=63) [tSig]f900000000000000 0000000000000000 => 1 (BF=0)
+dtstsfq (ref_sig=63) [tSig]f900000000000000 0000000000000000 => 1 (BF=1)
+dtstsfq (ref_sig=63) [tSig]f900000000000000 0000000000000000 => 1 (BF=6)
+
+Test DFP DPD-to-BCD instructions
+ddedpd (SP=0) [D->B]2234000000000e50 ==> 0000000000003450
+ddedpd (SP=1) [D->B]2234000000000e50 ==> 0000000000003450
+ddedpd (SP=2) [D->B]2234000000000e50 ==> 000000000003450c
+ddedpd (SP=3) [D->B]2234000000000e50 ==> 000000000003450f
+ddedpd (SP=0) [D->B]223400000014c000 ==> 0000000001230000
+ddedpd (SP=1) [D->B]223400000014c000 ==> 0000000001230000
+ddedpd (SP=2) [D->B]223400000014c000 ==> 000000001230000c
+ddedpd (SP=3) [D->B]223400000014c000 ==> 000000001230000f
+ddedpd (SP=0) [D->B]a2340000000000e0 ==> 0000000000000160
+ddedpd (SP=1) [D->B]a2340000000000e0 ==> 0000000000000160
+ddedpd (SP=2) [D->B]a2340000000000e0 ==> 000000000000160d
+ddedpd (SP=3) [D->B]a2340000000000e0 ==> 000000000000160d
+ddedpd (SP=0) [D->B]22240000000000cf ==> 0000000000000189
+ddedpd (SP=1) [D->B]22240000000000cf ==> 0000000000000189
+ddedpd (SP=2) [D->B]22240000000000cf ==> 000000000000189c
+ddedpd (SP=3) [D->B]22240000000000cf ==> 000000000000189f
+ddedpd (SP=0) [D->B]a21400010a395bcf ==> 0000004123456789
+ddedpd (SP=1) [D->B]a21400010a395bcf ==> 0000004123456789
+ddedpd (SP=2) [D->B]a21400010a395bcf ==> 000004123456789d
+ddedpd (SP=3) [D->B]a21400010a395bcf ==> 000004123456789d
+ddedpd (SP=0) [D->B]6e4d3f1f534acdd4 ==> 9839871234533354
+ddedpd (SP=1) [D->B]6e4d3f1f534acdd4 ==> 9839871234533354
+ddedpd (SP=2) [D->B]6e4d3f1f534acdd4 ==> 839871234533354c
+ddedpd (SP=3) [D->B]6e4d3f1f534acdd4 ==> 839871234533354f
+ddedpd (SP=0) [D->B]000400000089b000 ==> 0000000008864000
+ddedpd (SP=1) [D->B]000400000089b000 ==> 0000000008864000
+ddedpd (SP=2) [D->B]000400000089b000 ==> 000000008864000c
+ddedpd (SP=3) [D->B]000400000089b000 ==> 000000008864000f
+ddedpd (SP=0) [D->B]2238000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]2238000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]2238000000000000 ==> 000000000000000c
+ddedpd (SP=3) [D->B]2238000000000000 ==> 000000000000000f
+ddedpd (SP=0) [D->B]a238000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]a238000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]a238000000000000 ==> 000000000000000d
+ddedpd (SP=3) [D->B]a238000000000000 ==> 000000000000000d
+ddedpd (SP=0) [D->B]4248000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]4248000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]4248000000000000 ==> 000000000000000c
+ddedpd (SP=3) [D->B]4248000000000000 ==> 000000000000000f
+ddedpd (SP=0) [D->B]7e34000000000111 ==> 0000000000000211
+ddedpd (SP=1) [D->B]7e34000000000111 ==> 0000000000000211
+ddedpd (SP=2) [D->B]7e34000000000111 ==> 000000000000211c
+ddedpd (SP=3) [D->B]7e34000000000111 ==> 000000000000211f
+ddedpd (SP=0) [D->B]fe000000d0e0a0d0 ==> 0000003882028150
+ddedpd (SP=1) [D->B]fe000000d0e0a0d0 ==> 0000003882028150
+ddedpd (SP=2) [D->B]fe000000d0e0a0d0 ==> 000003882028150d
+ddedpd (SP=3) [D->B]fe000000d0e0a0d0 ==> 000003882028150d
+ddedpd (SP=0) [D->B]fc00000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]fc00000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]fc00000000000000 ==> 000000000000000d
+ddedpd (SP=3) [D->B]fc00000000000000 ==> 000000000000000d
+ddedpd (SP=0) [D->B]7800000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]7800000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]7800000000000000 ==> 000000000000000c
+ddedpd (SP=3) [D->B]7800000000000000 ==> 000000000000000f
+ddedpd (SP=0) [D->B]f800000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]f800000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]f800000000000000 ==> 000000000000000d
+ddedpd (SP=3) [D->B]f800000000000000 ==> 000000000000000d
+ddedpd (SP=0) [D->B]7a34000000000000 ==> 0000000000000000
+ddedpd (SP=1) [D->B]7a34000000000000 ==> 0000000000000000
+ddedpd (SP=2) [D->B]7a34000000000000 ==> 000000000000000c
+ddedpd (SP=3) [D->B]7a34000000000000 ==> 000000000000000f
+
+ddedpdq (SP=0) [D->B]2207c00000000000 0000000000000e50 ==> 0000000000000000 0000000000003450
+ddedpdq (SP=1) [D->B]2207c00000000000 0000000000000e50 ==> 0000000000000000 0000000000003450
+ddedpdq (SP=2) [D->B]2207c00000000000 0000000000000e50 ==> 0000000000000000 000000000003450c
+ddedpdq (SP=3) [D->B]2207c00000000000 0000000000000e50 ==> 0000000000000000 000000000003450f
+ddedpdq (SP=0) [D->B]2207c00000000000 000000000014c000 ==> 0000000000000000 0000000001230000
+ddedpdq (SP=1) [D->B]2207c00000000000 000000000014c000 ==> 0000000000000000 0000000001230000
+ddedpdq (SP=2) [D->B]2207c00000000000 000000000014c000 ==> 0000000000000000 000000001230000c
+ddedpdq (SP=3) [D->B]2207c00000000000 000000000014c000 ==> 0000000000000000 000000001230000f
+ddedpdq (SP=0) [D->B]a207c00000000000 00000000000000e0 ==> 0000000000000000 0000000000000160
+ddedpdq (SP=1) [D->B]a207c00000000000 00000000000000e0 ==> 0000000000000000 0000000000000160
+ddedpdq (SP=2) [D->B]a207c00000000000 00000000000000e0 ==> 0000000000000000 000000000000160d
+ddedpdq (SP=3) [D->B]a207c00000000000 00000000000000e0 ==> 0000000000000000 000000000000160d
+ddedpdq (SP=0) [D->B]2206c00000000000 00000000000000cf ==> 0000000000000000 0000000000000189
+ddedpdq (SP=1) [D->B]2206c00000000000 00000000000000cf ==> 0000000000000000 0000000000000189
+ddedpdq (SP=2) [D->B]2206c00000000000 00000000000000cf ==> 0000000000000000 000000000000189c
+ddedpdq (SP=3) [D->B]2206c00000000000 00000000000000cf ==> 0000000000000000 000000000000189f
+ddedpdq (SP=0) [D->B]a205c00000000000 000000010a395bcf ==> 0000000000000000 0000004123456789
+ddedpdq (SP=1) [D->B]a205c00000000000 000000010a395bcf ==> 0000000000000000 0000004123456789
+ddedpdq (SP=2) [D->B]a205c00000000000 000000010a395bcf ==> 0000000000000000 000004123456789d
+ddedpdq (SP=3) [D->B]a205c00000000000 000000010a395bcf ==> 0000000000000000 000004123456789d
+ddedpdq (SP=0) [D->B]6209400000fd0000 00253f1f534acdd4 ==> 0000097100000000 9839871234533354
+ddedpdq (SP=1) [D->B]6209400000fd0000 00253f1f534acdd4 ==> 0000097100000000 9839871234533354
+ddedpdq (SP=2) [D->B]6209400000fd0000 00253f1f534acdd4 ==> 0000971000000009 839871234533354c
+ddedpdq (SP=3) [D->B]6209400000fd0000 00253f1f534acdd4 ==> 0000971000000009 839871234533354f
+ddedpdq (SP=0) [D->B]000400000089b000 0a6000d000000049 ==> 0000010954000051 8000640000000049
+ddedpdq (SP=1) [D->B]000400000089b000 0a6000d000000049 ==> 0000010954000051 8000640000000049
+ddedpdq (SP=2) [D->B]000400000089b000 0a6000d000000049 ==> 0000109540000518 000640000000049c
+ddedpdq (SP=3) [D->B]000400000089b000 0a6000d000000049 ==> 0000109540000518 000640000000049f
+ddedpdq (SP=0) [D->B]2208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]2208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]2208000000000000 0000000000000000 ==> 0000000000000000 000000000000000c
+ddedpdq (SP=3) [D->B]2208000000000000 0000000000000000 ==> 0000000000000000 000000000000000f
+ddedpdq (SP=0) [D->B]a208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]a208000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]a208000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=3) [D->B]a208000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=0) [D->B]a248000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]a248000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]a248000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=3) [D->B]a248000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=0) [D->B]7c00000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]7c00000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]7c00000000000000 0000000000000000 ==> 0000000000000000 000000000000000c
+ddedpdq (SP=3) [D->B]7c00000000000000 0000000000000000 ==> 0000000000000000 000000000000000f
+ddedpdq (SP=0) [D->B]fc00000000000000 c00100035b007700 ==> 0000000000080000 0200801330811600
+ddedpdq (SP=1) [D->B]fc00000000000000 c00100035b007700 ==> 0000000000080000 0200801330811600
+ddedpdq (SP=2) [D->B]fc00000000000000 c00100035b007700 ==> 0000000000800000 200801330811600d
+ddedpdq (SP=3) [D->B]fc00000000000000 c00100035b007700 ==> 0000000000800000 200801330811600d
+ddedpdq (SP=0) [D->B]7e00000000000000 fe000000d0e0a0d0 ==> 0000000000088170 0000003882028150
+ddedpdq (SP=1) [D->B]7e00000000000000 fe000000d0e0a0d0 ==> 0000000000088170 0000003882028150
+ddedpdq (SP=2) [D->B]7e00000000000000 fe000000d0e0a0d0 ==> 0000000000881700 000003882028150c
+ddedpdq (SP=3) [D->B]7e00000000000000 fe000000d0e0a0d0 ==> 0000000000881700 000003882028150f
+ddedpdq (SP=0) [D->B]7800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]7800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]7800000000000000 0000000000000000 ==> 0000000000000000 000000000000000c
+ddedpdq (SP=3) [D->B]7800000000000000 0000000000000000 ==> 0000000000000000 000000000000000f
+ddedpdq (SP=0) [D->B]f800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]f800000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]f800000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=3) [D->B]f800000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=0) [D->B]f900000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=1) [D->B]f900000000000000 0000000000000000 ==> 0000000000000000 0000000000000000
+ddedpdq (SP=2) [D->B]f900000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+ddedpdq (SP=3) [D->B]f900000000000000 0000000000000000 ==> 0000000000000000 000000000000000d
+
+Test DFP BCD-to-DPD instructions
+denbcd (S=0) [B->D]0000000000003450 ==> 2238000000000e50
+denbcd (S=1) [B->D]0000000000003450 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000003450c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000003450c ==> 2238000000000e50
+denbcd (S=0) [B->D]000000000003450f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000003450f ==> 2238000000000e50
+denbcd (S=0) [B->D]0000000001230000 ==> 223800000014c000
+denbcd (S=1) [B->D]0000000001230000 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000001230000c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000001230000c ==> 223800000014c000
+denbcd (S=0) [B->D]000000001230000f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000001230000f ==> 223800000014c000
+denbcd (S=0) [B->D]0000000000000160 ==> 22380000000000e0
+denbcd (S=1) [B->D]0000000000000160 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000000160d ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000160d ==> a2380000000000e0
+denbcd (S=0) [B->D]0000000000000189 ==> 22380000000000cf
+denbcd (S=1) [B->D]0000000000000189 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000000189c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000189c ==> 22380000000000cf
+denbcd (S=0) [B->D]000000000000189f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000189f ==> 22380000000000cf
+denbcd (S=0) [B->D]0000004123456789 ==> 223800010a395bcf
+denbcd (S=1) [B->D]0000004123456789 ==> 7c00000000000000
+denbcd (S=0) [B->D]000004123456789d ==> 7c00000000000000
+denbcd (S=1) [B->D]000004123456789d ==> a23800010a395bcf
+denbcd (S=0) [B->D]9839871234533354 ==> 6e393f1f534acdd4
+denbcd (S=1) [B->D]9839871234533354 ==> 7c00000000000000
+denbcd (S=0) [B->D]839871234533354c ==> 7c00000000000000
+denbcd (S=1) [B->D]839871234533354c ==> 22393f1f534acdd4
+denbcd (S=0) [B->D]839871234533354f ==> 7c00000000000000
+denbcd (S=1) [B->D]839871234533354f ==> 22393f1f534acdd4
+denbcd (S=0) [B->D]0000000008864000 ==> 223800000089b000
+denbcd (S=1) [B->D]0000000008864000 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000008864000c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000008864000c ==> 223800000089b000
+denbcd (S=0) [B->D]000000008864000f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000008864000f ==> 223800000089b000
+denbcd (S=0) [B->D]0000000000000000 ==> 2238000000000000
+denbcd (S=1) [B->D]0000000000000000 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000000000c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000000c ==> 2238000000000000
+denbcd (S=0) [B->D]000000000000000f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000000f ==> 2238000000000000
+denbcd (S=0) [B->D]000000000000000d ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000000d ==> a238000000000000
+denbcd (S=0) [B->D]0000000000000211 ==> 2238000000000111
+denbcd (S=1) [B->D]0000000000000211 ==> 7c00000000000000
+denbcd (S=0) [B->D]000000000000211c ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000211c ==> 2238000000000111
+denbcd (S=0) [B->D]000000000000211f ==> 7c00000000000000
+denbcd (S=1) [B->D]000000000000211f ==> 2238000000000111
+denbcd (S=0) [B->D]0000003882028150 ==> 22380000d0e0a0d0
+denbcd (S=1) [B->D]0000003882028150 ==> 7c00000000000000
+denbcd (S=0) [B->D]000003882028150d ==> 7c00000000000000
+denbcd (S=1) [B->D]000003882028150d ==> a2380000d0e0a0d0
+
+denbcdq (S=0) [B->D]0000000000000000 0000000000003450 ==> 2208000000000000 0000000000000e50
+denbcdq (S=1) [B->D]0000000000000000 0000000000003450 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000003450c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000003450c ==> 2208000000000000 0000000000000e50
+denbcdq (S=0) [B->D]0000000000000000 000000000003450f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000003450f ==> 2208000000000000 0000000000000e50
+denbcdq (S=0) [B->D]0000000000000000 0000000001230000 ==> 2208000000000000 000000000014c000
+denbcdq (S=1) [B->D]0000000000000000 0000000001230000 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000001230000c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000001230000c ==> 2208000000000000 000000000014c000
+denbcdq (S=0) [B->D]0000000000000000 000000001230000f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000001230000f ==> 2208000000000000 000000000014c000
+denbcdq (S=0) [B->D]0000000000000000 0000000000000160 ==> 2208000000000000 00000000000000e0
+denbcdq (S=1) [B->D]0000000000000000 0000000000000160 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000160d ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000160d ==> a208000000000000 00000000000000e0
+denbcdq (S=0) [B->D]0000000000000000 0000000000000189 ==> 2208000000000000 00000000000000cf
+denbcdq (S=1) [B->D]0000000000000000 0000000000000189 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000189c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000189c ==> 2208000000000000 00000000000000cf
+denbcdq (S=0) [B->D]0000000000000000 000000000000189f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000189f ==> 2208000000000000 00000000000000cf
+denbcdq (S=0) [B->D]0000000000000000 0000004123456789 ==> 2208000000000000 000000010a395bcf
+denbcdq (S=1) [B->D]0000000000000000 0000004123456789 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000004123456789d ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000004123456789d ==> a208000000000000 000000010a395bcf
+denbcdq (S=0) [B->D]0000097100000000 9839871234533354 ==> 2208000000fd0000 00253f1f534acdd4
+denbcdq (S=1) [B->D]0000097100000000 9839871234533354 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000971000000009 839871234533354c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000971000000009 839871234533354c ==> 2208000000fd0000 00253f1f534acdd4
+denbcdq (S=0) [B->D]0000971000000009 839871234533354f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000971000000009 839871234533354f ==> 2208000000fd0000 00253f1f534acdd4
+denbcdq (S=0) [B->D]0000010954000051 8000640000000049 ==> 220800000089b000 0a6000d000000049
+denbcdq (S=1) [B->D]0000010954000051 8000640000000049 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000109540000518 000640000000049c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000109540000518 000640000000049c ==> 220800000089b000 0a6000d000000049
+denbcdq (S=0) [B->D]0000109540000518 000640000000049f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000109540000518 000640000000049f ==> 220800000089b000 0a6000d000000049
+denbcdq (S=0) [B->D]0000000000000000 0000000000000000 ==> 2208000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 0000000000000000 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000000c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000000c ==> 2208000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000000f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000000f ==> 2208000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000000000 000000000000000d ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000000000 000000000000000d ==> a208000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000080000 0200801330811600 ==> 2208000000000000 c00100035b007700
+denbcdq (S=1) [B->D]0000000000080000 0200801330811600 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000800000 200801330811600d ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000800000 200801330811600d ==> a208000000000000 c00100035b007700
+denbcdq (S=0) [B->D]0000000000088170 0000003882028150 ==> 2208000000000000 fe000000d0e0a0d0
+denbcdq (S=1) [B->D]0000000000088170 0000003882028150 ==> 7c00000000000000 0000000000000000
+denbcdq (S=0) [B->D]0000000000881700 000003882028150c ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000881700 000003882028150c ==> 2208000000000000 fe000000d0e0a0d0
+denbcdq (S=0) [B->D]0000000000881700 000003882028150f ==> 7c00000000000000 0000000000000000
+denbcdq (S=1) [B->D]0000000000881700 000003882028150f ==> 2208000000000000 fe000000d0e0a0d0
+
diff --git a/none/tests/ppc64/test_isa_2_06_part1.c b/none/tests/ppc64/test_isa_2_06_part1.c
deleted file mode 120000
index 0c78636..0000000
--- a/none/tests/ppc64/test_isa_2_06_part1.c
+++ /dev/null
@@ -1 +0,0 @@
-../../../none/tests/ppc32/test_isa_2_06_part1.c
\ No newline at end of file
diff --git a/none/tests/ppc64/test_isa_2_06_part1.c b/none/tests/ppc64/test_isa_2_06_part1.c
new file mode 100644
index 0000000..7cd4930
--- /dev/null
+++ b/none/tests/ppc64/test_isa_2_06_part1.c
@@ -0,0 +1,2073 @@
+/* Copyright (C) 2011 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#ifdef HAS_VSX
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <malloc.h>
+#include <altivec.h>
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif /* __powerpc64__ */
+
+#ifdef VGP_ppc64le_linux
+#define isLE 1
+#else
+#define isLE 0
+#endif
+
+register HWord_t r14 __asm__ ("r14");
+register HWord_t r15 __asm__ ("r15");
+register HWord_t r16 __asm__ ("r16");
+register HWord_t r17 __asm__ ("r17");
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+
+static volatile unsigned int cond_reg;
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+
+typedef void (*test_func_t)(void);
+typedef struct ldst_test ldst_test_t;
+typedef struct vsx_logic_test logic_test_t;
+typedef struct xs_conv_test xs_conv_test_t;
+typedef struct p7_fp_test fp_test_t;
+typedef struct vx_fp_test vx_fp_test_t;
+typedef struct vsx_move_test move_test_t;
+typedef struct vsx_permute_test permute_test_t;
+typedef struct test_table test_table_t;
+
+static double *fargs = NULL;
+static int nb_fargs;
+
+/* These functions below that construct a table of floating point
+ * values were lifted from none/tests/ppc32/jm-insns.c.
+ */
+
+#if defined (DEBUG_ARGS_BUILD)
+#define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define AB_DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+static inline void register_farg (void *farg,
+ int s, uint16_t _exp, uint64_t mant)
+{
+ uint64_t tmp;
+
+ tmp = ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
+ *(uint64_t *)farg = tmp;
+ AB_DPRINTF("%d %03x %013llx => %016llx %0e\n",
+ s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
+}
+
+static void build_fargs_table(void)
+/*
+ * Double precision:
+ * Sign goes from zero to one (1 bit)
+ * Exponent goes from 0 to ((1 << 12) - 1) (11 bits)
+ * Mantissa goes from 1 to ((1 << 52) - 1) (52 bits)
+ * + special values:
+ * +0.0 : 0 0x000 0x0000000000000 => 0x0000000000000000
+ * -0.0 : 1 0x000 0x0000000000000 => 0x8000000000000000
+ * +infinity : 0 0x7FF 0x0000000000000 => 0x7FF0000000000000
+ * -infinity : 1 0x7FF 0x0000000000000 => 0xFFF0000000000000
+ * +QNaN : 0 0x7FF 0x8000000000000 => 0x7FF8000000000000
+ * -QNaN : 1 0x7FF 0x8000000000000 => 0xFFF8000000000000
+ * +SNaN : 0 0x7FF 0x7FFFFFFFFFFFF => 0x7FF7FFFFFFFFFFFF
+ * -SNaN : 1 0x7FF 0x7FFFFFFFFFFFF => 0xFFF7FFFFFFFFFFFF
+ * (8 values)
+ *
+ * Single precision
+ * Sign: 1 bit
+ * Exponent: 8 bits
+ * Mantissa: 23 bits
+ * +0.0 : 0 0x00 0x000000 => 0x00000000
+ * -0.0 : 1 0x00 0x000000 => 0x80000000
+ * +infinity : 0 0xFF 0x000000 => 0x7F800000
+ * -infinity : 1 0xFF 0x000000 => 0xFF800000
+ * +QNaN : 0 0xFF 0x400000 => 0x7FC00000
+ * -QNaN : 1 0xFF 0x400000 => 0xFFC00000
+ * +SNaN : 0 0xFF 0x3FFFFF => 0x7FBFFFFF
+ * -SNaN : 1 0xFF 0x3FFFFF => 0xFFBFFFFF
+*/
+{
+ uint64_t mant;
+ uint16_t _exp, e1;
+ int s;
+ int i=0;
+
+ if (nb_fargs)
+ return;
+
+ fargs = malloc( 16 * sizeof(double) );
+ for (s = 0; s < 2; s++) {
+ for (e1 = 0x001;; e1 = ((e1 + 1) << 13) + 7) {
+ if (e1 >= 0x400)
+ e1 = 0x3fe;
+ _exp = e1;
+ for (mant = 0x0000000000001ULL; mant < (1ULL << 52);
+ /* Add 'random' bits */
+ mant = ((mant + 0x4A6) << 29) + 0x359) {
+ register_farg( &fargs[i++], s, _exp, mant );
+ }
+ if (e1 == 0x3fe)
+ break;
+ }
+ }
+ // add a few smaller values to fargs . . .
+ s = 0;
+ _exp = 0x002;
+ mant = 0x0000000000b01ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ _exp = 0x000;
+ mant = 0x00000203f0b3dULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ mant = 0x00000005a203dULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ s = 1;
+ _exp = 0x002;
+ mant = 0x0000000000b01ULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ _exp = 0x000;
+ mant = 0x00000203f0b3dULL;
+ register_farg(&fargs[i++], s, _exp, mant);
+
+ nb_fargs = i;
+}
+
+
+typedef struct fp_test_args {
+ int fra_idx;
+ int frb_idx;
+ int cr_flags;
+} fp_test_args_t;
+
+
+fp_test_args_t ftdiv_tests[] = {
+ {0, 1, 0x8},
+ {9, 1, 0xa},
+ {1, 12, 0xa},
+ {0, 2, 0xa},
+ {1, 3, 0xa},
+ {3, 0, 0xa},
+ {0, 3, 0xa},
+ {4, 0, 0xa},
+ {7, 1, 0xe},
+ {8, 1, 0xe},
+ {1, 7, 0xe},
+ {0, 13, 0xe},
+ {5, 5, 0xe},
+ {5, 6, 0xe},
+};
+
+fp_test_args_t xscmpX_tests[] = {
+ {8, 8, 0x2},
+ {8, 14, 0x8},
+ {8, 6, 0x8},
+ {8, 5, 0x8},
+ {8, 4, 0x8},
+ {8, 7, 0x8},
+ {8, 9, 0x1},
+ {8, 11, 0x1},
+ {14, 8, 0x4},
+ {14, 14, 0x2},
+ {14, 6, 0x8},
+ {14, 5, 0x8},
+ {14, 4, 0x8},
+ {14, 7, 0x8},
+ {14, 9, 0x1},
+ {14, 11, 0x1},
+ {6, 8, 0x4},
+ {6, 14, 0x4},
+ {6, 6, 0x2},
+ {6, 5, 0x2},
+ {6, 4, 0x8},
+ {6, 7, 0x8},
+ {6, 9, 0x1},
+ {6, 11, 0x1},
+ {5, 8, 0x4},
+ {5, 14, 0x4},
+ {5, 6, 0x2},
+ {5, 5, 0x2},
+ {5, 4, 0x8},
+ {5, 7, 0x8},
+ {5, 9, 0x1},
+ {5, 11, 0x1},
+ {4, 8, 0x4},
+ {4, 14, 0x4},
+ {4, 6, 0x4},
+ {4, 5, 0x4},
+ {4, 1, 0x8},
+ {4, 7, 0x8},
+ {4, 9, 0x1},
+ {4, 11, 0x1},
+ {7, 8, 0x4},
+ {7, 14, 0x4},
+ {7, 6, 0x4},
+ {7, 5, 0x4},
+ {7, 4, 0x4},
+ {7, 7, 0x2},
+ {7, 9, 0x1},
+ {7, 11, 0x1},
+ {10, 8, 0x1},
+ {10, 14, 0x1},
+ {10, 6, 0x1},
+ {10, 5, 0x1},
+ {10, 4, 0x1},
+ {10, 7, 0x1},
+ {10, 9, 0x1},
+ {10, 11, 0x1},
+ {12, 8, 0x1},
+ {12, 14, 0x1},
+ {12, 6, 0x1},
+ {12, 5, 0x1},
+ {12, 4, 0x1},
+ {12, 7, 0x1},
+ {12, 9, 0x1},
+ {12, 11, 0x1},
+};
+
+fp_test_args_t xsadddp_tests[] = {
+ {8, 8, 0x0},
+ {8, 14, 0x0},
+ {8, 6, 0x0},
+ {8, 5, 0x0},
+ {8, 4, 0x0},
+ {8, 7, 0x0},
+ {8, 9, 0x0},
+ {8, 11, 0x0},
+ {14, 8, 0x0},
+ {14, 14, 0x0},
+ {14, 6, 0x0},
+ {14, 5, 0x0},
+ {14, 4, 0x0},
+ {14, 7, 0x0},
+ {14, 9, 0x0},
+ {14, 11, 0x0},
+ {6, 8, 0x0},
+ {6, 14, 0x0},
+ {6, 6, 0x0},
+ {6, 5, 0x0},
+ {6, 4, 0x0},
+ {6, 7, 0x0},
+ {6, 9, 0x0},
+ {6, 11, 0x0},
+ {5, 8, 0x0},
+ {5, 14, 0x0},
+ {5, 6, 0x0},
+ {5, 5, 0x0},
+ {5, 4, 0x0},
+ {5, 7, 0x0},
+ {5, 9, 0x0},
+ {5, 11, 0x0},
+ {4, 8, 0x0},
+ {4, 14, 0x0},
+ {4, 6, 0x0},
+ {4, 5, 0x0},
+ {4, 1, 0x0},
+ {4, 7, 0x0},
+ {4, 9, 0x0},
+ {4, 11, 0x0},
+ {7, 8, 0x0},
+ {7, 14, 0x0},
+ {7, 6, 0x0},
+ {7, 5, 0x0},
+ {7, 4, 0x0},
+ {7, 7, 0x0},
+ {7, 9, 0x0},
+ {7, 11, 0x0},
+ {10, 8, 0x0},
+ {10, 14, 0x0},
+ {10, 6, 0x0},
+ {10, 5, 0x0},
+ {10, 4, 0x0},
+ {10, 7, 0x0},
+ {10, 9, 0x0},
+ {10, 11, 0x0},
+ {12, 8, 0x0},
+ {12, 14, 0x0},
+ {12, 6, 0x0},
+ {12, 5, 0x0},
+ {12, 4, 0x0},
+ {12, 7, 0x0},
+ {12, 9, 0x0},
+ {12, 11, 0x0},
+};
+
+fp_test_args_t xsdivdp_tests[] = {
+ {8, 8, 0x0},
+ {8, 14, 0x0},
+ {8, 6, 0x0},
+ {8, 5, 0x0},
+ {8, 4, 0x0},
+ {8, 7, 0x0},
+ {8, 9, 0x0},
+ {8, 11, 0x0},
+ {14, 8, 0x0},
+ {14, 14, 0x0},
+ {14, 6, 0x0},
+ {14, 5, 0x0},
+ {14, 4, 0x0},
+ {14, 7, 0x0},
+ {14, 9, 0x0},
+ {14, 11, 0x0},
+ {6, 8, 0x0},
+ {6, 14, 0x0},
+ {6, 6, 0x0},
+ {6, 5, 0x0},
+ {6, 4, 0x0},
+ {6, 7, 0x0},
+ {6, 9, 0x0},
+ {6, 11, 0x0},
+ {5, 8, 0x0},
+ {5, 14, 0x0},
+ {5, 6, 0x0},
+ {5, 5, 0x0},
+ {5, 4, 0x0},
+ {5, 7, 0x0},
+ {5, 9, 0x0},
+ {5, 11, 0x0},
+ {4, 8, 0x0},
+ {4, 14, 0x0},
+ {4, 6, 0x0},
+ {4, 5, 0x0},
+ {4, 1, 0x0},
+ {4, 7, 0x0},
+ {4, 9, 0x0},
+ {4, 11, 0x0},
+ {7, 8, 0x0},
+ {7, 14, 0x0},
+ {7, 6, 0x0},
+ {7, 5, 0x0},
+ {7, 4, 0x0},
+ {7, 7, 0x0},
+ {7, 9, 0x0},
+ {7, 11, 0x0},
+ {10, 8, 0x0},
+ {10, 14, 0x0},
+ {10, 6, 0x0},
+ {10, 5, 0x0},
+ {10, 4, 0x0},
+ {10, 7, 0x0},
+ {10, 9, 0x0},
+ {10, 11, 0x0},
+ {12, 8, 0x0},
+ {12, 14, 0x0},
+ {12, 6, 0x0},
+ {12, 5, 0x0},
+ {12, 4, 0x0},
+ {12, 7, 0x0},
+ {12, 9, 0x0},
+ {12, 11, 0x0},
+};
+
+fp_test_args_t xsmaddXdp_tests[] = {
+ {8, 8, 0x0},
+ {8, 14, 0x0},
+ {8, 6, 0x0},
+ {8, 5, 0x0},
+ {8, 4, 0x0},
+ {8, 7, 0x0},
+ {8, 9, 0x0},
+ {8, 11, 0x0},
+ {14, 8, 0x0},
+ {14, 14, 0x0},
+ {14, 6, 0x0},
+ {14, 5, 0x0},
+ {14, 4, 0x0},
+ {14, 7, 0x0},
+ {14, 9, 0x0},
+ {14, 11, 0x0},
+ {6, 8, 0x0},
+ {6, 14, 0x0},
+ {6, 6, 0x0},
+ {6, 5, 0x0},
+ {6, 4, 0x0},
+ {6, 7, 0x0},
+ {6, 9, 0x0},
+ {6, 11, 0x0},
+ {5, 8, 0x0},
+ {5, 14, 0x0},
+ {5, 6, 0x0},
+ {5, 5, 0x0},
+ {5, 4, 0x0},
+ {5, 7, 0x0},
+ {5, 9, 0x0},
+ {5, 11, 0x0},
+ {4, 8, 0x0},
+ {4, 14, 0x0},
+ {4, 6, 0x0},
+ {4, 5, 0x0},
+ {4, 1, 0x0},
+ {4, 7, 0x0},
+ {4, 9, 0x0},
+ {4, 11, 0x0},
+ {7, 8, 0x0},
+ {7, 14, 0x0},
+ {7, 6, 0x0},
+ {7, 5, 0x0},
+ {7, 4, 0x0},
+ {7, 7, 0x0},
+ {7, 9, 0x0},
+ {7, 11, 0x0},
+ {10, 8, 0x0},
+ {10, 14, 0x0},
+ {10, 6, 0x0},
+ {10, 5, 0x0},
+ {10, 4, 0x0},
+ {10, 7, 0x0},
+ {10, 9, 0x0},
+ {10, 11, 0x0},
+ {12, 8, 0x0},
+ {12, 14, 0x0},
+ {12, 6, 0x0},
+ {12, 5, 0x0},
+ {12, 4, 0x0},
+ {12, 7, 0x0},
+ {12, 9, 0x0},
+ {12, 11, 0x0},
+};
+
+fp_test_args_t xsmsubXdp_tests[] = {
+ {8, 8, 0x0},
+ {8, 14, 0x0},
+ {8, 6, 0x0},
+ {8, 5, 0x0},
+ {8, 4, 0x0},
+ {8, 7, 0x0},
+ {8, 9, 0x0},
+ {8, 11, 0x0},
+ {14, 8, 0x0},
+ {14, 14, 0x0},
+ {14, 6, 0x0},
+ {14, 5, 0x0},
+ {14, 4, 0x0},
+ {14, 7, 0x0},
+ {14, 9, 0x0},
+ {14, 11, 0x0},
+ {6, 8, 0x0},
+ {6, 14, 0x0},
+ {6, 6, 0x0},
+ {6, 5, 0x0},
+ {6, 4, 0x0},
+ {6, 7, 0x0},
+ {6, 9, 0x0},
+ {6, 11, 0x0},
+ {5, 8, 0x0},
+ {5, 14, 0x0},
+ {5, 6, 0x0},
+ {5, 5, 0x0},
+ {5, 4, 0x0},
+ {5, 7, 0x0},
+ {5, 9, 0x0},
+ {5, 11, 0x0},
+ {4, 8, 0x0},
+ {4, 14, 0x0},
+ {4, 6, 0x0},
+ {4, 5, 0x0},
+ {4, 1, 0x0},
+ {4, 7, 0x0},
+ {4, 9, 0x0},
+ {4, 11, 0x0},
+ {7, 8, 0x0},
+ {7, 14, 0x0},
+ {7, 6, 0x0},
+ {7, 5, 0x0},
+ {7, 4, 0x0},
+ {7, 7, 0x0},
+ {7, 9, 0x0},
+ {7, 11, 0x0},
+ {10, 8, 0x0},
+ {10, 14, 0x0},
+ {10, 6, 0x0},
+ {10, 5, 0x0},
+ {10, 4, 0x0},
+ {10, 7, 0x0},
+ {10, 9, 0x0},
+ {10, 11, 0x0},
+ {12, 8, 0x0},
+ {12, 14, 0x0},
+ {12, 6, 0x0},
+ {12, 5, 0x0},
+ {12, 4, 0x0},
+ {12, 7, 0x0},
+ {12, 9, 0x0},
+ {12, 11, 0x0},
+};
+
+fp_test_args_t xsnmaddXdp_tests[] = {
+ {8, 8, 0x0},
+ {8, 14, 0x0},
+ {8, 6, 0x0},
+ {8, 5, 0x0},
+ {8, 4, 0x0},
+ {8, 7, 0x0},
+ {8, 9, 0x0},
+ {8, 11, 0x0},
+ {14, 8, 0x0},
+ {14, 14, 0x0},
+ {14, 6, 0x0},
+ {14, 5, 0x0},
+ {14, 4, 0x0},
+ {14, 7, 0x0},
+ {14, 9, 0x0},
+ {14, 11, 0x0},
+ {6, 8, 0x0},
+ {6, 14, 0x0},
+ {6, 6, 0x0},
+ {6, 5, 0x0},
+ {6, 4, 0x0},
+ {6, 7, 0x0},
+ {6, 9, 0x0},
+ {6, 11, 0x0},
+ {5, 8, 0x0},
+ {5, 14, 0x0},
+ {5, 6, 0x0},
+ {5, 5, 0x0},
+ {5, 4, 0x0},
+ {5, 7, 0x0},
+ {5, 9, 0x0},
+ {5, 11, 0x0},
+ {4, 8, 0x0},
+ {4, 14, 0x0},
+ {4, 6, 0x0},
+ {4, 5, 0x0},
+ {4, 1, 0x0},
+ {4, 7, 0x0},
+ {4, 9, 0x0},
+ {4, 11, 0x0},
+ {7, 8, 0x0},
+ {7, 14, 0x0},
+ {7, 6, 0x0},
+ {7, 5, 0x0},
+ {7, 4, 0x0},
+ {7, 7, 0x0},
+ {7, 9, 0x0},
+ {7, 11, 0x0},
+ {10, 8, 0x0},
+ {10, 14, 0x0},
+ {10, 6, 0x0},
+ {10, 5, 0x0},
+ {10, 4, 0x0},
+ {10, 7, 0x0},
+ {10, 9, 0x0},
+ {10, 11, 0x0},
+ {12, 8, 0x0},
+ {12, 14, 0x0},
+ {12, 6, 0x0},
+ {12, 5, 0x0},
+ {12, 4, 0x0},
+ {12, 7, 0x0},
+ {12, 9, 0x0},
+ {12, 11, 0x0},
+};
+
+fp_test_args_t xsmuldp_tests[] = {
+ {8, 8, 0x0},
+ {8, 14, 0x0},
+ {8, 6, 0x0},
+ {8, 5, 0x0},
+ {8, 4, 0x0},
+ {8, 7, 0x0},
+ {8, 9, 0x0},
+ {8, 11, 0x0},
+ {14, 8, 0x0},
+ {14, 14, 0x0},
+ {14, 6, 0x0},
+ {14, 5, 0x0},
+ {14, 4, 0x0},
+ {14, 7, 0x0},
+ {14, 9, 0x0},
+ {14, 11, 0x0},
+ {6, 8, 0x0},
+ {6, 14, 0x0},
+ {6, 6, 0x0},
+ {6, 5, 0x0},
+ {6, 4, 0x0},
+ {6, 7, 0x0},
+ {6, 9, 0x0},
+ {6, 11, 0x0},
+ {5, 8, 0x0},
+ {5, 14, 0x0},
+ {5, 6, 0x0},
+ {5, 5, 0x0},
+ {5, 4, 0x0},
+ {5, 7, 0x0},
+ {5, 9, 0x0},
+ {5, 11, 0x0},
+ {4, 8, 0x0},
+ {4, 14, 0x0},
+ {4, 6, 0x0},
+ {4, 5, 0x0},
+ {4, 1, 0x0},
+ {4, 7, 0x0},
+ {4, 9, 0x0},
+ {4, 11, 0x0},
+ {7, 8, 0x0},
+ {7, 14, 0x0},
+ {7, 6, 0x0},
+ {7, 5, 0x0},
+ {7, 4, 0x0},
+ {7, 7, 0x0},
+ {7, 9, 0x0},
+ {7, 11, 0x0},
+ {10, 8, 0x0},
+ {10, 14, 0x0},
+ {10, 6, 0x0},
+ {10, 5, 0x0},
+ {10, 4, 0x0},
+ {10, 7, 0x0},
+ {10, 9, 0x0},
+ {10, 11, 0x0},
+ {12, 8, 0x0},
+ {12, 14, 0x0},
+ {12, 6, 0x0},
+ {12, 5, 0x0},
+ {12, 4, 0x0},
+ {12, 7, 0x0},
+ {12, 9, 0x0},
+ {12, 11, 0x0},
+};
+
+fp_test_args_t xssubdp_tests[] = {
+ {8, 8, 0x0},
+ {8, 14, 0x0},
+ {8, 6, 0x0},
+ {8, 5, 0x0},
+ {8, 4, 0x0},
+ {8, 7, 0x0},
+ {8, 9, 0x0},
+ {8, 11, 0x0},
+ {14, 8, 0x0},
+ {14, 14, 0x0},
+ {14, 6, 0x0},
+ {14, 5, 0x0},
+ {14, 4, 0x0},
+ {14, 7, 0x0},
+ {14, 9, 0x0},
+ {14, 11, 0x0},
+ {6, 8, 0x0},
+ {6, 14, 0x0},
+ {6, 6, 0x0},
+ {6, 5, 0x0},
+ {6, 4, 0x0},
+ {6, 7, 0x0},
+ {6, 9, 0x0},
+ {6, 11, 0x0},
+ {5, 8, 0x0},
+ {5, 14, 0x0},
+ {5, 6, 0x0},
+ {5, 5, 0x0},
+ {5, 4, 0x0},
+ {5, 7, 0x0},
+ {5, 9, 0x0},
+ {5, 11, 0x0},
+ {4, 8, 0x0},
+ {4, 14, 0x0},
+ {4, 6, 0x0},
+ {4, 5, 0x0},
+ {4, 1, 0x0},
+ {4, 7, 0x0},
+ {4, 9, 0x0},
+ {4, 11, 0x0},
+ {7, 8, 0x0},
+ {7, 14, 0x0},
+ {7, 6, 0x0},
+ {7, 5, 0x0},
+ {7, 4, 0x0},
+ {7, 7, 0x0},
+ {7, 9, 0x0},
+ {7, 11, 0x0},
+ {10, 8, 0x0},
+ {10, 14, 0x0},
+ {10, 6, 0x0},
+ {10, 5, 0x0},
+ {10, 4, 0x0},
+ {10, 7, 0x0},
+ {10, 9, 0x0},
+ {10, 11, 0x0},
+ {12, 8, 0x0},
+ {12, 14, 0x0},
+ {12, 6, 0x0},
+ {12, 5, 0x0},
+ {12, 4, 0x0},
+ {12, 7, 0x0},
+ {12, 9, 0x0},
+ {12, 11, 0x0},
+};
+
+
+
+static int nb_special_fargs;
+static double * spec_fargs;
+
+static void build_special_fargs_table(void)
+{
+ /* The special floating point values created below are for
+ * use in the ftdiv tests for setting the fe_flag and fg_flag,
+ * but they can also be used for other tests (e.g., xscmpudp).
+ *
+ * Note that fl_flag is 'always '1' on ppc64 Linux.
+ *
+ Entry Sign Exp fraction Special value
+ 0 0 3fd 0x8000000000000ULL Positive finite number
+ 1 0 404 0xf000000000000ULL ...
+ 2 0 001 0x8000000b77501ULL ...
+ 3 0 7fe 0x800000000051bULL ...
+ 4 0 012 0x3214569900000ULL ...
+ 5 0 000 0x0000000000000ULL +0.0 (+zero)
+ 6 1 000 0x0000000000000ULL -0.0 (-zero)
+ 7 0 7ff 0x0000000000000ULL +infinity
+ 8 1 7ff 0x0000000000000ULL -infinity
+ 9 0 7ff 0x7FFFFFFFFFFFFULL +SNaN
+ 10 1 7ff 0x7FFFFFFFFFFFFULL -SNaN
+ 11 0 7ff 0x8000000000000ULL +QNaN
+ 12 1 7ff 0x8000000000000ULL -QNaN
+ 13 1 000 0x8340000078000ULL Denormalized val (zero exp and non-zero fraction)
+ 14 1 40d 0x0650f5a07b353ULL Negative finite number
+ */
+
+ uint64_t mant;
+ uint16_t _exp;
+ int s;
+ int i = 0;
+
+ if (spec_fargs)
+ return;
+
+ spec_fargs = malloc( 16 * sizeof(double) );
+
+ // #0
+ s = 0;
+ _exp = 0x3fd;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #1
+ s = 0;
+ _exp = 0x404;
+ mant = 0xf000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* None of the ftdiv tests succeed.
+ * FRA = value #0; FRB = value #1
+ * ea_ = -2; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 100
+ */
+
+ /*************************************************
+ * fe_flag tests
+ *
+ *************************************************/
+
+ /* fe_flag <- 1 if FRA is a NaN
+ * FRA = value #9; FRB = value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRB is a NaN
+ * FRA = value #1; FRB = value #12
+ * e_a = 5; e_b = 1024
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if e_b <= -1022
+ * FRA = value #0; FRB = value #2
+ * e_a = -2; e_b = -1022
+ * fl_flag || fg_flag || fe_flag = 101
+ *
+ */
+ // #2
+ s = 0;
+ _exp = 0x001;
+ mant = 0x8000000b77501ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* fe_flag <- 1 if e_b >= 1021
+ * FRA = value #1; FRB = value #3
+ * e_a = 5; e_b = 1023
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+ // #3
+ s = 0;
+ _exp = 0x7fe;
+ mant = 0x800000000051bULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* fe_flag <- 1 if FRA != 0 && e_a - e_b >= 1023
+ * Let FRA = value #3 and FRB be value #0.
+ * e_a = 1023; e_b = -2
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRA != 0 && e_a - e_b <= -1023
+ * Let FRA = value #0 above and FRB be value #3 above
+ * e_a = -2; e_b = 1023
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRA != 0 && e_a <= -970
+ * Let FRA = value #4 and FRB be value #0
+ * e_a = -1005; e_b = -2
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+ // #4
+ s = 0;
+ _exp = 0x012;
+ mant = 0x3214569900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /*************************************************
+ * fg_flag tests
+ *
+ *************************************************/
+ /* fg_flag <- 1 if FRA is an Infinity
+ * NOTE: FRA = Inf also sets fe_flag
+ * Do two tests, using values #7 and #8 (+/- Inf) for FRA.
+ * Test 1:
+ * Let FRA be value #7 and FRB be value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 111
+ *
+ * Test 2:
+ * Let FRA be value #8 and FRB be value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 111
+ *
+ */
+
+ /* fg_flag <- 1 if FRB is an Infinity
+ * NOTE: FRB = Inf also sets fe_flag
+ * Let FRA be value #1 and FRB be value #7
+ * e_a = 5; e_b = 1024
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is denormalized
+ * NOTE: e_b < -1022 ==> fe_flag <- 1
+ * Let FRA be value #0 and FRB be value #13
+ * e_a = -2; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is +zero
+ * NOTE: FRA = Inf also sets fe_flag
+ * Let FRA = val #5; FRB = val #5
+ * ea_ = -1023; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is -zero
+ * NOTE: FRA = Inf also sets fe_flag
+ * Let FRA = val #5; FRB = val #6
+ * ea_ = -1023; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* Special values */
+ /* +0.0 : 0 0x000 0x0000000000000 */
+ // #5
+ s = 0;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -0.0 : 1 0x000 0x0000000000000 */
+ // #6
+ s = 1;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +infinity : 0 0x7FF 0x0000000000000 */
+ // #7
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -infinity : 1 0x7FF 0x0000000000000 */
+ // #8
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +SNaN : 0 0x7FF 0x7FFFFFFFFFFFF */
+ // #9
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -SNaN : 1 0x7FF 0x7FFFFFFFFFFFF */
+ // #10
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +QNaN : 0 0x7FF 0x8000000000000 */
+ // #11
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -QNaN : 1 0x7FF 0x8000000000000 */
+ // #12
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* denormalized value */
+ // #13
+ s = 1;
+ _exp = 0x000;
+ mant = 0x8340000078000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* Negative finite number */
+ // #14
+ s = 1;
+ _exp = 0x40d;
+ mant = 0x0650f5a07b353ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ nb_special_fargs = i;
+}
+
+
+struct test_table
+{
+ test_func_t test_category;
+ char * name;
+};
+
+struct p7_fp_test
+{
+ test_func_t test_func;
+ const char *name;
+ int single; // 1=single precision result; 0=double precision result
+};
+
+typedef enum {
+ VX_FP_CMP,
+ VX_FP_SMA,
+ VX_FP_SMS,
+ VX_FP_SNMA,
+ VX_FP_OTHER
+} vx_fp_test_type;
+
+struct vx_fp_test
+{
+ test_func_t test_func;
+ const char *name;
+ fp_test_args_t * targs;
+ int num_tests;
+ vx_fp_test_type test_type;
+};
+
+struct xs_conv_test
+{
+ test_func_t test_func;
+ const char *name;
+ int num_tests;
+};
+
+typedef enum {
+ VSX_LOAD =1,
+ VSX_LOAD_SPLAT,
+ VSX_STORE
+} vsx_ldst_type;
+
+struct ldst_test
+{
+ test_func_t test_func;
+ const char *name;
+ void * base_addr;
+ uint32_t offset;
+ int num_words_to_process;
+ vsx_ldst_type type;
+};
+
+typedef enum {
+ VSX_AND = 1,
+ VSX_XOR,
+ VSX_ANDC,
+ VSX_OR,
+ VSX_NOR
+} vsx_log_op;
+
+struct vsx_logic_test
+{
+ test_func_t test_func;
+ const char *name;
+ vsx_log_op op;
+};
+
+struct vsx_move_test
+{
+ test_func_t test_func;
+ const char *name;
+};
+
+struct vsx_permute_test
+{
+ test_func_t test_func;
+ const char *name;
+ unsigned int xa[4];
+ unsigned int xb[4];
+};
+
+static vector unsigned int vec_out, vec_inA, vec_inB;
+
+static void test_lxsdx(void)
+{
+ __asm__ __volatile__ ("lxsdx %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void
+test_lxvd2x(void)
+{
+ __asm__ __volatile__ ("lxvd2x %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void test_lxvdsx(void)
+{
+ __asm__ __volatile__ ("lxvdsx %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void test_lxvw4x(void)
+{
+ __asm__ __volatile__ ("lxvw4x %x0, %1, %2" : "=wa" (vec_out): "b" (r14),"r" (r15));
+}
+
+static void test_stxsdx(void)
+{
+ __asm__ __volatile__ ("stxsdx %x0, %1, %2" : : "wa" (vec_inA), "b" (r14),"r" (r15));
+}
+
+static void test_stxvd2x(void)
+{
+ __asm__ __volatile__ ("stxvd2x %x0, %1, %2" : : "wa" (vec_inA), "b" (r14),"r" (r15));
+}
+
+static void test_stxvw4x(void)
+{
+ __asm__ __volatile__ ("stxvw4x %x0, %1, %2" : : "wa" (vec_inA), "b" (r14),"r" (r15));
+}
+
+static void test_xxlxor(void)
+{
+ __asm__ __volatile__ ("xxlxor %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxlor(void)
+{
+ __asm__ __volatile__ ("xxlor %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxlnor(void)
+{
+ __asm__ __volatile__ ("xxlnor %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxland(void)
+{
+ __asm__ __volatile__ ("xxland %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxlandc(void)
+{
+ __asm__ __volatile__ ("xxlandc %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxmrghw(void)
+{
+ __asm__ __volatile__ ("xxmrghw %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxmrglw(void)
+{
+ __asm__ __volatile__ ("xxmrglw %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxpermdi_00(void)
+{
+ __asm__ __volatile__ ("xxpermdi %x0, %x1, %x2, 0x0" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxpermdi_01(void)
+{
+ __asm__ __volatile__ ("xxpermdi %x0, %x1, %x2, 0x1" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxpermdi_10(void)
+{
+ __asm__ __volatile__ ("xxpermdi %x0, %x1, %x2, 0x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxpermdi_11(void)
+{
+ __asm__ __volatile__ ("xxpermdi %x0, %x1, %x2, 0x3" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxsldwi_0(void)
+{
+ __asm__ __volatile__ ("xxsldwi %x0, %x1, %x2, 0" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxsldwi_1(void)
+{
+ __asm__ __volatile__ ("xxsldwi %x0, %x1, %x2, 1" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxsldwi_2(void)
+{
+ __asm__ __volatile__ ("xxsldwi %x0, %x1, %x2, 2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xxsldwi_3(void)
+{
+ __asm__ __volatile__ ("xxsldwi %x0, %x1, %x2, 3" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_fcfids (void)
+{
+ __asm__ __volatile__ ("fcfids %0, %1" : "=f" (f17): "d" (f14));
+}
+
+static void test_fcfidus (void)
+{
+ __asm__ __volatile__ ("fcfidus %0, %1" : "=f" (f17): "d" (f14));
+}
+
+static void test_fcfidu (void)
+{
+ __asm__ __volatile__ ("fcfidu %0, %1" : "=f" (f17): "d" (f14));
+}
+
+static void test_xsabsdp (void)
+{
+ __asm__ __volatile__ ("xsabsdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscpsgndp (void)
+{
+ __asm__ __volatile__ ("xscpsgndp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsnabsdp (void)
+{
+ __asm__ __volatile__ ("xsnabsdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsnegdp (void)
+{
+ __asm__ __volatile__ ("xsnegdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static int do_cmpudp;
+static void test_xscmp (void)
+{
+ if (do_cmpudp)
+ __asm__ __volatile__ ("xscmpudp cr1, %x0, %x1" : : "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xscmpodp cr1, %x0, %x1" : : "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsadddp(void)
+{
+ __asm__ __volatile__ ("xsadddp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsdivdp(void)
+{
+ __asm__ __volatile__ ("xsdivdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static int do_adp;
+static void test_xsmadd(void)
+{
+ if (do_adp)
+ __asm__ __volatile__ ("xsmaddadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsmaddmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsmsub(void)
+{
+ if (do_adp)
+ __asm__ __volatile__ ("xsmsubadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsmsubmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsnmadd(void)
+{
+ if (do_adp)
+ __asm__ __volatile__ ("xsnmaddadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsnmaddmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsmuldp(void)
+{
+ __asm__ __volatile__ ("xsmuldp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xssubdp(void)
+{
+ __asm__ __volatile__ ("xssubdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xscvdpsxds (void)
+{
+ __asm__ __volatile__ ("xscvdpsxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvsxddp (void)
+{
+ __asm__ __volatile__ ("xscvsxddp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvuxddp (void)
+{
+ __asm__ __volatile__ ("xscvuxddp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static unsigned int vstg[] __attribute__ ((aligned (16))) = { 0, 0, 0,0,
+ 0, 0, 0, 0 };
+
+#define NUM_VSTG_INTS (sizeof vstg/sizeof vstg[0])
+#define NUM_VSTG_VECS (NUM_VSTG_INTS/4)
+
+static unsigned int viargs[] __attribute__ ((aligned (16))) = { 0x01234567,
+ 0x89abcdef,
+ 0x00112233,
+ 0x44556677,
+ 0x8899aabb,
+ 0x91929394,
+ 0xa1a2a3a4,
+ 0xb1b2b3b4,
+ 0xc1c2c3c4,
+ 0xd1d2d3d4,
+ 0x7a6b5d3e
+};
+#define NUM_VIARGS_INTS (sizeof viargs/sizeof viargs[0])
+#define NUM_VIARGS_VECS (NUM_VIARGS_INTS/4)
+
+static ldst_test_t ldst_tests[] = { { &test_lxsdx, "lxsdx", viargs, 0, 2, VSX_LOAD },
+ { &test_lxsdx, "lxsdx", viargs, 4, 2, VSX_LOAD },
+ { &test_lxvd2x, "lxvd2x", viargs, 0, 4, VSX_LOAD },
+ { &test_lxvd2x, "lxvd2x", viargs, 4, 4, VSX_LOAD },
+ { &test_lxvdsx, "lxvdsx", viargs, 0, 4, VSX_LOAD_SPLAT },
+ { &test_lxvdsx, "lxvdsx", viargs, 4, 4, VSX_LOAD_SPLAT },
+ { &test_lxvw4x, "lxvw4x", viargs, 0, 4, VSX_LOAD },
+ { &test_lxvw4x, "lxvw4x", viargs, 4, 4, VSX_LOAD },
+ { &test_stxsdx, "stxsdx", vstg, 0, 2, VSX_STORE },
+ { &test_stxsdx, "stxsdx", vstg, 4, 2, VSX_STORE },
+ { &test_stxvd2x, "stxvd2x", vstg, 0, 4, VSX_STORE },
+ { &test_stxvd2x, "stxvd2x", vstg, 4, 4, VSX_STORE },
+ { &test_stxvw4x, "stxvw4x", vstg, 0, 4, VSX_STORE },
+ { &test_stxvw4x, "stxvw4x", vstg, 4, 4, VSX_STORE },
+ { NULL, NULL, NULL, 0, 0, 0 } };
+
+static logic_test_t logic_tests[] = { { &test_xxlxor, "xxlxor", VSX_XOR },
+ { &test_xxlor, "xxlor", VSX_OR } ,
+ { &test_xxlnor, "xxlnor", VSX_NOR },
+ { &test_xxland, "xxland", VSX_AND },
+ { &test_xxlandc, "xxlandc", VSX_ANDC },
+ { NULL, NULL, 0}};
+
+static move_test_t move_tests[] = { { &test_xsabsdp, "xsabsdp" },
+ { &test_xscpsgndp, "xscpsgndp" },
+ { &test_xsnabsdp, "xsnabsdp" },
+ { &test_xsnegdp, "xsnegdp" },
+ { NULL, NULL }
+
+};
+
+static permute_test_t permute_tests[] =
+{
+ { &test_xxmrghw, "xxmrghw",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ },
+ { &test_xxmrghw, "xxmrghw",
+ { 0x00112233, 0x44556677, 0x8899aabb, 0xccddeeff }, /* XA input */
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XB input */
+ },
+ { &test_xxmrglw, "xxmrglw",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ },
+ { &test_xxmrglw, "xxmrglw",
+ { 0x00112233, 0x44556677, 0x8899aabb, 0xccddeeff}, /* XA input */
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444}, /* XB input */
+ },
+ { &test_xxpermdi_00, "xxpermdi DM=00",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ },
+ { &test_xxpermdi_01, "xxpermdi DM=01",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ },
+ { &test_xxpermdi_10, "xxpermdi DM=10",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ },
+ { &test_xxpermdi_11, "xxpermdi DM=11",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ },
+ { &test_xxsldwi_0, "xxsldwi SHW=0",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ },
+ { &test_xxsldwi_1, "xxsldwi SHW=1",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ },
+ { &test_xxsldwi_2, "xxsldwi SHW=2",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ },
+ { &test_xxsldwi_3, "xxsldwi SHW=3",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+ },
+ { NULL, NULL }
+};
+
+static fp_test_t fp_tests[] = { { &test_fcfids, "fcfids", 1 },
+ { &test_fcfidus, "fcfidus", 1 },
+ { &test_fcfidu, "fcfidu", 1 },
+ { NULL, NULL, 0 },
+
+};
+
+static vx_fp_test_t vx_fp_tests[] = {
+ { &test_xscmp, "xscmp", xscmpX_tests, 64, VX_FP_CMP},
+ { &test_xsadddp, "xsadddp", xsadddp_tests, 64, VX_FP_OTHER},
+ { &test_xsdivdp, "xsdivdp", xsdivdp_tests, 64, VX_FP_OTHER},
+ { &test_xsmadd, "xsmadd", xsmaddXdp_tests, 64, VX_FP_SMA},
+ { &test_xsmsub, "xsmsub", xsmsubXdp_tests, 64, VX_FP_SMS},
+ { &test_xsnmadd, "xsnmadd", xsnmaddXdp_tests, 64, VX_FP_SNMA},
+ { & test_xsmuldp, "xsmuldp", xsmuldp_tests, 64, VX_FP_OTHER},
+ { & test_xssubdp, "xssubdp", xssubdp_tests, 64, VX_FP_OTHER},
+ { NULL, NULL, NULL, 0, 0 }
+};
+
+static xs_conv_test_t xs_conv_tests[] = {
+ { &test_xscvdpsxds, "xscvdpsxds", 15},
+ { &test_xscvsxddp, "xscvsxddp", 15},
+ { &test_xscvuxddp, "xscvuxddp", 15},
+ { NULL, NULL, 0}
+};
+
+#ifdef __powerpc64__
+static void test_ldbrx(void)
+{
+ int i;
+ HWord_t reg_out;
+ unsigned char * byteIn, * byteOut;
+ r14 = (HWord_t)viargs;
+ // Just try the instruction an arbitrary number of times at different r15 offsets.
+ for (i = 0; i < 3; i++) {
+ int j, k;
+ reg_out = 0;
+ r15 = i * 4;
+ __asm__ __volatile__ ("ldbrx %0, %1, %2" : "=r" (reg_out): "b" (r14),"r" (r15));
+ byteIn = ((unsigned char *)(r14 + r15));
+ byteOut = (unsigned char *)®_out;
+
+ printf("ldbrx:");
+ for (k = 0; k < 8; k++) {
+ printf( " %02x", (byteIn[k]));
+ }
+ printf(" (reverse) =>");
+ for (j = 0; j < 8; j++) {
+ printf( " %02x", (byteOut[j]));
+ }
+ printf("\n");
+ }
+ printf( "\n" );
+}
+
+static void
+test_popcntd(void)
+{
+ uint64_t res;
+ unsigned long long src = 0x9182736405504536ULL;
+ r14 = src;
+ __asm__ __volatile__ ("popcntd %0, %1" : "=r" (res): "r" (r14));
+ printf("popcntd: 0x%llx => %d\n", src, (int)res);
+ printf( "\n" );
+}
+#endif
+
+static void
+test_lfiwzx(void)
+{
+ unsigned int i;
+ unsigned int * src;
+ uint64_t reg_out;
+ r14 = (HWord_t)viargs;
+ // Just try the instruction an arbitrary number of times at different r15 offsets.
+ for (i = 0; i < 3; i++) {
+ reg_out = 0;
+ r15 = i * 4;
+ __asm__ __volatile__ ("lfiwzx %0, %1, %2" : "=d" (reg_out): "b" (r14),"r" (r15));
+ src = ((unsigned int *)(r14 + r15));
+ printf("lfiwzx: %u => %llu.00\n", *src, (unsigned long long)reg_out);
+
+ }
+ printf( "\n" );
+}
+
+static void test_vx_fp_ops(void)
+{
+
+ test_func_t func;
+ int k;
+ char * test_name = (char *)malloc(20);
+ k = 0;
+
+ build_special_fargs_table();
+ while ((func = vx_fp_tests[k].test_func)) {
+ int i, condreg, repeat = 0;
+ unsigned int flags;
+ unsigned long long * frap, * frbp, * dst;
+ vx_fp_test_t test_group = vx_fp_tests[k];
+ vx_fp_test_type test_type = test_group.test_type;
+
+ switch (test_type) {
+ case VX_FP_CMP:
+ strcpy(test_name, "xscmp");
+ if (!repeat) {
+ repeat = 1;
+ strcat(test_name, "udp");
+ do_cmpudp = 1;
+ }
+ break;
+ case VX_FP_SMA:
+ case VX_FP_SMS:
+ case VX_FP_SNMA:
+ if (test_type == VX_FP_SMA)
+ strcpy(test_name, "xsmadd");
+ else if (test_type == VX_FP_SMS)
+ strcpy(test_name, "xsmsub");
+ else
+ strcpy(test_name, "xsnmadd");
+ if (!repeat) {
+ repeat = 1;
+ strcat(test_name, "adp");
+ do_adp = 1;
+ }
+ break;
+ case VX_FP_OTHER:
+ strcpy(test_name, test_group.name);
+ break;
+ default:
+ printf("ERROR: Invalid VX FP test type %d\n", test_type);
+ exit(1);
+ }
+
+again:
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int * inA, * inB, * pv;
+ double * dpA = (double *)&vec_inA;
+ double * dpB = (double *)&vec_inB;
+ double * dpT = (double *)&vec_out;
+
+ fp_test_args_t aTest = test_group.targs[i];
+ inA = (unsigned int *)&spec_fargs[aTest.fra_idx];
+ inB = (unsigned int *)&spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ // Only need to copy one doubleword into each vector's element 0
+ if (isLE) {
+ // With LE, vector element 0 is the second doubleword from the left
+ memset(dpA, 0, 8);
+ memset(dpB, 0, 8);
+ dpA++;
+ dpB++;
+ }
+ memcpy(dpA, inA, 8);
+ memcpy(dpB, inB, 8);
+
+ switch (test_type) {
+ case VX_FP_CMP:
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ condreg = (flags & 0x0f000000) >> 24;
+ printf("#%d: %s %016llx <=> %016llx ? %x (CRx)\n", i, test_name, *frap, *frbp, condreg);
+ // printf("\tFRA: %e; FRB: %e\n", spec_fargs[aTest.fra_idx], spec_fargs[aTest.frb_idx]);
+ if ( condreg != aTest.cr_flags) {
+ printf("Error: Expected CR flags 0x%x; actual flags: 0x%x\n", aTest.cr_flags, condreg);
+ }
+ break;
+ case VX_FP_SMA:
+ case VX_FP_SMS:
+ case VX_FP_SNMA:
+ case VX_FP_OTHER:
+ {
+ int idx;
+ unsigned long long vsr_XT;
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (test_type != VX_FP_OTHER) {
+ /* Then we need a third src argument, which is stored in element 0 of
+ * VSX[XT] -- i.e., vec_out. For the xs<ZZZ>mdp cases, VSX[XT] holds
+ * src3 and VSX[XB] holds src2; for the xs<ZZZ>adp cases, VSX[XT] holds
+ * src2 and VSX[XB] holds src3. The fp_test_args_t that holds the test
+ * data (input args) contain only two inputs, so I arbitrarily
+ * use spec_fargs elements 4 and 14 (alternating) for the third source
+ * argument. We can use the same input data for a given pair of
+ * adp/mdp-type instructions by swapping the src2 and src3 arguments; thus
+ * the expected result should be the same.
+ */
+ int extra_arg_idx;
+ if (i % 2)
+ extra_arg_idx = 4;
+ else
+ extra_arg_idx = 14;
+
+ if (repeat) {
+ /* We're on the first time through of one of the VX_FP_SMx
+ * test types, meaning we're testing a xs<ZZZ>adp case, thus we
+ * have to swap inputs as described above:
+ * src2 <= VSX[XT]
+ * src3 <= VSX[XB]
+ */
+ if (isLE)
+ dpT++;
+ memcpy(dpT, inB, 8); // src2
+ memcpy(dpB, &spec_fargs[extra_arg_idx], 8); //src3
+ frbp = (unsigned long long *)&spec_fargs[extra_arg_idx];
+ } else {
+ // Don't need to init src2, as it's done before the switch()
+ if (isLE)
+ dpT++;
+ memcpy(dpT, &spec_fargs[extra_arg_idx], 8); //src3
+ }
+ memcpy(&vsr_XT, dpT, 8);
+ }
+
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ if (isLE)
+ dst++;
+ if (test_type == VX_FP_OTHER)
+ printf("#%d: %s %016llx %016llx = %016llx\n", i, test_name, *frap, *frbp, *dst);
+ else
+ printf( "#%d: %s %016llx %016llx %016llx = %016llx\n", i,
+ test_name, vsr_XT, *frap, *frbp, *dst );
+
+ /*
+ {
+ // Debug code. Keep this block commented out except when debugging.
+ double result, expected;
+ memcpy(&result, dst, 8);
+ memcpy(&expected, &aTest.dp_bin_result, 8);
+ printf( "\tFRA + FRB: %e + %e: Expected = %e; Actual = %e\n",
+ spec_fargs[aTest.fra_idx], spec_fargs[aTest.frb_idx],
+ expected, result );
+ }
+ */
+ break;
+ }
+ }
+
+
+ }
+ printf( "\n" );
+
+ if (repeat) {
+ repeat = 0;
+ switch (test_type) {
+ case VX_FP_CMP:
+ strcpy(test_name, "xscmp");
+ strcat(test_name, "odp");
+ do_cmpudp = 0;
+ break;
+ case VX_FP_SMA:
+ case VX_FP_SMS:
+ case VX_FP_SNMA:
+ if (test_type == VX_FP_SMA)
+ strcpy(test_name, "xsmadd");
+ else if (test_type == VX_FP_SMS)
+ strcpy(test_name, "xsmsub");
+ else
+ strcpy(test_name, "xsnmadd");
+ strcat(test_name, "mdp");
+ do_adp = 0;
+ break;
+ case VX_FP_OTHER:
+ break;
+ }
+ goto again;
+ }
+ k++;
+ }
+ printf( "\n" );
+ free(test_name);
+}
+
+static void test_xs_conv_ops(void)
+{
+
+ test_func_t func;
+ int k = 0;
+ double * dpB = (double *)&vec_inB;
+ if (isLE) {
+ memset(dpB, 0, 8);
+ dpB++;
+ }
+
+ build_special_fargs_table();
+ while ((func = xs_conv_tests[k].test_func)) {
+ int i;
+ unsigned long long * frbp, * dst;
+ xs_conv_test_t test_group = xs_conv_tests[k];
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int * inB, * pv;
+ int idx;
+ inB = (unsigned int *)&spec_fargs[i];
+ frbp = (unsigned long long *)&spec_fargs[i];
+
+ memcpy(dpB, inB, 8);
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ if (isLE)
+ dst++;
+ printf("#%d: %s %016llx => %016llx\n", i, test_group.name, *frbp, *dst);
+
+ }
+ k++;
+ printf("\n");
+ }
+ printf( "\n" );
+}
+
+static void do_load_test(ldst_test_t loadTest)
+{
+ test_func_t func;
+ unsigned int *src, *dst;
+ int splat = loadTest.type == VSX_LOAD_SPLAT ? 1: 0;
+ int i, j, m, k;
+ i = j = 0;
+
+ func = loadTest.test_func;
+ for (i = 0, r14 = (HWord_t) loadTest.base_addr; i < NUM_VIARGS_VECS; i++) {
+ int again;
+ j = 0;
+ r14 += i * 16;
+ do {
+ unsigned int * pv = (unsigned int *)&vec_out;
+ int idx;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv+=idx)
+ *pv = 0;
+
+ again = 0;
+ r15 = j;
+
+ // execute test insn
+ (*func)();
+
+ src = (unsigned int*) (((unsigned char *)r14) + j);
+ dst = (unsigned int*) &vec_out;
+
+ printf( "%s:", loadTest.name);
+ for (m = 0; m < loadTest.num_words_to_process; m++) {
+ printf( " %08x", src[splat ? m % 2 : m]);
+ }
+ printf( " =>");
+ m = 0;
+ k = loadTest.num_words_to_process;
+ if (isLE) {
+ if (loadTest.num_words_to_process == 2) {
+ m = 2;
+ k += 2;
+ }
+ }
+
+ for (; m < k; m++) {
+ printf( " %08x", dst[m]);
+ }
+ printf("\n");
+ if (j == 0 && loadTest.offset) {
+ again = 1;
+ j += loadTest.offset;
+ }
+ }
+ while (again);
+ }
+}
+
+static void
+do_store_test ( ldst_test_t storeTest )
+{
+ test_func_t func;
+ unsigned int *src, *dst;
+ int m;
+
+ func = storeTest.test_func;
+ r14 = (HWord_t) storeTest.base_addr;
+ r15 = (HWord_t) storeTest.offset;
+ unsigned int * pv = (unsigned int *) storeTest.base_addr;
+ int idx;
+ // clear out storage destination
+ for (idx = 0; idx < 4; idx++, pv += idx)
+ *pv = 0;
+
+ memcpy(&vec_inA, &viargs[0], sizeof(vector unsigned char));
+
+ // execute test insn
+ (*func)();
+ src = &viargs[0];
+ dst = (unsigned int*) (((unsigned char *) r14) + storeTest.offset);
+
+ printf( "%s:", storeTest.name );
+ for (m = 0; m < storeTest.num_words_to_process; m++) {
+ printf( " %08x", src[m] );
+ }
+ printf( " =>" );
+ for (m = 0; m < storeTest.num_words_to_process; m++) {
+ printf( " %08x", dst[m] );
+ }
+ printf( "\n" );
+}
+
+
+static void test_ldst(void)
+{
+ int k = 0;
+
+ while (ldst_tests[k].test_func) {
+ if (ldst_tests[k].type == VSX_STORE)
+ do_store_test(ldst_tests[k]);
+ else
+ do_load_test(ldst_tests[k]);
+ k++;
+ printf("\n");
+ }
+}
+
+static void test_ftdiv(void)
+{
+ int i, num_tests, crx;
+ unsigned int flags;
+ unsigned long long * frap, * frbp;
+ build_special_fargs_table();
+
+ num_tests = sizeof ftdiv_tests/sizeof ftdiv_tests[0];
+
+ for (i = 0; i < num_tests; i++) {
+ fp_test_args_t aTest = ftdiv_tests[i];
+ f14 = spec_fargs[aTest.fra_idx];
+ f15 = spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("ftdiv cr1, %0, %1" : : "d" (f14), "d" (f15));
+ GET_CR(flags);
+ crx = (flags & 0x0f000000) >> 24;
+ printf( "ftdiv: %016llx <=> %016llx ? %x (CRx)\n", *frap, *frbp, crx);
+// printf("\tFRA: %e; FRB: %e\n", f14, f15);
+ if ( crx != aTest.cr_flags) {
+ printf("Error: Expected CR flags 0x%x; actual flags: 0x%x\n", aTest.cr_flags, crx);
+ }
+ }
+ printf( "\n" );
+}
+
+
+static void test_p7_fpops ( void )
+{
+ int k = 0;
+ test_func_t func;
+
+ build_fargs_table();
+ while ((func = fp_tests[k].test_func)) {
+ float res;
+ double resd;
+ unsigned long long u0;
+ int i;
+ int res32 = strcmp(fp_tests[k].name, "fcfidu");
+
+ for (i = 0; i < nb_fargs; i++) {
+ u0 = *(unsigned long long *) (&fargs[i]);
+ f14 = fargs[i];
+ (*func)();
+ if (res32) {
+ res = f17;
+ printf( "%s %016llx => (raw sp) %08x)",
+ fp_tests[k].name, u0, *((unsigned int *)&res));
+ } else {
+ resd = f17;
+ printf( "%s %016llx => (raw sp) %016llx)",
+ fp_tests[k].name, u0, *(unsigned long long *)(&resd));
+ }
+ printf( "\n" );
+ }
+
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_vsx_logic(void)
+{
+ logic_test_t aTest;
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = logic_tests[k].test_func)) {
+ unsigned int * pv;
+ int startA, startB;
+ unsigned int * inA, * inB, * dst;
+ int idx, i;
+ startA = 0;
+ aTest = logic_tests[k];
+ for (i = 0; i <= (NUM_VIARGS_INTS - (NUM_VIARGS_VECS * sizeof(int))); i++, startA++) {
+ startB = startA + 4;
+ pv = (unsigned int *)&vec_out;
+ inA = &viargs[startA];
+ inB = &viargs[startB];
+ memcpy(&vec_inA, inA, sizeof(vector unsigned char));
+ memcpy(&vec_inB, inB, sizeof(vector unsigned char));
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ // execute test insn
+ (*func)();
+ dst = (unsigned int*) &vec_out;
+
+ printf( "%s:", aTest.name);
+ printf( " %08x %08x %08x %08x %s", inA[0], inA[1], inA[2], inA[3], aTest.name);
+ printf( " %08x %08x %08x %08x", inB[0], inB[1], inB[2], inB[3]);
+ printf(" => %08x %08x %08x %08x\n", dst[0], dst[1], dst[2], dst[3]);
+
+ }
+ k++;
+ }
+ printf( "\n" );
+}
+
+static vector unsigned long long vec_args[] __attribute__ ((aligned (16))) =
+{
+ { 0x0123456789abcdefULL, 0x0011223344556677ULL},
+ { 0x8899aabb19293942ULL, 0xa1a2a3a4b1b2b3b4ULL},
+ { 0xc1c2c3c4d1d2d3d4ULL, 0x7a6b5d3efc032778ULL}
+};
+#define NUM_VEC_ARGS_LONGS (sizeof vec_args/sizeof vec_args[0])
+
+static void test_move_ops (void)
+{
+ move_test_t aTest;
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = move_tests[k].test_func)) {
+ unsigned int * pv;
+ int startA, startB;
+ unsigned long long * inA, * inB, * dst;
+ int use_vecA = (strcmp(move_tests[k].name, "xscpsgndp") == 0);
+ int idx;
+ inA = NULL;
+ aTest = move_tests[k];
+ for (startB = 0; startB < NUM_VEC_ARGS_LONGS; startB++) {
+ inB = (unsigned long long *)&vec_args[startB];
+ memcpy(&vec_inB, inB, sizeof(vector unsigned char));
+ if (isLE)
+ inB++;
+ startA = 0;
+repeat:
+ if (use_vecA) {
+ inA = (unsigned long long *)&vec_args[startA];
+ memcpy(&vec_inA, inA, sizeof(vector unsigned char));
+ startA++;
+ }
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ // execute test insn
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ if (isLE) {
+ dst++;
+ inA++;
+ }
+
+ printf( "%s:", aTest.name);
+ if (use_vecA)
+ printf( " X[A]: %016llx ", *inA);
+ printf( " X[B]: %016llx", *inB);
+ printf(" => %016llx\n", *dst);
+
+ if (use_vecA && startA < NUM_VEC_ARGS_LONGS)
+ goto repeat;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_permute_ops (void)
+{
+ permute_test_t *aTest;
+ unsigned int *dst = (unsigned int *) &vec_out;
+
+ for (aTest = &(permute_tests[0]); aTest->test_func != NULL; aTest++)
+ {
+ /* Grab test input and clear output vector. */
+ memcpy(&vec_inA, aTest->xa, sizeof(vec_inA));
+ memcpy(&vec_inB, aTest->xb, sizeof(vec_inB));
+ memset(dst, 0, sizeof(vec_out));
+
+ /* execute test insn */
+ aTest->test_func();
+
+ printf( "%s:\n", aTest->name);
+ printf( " XA[%08x,%08x,%08x,%08x]\n",
+ aTest->xa[0], aTest->xa[1], aTest->xa[2], aTest->xa[3]);
+ printf( " XB[%08x,%08x,%08x,%08x]\n",
+ aTest->xb[0], aTest->xb[1], aTest->xb[2], aTest->xb[3]);
+ printf( " => XT[%08x,%08x,%08x,%08x]\n",
+ dst[0], dst[1], dst[2], dst[3]);
+
+ }
+ printf( "\n" );
+}
+
+static test_table_t all_tests[] = { { &test_ldst,
+ "Test VSX load/store instructions" },
+ { &test_vsx_logic,
+ "Test VSX logic instructions" },
+#ifdef __powerpc64__
+ { &test_ldbrx,
+ "Test ldbrx instruction" },
+ { &test_popcntd,
+ "Test popcntd instruction" },
+#endif
+ { &test_lfiwzx,
+ "Test lfiwzx instruction" },
+ { &test_p7_fpops,
+ "Test P7 floating point convert instructions"},
+ { &test_ftdiv,
+ "Test ftdiv instruction" },
+ { &test_move_ops,
+ "Test VSX move instructions"},
+ { &test_permute_ops,
+ "Test VSX permute instructions"},
+ { &test_vx_fp_ops,
+ "Test VSX floating point instructions"},
+ { &test_xs_conv_ops,
+ "Test VSX scalar integer conversion instructions" },
+ { NULL, NULL }
+};
+#endif // HAS_VSX
+
+int main(int argc, char *argv[])
+{
+#ifdef HAS_VSX
+
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+
+#endif // HAS _VSX
+
+ return 0;
+}
diff --git a/none/tests/ppc64/test_isa_2_06_part2.c b/none/tests/ppc64/test_isa_2_06_part2.c
deleted file mode 120000
index e86c1a0..0000000
--- a/none/tests/ppc64/test_isa_2_06_part2.c
+++ /dev/null
@@ -1 +0,0 @@
-../../../none/tests/ppc32/test_isa_2_06_part2.c
\ No newline at end of file
diff --git a/none/tests/ppc64/test_isa_2_06_part2.c b/none/tests/ppc64/test_isa_2_06_part2.c
new file mode 100644
index 0000000..b33849a
--- /dev/null
+++ b/none/tests/ppc64/test_isa_2_06_part2.c
@@ -0,0 +1,1793 @@
+/* Copyright (C) 2011 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#ifdef HAS_VSX
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <malloc.h>
+#include <altivec.h>
+#include <math.h>
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif /* __powerpc64__ */
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+
+#ifdef VGP_ppc64le_linux
+#define isLE 1
+#else
+#define isLE 0
+#endif
+
+register HWord_t r14 __asm__ ("r14");
+register HWord_t r15 __asm__ ("r15");
+register HWord_t r16 __asm__ ("r16");
+register HWord_t r17 __asm__ ("r17");
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+
+static volatile unsigned int div_flags, div_xer;
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+
+typedef void (*test_func_t)(void);
+typedef struct test_table test_table_t;
+
+
+/* These functions below that construct a table of floating point
+ * values were lifted from none/tests/ppc32/jm-insns.c.
+ */
+
+#if defined (DEBUG_ARGS_BUILD)
+#define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define AB_DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+static inline void register_farg (void *farg,
+ int s, uint16_t _exp, uint64_t mant)
+{
+ uint64_t tmp;
+
+ tmp = ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
+ *(uint64_t *)farg = tmp;
+ AB_DPRINTF("%d %03x %013llx => %016llx %0e\n",
+ s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
+}
+
+static inline void register_sp_farg (void *farg,
+ int s, uint16_t _exp, uint32_t mant)
+{
+ uint32_t tmp;
+ tmp = ((uint32_t)s << 31) | ((uint32_t)_exp << 23) | mant;
+ *(uint32_t *)farg = tmp;
+}
+
+typedef struct fp_test_args {
+ int fra_idx;
+ int frb_idx;
+} fp_test_args_t;
+
+
+fp_test_args_t fp_cmp_tests[] = {
+ {8, 8},
+ {8, 14},
+ {8, 6},
+ {8, 5},
+ {8, 4},
+ {8, 7},
+ {8, 9},
+ {8, 11},
+ {14, 8},
+ {14, 14},
+ {14, 6},
+ {14, 5},
+ {14, 4},
+ {14, 7},
+ {14, 9},
+ {14, 11},
+ {6, 8},
+ {6, 14},
+ {6, 6},
+ {6, 5},
+ {6, 4},
+ {6, 7},
+ {6, 9},
+ {6, 11},
+ {5, 8},
+ {5, 14},
+ {5, 6},
+ {5, 5},
+ {5, 4},
+ {5, 7},
+ {5, 9},
+ {5, 11},
+ {4, 8},
+ {4, 14},
+ {4, 6},
+ {4, 5},
+ {4, 1},
+ {4, 7},
+ {4, 9},
+ {4, 11},
+ {7, 8},
+ {7, 14},
+ {7, 6},
+ {7, 5},
+ {7, 4},
+ {7, 7},
+ {7, 9},
+ {7, 11},
+ {10, 8},
+ {10, 14},
+ {10, 6},
+ {10, 5},
+ {10, 4},
+ {10, 7},
+ {10, 9},
+ {10, 10},
+ {12, 8},
+ {12, 14},
+ {12, 6},
+ {12, 5},
+ {1, 1},
+ {2, 2},
+ {3, 3},
+ {4, 4},
+};
+
+
+fp_test_args_t two_arg_fp_tests[] = {
+ {8, 8},
+ {8, 14},
+ {15, 16},
+ {8, 5},
+ {8, 4},
+ {8, 7},
+ {8, 9},
+ {8, 11},
+ {14, 8},
+ {14, 14},
+ {14, 6},
+ {14, 5},
+ {14, 4},
+ {14, 7},
+ {14, 9},
+ {14, 11},
+ {6, 8},
+ {6, 14},
+ {6, 6},
+ {6, 5},
+ {6, 4},
+ {6, 7},
+ {6, 9},
+ {6, 11},
+ {5, 8},
+ {5, 14},
+ {5, 6},
+ {5, 5},
+ {5, 4},
+ {5, 7},
+ {5, 9},
+ {5, 11},
+ {4, 8},
+ {4, 14},
+ {4, 6},
+ {4, 5},
+ {4, 1},
+ {4, 7},
+ {4, 9},
+ {4, 11},
+ {7, 8},
+ {7, 14},
+ {7, 6},
+ {7, 5},
+ {7, 4},
+ {7, 7},
+ {7, 9},
+ {7, 11},
+ {10, 8},
+ {10, 14},
+ {12, 6},
+ {12, 5},
+ {10, 4},
+ {10, 7},
+ {10, 9},
+ {10, 11},
+ {12, 8 },
+ {12, 14},
+ {12, 6},
+ {15, 16},
+ {15, 16},
+ {9, 11},
+ {11, 11},
+ {11, 12}
+};
+
+
+static int nb_special_fargs;
+static double * spec_fargs;
+static float * spec_sp_fargs;
+
+static void build_special_fargs_table(void)
+{
+/*
+ Entry Sign Exp fraction Special value
+ 0 0 3fd 0x8000000000000ULL Positive finite number
+ 1 0 404 0xf000000000000ULL ...
+ 2 0 001 0x8000000b77501ULL ...
+ 3 0 7fe 0x800000000051bULL ...
+ 4 0 012 0x3214569900000ULL ...
+ 5 0 000 0x0000000000000ULL +0.0 (+zero)
+ 6 1 000 0x0000000000000ULL -0.0 (-zero)
+ 7 0 7ff 0x0000000000000ULL +infinity
+ 8 1 7ff 0x0000000000000ULL -infinity
+ 9 0 7ff 0x7FFFFFFFFFFFFULL +SNaN
+ 10 1 7ff 0x7FFFFFFFFFFFFULL -SNaN
+ 11 0 7ff 0x8000000000000ULL +QNaN
+ 12 1 7ff 0x8000000000000ULL -QNaN
+ 13 1 000 0x8340000078000ULL Denormalized val (zero exp and non-zero fraction)
+ 14 1 40d 0x0650f5a07b353ULL Negative finite number
+ 15 0 412 0x32585a9900000ULL A couple more positive finite numbers
+ 16 0 413 0x82511a2000000ULL ...
+*/
+
+ uint64_t mant;
+ uint32_t mant_sp;
+ uint16_t _exp;
+ int s;
+ int j, i = 0;
+
+ if (spec_fargs)
+ return;
+
+ spec_fargs = malloc( 17 * sizeof(double) );
+ spec_sp_fargs = malloc( 17 * sizeof(float) );
+
+ // #0
+ s = 0;
+ _exp = 0x3fd;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #1
+ s = 0;
+ _exp = 0x404;
+ mant = 0xf000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* None of the ftdiv tests succeed.
+ * FRA = value #0; FRB = value #1
+ * ea_ = -2; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 100
+ */
+
+ /*************************************************
+ * fe_flag tests
+ *
+ *************************************************/
+
+ /* fe_flag <- 1 if FRA is a NaN
+ * FRA = value #9; FRB = value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRB is a NaN
+ * FRA = value #1; FRB = value #12
+ * e_a = 5; e_b = 1024
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if e_b <= -1022
+ * FRA = value #0; FRB = value #2
+ * e_a = -2; e_b = -1022
+ * fl_flag || fg_flag || fe_flag = 101
+ *
+ */
+ // #2
+ s = 0;
+ _exp = 0x001;
+ mant = 0x8000000b77501ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* fe_flag <- 1 if e_b >= 1021
+ * FRA = value #1; FRB = value #3
+ * e_a = 5; e_b = 1023
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+ // #3
+ s = 0;
+ _exp = 0x7fe;
+ mant = 0x800000000051bULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* fe_flag <- 1 if FRA != 0 && e_a - e_b >= 1023
+ * Let FRA = value #3 and FRB be value #0.
+ * e_a = 1023; e_b = -2
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRA != 0 && e_a - e_b <= -1023
+ * Let FRA = value #0 above and FRB be value #3 above
+ * e_a = -2; e_b = 1023
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+
+ /* fe_flag <- 1 if FRA != 0 && e_a <= -970
+ * Let FRA = value #4 and FRB be value #0
+ * e_a = -1005; e_b = -2
+ * fl_flag || fg_flag || fe_flag = 101
+ */
+ // #4
+ s = 0;
+ _exp = 0x012;
+ mant = 0x3214569900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /*************************************************
+ * fg_flag tests
+ *
+ *************************************************/
+ /* fg_flag <- 1 if FRA is an Infinity
+ * NOTE: FRA = Inf also sets fe_flag
+ * Do two tests, using values #7 and #8 (+/- Inf) for FRA.
+ * Test 1:
+ * Let FRA be value #7 and FRB be value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 111
+ *
+ * Test 2:
+ * Let FRA be value #8 and FRB be value #1
+ * e_a = 1024; e_b = 5
+ * fl_flag || fg_flag || fe_flag = 111
+ *
+ */
+
+ /* fg_flag <- 1 if FRB is an Infinity
+ * NOTE: FRB = Inf also sets fe_flag
+ * Let FRA be value #1 and FRB be value #7
+ * e_a = 5; e_b = 1024
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is denormalized
+ * NOTE: e_b < -1022 ==> fe_flag <- 1
+ * Let FRA be value #0 and FRB be value #13
+ * e_a = -2; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is +zero
+ * NOTE: FRA = Inf also sets fe_flag
+ * Let FRA = val #5; FRB = val #5
+ * ea_ = -1023; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* fg_flag <- 1 if FRB is -zero
+ * NOTE: FRA = Inf also sets fe_flag
+ * Let FRA = val #5; FRB = val #6
+ * ea_ = -1023; e_b = -1023
+ * fl_flag || fg_flag || fe_flag = 111
+ */
+
+ /* Special values */
+ /* +0.0 : 0 0x000 0x0000000000000 */
+ // #5
+ s = 0;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -0.0 : 1 0x000 0x0000000000000 */
+ // #6
+ s = 1;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +infinity : 0 0x7FF 0x0000000000000 */
+ // #7
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -infinity : 1 0x7FF 0x0000000000000 */
+ // #8
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /*
+ * This comment applies to values #9 and #10 below:
+ * When src is a SNaN, it's converted to a QNaN first before rounding to single-precision,
+ * so we can't just copy the double-precision value to the corresponding slot in the
+ * single-precision array (i.e., in the loop at the end of this function). Instead, we
+ * have to manually set the bits using register_sp_farg().
+ */
+
+ /* +SNaN : 0 0x7FF 0x7FFFFFFFFFFFF */
+ // #9
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+ _exp = 0xff;
+ mant_sp = 0x3FFFFF;
+ register_sp_farg(&spec_sp_fargs[i-1], s, _exp, mant_sp);
+
+ /* -SNaN : 1 0x7FF 0x7FFFFFFFFFFFF */
+ // #10
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+ _exp = 0xff;
+ mant_sp = 0x3FFFFF;
+ register_sp_farg(&spec_sp_fargs[i-1], s, _exp, mant_sp);
+
+ /* +QNaN : 0 0x7FF 0x8000000000000 */
+ // #11
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -QNaN : 1 0x7FF 0x8000000000000 */
+ // #12
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* denormalized value */
+ // #13
+ s = 1;
+ _exp = 0x000;
+ mant = 0x8340000078000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* Negative finite number */
+ // #14
+ s = 1;
+ _exp = 0x40d;
+ mant = 0x0650f5a07b353ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* A couple positive finite numbers ... */
+ // #15
+ s = 0;
+ _exp = 0x412;
+ mant = 0x32585a9900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #16
+ s = 0;
+ _exp = 0x413;
+ mant = 0x82511a2000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ nb_special_fargs = i;
+ for (j = 0; j < i; j++) {
+ if (!(j == 9 || j == 10))
+ spec_sp_fargs[j] = spec_fargs[j];
+ }
+}
+
+
+struct test_table
+{
+ test_func_t test_category;
+ char * name;
+};
+
+typedef enum {
+ SINGLE_TEST,
+ DOUBLE_TEST
+} precision_type_t;
+
+typedef enum {
+ VX_SCALAR_FP_NMSUB = 0,
+ // ALL VECTOR-TYPE OPS SHOULD BE ADDED AFTER THIS LINE
+ VX_VECTOR_FP_MULT_AND_OP2 = 10,
+ // and before this line
+ VX_BASIC_CMP = 30,
+ VX_CONV_WORD,
+ VX_DEFAULT
+} vx_fp_test_type;
+
+typedef struct vx_fp_test
+{
+ test_func_t test_func;
+ const char * name;
+ fp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ vx_fp_test_type type;
+ const char * op;
+} vx_fp_test_t;
+
+static vector unsigned int vec_out, vec_inA, vec_inB, vec_inC;
+
+static Bool do_dot;
+static void test_xvcmpeqdp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpeqdp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpeqdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpgedp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpgedp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpgedp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpgtdp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpgtdp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpgtdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpeqsp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpeqsp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpeqsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpgesp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpgesp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpgesp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcmpgtsp(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("xvcmpgtsp. %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvcmpgtsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static Bool do_aXp;
+static Bool do_dp;
+static void test_xsnmsub(void)
+{
+ if (do_aXp)
+ __asm__ __volatile__ ("xsnmsubadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xsnmsubmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmadd(void)
+{
+ if (do_aXp)
+ if (do_dp)
+ __asm__ __volatile__ ("xvmaddadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvmaddasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ if (do_dp)
+ __asm__ __volatile__ ("xvmaddmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvmaddmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvnmadd(void)
+{
+ if (do_aXp)
+ if (do_dp)
+ __asm__ __volatile__ ("xvnmaddadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvnmaddasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ if (do_dp)
+ __asm__ __volatile__ ("xvnmaddmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvnmaddmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvnmsub(void)
+{
+ if (do_aXp)
+ if (do_dp)
+ __asm__ __volatile__ ("xvnmsubadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvnmsubasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ if (do_dp)
+ __asm__ __volatile__ ("xvnmsubmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvnmsubmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmsub(void)
+{
+ if (do_aXp)
+ if (do_dp)
+ __asm__ __volatile__ ("xvmsubadp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvmsubasp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ if (do_dp)
+ __asm__ __volatile__ ("xvmsubmdp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+ else
+ __asm__ __volatile__ ("xvmsubmsp %x0, %x1, %x2" : "+wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xssqrtdp(void)
+{
+ __asm__ __volatile__ ("xssqrtdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpim(void)
+{
+ __asm__ __volatile__ ("xsrdpim %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpip(void)
+{
+ __asm__ __volatile__ ("xsrdpip %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xstdivdp(void)
+{
+ __asm__ __volatile__ ("xstdivdp 6, %x0, %x1" : : "wa" (vec_inA), "wa" (vec_inB));
+}
+
+static void test_xsmaxdp(void)
+{
+ __asm__ __volatile__ ("xsmaxdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xsmindp(void)
+{
+ __asm__ __volatile__ ("xsmindp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvadddp(void)
+{
+ __asm__ __volatile__ ("xvadddp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvaddsp(void)
+{
+ __asm__ __volatile__ ("xvaddsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvdivdp(void)
+{
+ __asm__ __volatile__ ("xvdivdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvdivsp(void)
+{
+ __asm__ __volatile__ ("xvdivsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmuldp(void)
+{
+ __asm__ __volatile__ ("xvmuldp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmulsp(void)
+{
+ __asm__ __volatile__ ("xvmulsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvsubdp(void)
+{
+ __asm__ __volatile__ ("xvsubdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmaxdp(void)
+{
+ __asm__ __volatile__ ("xvmaxdp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmindp(void)
+{
+ __asm__ __volatile__ ("xvmindp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvmaxsp(void)
+{
+ __asm__ __volatile__ ("xvmaxsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvminsp(void)
+{
+ __asm__ __volatile__ ("xvminsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvsubsp(void)
+{
+ __asm__ __volatile__ ("xvsubsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvresp(void)
+{
+ __asm__ __volatile__ ("xvresp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xxsel(void)
+{
+ unsigned long long * dst;
+ unsigned long long xa[] = { 0xa12bc37de56f9708ULL, 0x3894c1fddeadbeefULL};
+ unsigned long long xb[] = { 0xfedc432124681235ULL, 0xf1e2d3c4e0057708ULL};
+ unsigned long long xc[] = { 0xffffffff01020304ULL, 0x128934bd00000000ULL};
+
+ memcpy(&vec_inA, xa, 16);
+ memcpy(&vec_inB, xb, 16);
+ memcpy(&vec_inC, xc, 16);
+
+
+ __asm__ __volatile__ ("xxsel %x0, %x1, %x2, %x3" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB),"wa" (vec_inC));
+ dst = (unsigned long long *) &vec_out;
+ printf("xxsel %016llx,%016llx,%016llx => %016llx\n", xa[0], xb[0], xc[0], *dst);
+ dst++;
+ printf("xxsel %016llx,%016llx,%016llx => %016llx\n", xa[1], xb[1], xc[1], *dst);
+ printf("\n");
+}
+
+static void test_xxspltw(void)
+{
+ int uim;
+ unsigned long long * dst = NULL;
+ unsigned int xb[] = { 0xfedc4321, 0x24681235, 0xf1e2d3c4, 0xe0057708};
+ int i;
+ void * vecB_ptr = &vec_inB;
+ if (isLE) {
+ for (i = 3; i >=0; i--) {
+ memcpy(vecB_ptr, &xb[i], 4);
+ vecB_ptr+=4;
+ }
+ } else {
+ for (i = 0; i < 4; i++) {
+ memcpy(vecB_ptr, &xb[i], 4);
+ vecB_ptr+=4;
+ }
+ }
+
+ for (uim = 0; uim < 4; uim++) {
+ switch (uim) {
+ case 0:
+ __asm__ __volatile__ ("xxspltw %x0, %x1, 0" : "=wa" (vec_out): "wa" (vec_inB));
+ break;
+ case 1:
+ __asm__ __volatile__ ("xxspltw %x0, %x1, 1" : "=wa" (vec_out): "wa" (vec_inB));
+ break;
+ case 2:
+ __asm__ __volatile__ ("xxspltw %x0, %x1, 2" : "=wa" (vec_out): "wa" (vec_inB));
+ break;
+ case 3:
+ __asm__ __volatile__ ("xxspltw %x0, %x1, 3" : "=wa" (vec_out): "wa" (vec_inB));
+ break;
+ }
+ dst = (unsigned long long *) &vec_out;
+ printf("xxspltw 0x%08x%08x%08x%08x %d=> 0x%016llx", xb[0], xb[1],
+ xb[2], xb[3], uim, *dst);
+ dst++;
+ printf("%016llx\n", *dst);
+ }
+ printf("\n");
+}
+
+static void test_xscvdpsxws(void)
+{
+ __asm__ __volatile__ ("xscvdpsxws %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvdpuxds(void)
+{
+ __asm__ __volatile__ ("xscvdpuxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcpsgndp(void)
+{
+ __asm__ __volatile__ ("xvcpsgndp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcpsgnsp(void)
+{
+ __asm__ __volatile__ ("xvcpsgnsp %x0, %x1, %x2" : "=wa" (vec_out): "wa" (vec_inA),"wa" (vec_inB));
+}
+
+static void test_xvcvdpsxws(void)
+{
+ __asm__ __volatile__ ("xvcvdpsxws %x0, %x1 " : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspsxws(void)
+{
+ __asm__ __volatile__ ("xvcvspsxws %x0, %x1 " : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static vx_fp_test_t
+vx_vector_one_fp_arg_tests[] = {
+ { &test_xvresp, "xvresp", NULL, 16, SINGLE_TEST, VX_BASIC_CMP, "1/x"},
+ { &test_xvcvdpsxws, "xvcvdpsxws", NULL, 16, DOUBLE_TEST, VX_CONV_WORD, "conv"},
+ { &test_xvcvspsxws, "xvcvspsxws", NULL, 16, SINGLE_TEST, VX_CONV_WORD, "conv"},
+ { NULL, NULL, NULL, 0 , 0, 0, NULL}
+};
+
+static vx_fp_test_t
+vx_vector_fp_tests[] = {
+ { &test_xvcmpeqdp, "xvcmpeqdp", fp_cmp_tests, 64, DOUBLE_TEST, VX_BASIC_CMP, "eq"},
+ { &test_xvcmpgedp, "xvcmpgedp", fp_cmp_tests, 64, DOUBLE_TEST, VX_BASIC_CMP, "ge"},
+ { &test_xvcmpgtdp, "xvcmpgtdp", fp_cmp_tests, 64, DOUBLE_TEST, VX_BASIC_CMP, "gt"},
+ { &test_xvcmpeqsp, "xvcmpeqsp", fp_cmp_tests, 64, SINGLE_TEST, VX_BASIC_CMP, "eq"},
+ { &test_xvcmpgesp, "xvcmpgesp", fp_cmp_tests, 64, SINGLE_TEST, VX_BASIC_CMP, "ge"},
+ { &test_xvcmpgtsp, "xvcmpgtsp", fp_cmp_tests, 64, SINGLE_TEST, VX_BASIC_CMP, "gt"},
+ { &test_xvadddp, "xvadddp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "+" },
+ { &test_xvaddsp, "xvaddsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "+" },
+ { &test_xvdivdp, "xvdivdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "/" },
+ { &test_xvdivsp, "xvdivsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "/" },
+ { &test_xvmuldp, "xvmuldp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "*" },
+ { &test_xvmulsp, "xvmulsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "*" },
+ { &test_xvsubdp, "xvsubdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "-" },
+ { &test_xvsubsp, "xvsubsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "-" },
+ { &test_xvmaxdp, "xvmaxdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "@max@" },
+ { &test_xvmindp, "xvmindp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "@min@" },
+ { &test_xvmaxsp, "xvmaxsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "@max@" },
+ { &test_xvminsp, "xvminsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "@min@" },
+ { &test_xvcpsgndp, "xvcpsgndp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, "+-cp"},
+ { &test_xvcpsgnsp, "xvcpsgnsp", two_arg_fp_tests, 64, SINGLE_TEST, VX_DEFAULT, "+-cp"},
+ { NULL, NULL, NULL, 0 , 0, 0, NULL}
+};
+
+
+static vx_fp_test_t
+vx_aORm_fp_tests[] = {
+ { &test_xsnmsub, "xsnmsub", two_arg_fp_tests, 64, DOUBLE_TEST, VX_SCALAR_FP_NMSUB, "!*-"},
+ { &test_xvmadd, "xvmadd", two_arg_fp_tests, 64, DOUBLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "*+"},
+ { &test_xvmadd, "xvmadd", two_arg_fp_tests, 64, SINGLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "*+"},
+ { &test_xvnmadd, "xvnmadd", two_arg_fp_tests, 64, DOUBLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "!*+"},
+ { &test_xvnmadd, "xvnmadd", two_arg_fp_tests, 64, SINGLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "!*+"},
+ { &test_xvmsub, "xvmsub", two_arg_fp_tests, 64, DOUBLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "*-"},
+ { &test_xvmsub, "xvmsub", two_arg_fp_tests, 64, SINGLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "*-"},
+ { &test_xvnmsub, "xvnmsub", two_arg_fp_tests, 64, DOUBLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "!*-"},
+ { &test_xvnmsub, "xvnmsub", two_arg_fp_tests, 64, SINGLE_TEST, VX_VECTOR_FP_MULT_AND_OP2, "!*-"},
+ { NULL, NULL, NULL, 0, 0, 0, NULL }
+};
+
+static vx_fp_test_t
+vx_simple_scalar_fp_tests[] = {
+ { &test_xssqrtdp, "xssqrtdp", NULL, 17, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xsrdpim, "xsrdpim", NULL, 17, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xsrdpip, "xsrdpip", NULL, 17, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xstdivdp, "xstdivdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xsmaxdp, "xsmaxdp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xsmindp, "xsmindp", two_arg_fp_tests, 64, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { &test_xscvdpsxws, "xscvdpsxws", NULL, 17, DOUBLE_TEST, VX_CONV_WORD, NULL},
+ { &test_xscvdpuxds, "xscvdpuxds", NULL, 17, DOUBLE_TEST, VX_DEFAULT, NULL},
+ { NULL, NULL, NULL, 0, 0, 0, NULL }
+};
+
+
+#ifdef __powerpc64__
+static void test_bpermd(void)
+{
+ /* NOTE: Bit number is '0 . . . 63'
+ *
+ * Permuted bits are generated bit 0 -7 as follows:
+ * index = (r14)8*i:8*i+7
+ * perm[i] = (r15)index
+ *
+ * So, for i = 0, index is (r14)8*0:8*0+7, or (r14)0:7, which is the MSB
+ * byte of r14, 0x1b(27/base 10). This identifies bit 27 of r15, which is '1'.
+ * For i = 1, index is 0x2c, identifying bit 44 of r15, which is '1'.
+ * So the result of the first two iterations of i are:
+ * perm = 0b01xxxxxx
+ *
+ */
+ r15 = 0xa12bc37de56f9708ULL;
+ r14 = 0x1b2c31f030000001ULL;
+ __asm__ __volatile__ ("bpermd %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ printf("bpermd: 0x%016llx : 0x%016llx => 0x%llx\n", (unsigned long long)r14,
+ (unsigned long long)r15, (unsigned long long)r17);
+ printf("\n");
+}
+#endif
+
+static Bool do_OE;
+typedef enum {
+ DIV_BASE = 1,
+ DIV_OE = 2,
+ DIV_DOT = 4,
+} div_type_t;
+/* Possible divde type combinations are:
+ * - base
+ * - base+dot
+ * - base+OE
+ * - base+OE+dot
+ */
+#ifdef __powerpc64__
+static void test_divde(void)
+{
+ int divde_type = DIV_BASE;
+ if (do_OE)
+ divde_type |= DIV_OE;
+ if (do_dot)
+ divde_type |= DIV_DOT;
+
+ switch (divde_type) {
+ case 1:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divde %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 3:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeo %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 5:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divde. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 7:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeo. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ default:
+ fprintf(stderr, "Invalid divde type. Exiting\n");
+ exit(1);
+ }
+}
+#endif
+
+static void test_divweu(void)
+{
+ int divweu_type = DIV_BASE;
+ if (do_OE)
+ divweu_type |= DIV_OE;
+ if (do_dot)
+ divweu_type |= DIV_DOT;
+
+ switch (divweu_type) {
+ case 1:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweu %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 3:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweuo %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 5:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweu. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 7:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweuo. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ default:
+ fprintf(stderr, "Invalid divweu type. Exiting\n");
+ exit(1);
+ }
+}
+
+static void test_fctiduz(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("fctiduz. %0, %1" : "=d" (f17) : "d" (f14));
+ else
+ __asm__ __volatile__ ("fctiduz %0, %1" : "=d" (f17) : "d" (f14));
+}
+
+static void test_fctidu(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("fctidu. %0, %1" : "=d" (f17) : "d" (f14));
+ else
+ __asm__ __volatile__ ("fctidu %0, %1" : "=d" (f17) : "d" (f14));
+}
+
+static void test_fctiwuz(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("fctiwuz. %0, %1" : "=d" (f17) : "d" (f14));
+ else
+ __asm__ __volatile__ ("fctiwuz %0, %1" : "=d" (f17) : "d" (f14));
+}
+
+static void test_fctiwu(void)
+{
+ if (do_dot)
+ __asm__ __volatile__ ("fctiwu. %0, %1" : "=d" (f17) : "d" (f14));
+ else
+ __asm__ __volatile__ ("fctiwu %0, %1" : "=d" (f17) : "d" (f14));
+}
+
+typedef struct simple_test {
+ test_func_t test_func;
+ char * name;
+ precision_type_t precision;
+} simple_test_t;
+
+static simple_test_t fct_tests[] = {
+ { &test_fctiduz, "fctiduz", DOUBLE_TEST },
+ { &test_fctidu, "fctidu", DOUBLE_TEST },
+ { &test_fctiwuz, "fctiwuz", SINGLE_TEST },
+ { &test_fctiwu, "fctiwu", SINGLE_TEST },
+ { NULL, NULL }
+};
+
+static void setup_sp_fp_args(fp_test_args_t * targs, Bool swap_inputs)
+{
+ int a_idx, b_idx, i;
+ void * inA, * inB;
+ void * vec_src = swap_inputs ? &vec_out : &vec_inB;
+
+ for (i = 0; i < 4; i++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ inA = (void *)&spec_sp_fargs[a_idx];
+ inB = (void *)&spec_sp_fargs[b_idx];
+ // copy single precision FP into vector element i
+ memcpy(((void *)&vec_inA) + (i * 4), inA, 4);
+ memcpy(vec_src + (i * 4), inB, 4);
+ targs++;
+ }
+}
+
+static void setup_dp_fp_args(fp_test_args_t * targs, Bool swap_inputs)
+{
+ int a_idx, b_idx, i;
+ void * inA, * inB;
+ void * vec_src = swap_inputs ? (void *)&vec_out : (void *)&vec_inB;
+
+ for (i = 0; i < 2; i++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ inA = (void *)&spec_fargs[a_idx];
+ inB = (void *)&spec_fargs[b_idx];
+ // copy double precision FP into vector element i
+ memcpy(((void *)&vec_inA) + (i * 8), inA, 8);
+ memcpy(vec_src + (i * 8), inB, 8);
+ targs++;
+ }
+}
+
+#define VX_NOT_CMP_OP 0xffffffff
+static void print_vector_fp_result(unsigned int cc, vx_fp_test_t * test_group, int i)
+{
+ int a_idx, b_idx, k;
+ char * name = malloc(20);
+ int dp = test_group->precision == DOUBLE_TEST ? 1 : 0;
+ int loops = dp ? 2 : 4;
+ fp_test_args_t * targs = &test_group->targs[i];
+ unsigned long long * frA_dp, * frB_dp, * dst_dp;
+ unsigned int * frA_sp, *frB_sp, * dst_sp;
+ strcpy(name, test_group->name);
+ printf("#%d: %s%s ", dp? i/2 : i/4, name, (do_dot ? "." : ""));
+ for (k = 0; k < loops; k++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ if (k)
+ printf(" AND ");
+ if (dp) {
+ frA_dp = (unsigned long long *)&spec_fargs[a_idx];
+ frB_dp = (unsigned long long *)&spec_fargs[b_idx];
+ printf("%016llx %s %016llx", *frA_dp, test_group->op, *frB_dp);
+ } else {
+ frA_sp = (unsigned int *)&spec_sp_fargs[a_idx];
+ frB_sp = (unsigned int *)&spec_sp_fargs[b_idx];
+ printf("%08x %s %08x", *frA_sp, test_group->op, *frB_sp);
+ }
+ targs++;
+ }
+ if (cc != VX_NOT_CMP_OP)
+ printf(" ? cc=%x", cc);
+
+ if (dp) {
+ dst_dp = (unsigned long long *) &vec_out;
+ printf(" => %016llx %016llx\n", dst_dp[0], dst_dp[1]);
+ } else {
+ dst_sp = (unsigned int *) &vec_out;
+ printf(" => %08x %08x %08x %08x\n", dst_sp[0], dst_sp[1], dst_sp[2], dst_sp[3]);
+ }
+ free(name);
+}
+
+
+static void print_vx_aORm_fp_result(unsigned long long * XT_arg, unsigned long long * XB_arg,
+ vx_fp_test_t * test_group, int i)
+{
+ int a_idx, k;
+ char * name = malloc(20);
+ int dp = test_group->precision == DOUBLE_TEST ? 1 : 0;
+ int loops = dp ? 2 : 4;
+ fp_test_args_t * targs = &test_group->targs[i];
+ unsigned long long frA_dp, * dst_dp;
+ unsigned int frA_sp, * dst_sp;
+
+ strcpy(name, test_group->name);
+ if (do_aXp)
+ if (dp)
+ strcat(name, "adp");
+ else
+ strcat(name, "asp");
+ else
+ if (dp)
+ strcat(name, "mdp");
+ else
+ strcat(name, "msp");
+
+ printf("#%d: %s ", dp? i/2 : i/4, name);
+ for (k = 0; k < loops; k++) {
+ a_idx = targs->fra_idx;
+ if (k)
+ printf(" AND ");
+ if (dp) {
+ frA_dp = *((unsigned long long *)&spec_fargs[a_idx]);
+ printf("%s(%016llx,%016llx,%016llx)", test_group->op, XT_arg[k], frA_dp, XB_arg[k]);
+ } else {
+ unsigned int * xt_sp = (unsigned int *)XT_arg;
+ unsigned int * xb_sp = (unsigned int *)XB_arg;
+ frA_sp = *((unsigned int *)&spec_sp_fargs[a_idx]);
+ printf("%s(%08x,%08x,%08x)", test_group->op, xt_sp[k], frA_sp, xb_sp[k]);
+ }
+ targs++;
+ }
+
+ if (dp) {
+ dst_dp = (unsigned long long *) &vec_out;
+ printf(" => %016llx %016llx\n", dst_dp[0], dst_dp[1]);
+ } else {
+ dst_sp = (unsigned int *) &vec_out;
+ printf(" => %08x %08x %08x %08x\n", dst_sp[0], dst_sp[1], dst_sp[2], dst_sp[3]);
+ }
+ free(name);
+}
+
+/* This function currently only supports double precision input arguments. */
+static void test_vx_simple_scalar_fp_ops(void)
+{
+ test_func_t func;
+ int k = 0;
+
+ build_special_fargs_table();
+ while ((func = vx_simple_scalar_fp_tests[k].test_func)) {
+ unsigned long long * frap, * frbp, * dst;
+ unsigned int * pv;
+ int idx;
+ vx_fp_test_t test_group = vx_simple_scalar_fp_tests[k];
+ Bool convToWord = (test_group.type == VX_CONV_WORD);
+ if (test_group.precision != DOUBLE_TEST) {
+ fprintf(stderr, "Unsupported single precision for scalar op in test_vx_aORm_fp_ops\n");
+ exit(1);
+ }
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ /* If num_tests is exactly equal to nb_special_fargs, this implies the
+ * instruction being tested only requires one floating point argument
+ * (e.g. xssqrtdp).
+ */
+ if (test_group.num_tests == nb_special_fargs && !test_group.targs) {
+ void * inB, * vec_void_ptr = (void *)&vec_inB;
+ int i;
+ if (isLE)
+ vec_void_ptr += 8;
+ for (i = 0; i < nb_special_fargs; i++) {
+ inB = (void *)&spec_fargs[i];
+ frbp = (unsigned long long *)&spec_fargs[i];
+ memcpy(vec_void_ptr, inB, 8);
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ if (isLE)
+ dst++;
+ printf("#%d: %s %016llx => %016llx\n", i, test_group.name, *frbp,
+ convToWord ? (*dst & 0x00000000ffffffffULL) : *dst);
+ }
+ } else {
+ void * inA, * inB, * vecA_void_ptr, * vecB_void_ptr;
+ unsigned int condreg, flags;
+ int isTdiv = (strstr(test_group.name, "xstdivdp") != NULL) ? 1 : 0;
+ int i;
+ if (isLE) {
+ vecA_void_ptr = (void *)&vec_inA + 8;
+ vecB_void_ptr = (void *)&vec_inB + 8;
+ } else {
+ vecA_void_ptr = (void *)&vec_inA;
+ vecB_void_ptr = (void *)&vec_inB;
+ }
+ for (i = 0; i < test_group.num_tests; i++) {
+ fp_test_args_t aTest = test_group.targs[i];
+ inA = (void *)&spec_fargs[aTest.fra_idx];
+ inB = (void *)&spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ // Only need to copy one doubleword into each vector's element 0
+ memcpy(vecA_void_ptr, inA, 8);
+ memcpy(vecB_void_ptr, inB, 8);
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ if (isTdiv) {
+ condreg = (flags & 0x000000f0) >> 4;
+ printf("#%d: %s %016llx,%016llx => cr %x\n", i, test_group.name, *frap, *frbp, condreg);
+ } else {
+ dst = (unsigned long long *) &vec_out;
+ if (isLE)
+ dst++;
+ printf("#%d: %s %016llx,%016llx => %016llx\n", i, test_group.name,
+ *frap, *frbp, *dst);
+ }
+ }
+ }
+ printf( "\n" );
+ k++;
+ }
+}
+
+static void test_vx_aORm_fp_ops(void)
+{
+ /* These ops need a third src argument, which is stored in element 0 of
+ * VSX[XT] -- i.e., vec_out. For the xs<ZZZ>m{d|s}p cases, VSX[XT] holds
+ * src3 and VSX[XB] holds src2; for the xs<ZZZ>a{d|s}p cases, VSX[XT] holds
+ * src2 and VSX[XB] holds src3. The fp_test_args_t that holds the test
+ * data (input args, result) contain only two inputs, so I arbitrarily
+ * choose some spec_fargs elements for the third source argument.
+ * Note that that by using the same input data for a given pair of
+ * a{d|s}p/m{d|s}p-type instructions (by swapping the src2 and src3
+ * arguments), the expected result should be the same.
+ */
+
+ test_func_t func;
+ int k;
+ char * test_name = (char *)malloc(20);
+ k = 0;
+ do_dot = False;
+
+ build_special_fargs_table();
+ while ((func = vx_aORm_fp_tests[k].test_func)) {
+ int i, stride;
+ Bool repeat = False;
+ Bool scalar = False;
+ unsigned long long * frap, * frbp, * dst;
+ vx_fp_test_t test_group = vx_aORm_fp_tests[k];
+ vx_fp_test_type test_type = test_group.type;
+ do_dp = test_group.precision == DOUBLE_TEST ? True : False;
+ frap = frbp = NULL;
+
+ if (test_type < VX_VECTOR_FP_MULT_AND_OP2) {
+ scalar = True;
+ strcpy(test_name, test_group.name);
+ if (!repeat) {
+ repeat = 1;
+ stride = 1;
+ // Only support double precision scalar ops in this function
+ if (do_dp) {
+ strcat(test_name, "adp");
+ } else {
+ fprintf(stderr, "Unsupported single precision for scalar op in test_vx_aORm_fp_ops\n");
+ exit(1);
+ }
+ do_aXp = True;
+ }
+ } else if (test_type < VX_BASIC_CMP) {
+ // Then it must be a VX_VECTOR_xxx type
+ stride = do_dp ? 2 : 4;
+ if (!repeat) {
+ // No need to work up the testcase name here, since that will be done in
+ // the print_vx_aORm_fp_result() function we'll call for vector-type ops.
+ repeat = 1;
+ do_aXp = True;
+ }
+ } else {
+ printf("ERROR: Invalid VX FP test type %d\n", test_type);
+ exit(1);
+ }
+
+again:
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ void * inA, * inB;
+ int m, fp_idx[4];
+ unsigned long long vsr_XT[2];
+ unsigned long long vsr_XB[2];
+ fp_test_args_t aTest = test_group.targs[i];
+ for (m = 0; m < stride; m++)
+ fp_idx[m] = i % (nb_special_fargs - stride) + m;
+
+ /* When repeat == True, we're on the first time through of one of the VX_FP_SMx
+ * test types, meaning we're testing a xs<ZZZ>adp case, thus we have to swap
+ * inputs as described above:
+ * src2 <= VSX[XT]
+ * src3 <= VSX[XB]
+ */
+ if (scalar) {
+#ifdef VGP_ppc64le_linux
+#define VECTOR_ADDR(_v) ((void *)&_v) + 8
+#else
+#define VECTOR_ADDR(_v) ((void *)&_v)
+#endif
+ // For scalar op, only need to copy one doubleword into each vector's element 0
+ inA = (void *)&spec_fargs[aTest.fra_idx];
+ inB = (void *)&spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ memcpy(VECTOR_ADDR(vec_inA), inA, 8);
+ if (repeat) {
+ memcpy(VECTOR_ADDR(vec_out), inB, 8); // src2
+ memcpy(VECTOR_ADDR(vec_inB), &spec_fargs[fp_idx[0]], 8); //src3
+ frbp = (unsigned long long *)&spec_fargs[fp_idx[0]];
+ } else {
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ memcpy(VECTOR_ADDR(vec_inB), inB, 8); // src2
+ memcpy(VECTOR_ADDR(vec_out), &spec_fargs[fp_idx[0]], 8); //src3
+ }
+ memcpy(vsr_XT, VECTOR_ADDR(vec_out), 8);
+ } else {
+ int j, loops = do_dp ? 2 : 4;
+ size_t len = do_dp ? 8 : 4;
+ void * vec_src = repeat ? (void *)&vec_inB : (void *)&vec_out;
+ for (j = 0; j < loops; j++) {
+ if (do_dp)
+ memcpy(vec_src + (j * len), &spec_fargs[fp_idx[j]], len);
+ else
+ memcpy(vec_src + (j * len), &spec_sp_fargs[fp_idx[j]], len);
+ }
+ if (do_dp)
+ setup_dp_fp_args(&test_group.targs[i], repeat);
+ else
+ setup_sp_fp_args(&test_group.targs[i], repeat);
+
+ memcpy(vsr_XT, &vec_out, 16);
+ memcpy(vsr_XB, &vec_inB, 16);
+ }
+
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+ if (isLE)
+ dst++;
+ if (test_type < VX_VECTOR_FP_MULT_AND_OP2)
+ printf( "#%d: %s %s(%016llx,%016llx,%016llx) = %016llx\n", i,
+ test_name, test_group.op, vsr_XT[0], *frap, *frbp, *dst );
+ else
+ print_vx_aORm_fp_result(vsr_XT, vsr_XB, &test_group, i);
+ }
+ printf( "\n" );
+
+ if (repeat) {
+ repeat = 0;
+ if (test_type < VX_VECTOR_FP_MULT_AND_OP2) {
+ strcpy(test_name, test_group.name);
+ strcat(test_name, "mdp");
+ }
+ do_aXp = False;
+ goto again;
+ }
+ k++;
+ }
+ printf( "\n" );
+ free(test_name);
+}
+
+static void test_vx_vector_one_fp_arg(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+ build_special_fargs_table();
+
+ while ((func = vx_vector_one_fp_arg_tests[k].test_func)) {
+ int idx, i;
+ vx_fp_test_t test_group = vx_vector_one_fp_arg_tests[k];
+ Bool convToWord = (test_group.type == VX_CONV_WORD);
+ Bool dp = (test_group.precision == DOUBLE_TEST) ? True : False;
+ Bool xvrespTest = (strstr(test_group.name , "xvresp") != NULL) ? True: False;
+ int stride = dp ? 2 : 4;
+
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv;
+ void * inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (dp) {
+ int j;
+ unsigned long long * frB_dp, *dst_dp;
+ for (j = 0; j < 2; j++) {
+ inB = (void *)&spec_fargs[i + j];
+ // copy double precision FP into vector element i
+ memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
+ }
+ // execute test insn
+ (*func)();
+ dst_dp = (unsigned long long *) &vec_out;
+ printf("#%d: %s ", i/2, test_group.name);
+ for (j = 0; j < 2; j++) {
+ if (j)
+ printf("; ");
+ frB_dp = (unsigned long long *)&spec_fargs[i + j];
+ printf("%s(%016llx)", test_group.op, *frB_dp);
+ printf(" = %016llx", convToWord ? (dst_dp[j] & 0x00000000ffffffffULL) : dst_dp[j]);
+ }
+ printf("\n");
+ } else {
+ int j;
+ unsigned int * frB_sp, * dst_sp;
+
+ for (j = 0; j < 4; j++) {
+ inB = (void *)&spec_sp_fargs[i + j];
+ // copy single precision FP into vector element i
+ memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
+ }
+ // execute test insn
+ (*func)();
+ dst_sp = (unsigned int *) &vec_out;
+ // print result
+ printf("#%d: %s ", i/4, test_group.name);
+ for (j = 0; j < 4; j++) {
+ if (j)
+ printf("; ");
+ frB_sp = (unsigned int *)&spec_sp_fargs[i + j];
+ printf("%s(%08x)", test_group.op, *frB_sp);
+ if (xvrespTest) {
+ float calc_diff = fabs(spec_sp_fargs[i + j]/256);
+ float sp_res;
+ memcpy(&sp_res, &dst_sp[j], 4);
+ float div_result = 1/spec_sp_fargs[i + j];
+ float real_diff = fabs(sp_res - div_result);
+ printf( " ==> %s",
+ ( ( sp_res == div_result )
+ || ( isnan(sp_res) && isnan(div_result) )
+ || ( real_diff <= calc_diff ) ) ? "PASS"
+ : "FAIL");
+ } else {
+ printf(" = %08x", dst_sp[j]);
+ }
+ }
+ printf("\n");
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+
+}
+
+/* This function assumes the instruction being tested requires two args. */
+static void test_vx_vector_fp_ops(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+ build_special_fargs_table();
+
+ while ((func = vx_vector_fp_tests[k].test_func)) {
+ int idx, i, repeat = 1;
+ vx_fp_test_t test_group = vx_vector_fp_tests[k];
+ int stride = test_group.precision == DOUBLE_TEST ? 2 : 4;
+ do_dot = False;
+
+again:
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv, condreg;
+ unsigned int flags;
+
+ pv = (unsigned int *)&vec_out;
+ if (test_group.precision == DOUBLE_TEST)
+ setup_dp_fp_args(&test_group.targs[i], False);
+ else
+ setup_sp_fp_args(&test_group.targs[i], False);
+
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ // execute test insn
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ if (test_group.type == VX_BASIC_CMP) {
+ condreg = (flags & 0x000000f0) >> 4;
+ } else {
+ condreg = VX_NOT_CMP_OP;
+ }
+ print_vector_fp_result(condreg, &test_group, i);
+ }
+ printf("\n");
+ if (repeat && test_group.type == VX_BASIC_CMP) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+// The div doubleword test data
+signed long long div_dw_tdata[13][2] = {
+ { 4, -4 },
+ { 4, -3 },
+ { 4, 4 },
+ { 4, -5 },
+ { 3, 8 },
+ { 0x8000000000000000ULL, 0xa },
+ { 0x50c, -1 },
+ { 0x50c, -4096 },
+ { 0x1234fedc, 0x8000a873 },
+ { 0xabcd87651234fedcULL, 0xa123b893 },
+ { 0x123456789abdcULL, 0 },
+ { 0, 2 },
+ { 0x77, 0xa3499 }
+};
+#define dw_tdata_len (sizeof(div_dw_tdata)/sizeof(signed long long)/2)
+
+// The div word test data
+unsigned int div_w_tdata[6][2] = {
+ { 0, 2 },
+ { 2, 0 },
+ { 0x7abc1234, 0xf0000000 },
+ { 0xfabc1234, 5 },
+ { 77, 66 },
+ { 5, 0xfabc1234 },
+};
+#define w_tdata_len (sizeof(div_w_tdata)/sizeof(unsigned int)/2)
+
+typedef struct div_ext_test
+{
+ test_func_t test_func;
+ const char *name;
+ int num_tests;
+ div_type_t div_type;
+ precision_type_t precision;
+} div_ext_test_t;
+
+static div_ext_test_t div_tests[] = {
+#ifdef __powerpc64__
+ { &test_divde, "divde", dw_tdata_len, DIV_BASE, DOUBLE_TEST },
+ { &test_divde, "divdeo", dw_tdata_len, DIV_OE, DOUBLE_TEST },
+#endif
+ { &test_divweu, "divweu", w_tdata_len, DIV_BASE, SINGLE_TEST },
+ { &test_divweu, "divweuo", w_tdata_len, DIV_OE, SINGLE_TEST },
+ { NULL, NULL, 0, 0, 0 }
+};
+
+static void test_div_extensions(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = div_tests[k].test_func)) {
+ int i, repeat = 1;
+ div_ext_test_t test_group = div_tests[k];
+ do_dot = False;
+
+again:
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int condreg;
+
+ if (test_group.div_type == DIV_OE)
+ do_OE = True;
+ else
+ do_OE = False;
+
+ if (test_group.precision == DOUBLE_TEST) {
+ r14 = div_dw_tdata[i][0];
+ r15 = div_dw_tdata[i][1];
+ } else {
+ r14 = div_w_tdata[i][0];
+ r15 = div_w_tdata[i][1];
+ }
+ // execute test insn
+ (*func)();
+ condreg = (div_flags & 0xf0000000) >> 28;
+ printf("#%d: %s%s: ", i, test_group.name, do_dot ? "." : "");
+ if (test_group.precision == DOUBLE_TEST) {
+ printf("0x%016llx / 0x%016llx = 0x%016llx;",
+ div_dw_tdata[i][0], div_dw_tdata[i][1], (signed long long) r17);
+ } else {
+ printf("0x%08x / 0x%08x = 0x%08x;",
+ div_w_tdata[i][0], div_w_tdata[i][1], (unsigned int) r17);
+ }
+ printf(" CR=%x; XER=%x\n", condreg, div_xer);
+ }
+ printf("\n");
+ if (repeat) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+
+}
+
+static void test_fct_ops(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = fct_tests[k].test_func)) {
+ int i, repeat = 1;
+ simple_test_t test_group = fct_tests[k];
+ do_dot = False;
+
+again:
+ for (i = 0; i < nb_special_fargs; i++) {
+ double result;
+#define SINGLE_MASK 0x00000000FFFFFFFFULL
+
+ f14 = spec_fargs[i];
+ // execute test insn
+ SET_FPSCR_ZERO;
+ (*func)();
+ result = f17;
+ printf("#%d: %s%s: ", i, test_group.name, do_dot ? "." : "");
+ printf("0x%016llx (%e) ==> 0x%016llx\n",
+ *((unsigned long long *)(&spec_fargs[i])), spec_fargs[i],
+ test_group.precision == SINGLE_TEST ? (SINGLE_MASK &
+ *((unsigned long long *)(&result))) :
+ *((unsigned long long *)(&result)));
+ }
+ printf("\n");
+ if (repeat) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+#ifdef __powerpc64__
+void test_stdbrx(void)
+{
+ unsigned long long store, val = 0xdeadbacf12345678ULL;
+ printf("stdbrx: 0x%llx ==> ", val);
+ r17 = (HWord_t)val;
+ r14 = (HWord_t)&store;
+ __asm__ __volatile__ ("stdbrx %0, 0, %1" : : "r"(r17), "r"(r14));
+ printf("0x%llx\n", store);
+ printf( "\n" );
+}
+#endif
+
+static test_table_t
+ all_tests[] =
+{
+ { &test_vx_vector_one_fp_arg,
+ "Test VSX vector single arg instructions"},
+ { &test_vx_vector_fp_ops,
+ "Test VSX floating point compare and basic arithmetic instructions" },
+#ifdef __powerpc64__
+ { &test_bpermd,
+ "Test bit permute double"},
+#endif
+ { &test_xxsel,
+ "Test xxsel instruction" },
+ { &test_xxspltw,
+ "Test xxspltw instruction" },
+ { &test_div_extensions,
+ "Test div extensions" },
+ { &test_fct_ops,
+ "Test floating point convert [word | doubleword] unsigned, with round toward zero" },
+#ifdef __powerpc64__
+ { &test_stdbrx,
+ "Test stdbrx instruction"},
+#endif
+ { &test_vx_aORm_fp_ops,
+ "Test floating point arithmetic instructions -- with a{d|s}p or m{d|s}p"},
+ { &test_vx_simple_scalar_fp_ops,
+ "Test scalar floating point arithmetic instructions"},
+ { NULL, NULL }
+};
+#endif // HAS_VSX
+
+int main(int argc, char *argv[])
+{
+#ifdef HAS_VSX
+
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+ if (spec_fargs)
+ free(spec_fargs);
+ if (spec_sp_fargs)
+ free(spec_sp_fargs);
+
+#endif // HAS _VSX
+
+ return 0;
+}
diff --git a/none/tests/ppc64/test_isa_2_06_part3.c b/none/tests/ppc64/test_isa_2_06_part3.c
deleted file mode 120000
index 57da4ec..0000000
--- a/none/tests/ppc64/test_isa_2_06_part3.c
+++ /dev/null
@@ -1 +0,0 @@
-../../../none/tests/ppc32/test_isa_2_06_part3.c
\ No newline at end of file
diff --git a/none/tests/ppc64/test_isa_2_06_part3.c b/none/tests/ppc64/test_isa_2_06_part3.c
new file mode 100644
index 0000000..9f9cd79
--- /dev/null
+++ b/none/tests/ppc64/test_isa_2_06_part3.c
@@ -0,0 +1,1626 @@
+/* Copyright (C) 2011 IBM
+
+ Author: Maynard Johnson <maynardj@us.ibm.com>
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+#ifdef HAS_VSX
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <malloc.h>
+#include <altivec.h>
+#include <math.h>
+
+#ifndef __powerpc64__
+typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif /* __powerpc64__ */
+
+#ifdef VGP_ppc64le_linux
+#define isLE 1
+#else
+#define isLE 0
+#endif
+
+typedef unsigned char Bool;
+#define True 1
+#define False 0
+register HWord_t r14 __asm__ ("r14");
+register HWord_t r15 __asm__ ("r15");
+register HWord_t r16 __asm__ ("r16");
+register HWord_t r17 __asm__ ("r17");
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+register double f16 __asm__ ("fr16");
+register double f17 __asm__ ("fr17");
+
+static volatile unsigned int div_flags, div_xer;
+
+#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
+
+#define SET_CR(_arg) \
+ __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
+
+#define SET_XER(_arg) \
+ __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
+
+#define GET_CR(_lval) \
+ __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
+
+#define GET_XER(_lval) \
+ __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
+
+#define GET_CR_XER(_lval_cr,_lval_xer) \
+ do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
+
+#define SET_CR_ZERO \
+ SET_CR(0)
+
+#define SET_XER_ZERO \
+ SET_XER(0)
+
+#define SET_CR_XER_ZERO \
+ do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
+
+#define SET_FPSCR_ZERO \
+ do { double _d = 0.0; \
+ __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
+ } while (0)
+
+
+typedef void (*test_func_t)(void);
+typedef struct test_table test_table_t;
+
+
+/* These functions below that construct a table of floating point
+ * values were lifted from none/tests/ppc32/jm-insns.c.
+ */
+
+#if defined (DEBUG_ARGS_BUILD)
+#define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
+#else
+#define AB_DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+static inline void register_farg (void *farg,
+ int s, uint16_t _exp, uint64_t mant)
+{
+ uint64_t tmp;
+
+ tmp = ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
+ *(uint64_t *)farg = tmp;
+ AB_DPRINTF("%d %03x %013llx => %016llx %0e\n",
+ s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
+}
+
+static inline void register_sp_farg (void *farg,
+ int s, uint16_t _exp, uint32_t mant)
+{
+ uint32_t tmp;
+ tmp = ((uint32_t)s << 31) | ((uint32_t)_exp << 23) | mant;
+ *(uint32_t *)farg = tmp;
+}
+
+
+typedef struct fp_test_args {
+ int fra_idx;
+ int frb_idx;
+} fp_test_args_t;
+
+
+fp_test_args_t two_arg_fp_tests[] = {
+ {8, 8},
+ {8, 14},
+ {15, 16},
+ {8, 5},
+ {8, 4},
+ {8, 7},
+ {8, 9},
+ {8, 11},
+ {14, 8},
+ {14, 14},
+ {14, 6},
+ {14, 5},
+ {14, 4},
+ {14, 7},
+ {14, 9},
+ {14, 11},
+ {6, 8},
+ {6, 14},
+ {6, 6},
+ {6, 5},
+ {6, 4},
+ {6, 7},
+ {6, 9},
+ {6, 11},
+ {5, 8},
+ {5, 14},
+ {5, 6},
+ {5, 5},
+ {5, 4},
+ {5, 7},
+ {5, 9},
+ {5, 11},
+ {4, 8},
+ {4, 14},
+ {4, 6},
+ {4, 5},
+ {4, 1},
+ {4, 7},
+ {4, 9},
+ {4, 11},
+ {7, 8},
+ {7, 14},
+ {7, 6},
+ {7, 5},
+ {7, 4},
+ {7, 7},
+ {7, 9},
+ {7, 11},
+ {10, 8},
+ {10, 14},
+ {12, 6},
+ {12, 5},
+ {10, 4},
+ {10, 7},
+ {10, 9},
+ {10, 11},
+ {12, 8 },
+ {12, 14},
+ {12, 6},
+ {15, 16},
+ {15, 16},
+ {9, 11},
+ {11, 11},
+ {11, 12},
+ {16, 18},
+ {17, 16},
+ {19, 19},
+ {19, 18}
+};
+
+
+static int nb_special_fargs;
+static double * spec_fargs;
+static float * spec_sp_fargs;
+
+static void build_special_fargs_table(void)
+{
+/*
+ Entry Sign Exp fraction Special value
+ 0 0 3fd 0x8000000000000ULL Positive finite number
+ 1 0 404 0xf000000000000ULL ...
+ 2 0 001 0x8000000b77501ULL ...
+ 3 0 7fe 0x800000000051bULL ...
+ 4 0 012 0x3214569900000ULL ...
+ 5 0 000 0x0000000000000ULL +0.0 (+zero)
+ 6 1 000 0x0000000000000ULL -0.0 (-zero)
+ 7 0 7ff 0x0000000000000ULL +infinity
+ 8 1 7ff 0x0000000000000ULL -infinity
+ 9 0 7ff 0x7FFFFFFFFFFFFULL +SNaN
+ 10 1 7ff 0x7FFFFFFFFFFFFULL -SNaN
+ 11 0 7ff 0x8000000000000ULL +QNaN
+ 12 1 7ff 0x8000000000000ULL -QNaN
+ 13 1 000 0x8340000078000ULL Denormalized val (zero exp and non-zero fraction)
+ 14 1 40d 0x0650f5a07b353ULL Negative finite number
+ 15 0 412 0x32585a9900000ULL A few more positive finite numbers
+ 16 0 413 0x82511a2000000ULL ...
+ 17 . . . . . . . . . . . . . . . . . . . . . . .
+ 18 . . . . . . . . . . . . . . . . . . . . . . .
+ 19 . . . . . . . . . . . . . . . . . . . . . . .
+*/
+
+ uint64_t mant;
+ uint32_t mant_sp;
+ uint16_t _exp;
+ int s;
+ int j, i = 0;
+
+ if (spec_fargs)
+ return;
+
+ spec_fargs = malloc( 20 * sizeof(double) );
+ spec_sp_fargs = malloc( 20 * sizeof(float) );
+
+ // #0
+ s = 0;
+ _exp = 0x3fd;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #1
+ s = 0;
+ _exp = 0x404;
+ mant = 0xf000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #2
+ s = 0;
+ _exp = 0x001;
+ mant = 0x8000000b77501ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #3
+ s = 0;
+ _exp = 0x7fe;
+ mant = 0x800000000051bULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #4
+ s = 0;
+ _exp = 0x012;
+ mant = 0x3214569900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+
+ /* Special values */
+ /* +0.0 : 0 0x000 0x0000000000000 */
+ // #5
+ s = 0;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -0.0 : 1 0x000 0x0000000000000 */
+ // #6
+ s = 1;
+ _exp = 0x000;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* +infinity : 0 0x7FF 0x0000000000000 */
+ // #7
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -infinity : 1 0x7FF 0x0000000000000 */
+ // #8
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x0000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /*
+ * This comment applies to values #9 and #10 below:
+ * When src is a SNaN, it's converted to a QNaN first before rounding to single-precision,
+ * so we can't just copy the double-precision value to the corresponding slot in the
+ * single-precision array (i.e., in the loop at the end of this function). Instead, we
+ * have to manually set the bits using register_sp_farg().
+ */
+
+ /* +SNaN : 0 0x7FF 0x7FFFFFFFFFFFF */
+ // #9
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+ _exp = 0xff;
+ mant_sp = 0x3FFFFF;
+ register_sp_farg(&spec_sp_fargs[i-1], s, _exp, mant_sp);
+
+ /* -SNaN : 1 0x7FF 0x7FFFFFFFFFFFF */
+ // #10
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x7FFFFFFFFFFFFULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+ _exp = 0xff;
+ mant_sp = 0x3FFFFF;
+ register_sp_farg(&spec_sp_fargs[i-1], s, _exp, mant_sp);
+
+ /* +QNaN : 0 0x7FF 0x8000000000000 */
+ // #11
+ s = 0;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* -QNaN : 1 0x7FF 0x8000000000000 */
+ // #12
+ s = 1;
+ _exp = 0x7FF;
+ mant = 0x8000000000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* denormalized value */
+ // #13
+ s = 1;
+ _exp = 0x000;
+ mant = 0x8340000078000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* Negative finite number */
+ // #14
+ s = 1;
+ _exp = 0x40d;
+ mant = 0x0650f5a07b353ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ /* A few positive finite numbers ... */
+ // #15
+ s = 0;
+ _exp = 0x412;
+ mant = 0x32585a9900000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #16
+ s = 0;
+ _exp = 0x413;
+ mant = 0x82511a2000000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #17
+ s = 0;
+ _exp = 0x403;
+ mant = 0x12ef5a9300000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #18
+ s = 0;
+ _exp = 0x405;
+ mant = 0x14bf5d2300000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ // #19
+ s = 0;
+ _exp = 0x409;
+ mant = 0x76bf982440000ULL;
+ register_farg(&spec_fargs[i++], s, _exp, mant);
+
+ nb_special_fargs = i;
+ for (j = 0; j < i; j++) {
+ if (!(j == 9 || j == 10))
+ spec_sp_fargs[j] = spec_fargs[j];
+ }
+}
+
+
+struct test_table
+{
+ test_func_t test_category;
+ char * name;
+};
+
+/* Type of input for floating point operations.*/
+typedef enum {
+ SINGLE_TEST,
+ DOUBLE_TEST
+} precision_type_t;
+
+typedef enum {
+ VX_SCALAR_CONV_TO_WORD,
+ VX_CONV_TO_SINGLE,
+ VX_CONV_TO_DOUBLE,
+ VX_ESTIMATE,
+ VX_DEFAULT
+} vx_fp_test_type;
+
+static vector unsigned int vec_out, vec_inA, vec_inB;
+
+/* This function is for checking the reciprocal and reciprocal square root
+ * estimate instructions.
+ */
+Bool check_estimate(precision_type_t type, Bool is_rsqrte, int idx, int output_vec_idx)
+{
+ /* Technically, the number of bits of precision for xvredp and xvrsqrtedp is
+ * 14 bits (14 = log2 16384). However, the VEX emulation of these instructions
+ * does an actual reciprocal calculation versus estimation, so the answer we get back from
+ * valgrind can easily differ from the estimate in the lower bits (within the 14 bits of
+ * precision) and the estimate may still be within expected tolerances. On top of that,
+ * we can't count on these estimates always being the same across implementations.
+ * For example, with the fre[s] instruction (which should be correct to within one part
+ * in 256 -- i.e., 8 bits of precision) . . . When approximating the value 1.0111_1111_1111,
+ * one implementation could return 1.0111_1111_0000 and another implementation could return
+ * 1.1000_0000_0000. Both estimates meet the 1/256 accuracy requirement, but share only a
+ * single bit in common.
+ *
+ * The upshot is we can't validate the VEX output for these instructions by comparing against
+ * stored bit patterns. We must check that the result is within expected tolerances.
+ */
+
+
+ /* A mask to be used for validation as a last resort.
+ * Only use 12 bits of precision for reasons discussed above.
+ */
+#define VSX_RECIP_ESTIMATE_MASK_DP 0xFFFFFF0000000000ULL
+#define VSX_RECIP_ESTIMATE_MASK_SP 0xFFFFFF00
+
+ Bool result = False;
+ Bool dp_test = type == DOUBLE_TEST;
+ double src_dp, res_dp;
+ float src_sp, res_sp;
+ src_dp = res_dp = 0;
+ src_sp = res_sp = 0;
+#define SRC (dp_test ? src_dp : src_sp)
+#define RES (dp_test ? res_dp : res_sp)
+ Bool src_is_negative = False;
+ Bool res_is_negative = False;
+ unsigned long long * dst_dp = NULL;
+ unsigned int * dst_sp = NULL;
+ if (dp_test) {
+ unsigned long long * src_dp_ull;
+ dst_dp = (unsigned long long *) &vec_out;
+ src_dp = spec_fargs[idx];
+ src_dp_ull = (unsigned long long *) &src_dp;
+ src_is_negative = (*src_dp_ull & 0x8000000000000000ULL) ? True : False;
+ res_is_negative = (dst_dp[output_vec_idx] & 0x8000000000000000ULL) ? True : False;
+ memcpy(&res_dp, &dst_dp[output_vec_idx], 8);
+ } else {
+ unsigned int * src_sp_uint;
+ dst_sp = (unsigned int *) &vec_out;
+ src_sp = spec_sp_fargs[idx];
+ src_sp_uint = (unsigned int *) &src_sp;
+ src_is_negative = (*src_sp_uint & 0x80000000) ? True : False;
+ res_is_negative = (dst_sp[output_vec_idx] & 0x80000000) ? True : False;
+ memcpy(&res_sp, &dst_sp[output_vec_idx], 4);
+ }
+
+ // Below are common rules for xvre{d|s}p and xvrsqrte{d|s}p
+ if (isnan(SRC))
+ return isnan(RES);
+ if (fpclassify(SRC) == FP_ZERO)
+ return isinf(RES);
+ if (!src_is_negative && isinf(SRC))
+ return !res_is_negative && (fpclassify(RES) == FP_ZERO);
+ if (is_rsqrte) {
+ if (src_is_negative)
+ return isnan(RES);
+ } else {
+ if (src_is_negative && isinf(SRC))
+ return res_is_negative && (fpclassify(RES) == FP_ZERO);
+ }
+ if (dp_test) {
+ double calc_diff;
+ double real_diff;
+ double recip_divisor;
+ double div_result;
+ double calc_diff_tmp;
+
+ if (is_rsqrte)
+ recip_divisor = sqrt(src_dp);
+ else
+ recip_divisor = src_dp;
+
+ div_result = 1.0/recip_divisor;
+ calc_diff_tmp = recip_divisor * 16384.0;
+ if (isnormal(calc_diff_tmp)) {
+ calc_diff = fabs(1.0/calc_diff_tmp);
+ real_diff = fabs(res_dp - div_result);
+ result = ( ( res_dp == div_result )
+ || ( real_diff <= calc_diff ) );
+ } else {
+ /* Unable to compute theoretical difference, so we fall back to masking out
+ * un-precise bits.
+ */
+ unsigned long long * div_result_dp = (unsigned long long *) &div_result;
+ result = (dst_dp[output_vec_idx] & VSX_RECIP_ESTIMATE_MASK_DP) == (*div_result_dp & VSX_RECIP_ESTIMATE_MASK_DP);
+ }
+ /* For debug use . . .
+ if (!result) {
+ unsigned long long * dv = &div_result;
+ unsigned long long * rd = &real_diff;
+ unsigned long long * cd = &calc_diff;
+ printf("\n\t {actual div_result: %016llx; real_diff: %016llx; calc_diff: %016llx}\n",
+ *dv, *rd, *cd);
+ }
+ */
+ } else { // single precision test (only have xvrsqrtesp, since xvresp was implemented in stage 2)
+ float calc_diff;
+ float real_diff;
+ float div_result;
+ float calc_diff_tmp;
+ float recip_divisor = sqrt(src_sp);
+
+ div_result = 1.0/recip_divisor;
+ calc_diff_tmp = recip_divisor * 16384.0;
+ if (isnormal(calc_diff_tmp)) {
+ calc_diff = fabsf(1.0/calc_diff_tmp);
+ real_diff = fabsf(res_sp - div_result);
+ result = ( ( res_sp == div_result )
+ || ( real_diff <= calc_diff ) );
+ } else {
+ /* Unable to compute theoretical difference, so we fall back to masking out
+ * un-precise bits.
+ */
+ unsigned int * div_result_sp = (unsigned int *) &div_result;
+ result = (dst_sp[output_vec_idx] & VSX_RECIP_ESTIMATE_MASK_SP) == (*div_result_sp & VSX_RECIP_ESTIMATE_MASK_SP);
+ }
+ /* For debug use . . .
+ if (!result) {
+ unsigned long long * dv = &div_result;
+ unsigned long long * rd = &real_diff;
+ unsigned long long * cd = &calc_diff;
+ printf("\n\t {actual div_result: %016llx; real_diff: %016llx; calc_diff: %016llx}\n",
+ *dv, *rd, *cd);
+ }
+ */
+ }
+ return result;
+}
+
+typedef struct vx_fp_test
+{
+ test_func_t test_func;
+ const char * name;
+ fp_test_args_t * targs;
+ int num_tests;
+ precision_type_t precision;
+ vx_fp_test_type type;
+ const char * op;
+} vx_fp_test_t;
+
+
+static Bool do_dot;
+
+static void test_xvredp(void)
+{
+ __asm__ __volatile__ ("xvredp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsredp(void)
+{
+ __asm__ __volatile__ ("xsredp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrsqrtedp(void)
+{
+ __asm__ __volatile__ ("xvrsqrtedp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrsqrtedp(void)
+{
+ __asm__ __volatile__ ("xsrsqrtedp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrsqrtesp(void)
+{
+ __asm__ __volatile__ ("xvrsqrtesp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xstsqrtdp(void)
+{
+ __asm__ __volatile__ ("xstsqrtdp cr1, %x0" : : "wa" (vec_inB));
+}
+
+static void test_xvtsqrtdp(void)
+{
+ __asm__ __volatile__ ("xvtsqrtdp cr1, %x0" : : "wa" (vec_inB));
+}
+
+static void test_xvtsqrtsp(void)
+{
+ __asm__ __volatile__ ("xvtsqrtsp cr1, %x0" : : "wa" (vec_inB));
+}
+
+static void test_xvsqrtdp(void)
+{
+ __asm__ __volatile__ ("xvsqrtdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvsqrtsp(void)
+{
+ __asm__ __volatile__ ("xvsqrtsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvtdivdp(void)
+{
+ __asm__ __volatile__ ("xvtdivdp cr1, %x0, %x1" : : "wa" (vec_inA), "wa" (vec_inB));
+}
+
+static void test_xvtdivsp(void)
+{
+ __asm__ __volatile__ ("xvtdivsp cr1, %x0, %x1" : : "wa" (vec_inA), "wa" (vec_inB));
+}
+
+static void test_xscvdpsp(void)
+{
+ __asm__ __volatile__ ("xscvdpsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvdpuxws(void)
+{
+ __asm__ __volatile__ ("xscvdpuxws %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xscvspdp(void)
+{
+ __asm__ __volatile__ ("xscvspdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvdpsp(void)
+{
+ __asm__ __volatile__ ("xvcvdpsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvdpuxds(void)
+{
+ __asm__ __volatile__ ("xvcvdpuxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvdpuxws(void)
+{
+ __asm__ __volatile__ ("xvcvdpuxws %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspdp(void)
+{
+ __asm__ __volatile__ ("xvcvspdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspsxds(void)
+{
+ __asm__ __volatile__ ("xvcvspsxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspuxds(void)
+{
+ __asm__ __volatile__ ("xvcvspuxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvdpsxds(void)
+{
+ __asm__ __volatile__ ("xvcvdpsxds %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvspuxws(void)
+{
+ __asm__ __volatile__ ("xvcvspuxws %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvsxddp(void)
+{
+ __asm__ __volatile__ ("xvcvsxddp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvuxddp(void)
+{
+ __asm__ __volatile__ ("xvcvuxddp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvsxdsp(void)
+{
+ __asm__ __volatile__ ("xvcvsxdsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvuxdsp(void)
+{
+ __asm__ __volatile__ ("xvcvuxdsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvsxwdp(void)
+{
+ __asm__ __volatile__ ("xvcvsxwdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvuxwdp(void)
+{
+ __asm__ __volatile__ ("xvcvuxwdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvsxwsp(void)
+{
+ __asm__ __volatile__ ("xvcvsxwsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvcvuxwsp(void)
+{
+ __asm__ __volatile__ ("xvcvuxwsp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpic(void)
+{
+ __asm__ __volatile__ ("xsrdpic %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpiz(void)
+{
+ __asm__ __volatile__ ("xsrdpiz %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xsrdpi(void)
+{
+ __asm__ __volatile__ ("xsrdpi %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvabsdp(void)
+{
+ __asm__ __volatile__ ("xvabsdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvnabsdp(void)
+{
+ __asm__ __volatile__ ("xvnabsdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvnegdp(void)
+{
+ __asm__ __volatile__ ("xvnegdp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvabssp(void)
+{
+ __asm__ __volatile__ ("xvabssp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvnabssp(void)
+{
+ __asm__ __volatile__ ("xvnabssp %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpi(void)
+{
+ __asm__ __volatile__ ("xvrdpi %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpic(void)
+{
+ __asm__ __volatile__ ("xvrdpic %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpim(void)
+{
+ __asm__ __volatile__ ("xvrdpim %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpip(void)
+{
+ __asm__ __volatile__ ("xvrdpip %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrdpiz(void)
+{
+ __asm__ __volatile__ ("xvrdpiz %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspi(void)
+{
+ __asm__ __volatile__ ("xvrspi %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspic(void)
+{
+ __asm__ __volatile__ ("xvrspic %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspim(void)
+{
+ __asm__ __volatile__ ("xvrspim %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspip(void)
+{
+ __asm__ __volatile__ ("xvrspip %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static void test_xvrspiz(void)
+{
+ __asm__ __volatile__ ("xvrspiz %x0, %x1" : "=wa" (vec_out): "wa" (vec_inB));
+}
+
+static vx_fp_test_t
+vsx_one_fp_arg_tests[] = {
+ { &test_xvredp, "xvredp", NULL, 18, DOUBLE_TEST, VX_ESTIMATE, "1/x"},
+ { &test_xsredp, "xsredp", NULL, 18, DOUBLE_TEST, VX_ESTIMATE, "1/x"},
+ { &test_xvrsqrtedp, "xvrsqrtedp", NULL, 18, DOUBLE_TEST, VX_ESTIMATE, "1/x-sqrt"},
+ { &test_xsrsqrtedp, "xsrsqrtedp", NULL, 18, DOUBLE_TEST, VX_ESTIMATE, "1/x-sqrt"},
+ { &test_xvrsqrtesp, "xvrsqrtesp", NULL, 18, SINGLE_TEST, VX_ESTIMATE, "1/x-sqrt"},
+ { &test_xvsqrtdp, "xvsqrtdp", NULL, 18, DOUBLE_TEST, VX_DEFAULT, "sqrt"},
+ { &test_xvsqrtsp, "xvsqrtsp", NULL, 18, SINGLE_TEST, VX_DEFAULT, "sqrt"},
+ { &test_xscvdpsp, "xscvdpsp", NULL, 20, DOUBLE_TEST, VX_CONV_TO_SINGLE, "conv"},
+ { &test_xscvdpuxws, "xscvdpuxws", NULL, 20, DOUBLE_TEST, VX_SCALAR_CONV_TO_WORD, "conv"},
+ { &test_xscvspdp, "xscvspdp", NULL, 20, SINGLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvdpsp, "xvcvdpsp", NULL, 20, DOUBLE_TEST, VX_CONV_TO_SINGLE, "conv"},
+ { &test_xvcvdpuxds, "xvcvdpuxds", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvdpuxws, "xvcvdpuxws", NULL, 20, DOUBLE_TEST, VX_CONV_TO_SINGLE, "conv"},
+ { &test_xvcvspdp, "xvcvspdp", NULL, 20, SINGLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvspsxds, "xvcvspsxds", NULL, 20, SINGLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvdpsxds, "xvcvdpsxds", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvspuxds, "xvcvspuxds", NULL, 20, SINGLE_TEST, VX_CONV_TO_DOUBLE, "conv"},
+ { &test_xvcvspuxws, "xvcvspuxws", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "conv"},
+ { &test_xsrdpic, "xsrdpic", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xsrdpiz, "xsrdpiz", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xsrdpi, "xsrdpi", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvabsdp, "xvabsdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "abs"},
+ { &test_xvnabsdp, "xvnabsdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "nabs"},
+ { &test_xvnegdp, "xvnegdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "neg"},
+ { &test_xvabssp, "xvabssp", NULL, 20, SINGLE_TEST, VX_DEFAULT, "abs"},
+ { &test_xvnabssp, "xvnabssp", NULL, 20, SINGLE_TEST, VX_DEFAULT, "nabs"},
+ { &test_xvrdpi, "xvrdpi", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrdpic, "xvrdpic", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrdpim, "xvrdpim", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrdpip, "xvrdpip", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrdpiz, "xvrdpiz", NULL, 20, DOUBLE_TEST, VX_CONV_TO_DOUBLE, "round"},
+ { &test_xvrspi, "xvrspi", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { &test_xvrspic, "xvrspic", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { &test_xvrspim, "xvrspim", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { &test_xvrspip, "xvrspip", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { &test_xvrspiz, "xvrspiz", NULL, 20, SINGLE_TEST, VX_CONV_TO_SINGLE, "round"},
+ { NULL, NULL, NULL, 0, 0, 0, NULL}
+};
+
+static vx_fp_test_t
+vx_tdivORtsqrt_tests[] = {
+ { &test_xstsqrtdp, "xstsqrtdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "test-sqrt"},
+ { &test_xvtsqrtdp, "xvtsqrtdp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "test-sqrt"},
+ { &test_xvtsqrtsp, "xvtsqrtsp", NULL, 20, SINGLE_TEST, VX_DEFAULT, "test-sqrt"},
+ { &test_xvtdivdp, "xvtdivdp", two_arg_fp_tests, 68, DOUBLE_TEST, VX_DEFAULT, "test-div"},
+ { &test_xvtdivsp, "xvtdivsp", two_arg_fp_tests, 68, SINGLE_TEST, VX_DEFAULT, "test-div"},
+ { NULL, NULL, NULL, 0 , 0, 0, NULL}
+};
+
+static unsigned long long doubleWord[] = { 0,
+ 0xffffffff00000000LL,
+ 0x00000000ffffffffLL,
+ 0xffffffffffffffffLL,
+ 0x89abcde123456789LL,
+ 0x0102030405060708LL,
+ 0x00000000a0b1c2d3LL,
+ 0x1111222233334444LL
+};
+
+static unsigned int singleWord[] = {0,
+ 0xffff0000,
+ 0x0000ffff,
+ 0xffffffff,
+ 0x89a73522,
+ 0x01020304,
+ 0x0000abcd,
+ 0x11223344
+};
+
+typedef struct vx_intToFp_test
+{
+ test_func_t test_func;
+ const char * name;
+ void * targs;
+ int num_tests;
+ precision_type_t precision;
+ vx_fp_test_type type;
+} vx_intToFp_test_t;
+
+static vx_intToFp_test_t
+intToFp_tests[] = {
+ { test_xvcvsxddp, "xvcvsxddp", (void *)doubleWord, 8, DOUBLE_TEST, VX_CONV_TO_DOUBLE },
+ { test_xvcvuxddp, "xvcvuxddp", (void *)doubleWord, 8, DOUBLE_TEST, VX_CONV_TO_DOUBLE },
+ { test_xvcvsxdsp, "xvcvsxdsp", (void *)doubleWord, 8, DOUBLE_TEST, VX_CONV_TO_SINGLE },
+ { test_xvcvuxdsp, "xvcvuxdsp", (void *)doubleWord, 8, DOUBLE_TEST, VX_CONV_TO_SINGLE },
+ { test_xvcvsxwdp, "xvcvsxwdp", (void *)singleWord, 8, SINGLE_TEST, VX_CONV_TO_DOUBLE },
+ { test_xvcvuxwdp, "xvcvuxwdp", (void *)singleWord, 8, SINGLE_TEST, VX_CONV_TO_DOUBLE },
+ { test_xvcvsxwsp, "xvcvsxwsp", (void *)singleWord, 8, SINGLE_TEST, VX_CONV_TO_SINGLE },
+ { test_xvcvuxwsp, "xvcvuxwsp", (void *)singleWord, 8, SINGLE_TEST, VX_CONV_TO_SINGLE },
+ { NULL, NULL, NULL, 0, 0 }
+};
+
+static Bool do_OE;
+typedef enum {
+ DIV_BASE = 1,
+ DIV_OE = 2,
+ DIV_DOT = 4,
+} div_type_t;
+/* Possible divde type combinations are:
+ * - base
+ * - base+dot
+ * - base+OE
+ * - base+OE+dot
+ */
+#ifdef __powerpc64__
+static void test_divdeu(void)
+{
+ int divdeu_type = DIV_BASE;
+ if (do_OE)
+ divdeu_type |= DIV_OE;
+ if (do_dot)
+ divdeu_type |= DIV_DOT;
+
+ switch (divdeu_type) {
+ case 1:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeu %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 3:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeuo %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 5:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeu. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 7:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divdeuo. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ default:
+ fprintf(stderr, "Invalid divdeu type. Exiting\n");
+ exit(1);
+ }
+}
+#endif
+
+static void test_divwe(void)
+{
+ int divwe_type = DIV_BASE;
+ if (do_OE)
+ divwe_type |= DIV_OE;
+ if (do_dot)
+ divwe_type |= DIV_DOT;
+
+ switch (divwe_type) {
+ case 1:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divwe %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 3:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweo %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 5:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divwe. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ case 7:
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("divweo. %0, %1, %2" : "=r" (r17) : "r" (r14),"r" (r15));
+ GET_CR_XER(div_flags, div_xer);
+ break;
+ default:
+ fprintf(stderr, "Invalid divweu type. Exiting\n");
+ exit(1);
+ }
+}
+
+
+typedef struct simple_test {
+ test_func_t test_func;
+ char * name;
+ precision_type_t precision;
+} simple_test_t;
+
+
+static void setup_sp_fp_args(fp_test_args_t * targs, Bool swap_inputs)
+{
+ int a_idx, b_idx, i;
+ void * inA, * inB;
+ void * vec_src = swap_inputs ? &vec_out : &vec_inB;
+
+ for (i = 0; i < 4; i++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ inA = (void *)&spec_sp_fargs[a_idx];
+ inB = (void *)&spec_sp_fargs[b_idx];
+ // copy single precision FP into vector element i
+ memcpy(((void *)&vec_inA) + (i * 4), inA, 4);
+ memcpy(vec_src + (i * 4), inB, 4);
+ targs++;
+ }
+}
+
+static void setup_dp_fp_args(fp_test_args_t * targs, Bool swap_inputs)
+{
+ int a_idx, b_idx, i;
+ void * inA, * inB;
+ void * vec_src = swap_inputs ? (void *)&vec_out : (void *)&vec_inB;
+
+ for (i = 0; i < 2; i++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ inA = (void *)&spec_fargs[a_idx];
+ inB = (void *)&spec_fargs[b_idx];
+ // copy double precision FP into vector element i
+ memcpy(((void *)&vec_inA) + (i * 8), inA, 8);
+ memcpy(vec_src + (i * 8), inB, 8);
+ targs++;
+ }
+}
+
+#define VX_NOT_CMP_OP 0xffffffff
+static void print_vector_fp_result(unsigned int cc, vx_fp_test_t * test_group, int i, Bool print_vec_out)
+{
+ int a_idx, b_idx, k;
+ char * name = malloc(20);
+ int dp = test_group->precision == DOUBLE_TEST ? 1 : 0;
+ int loops = dp ? 2 : 4;
+ fp_test_args_t * targs = &test_group->targs[i];
+ unsigned long long * frA_dp, * frB_dp, * dst_dp;
+ unsigned int * frA_sp, *frB_sp, * dst_sp;
+ strcpy(name, test_group->name);
+ printf("#%d: %s%s ", dp? i/2 : i/4, name, (do_dot ? "." : ""));
+ for (k = 0; k < loops; k++) {
+ a_idx = targs->fra_idx;
+ b_idx = targs->frb_idx;
+ if (k)
+ printf(" AND ");
+ if (dp) {
+ frA_dp = (unsigned long long *)&spec_fargs[a_idx];
+ frB_dp = (unsigned long long *)&spec_fargs[b_idx];
+ printf("%016llx %s %016llx", *frA_dp, test_group->op, *frB_dp);
+ } else {
+ frA_sp = (unsigned int *)&spec_sp_fargs[a_idx];
+ frB_sp = (unsigned int *)&spec_sp_fargs[b_idx];
+ printf("%08x %s %08x", *frA_sp, test_group->op, *frB_sp);
+ }
+ targs++;
+ }
+ if (cc != VX_NOT_CMP_OP)
+ printf(" ? cc=%x", cc);
+
+ if (print_vec_out) {
+ if (dp) {
+ dst_dp = (unsigned long long *) &vec_out;
+ printf(" => %016llx %016llx\n", dst_dp[0], dst_dp[1]);
+ } else {
+ dst_sp = (unsigned int *) &vec_out;
+ printf(" => %08x %08x %08x %08x\n", dst_sp[0], dst_sp[1], dst_sp[2], dst_sp[3]);
+ }
+ } else {
+ printf("\n");
+ }
+ free(name);
+}
+
+
+
+static void test_vsx_one_fp_arg(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+ build_special_fargs_table();
+
+ while ((func = vsx_one_fp_arg_tests[k].test_func)) {
+ int idx, i;
+ vx_fp_test_t test_group = vsx_one_fp_arg_tests[k];
+ Bool estimate = (test_group.type == VX_ESTIMATE);
+ Bool dp = (test_group.precision == DOUBLE_TEST) ? True : False;
+ Bool is_sqrt = (strstr(test_group.name, "sqrt")) ? True : False;
+ Bool is_scalar = (strstr(test_group.name, "xs")) ? True : False;
+ Bool sparse_sp = False;
+ int stride = dp ? 2 : 4;
+ int loops = is_scalar ? 1 : stride;
+ stride = is_scalar ? 1: stride;
+
+ /* For conversions of single to double, the 128-bit input register is sparsely populated:
+ * |___ SP___|_Unused_|___SP___|__Unused__| // for vector op
+ * or
+ * |___ SP___|_Unused_|_Unused_|__Unused__| // for scalar op
+ *
+ * For the vector op case, we need to adjust stride from '4' to '2', since
+ * we'll only be loading two values per loop into the input register.
+ */
+ if (!dp && !is_scalar && test_group.type == VX_CONV_TO_DOUBLE) {
+ sparse_sp = True;
+ stride = 2;
+ }
+
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv;
+ void * inB, * vecB_void_ptr = (void *)&vec_inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (dp) {
+ int j;
+ unsigned long long * frB_dp, *dst_dp;
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_fargs[i + j];
+ // copy double precision FP into vector element i
+ if (isLE && is_scalar)
+ vecB_void_ptr += 8;
+ memcpy(vecB_void_ptr + (j * 8), inB, 8);
+ }
+ // execute test insn
+ (*func)();
+ dst_dp = (unsigned long long *) &vec_out;
+ if (isLE && is_scalar)
+ dst_dp++;
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ frB_dp = (unsigned long long *)&spec_fargs[i + j];
+ printf("%s(%016llx)", test_group.op, *frB_dp);
+ if (estimate) {
+ Bool res = check_estimate(DOUBLE_TEST, is_sqrt, i + j, (isLE && is_scalar) ? 1: j);
+ printf(" ==> %s)", res ? "PASS" : "FAIL");
+ /* For debugging . . .
+ printf(" ==> %s (res=%016llx)", res ? "PASS" : "FAIL", dst_dp[j]);
+ */
+ } else {
+ vx_fp_test_type type = test_group.type;
+ switch (type) {
+ case VX_SCALAR_CONV_TO_WORD:
+ printf(" = %016llx", dst_dp[j] & 0x00000000ffffffffULL);
+ break;
+ case VX_CONV_TO_SINGLE:
+ printf(" = %016llx", dst_dp[j] & 0xffffffff00000000ULL);
+ break;
+ default: // For VX_CONV_TO_DOUBLE and non-convert instructions . . .
+ printf(" = %016llx", dst_dp[j]);
+ }
+ }
+ }
+ printf("\n");
+ } else {
+ int j;
+ unsigned int * frB_sp, * dst_sp = NULL;
+ unsigned long long * dst_dp = NULL;
+ if (sparse_sp)
+ loops = 2;
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_sp_fargs[i + j];
+ // copy single precision FP into vector element i
+ if (sparse_sp) {
+ if (isLE)
+ memcpy(vecB_void_ptr + ((2 * j * 4) + 4), inB, 4);
+ else
+ memcpy(vecB_void_ptr + ((2 * j * 4) ), inB, 4);
+ } else {
+ if (isLE && is_scalar)
+ vecB_void_ptr += 12;
+ memcpy(vecB_void_ptr + (j * 4), inB, 4);
+ }
+ }
+ // execute test insn
+ (*func)();
+ if (test_group.type == VX_CONV_TO_DOUBLE) {
+ dst_dp = (unsigned long long *) &vec_out;
+ if (isLE && is_scalar)
+ dst_dp++;
+ } else {
+ dst_sp = (unsigned int *) &vec_out;
+ if (isLE && is_scalar)
+ dst_sp += 3;
+ }
+ // print result
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ frB_sp = (unsigned int *)&spec_sp_fargs[i + j];
+ printf("%s(%08x)", test_group.op, *frB_sp);
+ if (estimate) {
+ Bool res = check_estimate(SINGLE_TEST, is_sqrt, i + j, (isLE && is_scalar) ? 3 : j);
+ printf(" ==> %s)", res ? "PASS" : "FAIL");
+ } else {
+ if (test_group.type == VX_CONV_TO_DOUBLE)
+ printf(" = %016llx", dst_dp[j]);
+ else
+ /* Special case: Current VEX implementation for fsqrts (single precision)
+ * uses the same implementation as that used for double precision fsqrt.
+ * However, I've found that for xvsqrtsp, the result from that implementation
+ * may be off by the two LSBs. Generally, even this small inaccuracy can cause the
+ * output to appear very different if you end up with a carry. But for the given
+ * inputs in this testcase, we can simply mask out these bits.
+ */
+ printf(" = %08x", is_sqrt ? (dst_sp[j] & 0xfffffffc) : dst_sp[j]);
+ }
+ }
+ printf("\n");
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+static void test_int_to_fp_convert(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = intToFp_tests[k].test_func)) {
+ int idx, i;
+ vx_intToFp_test_t test_group = intToFp_tests[k];
+ Bool dp = (test_group.precision == DOUBLE_TEST) ? True : False;
+ Bool sparse_sp = False;
+ int stride = dp ? 2 : 4;
+ int loops = stride;
+
+ /* For conversions of single to double, the 128-bit input register is sparsely populated:
+ * |___ int___|_Unused_|___int___|__Unused__| // for vector op
+ * or
+ * We need to adjust stride from '4' to '2', since we'll only be loading
+ * two values per loop into the input register.
+ */
+ if (!dp && test_group.type == VX_CONV_TO_DOUBLE) {
+ sparse_sp = True;
+ stride = 2;
+ }
+
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv;
+ void * inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (dp) {
+ int j;
+ unsigned long long *dst_dw, * targs = test_group.targs;
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&targs[i + j];
+ // copy doubleword into vector element i
+ memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
+ }
+ // execute test insn
+ (*func)();
+ dst_dw = (unsigned long long *) &vec_out;
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ printf("conv(%016llx)", targs[i + j]);
+
+ if (test_group.type == VX_CONV_TO_SINGLE)
+ printf(" = %016llx", dst_dw[j] & 0xffffffff00000000ULL);
+ else
+ printf(" = %016llx", dst_dw[j]);
+ }
+ printf("\n");
+ } else {
+ int j;
+ unsigned int * dst_sp = NULL;
+ unsigned int * targs = test_group.targs;
+ unsigned long long * dst_dp = NULL;
+ void * vecB_void_ptr = (void *)&vec_inB;
+ if (sparse_sp)
+ loops = 2;
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&targs[i + j];
+ // copy single word into vector element i
+ if (sparse_sp) {
+ if (isLE)
+ memcpy(vecB_void_ptr + ((2 * j * 4) + 4), inB, 4);
+ else
+ memcpy(vecB_void_ptr + ((2 * j * 4) ), inB, 4);
+ } else {
+ memcpy(vecB_void_ptr + (j * 4), inB, 4);
+ }
+ }
+ // execute test insn
+ (*func)();
+ if (test_group.type == VX_CONV_TO_DOUBLE)
+ dst_dp = (unsigned long long *) &vec_out;
+ else
+ dst_sp = (unsigned int *) &vec_out;
+ // print result
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ printf("conv(%08x)", targs[i + j]);
+ if (test_group.type == VX_CONV_TO_DOUBLE)
+ printf(" = %016llx", dst_dp[j]);
+ else
+ printf(" = %08x", dst_sp[j]);
+ }
+ printf("\n");
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+
+// The div doubleword test data
+signed long long div_dw_tdata[13][2] = {
+ { 4, -4 },
+ { 4, -3 },
+ { 4, 4 },
+ { 4, -5 },
+ { 3, 8 },
+ { 0x8000000000000000ULL, 0xa },
+ { 0x50c, -1 },
+ { 0x50c, -4096 },
+ { 0x1234fedc, 0x8000a873 },
+ { 0xabcd87651234fedcULL, 0xa123b893 },
+ { 0x123456789abdcULL, 0 },
+ { 0, 2 },
+ { 0x77, 0xa3499 }
+};
+#define dw_tdata_len (sizeof(div_dw_tdata)/sizeof(signed long long)/2)
+
+// The div word test data
+unsigned int div_w_tdata[6][2] = {
+ { 0, 2 },
+ { 2, 0 },
+ { 0x7abc1234, 0xf0000000 },
+ { 0xfabc1234, 5 },
+ { 77, 66 },
+ { 5, 0xfabc1234 },
+};
+#define w_tdata_len (sizeof(div_w_tdata)/sizeof(unsigned int)/2)
+
+typedef struct div_ext_test
+{
+ test_func_t test_func;
+ const char *name;
+ int num_tests;
+ div_type_t div_type;
+ precision_type_t precision;
+} div_ext_test_t;
+
+static div_ext_test_t div_tests[] = {
+#ifdef __powerpc64__
+ { &test_divdeu, "divdeu", dw_tdata_len, DIV_BASE, DOUBLE_TEST },
+ { &test_divdeu, "divdeuo", dw_tdata_len, DIV_OE, DOUBLE_TEST },
+#endif
+ { &test_divwe, "divwe", w_tdata_len, DIV_BASE, SINGLE_TEST },
+ { &test_divwe, "divweo", w_tdata_len, DIV_OE, SINGLE_TEST },
+ { NULL, NULL, 0, 0, 0 }
+};
+
+static void test_div_extensions(void)
+{
+ test_func_t func;
+ int k;
+ k = 0;
+
+ while ((func = div_tests[k].test_func)) {
+ int i, repeat = 1;
+ div_ext_test_t test_group = div_tests[k];
+ do_dot = False;
+
+again:
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int condreg;
+
+ if (test_group.div_type == DIV_OE)
+ do_OE = True;
+ else
+ do_OE = False;
+
+ if (test_group.precision == DOUBLE_TEST) {
+ r14 = div_dw_tdata[i][0];
+ r15 = div_dw_tdata[i][1];
+ } else {
+ r14 = div_w_tdata[i][0];
+ r15 = div_w_tdata[i][1];
+ }
+ // execute test insn
+ (*func)();
+ condreg = (div_flags & 0xf0000000) >> 28;
+ printf("#%d: %s%s: ", i, test_group.name, do_dot ? "." : "");
+ if (test_group.precision == DOUBLE_TEST) {
+ printf("0x%016llx0000000000000000 / 0x%016llx = 0x%016llx;",
+ div_dw_tdata[i][0], div_dw_tdata[i][1], (signed long long) r17);
+ } else {
+ printf("0x%08x00000000 / 0x%08x = 0x%08x;",
+ div_w_tdata[i][0], div_w_tdata[i][1], (unsigned int) r17);
+ }
+ printf(" CR=%x; XER=%x\n", condreg, div_xer);
+ }
+ printf("\n");
+ if (repeat) {
+ repeat = 0;
+ do_dot = True;
+ goto again;
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static void test_vx_tdivORtsqrt(void)
+{
+ test_func_t func;
+ int k, crx;
+ unsigned int flags;
+ k = 0;
+ do_dot = False;
+ build_special_fargs_table();
+
+ while ((func = vx_tdivORtsqrt_tests[k].test_func)) {
+ int idx, i;
+ vx_fp_test_t test_group = vx_tdivORtsqrt_tests[k];
+ Bool dp = (test_group.precision == DOUBLE_TEST) ? True : False;
+ Bool is_scalar = (strstr(test_group.name, "xs")) ? True : False;
+ Bool two_args = test_group.targs ? True : False;
+ int stride = dp ? 2 : 4;
+ int loops = is_scalar ? 1 : stride;
+ stride = is_scalar ? 1: stride;
+
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv;
+ void * inB, * vecB_void_ptr = (void *)&vec_inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+
+ if (dp) {
+ int j;
+ unsigned long long * frB_dp;
+ if (two_args) {
+ setup_dp_fp_args(&test_group.targs[i], False);
+ } else {
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_fargs[i + j];
+ // copy double precision FP into vector element i
+ if (isLE && is_scalar)
+ vecB_void_ptr += 8;
+ memcpy(vecB_void_ptr + (j * 8), inB, 8);
+ }
+ }
+ // execute test insn
+ // Must do set/get of CRs immediately before/after calling the asm func
+ // to avoid CRs being modified by other instructions.
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ // assumes using CR1
+ crx = (flags & 0x0f000000) >> 24;
+ if (two_args) {
+ print_vector_fp_result(crx, &test_group, i, False/*do not print vec_out*/);
+ } else {
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ frB_dp = (unsigned long long *)&spec_fargs[i + j];
+ printf("%s(%016llx)", test_group.op, *frB_dp);
+ }
+ printf( " ? %x (CRx)\n", crx);
+ }
+ } else {
+ int j;
+ unsigned int * frB_sp;
+ if (two_args) {
+ setup_sp_fp_args(&test_group.targs[i], False);
+ } else {
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_sp_fargs[i + j];
+ // copy single precision FP into vector element i
+ memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
+ }
+ }
+ // execute test insn
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+ GET_CR(flags);
+ crx = (flags & 0x0f000000) >> 24;
+ // print result
+ if (two_args) {
+ print_vector_fp_result(crx, &test_group, i, False/*do not print vec_out*/);
+ } else {
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+ printf("; ");
+ frB_sp = (unsigned int *)&spec_sp_fargs[i + j];
+ printf("%s(%08x)", test_group.op, *frB_sp);
+ }
+ printf( " ? %x (CRx)\n", crx);
+ }
+ }
+ }
+ k++;
+ printf( "\n" );
+ }
+}
+
+
+static void test_ftsqrt(void)
+{
+ int i, crx;
+ unsigned int flags;
+ unsigned long long * frbp;
+ build_special_fargs_table();
+
+
+ for (i = 0; i < nb_special_fargs; i++) {
+ f14 = spec_fargs[i];
+ frbp = (unsigned long long *)&spec_fargs[i];
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ __asm__ __volatile__ ("ftsqrt cr1, %0" : : "d" (f14));
+ GET_CR(flags);
+ crx = (flags & 0x0f000000) >> 24;
+ printf( "ftsqrt: %016llx ? %x (CRx)\n", *frbp, crx);
+ }
+ printf( "\n" );
+}
+
+static void
+test_popcntw(void)
+{
+#ifdef __powerpc64__
+ uint64_t res;
+ unsigned long long src = 0x9182736405504536ULL;
+ r14 = src;
+ __asm__ __volatile__ ("popcntw %0, %1" : "=r" (res): "r" (r14));
+ printf("popcntw: 0x%llx => 0x%016llx\n", (unsigned long long)src, (unsigned long long)res);
+#else
+ uint32_t res;
+ unsigned int src = 0x9182730E;
+ r14 = src;
+ __asm__ __volatile__ ("popcntw %0, %1" : "=r" (res): "r" (r14));
+ printf("popcntw: 0x%x => 0x%08x\n", src, (int)res);
+#endif
+ printf( "\n" );
+}
+
+
+static test_table_t
+ all_tests[] =
+{
+
+ { &test_vsx_one_fp_arg,
+ "Test VSX vector and scalar single argument instructions"} ,
+ { &test_int_to_fp_convert,
+ "Test VSX vector integer to float conversion instructions" },
+ { &test_div_extensions,
+ "Test div extensions" },
+ { &test_ftsqrt,
+ "Test ftsqrt instruction" },
+ { &test_vx_tdivORtsqrt,
+ "Test vector and scalar tdiv and tsqrt instructions" },
+ { &test_popcntw,
+ "Test popcntw instruction" },
+ { NULL, NULL }
+};
+#endif // HAS_VSX
+
+int main(int argc, char *argv[])
+{
+#ifdef HAS_VSX
+
+ test_table_t aTest;
+ test_func_t func;
+ int i = 0;
+
+ while ((func = all_tests[i].test_category)) {
+ aTest = all_tests[i];
+ printf( "%s\n", aTest.name );
+ (*func)();
+ i++;
+ }
+ if (spec_fargs)
+ free(spec_fargs);
+ if (spec_sp_fargs)
+ free(spec_sp_fargs);
+
+#endif // HAS _VSX
+
+ return 0;
+}
diff --git a/none/tests/ppc64/test_isa_2_07_part1.c b/none/tests/ppc64/test_isa_2_07_part1.c
index be0a5ed..73a563c 100644
--- a/none/tests/ppc64/test_isa_2_07_part1.c
+++ b/none/tests/ppc64/test_isa_2_07_part1.c
@@ -874,7 +874,8 @@
static int arg_list_size = 0;
static unsigned long long * vdargs = NULL;
static unsigned long long * vdargs_x = NULL;
-#define NB_VDARGS 4
+#define NB_VDARGS 9
+#define NB_VDARGS_X 4
static void build_vdargs_table (void)
{
@@ -884,8 +885,13 @@
vdargs[1] = 0x090A0B0C0E0D0E0FULL;
vdargs[2] = 0xF1F2F3F4F5F6F7F8ULL;
vdargs[3] = 0xF9FAFBFCFEFDFEFFULL;
+ vdargs[4] = 0x00007FFFFFFFFFFFULL;
+ vdargs[5] = 0xFFFF000000000000ULL;
+ vdargs[6] = 0x0000800000000000ULL;
+ vdargs[7] = 0x0000000000000000ULL;
+ vdargs[8] = 0xFFFFFFFFFFFFFFFFULL;
- vdargs_x = memalign16(NB_VDARGS * sizeof(unsigned long long));
+ vdargs_x = memalign16(NB_VDARGS_X * sizeof(unsigned long long));
vdargs_x[0] = 0x000000007c118a2bULL;
vdargs_x[1] = 0x00000000f1112345ULL;
vdargs_x[2] = 0x01F2F3F4F5F6F7F8ULL;
@@ -922,7 +928,8 @@
0x0ULL, // Invalid BCD zero (no sign code)
0x0ULL
};
-#define NUM_VBCD_VALS (sizeof vbcd_args/sizeof vbcd_args[0])
+//#define NUM_VBCD_VALS (sizeof vbcd_args/sizeof vbcd_args[0])
+#define NUM_VBCD_VALS 8
static void build_vargs_table (void)
{
@@ -1288,12 +1295,12 @@
else
is_vpmsumd = 0;
- for (i = 0; i < NB_VDARGS; i+=2) {
+ for (i = 0; i < NB_VDARGS - 1; i+=2) {
if (isLE && family == PPC_ALTIVECQ)
vec_inA = (vector unsigned long long){ vdargs[i+1], vdargs[i] };
else
vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
- for (j = 0; j < NB_VDARGS; j+=2) {
+ for (j = 0; j < NB_VDARGS - 1; j+=2) {
if (isLE && family == PPC_ALTIVECQ)
vec_inB = (vector unsigned long long){ vdargs[j+1], vdargs[j] };
else
@@ -1353,7 +1360,7 @@
unsigned long long * dst;
int i;
- for (i = 0; i < NB_VDARGS; i+=2) {
+ for (i = 0; i < NB_VDARGS - 1; i+=2) {
vec_inB = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
vec_out = (vector unsigned long long){ 0,0 };
@@ -1372,7 +1379,7 @@
unsigned long long * dst;
int i, st, six;
- for (i = 0; i < NB_VDARGS; i+=2) {
+ for (i = 0; i < NB_VDARGS - 1; i+=2) {
vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
vec_out = (vector unsigned long long){ 0,0 };
@@ -1396,14 +1403,14 @@
unsigned long long * dst;
int i, j;
- for (i = 0; i < NUM_VBCD_VALS; i+=2) {
+ for (i = 0; i < NUM_VBCD_VALS - 1; i+=2) {
if (isLE)
- vec_inA = (vector unsigned long long){ vbcd_args[i+1], vbcd_args[i] };
+ vec_inA = (vector unsigned long long){ vbcd_args[i+1], vbcd_args[i]};
else
vec_inA = (vector unsigned long long){ vbcd_args[i], vbcd_args[i+1] };
- for (j = 0; j < NUM_VBCD_VALS; j+=2) {
+ for (j = 0; j < NUM_VBCD_VALS - 1; j+=2) {
if (isLE)
- vec_inB = (vector unsigned long long){ vbcd_args[j+1], vbcd_args[j] };
+ vec_inB = (vector unsigned long long){ vbcd_args[j+1] , vbcd_args[j] };
else
vec_inB = (vector unsigned long long){ vbcd_args[j], vbcd_args[j+1] };
vec_out = (vector unsigned long long){ 0, 0 };
@@ -1431,9 +1438,9 @@
unsigned int * dst_int;
int i,j;
- for (i = 0; i < NB_VDARGS; i+=2) {
+ for (i = 0; i < NB_VDARGS_X - 1; i+=2) {
vec_inA = (vector unsigned long long){ vdargs_x[i], vdargs_x[i+1] };
- for (j = 0; j < NB_VDARGS; j+=2) {
+ for (j = 0; j < NB_VDARGS_X - 1; j+=2) {
vec_inB = (vector unsigned long long){ vdargs_x[j], vdargs_x[j+1] };
vec_out = (vector unsigned long long){ 0,0 };
@@ -1671,17 +1678,17 @@
0xf000000000000000ULL, 0xf000000000000000ULL,
0xf000000000000000ULL, 0xf000000000000001ULL
};
- for (i = 0; i < NB_VDARGS; i+=2) {
+ for (i = 0; i < NB_VDARGS - 1; i+=2) {
if (isLE)
vec_inA = (vector unsigned long long){ vdargs[i+1], vdargs[i] };
else
vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
- for (j = 0; j < NB_VDARGS; j+=2) {
+ for (j = 0; j < NB_VDARGS - 1; j+=2) {
if (isLE)
vec_inB = (vector unsigned long long){ vdargs[j+1], vdargs[j] };
else
vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
- for (k = 0; k < 4; k+=2) {
+ for (k = 0; k < 4 - 1; k+=2) {
if (family == PPC_ALTIVECQ) {
if (isLE)
vec_inC = (vector unsigned long long){ cin_vals[k+1], cin_vals[k] };
diff --git a/none/tests/ppc64/test_isa_3_0.c b/none/tests/ppc64/test_isa_3_0.c
new file mode 100644
index 0000000..5f5cd18
--- /dev/null
+++ b/none/tests/ppc64/test_isa_3_0.c
@@ -0,0 +1,4121 @@
+/* HOW TO COMPILE:
+ * 64bit build:
+ * gcc -Winline -Wall -g -O -mregnames -maltivec -m64
+ */
+
+/*
+ * test_isa_3_0.c:
+ * Copyright (c) 2016 Carl Love <cel@us.ibm.com>
+ * Copyright (c) 2016 Will Schmidt <will_schmidt@vnet.ibm.com>
+ *
+ * This testfile contains tests for the ISA 3.0 instructions.
+ * The framework of this test file was based on the framework
+ * of the jm-insns.c testfile, whose original author was
+ * Jocelyn Mayer.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License V2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ * Theory of operations:
+ * a few registers are reserved for the test program:
+ * r14...r18
+ * f14...f18
+ * - pre-load test values in r14 through r17
+ * - patch the test opcode if any immediate operands are
+ * required
+ * - execute the tested opcode.
+ * CR and FPSCR are cleared before every test.
+ * results in {r,f}17
+ * check FPSCR for floating point operations.
+ */
+
+/*
+ * Operation details
+ * -----------------
+ * The 'test' functions (via all_tests[]) are wrappers of
+ * single __asm__ instructions
+ *
+ * The 'loops' (e.g. int_loops) do the actual work:
+ * - loops over as many arguments as the instruction needs (regs | imms)
+ * - sets up the environment (reset cr, assign src regs...)
+ * - maybe modifies the asm instruction to test different immediate args
+ * - call the test function
+ * - retrieve relevant register data (rD,cr,...)
+ * - prints argument and result data.
+ *
+ * all_tests[i] holds instruction tests
+ * - of which each holds: {instn_test_arr[], description, flags}
+ *
+ * flags hold 3 instruction classifiers: {family, type, arg_type}
+ *
+ * // The main test loop:
+ * do_tests( user_ctl_flags ) {
+ * foreach(curr_test = all_test[i]) {
+ *
+ * // flags are used to control what tests are run:
+ * if (curr_test->flags && !user_ctl_flags)
+ * continue;
+ *
+ * // a 'loop_family_arr' is chosen based on the 'family' flag...
+ * switch(curr_test->flags->family) {
+ * case x: loop_family_arr = int_loops;
+ * ...
+ * }
+ *
+ * // ...and the actual test_loop to run is found by indexing into
+ * // the loop_family_arr with the 'arg_type' flag:
+ * test_loop = loop_family[curr_test->flags->arg_type]
+ *
+ * // finally, loop over all instn tests for this test:
+ * foreach (instn_test = curr_test->instn_test_arr[i]) {
+ *
+ * // and call the test_loop with the current instn_test function,name
+ * test_loop( instn_test->func, instn_test->name )
+ * }
+ * }
+ * }
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+
+/* This test is only valid on machines that support IBM POWER ISA 3.0. */
+#ifdef HAS_ISA_3_00
+
+#include <assert.h>
+#include <ctype.h> // isspace
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h> // getopt
+#include <altivec.h> // vector
+
+#undef DEBUG_VECTOR_PERMUTE
+static int verbose = 0;
+
+#include "../ppc64/ppc64_helpers.h" // SET_CR() and friends.
+
+#define VERBOSE_FUNCTION_CALLOUT \
+ if (verbose) \
+ printf("Test Harness Function: %s\n", __FUNCTION__);
+
+/* generic out-of-range reporting.
+ * Note: results are typically 'undefined' in these cases, so rather than
+ * pushing through and getting potentially random results, avoid the check.
+ * The caller should suppress output when insert_extract_error is set. */
+#define vinsertextract_err \
+ insert_extract_error = 1; \
+ if (verbose > 1) \
+ printf("Expected error - index out of range in %s (%d)\n", \
+ __FUNCTION__, x_index);
+
+#define MAX(x, y) (x > y ? x : y)
+
+/* Used in do_tests, indexed by flags->nb_args
+ Elements correspond to enum test_flags::num args
+*/
+
+/* XXXX these must all be callee-save regs! */
+register HWord_t r14 __asm__ ("r14");
+register HWord_t r15 __asm__ ("r15");
+register HWord_t r16 __asm__ ("r16");
+register HWord_t r17 __asm__ ("r17");
+register double f14 __asm__ ("fr14");
+register double f15 __asm__ ("fr15");
+
+/* globals used for vector tests */
+static vector unsigned long vec_xa, vec_xb, vec_xc, vec_xt;
+
+/* globals for the condition register fields. These are used to
+ * capture the condition register values immediately after the
+ * instruction under test is tested.
+ * This is to help prevent other test overhead, switch statements,
+ * compares, what-not from interfering.
+ */
+unsigned long local_cr;
+unsigned long local_fpscr;
+volatile unsigned int cr_value;
+
+/* global for holding the DFP values */
+dfp_val_t dfp_value;
+
+/* individual instruction tests */
+typedef void (*test_func_t) (void);
+struct test_list_t {
+ test_func_t func;
+ const char *name;
+};
+typedef struct test_list_t test_list_t;
+
+/* global variable, used to pass shift info down to the test functions.*/
+volatile int x_shift;
+
+/* Indicator for DCMX (Data Class Mask) matches. */
+volatile int dcmx_match;
+
+/* Error indicator to determine of the UIN (Unsigned Immediate) field
+ * from insert/extract was out of range */
+volatile int insert_extract_error;
+
+/* vector splat value */
+volatile int x_splat;
+volatile int dfp_significance;
+
+/* global variable, ... vector insert functions. */
+volatile int x_index;
+
+/* global variable, used to pass shift info down to the test functions.*/
+volatile int x_shift;
+
+/* groups of instruction tests, calling individual tests */
+typedef void (*test_group_t) (const char *name, test_func_t func,
+ unsigned int test_flags);
+
+enum test_flags {
+ /* Nb arguments */
+ PPC_ONE_ARG = 0x00000001,
+ PPC_TWO_ARGS = 0x00000002,
+ PPC_THREE_ARGS = 0x00000003,
+ PPC_FOUR_ARGS = 0x00000004,
+ PPC_COMPARE_ARGS = 0x00000005,
+ PPC_LD_ARGS = 0x00000006,
+ PPC_ST_ARGS = 0x00000007,
+ PPC_ONE_IMM = 0x00000008,
+ PPC_NB_ARGS_MASK = 0x0000000F,
+
+ /* Type */
+ PPC_ARITH = 0x00000100,
+ PPC_LOGICAL = 0x00000200,
+ PPC_COMPARE = 0x00000300,
+ PPC_LDST = 0x00000400,
+ PPC_POPCNT = 0x00000500,
+ PPC_INSERTEXTRACT = 0x00000600,
+ PPC_PERMUTE = 0x00000700,
+ PPC_ROUND = 0x00000800,
+ PPC_TYPE_MASK = 0x00000F00,
+
+ /* Family */
+ PPC_INTEGER = 0x00010000,
+ PPC_ALTIVEC = 0x00030000,
+ PPC_ALTIVEC_QUAD = 0x00040000,
+ PPC_ALTIVEC_DOUBLE = 0x00050000,
+ PPC_DFP = 0x00060000,
+ PPC_BCD = 0x00070000,
+ PPC_MISC = 0x00080000,
+ PPC_NO_OP = 0x00090000,
+ PPC_PC_IMMEDIATE = 0x000A0000,
+ PPC_FAMILY_MASK = 0x000F0000,
+
+ /* Flags: these may be combined, so use separate bit-fields. */
+ PPC_CR = 0x01000000,
+ PPC_XER_CA = 0x02000000,
+};
+
+static void test_cnttzw (void)
+{
+ __asm__ __volatile__ ("cnttzw 17, 14");
+}
+
+static void test_cnttzd (void)
+{
+ __asm__ __volatile__ ("cnttzd 17, 14");
+}
+
+static void test_dotted_cnttzw (void)
+{
+ __asm__ __volatile__ ("cnttzw. 17, 14");
+}
+
+static void test_dotted_cnttzd (void)
+{
+ __asm__ __volatile__ ("cnttzd. 17, 14");
+}
+
+static test_list_t testgroup_logical_one[] = {
+ { &test_cnttzw , "cnttzw" },
+ { &test_cnttzd , "cnttzd" },
+ { &test_dotted_cnttzw, "cnttzw." },
+ { &test_dotted_cnttzd, "cnttzd." },
+ { NULL , NULL },
+};
+
+static void test_modsw (void)
+{
+ __asm__ __volatile__ ("modsw 17, 14, 15");
+}
+
+static void test_moduw (void)
+{
+ __asm__ __volatile__ ("moduw 17, 14, 15");
+}
+
+static void test_modsd (void)
+{
+ __asm__ __volatile__ ("modsd 17, 14, 15");
+}
+
+static void test_modud (void)
+{
+ __asm__ __volatile__ ("modud 17, 14, 15");
+}
+
+static test_list_t testgroup_ia_ops_two[] = {
+ { &test_modsw, "modsw" },
+ { &test_moduw, "moduw" },
+ { &test_modsd, "modsd" },
+ { &test_modud, "modud" },
+ { NULL , NULL },
+};
+
+static void test_dotted_extswsli (void)
+{
+ switch(x_shift) {
+ case SH_0:
+ __asm__ __volatile__ ("extswsli. %0, %1, %2" : "=r" (r17) : "r" (r14), "i" (SH_0) );
+ break;
+
+ case SH_1:
+ __asm__ __volatile__ ("extswsli. %0, %1, %2" : "=r" (r17) : "r" (r14), "i" (SH_1) );
+ break;
+
+ case SH_2:
+ __asm__ __volatile__ ("extswsli. %0, %1, %2" : "=r" (r17) : "r" (r14), "i" (SH_2) );
+ break;
+
+ case SH_3:
+ __asm__ __volatile__ ("extswsli. %0, %1, %2" : "=r" (r17) : "r" (r14), "i" (SH_3) );
+ break;
+
+ default:
+ printf("Unhandled shift value for extswsli. %d\n", x_shift);
+ }
+}
+
+static void test_extswsli (void)
+{
+ switch(x_shift) {
+ case SH_0:
+ __asm__ __volatile__ ("extswsli %0, %1, %2" : "=r" (r17) : "r" (r14), "i"(SH_0));
+ break;
+
+ case SH_1:
+ __asm__ __volatile__ ("extswsli %0, %1, %2" : "=r" (r17) : "r" (r14), "i"(SH_1));
+ break;
+
+ case SH_2:
+ __asm__ __volatile__ ("extswsli %0, %1, %2" : "=r" (r17) : "r" (r14), "i"(SH_2));
+ break;
+
+ case SH_3:
+ __asm__ __volatile__ ("extswsli %0, %1, %2" : "=r" (r17) : "r" (r14), "i"(SH_3));
+ break;
+
+ default:
+ printf("Unhandled shift value for extswsli %d\n", x_shift);
+ }
+}
+
+static test_list_t testgroup_shifted_one[] = {
+ { &test_extswsli , "extswsli " },
+ { &test_dotted_extswsli, "extswsli." },
+ { NULL , NULL },
+};
+
+static void test_maddhd (void)
+{
+ __asm__ __volatile__ ("maddhd 17, 14, 15, 16");
+}
+static void test_maddhdu (void)
+{
+ __asm__ __volatile__ ("maddhdu 17, 14, 15, 16");
+}
+static void test_maddld (void)
+{
+ __asm__ __volatile__ ("maddld 17, 14, 15, 16");
+}
+
+static test_list_t testgroup_three_args[] = {
+ { &test_maddhd , "maddhd " },
+ { &test_maddhdu, "maddhdu" },
+ { &test_maddld , "maddld " },
+ { NULL , NULL },
+};
+
+/* VSX vector permutes. */
+static void test_xxperm (void)
+{
+ __asm__ __volatile__ ("xxperm %x0, %x1, %x2" : "+wa" (vec_xt): "wa" (vec_xa), "wa" (vec_xb));
+}
+
+/* VSX vector permute, right indexed. */
+static void test_xxpermr (void)
+{
+ __asm__ __volatile__ ("xxpermr %x0, %x1, %x2" : "+wa" (vec_xt): "wa" (vec_xa), "wa" (vec_xb));
+}
+
+static test_list_t testgroup_vsx_xxpermute[] = {
+ { &test_xxperm , "xxperm" },
+ { &test_xxpermr, "xxpermr" },
+ { NULL , NULL },
+};
+
+static void test_vabsdub(void) {
+ __asm__ __volatile__ ("vabsdub %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vabsduh(void) {
+ __asm__ __volatile__ ("vabsduh %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vabsduw(void) {
+ __asm__ __volatile__ ("vabsduw %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vcmpneb(void) {
+ __asm__ __volatile__ ("vcmpneb %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_dotted_vcmpneb(void) {
+ __asm__ __volatile__ ("vcmpneb. %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vcmpnezb(void) {
+ __asm__ __volatile__ ("vcmpnezb %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_dotted_vcmpnezb(void) {
+ __asm__ __volatile__ ("vcmpnezb. %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vcmpneh(void) {
+ __asm__ __volatile__ ("vcmpneh %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_dotted_vcmpneh(void) {
+ __asm__ __volatile__ ("vcmpneh. %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vcmpnezh(void) {
+ __asm__ __volatile__ ("vcmpnezh %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_dotted_vcmpnezh(void) {
+ __asm__ __volatile__ ("vcmpnezh. %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vcmpnew(void) {
+ __asm__ __volatile__ ("vcmpnew %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_dotted_vcmpnew(void) {
+ __asm__ __volatile__ ("vcmpnew. %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vcmpnezw(void) {
+ __asm__ __volatile__ ("vcmpnezw %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_dotted_vcmpnezw(void) {
+ __asm__ __volatile__ ("vcmpnezw. %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vrlwmi(void) {
+ __asm__ __volatile__ ("vrlwmi %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vrldmi(void) {
+ __asm__ __volatile__ ("vrldmi %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vbpermd(void) {
+/* vector bit permute doubleword */
+ __asm__ __volatile__ ("vbpermd %0, %1, %2 " : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vrlwnm(void) {
+ __asm__ __volatile__ ("vrlwnm %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vrldnm(void) {
+ __asm__ __volatile__ ("vrldnm %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_xviexpdp(void) {
+ __asm__ __volatile__ ("xviexpdp %0, %1, %2 " : "+wa" (vec_xt): "wa" (vec_xa), "wa" (vec_xb));
+}
+
+static void test_xviexpsp(void) {
+ __asm__ __volatile__ ("xviexpsp %0, %1, %2 " : "+wa" (vec_xt): "wa" (vec_xa), "wa" (vec_xb));
+}
+
+static test_list_t testgroup_vsx_absolute[] = {
+ { &test_vabsdub , "vabsdub" },
+ { &test_vabsduh , "vabsduh" },
+ { &test_vabsduw , "vabsduw" },
+ { &test_vcmpneb , "vcmpneb" },
+ { &test_dotted_vcmpneb , "vcmpneb." },
+ { &test_vcmpnezb , "vcmpnezb" },
+ { &test_dotted_vcmpnezb, "vcmpnezb." },
+ { &test_vcmpneh , "vcmpneh" },
+ { &test_dotted_vcmpneh , "vcmpneh." },
+ { &test_vcmpnezh , "vcmpnezh" },
+ { &test_dotted_vcmpnezh, "vcmpnezh." },
+ { &test_vcmpnew , "vcmpnew" },
+ { &test_dotted_vcmpnew , "vcmpnew." },
+ { &test_vcmpnezw , "vcmpnezw" },
+ { &test_dotted_vcmpnezw, "vcmpnezw." },
+ { &test_vrlwnm , "vrlwnm" },
+ { &test_vrlwmi , "vrlwmi" },
+ { &test_vrldnm , "vrldnm" },
+ { &test_vrldmi , "vrldmi" },
+ { &test_vbpermd , "vbpermd" },
+ { &test_xviexpdp , "xviexpdp" },
+ { &test_xviexpsp , "xviexpsp" },
+ { NULL , NULL },
+};
+
+static void test_vpermr(void)
+{ /* vector permute right-indexed */
+ __asm__ __volatile__ ("vpermr %0, %1, %2, %3 " : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb), "v" (vec_xc));
+}
+
+/* vector, 3->1 unique; four arguments. xt, xa, xb, xc (xc = permute) */
+static test_list_t testgroup_vector_four[] = {
+ { &test_vpermr, "vpermr" },
+ { NULL , NULL },
+};
+
+/* vector insert instructions */
+#define VINSERTB(X) __asm__ __volatile__ ("vinsertb %0, %1, %2" : "+v" (vec_xt) : "v" (vec_xb), "i"(X));
+
+#define VINSERTH(X) __asm__ __volatile__ ("vinserth %0, %1, %2" : "+v" (vec_xt) : "v" (vec_xb), "i"(X));
+
+#define VINSERTW(X) __asm__ __volatile__ ("vinsertw %0, %1, %2" : "+v" (vec_xt) : "v" (vec_xb), "i"(X));
+
+#define VINSERTD(X) __asm__ __volatile__ ("vinsertd %0, %1, %2" : "+v" (vec_xt) : "v" (vec_xb), "i"(X));
+
+#define VEXTRACTUB(X) __asm__ __volatile__ ("vextractub %0, %1, %2" : "+v" (vec_xt) : "v" (vec_xb), "i"(X));
+
+#define VEXTRACTUH(X) __asm__ __volatile__ ("vextractuh %0, %1, %2" : "+v" (vec_xt) : "v" (vec_xb), "i"(X));
+
+#define VEXTRACTUW(X) __asm__ __volatile__ ("vextractuw %0, %1, %2" : "+v" (vec_xt) : "v" (vec_xb), "i"(X));
+
+#define VEXTRACTD(X) __asm__ __volatile__ ("vextractd %0, %1, %2" : "+v" (vec_xt) : "v" (vec_xb), "i"(X));
+
+#define XXINSERTW(X) __asm__ __volatile__ ("xxinsertw %0, %1, %2" : "+wa" (vec_xt) : "wa" (vec_xb), "i"(X));
+
+#define XXEXTRACTUW(X) __asm__ __volatile__ ("xxextractuw %0, %1, %2" : "+wa" (vec_xt) : "wa" (vec_xb), "i"(X));
+
+static void test_vinsertb (void)
+{
+ switch(x_index) {
+ case 0: VINSERTB( 0); break;
+ case 1: VINSERTB( 1); break;
+ case 2: VINSERTB( 2); break;
+ case 3: VINSERTB( 3); break;
+ case 4: VINSERTB( 4); break;
+ case 5: VINSERTB( 5); break;
+ case 6: VINSERTB( 6); break;
+ case 7: VINSERTB( 7); break;
+ case 8: VINSERTB( 8); break;
+ case 9: VINSERTB( 9); break;
+ case 10: VINSERTB(10); break;
+ case 11: VINSERTB(11); break;
+ case 12: VINSERTB(12); break;
+ case 13: VINSERTB(13); break;
+ case 14: VINSERTB(14); break;
+ case 15: VINSERTB(15); break;
+ default:
+ vinsertextract_err;
+ break;
+ }
+}
+
+static void test_vinserth (void)
+{
+ switch(x_index) {
+ case 0: VINSERTH(0); break;
+ case 1: VINSERTH(1); break;
+ case 2: VINSERTH(2); break;
+ case 3: VINSERTH(3); break;
+ case 4: VINSERTH(4); break;
+ case 5: VINSERTH(5); break;
+ case 6: VINSERTH(6); break;
+ case 7: VINSERTH(7); break;
+ case 8: VINSERTH(8); break;
+ case 9: VINSERTH(9); break;
+ case 10: VINSERTH(10); break;
+ case 11: VINSERTH(11); break;
+ case 12: VINSERTH(12); break;
+ case 13: VINSERTH(13); break;
+ case 14: VINSERTH(14); break;
+ default:
+ vinsertextract_err;
+ break;
+ }
+}
+
+static void test_vinsertw (void)
+{
+ switch(x_index) {
+ case 0: VINSERTW(0); break;
+ case 1: VINSERTW(1); break;
+ case 2: VINSERTW(2); break;
+ case 3: VINSERTW(3); break;
+ case 4: VINSERTW(4); break;
+ case 5: VINSERTW(5); break;
+ case 6: VINSERTW(6); break;
+ case 7: VINSERTW(7); break;
+ case 8: VINSERTW(8); break;
+ case 9: VINSERTW(9); break;
+ case 10: VINSERTW(10); break;
+ case 11: VINSERTW(11); break;
+ case 12: VINSERTW(12); break;
+ default:
+ vinsertextract_err;
+ break;
+ }
+}
+
+static void test_vinsertd (void)
+{
+ switch(x_index) {
+ case 0: VINSERTD(0); break;
+ case 1: VINSERTD(1); break;
+ case 2: VINSERTD(2); break;
+ case 3: VINSERTD(3); break;
+ case 4: VINSERTD(4); break;
+ case 5: VINSERTD(5); break;
+ case 6: VINSERTD(6); break;
+ case 7: VINSERTD(7); break;
+ case 8: VINSERTD(8); break;
+ default:
+ vinsertextract_err;
+ break;
+ }
+}
+
+/* extracts */
+static void test_vextractub (void)
+{
+ switch(x_index) {
+ case 0: VEXTRACTUB( 0); break;
+ case 1: VEXTRACTUB( 1); break;
+ case 2: VEXTRACTUB( 2); break;
+ case 3: VEXTRACTUB( 3); break;
+ case 4: VEXTRACTUB( 4); break;
+ case 5: VEXTRACTUB( 5); break;
+ case 6: VEXTRACTUB( 6); break;
+ case 7: VEXTRACTUB( 7); break;
+ case 8: VEXTRACTUB( 8); break;
+ case 9: VEXTRACTUB( 9); break;
+ case 10: VEXTRACTUB(10); break;
+ case 11: VEXTRACTUB(11); break;
+ case 12: VEXTRACTUB(12); break;
+ case 13: VEXTRACTUB(13); break;
+ case 14: VEXTRACTUB(14); break;
+ case 15: VEXTRACTUB(15); break;
+ default:
+ vinsertextract_err;
+ break;
+ }
+}
+
+static void test_vextractuh (void)
+{
+ switch(x_index) {
+ case 0: VEXTRACTUH( 0); break;
+ case 1: VEXTRACTUH( 1); break;
+ case 2: VEXTRACTUH( 2); break;
+ case 3: VEXTRACTUH( 3); break;
+ case 4: VEXTRACTUH( 4); break;
+ case 5: VEXTRACTUH( 5); break;
+ case 6: VEXTRACTUH( 6); break;
+ case 7: VEXTRACTUH( 7); break;
+ case 8: VEXTRACTUH( 8); break;
+ case 9: VEXTRACTUH( 9); break;
+ case 10: VEXTRACTUH(10); break;
+ case 11: VEXTRACTUH(11); break;
+ case 12: VEXTRACTUH(12); break;
+ case 13: VEXTRACTUH(13); break;
+ case 14: VEXTRACTUH(14); break;
+ default:
+ vinsertextract_err;
+ break;
+ }
+}
+
+static void test_vextractuw (void)
+{
+ switch(x_index) {
+ case 0: VEXTRACTUW( 0); break;
+ case 1: VEXTRACTUW( 1); break;
+ case 2: VEXTRACTUW( 2); break;
+ case 3: VEXTRACTUW( 3); break;
+ case 4: VEXTRACTUW( 4); break;
+ case 5: VEXTRACTUW( 5); break;
+ case 6: VEXTRACTUW( 6); break;
+ case 7: VEXTRACTUW( 7); break;
+ case 8: VEXTRACTUW( 8); break;
+ case 9: VEXTRACTUW( 9); break;
+ case 10: VEXTRACTUW(10); break;
+ case 11: VEXTRACTUW(11); break;
+ default:
+ vinsertextract_err;
+ break;
+ }
+}
+
+static void test_vextractd (void)
+{
+ switch(x_index) {
+ case 0: VEXTRACTD( 0); break;
+ case 1: VEXTRACTD( 1); break;
+ case 2: VEXTRACTD( 2); break;
+ case 3: VEXTRACTD( 3); break;
+ case 4: VEXTRACTD( 4); break;
+ case 5: VEXTRACTD( 5); break;
+ case 6: VEXTRACTD( 6); break;
+ case 7: VEXTRACTD( 7); break;
+ case 8: VEXTRACTD( 8); break;
+ default:
+ vinsertextract_err;
+ break;
+ }
+}
+
+static void test_xxinsertw (void)
+{
+ switch(x_index) {
+ case 0: XXINSERTW( 0); break;
+ case 1: XXINSERTW( 1); break;
+ case 2: XXINSERTW( 2); break;
+ case 3: XXINSERTW( 3); break;
+ case 4: XXINSERTW( 4); break;
+ case 5: XXINSERTW( 5); break;
+ case 6: XXINSERTW( 6); break;
+ case 7: XXINSERTW( 7); break;
+ case 8: XXINSERTW( 8); break;
+ case 9: XXINSERTW( 9); break;
+ case 10: XXINSERTW(10); break;
+ case 11: XXINSERTW(11); break;
+ case 12: XXINSERTW(12); break;
+ default:
+ vinsertextract_err;
+ break;
+ }
+}
+
+static void test_xxextractuw (void)
+{
+ switch(x_index) {
+ case 0: XXEXTRACTUW( 0); break;
+ case 1: XXEXTRACTUW( 1); break;
+ case 2: XXEXTRACTUW( 2); break;
+ case 3: XXEXTRACTUW( 3); break;
+ case 4: XXEXTRACTUW( 4); break;
+ case 5: XXEXTRACTUW( 5); break;
+ case 6: XXEXTRACTUW( 6); break;
+ case 7: XXEXTRACTUW( 7); break;
+ case 8: XXEXTRACTUW( 8); break;
+ case 9: XXEXTRACTUW( 9); break;
+ case 10: XXEXTRACTUW(10); break;
+ case 11: XXEXTRACTUW(11); break;
+ case 12: XXEXTRACTUW(12); break;
+ default:
+ vinsertextract_err;
+ break;
+ }
+}
+
+static test_list_t testgroup_vector_inserts[] = {
+ { &test_vinsertb , "vinsertb " },
+ { &test_vinserth , "vinserth " },
+ { &test_vinsertw , "vinsertw " },
+ { &test_vinsertd , "vinsertd " },
+ { &test_vextractub , "vextractub " },
+ { &test_vextractuh , "vextractuh " },
+ { &test_vextractuw , "vextractuw " },
+ { &test_vextractd , "vextractd " },
+ { &test_xxinsertw , "xxinsertw " },
+ { &test_xxextractuw, "xxextractuw" },
+ { NULL , NULL },
+};
+
+static void test_xxspltib(void)
+{ /* vector splat byte */
+ switch(x_splat) {
+ case SPLAT0: __asm__ __volatile__ ("xxspltib %x0, %1 " : "=wa"(vec_xt) : "i"(SPLAT0)); break;
+
+ case SPLAT1: __asm__ __volatile__ ("xxspltib %x0, %1 " : "=wa"(vec_xt) : "i"(SPLAT1)); break;
+
+ case SPLAT2: __asm__ __volatile__ ("xxspltib %x0, %1 " : "=wa"(vec_xt) : "i"(SPLAT2)); break;
+
+ case SPLAT3: __asm__ __volatile__ ("xxspltib %x0, %1 " : "=wa"(vec_xt) : "i"(SPLAT3)); break;
+
+ case SPLAT4: __asm__ __volatile__ ("xxspltib %x0, %1 " : "=wa"(vec_xt) : "i"(SPLAT4)); break;
+
+ default:
+ printf("Unhandled splat value for %s %d\n", __FUNCTION__, x_splat);
+ }
+};
+
+static test_list_t testgroup_vector_immediate[] = {
+ { &test_xxspltib, "xxspltib" },
+ { NULL , NULL },
+};
+
+/* vector reverse bytes ... */
+static void test_xxbrh(void)
+{ /* vector reverse byte halfword*/
+ __asm__ __volatile__ ("xxbrh %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static void test_xxbrw(void)
+{ /* vector reverse byte word*/
+ __asm__ __volatile__ ("xxbrw %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static void test_xxbrd(void)
+{ /* vector reverse byte double*/
+ __asm__ __volatile__ ("xxbrd %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static void test_xxbrq(void)
+{ /* vector reverse byte */
+ __asm__ __volatile__ ("xxbrq %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static void test_xvxexpdp(void) {
+ __asm__ __volatile__ ("xvxexpdp %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static void test_xvxexpsp(void) {
+ __asm__ __volatile__ ("xvxexpsp %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static void test_xvxsigdp(void) {
+ __asm__ __volatile__ ("xvxsigdp %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static void test_xvxsigsp(void) {
+ __asm__ __volatile__ ("xvxsigsp %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static void test_xsxexpdp(void) {
+ __asm__ __volatile__ ("xsxexpdp %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static void test_xsxsigdp(void) {
+ __asm__ __volatile__ ("xsxsigdp %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static test_list_t testgroup_vector_logical_one[] = {
+ { &test_xxbrh , "xxbrh" },
+ { &test_xxbrw , "xxbrw" },
+ { &test_xxbrd , "xxbrd" },
+ { &test_xxbrq , "xxbrq" },
+ { &test_xvxexpdp, "xvxexpdp" },
+ { &test_xvxexpsp, "xvxexpsp" },
+ { &test_xvxsigdp, "xvxsigdp" },
+ { &test_xvxsigsp, "xvxsigsp" },
+ { &test_xsxexpdp, "xsxexpdp" },
+ { &test_xsxsigdp, "xsxsigdp" },
+ { NULL , NULL },
+};
+
+static void test_lxvx(void) {
+ __asm__ __volatile__ ("lxvx %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_lxvwsx(void) {
+ __asm__ __volatile__ ("lxvwsx %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_lxvh8x(void) {
+ __asm__ __volatile__ ("lxvh8x %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_lxvb16x(void) {
+ __asm__ __volatile__ ("lxvb16x %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_stxvx(void) {
+ __asm__ __volatile__ ("stxvx %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_stxvh8x(void) {
+ __asm__ __volatile__ ("stxvh8x %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_stxvb16x(void) {
+ __asm__ __volatile__ ("stxvb16x %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+static test_list_t testgroup_vector_loadstore[] = {
+ { &test_lxvx , "lxvx" },
+ { &test_lxvwsx , "lxvwsx" },
+ { &test_lxvh8x , "lxvh8x" },
+ { &test_lxvb16x , "lxvb16x" },
+ { &test_stxvx , "stxvx" },
+ { &test_stxvh8x , "stxvh8x" },
+ { &test_stxvb16x, "stxvb16x" },
+ { NULL , NULL },
+};
+
+static void test_lxvl(void) {
+ __asm__ __volatile__ ("lxvl %0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_stxvl(void) {
+ __asm__ __volatile__ ("stxvl %0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_lxvll(void) {
+ __asm__ __volatile__ ("lxvll %0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_stxvll(void) {
+ __asm__ __volatile__ ("stxvll %0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_lxsibzx(void) {
+ __asm__ __volatile__ ("lxsibzx %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_lxsihzx(void) {
+ __asm__ __volatile__ ("lxsihzx %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_stxsibx(void) {
+ __asm__ __volatile__ ("stxsibx %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_stxsihx(void) {
+ __asm__ __volatile__ ("stxsihx %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+/* d-form vsx load/store */
+static void test_lxsd_0(void) {
+ __asm__ __volatile__ ("lxsd %0, 0(%1) " : "=v"(vec_xt) : "r"(r14));
+}
+
+static void test_stxsd_0(void) {
+ __asm__ __volatile__ ("stxsd %0, 0(%1)" : "=v"(vec_xt) : "r"(r14));
+}
+
+static void test_lxsd_16(void) {
+ __asm__ __volatile__ ("lxsd %0, 16(%1)" : "=v"(vec_xt) : "r"(r14));
+}
+
+static void test_stxsd_16(void) {
+ __asm__ __volatile__ ("stxsd %0, 16(%1)" : "=v"(vec_xt) : "r"(r14));
+}
+
+static void test_lxssp_0(void) {
+ __asm__ __volatile__ ("lxssp %0, 0(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static void test_stxssp_0(void) {
+ __asm__ __volatile__ ("stxssp %0, 0(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static void test_lxssp_16(void) {
+ __asm__ __volatile__ ("lxssp %0, 16(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static void test_stxssp_16(void) {
+ __asm__ __volatile__ ("stxssp %0, 16(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static void test_lxv_0(void) {
+ __asm__ __volatile__ ("lxv %0, 0(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static void test_stxv_0(void) {
+ __asm__ __volatile__ ("stxv %0, 0(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static void test_lxv_16(void) {
+ __asm__ __volatile__ ("lxv %0, 16(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static void test_stxv_16(void) {
+ __asm__ __volatile__ ("stxv %0, 16(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static test_list_t testgroup_vector_scalar_loadstore_length[] = {
+ { &test_lxvl , "lxvl " },
+ { &test_lxvll , "lxvll " },
+ { &test_lxsibzx , "lxsibzx " },
+ { &test_lxsihzx , "lxsihzx " },
+ { &test_stxvl , "stxvl " },
+ { &test_stxvll , "stxvll " },
+ { &test_stxsibx , "stxsibx " },
+ { &test_stxsihx , "stxsihx " },
+ { &test_lxsd_0 , "lxsd 0 " },
+ { &test_stxsd_0 , "stxsd 0 " },
+ { &test_lxsd_16 , "lxsd 16 " },
+ { &test_stxsd_16 , "stxsd 16 " },
+ { &test_lxssp_0 , "lxssp 0 " },
+ { &test_stxssp_0 , "stxssp 0 " },
+ { &test_lxssp_16 , "lxssp 16 " },
+ { &test_stxssp_16, "stxssp 16" },
+ { &test_lxv_0 , "lxv 0 " },
+ { &test_stxv_0 , "stxv 0 " },
+ { &test_lxv_16 , "lxv 16 " },
+ { &test_stxv_16 , "stxv 16 " },
+ { NULL , NULL },
+};
+
+/* move from/to VSR */
+static void test_mfvsrld (void)
+{
+ __asm__ __volatile__ ("mfvsrld %0, %x1" : "=r" (r14) : "wa" (vec_xt));
+};
+
+static void test_mtvsrdd (void)
+{
+ __asm__ __volatile__ ("mtvsrdd %x0, 14, 15" : "=wa" (vec_xt));
+};
+
+static void test_mtvsrws (void)
+{ /* To fit in better with the caller for the mfvsrdd test, use r15
+ * instead of r14 as input here.
+ */
+ __asm__ __volatile__ ("mtvsrws %0, 15" : "=wa" (vec_xt));
+};
+
+static test_list_t testgroup_vectorscalar_move_tofrom[] = {
+ { &test_mfvsrld, "mfvsrld" }, /* RA, XS */
+ { &test_mtvsrdd, "mtvsrdd" }, /* XT, RA, RB */
+ { &test_mtvsrws, "mtvsrws" }, /* XT, RA */
+ { NULL , NULL },
+};
+
+/* vector count {leading, trailing} zero least-significant bits byte.
+ * roughly... how many leading/trailing bytes are even. */
+static void test_vclzlsbb(void) {
+ __asm__ __volatile__ ("vclzlsbb %0, %1" : "=r"(r14) : "v"(vec_xb));
+}
+
+static void test_vctzlsbb(void) {
+ __asm__ __volatile__ ("vctzlsbb %0, %1" : "=r"(r14) : "v"(vec_xb));
+}
+
+static test_list_t testgroup_vector_count_bytes[] = {
+ { &test_vclzlsbb, "vclzlsbb" },
+ { &test_vctzlsbb, "vctzlsbb" },
+ { NULL , NULL },
+};
+
+static void test_vextsb2w(void) {
+ __asm__ __volatile__ ("vextsb2w %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vextsb2d(void) {
+ __asm__ __volatile__ ("vextsb2d %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vextsh2w(void) {
+ __asm__ __volatile__ ("vextsh2w %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vextsh2d(void) {
+ __asm__ __volatile__ ("vextsh2d %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vextsw2d(void) {
+ __asm__ __volatile__ ("vextsw2d %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vnegw(void) {
+ __asm__ __volatile__ ("vnegw %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vnegd(void) {
+ __asm__ __volatile__ ("vnegd %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vprtybw(void) {
+ __asm__ __volatile__ ("vprtybw %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vprtybd(void) {
+ __asm__ __volatile__ ("vprtybd %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vprtybq(void) {
+ __asm__ __volatile__ ("vprtybq %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vctzb(void) {
+ __asm__ __volatile__ ("vctzb %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vctzh(void) {
+ __asm__ __volatile__ ("vctzh %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vctzw(void) {
+ __asm__ __volatile__ ("vctzw %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vctzd(void) {
+ __asm__ __volatile__ ("vctzd %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static test_list_t testgroup_vector_extend_sign[] = {
+ { &test_vextsb2w, "vextsb2w" },
+ { &test_vextsb2d, "vextsb2d" },
+ { &test_vextsh2w, "vextsh2w" },
+ { &test_vextsh2d, "vextsh2d" },
+ { &test_vextsw2d, "vextsw2d" },
+ { &test_vnegw , "vnegw " },
+ { &test_vnegd , "vnegd " },
+ { &test_vprtybw , "vprtybw " },
+ { &test_vprtybd , "vprtybd " },
+ { &test_vprtybq , "vprtybq " },
+ { &test_vctzb , "vctzb " },
+ { &test_vctzh , "vctzh " },
+ { &test_vctzw , "vctzw " },
+ { &test_vctzd , "vctzd " },
+ { NULL , NULL },
+};
+
+static void test_vextublx(void) {
+ __asm__ __volatile__ ("vextublx %0, %1, %2" : "=r"(r14) : "r" (r15), "v" (vec_xb));
+}
+
+static void test_vextubrx(void) {
+ __asm__ __volatile__ ("vextubrx %0, %1, %2" : "=r"(r14) : "r"(r15), "v"(vec_xb));
+}
+
+static void test_vextuhlx(void) {
+ if (r15 > 14) return; // limit to 14 halfwords
+ __asm__ __volatile__ ("vextuhlx %0, %1, %2" : "=r"(r14) : "r"(r15), "v"(vec_xb));
+}
+
+static void test_vextuhrx(void) {
+ if (r15 > 14) return; // limit to 14 halfwords
+ __asm__ __volatile__ ("vextuhrx %0, %1, %2" : "=r"(r14) : "r"(r15), "v"(vec_xb));
+}
+
+static void test_vextuwlx(void) {
+ if (r15 > 12) return; // limit to 12 words
+ __asm__ __volatile__ ("vextuwlx %0, %1, %2" : "=r"(r14) : "r"(r15), "v"(vec_xb));
+}
+
+static void test_vextuwrx(void) {
+ if (r15 > 12) return; // limit to 12 words
+ __asm__ __volatile__ ("vextuwrx %0, %1, %2" : "=r"(r14) : "r"(r15), "v"(vec_xb));
+}
+
+static test_list_t testgroup_vector_extract[] = {
+ { &test_vextublx, "vextublx" },
+ { &test_vextubrx, "vextubrx" },
+ { &test_vextuhlx, "vextuhlx" },
+ { &test_vextuhrx, "vextuhrx" },
+ { &test_vextuwlx, "vextuwlx" },
+ { &test_vextuwrx, "vextuwrx" },
+ { NULL , NULL },
+};
+
+#define XSCMPEXPDP(x) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xscmpexpdp %0, %1, %2"::"i"(x), "v"(vec_xa), "v"(vec_xb));\
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+static void test_xscmpexpdp(void) {
+ switch(x_index) {
+ case 0: XSCMPEXPDP(0); break;
+ case 1: XSCMPEXPDP(1); break;
+ case 2: XSCMPEXPDP(2); break;
+ case 3: XSCMPEXPDP(3); break;
+ case 4: XSCMPEXPDP(4); break;
+ case 5: XSCMPEXPDP(5); break;
+ case 6: XSCMPEXPDP(6); break;
+ case 7: XSCMPEXPDP(7); break;
+ default:
+ printf("Unhandled shift value for %s %x\n", __FUNCTION__, x_index);
+ };
+}
+
+static test_list_t testgroup_vector_scalar_compare_exp_double[] = {
+ { &test_xscmpexpdp , "xscmpexpdp " },
+ { NULL , NULL },
+};
+
+#define XSTSTDCQP(R,DCMX) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xststdcqp %0, %1, %2":: "i"(R), "wa"(vec_xb), "i"(DCMX)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+#define XSTSTDCDP(R,DCMX) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xststdcdp %0, %1, %2":: "i"(R), "wa"(vec_xb), "i"(DCMX)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+#define XSTSTDCSP(R,DCMX) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xststdcsp %0, %1, %2":: "i"(R), "wa"(vec_xb), "i"(DCMX)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+#define XVTSTDCDP(R,DCMX) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xvtstdcdp %0, %1, %2": "=wa"(vec_xt) : "wa"(vec_xb), "i"(DCMX)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+#define XVTSTDCSP(R,DCMX) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xvtstdcsp %0, %1, %2": "=wa"(vec_xt) : "wa"(vec_xb), "i"(DCMX)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+static void test_xststdcqp(void) {
+ switch(x_index) {
+ case 1: XSTSTDCQP(3, 0x01); break; /* NaN */
+ case 2: XSTSTDCQP(3, 0x02); break; /* +inf */
+ case 3: XSTSTDCQP(3, 0x04); break; /* -inf */
+ case 4: XSTSTDCQP(3, 0x08); break; /* +zero */
+ case 5: XSTSTDCQP(3, 0x10); break; /* -zero */
+ case 6: XSTSTDCQP(3, 0x20); break; /* +denormal */
+ case 7: XSTSTDCQP(3, 0x40); break; /* -denormal */
+ case 0: XSTSTDCQP(3, 0x7f); break; /* all of the above */
+ }
+}
+
+static void test_xststdcdp(void) {
+ switch(x_index) {
+ case 1: XSTSTDCDP(3, 0x01); break; /* NaN */
+ case 2: XSTSTDCDP(3, 0x02); break; /* +inf */
+ case 3: XSTSTDCDP(3, 0x04); break; /* -inf */
+ case 4: XSTSTDCDP(3, 0x08); break; /* +zero */
+ case 5: XSTSTDCDP(3, 0x10); break; /* -zero */
+ case 6: XSTSTDCDP(3, 0x20); break; /* +denormal */
+ case 7: XSTSTDCDP(3, 0x40); break; /* -denormal */
+ case 0: XSTSTDCDP(3, 0x7f); break; /* all of the above */
+ }
+}
+
+static void test_xststdcsp(void) {
+ switch(x_index) {
+ case 1: XSTSTDCSP(3, 0x01); break; /* NaN */
+ case 2: XSTSTDCSP(3, 0x02); break; /* +inf */
+ case 3: XSTSTDCSP(3, 0x04); break; /* -inf */
+ case 4: XSTSTDCSP(3, 0x08); break; /* +zero */
+ case 5: XSTSTDCSP(3, 0x10); break; /* -zero */
+ case 6: XSTSTDCSP(3, 0x20); break; /* +denormal */
+ case 7: XSTSTDCSP(3, 0x40); break; /* -denormal */
+ case 0: XSTSTDCSP(3, 0x7f); break; /* all of the above */
+ }
+}
+
+static void test_xvtstdcdp(void) {
+ switch(x_index) {
+ case 1: XVTSTDCDP(3, 0x01); break; /* NaN */
+ case 2: XVTSTDCDP(3, 0x02); break; /* +inf */
+ case 3: XVTSTDCDP(3, 0x04); break; /* -inf */
+ case 4: XVTSTDCDP(3, 0x08); break; /* +zero */
+ case 5: XVTSTDCDP(3, 0x10); break; /* -zero */
+ case 6: XVTSTDCDP(3, 0x20); break; /* +denormal */
+ case 7: XVTSTDCDP(3, 0x40); break; /* -denormal */
+ case 0: XVTSTDCDP(3, 0x7f); break; /* all of the above */
+ }
+}
+
+/* Note: Due to the test groupings, the input for the xvtstdcsp test is
+ * actually 'double'. It is good enough for this test, but may wish to break
+ * this one out eventually.
+ */
+static void test_xvtstdcsp(void) {
+ switch(x_index) {
+ case 1: XVTSTDCSP(3, 0x01); break; /* NaN */
+ case 2: XVTSTDCSP(3, 0x02); break; /* +inf */
+ case 3: XVTSTDCSP(3, 0x04); break; /* -inf */
+ case 4: XVTSTDCSP(3, 0x08); break; /* +zero */
+ case 5: XVTSTDCSP(3, 0x10); break; /* -zero */
+ case 6: XVTSTDCSP(3, 0x20); break; /* +denormal */
+ case 7: XVTSTDCSP(3, 0x40); break; /* -denormal */
+ case 0: XVTSTDCSP(3, 0x7f); break; /* all of the above */
+ }
+}
+
+static test_list_t testgroup_vector_scalar_data_class[] = {
+ { &test_xststdcqp, "xststdcqp " },
+ { &test_xststdcdp, "xststdcdp " },
+ { &test_xststdcsp, "xststdcsp " },
+ { &test_xvtstdcsp, "xvtstdcsp " },
+ { &test_xvtstdcdp, "xvtstdcdp " },
+ { NULL , NULL },
+};
+
+static void test_setb (void) {
+ /* setb RT,BFA
+ * BFA is a 3-bit field. */
+
+ switch(x_index) {
+ case 0:SET_CR0_FIELD(cr_value);
+ __asm__ __volatile__ ("setb %0, 0" : "=r" (r14)); break;
+
+ case 1:SET_CR1_FIELD(cr_value);
+ __asm__ __volatile__ ("setb %0, 1" : "=r" (r14)); break;
+
+ case 2:SET_CR2_FIELD(cr_value);
+ __asm__ __volatile__ ("setb %0, 2" : "=r" (r14)); break;
+
+ case 3:SET_CR3_FIELD(cr_value);
+ __asm__ __volatile__ ("setb %0, 3" : "=r" (r14)); break;
+
+ case 4:SET_CR4_FIELD(cr_value);
+ __asm__ __volatile__ ("setb %0, 4" : "=r" (r14)); break;
+
+ case 5:SET_CR5_FIELD(cr_value);
+ __asm__ __volatile__ ("setb %0, 5" : "=r" (r14)); break;
+
+ case 6:SET_CR6_FIELD(cr_value);
+ __asm__ __volatile__ ("setb %0, 6" : "=r" (r14)); break;
+
+ case 7:SET_CR7_FIELD(cr_value);
+ __asm__ __volatile__ ("setb %0, 7" : "=r" (r14)); break;
+ }
+
+ GET_CR(local_cr);
+
+ if (verbose) {
+ dissect_cr(local_cr);
+ }
+}
+
+static test_list_t testgroup_set_boolean[] = {
+ { &test_setb, "setb"},
+ { NULL , NULL },
+};
+
+/* cmprb l = 0:
+ * compares r14 = src with range specified by values in r15
+ * bits (48:55 - 56:63)].
+ *
+ * cmprb l=1:
+ * compares r14 = src with ranges between two pairs of values, as above and
+ * also in r15 bits (32:39 - 40:47 .
+ */
+static void test_cmprb_l0() {
+ switch(x_index) {
+ case 0: __asm__ __volatile__ ("cmprb 0, 0, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 1: __asm__ __volatile__ ("cmprb 1, 0, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 2: __asm__ __volatile__ ("cmprb 2, 0, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 3: __asm__ __volatile__ ("cmprb 3, 0, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 4: __asm__ __volatile__ ("cmprb 4, 0, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 5: __asm__ __volatile__ ("cmprb 5, 0, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 6: __asm__ __volatile__ ("cmprb 6, 0, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 7: __asm__ __volatile__ ("cmprb 7, 0, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+ }
+}
+
+static void test_cmprb_l1() {
+ switch(x_index) {
+ case 0: __asm__ __volatile__ ("cmprb 0, 1 ,%0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 1: __asm__ __volatile__ ("cmprb 1, 1, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 2: __asm__ __volatile__ ("cmprb 2, 1, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 3: __asm__ __volatile__ ("cmprb 3, 1, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 4: __asm__ __volatile__ ("cmprb 4, 1, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 5: __asm__ __volatile__ ("cmprb 5, 1, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 6: __asm__ __volatile__ ("cmprb 6, 1, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 7: __asm__ __volatile__ ("cmprb 7, 1, %0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+ }
+}
+
+static void test_cmpeqb() {
+ switch(x_index) {
+ case 0: __asm__ __volatile__ ("cmpeqb 0,%0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 1: __asm__ __volatile__ ("cmpeqb 1,%0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 2: __asm__ __volatile__ ("cmpeqb 2,%0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 3: __asm__ __volatile__ ("cmpeqb 3,%0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 4: __asm__ __volatile__ ("cmpeqb 4,%0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 5: __asm__ __volatile__ ("cmpeqb 5,%0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 6: __asm__ __volatile__ ("cmpeqb 6,%0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+
+ case 7: __asm__ __volatile__ ("cmpeqb 7,%0, %1" : : "r"(r14), "r"(r15));
+ GET_CR(local_cr); break;
+ }
+}
+
+static test_list_t testgroup_char_compare[] = {
+ { &test_cmprb_l0, "cmprb l=0" },
+ { &test_cmprb_l1, "cmprb l=1" },
+ { &test_cmpeqb , "cmpeqb" },
+ { NULL , NULL },
+};
+
+static void test_bcdtrunc_p0(void) {
+ __asm__ __volatile__ ("bcdtrunc. %0, %1, %2, 0": "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_bcdtrunc_p1(void) {
+ __asm__ __volatile__ ("bcdtrunc. %0, %1, %2, 1": "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_bcdutrunc(void) {
+ __asm__ __volatile__ ("bcdutrunc. %0, %1, %2 ": "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_bcdadd_p0(void) {
+ __asm__ __volatile__ ("bcdadd. %0, %1, %2, 0" : "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_bcdadd_p1(void) {
+ __asm__ __volatile__ ("bcdadd. %0, %1, %2, 1" : "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_bcdsub_p0(void) {
+ __asm__ __volatile__ ("bcdsub. %0, %1, %2, 0" : "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_bcdsub_p1(void) {
+ __asm__ __volatile__ ("bcdsub. %0, %1, %2, 1" : "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_bcdcpsgn(void) {
+ __asm__ __volatile__ ("bcdcpsgn. %0, %1, %2 ": "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_bcdctz_p0(void) {
+ __asm__ __volatile__ ("bcdctz. %0, %1, 0 " : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_bcdctz_p1(void) {
+ __asm__ __volatile__ ("bcdctz. %0, %1, 1 " : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_bcdsetsgn_p0(void) {
+ __asm__ __volatile__ ("bcdsetsgn. %0, %1, 0 " : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_bcdsetsgn_p1(void) {
+ __asm__ __volatile__ ("bcdsetsgn. %0, %1, 1 " : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_bcds_p0(void) {
+ __asm__ __volatile__ ("bcds. %0, %1, %2, 0" : "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_bcds_p1(void) {
+ __asm__ __volatile__ ("bcds. %0, %1, %2, 1" : "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_bcdus(void) {
+ __asm__ __volatile__ ("bcdus. %0, %1, %2 " : "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_bcdsr_p0(void) {
+ __asm__ __volatile__ ("bcdsr. %0, %1, %2, 0" : "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_bcdsr_p1(void) {
+ __asm__ __volatile__ ("bcdsr. %0, %1, %2, 1" : "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_bcdcfn_p0(void) {
+ __asm__ __volatile__ ("bcdcfn. %0, %1, 0 " : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_bcdcfn_p1(void) {
+ __asm__ __volatile__ ("bcdcfn. %0, %1, 1 " : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_bcdcfz_p0(void) {
+ __asm__ __volatile__ ("bcdcfz. %0, %1, 0 " : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_bcdcfz_p1(void) {
+ __asm__ __volatile__ ("bcdcfz. %0, %1, 1 " : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_bcdctn(void) {
+ __asm__ __volatile__ ("bcdctn. %0, %1 " : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vmul10uq(void) {
+ __asm__ __volatile__ ("vmul10uq %0, %1 " : "=v"(vec_xt) : "v"(vec_xa));
+}
+
+static void test_vmul10cuq(void) {
+ __asm__ __volatile__ ("vmul10cuq %0, %1 " : "=v"(vec_xt) : "v"(vec_xa));
+}
+
+static void test_vmul10euq(void) {
+ __asm__ __volatile__ ("vmul10euq %0, %1, %2 " : "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_vmul10ecuq(void) {
+ __asm__ __volatile__ ("vmul10ecuq %0, %1, %2 " : "=v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_bcdctsq(void) {
+ __asm__ __volatile__ ("bcdctsq. %0, %1 " : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_bcdcfsq_p0(void) {
+ __asm__ __volatile__ ("bcdcfsq. %0, %1, 0 " : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_bcdcfsq_p1(void) {
+ __asm__ __volatile__ ("bcdcfsq. %0, %1, 1 " : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static test_list_t testgroup_bcd_misc[] = {
+ { &test_bcdadd_p0 , "bcdadd. p0" },
+ { &test_bcdadd_p1 , "bcdadd. p1" },
+ { &test_bcdsub_p0 , "bcdsub. p0" },
+ { &test_bcdsub_p1 , "bcdsub. p1" },
+ { &test_bcdcfn_p0 , "bcdcfn. p0" },
+ { &test_bcdcfn_p1 , "bcdcfn. p1" },
+ { &test_bcdcfz_p0 , "bcdcfz. p0" }, /* The p0, p1 substrings are used later */
+ { &test_bcdcfz_p1 , "bcdcfz. p1" }, /* " " */
+ { &test_bcdctn , "bcdctn. " },
+ { &test_bcdctz_p0 , "bcdctz. p0" }, /* note: p0, p1 substrings are used later */
+ { &test_bcdctz_p1 , "bcdctz. p1" }, /* " " */
+ { &test_bcdcpsgn , "bcdcpsgn." },
+ { &test_bcdsetsgn_p0, "bcdsetsgn. p0" },
+ { &test_bcdsetsgn_p1, "bcdsetsgn. p1" },
+ { &test_bcds_p0 , "bcds. p0" },
+ { &test_bcds_p1 , "bcds. p1" },
+ { &test_bcdus , "bcdus. " },
+ { &test_bcdsr_p0 , "bcdsr. p0" },
+ { &test_bcdsr_p1 , "bcdsr. p1" },
+ { &test_bcdtrunc_p0 , "bcdtrunc. p0" },
+ { &test_bcdtrunc_p1 , "bcdtrunc. p1" },
+ { &test_bcdutrunc , "bcdutrunc. " },
+ { &test_vmul10uq , "vmul10uq " },
+ { &test_vmul10cuq , "vmul10cuq " },
+ { &test_vmul10euq , "vmul10euq " },
+ { &test_vmul10ecuq , "vmul10ecuq " },
+ { &test_bcdctsq , "bcdctsq." },
+ { &test_bcdcfsq_p0 , "bcdcfsq. p0" },
+ { &test_bcdcfsq_p1 , "bcdcfsq. p1" },
+ { NULL , NULL },
+};
+
+static void test_wait(void) {
+ __asm__ __volatile__ ("wait 0" : :);
+}
+
+static test_list_t testgroup_noop_misc[] = {
+ { &test_wait, "wait ",},
+ { NULL , NULL, },
+};
+
+/* The significance field can be any values within bits 10-15 of the
+ * instruction. For this test, limiting the values to one per bit location.
+ */
+static void test_dtstsfi() {
+ _Decimal128 df14 = dfp_value.dec_val128;
+ switch(dfp_significance) {
+ case 0x00: __asm__ __volatile__ ("dtstsfi 3, 0x00, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x01: __asm__ __volatile__ ("dtstsfi 3, 0x01, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x02: __asm__ __volatile__ ("dtstsfi 3, 0x02, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x03: __asm__ __volatile__ ("dtstsfi 3, 0x03, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x04: __asm__ __volatile__ ("dtstsfi 3, 0x04, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x06: __asm__ __volatile__ ("dtstsfi 3, 0x06, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x08: __asm__ __volatile__ ("dtstsfi 3, 0x08, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x0c: __asm__ __volatile__ ("dtstsfi 3, 0x0c, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x10: __asm__ __volatile__ ("dtstsfi 3, 0x10, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x18: __asm__ __volatile__ ("dtstsfi 3, 0x18, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x20: __asm__ __volatile__ ("dtstsfi 3, 0x20, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+ }
+}
+
+static void test_dtstsfiq() {
+ _Decimal128 df14 = dfp_value.dec_val128;
+ switch(dfp_significance) {
+ case 0x00: __asm__ __volatile__ ("dtstsfiq 3, 0x00, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x01: __asm__ __volatile__ ("dtstsfiq 3, 0x01, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x02: __asm__ __volatile__ ("dtstsfiq 3, 0x02, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x03: __asm__ __volatile__ ("dtstsfiq 3, 0x03, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x04: __asm__ __volatile__ ("dtstsfiq 3, 0x04, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x06: __asm__ __volatile__ ("dtstsfiq 3, 0x06, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x08: __asm__ __volatile__ ("dtstsfiq 3, 0x08, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x0c: __asm__ __volatile__ ("dtstsfiq 3, 0x0c, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x10: __asm__ __volatile__ ("dtstsfiq 3, 0x10, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x18: __asm__ __volatile__ ("dtstsfiq 3, 0x18, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+
+ case 0x20: __asm__ __volatile__ ("dtstsfiq 3, 0x20, %0" : : "f" (df14));
+ GET_CR(local_cr); break;
+ }
+}
+
+static test_list_t testgroup_dfp_significance[] = {
+ { &test_dtstsfi , "dtstsfi" },
+ { &test_dtstsfiq, "dtstsfiq" },
+ { NULL , NULL },
+};
+
+static void test_addpcis(void) {
+ switch (x_index) {
+ case 0x0: __asm__ __volatile__ ("addpcis 14, %0" : : "i"(0x0) ); break;
+ case 0x1: __asm__ __volatile__ ("addpcis 14, %0" : : "i"(0x1) ); break;
+ case 0x2: __asm__ __volatile__ ("addpcis 14, %0" : : "i"(0x2) ); break;
+ case 0x3: __asm__ __volatile__ ("addpcis 14, %0" : : "i"(0x40) ); break;
+ case 0x4: __asm__ __volatile__ ("addpcis 14, %0" : : "i"(0x800) ); break;
+ case 0x5: __asm__ __volatile__ ("addpcis 14, %0" : : "i"(0x2000) ); break;
+ case 0x6: __asm__ __volatile__ ("addpcis 14, %0" : : "i"(0x7fff) ); break;
+ case 0x7: __asm__ __volatile__ ("addpcis 14, %0" : : "i"(0x8000) ); break;
+ case 0x8: __asm__ __volatile__ ("addpcis 14, -%0" : : "i"(0x0) ); break;
+ case 0x9: __asm__ __volatile__ ("addpcis 14, -%0" : : "i"(0x1) ); break;
+ case 0xa: __asm__ __volatile__ ("addpcis 14, -%0" : : "i"(0x2) ); break;
+ case 0xb: __asm__ __volatile__ ("addpcis 14, -%0" : : "i"(0x40) ); break;
+ case 0xc: __asm__ __volatile__ ("addpcis 14, -%0" : : "i"(0x800) ); break;
+ case 0xd: __asm__ __volatile__ ("addpcis 14, -%0" : : "i"(0x2000) ); break;
+ case 0xe: __asm__ __volatile__ ("addpcis 14, -%0" : : "i"(0x7fff) ); break;
+ case 0xf: __asm__ __volatile__ ("addpcis 14, -%0" : : "i"(0x8000) ); break;
+ }
+}
+
+static void test_subpcis(void) {
+ switch (x_index) {
+ case 0x0: __asm__ __volatile__ ("subpcis 14, %0" : : "i"(0x0) ); break;
+ case 0x1: __asm__ __volatile__ ("subpcis 14, %0" : : "i"(0x1) ); break;
+ case 0x2: __asm__ __volatile__ ("subpcis 14, %0" : : "i"(0x2) ); break;
+ case 0x3: __asm__ __volatile__ ("subpcis 14, %0" : : "i"(0x40) ); break;
+ case 0x4: __asm__ __volatile__ ("subpcis 14, %0" : : "i"(0x800) ); break;
+ case 0x5: __asm__ __volatile__ ("subpcis 14, %0" : : "i"(0x2000) ); break;
+ case 0x6: __asm__ __volatile__ ("subpcis 14, %0" : : "i"(0x7fff) ); break;
+ case 0x7: __asm__ __volatile__ ("subpcis 14, %0" : : "i"(0x8000) ); break;
+ case 0x8: __asm__ __volatile__ ("subpcis 14, -%0" : : "i"(0x0) ); break;
+ case 0x9: __asm__ __volatile__ ("subpcis 14, -%0" : : "i"(0x1) ); break;
+ case 0xa: __asm__ __volatile__ ("subpcis 14, -%0" : : "i"(0x2) ); break;
+ case 0xb: __asm__ __volatile__ ("subpcis 14, -%0" : : "i"(0x40) ); break;
+ case 0xc: __asm__ __volatile__ ("subpcis 14, -%0" : : "i"(0x80) ); break;
+ case 0xd: __asm__ __volatile__ ("subpcis 14, -%0" : : "i"(0x200) ); break;
+ case 0xe: __asm__ __volatile__ ("subpcis 14, -%0" : : "i"(0x7fff) ); break;
+ case 0xf: __asm__ __volatile__ ("subpcis 14, -%0" : : "i"(0x8000) ); break;
+ }
+}
+
+static test_list_t testgroup_pc_immediate_misc[] = {
+ { &test_addpcis, "addpcis " },
+ { &test_subpcis, "subpcis " },
+ { NULL , NULL },
+};
+
+static void test_xsiexpdp(void) {
+ __asm__ __volatile__ ("xsiexpdp %0, %1, %2 " : "+wa" (vec_xt): "r" (r14), "r" (r15));
+}
+
+static void test_xscvhpdp(void) {
+ __asm__ __volatile__ ("xscvhpdp %x0, %x1 " : "+wa" (vec_xt) : "wa" (vec_xb));
+}
+
+static void test_xscvdphp(void) {
+ __asm__ __volatile__ ("xscvdphp %x0, %x1 " : "+wi" (vec_xt) : "wi" (vec_xb));
+}
+
+static void test_xvcvhpsp(void) {
+ __asm__ __volatile__ ("xvcvhpsp %x0, %x1 " : "+ww" (vec_xt) : "ww" (vec_xb));
+}
+
+static void test_xvcvsphp(void) {
+ __asm__ __volatile__ ("xvcvsphp %x0, %x1 " : "+ww" (vec_xt) : "ww" (vec_xb));
+}
+
+static test_list_t testgroup_vector_scalar_two_double[] = {
+ { &test_xsiexpdp, "xsiexpdp" },
+ { &test_xscvhpdp, "xscvhpdp" },
+ { &test_xscvdphp, "xscvdphp" },
+ { &test_xvcvhpsp, "xvcvhpsp" },
+ { &test_xvcvsphp, "xvcvsphp" },
+ { NULL , NULL },
+};
+
+
+static void test_xsabsqp(void) {
+ __asm__ __volatile__ ("xsabsqp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xscvdpqp(void) {
+ __asm__ __volatile__ ("xscvdpqp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xscvqpdp(void) {
+ __asm__ __volatile__ ("xscvqpdp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xscvqpdpo(void) {
+ __asm__ __volatile__ ("xscvqpdpo %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xscvqpsdz(void) {
+ __asm__ __volatile__ ("xscvqpsdz %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xscvqpswz(void) {
+ __asm__ __volatile__ ("xscvqpswz %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xscvqpudz(void) {
+ __asm__ __volatile__ ("xscvqpudz %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xscvqpuwz(void) {
+ __asm__ __volatile__ ("xscvqpuwz %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xscvsdqp(void) {
+ __asm__ __volatile__ ("xscvsdqp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xscvudqp(void) {
+ __asm__ __volatile__ ("xscvudqp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xsxexpqp(void) {
+ __asm__ __volatile__ ("xsxexpqp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xsxsigqp(void) {
+ __asm__ __volatile__ ("xsxsigqp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xsnegqp(void) {
+ __asm__ __volatile__ ("xsnegqp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xsnabsqp(void) {
+ __asm__ __volatile__ ("xsnabsqp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xssqrtqp(void) {
+ __asm__ __volatile__ ("xssqrtqp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xssqrtqpo(void) {
+ __asm__ __volatile__ ("xssqrtqpo %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static test_list_t testgroup_vector_scalar_two_quad[] = {
+ { &test_xsabsqp , "xsabsqp " },
+ { &test_xscvdpqp , "xscvdpqp " },
+ { &test_xscvqpdp , "xscvqpdp " },
+ { &test_xscvqpdpo, "xscvqpdpo " },
+ { &test_xscvqpsdz, "xscvqpsdz " },
+ { &test_xscvqpswz, "xscvqpswz " },
+ { &test_xscvqpudz, "xscvqpudz " },
+ { &test_xscvqpuwz, "xscvqpuwz " },
+ { &test_xscvsdqp , "xscvsdqp " },
+ { &test_xscvudqp , "xscvudqp " },
+ { &test_xsxexpqp , "xsxexpqp " },
+ { &test_xsxsigqp , "xsxsigqp " },
+ { &test_xsnegqp , "xsnegqp " },
+ { &test_xsnabsqp , "xsnabsqp " },
+ { &test_xssqrtqp , "xssqrtqp " },
+ { &test_xssqrtqpo, "xssqrtqpo " },
+ { NULL , NULL },
+};
+
+static void test_xsaddqp(void) {
+ __asm__ __volatile__ ("xsaddqp %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsaddqpo(void) {
+ __asm__ __volatile__ ("xsaddqpo %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xscpsgnqp(void) {
+ __asm__ __volatile__ ("xscpsgnqp %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsdivqp(void) {
+ __asm__ __volatile__ ("xsdivqp %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsdivqpo(void) {
+ __asm__ __volatile__ ("xsdivqpo %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsiexpqp(void) {
+ __asm__ __volatile__ ("xsiexpqp %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsmaddqp(void) {
+ __asm__ __volatile__ ("xsmaddqp %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsmaddqpo(void) {
+ __asm__ __volatile__ ("xsmaddqpo %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsmsubqp(void) {
+ __asm__ __volatile__ ("xsmsubqp %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsmsubqpo(void) {
+ __asm__ __volatile__ ("xsmsubqpo %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsmulqp(void) {
+ __asm__ __volatile__ ("xsmulqp %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsmulqpo(void) {
+ __asm__ __volatile__ ("xsmulqpo %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsnmaddqp(void) {
+ __asm__ __volatile__ ("xsnmaddqp %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsnmaddqpo(void) {
+ __asm__ __volatile__ ("xsnmaddqpo %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsnmsubqp(void) {
+ __asm__ __volatile__ ("xsnmsubqp %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsnmsubqpo(void) {
+ __asm__ __volatile__ ("xsnmsubqpo %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xssubqp(void) {
+ __asm__ __volatile__ ("xssubqp %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xssubqpo(void) {
+ __asm__ __volatile__ ("xssubqpo %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static test_list_t testgroup_vector_three_quad[] = {
+ { &test_xsaddqp , "xsaddqp " },
+ { &test_xsaddqpo , "xsaddqpo " },
+ { &test_xscpsgnqp , "xscpsgnqp " },
+ { &test_xsdivqp , "xsdivqp " },
+ { &test_xsdivqpo , "xsdivqpo " },
+ { &test_xsiexpqp , "xsiexpqp " },
+ { &test_xsmaddqp , "xsmaddqp " },
+ { &test_xsmaddqpo , "xsmaddqpo " },
+ { &test_xsmsubqp , "xsmsubqp " },
+ { &test_xsmsubqpo , "xsmsubqpo " },
+ { &test_xsmulqp , "xsmulqp " },
+ { &test_xsmulqpo , "xsmulqpo " },
+ { &test_xsnmaddqp , "xsnmaddqp " },
+ { &test_xsnmaddqpo, "xsnmaddqpo " },
+ { &test_xsnmsubqp , "xsnmsubqp " },
+ { &test_xsnmsubqpo, "xsnmsubqpo " },
+ { &test_xssubqp , "xssubqp " },
+ { &test_xssubqpo , "xssubqpo " },
+ { NULL , NULL },
+};
+
+#define XSCMPEXPQP(x) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xscmpexpqp %0, %1, %2" :: "i"(x), "v"(vec_xa), "v"(vec_xb)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+#define XSCMPOQP(x) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xscmpoqp %0, %1, %2" :: "i"(x), "v"(vec_xa), "v"(vec_xb)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+#define XSCMPUQP(x) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xscmpuqp %0, %1, %2"::"i"(x), "v"(vec_xa), "v"(vec_xb)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+static void test_xscmpexpqp(void) {
+ switch(x_index) {
+ case 0: XSCMPEXPQP(0); break;
+ case 1: XSCMPEXPQP(1); break;
+ case 2: XSCMPEXPQP(2); break;
+ case 3: XSCMPEXPQP(3); break;
+ case 4: XSCMPEXPQP(4); break;
+ case 5: XSCMPEXPQP(5); break;
+ case 6: XSCMPEXPQP(6); break;
+ case 7: XSCMPEXPQP(7); break;
+ default:
+ printf("Unhandled shift value for %s %x\n", __FUNCTION__, x_index);
+ };
+}
+
+static void test_xscmpoqp(void) {
+ switch(x_index) {
+ case 0: XSCMPOQP(0); break;
+ case 1: XSCMPOQP(1); break;
+ case 2: XSCMPOQP(2); break;
+ case 3: XSCMPOQP(3); break;
+ case 4: XSCMPOQP(4); break;
+ case 5: XSCMPOQP(5); break;
+ case 6: XSCMPOQP(6); break;
+ case 7: XSCMPOQP(7); break;
+ default:
+ printf("Unhandled shift value for %s %x\n", __FUNCTION__, x_index);
+ };
+}
+
+static void test_xscmpuqp(void) {
+ switch(x_index) {
+ case 0: XSCMPUQP(0); break;
+ case 1: XSCMPUQP(1); break;
+ case 2: XSCMPUQP(2); break;
+ case 3: XSCMPUQP(3); break;
+ case 4: XSCMPUQP(4); break;
+ case 5: XSCMPUQP(5); break;
+ case 6: XSCMPUQP(6); break;
+ case 7: XSCMPUQP(7); break;
+ default:
+ printf("Unhandled shift value for %s %x\n", __FUNCTION__, x_index);
+ };
+}
+
+static test_list_t testgroup_vector_scalar_compare_quads[] = {
+ { &test_xscmpexpqp, "xscmpexpqp" },
+ { &test_xscmpoqp , "xscmpoqp " },
+ { &test_xscmpuqp , "xscmpuqp " },
+ { NULL , NULL },
+};
+
+#define XSRQPI(R,RMC) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xsrqpi %1, %0, %2, %3" : "=v"(vec_xt) : "i"(R), "v"(vec_xb), "i"(RMC)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+#define XSRQPIX(R,RMC) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xsrqpix %1, %0, %2, %3" : "=v"(vec_xt) : "i"(R), "v"(vec_xb), "i"(RMC));\
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+#define XSRQPXP(R,RMC) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xsrqpxp %1, %0, %2, %3" : "=v"(vec_xt) : "i"(R), "v"(vec_xb), "i"(RMC));\
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+/* For the scalar round to quad instructions, x_index is used to key into
+ * two fields; x_index bit [2] becomes the one-bit 'R' and x_index bits [0, 1]
+ * becomes the two-bit 'RMC'.
+ */
+static void test_xsrqpi(void) {
+ switch(x_index) {
+ case 0: XSRQPI(0, 0); break;
+ case 1: XSRQPI(0, 1); break;
+ case 2: XSRQPI(0, 2); break;
+ case 3: XSRQPI(0, 3); break;
+ case 4: XSRQPI(1, 0); break;
+ case 5: XSRQPI(1, 1); break;
+ case 6: XSRQPI(1, 2); break;
+ case 7: XSRQPI(1, 3); break;
+ }
+}
+static void test_xsrqpix(void) {
+ switch(x_index) {
+ case 0: XSRQPIX(0, 0); break;
+ case 1: XSRQPIX(0, 1); break;
+ case 2: XSRQPIX(0, 2); break;
+ case 3: XSRQPIX(0, 3); break;
+ case 4: XSRQPIX(1, 0); break;
+ case 5: XSRQPIX(1, 1); break;
+ case 6: XSRQPIX(1, 2); break;
+ case 7: XSRQPIX(1, 3); break;
+ }
+}
+
+static void test_xsrqpxp(void) {
+ switch(x_index) {
+ case 0: XSRQPXP(0, 0); break;
+ case 1: XSRQPXP(0, 1); break;
+ case 2: XSRQPXP(0, 2); break;
+ case 3: XSRQPXP(0, 3); break;
+ case 4: XSRQPXP(1, 0); break;
+ case 5: XSRQPXP(1, 1); break;
+ case 6: XSRQPXP(1, 2); break;
+ case 7: XSRQPXP(1, 3); break;
+ }
+}
+
+static test_list_t testgroup_vector_scalar_rounding_quads[] = {
+ { &test_xsrqpi , "xsrqpi " },
+ { &test_xsrqpix, "xsrqpix" },
+ { &test_xsrqpxp, "xsrqpxp" },
+ { NULL , NULL },
+};
+
+
+/* ###### begin all_tests table. */
+
+/* table containing all of the instruction groups */
+struct test_group_table_t {
+ test_list_t *tests;
+ const char *name;
+ unsigned int flags;
+};
+
+typedef struct test_group_table_t test_group_table_t;
+
+static test_group_table_t all_tests[] = {
+ {
+ testgroup_ia_ops_two,
+ "PPC integer arith instructions with two args",
+ PPC_INTEGER | PPC_ARITH | PPC_TWO_ARGS,
+ },
+ {
+ testgroup_shifted_one,
+ "ppc one argument plus shift",
+ PPC_MISC | PPC_CR | PPC_TWO_ARGS,
+ },
+ {
+ testgroup_three_args,
+ "ppc three parameter ops",
+ PPC_INTEGER | PPC_ARITH | PPC_THREE_ARGS,
+ },
+ {
+ testgroup_logical_one,
+ "ppc count zeros",
+ PPC_INTEGER | PPC_LOGICAL | PPC_ONE_ARG,
+ },
+ {
+ testgroup_set_boolean,
+ "ppc set boolean",
+ PPC_INTEGER | PPC_LOGICAL | PPC_ONE_IMM,
+ },
+ {
+ testgroup_char_compare,
+ "ppc char compare",
+ PPC_INTEGER | PPC_COMPARE,
+ },
+ {
+ testgroup_vsx_absolute,
+ "ppc vector absolutes",
+ PPC_ALTIVEC | PPC_ARITH | PPC_TWO_ARGS,
+ },
+ {
+ testgroup_vector_immediate,
+ "ppc vector logical immediate",
+ PPC_ALTIVEC | PPC_LOGICAL | PPC_ONE_IMM,
+ },
+ {
+ testgroup_vector_logical_one,
+ "ppc vector logical one",
+ PPC_ALTIVEC | PPC_LOGICAL | PPC_ONE_ARG,
+ },
+ {
+ testgroup_vector_extend_sign,
+ "ppc vector extend sign",
+ PPC_ALTIVEC | PPC_LOGICAL | PPC_TWO_ARGS,
+ },
+ {
+ testgroup_vector_three_quad,
+ "ppc vector three quad",
+ PPC_ALTIVEC | PPC_LOGICAL | PPC_THREE_ARGS,
+ },
+ {
+ testgroup_vector_scalar_two_quad,
+ "ppc vector scalar quad",
+ PPC_ALTIVEC_QUAD | PPC_LOGICAL | PPC_TWO_ARGS,
+ },
+ {
+ testgroup_vector_scalar_compare_quads,
+ "ppc vector scalar compare exponents quads",
+ PPC_ALTIVEC_QUAD | PPC_COMPARE | PPC_COMPARE_ARGS,
+ },
+ {
+ testgroup_vector_scalar_rounding_quads,
+ "ppc vector scalar rounding quads",
+ PPC_ALTIVEC_QUAD | PPC_ROUND,
+ },
+ {
+ testgroup_vsx_xxpermute,
+ "ppc vector permutes",
+ PPC_ALTIVEC | PPC_PERMUTE,
+ },
+ {
+ testgroup_vector_four,
+ "ppc vector three args + dest",
+ PPC_ALTIVEC | PPC_LOGICAL | PPC_FOUR_ARGS,
+ },
+ {
+ testgroup_vector_inserts,
+ "ppc vector inserts",
+ PPC_ALTIVEC | PPC_INSERTEXTRACT | PPC_ONE_IMM,
+ },
+ {
+ testgroup_vector_extract,
+ "ppc vector extract from vector to reg",
+ PPC_ALTIVEC | PPC_INSERTEXTRACT | PPC_TWO_ARGS,
+ },
+ {
+ testgroup_vector_count_bytes,
+ "ppc vector count leading/trailing bytes",
+ PPC_ALTIVEC | PPC_POPCNT,
+ },
+ {
+ testgroup_vector_scalar_loadstore_length,
+ "ppc vector load/store",
+ PPC_ALTIVEC | PPC_LDST | PPC_ONE_IMM,
+ },
+ {
+ testgroup_vector_loadstore,
+ "ppc vector load/store",
+ PPC_ALTIVEC | PPC_LDST | PPC_TWO_ARGS,
+ },
+ {
+ testgroup_vectorscalar_move_tofrom,
+ "ppc vector scalar move to/from",
+ PPC_MISC | PPC_TWO_ARGS,
+ },
+ {
+ testgroup_vector_scalar_compare_exp_double,
+ "ppc vector scalar compare exponents doubles",
+ PPC_ALTIVEC_DOUBLE | PPC_COMPARE | PPC_COMPARE_ARGS,
+ },
+ {
+ testgroup_vector_scalar_data_class,
+ "ppc vector scalar test data class tests",
+ PPC_ALTIVEC_DOUBLE | PPC_COMPARE | PPC_ONE_ARG,
+ },
+ {
+ testgroup_vector_scalar_two_double,
+ "ppc vector scalar tests against float double two args ",
+ PPC_ALTIVEC_DOUBLE | PPC_COMPARE | PPC_TWO_ARGS,
+ },
+ {
+ testgroup_dfp_significance,
+ "ppc dfp significance",
+ PPC_DFP,
+ },
+ {
+ testgroup_bcd_misc,
+ "ppc bcd misc",
+ PPC_BCD,
+ },
+ {
+ testgroup_noop_misc,
+ "ppc noop misc",
+ PPC_NO_OP,
+ },
+ {
+ testgroup_pc_immediate_misc,
+ "ppc addpc_misc",
+ PPC_PC_IMMEDIATE,
+ },
+ { NULL, NULL, 0x00000000, },
+};
+
+static void testfunction_int_two_args (const char* instruction_name,
+ test_func_t func,
+ unsigned int test_flags)
+{
+ volatile HWord_t res;
+ volatile unsigned int cr;
+ int i, j;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_iargs; i++) {
+ for (j = 0; j < nb_iargs; j++) {
+
+ r14 = iargs[i];
+ r15 = iargs[j];
+
+ SET_CR_ZERO;
+ (*func)();
+ GET_CR(cr);
+ res = r17;
+
+ printf("%s %016lx, %016lx => %016lx (%08x)\n",
+ instruction_name, (long unsigned)iargs[i],
+ (long unsigned)iargs[j], (long unsigned)res,
+ cr);
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+#define instruction_sets_cr0_to_zero(inst_name) \
+ ( (strncmp(inst_name, "cnttzw.", 7) == 0 ) || \
+ (strncmp(inst_name, "cnttzd.", 7) == 0 ) )
+
+static void testfunction_logical_one (const char* instruction_name,
+ test_func_t func,
+ unsigned int test_flags) {
+ int i;
+ volatile HWord_t res;
+ volatile unsigned int cr;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_iargs; i++) {
+
+ r14 = iargs[i];
+
+ /* The logical instructions will set CR fields to zero, so
+ * lets start with some non zero content in CR0.
+ */
+ SET_CR0_FIELD(0xF);
+
+ (*func)();
+
+ res = r17;
+ GET_CR(cr);
+
+ printf("%s %016lx => %016lx",
+ instruction_name, (long unsigned)iargs[i], (long unsigned)res);
+
+ if (instruction_sets_cr0_to_zero(instruction_name)
+ && ((cr & 0xF0000000) != 0 )) {
+ /* The dotted version sets the CR0 to 0, verify */
+ printf(" Expected cr0 to be zero, it is (%08x)\n", cr & 0xF0000000);
+ }
+ printf("\n");
+
+ if (verbose) printf("\n");
+ }
+}
+
+void testfunction_one_arg_with_shift (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags)
+{
+ /*This function uses global variable x_shift */
+ volatile HWord_t res;
+ volatile unsigned int cr;
+ int i, j;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < SHIFT_VALUES_SIZE; i++) {
+ for (j = 0; j < SHIFT_ARRAY_SIZE; j++) {
+
+ r14 = values_to_shift[i];
+ x_shift = shift_amounts[j];
+
+ SET_CR_ZERO;
+
+ (*test_function)();
+
+ GET_CR(cr);
+ res = r17;
+
+ printf("%s %016lx, %016lx => %016lx (%08x)\n",
+ instruction_name, (long unsigned)values_to_shift[i],
+ (long unsigned)x_shift, (long unsigned)res, cr);
+ }
+ }
+}
+
+static void testfunction_three_args (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags)
+{
+ volatile HWord_t res;
+ volatile unsigned int cr;
+ int i, j, l;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_iargs; i++) {
+ for (j = 0; j < nb_iargs; j++) {
+ for (l = 0; l < nb_iargs; l++) {
+ r14 = iargs[i];
+ r15 = iargs[j];
+ r16 = iargs[l];
+
+ SET_CR_ZERO;
+
+ (*test_function)();
+
+ GET_CR(cr);
+ res = r17;
+
+ printf("%s %016lx, %016lx, %016lx => %016lx (%08x)\n",
+ instruction_name,
+ (long unsigned)r14, (long unsigned)r15,
+ (long unsigned)r16, (long unsigned)res,
+ cr);
+ }
+ }
+ }
+}
+
+static void testfunction_vector_absolute (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags)
+{
+ /* Notes:
+ * iterate across xa, xb values.
+ * Results are in xt.
+ */
+ volatile unsigned int cr;
+ int i, j;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 4) {
+ /* patterns more interesting when shifted like so.. */
+ for (j = 0; j < nb_vpcv; j += 2) {
+
+ vec_xa = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ vec_xb = (vector unsigned long){vsxargs[j], vsxargs[j]};
+ vec_xt = (vector unsigned long){0, 0};
+
+ printf("%s xa:%016lx %016lx xb:%016lx %016lx ",
+ instruction_name,
+ vec_xa[1],vec_xa[0],
+ vec_xb[0],vec_xb[1]
+ );
+ printf(" => ");
+
+ SET_CR_ZERO;
+
+ (*test_function)();
+
+ GET_CR(cr);
+
+ printf(" xt:%016lx %016lx (%08x)\n", vec_xt[0], vec_xt[1], cr);
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+static void testfunction_vector_xxpermute (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags)
+{
+ /* Notes:
+ * VSX permute uses both xt and xa as source registers.
+ * Permute control vector is in xb.
+ * Results are in xt.
+ */
+ volatile unsigned int cr;
+ int i, j;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 4) {
+ for (j = 0; j < nb_vpcv; j += 2) {
+
+ vec_xa = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ vec_xt = (vector unsigned long){vsxargs[i+2], vsxargs[i+3]};
+ vec_xb = (vector unsigned long){vpcv[j], vpcv[j+1]};
+
+ printf("%s %016lx %016lx %016lx %016lx, pcv[%016lx %016lx] => ",
+ instruction_name,
+ vec_xa[1], vec_xa[0],
+ vec_xt[1], vec_xt[0],
+ vec_xb[0], vec_xb[1]);
+
+ SET_CR_ZERO;
+
+ (*test_function)();
+
+ GET_CR(cr);
+
+ printf(" %016lx %016lx (%08x)\n", vec_xt[0], vec_xt[1], cr);
+
+#if defined (DEBUG_VECTOR_PERMUTE)
+ printf("DEBUG:%s %016lx %016lx %016lx %016lx, pcv[%016lx %016lx]\n",
+ ignore_name,
+ vec_xa[0], vec_xa[1],
+ vec_xt[0], vec_xt[1],
+ vec_xb[0], vec_xb[1]);
+#endif
+ }
+ if (verbose) printf("\n");
+ }
+}
+
+static void testfunction_vector_logical_one (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags)
+{
+ /* Notes:
+ * vector instructions with one input, one output.
+ * xt, xa
+ */
+ int i;
+ int t;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 2) {
+
+ vec_xa = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ for (t = 0; t < 2; t++) {
+ vec_xt[0] = (t == 0) ? 0 : 0xffffffffffffffff;
+ vec_xt[1] = (t == 0) ? 0 : 0xffffffffffffffff;
+
+ printf("%s xa:%016lx %016lx xt:%016lx %016lx => ",
+ instruction_name,
+ vec_xa[0], vec_xa[1],
+ vec_xt[0], vec_xt[1]);
+
+ (*test_function)();
+
+ printf(" xt:%016lx %016lx\n",
+ vec_xt[0], vec_xt[1]);
+ }
+ }
+ if (verbose) printf("\n");
+}
+
+static void testfunction_vector_logical_four (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags) {
+ /* Notes:
+ * vector instructions with three input arguments, one output.
+ * xt, xa, xb, xc.
+ * Permute control vector is in xc.
+ * Results are in xt.
+ */
+ volatile unsigned int cr;
+ int i, j;
+ int p;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 4) {
+ for (j = 0; j < nb_vargs; j += 4) {
+ for (p = 0; p < nb_vpcv; p += 2) {
+
+ vec_xa = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ vec_xb = (vector unsigned long){vsxargs[j], vsxargs[j+1]};
+ vec_xc = (vector unsigned long){vpcv[p], vpcv[p+1]};
+
+ printf("%s %016lx %016lx %016lx %016lx, pcv[%016lx %016lx] => ",
+ instruction_name,
+ vec_xa[1], vec_xa[0],
+ vec_xb[1], vec_xb[0],
+ vec_xc[0], vec_xc[1]);
+
+ SET_CR_ZERO;
+
+ (*test_function)();
+
+ GET_CR(cr);
+
+ printf(" %016lx %016lx (%08x)\n", vec_xt[0], vec_xt[1], cr);
+ }
+ }
+
+ if (verbose) printf("\n");
+ }
+}
+
+static
+void testfunction_vector_insert_or_extract_immediate (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags) {
+ /* Uses global variable x_index */
+ /* uses global variable insert_extract_error */
+ int i;
+ int t;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ /* for the insert and extract tests, we deliberately use only a
+ * subset of the vsxargs array as input data.
+ */
+ for (i = 2; i < 9 ; i += 4) { /* index into vsxargs[] array */
+
+ /* Note:
+ * Determining the proper offset for {extract, insert} byte, halfword,
+ * word, double would complicate things. For simplicity, allow the
+ * sub-functions to ignore input that would be invalid. Catch and
+ * suppress output for those cases per the global variable.
+ */
+ for (x_index = 0; x_index < 16 ; x_index++) {
+ vec_xb[0] = (unsigned long) vsxargs[i];
+ vec_xb[1] = (unsigned long) vsxargs[i+1];
+
+ /* Run each test against all zeros and then all ones,
+ * This is intended to help any bitfield changes stand out.
+ */
+ for (t = 0; t < 2; t++) {
+
+ vec_xt[0] = (t == 0) ? 0 : 0xffffffffffffffff;
+ vec_xt[1] = (t == 0) ? 0 : 0xffffffffffffffff;
+
+ insert_extract_error = 0;
+
+ (*test_function)();
+
+ if (!insert_extract_error) {
+ printf("%s %016lx %016lx [%d] (into%s) => ",
+ instruction_name, vec_xb[1], vec_xb[0], x_index,
+ (t == 0 ? " zeros" : " ones") );
+
+ printf("%016lx %016lx\n", vec_xt[1], vec_xt[0]);
+ }
+ }
+ }
+ }
+}
+
+
+static void testfunction_vector_immediate (const char * instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags) {
+ /* Uses global variable x_splat */
+ int i;
+ int t;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < SPLAT_ARRAY_SIZE; i++) {
+ x_splat = splat_values[i];
+ for (t = 0; t < 2; t++) {
+ vec_xt[0] = (t == 0) ? 0 : 0xffffffffffffffff;
+ vec_xt[1] = (t == 0) ? 0 : 0xffffffffffffffff;
+
+ printf("%s %016lx %016lx [%2x] => ",
+ instruction_name, vec_xt[1], vec_xt[0], x_splat);
+
+ (*test_function)();
+
+ printf("%016lx %016lx\n", vec_xt[1], vec_xt[0]);
+ }
+ }
+}
+
+static void testfunction_vector_loadstore (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_flags) {
+ /* exercises vector loads from memory, and vector stores from memory.
+ * <load or store instruction> XS, RA, RB
+ * For these tests, RA will be zero.
+ * EA is then, simply, RB.
+ */
+ int i;
+ int buffer_pattern;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 2) {
+
+ vec_xt = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ r14 = 0;
+ r15 = (unsigned long) & buffer;
+
+ for (buffer_pattern = 0; buffer_pattern < MAX_BUFFER_PATTERNS;
+ buffer_pattern++) {
+
+ /* set patterns on both ends */
+ initialize_buffer(buffer_pattern);
+
+ printf("%s ", instruction_name);
+ printf("%016lx %016lx ", vec_xt[1], vec_xt[0]);
+ dump_small_buffer();
+ printf(" =>\n");
+
+ (*test_function)();
+
+ printf(" %016lx %016lx ", vec_xt[1], vec_xt[0]);
+ dump_small_buffer();
+ printf("\n");
+ }
+ }
+}
+
+
+static void testfunction_vectorscalar_move_tofrom (const char * instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags) {
+ /* Move to / move from vector scalar. spin through simple variants of
+ * both the VSR and the register.
+ * for simplicity, RA from 'mtvsrdd xt, ra, rb' is 0.
+ */
+ int i, v;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < PATTERN_SIZE; i++) {
+ for (v = 0; v < PATTERN_SIZE; v++) {
+ /* if i==v, patterns will match, so just skip these as
+ * non-interesting..
+ */
+ if (i == v) continue;
+ r14 = 0;
+ r15 = pattern[i%PATTERN_SIZE];
+ vec_xt[0] = pattern[v%PATTERN_SIZE];
+ vec_xt[1] = pattern[v%PATTERN_SIZE];
+
+ printf("%s ", instruction_name);
+ printf("%016lx %016lx %lx %016lx ", vec_xt[1], vec_xt[0],
+ (long unsigned)r14, (long unsigned)r15 );
+
+ (*test_function)();
+
+ printf("=> %016lx %016lx %lx %016lx", vec_xt[1], vec_xt[0],
+ (long unsigned)r14, (long unsigned)r15 );
+ printf("\n");
+ }
+ }
+}
+
+/* Some of the load/store vector instructions use a length value that
+ * is stored in bits 0:7 of RB. */
+#define uses_bits_0to7(instruction_name) ( \
+ (strncmp(instruction_name, "lxvl " ,5) == 0) || \
+ (strncmp(instruction_name, "lxvll " ,6) == 0) || \
+ (strncmp(instruction_name, "stxvl " ,6) == 0) || \
+ (strncmp(instruction_name, "stxvll ",7) == 0) )
+
+static void testfunction_vector_scalar_loadstore_length (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_flags) {
+ /* exercises vector loads from memory, and vector stores from memory.
+ * with length specification.
+ * <load or store instruction> XS, RA, RB
+ * For these tests, RA (i.e. EA) is address of source/dest and can
+ * not be zero.
+ * The length value is in rb. For a subset of these instructions,
+ * the length is stored in bits 0:7, versus 56:63 of r15.
+ */
+ int i;
+ unsigned long l;
+ int buffer_pattern;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 2) {
+ for (l = 0; l <= 16; l += 4) {
+
+ for (buffer_pattern = 0; buffer_pattern < MAX_BUFFER_PATTERNS;
+ buffer_pattern++) {
+
+ /* set patterns on both ends */
+ vec_xt = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ r14 = (unsigned long) & buffer;
+
+ if (uses_bits_0to7(instruction_name)) {
+ /* length is stored in bits 0:7 of gpr[r15]. */
+ r15 = (unsigned long)((0xff & l) << 56);
+
+ } else {
+ /* length is stored in gpr[r15]. */
+ r15 = l;
+ }
+
+ initialize_buffer(buffer_pattern);
+
+ printf("%s ", instruction_name);
+ printf("%016lx %016lx ", vec_xt[1], vec_xt[0] );
+ if (uses_bits_0to7(instruction_name)) {
+ printf(" 0x%2lx ", (long unsigned)r15>>56 );
+
+ } else {
+ printf(" l = 0x%2lx ", (long unsigned)r15 );
+ }
+
+ dump_small_buffer();
+
+ (*test_function)();
+
+ printf("=> %016lx %016lx & %16lx", vec_xt[1], vec_xt[0],
+ (long unsigned)r15 );
+ printf("\n");
+ }
+ }
+ }
+}
+
+static void testfunction_vector_count_bytes (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_flags)
+{
+ int i;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 2) {
+ vec_xb = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ r14 = 0;
+
+ printf("%s ", instruction_name);
+ printf("%016lx %016lx %2d ", vec_xb[1], vec_xb[0], (unsigned)r14);
+
+ (*test_function)();
+
+ printf("=> %2d\n", (unsigned)r14 );
+ }
+}
+
+static void testfunction_vector_extract (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_flags)
+{
+ int i;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 2) {
+ vec_xb = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ for (r15 = 0; r15 < 16; r15++) {
+ r14 = 0;
+
+ printf("%s ", instruction_name);
+ printf("%016lx %016lx %2d ", vec_xb[1], vec_xb[0], (unsigned)r15);
+
+ (*test_function)();
+
+ printf("=> %16lx\n", (long unsigned)r14 );
+ }
+ }
+}
+
+static void testfunction_vector_extend_sign (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_flags)
+{
+ int i;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 2) {
+ vec_xb = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ vec_xt = (vector unsigned long){0, 0};
+
+ printf("%s ", instruction_name);
+ printf("%016lx %016lx ", vec_xb[1], vec_xb[0]);
+
+ (*test_function)();
+
+ printf("=> %016lx %016lx\n", vec_xt[1], vec_xt[0]);
+ }
+}
+
+/* packed binary decimal misc */
+
+#define convert_from_zoned(instruction_name) (strncmp(instruction_name, "bcdcfz", 6) ==0 )
+
+#define convert_from_national(instruction_name) (strncmp(instruction_name, "bcdcfn", 6) == 0)
+
+#define convert_to_zoned(instruction_name) (strncmp(instruction_name, "bcdctz", 6) == 0)
+
+#define convert_to_national(instruction_name) (strncmp(instruction_name, "bcdctn", 6) == 0)
+
+#define shift_or_truncate(instruction_name) \
+ (strncmp(instruction_name, "bcds", 4) == 0 || \
+ strncmp(instruction_name, "bcdus", 5) == 0 || \
+ strncmp(instruction_name, "bcdsr", 5) == 0 || \
+ strncmp(instruction_name, "bcdtrunc", 8) == 0 || \
+ strncmp(instruction_name, "bcdutrunc", 9) == 0)
+
+
+/* Helper function - returns 1 or 0 per whether the p1 or p0 string
+ * exists in the instruction name passed in. The PS indicates preferred
+ * sign, and has meaning for some of the BCD instructions.
+ */
+static inline int p_value(const char * instruction_name) {
+ char * found_p0;
+ char * found_p1;
+
+ found_p1 = strstr(instruction_name, "p1");
+ found_p0 = strstr(instruction_name, "p0");
+
+ if (found_p1) return 1;
+
+ if (found_p0) return 0;
+
+ if (verbose) printf("p* substring not found in (%s)\n", instruction_name);
+
+ return 0;
+}
+
+/* bcd test has been split out a bit.. a few bcd specific global vars here
+ * to help keep that clean.
+ */
+long shift_or_truncate_instruction;
+int xa_sign, xb_sign, xt_sign;
+int short_circuit;
+
+/* testfunction_bcd_setup_inputs
+ * This is a helper function that sets up the vec_xa, vec_xb values for
+ * use in the bcd tests.
+ */
+static inline void testfunction_bcd_setup_inputs(const char * instruction_name,
+ int i, int j) {
+ short_circuit=0;
+
+ if (shift_or_truncate_instruction) {
+ if (i >= nb_decimal_shift_entries - 2) {
+ short_circuit = 1;
+ return;
+ }
+ vec_xa = (vector unsigned long) {decimal_shift_table[i+1],
+ decimal_shift_table[i]};
+
+ } else {
+ if (i >= nb_decimal_shift_entries - 2) {
+ short_circuit = 1;
+ return;
+ }
+
+ vec_xa = (vector unsigned long) {packed_decimal_table[i+1],
+ packed_decimal_table[i]};
+ xa_sign = extract_packed_decimal_sign(vec_xa[0], vec_xa[1]);
+ }
+
+ if (convert_from_zoned(instruction_name)) { /* convert from zoned */
+ if (j >= nb_zoned_decimal_entries - 2) {
+ short_circuit = 1;
+ return;
+ }
+
+ vec_xb = (vector unsigned long) {zoned_decimal_table[j+1],
+ zoned_decimal_table[j]};
+ xb_sign = extract_zoned_decimal_sign(vec_xb[0], vec_xb[1]);
+
+ } else if (convert_from_national(instruction_name)) {
+ /* convert from national */
+ if (j >= nb_national_decimal_entries - 2) {
+ short_circuit = 1;
+ return;
+ }
+ vec_xb = (vector unsigned long) {national_decimal_table[j+1],
+ national_decimal_table[j]};
+ xb_sign = extract_national_decimal_sign(vec_xb[0], vec_xb[1]);
+
+ } else {
+ /* packed decimal entries */
+ if (j >= nb_packed_decimal_entries - 2) {
+ short_circuit = 1;
+ return;
+ }
+ vec_xb = (vector unsigned long) {packed_decimal_table[j+1],
+ packed_decimal_table[j]};
+ xb_sign = extract_packed_decimal_sign(vec_xb[0], vec_xb[1]);
+ }
+}
+
+static inline void testfunction_bcd_display_outputs(const char * instruction_name) {
+
+ printf(" xt:%016lx %016lx", vec_xt[0], vec_xt[1] );
+
+ if (convert_to_zoned(instruction_name)) {
+ /* convert to zoned */
+ xt_sign = extract_zoned_decimal_sign(vec_xt[0], vec_xt[1]);
+ dissect_zoned_decimal_sign(xt_sign, p_value(instruction_name));
+
+ } else if (convert_to_national(instruction_name)) {
+ /* convert to national */
+ xt_sign = extract_national_decimal_sign(vec_xt[0], vec_xt[1]);
+ dissect_national_decimal_sign(xt_sign);
+
+ } else {
+ /* packed decimal entries, or shift/truncate */
+ if (!shift_or_truncate_instruction) {
+ xt_sign = extract_packed_decimal_sign(vec_xt[0], vec_xt[1]);
+ dissect_packed_decimal_sign(xt_sign);
+ }
+ }
+ printf("\n");
+}
+
+#define uses_half_precision_input(instruction_name) ( \
+ (strncmp(instruction_name, "xscvhpdp", 8) == 0) || \
+ (strncmp(instruction_name, "xvcvhpsp", 8) == 0) )
+
+#define uses_single_precision_input(instruction_name) ( \
+ (strncmp(instruction_name, "xvcvsphp", 8) == 0) )
+
+#define uses_double_precision_input(instruction_name) ( \
+ (strncmp(instruction_name, "xscvdphp", 8) == 0) )
+
+#define uses_half_precision_output(instruction_name) ( \
+ (strncmp(instruction_name, "xscvdphp", 8) == 0) || \
+ (strncmp(instruction_name, "xvcvsphp", 8) == 0) )
+
+#define is_half_precision_instruction(instruction_name) ( \
+ uses_half_precision_input(instruction_name) || \
+ uses_half_precision_output(instruction_name) )
+
+/* Helper for those instructions with an unused second dword, indicating
+ * the outer loop can be short-circuited after one pass.
+ */
+#define unused_second_dword(instruction_name) ( \
+ (strncmp(instruction_name, "xscvhpdp", 8) == 0) || \
+ (strncmp(instruction_name, "xscvdphp", 8) == 0) )
+
+static void testfunction_vector_scalar_two_quad (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_flags)
+{
+ int i;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 2) {
+ if (uses_half_precision_input(instruction_name)) {
+ vec_xb = (vector unsigned long){binary16_float_vsxargs[i],
+ binary16_float_vsxargs[i+1]};
+ } else {
+ vec_xb = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ }
+
+ vec_xt = (vector unsigned long){0, 0};
+
+ printf("%s ", instruction_name);
+ printf("%016lx %016lx ", vec_xb[1], vec_xb[0]);
+
+ SET_FPSCR_ZERO
+
+ (*test_function)();
+
+ GET_FPSCR(local_fpscr);
+
+ printf("=> %016lx %016lx", vec_xt[1], vec_xt[0]);
+ dissect_fpscr(local_fpscr);
+ printf("\n");
+ }
+}
+
+static void
+testfunction_vector_scalar_compare_exp_double (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags){
+ int i,j;
+ /* Uses global variable x_index */
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_float_vsxargs - 1; i++) {
+ for (j = 0; j < nb_float_vsxargs - 1; j++) {
+ for (x_index = 2; x_index < 3; x_index++) {
+
+ /* TODO FIXME- there was a casting issue below. This incantation
+ * works, but I suspect can be simplified...
+ */
+ vec_xa = (vector unsigned long){(unsigned long)binary64_float_vsxargs[i+1], (unsigned long)binary64_float_vsxargs[i]};
+
+ vec_xb = (vector unsigned long){(unsigned long)binary64_float_vsxargs[j], (unsigned long)binary64_float_vsxargs[j+1]};
+
+ /* run each test against cleared CR and FPSCR */
+ /* Note that the SET_*_ZERO calls are not actually sufficient here,
+ * due to infrastructure between here and there that also set some
+ * of the CR bits. The condition regs are cleared here, but are
+ * also both cleared and read within the to-be-tested asm chunk to
+ * get accurate results.
+ */
+ SET_CR_ZERO
+ SET_FPSCR_ZERO
+
+ printf("%s %016lx %016lx %016lx %016lx",
+ instruction_name,
+ vec_xa[0], vec_xa[1],
+ vec_xb[0], vec_xb[1]);
+
+ if (verbose) printf(" cr#%d ", x_index);
+
+ printf(" => ");
+
+ (*test_function)();
+
+ dissect_fpscr(local_fpscr);
+ dissect_fpscr_result_value_class(local_fpscr);
+ dissect_cr_rn(local_cr, x_index);
+ printf("\n");
+ }
+ }
+ }
+}
+
+/* These instructions set the floating point condition codes. */
+/* verify logic reversal */
+#define does_not_set_floating_point_cc(instruction_name) \
+ (strncmp(instruction_name, "xvtstdcdp", 9) == 0) | \
+ (strncmp(instruction_name, "xvtstdcsp", 9) == 0)
+
+static void
+testfunction_vector_scalar_data_class (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags) {
+ int j;
+ /* x_index is used as a key into the DCMX value.
+ *
+ * BF, XB, DCMX
+ * For instruction tests called through this function, note that we are only
+ * utilizing bf (condition register) #3; where 3 was mostly randomly
+ * chosen, and has no special meaning.
+ */
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (j = 0; j < nb_float_vsxargs - 1; j++) {
+ /* for dcmx field, start with x_index=1 to skip the 'all' dcmx entry. */
+ for (x_index = 1; x_index < 8; x_index++) {
+ vec_xb[0] = float_vsxargs[j];
+ vec_xb[1] = float_vsxargs[j+1];
+ vec_xt[0] = 0x0a0a0a0a0a0a0a0a;
+ vec_xt[1] = 0x0505050505050505;
+ SET_CR_ZERO
+ SET_FPSCR_ZERO
+
+ dcmx_match = 0;
+
+ (*test_function)();
+
+ /* the local_fpscr value is gathered within the test_function call. */
+ dcmx_match = (local_fpscr & FPCC_FE_BIT);
+
+ if (dcmx_match || (verbose>2)) {
+ printf("%s %016lx, %016lx ",
+ instruction_name, vec_xb[1], vec_xb[0]);
+
+ print_dcmx_field(x_index);
+
+ if (dcmx_match)
+ printf(" => Match. ");
+
+ printf(" %016lx, %016lx ", vec_xt[1], vec_xt[0]);
+
+ dissect_cr_rn(local_cr,3);
+ dissect_fpscr_dcmx_indicator(local_fpscr);
+ printf("\n");
+ }
+
+ printf("%s %016lx, %016lx => ",
+ instruction_name, vec_xb[1], vec_xb[0]);
+
+ printf(" %016lx, %016lx\n", vec_xt[1], vec_xt[0]);
+ }
+ }
+}
+
+static void testfunction_vector_scalar_compare_quads (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags) {
+ /* Uses global variable x_index */
+ int i,j;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_float_vsxargs - 1; i++) {
+ for (j = 0; j < nb_float_vsxargs - 1; j++) {
+ for (x_index = 0; x_index < 3 ; x_index++) {
+ vec_xa[0] = float_vsxargs[i];
+ vec_xa[1] = float_vsxargs[i+1];
+ vec_xb[0] = float_vsxargs[j];
+ vec_xb[1] = float_vsxargs[j+1];
+
+ /* run each test against cleared CR and FPSCR */
+ /* Note that the SET_*_ZERO calls are not actually sufficient here,
+ * due to infrastructure between here and there that also set some
+ * of the CR bits. The condition regs are cleared here, but are
+ * also both cleared and read within the to-be-tested asm chunk
+ * to get accurate results.
+ */
+ printf("%s %016lx%016lx %016lx%016lx (cr#%d) => ",
+ instruction_name,
+ vec_xa[1], vec_xa[0],
+ vec_xb[1], vec_xb[0],
+ x_index);
+
+ SET_CR_ZERO
+ SET_FPSCR_ZERO
+
+ (*test_function)();
+
+ GET_CR(local_cr);
+ GET_FPSCR(local_fpscr);
+
+ dissect_fpscr(local_fpscr);
+ dissect_cr_rn(local_cr, x_index);
+ printf("\n");
+ }
+ }
+ }
+}
+
+static void testfunction_vector_scalar_rounding_quads (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags) {
+ /* Uses global variable x_index */
+ /* For this function, x_index is used as a key into R and RMC values.
+ * Also note, the fpscr.rn value may be used to affect the rounding mode.
+ * that variation is not evaluated here. */
+ int j;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (j = 0; j < nb_float_vsxargs - 1; j++) {
+ for (x_index = 0; x_index < 8; x_index++) {
+ vec_xb[0] = float_vsxargs[j];
+ vec_xb[1] = float_vsxargs[j+1];
+
+ printf("%s %016lx%016lx (R=%x) (RMC=%x) => ",
+ instruction_name,
+ vec_xb[1], vec_xb[0],
+ (x_index & 0x4) >> 2, x_index & 0x3);
+
+ SET_CR_ZERO
+ SET_FPSCR_ZERO
+
+ (*test_function)();
+
+ GET_FPSCR(local_fpscr);
+
+ printf("%016lx%016lx", vec_xt[1], vec_xt[0]);
+ dissect_fpscr(local_fpscr);
+ printf("\n");
+ }
+ }
+}
+
+static void testfunction_vector_three_special (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags){
+ /* Notes:
+ * vector instructions with two inputs, one output.
+ * vrt, vra, vrb
+ */
+ int i, j;
+ int t;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_float_vsxargs - 1; i++) {
+ for (j = 0; j < nb_float_vsxargs - 1; j++) {
+ vec_xa[0] = float_vsxargs[i];
+ vec_xa[1] = float_vsxargs[i+1];
+ vec_xb[0] = float_vsxargs[j];
+ vec_xb[1] = float_vsxargs[j+1];
+
+ for (t = 0; t < 2; t++) {
+ vec_xt[0] = (t == 0) ? 0 : 0xffffffffffffffff;
+ vec_xt[1] = (t == 0) ? 0 : 0xffffffffffffffff;
+
+ SET_FPSCR_ZERO;
+ printf("%s %016lx%016lx %016lx%016lx %016lx%016lx => ",
+ instruction_name,
+ vec_xa[1], vec_xa[0],
+ vec_xb[1], vec_xb[0],
+ vec_xt[1], vec_xt[0]);
+
+ (*test_function)();
+
+ GET_FPSCR(local_fpscr);
+
+ printf(" %016lx%016lx", vec_xt[1], vec_xt[0]);
+ dissect_fpscr(local_fpscr);
+ printf("\n");
+ }
+ }
+ }
+}
+
+#define vector_instruction_is_xvcvhpsp(instruction_name) \
+ (strncmp(instruction_name, "xvcvhpsp", 8) == 0)
+
+static void testfunction_vector_scalar_two_double(const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags) {
+ /* Notes:
+ * iterate across double values stored in xa, xb.
+ * Or, on half-word values in vec_xb.
+ * Results are in vec_xt.
+ */
+ int i, j;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_float_vsxargs - 1; i += 2) {
+ for (j = 0; j < nb_float_vsxargs - 1; j += 2) {
+ /* vec_xb is only used by the convert instructions, the other callers
+ * use the r14, r15 fields.
+ * The 16-bit converts reference every other half-word in the vector.
+ * For this reason, populate the input field with a cross-section of
+ * values.
+ */
+ printf("%s ",instruction_name);
+
+ if (uses_half_precision_input(instruction_name)) {
+ vec_xb = (vector unsigned long) {
+ binary16_float_vsxargs[i] |
+ binary16_float_vsxargs[j] << 16 |
+ binary16_float_vsxargs[i+1] << 32 |
+ binary16_float_vsxargs[j+1] << 48,
+ binary16_float_vsxargs[(nb_float_vsxargs - 1) - j - 1 ] |
+ binary16_float_vsxargs[(nb_float_vsxargs - 1) - i - 1] << 16 |
+
+ binary16_float_vsxargs[(nb_float_vsxargs - 1) - j ] << 32 |
+ binary16_float_vsxargs[(nb_float_vsxargs - 1) - i ] << 48
+ };
+ printf(" vec_xb[1] = 0x%lx, vec_xb[0] = 0x%lx ",
+ vec_xb[1], vec_xb[0]);
+
+ } else if (uses_single_precision_input(instruction_name)) {
+ vec_xb = (vector unsigned long) {
+ binary32_float_vsxargs[i] |
+ binary32_float_vsxargs[i+1] << 32,
+ binary32_float_vsxargs[nb_float_vsxargs - 1 - j ] |
+ binary32_float_vsxargs[nb_float_vsxargs - 1 - j ] << 32
+ };
+ printf(" vec_xb[1] = 0x%lx, vec_xb[0] = 0x%lx ",
+ vec_xb[1], vec_xb[0]);
+
+ } else { /* uses double */
+ r14 = binary64_float_vsxargs[i];
+ r15 = binary64_float_vsxargs[j];
+ printf(" r14 = 0x%lx, r15 = 0x%lx ", r14, r15);
+ }
+
+ vec_xt = (vector unsigned long){0, 0};
+
+ printf("%016lx %016lx ", vec_xb[1], vec_xb[0] );
+
+ if ((verbose > 2) && uses_double_precision_input(instruction_name)) {
+ dissect_binary64_float(vec_xb[1]);
+ dissect_binary64_float(vec_xb[0]);
+ }
+
+ printf(" => ");
+ SET_FPSCR_ZERO
+
+ (*test_function)();
+
+ GET_FPSCR(local_fpscr);
+ printf(" %016lx %016lx", vec_xt[1], vec_xt[0]);
+
+ if ((verbose > 2) && uses_half_precision_output(instruction_name)) {
+ dissect_double_as_16s(vec_xt[1]);
+ dissect_double_as_16s(vec_xt[0]);
+ }
+
+ /* The xvcvhpsp instruction does not set the C and FPCC fields */
+ if (!vector_instruction_is_xvcvhpsp(instruction_name))
+ dissect_fpscr(local_fpscr);
+
+ printf("\n");
+ } // j
+
+ /* If we are doing half precision conversions, the i-loop can be
+ * short-circuited to avoid duplicate input values. */
+ if (unused_second_dword(instruction_name))
+ i = nb_float_vsxargs+1;
+ } // i
+}
+
+static void testfunction_set_boolean (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags)
+{
+ int cr_base_value;
+ /* Notes:
+ * Set RT to values 0, -1, 1 depending on what bits are set in the specified
+ * CR field. x_index references here reflect the cr_field number.
+ */
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (x_index = 0; x_index <= 7; x_index++) {
+ for (cr_base_value = 0; cr_base_value <= 8; cr_base_value++) {
+ cr_value = (0x11111111 * cr_base_value)
+ & (0xf << (4 * (7 - x_index))) ;
+
+ r14 = 0xa5a5a5a5c7c7c7c7;
+
+ printf("%s cr_field:%1x cr_value::%08x",
+ instruction_name, x_index,cr_value);
+ printf(" => ");
+
+ (*test_function)();
+
+ printf(" %016lx\n", r14);
+ }
+ }
+}
+
+
+static void testfunction_char_compare (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags)
+{
+ /* Notes:
+ * iterate through char values stored in RA, RB.
+ * Results stored in cr field BF.
+ */
+ int i, j;
+ int local_crf;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (x_index = 0; x_index <= 7; x_index++) {
+ for (i = 0; i < nb_char_ranges; i += 4) {
+ for (j = 0; j < nb_char_args; j++) {
+ r14 = char_args[j];
+
+ /* For cmprb*, only needs the lower characters. */
+ r15 = char_ranges[i] | (char_ranges[i+1] << 8) |
+ char_ranges[i+2] << 16 | (char_ranges[i+3] << 24);
+
+ /* For cmpeqb, also load the rest of the range field, shift allk
+ * chars up by one.
+ */
+ r15 |= (r15 + 0x01010101) << 32;
+ printf("%s 0x%02lx (%c) (cmpeq:0x%016lx) (cmprb:src22(%c-%c) src21(%c-%c))",
+ instruction_name,
+ r14, (int)r14,
+ r15, (int)(r15 & 0xff), (int)((r15 >> 8) & 0xff),
+ (int)((r15 >> 16) & 0xff), (int)((r15 >> 24) & 0xff)
+ );
+
+ printf(" =>");
+
+ (*test_function)();
+
+ GET_CR(local_cr);
+ local_crf = extract_cr_rn(local_cr, x_index);
+
+ if (verbose)
+ printf(" %s found or in range (%x)",
+ (cr_positive_set(local_crf))?" " : " not", local_crf);
+ else
+ if (cr_positive_set(local_crf)) printf(" in range/found");
+
+ printf("\n");
+ }
+ }
+ }
+}
+
+#define instruction_uses_quads(instruction_name) (strncmp(instruction_name, "dtstsfiq", 8) == 0)
+
+static void testfunction_dfp_significance (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags)
+{
+ int local_crf;
+ int i;
+ int num_dfp_vals;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ if (instruction_uses_quads(instruction_name)) {
+ num_dfp_vals = nb_dfp128_vals;
+ } else {
+ num_dfp_vals = nb_dfp64_vals;
+ }
+
+ for (i = 0; i < num_dfp_vals; i++) {
+ if (instruction_uses_quads(instruction_name)) {
+ dfp_value.u128.vall = dfp128_vals[i * 2];
+ dfp_value.u128.valu = dfp128_vals[(i * 2) + 1];
+
+ } else {
+ // could rework this to use u64.val, but...
+ dfp_value.u128.vall = dfp128_vals[i ];
+ dfp_value.u128.valu = dfp128_vals[i ];
+ }
+
+ /* Keeping test simpler, always using cr3 within test_dtstsfi* */
+ for (dfp_significance = 0; dfp_significance <= 63;) {
+ /* Todo: tweak output here, or input values so the generated content
+ * looks better.
+ */
+ printf("%s significance(0x%02x) ",
+ instruction_name, dfp_significance);
+
+ if (instruction_uses_quads(instruction_name)) {
+ dissect_dfp128_float(dfp_value.u128.vall, dfp_value.u128.valu);
+
+ if (verbose > 6)
+ printf("(RAW) value = %16lx,%016lx ",
+ dfp_value.u128.vall, dfp_value.u128.valu /*f14, f15 */);
+
+ } else {
+ dissect_dfp64_float(dfp_value.u128.vall);
+
+ if (verbose > 6)
+ printf("(RAW) value = %16lx ", dfp_value.u128.vall /*f14 */);
+ }
+
+ (*test_function)();
+
+ GET_CR(local_cr);
+
+ local_crf = extract_cr_rn(local_cr, /* hardcoded cr3 */ 3);
+ dissect_cr_rn(local_cr, /* hardcoded cr3 */ 3);
+
+ printf(" (%x)", local_crf);
+ printf("\n");
+
+ /* Special case for incrementation of the significance checking
+ * value.
+ */
+ if (dfp_significance < 8)
+ dfp_significance += 4; /* 0, 4, 8 */
+
+ else if (dfp_significance < 32)
+ dfp_significance += 8; /* 16, 24, 32 */
+
+ else if (dfp_significance < 48)
+ dfp_significance += 16; /* 48 */
+
+ else
+ dfp_significance += 15; /* 63 */
+ }
+ }
+}
+
+/* packed binary decimal misc */
+
+#define convert_tofrom_instruction(instruction_name) \
+ ( (strncmp(instruction_name, "bcdcf", 5) == 0) || \
+ (strncmp(instruction_name, "bcdct", 5) == 0) )
+
+static void testfunction_bcd_misc (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags)
+{
+ int i, j;
+ int local_crf;
+ long max_xa_entries = 0;
+ long max_xb_entries = 0;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ shift_or_truncate_instruction = shift_or_truncate(instruction_name);
+
+ max_xa_entries = MAX(max_xa_entries, nb_decimal_shift_entries);
+ max_xa_entries = MAX(max_xa_entries, nb_packed_decimal_entries);
+
+ max_xb_entries = MAX(max_xb_entries, nb_zoned_decimal_entries);
+ max_xb_entries = MAX(max_xb_entries, nb_national_decimal_entries);
+ max_xb_entries = MAX(max_xb_entries, nb_packed_decimal_entries);
+
+ for (i = 0; i < (max_xa_entries - 1); i += 2) {
+ for (j = 0; j < (max_xb_entries - 1); j += 2) {
+ testfunction_bcd_setup_inputs(instruction_name, i, j);
+
+ if (short_circuit) continue;
+
+ printf("%s ", instruction_name);
+ printf("xa:%016lx %016lx ", vec_xa[0], vec_xa[1]);
+
+ if (!shift_or_truncate_instruction)
+ dissect_packed_decimal_sign(xa_sign);
+
+ printf(" xb:%016lx %016lx ", vec_xb[0], vec_xb[1]);
+
+ if (convert_from_zoned(instruction_name)) {
+ /* convert from zoned */
+ dissect_zoned_decimal_sign(xb_sign, p_value(instruction_name));
+
+ } else if (convert_from_national(instruction_name)) {
+ /* convert from national */
+ dissect_national_decimal_sign(xb_sign);
+
+ } else {
+ /* packed decimal entries */
+ if (!shift_or_truncate_instruction)
+ dissect_packed_decimal_sign(xb_sign);
+ }
+
+ printf(" => ");
+ SET_CR_ZERO
+
+ (*test_function)();
+
+ GET_CR(local_cr);
+
+ /* note: the bcd instructions are hard wired to use cr6. */
+ local_crf = extract_cr_rn(local_cr, 6);
+ dissect_cr_rn(local_cr, 6);
+ printf(" (%x)", local_crf);
+
+ if (cr_overflow_set(local_crf)) {
+ /* If overflow (S0) is set the results are undefined. Force the
+ * output to print as zeros so we have consistent results for
+ * comparison.
+ */
+ printf(" xt:%016lx %016lx", 0UL, 0UL);
+
+ } else {
+ testfunction_bcd_display_outputs(instruction_name);
+ }
+
+ printf("\n");
+ } // j = xb loop.
+
+ /* Since the bcdct* convert_tofrom instructions do not use the xa
+ * field, we will short-circuit the xa (i=*) loop here.
+ */
+ if (convert_tofrom_instruction(instruction_name))
+ i = nb_packed_decimal_entries;
+ } //i = xa loop.
+}
+
+
+static void testfunction_noop_misc (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags)
+{
+ VERBOSE_FUNCTION_CALLOUT
+
+ printf("%s ", instruction_name);
+ printf(" =>");
+
+ (*test_function)();
+
+ printf("\n");
+}
+
+static void testfunction_pc_immediate_misc (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags)
+{
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (x_index = 0; x_index < 16; x_index++) {
+ printf("%s ", instruction_name);
+ printf(" %016x ", x_index);
+ printf(" => ");
+ (*test_function)();
+ printf(" %016lx\n", r14);
+ }
+}
+
+/* ######## begin grand testing loops. */
+typedef struct insn_sel_flags_t_struct {
+ unsigned int one_arg, two_args, three_args, four_args, cmp_args, ld_args, st_args,
+ one_imed_args;
+ unsigned int arith, logical, compare, popcnt, ldst, insert_extract, permute, round;
+ unsigned int integer, altivec, altivec_quad, altivec_double, dfp, bcd, misc,
+ no_op, pc_immediate;
+ unsigned int cr;
+} insn_sel_flags_t;
+
+static void do_tests ( insn_sel_flags_t seln_flags)
+{
+ test_group_t group_function;
+ test_list_t *tests;
+ unsigned int nb_args, type, family;
+ int i, j, n;
+
+ n = 0;
+ group_function = NULL;
+
+ /* self-test of some utility functions. */
+ if (verbose > 1) {
+ printf("fpscr zero'd out:");
+ dissect_fpscr(0);
+ printf("\n");
+ printf("fpscr all ones:");
+ dissect_fpscr(0xffffffffffffffff);
+ printf("\n");
+ printf("fpscr RN bits:");
+ dissect_fpscr_rounding_mode(0x0000000000000003);
+ dissect_fpscr_rounding_mode(0x0000000000000002);
+ dissect_fpscr_rounding_mode(0x0000000000000001);
+ dissect_fpscr_rounding_mode(0x0000000000000000);
+ printf("\n");
+ }
+
+ for (i=0; all_tests[i].name != NULL; i++) {
+ nb_args = all_tests[i].flags & PPC_NB_ARGS_MASK;
+ /* Check number of arguments */
+ if ((nb_args == 1 && !seln_flags.one_arg) ||
+ (nb_args == 2 && !seln_flags.two_args) ||
+ (nb_args == 3 && !seln_flags.three_args) ||
+ (nb_args == 4 && !seln_flags.four_args) ||
+ (nb_args == 5 && !seln_flags.cmp_args) ||
+ (nb_args == 6 && !seln_flags.ld_args) ||
+ (nb_args == 7 && !seln_flags.st_args) ||
+ (nb_args == 8 && !seln_flags.one_imed_args))
+ continue;
+
+ /* Check instruction type */
+ type = all_tests[i].flags & PPC_TYPE_MASK;
+ if ((type == PPC_ARITH && !seln_flags.arith) ||
+ (type == PPC_LDST && !seln_flags.ldst) ||
+ (type == PPC_LOGICAL && !seln_flags.logical) ||
+ (type == PPC_COMPARE && !seln_flags.compare) ||
+ (type == PPC_POPCNT && !seln_flags.compare) ||
+ (type == PPC_INSERTEXTRACT && !seln_flags.insert_extract))
+ continue;
+
+ /* Check instruction family */
+ family = all_tests[i].flags & PPC_FAMILY_MASK;
+
+ /* do each check each case individually to reduce computation */
+ if (family == PPC_INTEGER && seln_flags.integer == 0) continue;
+ if (family == PPC_ALTIVEC && seln_flags.altivec == 0) continue;
+ if (family == PPC_DFP && seln_flags.dfp == 0) continue;
+ if (family == PPC_BCD && seln_flags.bcd == 0) continue;
+ if (family == PPC_NO_OP && seln_flags.no_op == 0) continue;
+ if (family == PPC_MISC && seln_flags.misc == 0) continue;
+ if (family == PPC_ALTIVEC_DOUBLE && seln_flags.altivec_double == 0)
+ continue;
+
+ if (family == PPC_ALTIVEC_QUAD && seln_flags.altivec_quad == 0)
+ continue;
+
+ if (family == PPC_PC_IMMEDIATE && seln_flags.pc_immediate == 0)
+ continue;
+
+ /* Check flags update */
+ if (((all_tests[i].flags & PPC_CR) && seln_flags.cr == 0) ||
+ (!(all_tests[i].flags & PPC_CR) && seln_flags.cr == 1))
+ continue;
+
+ /* All criteria validation passed, do the tests */
+ tests = all_tests[i].tests;
+
+ /* Select the test group */
+ switch (family) {
+ case PPC_INTEGER:
+ switch(type) {
+ case PPC_ARITH:
+ switch(nb_args) {
+ case PPC_TWO_ARGS:
+ group_function = &testfunction_int_two_args;
+ break;
+
+ case PPC_THREE_ARGS:
+ group_function = &testfunction_three_args;
+ break;
+
+ default:
+ printf("ERROR: PPC_INTEGER, unhandled number of arguments. 0x%08x\n",
+ nb_args);
+ }
+ break;
+
+ case PPC_LOGICAL:
+ switch(nb_args) {
+ case PPC_ONE_IMM:
+ group_function = &testfunction_set_boolean;
+ break;
+
+ case PPC_ONE_ARG:
+ group_function = &testfunction_logical_one;
+ break;
+
+ default:
+ printf("ERROR: PPC_LOGICAL, unhandled number of arguments. 0x%08x\n",
+ nb_args);
+ }
+ break;
+
+ case PPC_COMPARE:
+ group_function = &testfunction_char_compare;
+ break;
+
+ default:
+ printf("ERROR: PPC_INTEGER, unhandled type 0x%08x\n", type);
+ continue;
+ } /* switch (type) */
+ break;
+
+ case PPC_ALTIVEC:
+ switch(type) {
+ case PPC_ARITH:
+ switch(nb_args) {
+ case PPC_TWO_ARGS:
+ group_function = &testfunction_vector_absolute;
+
+ break;
+ default:
+ printf("ERROR: PPC_ALTIVEC, PPC_ARITH, unhandled number of arguments. 0x%08x\n", nb_args);
+ continue;
+ } /* switch (PPC_ARITH, nb_args) */
+ break;
+
+ case PPC_LOGICAL:
+ switch(nb_args) {
+ case PPC_ONE_IMM:
+ group_function = &testfunction_vector_immediate;
+ break;
+
+ case PPC_ONE_ARG:
+ group_function = &testfunction_vector_logical_one;
+ break;
+
+ case PPC_TWO_ARGS:
+ group_function = &testfunction_vector_extend_sign;
+ break;
+
+ case PPC_THREE_ARGS:
+ group_function = &testfunction_vector_three_special;
+ break;
+
+ case PPC_FOUR_ARGS:
+ group_function = &testfunction_vector_logical_four;
+ break;
+
+ default:
+ printf("ERROR: PPC_ALTIVEC, PPC_LOGICAL, unhandled number of arguments. 0x%08x\n", nb_args);
+ continue;
+ } /* switch(PPC_INSERTEXTRACT, nb_args) */
+ break;
+
+ case PPC_INSERTEXTRACT:
+ switch(nb_args) {
+ case PPC_ONE_IMM:
+ group_function = &testfunction_vector_insert_or_extract_immediate;
+ break;
+
+ case PPC_TWO_ARGS:
+ group_function = testfunction_vector_extract;
+ break;
+
+ default:
+ printf("ERROR: PPC_ALTIVEC, PPC_INSERTEXTRACT, unhandled number of arguments. 0x%08x\n", nb_args);
+ continue;
+ } /* switch(PPC_INSERTEXTRACT, nb_args) */
+ break;
+
+ case PPC_PERMUTE:
+ group_function = &testfunction_vector_xxpermute;
+ break;
+
+ case PPC_LDST:
+ switch(nb_args) {
+ case PPC_ONE_IMM:
+ /* Register holds immediate length value */
+ group_function = &testfunction_vector_scalar_loadstore_length;
+ break;
+
+ case PPC_TWO_ARGS:
+ /* Register holds address of buffer */
+ group_function = &testfunction_vector_loadstore;
+ break;
+
+ default:
+ printf("ERROR: PPC_ALTIVEC, PPC_LDST, unhandled number of arguments. 0x%08x\n", nb_args);
+ continue;
+ } /* switch(PPC_LDST, nb_args) */
+ break;
+
+ case PPC_POPCNT:
+ group_function = &testfunction_vector_count_bytes;
+ break;
+
+ default:
+ printf("ERROR: PPC_ALTIVEC, unhandled type. %d\n", type);
+ continue;
+ } /* switch (PPC_ALTIVEC, type) */
+ break;
+
+ case PPC_MISC:
+ switch(nb_args) {
+ case PPC_TWO_ARGS:
+ group_function = &testfunction_vectorscalar_move_tofrom;
+ break;
+ case PPC_THREE_ARGS:
+ group_function = &testfunction_one_arg_with_shift;
+ break;
+ default:
+ printf("ERROR: PPC_MISC, unhandled number of arguments. 0x%08x\n", nb_args);
+ continue;
+ } /* switch(PPC_MISC, nb_args) */
+ break;
+
+ case PPC_ALTIVEC_QUAD:
+ switch(type) {
+ case PPC_LOGICAL:
+ switch(nb_args) {
+ case PPC_TWO_ARGS:
+ group_function = &testfunction_vector_scalar_two_quad;
+ break;
+
+ default:
+ printf("ERROR: PPC_ALTIVEC_QUAD, PPC_LOGICAL, unhandled number of arguments. 0x%08x\n", nb_args);
+ continue;
+ } /* switch(PPC_LOGICAL, nb_args) */
+ break;
+
+ case PPC_COMPARE:
+ group_function = &testfunction_vector_scalar_compare_quads;
+ break;
+
+ case PPC_ROUND:
+ group_function = &testfunction_vector_scalar_rounding_quads;
+ break;
+
+ default:
+ printf("ERROR: PPC_ALTIVEC_QUAD, unhandled type. %d\n", type);
+ continue;
+ } /* switch(type) */
+ break;
+
+ case PPC_ALTIVEC_DOUBLE:
+ switch(type) {
+ case PPC_COMPARE:
+ switch(nb_args) {
+ case PPC_ONE_ARG:
+ group_function = &testfunction_vector_scalar_data_class;
+ break;
+
+ case PPC_TWO_ARGS:
+ group_function = &testfunction_vector_scalar_two_double;
+ break;
+
+ case PPC_COMPARE_ARGS:
+ group_function = &testfunction_vector_scalar_compare_exp_double;
+ break;
+
+ default:
+ printf("ERROR: PPC_ALTIVEC_DOUBLE, PPC_COMPARE, unhandled number of arguments. 0x%08x\n", nb_args);
+ continue;
+ } /* switch(PPC_COMPARE, nb_args) */
+ break;
+
+ default:
+ printf("ERROR: PPC_ALTIVEC_DOUBLE, unhandled type. %d\n", type);
+ continue;
+
+ } /* switch(type) */
+ break;
+
+ case PPC_DFP:
+ group_function = &testfunction_dfp_significance;
+ break;
+
+ case PPC_BCD:
+ group_function = &testfunction_bcd_misc;
+ break;
+
+ case PPC_NO_OP:
+ group_function = &testfunction_noop_misc;
+ break;
+
+ case PPC_PC_IMMEDIATE:
+ group_function = &testfunction_pc_immediate_misc;
+ break;
+
+ default:
+ printf("ERROR: unknown instruction family %08x\n", family);
+ continue;
+ } /* switch(family) */
+
+ printf("%s:\n", all_tests[i].name);
+
+ printf("Test instruction group [%s]\n", all_tests[i].name);
+ /* Now, spin through all entries in the group_function to
+ * run the individual instruction tests.
+ */
+ for (j = 0; tests[j].name != NULL; j++) {
+ if (verbose > 1)
+ printf("Test instruction %s\n", tests[j].name);
+ (*group_function)(tests[j].name, tests[j].func, all_tests[i].flags);
+ printf("\n");
+ n++;
+ }
+
+ if (verbose) printf("\n");
+
+ printf("All done. Tested %d different instructions\n", n);
+ } /* for (i = 0; all_tests[i].name...) */
+}
+
+static void usage (void)
+{
+ fprintf(stderr,
+ "Usage: test_isa_3_0 [OPTIONS]\n"
+ "\t-i: test integer instructions (default)\n"
+ "\t-a: test altivec instructions\n"
+ "\t-d: test altivec double instructions\n"
+ "\t-q: test altivec quad instructions\n"
+ "\t-D: test DFP instructions\n"
+ "\t-B: test BCD instructions\n"
+ "\t-N: test No Op instructions\n"
+ "\t-P: test PC Immediate Shifted instructions\n"
+ "\t-m: test miscellaneous instructions\n"
+ "\t-v: be verbose\n"
+ "\t-h: display this help and exit\n"
+ );
+}
+
+#endif // HAS_ISA_3_00
+int main (int argc, char **argv)
+{
+
+#ifndef HAS_ISA_3_00
+ printf("NO ISA 3.00 SUPPORT\n");
+ return 0;
+
+#else
+ insn_sel_flags_t flags;
+ int c;
+
+
+ // Args
+ flags.one_arg = 1;
+ flags.two_args = 1;
+ flags.three_args = 1;
+ flags.four_args = 1;
+ flags.cmp_args = 1;
+ flags.ld_args = 1;
+ flags.st_args = 1;
+ flags.one_imed_args = 1;
+
+ // Type
+ flags.arith = 1;
+ flags.logical = 1;
+ flags.compare = 1;
+ flags.ldst = 1;
+ flags.popcnt = 1;
+ flags.insert_extract = 1;
+ flags.permute = 1;
+ flags.round = 1;
+
+ // Family
+ flags.integer = 0;
+ flags.altivec = 0;
+ flags.altivec_double = 0;
+ flags.altivec_quad = 0;
+ flags.dfp = 0;
+ flags.bcd = 0;
+ flags.misc = 0;
+ flags.no_op = 0;
+ flags.pc_immediate = 0;
+
+ // Flags
+ flags.cr = 2;
+
+ while ((c = getopt(argc, argv, "ifmadqhvADBNP")) != -1) {
+ switch (c) {
+ case 'i':
+ flags.integer = 1;
+ break;
+
+ case 'a':
+ flags.altivec = 1;
+ break;
+
+ case 'd':
+ flags.altivec_double = 1;
+ break;
+
+ case 'q':
+ flags.altivec_quad = 1;
+ break;
+
+ case 'D':
+ flags.dfp = 1;
+ break;
+
+ case 'B':
+ flags.bcd = 1;
+ break;
+
+ case 'm':
+ flags.misc = 1;
+ break;
+
+ case 'N':
+ flags.no_op = 1;
+ break;
+
+ case 'P':
+ flags.pc_immediate = 1;
+ break;
+
+ case 'h':
+ usage();
+ return 0;
+
+ case 'v':
+ verbose++;
+ break;
+
+ default:
+ usage();
+ fprintf(stderr, "Unknown argument: '%c'\n", c);
+ return 1;
+ }
+ }
+
+ build_iargs_table();
+ build_vsx_table();
+ build_float_vsx_tables();
+ build_vector_permute_table();
+ build_char_table();
+ build_char_range_table();
+ build_packed_decimal_table();
+ build_national_decimal_table();
+ build_zoned_decimal_table();
+ build_decimal_shift_table();
+
+ if (verbose>2) {
+ dump_char_table();
+ dump_char_range_table();
+ dump_float_vsx_table();
+ dump_packed_decimal_table();
+ dump_national_decimal_table();
+ dump_zoned_decimal_table();
+ dump_decimal_shift_table();
+ dump_dfp64_table();
+ dump_dfp128_table();
+ }
+
+ if (verbose > 1) {
+ printf("\nInstruction Selection:\n");
+ printf(" n_args: \n");
+ printf(" one_arg = %d\n", flags.one_arg);
+ printf(" two_args = %d\n", flags.two_args);
+ printf(" three_args = %d\n", flags.three_args);
+ printf(" four_args = %d\n", flags.four_args);
+ printf(" cmp_args = %d\n", flags.cmp_args);
+ printf(" load_args = %d\n", flags.ld_args);
+ printf(" store_args = %d\n", flags.st_args);
+ printf(" one_im_args = %d\n", flags.one_imed_args);
+ printf(" type: \n");
+ printf(" arith = %d\n", flags.arith);
+ printf(" logical = %d\n", flags.logical);
+ printf(" popcnt = %d\n", flags.popcnt);
+ printf(" compare = %d\n", flags.compare);
+ printf(" inset/extract = %d\n", flags.insert_extract);
+ printf(" family: \n");
+ printf(" integer = %d\n", flags.integer);
+ printf(" altivec = %d\n", flags.altivec);
+ printf(" altivec double = %d\n", flags.altivec_double);
+ printf(" altivec quad = %d\n", flags.altivec_quad);
+ printf(" DFP = %d\n", flags.dfp);
+ printf(" BCD = %d\n", flags.bcd);
+ printf(" PC immediate shifted = %d\n", flags.pc_immediate);
+ printf(" misc = %d\n", flags.misc);
+ printf(" cr update: \n");
+ printf(" cr = %d\n", flags.cr);
+ printf("\n");
+ printf(" num args: \n");
+ printf(" iargs - %d\n", nb_iargs);
+ printf("\n");
+ }
+
+ do_tests( flags );
+#endif
+
+ return 0;
+}
diff --git a/none/tests/ppc64/test_isa_3_0_altivec.stderr.exp b/none/tests/ppc64/test_isa_3_0_altivec.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/ppc64/test_isa_3_0_altivec.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp
new file mode 100644
index 0000000..408909a
--- /dev/null
+++ b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp
@@ -0,0 +1,56233 @@
+ppc vector absolutes:
+Test instruction group [ppc vector absolutes]
+vabsdub xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vabsdub xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:0102030405060708 0102030405060708 (00000000)
+vabsdub xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0011223344556677 8899aabbccddeeff (00000000)
+vabsdub xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:010f1f2f3f4f5f6f 8797a7b7c7d7e7f7 (00000000)
+vabsdub xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010 (00000000)
+vabsdub xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:01020d0405060906 01020d0405060908 (00000000)
+vabsdub xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10 (00000000)
+vabsdub xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:0102190405061506 0102190405061508 (00000000)
+vabsdub xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10 (00000000)
+vabsdub xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:01021c0405061806 01021c0405061808 (00000000)
+
+vabsduh xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vabsduh xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:0102030405060708 0102030405060708 (00000000)
+vabsduh xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0011223344556677 8899aabbccddeeff (00000000)
+vabsduh xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:00f11f2f3f4f5f6f 8797a7b7c7d7e7f7 (00000000)
+vabsduh xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010 (00000000)
+vabsduh xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:01020cfc050608fa 01020d0405060908 (00000000)
+vabsduh xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10 (00000000)
+vabsduh xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:010218fc050614fa 0102190405061508 (00000000)
+vabsduh xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10 (00000000)
+vabsduh xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:01021bfc050617fa 01021c0405061808 (00000000)
+
+vabsduw xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vabsduw xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:0102030405060708 0102030405060708 (00000000)
+vabsduw xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0011223344556677 8899aabbccddeeff (00000000)
+vabsduw xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:00f0e0d13f4f5f6f 8797a7b7c7d7e7f7 (00000000)
+vabsduw xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010 (00000000)
+vabsduw xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:0101f3040505f706 0101f2fc0505f6f8 (00000000)
+vabsduw xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10 (00000000)
+vabsduw xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:0101e7040505eb06 0101e6fc0505eaf8 (00000000)
+vabsduw xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10 (00000000)
+vabsduw xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:0101e4040505e806 0101e3fc0505e7f8 (00000000)
+
+vcmpneb xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vcmpneb xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:00ffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000ff000000ffff 0000ffff0000ffff (00000000)
+vcmpneb xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:0000ff000000ffff 0000ffff0000ffff (00000000)
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+xviexpsp xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:0200000004000000 0200000004000000 (00000000)
+xviexpsp xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0011223300556677 8019aabb805deeff (00000000)
+xviexpsp xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:0211223304556677 8219aabb845deeff (00000000)
+xviexpsp xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010 (00000000)
+xviexpsp xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:0200100004001002 0200100804001010 (00000000)
+xviexpsp xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10 (00000000)
+xviexpsp xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:02001c0004001c02 02001c0804001c10 (00000000)
+xviexpsp xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10 (00000000)
+xviexpsp xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:02001f0004001f02 02001f0804001f10 (00000000)
+
+All done. Tested 22 different instructions
+ppc vector logical immediate:
+Test instruction group [ppc vector logical immediate]
+xxspltib 0000000000000000 0000000000000000 [ 0] => 0000000000000000 0000000000000000
+xxspltib ffffffffffffffff ffffffffffffffff [ 0] => 0000000000000000 0000000000000000
+xxspltib 0000000000000000 0000000000000000 [ 1] => 0101010101010101 0101010101010101
+xxspltib ffffffffffffffff ffffffffffffffff [ 1] => 0101010101010101 0101010101010101
+xxspltib 0000000000000000 0000000000000000 [aa] => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa
+xxspltib ffffffffffffffff ffffffffffffffff [aa] => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa
+xxspltib 0000000000000000 0000000000000000 [55] => 5555555555555555 5555555555555555
+xxspltib ffffffffffffffff ffffffffffffffff [55] => 5555555555555555 5555555555555555
+xxspltib 0000000000000000 0000000000000000 [ff] => ffffffffffffffff ffffffffffffffff
+xxspltib ffffffffffffffff ffffffffffffffff [ff] => ffffffffffffffff ffffffffffffffff
+
+All done. Tested 23 different instructions
+ppc vector logical one:
+Test instruction group [ppc vector logical one]
+xxbrh xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xxbrh xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xxbrh xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0201040306050807 0201020102010201
+xxbrh xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0201040306050807 0201020102010201
+xxbrh xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:1100332255447766 9988bbaaddccffee
+xxbrh xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:1100332255447766 9988bbaaddccffee
+xxbrh xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:e0f0c0d0a0b08090 6070405020300010
+xxbrh xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:e0f0c0d0a0b08090 6070405020300010
+xxbrh xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000001000000210 0000081000001010
+xxbrh xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000001000000210 0000081000001010
+xxbrh xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:1000001010000210 1000081010001010
+xxbrh xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:1000001010000210 1000081010001010
+xxbrh xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:0000001c0000021c 0000081c0000101c
+xxbrh xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:0000001c0000021c 0000081c0000101c
+xxbrh xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:1000001c1000021c 1000081c1000101c
+xxbrh xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:1000001c1000021c 1000081c1000101c
+xxbrh xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:0000001f0000021f 0000081f0000101f
+xxbrh xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:0000001f0000021f 0000081f0000101f
+xxbrh xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:1000001f1000021f 1000081f1000101f
+xxbrh xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:1000001f1000021f 1000081f1000101f
+
+xxbrw xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xxbrw xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xxbrw xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0403020108070605 0201020102010201
+xxbrw xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0403020108070605 0201020102010201
+xxbrw xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:3322110077665544 bbaa9988ffeeddcc
+xxbrw xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:3322110077665544 bbaa9988ffeeddcc
+xxbrw xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:c0d0e0f08090a0b0 4050607000102030
+xxbrw xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:c0d0e0f08090a0b0 4050607000102030
+xxbrw xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0010000002100000 0810000010100000
+xxbrw xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0010000002100000 0810000010100000
+xxbrw xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0010100002101000 0810100010101000
+xxbrw xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0010100002101000 0810100010101000
+xxbrw xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:001c0000021c0000 081c0000101c0000
+xxbrw xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:001c0000021c0000 081c0000101c0000
+xxbrw xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:001c1000021c1000 081c1000101c1000
+xxbrw xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:001c1000021c1000 081c1000101c1000
+xxbrw xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:001f0000021f0000 081f0000101f0000
+xxbrw xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:001f0000021f0000 081f0000101f0000
+xxbrw xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:001f1000021f1000 081f1000101f1000
+xxbrw xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:001f1000021f1000 081f1000101f1000
+
+xxbrd xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xxbrd xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xxbrd xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0807060504030201 0201020102010201
+xxbrd xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0807060504030201 0201020102010201
+xxbrd xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:7766554433221100 ffeeddccbbaa9988
+xxbrd xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:7766554433221100 ffeeddccbbaa9988
+xxbrd xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:8090a0b0c0d0e0f0 0010203040506070
+xxbrd xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:8090a0b0c0d0e0f0 0010203040506070
+xxbrd xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0210000000100000 1010000008100000
+xxbrd xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0210000000100000 1010000008100000
+xxbrd xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0210100000101000 1010100008101000
+xxbrd xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0210100000101000 1010100008101000
+xxbrd xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:021c0000001c0000 101c0000081c0000
+xxbrd xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:021c0000001c0000 101c0000081c0000
+xxbrd xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:021c1000001c1000 101c1000081c1000
+xxbrd xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:021c1000001c1000 101c1000081c1000
+xxbrd xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:021f0000001f0000 101f0000081f0000
+xxbrd xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:021f0000001f0000 101f0000081f0000
+xxbrd xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:021f1000001f1000 101f1000081f1000
+xxbrd xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:021f1000001f1000 101f1000081f1000
+
+xxbrq xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xxbrq xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xxbrq xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0201020102010201 0807060504030201
+xxbrq xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0201020102010201 0807060504030201
+xxbrq xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:ffeeddccbbaa9988 7766554433221100
+xxbrq xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:ffeeddccbbaa9988 7766554433221100
+xxbrq xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:0010203040506070 8090a0b0c0d0e0f0
+xxbrq xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:0010203040506070 8090a0b0c0d0e0f0
+xxbrq xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:1010000008100000 0210000000100000
+xxbrq xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:1010000008100000 0210000000100000
+xxbrq xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:1010100008101000 0210100000101000
+xxbrq xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:1010100008101000 0210100000101000
+xxbrq xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:101c0000081c0000 021c0000001c0000
+xxbrq xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:101c0000081c0000 021c0000001c0000
+xxbrq xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:101c1000081c1000 021c1000001c1000
+xxbrq xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:101c1000081c1000 021c1000001c1000
+xxbrq xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:101f0000081f0000 021f0000001f0000
+xxbrq xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:101f0000081f0000 021f0000001f0000
+xxbrq xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:101f1000081f1000 021f1000001f1000
+xxbrq xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:101f1000081f1000 021f1000001f1000
+
+xvxexpdp xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpdp xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpdp xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0000000000000010 0000000000000010
+xvxexpdp xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000010 0000000000000010
+xvxexpdp xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:0000000000000001 0000000000000089
+xvxexpdp xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000001 0000000000000089
+xvxexpdp xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:000000000000070e 0000000000000706
+xvxexpdp xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:000000000000070e 0000000000000706
+xvxexpdp xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpdp xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpdp xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0000000000000001 0000000000000001
+xvxexpdp xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000001 0000000000000001
+xvxexpdp xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpdp xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpdp xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:0000000000000001 0000000000000001
+xvxexpdp xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000001 0000000000000001
+xvxexpdp xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpdp xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpdp xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:0000000000000001 0000000000000001
+xvxexpdp xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000001 0000000000000001
+
+xvxexpsp xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:000000020000000a 0000000200000002
+xvxexpsp xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:000000020000000a 0000000200000002
+xvxexpsp xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:0000000000000088 0000001100000099
+xvxexpsp xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000088 0000001100000099
+xvxexpsp xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:000000e100000061 000000e000000060
+xvxexpsp xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:000000e100000061 000000e000000060
+xvxexpsp xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+
+xvxsigdp xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxsigdp xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxsigdp xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0012030405060708 0012010201020102
+xvxsigdp xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0012030405060708 0012010201020102
+xvxsigdp xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:0011223344556677 0019aabbccddeeff
+xvxsigdp xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:0011223344556677 0019aabbccddeeff
+xvxsigdp xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:0010d0c0b0a09080 0010504030201000
+xvxsigdp xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:0010d0c0b0a09080 0010504030201000
+xvxsigdp xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010
+xvxsigdp xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000100000001002 0000100800001010
+xvxsigdp xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0010100000101002 0010100800101010
+xvxsigdp xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0010100000101002 0010100800101010
+xvxsigdp xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10
+xvxsigdp xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:00001c0000001c02 00001c0800001c10
+xvxsigdp xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:00101c0000101c02 00101c0800101c10
+xvxsigdp xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:00101c0000101c02 00101c0800101c10
+xvxsigdp xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10
+xvxsigdp xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:00001f0000001f02 00001f0800001f10
+xvxsigdp xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:00101f0000101f02 00101f0800101f10
+xvxsigdp xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:00101f0000101f02 00101f0800101f10
+
+xvxsigsp xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxsigsp xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxsigsp xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0082030400860708 0082010200820102
+xvxsigsp xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0082030400860708 0082010200820102
+xvxsigsp xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:0011223300d56677 0099aabb00ddeeff
+xvxsigsp xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:0011223300d56677 0099aabb00ddeeff
+xvxsigsp xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:00e0d0c000a09080 00e0504000a01000
+xvxsigsp xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:00e0d0c000a09080 00e0504000a01000
+xvxsigsp xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010
+xvxsigsp xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000100000001002 0000100800001010
+xvxsigsp xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0010100000101002 0010100800101010
+xvxsigsp xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0010100000101002 0010100800101010
+xvxsigsp xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10
+xvxsigsp xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:00001c0000001c02 00001c0800001c10
+xvxsigsp xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:00101c0000101c02 00101c0800101c10
+xvxsigsp xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:00101c0000101c02 00101c0800101c10
+xvxsigsp xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10
+xvxsigsp xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:00001f0000001f02 00001f0800001f10
+xvxsigsp xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:00101f0000101f02 00101f0800101f10
+xvxsigsp xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:00101f0000101f02 00101f0800101f10
+
+xsxexpdp xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xsxexpdp xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xsxexpdp xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0102030405060708 0102010201020102
+xsxexpdp xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0102030405060708 0102010201020102
+xsxexpdp xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:0011223344556677 8899aabbccddeeff
+xsxexpdp xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:0011223344556677 8899aabbccddeeff
+xsxexpdp xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:f0e0d0c0b0a09080 7060504030201000
+xsxexpdp xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:f0e0d0c0b0a09080 7060504030201000
+xsxexpdp xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010
+xsxexpdp xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000100000001002 0000100800001010
+xsxexpdp xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0010100000101002 0010100800101010
+xsxexpdp xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0010100000101002 0010100800101010
+xsxexpdp xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10
+xsxexpdp xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:00001c0000001c02 00001c0800001c10
+xsxexpdp xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:00101c0000101c02 00101c0800101c10
+xsxexpdp xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:00101c0000101c02 00101c0800101c10
+xsxexpdp xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10
+xsxexpdp xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:00001f0000001f02 00001f0800001f10
+xsxexpdp xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:00101f0000101f02 00101f0800101f10
+xsxexpdp xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:00101f0000101f02 00101f0800101f10
+
+xsxsigdp xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xsxsigdp xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xsxsigdp xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0102030405060708 0102010201020102
+xsxsigdp xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0102030405060708 0102010201020102
+xsxsigdp xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:0011223344556677 8899aabbccddeeff
+xsxsigdp xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:0011223344556677 8899aabbccddeeff
+xsxsigdp xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:f0e0d0c0b0a09080 7060504030201000
+xsxsigdp xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:f0e0d0c0b0a09080 7060504030201000
+xsxsigdp xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010
+xsxsigdp xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000100000001002 0000100800001010
+xsxsigdp xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0010100000101002 0010100800101010
+xsxsigdp xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0010100000101002 0010100800101010
+xsxsigdp xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10
+xsxsigdp xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:00001c0000001c02 00001c0800001c10
+xsxsigdp xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:00101c0000101c02 00101c0800101c10
+xsxsigdp xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:00101c0000101c02 00101c0800101c10
+xsxsigdp xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10
+xsxsigdp xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:00001f0000001f02 00001f0800001f10
+xsxsigdp xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:00101f0000101f02 00101f0800101f10
+xsxsigdp xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:00101f0000101f02 00101f0800101f10
+
+All done. Tested 33 different instructions
+ppc vector extend sign:
+Test instruction group [ppc vector extend sign]
+vextsb2w 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vextsb2w 0102010201020102 0102030405060708 => 0000000200000002 0000000400000008
+vextsb2w 8899aabbccddeeff 0011223344556677 => ffffffbbffffffff 0000003300000077
+vextsb2w 7060504030201000 f0e0d0c0b0a09080 => 0000004000000000 ffffffc0ffffff80
+vextsb2w 0000100800001010 0000100000001002 => 0000000800000010 0000000000000002
+vextsb2w 0010100800101010 0010100000101002 => 0000000800000010 0000000000000002
+vextsb2w 00001c0800001c10 00001c0000001c02 => 0000000800000010 0000000000000002
+vextsb2w 00101c0800101c10 00101c0000101c02 => 0000000800000010 0000000000000002
+vextsb2w 00001f0800001f10 00001f0000001f02 => 0000000800000010 0000000000000002
+vextsb2w 00101f0800101f10 00101f0000101f02 => 0000000800000010 0000000000000002
+
+vextsb2d 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vextsb2d 0102010201020102 0102030405060708 => 0000000000000002 0000000000000008
+vextsb2d 8899aabbccddeeff 0011223344556677 => ffffffffffffffff 0000000000000077
+vextsb2d 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 ffffffffffffff80
+vextsb2d 0000100800001010 0000100000001002 => 0000000000000010 0000000000000002
+vextsb2d 0010100800101010 0010100000101002 => 0000000000000010 0000000000000002
+vextsb2d 00001c0800001c10 00001c0000001c02 => 0000000000000010 0000000000000002
+vextsb2d 00101c0800101c10 00101c0000101c02 => 0000000000000010 0000000000000002
+vextsb2d 00001f0800001f10 00001f0000001f02 => 0000000000000010 0000000000000002
+vextsb2d 00101f0800101f10 00101f0000101f02 => 0000000000000010 0000000000000002
+
+vextsh2w 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vextsh2w 0102010201020102 0102030405060708 => 0000010200000102 0000030400000708
+vextsh2w 8899aabbccddeeff 0011223344556677 => ffffaabbffffeeff 0000223300006677
+vextsh2w 7060504030201000 f0e0d0c0b0a09080 => 0000504000001000 ffffd0c0ffff9080
+vextsh2w 0000100800001010 0000100000001002 => 0000100800001010 0000100000001002
+vextsh2w 0010100800101010 0010100000101002 => 0000100800001010 0000100000001002
+vextsh2w 00001c0800001c10 00001c0000001c02 => 00001c0800001c10 00001c0000001c02
+vextsh2w 00101c0800101c10 00101c0000101c02 => 00001c0800001c10 00001c0000001c02
+vextsh2w 00001f0800001f10 00001f0000001f02 => 00001f0800001f10 00001f0000001f02
+vextsh2w 00101f0800101f10 00101f0000101f02 => 00001f0800001f10 00001f0000001f02
+
+vextsh2d 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vextsh2d 0102010201020102 0102030405060708 => 0000000000000102 0000000000000708
+vextsh2d 8899aabbccddeeff 0011223344556677 => ffffffffffffeeff 0000000000006677
+vextsh2d 7060504030201000 f0e0d0c0b0a09080 => 0000000000001000 ffffffffffff9080
+vextsh2d 0000100800001010 0000100000001002 => 0000000000001010 0000000000001002
+vextsh2d 0010100800101010 0010100000101002 => 0000000000001010 0000000000001002
+vextsh2d 00001c0800001c10 00001c0000001c02 => 0000000000001c10 0000000000001c02
+vextsh2d 00101c0800101c10 00101c0000101c02 => 0000000000001c10 0000000000001c02
+vextsh2d 00001f0800001f10 00001f0000001f02 => 0000000000001f10 0000000000001f02
+vextsh2d 00101f0800101f10 00101f0000101f02 => 0000000000001f10 0000000000001f02
+
+vextsw2d 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vextsw2d 0102010201020102 0102030405060708 => 0000000001020102 0000000005060708
+vextsw2d 8899aabbccddeeff 0011223344556677 => ffffffffccddeeff 0000000044556677
+vextsw2d 7060504030201000 f0e0d0c0b0a09080 => 0000000030201000 ffffffffb0a09080
+vextsw2d 0000100800001010 0000100000001002 => 0000000000001010 0000000000001002
+vextsw2d 0010100800101010 0010100000101002 => 0000000000101010 0000000000101002
+vextsw2d 00001c0800001c10 00001c0000001c02 => 0000000000001c10 0000000000001c02
+vextsw2d 00101c0800101c10 00101c0000101c02 => 0000000000101c10 0000000000101c02
+vextsw2d 00001f0800001f10 00001f0000001f02 => 0000000000001f10 0000000000001f02
+vextsw2d 00101f0800101f10 00101f0000101f02 => 0000000000101f10 0000000000101f02
+
+vnegw 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vnegw 0102010201020102 0102030405060708 => fefdfefefefdfefe fefdfcfcfaf9f8f8
+vnegw 8899aabbccddeeff 0011223344556677 => 7766554533221101 ffeeddcdbbaa9989
+vnegw 7060504030201000 f0e0d0c0b0a09080 => 8f9fafc0cfdff000 0f1f2f404f5f6f80
+vnegw 0000100800001010 0000100000001002 => ffffeff8ffffeff0 fffff000ffffeffe
+vnegw 0010100800101010 0010100000101002 => ffefeff8ffefeff0 ffeff000ffefeffe
+vnegw 00001c0800001c10 00001c0000001c02 => ffffe3f8ffffe3f0 ffffe400ffffe3fe
+vnegw 00101c0800101c10 00101c0000101c02 => ffefe3f8ffefe3f0 ffefe400ffefe3fe
+vnegw 00001f0800001f10 00001f0000001f02 => ffffe0f8ffffe0f0 ffffe100ffffe0fe
+vnegw 00101f0800101f10 00101f0000101f02 => ffefe0f8ffefe0f0 ffefe100ffefe0fe
+
+vnegd 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vnegd 0102010201020102 0102030405060708 => fefdfefdfefdfefe fefdfcfbfaf9f8f8
+vnegd 8899aabbccddeeff 0011223344556677 => 7766554433221101 ffeeddccbbaa9989
+vnegd 7060504030201000 f0e0d0c0b0a09080 => 8f9fafbfcfdff000 0f1f2f3f4f5f6f80
+vnegd 0000100800001010 0000100000001002 => ffffeff7ffffeff0 ffffefffffffeffe
+vnegd 0010100800101010 0010100000101002 => ffefeff7ffefeff0 ffefefffffefeffe
+vnegd 00001c0800001c10 00001c0000001c02 => ffffe3f7ffffe3f0 ffffe3ffffffe3fe
+vnegd 00101c0800101c10 00101c0000101c02 => ffefe3f7ffefe3f0 ffefe3ffffefe3fe
+vnegd 00001f0800001f10 00001f0000001f02 => ffffe0f7ffffe0f0 ffffe0ffffffe0fe
+vnegd 00101f0800101f10 00101f0000101f02 => ffefe0f7ffefe0f0 ffefe0ffffefe0fe
+
+vprtybw 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vprtybw 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+vprtybw 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+vprtybw 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 0000000000000000
+vprtybw 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+vprtybw 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+vprtybw 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+vprtybw 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+vprtybw 00001f0800001f10 00001f0000001f02 => 0000000100000001 0000000100000001
+vprtybw 00101f0800101f10 00101f0000101f02 => 0000000100000001 0000000100000001
+
+vprtybd 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vprtybd 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+vprtybd 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+vprtybd 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 0000000000000000
+vprtybd 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+vprtybd 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+vprtybd 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+vprtybd 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+vprtybd 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+vprtybd 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+vprtybq 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vprtybq 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+vprtybq 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+vprtybq 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 0000000000000000
+vprtybq 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+vprtybq 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+vprtybq 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+vprtybq 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+vprtybq 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+vprtybq 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+vctzb 0000000000000000 0000000000000000 => 0808080808080808 0808080808080808
+vctzb 0102010201020102 0102030405060708 => 0001000100010001 0001000200010003
+vctzb 8899aabbccddeeff 0011223344556677 => 0300010002000100 0800010002000100
+vctzb 7060504030201000 f0e0d0c0b0a09080 => 0405040604050408 0405040604050407
+vctzb 0000100800001010 0000100000001002 => 0808040308080404 0808040808080401
+vctzb 0010100800101010 0010100000101002 => 0804040308040404 0804040808040401
+vctzb 00001c0800001c10 00001c0000001c02 => 0808020308080204 0808020808080201
+vctzb 00101c0800101c10 00101c0000101c02 => 0804020308040204 0804020808040201
+vctzb 00001f0800001f10 00001f0000001f02 => 0808000308080004 0808000808080001
+vctzb 00101f0800101f10 00101f0000101f02 => 0804000308040004 0804000808040001
+
+vctzh 0000000000000000 0000000000000000 => 0010001000100010 0010001000100010
+vctzh 0102010201020102 0102030405060708 => 0001000100010001 0001000200010003
+vctzh 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+vctzh 7060504030201000 f0e0d0c0b0a09080 => 000500060005000c 0005000600050007
+vctzh 0000100800001010 0000100000001002 => 0010000300100004 0010000c00100001
+vctzh 0010100800101010 0010100000101002 => 0004000300040004 0004000c00040001
+vctzh 00001c0800001c10 00001c0000001c02 => 0010000300100004 0010000a00100001
+vctzh 00101c0800101c10 00101c0000101c02 => 0004000300040004 0004000a00040001
+vctzh 00001f0800001f10 00001f0000001f02 => 0010000300100004 0010000800100001
+vctzh 00101f0800101f10 00101f0000101f02 => 0004000300040004 0004000800040001
+
+vctzw 0000000000000000 0000000000000000 => 0000002000000020 0000002000000020
+vctzw 0102010201020102 0102030405060708 => 0000000100000001 0000000200000003
+vctzw 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+vctzw 7060504030201000 f0e0d0c0b0a09080 => 000000060000000c 0000000600000007
+vctzw 0000100800001010 0000100000001002 => 0000000300000004 0000000c00000001
+vctzw 0010100800101010 0010100000101002 => 0000000300000004 0000000c00000001
+vctzw 00001c0800001c10 00001c0000001c02 => 0000000300000004 0000000a00000001
+vctzw 00101c0800101c10 00101c0000101c02 => 0000000300000004 0000000a00000001
+vctzw 00001f0800001f10 00001f0000001f02 => 0000000300000004 0000000800000001
+vctzw 00101f0800101f10 00101f0000101f02 => 0000000300000004 0000000800000001
+
+vctzd 0000000000000000 0000000000000000 => 0000000000000040 0000000000000040
+vctzd 0102010201020102 0102030405060708 => 0000000000000001 0000000000000003
+vctzd 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+vctzd 7060504030201000 f0e0d0c0b0a09080 => 000000000000000c 0000000000000007
+vctzd 0000100800001010 0000100000001002 => 0000000000000004 0000000000000001
+vctzd 0010100800101010 0010100000101002 => 0000000000000004 0000000000000001
+vctzd 00001c0800001c10 00001c0000001c02 => 0000000000000004 0000000000000001
+vctzd 00101c0800101c10 00101c0000101c02 => 0000000000000004 0000000000000001
+vctzd 00001f0800001f10 00001f0000001f02 => 0000000000000004 0000000000000001
+vctzd 00101f0800101f10 00101f0000101f02 => 0000000000000004 0000000000000001
+
+All done. Tested 47 different instructions
+ppc vector three quad:
+Test instruction group [ppc vector three quad]
+xsaddqp 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
+xsaddqp 00000000000000000000000000000000 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
+xsaddqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 00000000000000000000000000000000 => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000007fffffffffff 00000000000000000000000000000000 => 000000000000000000007fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000000007fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff0000000000000000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff000000000000 00000000000000000000000000000000 => 000000000000000000ff000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000ff000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 000000000000000000ff7fffffffffff FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000000ff7fffffffffff FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff000000000000 00000000000000000000000000000000 => 000000000000000007ff000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000007ff000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 000000000000000007ff7fffffffffff FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000007ff7fffffffffff FPCC-FG
+xsaddqp 00000000000000000000000000000000 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00000000000000007fff000000000000 00000000000000000000000000000000 => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsaddqp 00000000000000000000000000000000 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsaddqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7fff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsaddqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsaddqp 00000000000000000000000000000000 80000000000000000000000000000000 00000000000000000000000000000000 => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00000000000000008000000000000000 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
+xsaddqp 00000000000000000000000000000000 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
+xsaddqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 80007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000080007fffffffffff 00000000000000000000000000000000 => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsaddqp 00000000000000000000000000000000 80ff0000000000000000000000000000 00000000000000000000000000000000 => 80ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => 000000000000000080ff000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000080ff000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 000000000000000080ff7fffffffffff FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080ff7fffffffffff FPCC-FL
+xsaddqp 00000000000000000000000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => 87ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => 000000000000000087ff000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000087ff000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 87ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 000000000000000087ff7fffffffffff FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000087ff7fffffffffff FPCC-FL
+xsaddqp 00000000000000000000000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => ffff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsaddqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 00000000000000000000000000000000 => 0000fffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000fffffffffffe0000000000000000 FPRF-C FPCC-FG
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+xsaddqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
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+xsaddqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
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+xssubqpo 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 80000000000000000000000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 00000000000000008000000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 000000000000000080007fffffffffff 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 80ff0000000000000000000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => 00000000000000007fff800000000000 FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007fff800000000000 FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 => ffff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 00000000000000000000000000000000 => ffff0000000000000000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffff0000000000000000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff 00000000000000000000000000000000 => 000080000000000180007ffffffffffe FPRF-C FPCC-FL
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 000080000000000180007ffffffffffe FPRF-C FPCC-FL
+xssubqpo ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 00000000000000000000000000000000 => ff007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ff007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 00000000000000000000000000000000 => ffffffffffffffff80feffffffffffff FPCC-FL
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff80feffffffffffff FPCC-FL
+xssubqpo ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => ff000000000000000000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ff000000000000000000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => ffffffffffffffff80ff7ffffffffffe FPCC-FL
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => ffffffffffffffff80ff7ffffffffffe FPCC-FL
+xssubqpo ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 00000000000000000000000000000000 => f8007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => f8007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 00000000000000000000000000000000 => ffffffffffffffff87feffffffffffff FPCC-FL
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff87feffffffffffff FPCC-FL
+xssubqpo ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => f8000000000000000000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => f8000000000000000000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => ffffffffffffffff87ff7ffffffffffe FPCC-FL
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => ffffffffffffffff87ff7ffffffffffe FPCC-FL
+xssubqpo ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 00000000000000000000000000000000 => 80007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 80000000000000000000000000000000 00000000000000000000000000000000 => 7fff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000008000000000000000 00000000000000000000000000000000 => ffff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => ffff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff 00000000000000000000000000000000 => ffff7fffffffffff00007fffffffffff FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => ffff7fffffffffff00007fffffffffff FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 00000000000000000000000000000000 => 7f007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7f007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => 000000000000000100ff000000000000 FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000100ff000000000000 FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7f000000000000000000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7f000000000000000000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 000000000000000100ff7fffffffffff FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000100ff7fffffffffff FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => 78007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 78007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => 000000000000000107ff000000000000 FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000107ff000000000000 FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 78000000000000000000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 78000000000000000000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 000000000000000107ff7fffffffffff FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000107ff7fffffffffff FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xssubqpo ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
+xssubqpo ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
+xssubqpo ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+
+All done. Tested 65 different instructions
+ppc vector scalar quad:
+Test instruction group [ppc vector scalar quad]
+xsabsqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xsabsqp 0102010201020102 0102030405060708 => 0102010201020102 0102030405060708
+xsabsqp 8899aabbccddeeff 0011223344556677 => 8899aabbccddeeff 0011223344556677
+xsabsqp 7060504030201000 f0e0d0c0b0a09080 => 7060504030201000 70e0d0c0b0a09080
+xsabsqp 0000100800001010 0000100000001002 => 0000100800001010 0000100000001002
+xsabsqp 0010100800101010 0010100000101002 => 0010100800101010 0010100000101002
+xsabsqp 00001c0800001c10 00001c0000001c02 => 00001c0800001c10 00001c0000001c02
+xsabsqp 00101c0800101c10 00101c0000101c02 => 00101c0800101c10 00101c0000101c02
+xsabsqp 00001f0800001f10 00001f0000001f02 => 00001f0800001f10 00001f0000001f02
+xsabsqp 00101f0800101f10 00101f0000101f02 => 00101f0800101f10 00101f0000101f02
+
+xscvdpqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvdpqp 0102010201020102 0102030405060708 => 8000000000000000 3c10203040506070 FPCC-FG
+xscvdpqp 8899aabbccddeeff 0011223344556677 => 7000000000000000 3c01122334455667 FPCC-FG
+xscvdpqp 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 c30e0d0c0b0a0908 FPCC-FL
+xscvdpqp 0000100800001010 0000100000001002 => 0000000000000000 3bf9000000010020 FPCC-FG
+xscvdpqp 0010100800101010 0010100000101002 => 2000000000000000 3c01010000010100 FPCC-FG
+xscvdpqp 00001c0800001c10 00001c0000001c02 => 0000000000000000 3bf9c0000001c020 FPCC-FG
+xscvdpqp 00101c0800101c10 00101c0000101c02 => 2000000000000000 3c0101c0000101c0 FPCC-FG
+xscvdpqp 00001f0800001f10 00001f0000001f02 => 0000000000000000 3bf9f0000001f020 FPCC-FG
+xscvdpqp 00101f0800101f10 00101f0000101f02 => 2000000000000000 3c0101f0000101f0 FPCC-FG
+
+xscvqpdp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 fff0000000000000 FPCC-FL FPCC-FU
+xscvqpdp 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000 FPCC-FE
+
+xscvqpdpo 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdpo 0102010201020102 0102030405060708 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+xscvqpdpo 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+xscvqpdpo 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 ffefffffffffffff FPCC-FL
+xscvqpdpo 0000100800001010 0000100000001002 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+xscvqpdpo 0010100800101010 0010100000101002 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+xscvqpdpo 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+xscvqpdpo 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+xscvqpdpo 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+xscvqpdpo 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+
+xscvqpsdz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpsdz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpsdz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpsdz 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 8000000000000000
+xscvqpsdz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpsdz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpsdz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpsdz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpsdz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpsdz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvqpswz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpswz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpswz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpswz 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 ffffffff80000000
+xscvqpswz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpswz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpswz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpswz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpswz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpswz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvqpudz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpudz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpudz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpudz 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 0000000000000000
+xscvqpudz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpudz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpudz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpudz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpudz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpudz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvqpuwz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpuwz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpuwz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpuwz 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 0000000000000000
+xscvqpuwz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpuwz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpuwz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpuwz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpuwz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpuwz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvsdqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvsdqp 0102010201020102 0102030405060708 => 0800000000000000 4037020304050607 FPCC-FG
+xscvsdqp 8899aabbccddeeff 0011223344556677 => 7000000000000000 4033122334455667 FPCC-FG
+xscvsdqp 7060504030201000 f0e0d0c0b0a09080 => f000000000000000 c03ae3e5e7e9ebed FPCC-FL
+xscvsdqp 0000100800001010 0000100000001002 => 0000000000000000 402b000000010020 FPCC-FG
+xscvsdqp 0010100800101010 0010100000101002 => 2000000000000000 4033010000010100 FPCC-FG
+xscvsdqp 00001c0800001c10 00001c0000001c02 => 0000000000000000 402bc0000001c020 FPCC-FG
+xscvsdqp 00101c0800101c10 00101c0000101c02 => 2000000000000000 403301c0000101c0 FPCC-FG
+xscvsdqp 00001f0800001f10 00001f0000001f02 => 0000000000000000 402bf0000001f020 FPCC-FG
+xscvsdqp 00101f0800101f10 00101f0000101f02 => 2000000000000000 403301f0000101f0 FPCC-FG
+
+xscvudqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvudqp 0102010201020102 0102030405060708 => 0800000000000000 4037020304050607 FPCC-FG
+xscvudqp 8899aabbccddeeff 0011223344556677 => 7000000000000000 4033122334455667 FPCC-FG
+xscvudqp 7060504030201000 f0e0d0c0b0a09080 => 2100000000000000 403ee1c1a1816141 FPCC-FG
+xscvudqp 0000100800001010 0000100000001002 => 0000000000000000 402b000000010020 FPCC-FG
+xscvudqp 0010100800101010 0010100000101002 => 2000000000000000 4033010000010100 FPCC-FG
+xscvudqp 00001c0800001c10 00001c0000001c02 => 0000000000000000 402bc0000001c020 FPCC-FG
+xscvudqp 00101c0800101c10 00101c0000101c02 => 2000000000000000 403301c0000101c0 FPCC-FG
+xscvudqp 00001f0800001f10 00001f0000001f02 => 0000000000000000 402bf0000001f020 FPCC-FG
+xscvudqp 00101f0800101f10 00101f0000101f02 => 2000000000000000 403301f0000101f0 FPCC-FG
+
+xsxexpqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xsxexpqp 0102010201020102 0102030405060708 => 0000000000000000 0000000000000102
+xsxexpqp 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000011
+xsxexpqp 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 00000000000070e0
+xsxexpqp 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xsxexpqp 0010100800101010 0010100000101002 => 0000000000000000 0000000000000010
+xsxexpqp 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xsxexpqp 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000010
+xsxexpqp 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xsxexpqp 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000010
+
+xsxsigqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xsxsigqp 0102010201020102 0102030405060708 => 0102010201020102 0001030405060708
+xsxsigqp 8899aabbccddeeff 0011223344556677 => 8899aabbccddeeff 0001223344556677
+xsxsigqp 7060504030201000 f0e0d0c0b0a09080 => 7060504030201000 0001d0c0b0a09080
+xsxsigqp 0000100800001010 0000100000001002 => 0000100800001010 0000100000001002
+xsxsigqp 0010100800101010 0010100000101002 => 0010100800101010 0001100000101002
+xsxsigqp 00001c0800001c10 00001c0000001c02 => 00001c0800001c10 00001c0000001c02
+xsxsigqp 00101c0800101c10 00101c0000101c02 => 00101c0800101c10 00011c0000101c02
+xsxsigqp 00001f0800001f10 00001f0000001f02 => 00001f0800001f10 00001f0000001f02
+xsxsigqp 00101f0800101f10 00101f0000101f02 => 00101f0800101f10 00011f0000101f02
+
+xsnegqp 0000000000000000 0000000000000000 => 0000000000000000 8000000000000000
+xsnegqp 0102010201020102 0102030405060708 => 0102010201020102 8102030405060708
+xsnegqp 8899aabbccddeeff 0011223344556677 => 8899aabbccddeeff 8011223344556677
+xsnegqp 7060504030201000 f0e0d0c0b0a09080 => 7060504030201000 70e0d0c0b0a09080
+xsnegqp 0000100800001010 0000100000001002 => 0000100800001010 8000100000001002
+xsnegqp 0010100800101010 0010100000101002 => 0010100800101010 8010100000101002
+xsnegqp 00001c0800001c10 00001c0000001c02 => 00001c0800001c10 80001c0000001c02
+xsnegqp 00101c0800101c10 00101c0000101c02 => 00101c0800101c10 80101c0000101c02
+xsnegqp 00001f0800001f10 00001f0000001f02 => 00001f0800001f10 80001f0000001f02
+xsnegqp 00101f0800101f10 00101f0000101f02 => 00101f0800101f10 80101f0000101f02
+
+xsnabsqp 0000000000000000 0000000000000000 => 0000000000000000 8000000000000000
+xsnabsqp 0102010201020102 0102030405060708 => 0102010201020102 8102030405060708
+xsnabsqp 8899aabbccddeeff 0011223344556677 => 8899aabbccddeeff 8011223344556677
+xsnabsqp 7060504030201000 f0e0d0c0b0a09080 => 7060504030201000 f0e0d0c0b0a09080
+xsnabsqp 0000100800001010 0000100000001002 => 0000100800001010 8000100000001002
+xsnabsqp 0010100800101010 0010100000101002 => 0010100800101010 8010100000101002
+xsnabsqp 00001c0800001c10 00001c0000001c02 => 00001c0800001c10 80001c0000001c02
+xsnabsqp 00101c0800101c10 00101c0000101c02 => 00101c0800101c10 80101c0000101c02
+xsnabsqp 00001f0800001f10 00001f0000001f02 => 00001f0800001f10 80001f0000001f02
+xsnabsqp 00101f0800101f10 00101f0000101f02 => 00101f0800101f10 80101f0000101f02
+
+xssqrtqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xssqrtqp 0102010201020102 0102030405060708 => 464bd73a50214d13 20806c2a33b95561 FPCC-FG
+xssqrtqp 8899aabbccddeeff 0011223344556677 => dc52638df54a24e2 200810907245f32e FPCC-FG
+xssqrtqp 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 7fff800000000000 FPRF-C FPCC-FU
+xssqrtqp 0000100800001010 0000100000001002 => 00006037ff80505e 1ffe000000008010 FPCC-FG
+xssqrtqp 0010100800101010 0010100000101002 => 830aae4bdadf703a 2007752e50e63f0a FPCC-FG
+xssqrtqp 00001c0800001c10 00001c0000001c02 => b110f1988f82fedd 1ffe52a7fa9dd8ee FPCC-FG
+xssqrtqp 00101c0800101c10 00101c0000101c02 => 77d067a08499cf9c 20077d52f24f5140 FPCC-FG
+xssqrtqp 00001f0800001f10 00001f0000001f02 => d618e68f6c3361e0 1ffe645640573e52 FPCC-FG
+xssqrtqp 00101f0800101f10 00101f0000101f02 => f52595ef36141b67 20077f552f622b76 FPCC-FG
+
+xssqrtqpo 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xssqrtqpo 0102010201020102 0102030405060708 => 464bd73a50214d13 20806c2a33b95561 FPCC-FG
+xssqrtqpo 8899aabbccddeeff 0011223344556677 => dc52638df54a24e3 200810907245f32e FPCC-FG
+xssqrtqpo 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 7fff800000000000 FPRF-C FPCC-FU
+xssqrtqpo 0000100800001010 0000100000001002 => 00006037ff80505d 1ffe000000008010 FPCC-FG
+xssqrtqpo 0010100800101010 0010100000101002 => 830aae4bdadf7039 2007752e50e63f0a FPCC-FG
+xssqrtqpo 00001c0800001c10 00001c0000001c02 => b110f1988f82fedd 1ffe52a7fa9dd8ee FPCC-FG
+xssqrtqpo 00101c0800101c10 00101c0000101c02 => 77d067a08499cf9d 20077d52f24f5140 FPCC-FG
+xssqrtqpo 00001f0800001f10 00001f0000001f02 => d618e68f6c3361df 1ffe645640573e52 FPCC-FG
+xssqrtqpo 00101f0800101f10 00101f0000101f02 => f52595ef36141b67 20077f552f622b76 FPCC-FG
+
+All done. Tested 81 different instructions
+ppc vector scalar compare exponents quads:
+Test instruction group [ppc vector scalar compare exponents quads]
+xscmpexpqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+
+xscmpoqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+
+xscmpuqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+
+All done. Tested 84 different instructions
+ppc vector scalar rounding quads:
+Test instruction group [ppc vector scalar rounding quads]
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=2) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=2) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000007fff000000000000 (R=0) (RMC=0) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpi 00000000000000007fff000000000000 (R=0) (RMC=1) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpi 00000000000000007fff000000000000 (R=0) (RMC=2) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpi 00000000000000007fff000000000000 (R=0) (RMC=3) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpi 00000000000000007fff000000000000 (R=1) (RMC=0) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpi 00000000000000007fff000000000000 (R=1) (RMC=1) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpi 00000000000000007fff000000000000 (R=1) (RMC=2) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpi 00000000000000007fff000000000000 (R=1) (RMC=3) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff7fffffffffff0000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 7fff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff7fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff7fffffffffff0000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 7fff7fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000007fff7fffffffffff (R=0) (RMC=0) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpi 00000000000000007fff7fffffffffff (R=0) (RMC=1) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpi 00000000000000007fff7fffffffffff (R=0) (RMC=2) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpi 00000000000000007fff7fffffffffff (R=0) (RMC=3) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpi 00000000000000007fff7fffffffffff (R=1) (RMC=0) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpi 00000000000000007fff7fffffffffff (R=1) (RMC=1) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpi 00000000000000007fff7fffffffffff (R=1) (RMC=2) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpi 00000000000000007fff7fffffffffff (R=1) (RMC=3) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpi 80000000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80000000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80000000000000000000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 80000000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80000000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80000000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80000000000000000000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 80000000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000008000000000000000 (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 00000000000000008000000000000000 (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 00000000000000008000000000000000 (R=0) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 00000000000000008000000000000000 (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 00000000000000008000000000000000 (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 00000000000000008000000000000000 (R=1) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 00000000000000008000000000000000 (R=1) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 00000000000000008000000000000000 (R=1) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 80007fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80007fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80007fffffffffff0000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 80007fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80007fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80007fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80007fffffffffff0000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 80007fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080007fffffffffff (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080007fffffffffff (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080007fffffffffff (R=0) (RMC=2) => 0000000000000000bfff000000000000 FPCC-FL
+xsrqpi 000000000000000080007fffffffffff (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080007fffffffffff (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080007fffffffffff (R=1) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080007fffffffffff (R=1) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080007fffffffffff (R=1) (RMC=3) => 0000000000000000bfff000000000000 FPCC-FL
+xsrqpi 80ff0000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80ff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80ff0000000000000000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 80ff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80ff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80ff0000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80ff0000000000000000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 80ff0000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080ff000000000000 (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080ff000000000000 (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080ff000000000000 (R=0) (RMC=2) => 0000000000000000bfff000000000000 FPCC-FL
+xsrqpi 000000000000000080ff000000000000 (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080ff000000000000 (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080ff000000000000 (R=1) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080ff000000000000 (R=1) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080ff000000000000 (R=1) (RMC=3) => 0000000000000000bfff000000000000 FPCC-FL
+xsrqpi 80ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 80ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 80ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080ff7fffffffffff (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080ff7fffffffffff (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080ff7fffffffffff (R=0) (RMC=2) => 0000000000000000bfff000000000000 FPCC-FL
+xsrqpi 000000000000000080ff7fffffffffff (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080ff7fffffffffff (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080ff7fffffffffff (R=1) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080ff7fffffffffff (R=1) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000080ff7fffffffffff (R=1) (RMC=3) => 0000000000000000bfff000000000000 FPCC-FL
+xsrqpi 87ff0000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 87ff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 87ff0000000000000000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 87ff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 87ff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 87ff0000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 87ff0000000000000000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 87ff0000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000087ff000000000000 (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000087ff000000000000 (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000087ff000000000000 (R=0) (RMC=2) => 0000000000000000bfff000000000000 FPCC-FL
+xsrqpi 000000000000000087ff000000000000 (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000087ff000000000000 (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000087ff000000000000 (R=1) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000087ff000000000000 (R=1) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000087ff000000000000 (R=1) (RMC=3) => 0000000000000000bfff000000000000 FPCC-FL
+xsrqpi 87ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 87ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 87ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 87ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 87ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 87ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 87ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 87ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000087ff7fffffffffff (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000087ff7fffffffffff (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000087ff7fffffffffff (R=0) (RMC=2) => 0000000000000000bfff000000000000 FPCC-FL
+xsrqpi 000000000000000087ff7fffffffffff (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000087ff7fffffffffff (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000087ff7fffffffffff (R=1) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000087ff7fffffffffff (R=1) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpi 000000000000000087ff7fffffffffff (R=1) (RMC=3) => 0000000000000000bfff000000000000 FPCC-FL
+xsrqpi ffff0000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi ffff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi ffff0000000000000000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi ffff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi ffff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi ffff0000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi ffff0000000000000000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi ffff0000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 0000000000000000ffff000000000000 (R=0) (RMC=0) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpi 0000000000000000ffff000000000000 (R=0) (RMC=1) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpi 0000000000000000ffff000000000000 (R=0) (RMC=2) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpi 0000000000000000ffff000000000000 (R=0) (RMC=3) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpi 0000000000000000ffff000000000000 (R=1) (RMC=0) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpi 0000000000000000ffff000000000000 (R=1) (RMC=1) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpi 0000000000000000ffff000000000000 (R=1) (RMC=2) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpi 0000000000000000ffff000000000000 (R=1) (RMC=3) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpi ffff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi ffff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi ffff7fffffffffff0000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi ffff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi ffff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi ffff7fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi ffff7fffffffffff0000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi ffff7fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 0000000000000000ffff7fffffffffff (R=0) (RMC=0) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpi 0000000000000000ffff7fffffffffff (R=0) (RMC=1) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpi 0000000000000000ffff7fffffffffff (R=0) (RMC=2) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpi 0000000000000000ffff7fffffffffff (R=0) (RMC=3) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
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+xsrqpix 0000000000000000ffff7fffffffffff (R=1) (RMC=3) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
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+xsrqpxp 00000000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
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+xsrqpxp 07ff0000000000000000000000000000 (R=0) (RMC=1) => 08000000000000000000000000000000 FPRF-C FPCC-FG
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+xsrqpxp 07ff0000000000000000000000000000 (R=1) (RMC=0) => 08000000000000000000000000000000 FPRF-C FPCC-FG
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+xsrqpxp 07ff0000000000000000000000000000 (R=1) (RMC=2) => 08000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 07ff0000000000000000000000000000 (R=1) (RMC=3) => 07fe0000000000000000000000000000 FPRF-C FPCC-FG
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+xsrqpxp 000000000000000007ff000000000000 (R=0) (RMC=1) => 000000000000000007ff000000000000 FPCC-FG
+xsrqpxp 000000000000000007ff000000000000 (R=0) (RMC=2) => 000000000000000007ff000000000000 FPCC-FG
+xsrqpxp 000000000000000007ff000000000000 (R=0) (RMC=3) => 000000000000000007ff000000000000 FPCC-FG
+xsrqpxp 000000000000000007ff000000000000 (R=1) (RMC=0) => 000000000000000007ff000000000000 FPCC-FG
+xsrqpxp 000000000000000007ff000000000000 (R=1) (RMC=1) => 000000000000000007ff000000000000 FPCC-FG
+xsrqpxp 000000000000000007ff000000000000 (R=1) (RMC=2) => 000000000000000007ff000000000000 FPCC-FG
+xsrqpxp 000000000000000007ff000000000000 (R=1) (RMC=3) => 000000000000000007ff000000000000 FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 08000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 08000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 08000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 08000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 08000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 07fe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 08000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 07fe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=0) (RMC=0) => 000000000000000007ff7fffffffffff FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=0) (RMC=1) => 000000000000000007ff7fffffffffff FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=0) (RMC=2) => 000000000000000007ff7fffffffffff FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=0) (RMC=3) => 000000000000000007ff7fffffffffff FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=1) (RMC=0) => 000000000000000007ff7fffffffffff FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=1) (RMC=1) => 000000000000000007ff7fffffffffff FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=1) (RMC=2) => 000000000000000007ff7fffffffffff FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=1) (RMC=3) => 000000000000000007ff7fffffffffff FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=0) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=0) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=1) => 7ffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=3) => 7ffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=0) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=1) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=2) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=3) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=0) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=1) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=2) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=3) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=1) => 7ffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=3) => 7ffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=0) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=1) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=2) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=3) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=0) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=1) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=2) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=3) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
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+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FG
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+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
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+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FE
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+xsrqpxp 80007fffffffffff0000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80007fffffffffff0000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80007fffffffffff0000000000000000 (R=1) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FG
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+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=0) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=1) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=2) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=3) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=0) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=1) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=2) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=3) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
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+xsrqpxp 000000000000000080ff000000000000 (R=1) (RMC=2) => 000000000000000080ff000000000000 FPCC-FL
+xsrqpxp 000000000000000080ff000000000000 (R=1) (RMC=3) => 000000000000000080ff000000000000 FPCC-FL
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+xsrqpxp 000000000000000080ff7fffffffffff (R=0) (RMC=0) => 000000000000000080ff7fffffffffff FPCC-FL
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+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=0) => 000000000000000087ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=1) => 000000000000000087ff7fffffffffff FPCC-FL
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+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=3) => 000000000000000087ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000087ff7fffffffffff (R=1) (RMC=0) => 000000000000000087ff7fffffffffff FPCC-FL
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+xsrqpxp 000000000000000087ff7fffffffffff (R=1) (RMC=3) => 000000000000000087ff7fffffffffff FPCC-FL
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+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=2) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=1) => fffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=2) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=3) => fffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=0) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=1) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=2) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=3) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=0) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=1) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=2) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=3) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=2) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=1) => fffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=2) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=3) => fffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=0) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=1) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=2) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=3) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=0) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=1) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=2) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=3) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+
+All done. Tested 87 different instructions
+ppc vector permutes:
+Test instruction group [ppc vector permutes]
+xxperm 0000000000000000 0000000000000000 0102010201020102 0102030405060708, pcv[12021a0817141317 100d1b05070f0205] => 0300010008050408 0100020000000000 (00000000)
+xxperm 0000000000000000 0000000000000000 0102010201020102 0102030405060708, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0000000000000000 0000000000000000 (00000000)
+xxperm 8899aabbccddeeff 0011223344556677 7060504030201000 f0e0d0c0b0a09080, pcv[12021a0817141317 100d1b05070f0205] => d022508880b0c080 f0dd405577ff2255 (00000000)
+xxperm 8899aabbccddeeff 0011223344556677 7060504030201000 f0e0d0c0b0a09080, pcv[0705030a0b01ea0c 0e0c09010602080d] => 775533aabb11aacc eecc9911662288dd (00000000)
+xxperm 0000100800001010 0000100000001002 0010100800101010 0010100000101002, pcv[12021a0817141317 100d1b05070f0205] => 1010100002000002 0000080002101000 (00000000)
+xxperm 0000100800001010 0000100000001002 0010100800101010 0010100000101002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0200001008001000 1000000010100000 (00000000)
+xxperm 00001c0800001c10 00001c0000001c02 00101c0800101c10 00101c0000101c02, pcv[12021a0817141317 100d1b05070f0205] => 1c1c1c0002000002 0000080002101c00 (00000000)
+xxperm 00001c0800001c10 00001c0000001c02 00101c0800101c10 00101c0000101c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0200001c08001c00 1c0000001c1c0000 (00000000)
+xxperm 00001f0800001f10 00001f0000001f02 00101f0800101f10 00101f0000101f02, pcv[12021a0817141317 100d1b05070f0205] => 1f1f1f0002000002 0000080002101f00 (00000000)
+xxperm 00001f0800001f10 00001f0000001f02 00101f0800101f10 00101f0000101f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0200001f08001f00 1f0000001f1f0000 (00000000)
+
+xxpermr 0000000000000000 0000000000000000 0102010201020102 0102030405060708, pcv[12021a0817141317 100d1b05070f0205] => 0002000800000000 0003000101010201 (00000000)
+xxpermr 0000000000000000 0000000000000000 0102010201020102 0102030405060708, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0101010605010604 0204070102020803 (00000000)
+xxpermr 8899aabbccddeeff 0011223344556677 7060504030201000 f0e0d0c0b0a09080, pcv[12021a0817141317 100d1b05070f0205] => dd20558088bbcc88 ffd0445070f02050 (00000000)
+xxpermr 8899aabbccddeeff 0011223344556677 7060504030201000 f0e0d0c0b0a09080, pcv[0705030a0b01ea0c 0e0c09010602080d] => 705030a0b010a0c0 e0c09010602080d0 (00000000)
+xxpermr 0000100800001010 0000100000001002 0010100800101010 0010100000101002, pcv[12021a0817141317 100d1b05070f0205] => 0010000200080000 1010001000001010 (00000000)
+xxpermr 0000100800001010 0000100000001002 0010100800101010 0010100000101002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0010001000101000 1000101010100210 (00000000)
+xxpermr 00001c0800001c10 00001c0000001c02 00101c0800101c10 00101c0000101c02, pcv[12021a0817141317 100d1b05070f0205] => 0010000200080000 101c001c0000101c (00000000)
+xxpermr 00001c0800001c10 00001c0000001c02 00101c0800101c10 00101c0000101c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001c0010001c1000 10001c1c1010021c (00000000)
+xxpermr 00001f0800001f10 00001f0000001f02 00101f0800101f10 00101f0000101f02, pcv[12021a0817141317 100d1b05070f0205] => 0010000200080000 101f001f0000101f (00000000)
+xxpermr 00001f0800001f10 00001f0000001f02 00101f0800101f10 00101f0000101f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001f0010001f1000 10001f1f1010021f (00000000)
+
+All done. Tested 89 different instructions
+ppc vector three args + dest:
+Test instruction group [ppc vector three args + dest]
+vpermr 0000000000000000 0000000000000000 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => 0000000000000000 0000000000000000 (00000000)
+vpermr 0000000000000000 0000000000000000 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0000000000000000 0000000000000000 (00000000)
+vpermr 0000000000000000 0000000000000000 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => 00dd007700000000 002200aa8800ddaa (00000000)
+vpermr 0000000000000000 0000000000000000 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => 88aacc5544ee5533 113366ee99dd7722 (00000000)
+vpermr 0000000000000000 0000000000000000 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => 0000000200000000 0010001000000010 (00000000)
+vpermr 0000000000000000 0000000000000000 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0010000000100000 0000101000000210 (00000000)
+vpermr 0000000000000000 0000000000000000 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => 0000000200000000 001c001c0000001c (00000000)
+vpermr 0000000000000000 0000000000000000 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001c0000001c0000 00001c1c0000021c (00000000)
+vpermr 0000000000000000 0000000000000000 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => 0000000200000000 001f001f0000001f (00000000)
+vpermr 0000000000000000 0000000000000000 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001f0000001f0000 00001f1f0000021f (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => dd00550088bbcc88 ff00440000000000 (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0000000000000000 0000000000000000 (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => dddd557788bbcc88 ff2244aa8800ddaa (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => 88aacc5544ee5533 113366ee99dd7722 (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => dd00550288bbcc88 ff10441000000010 (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0010000000100000 0000101000000210 (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => dd00550288bbcc88 ff1c441c0000001c (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001c0000001c0000 00001c1c0000021c (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => dd00550288bbcc88 ff1f441f0000001f (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001f0000001f0000 00001f1f0000021f (00000000)
+vpermr 0000100800001010 0000100000001002 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => 0000000000080000 1000000000000000 (00000000)
+vpermr 0000100800001010 0000100000001002 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0000000000000000 0000000000000000 (00000000)
+vpermr 0000100800001010 0000100000001002 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => 00dd007700080000 102200aa8800ddaa (00000000)
+vpermr 0000100800001010 0000100000001002 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => 88aacc5544ee5533 113366ee99dd7722 (00000000)
+vpermr 0000100800001010 0000100000001002 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => 0000000200080000 1010001000000010 (00000000)
+vpermr 0000100800001010 0000100000001002 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0010000000100000 0000101000000210 (00000000)
+vpermr 0000100800001010 0000100000001002 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => 0000000200080000 101c001c0000001c (00000000)
+vpermr 0000100800001010 0000100000001002 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001c0000001c0000 00001c1c0000021c (00000000)
+vpermr 0000100800001010 0000100000001002 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => 0000000200080000 101f001f0000001f (00000000)
+vpermr 0000100800001010 0000100000001002 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001f0000001f0000 00001f1f0000021f (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => 0000000000080000 1000000000000000 (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0000000000000000 0000000000000000 (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => 00dd007700080000 102200aa8800ddaa (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => 88aacc5544ee5533 113366ee99dd7722 (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => 0000000200080000 1010001000000010 (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0010000000100000 0000101000000210 (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => 0000000200080000 101c001c0000001c (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001c0000001c0000 00001c1c0000021c (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => 0000000200080000 101f001f0000001f (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001f0000001f0000 00001f1f0000021f (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => 0000000000080000 1000000000000000 (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0000000000000000 0000000000000000 (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => 00dd007700080000 102200aa8800ddaa (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => 88aacc5544ee5533 113366ee99dd7722 (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => 0000000200080000 1010001000000010 (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0010000000100000 0000101000000210 (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => 0000000200080000 101c001c0000001c (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001c0000001c0000 00001c1c0000021c (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => 0000000200080000 101f001f0000001f (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001f0000001f0000 00001f1f0000021f (00000000)
+
+All done. Tested 90 different instructions
+ppc vector inserts:
+Test instruction group [ppc vector inserts]
+vinsertb 0102010201020102 0102030405060708 [0] (into zeros) => 0000000000000000 0800000000000000
+vinsertb 0102010201020102 0102030405060708 [0] (into ones) => ffffffffffffffff 08ffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [1] (into zeros) => 0000000000000000 0008000000000000
+vinsertb 0102010201020102 0102030405060708 [1] (into ones) => ffffffffffffffff ff08ffffffffffff
+vinsertb 0102010201020102 0102030405060708 [2] (into zeros) => 0000000000000000 0000080000000000
+vinsertb 0102010201020102 0102030405060708 [2] (into ones) => ffffffffffffffff ffff08ffffffffff
+vinsertb 0102010201020102 0102030405060708 [3] (into zeros) => 0000000000000000 0000000800000000
+vinsertb 0102010201020102 0102030405060708 [3] (into ones) => ffffffffffffffff ffffff08ffffffff
+vinsertb 0102010201020102 0102030405060708 [4] (into zeros) => 0000000000000000 0000000008000000
+vinsertb 0102010201020102 0102030405060708 [4] (into ones) => ffffffffffffffff ffffffff08ffffff
+vinsertb 0102010201020102 0102030405060708 [5] (into zeros) => 0000000000000000 0000000000080000
+vinsertb 0102010201020102 0102030405060708 [5] (into ones) => ffffffffffffffff ffffffffff08ffff
+vinsertb 0102010201020102 0102030405060708 [6] (into zeros) => 0000000000000000 0000000000000800
+vinsertb 0102010201020102 0102030405060708 [6] (into ones) => ffffffffffffffff ffffffffffff08ff
+vinsertb 0102010201020102 0102030405060708 [7] (into zeros) => 0000000000000000 0000000000000008
+vinsertb 0102010201020102 0102030405060708 [7] (into ones) => ffffffffffffffff ffffffffffffff08
+vinsertb 0102010201020102 0102030405060708 [8] (into zeros) => 0800000000000000 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [8] (into ones) => 08ffffffffffffff ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [9] (into zeros) => 0008000000000000 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [9] (into ones) => ff08ffffffffffff ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [10] (into zeros) => 0000080000000000 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [10] (into ones) => ffff08ffffffffff ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [11] (into zeros) => 0000000800000000 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [11] (into ones) => ffffff08ffffffff ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [12] (into zeros) => 0000000008000000 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [12] (into ones) => ffffffff08ffffff ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [13] (into zeros) => 0000000000080000 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [13] (into ones) => ffffffffff08ffff ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [14] (into zeros) => 0000000000000800 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [14] (into ones) => ffffffffffff08ff ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [15] (into zeros) => 0000000000000008 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [15] (into ones) => ffffffffffffff08 ffffffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [0] (into zeros) => 0000000000000000 8000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [0] (into ones) => ffffffffffffffff 80ffffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [1] (into zeros) => 0000000000000000 0080000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [1] (into ones) => ffffffffffffffff ff80ffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [2] (into zeros) => 0000000000000000 0000800000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [2] (into ones) => ffffffffffffffff ffff80ffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [3] (into zeros) => 0000000000000000 0000008000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [3] (into ones) => ffffffffffffffff ffffff80ffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [4] (into zeros) => 0000000000000000 0000000080000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [4] (into ones) => ffffffffffffffff ffffffff80ffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [5] (into zeros) => 0000000000000000 0000000000800000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [5] (into ones) => ffffffffffffffff ffffffffff80ffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [6] (into zeros) => 0000000000000000 0000000000008000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [6] (into ones) => ffffffffffffffff ffffffffffff80ff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [7] (into zeros) => 0000000000000000 0000000000000080
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [7] (into ones) => ffffffffffffffff ffffffffffffff80
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [8] (into zeros) => 8000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [8] (into ones) => 80ffffffffffffff ffffffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [9] (into zeros) => 0080000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [9] (into ones) => ff80ffffffffffff ffffffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [10] (into zeros) => 0000800000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [10] (into ones) => ffff80ffffffffff ffffffffffffffff
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+vinserth 0102010201020102 0102030405060708 [5] (into ones) => ffffffffffffffff ffffffffff0708ff
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+vinserth 0102010201020102 0102030405060708 [6] (into ones) => ffffffffffffffff ffffffffffff0708
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+vinserth 0102010201020102 0102030405060708 [8] (into zeros) => 0708000000000000 0000000000000000
+vinserth 0102010201020102 0102030405060708 [8] (into ones) => 0708ffffffffffff ffffffffffffffff
+vinserth 0102010201020102 0102030405060708 [9] (into zeros) => 0007080000000000 0000000000000000
+vinserth 0102010201020102 0102030405060708 [9] (into ones) => ff0708ffffffffff ffffffffffffffff
+vinserth 0102010201020102 0102030405060708 [10] (into zeros) => 0000070800000000 0000000000000000
+vinserth 0102010201020102 0102030405060708 [10] (into ones) => ffff0708ffffffff ffffffffffffffff
+vinserth 0102010201020102 0102030405060708 [11] (into zeros) => 0000000708000000 0000000000000000
+vinserth 0102010201020102 0102030405060708 [11] (into ones) => ffffff0708ffffff ffffffffffffffff
+vinserth 0102010201020102 0102030405060708 [12] (into zeros) => 0000000007080000 0000000000000000
+vinserth 0102010201020102 0102030405060708 [12] (into ones) => ffffffff0708ffff ffffffffffffffff
+vinserth 0102010201020102 0102030405060708 [13] (into zeros) => 0000000000070800 0000000000000000
+vinserth 0102010201020102 0102030405060708 [13] (into ones) => ffffffffff0708ff ffffffffffffffff
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+vinserth 0102010201020102 0102030405060708 [14] (into ones) => ffffffffffff0708 ffffffffffffffff
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+vinserth 7060504030201000 f0e0d0c0b0a09080 [1] (into ones) => ffffffffffffffff ff9080ffffffffff
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+vinserth 7060504030201000 f0e0d0c0b0a09080 [3] (into zeros) => 0000000000000000 0000009080000000
+vinserth 7060504030201000 f0e0d0c0b0a09080 [3] (into ones) => ffffffffffffffff ffffff9080ffffff
+vinserth 7060504030201000 f0e0d0c0b0a09080 [4] (into zeros) => 0000000000000000 0000000090800000
+vinserth 7060504030201000 f0e0d0c0b0a09080 [4] (into ones) => ffffffffffffffff ffffffff9080ffff
+vinserth 7060504030201000 f0e0d0c0b0a09080 [5] (into zeros) => 0000000000000000 0000000000908000
+vinserth 7060504030201000 f0e0d0c0b0a09080 [5] (into ones) => ffffffffffffffff ffffffffff9080ff
+vinserth 7060504030201000 f0e0d0c0b0a09080 [6] (into zeros) => 0000000000000000 0000000000009080
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+vinserth 7060504030201000 f0e0d0c0b0a09080 [7] (into zeros) => 8000000000000000 0000000000000090
+vinserth 7060504030201000 f0e0d0c0b0a09080 [7] (into ones) => 80ffffffffffffff ffffffffffffff90
+vinserth 7060504030201000 f0e0d0c0b0a09080 [8] (into zeros) => 9080000000000000 0000000000000000
+vinserth 7060504030201000 f0e0d0c0b0a09080 [8] (into ones) => 9080ffffffffffff ffffffffffffffff
+vinserth 7060504030201000 f0e0d0c0b0a09080 [9] (into zeros) => 0090800000000000 0000000000000000
+vinserth 7060504030201000 f0e0d0c0b0a09080 [9] (into ones) => ff9080ffffffffff ffffffffffffffff
+vinserth 7060504030201000 f0e0d0c0b0a09080 [10] (into zeros) => 0000908000000000 0000000000000000
+vinserth 7060504030201000 f0e0d0c0b0a09080 [10] (into ones) => ffff9080ffffffff ffffffffffffffff
+vinserth 7060504030201000 f0e0d0c0b0a09080 [11] (into zeros) => 0000009080000000 0000000000000000
+vinserth 7060504030201000 f0e0d0c0b0a09080 [11] (into ones) => ffffff9080ffffff ffffffffffffffff
+vinserth 7060504030201000 f0e0d0c0b0a09080 [12] (into zeros) => 0000000090800000 0000000000000000
+vinserth 7060504030201000 f0e0d0c0b0a09080 [12] (into ones) => ffffffff9080ffff ffffffffffffffff
+vinserth 7060504030201000 f0e0d0c0b0a09080 [13] (into zeros) => 0000000000908000 0000000000000000
+vinserth 7060504030201000 f0e0d0c0b0a09080 [13] (into ones) => ffffffffff9080ff ffffffffffffffff
+vinserth 7060504030201000 f0e0d0c0b0a09080 [14] (into zeros) => 0000000000009080 0000000000000000
+vinserth 7060504030201000 f0e0d0c0b0a09080 [14] (into ones) => ffffffffffff9080 ffffffffffffffff
+
+vinsertw 0102010201020102 0102030405060708 [0] (into zeros) => 0000000000000000 0506070800000000
+vinsertw 0102010201020102 0102030405060708 [0] (into ones) => ffffffffffffffff 05060708ffffffff
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+vinsertw 0102010201020102 0102030405060708 [1] (into ones) => ffffffffffffffff ff05060708ffffff
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+vinsertw 0102010201020102 0102030405060708 [2] (into ones) => ffffffffffffffff ffff05060708ffff
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+vinsertw 0102010201020102 0102030405060708 [5] (into ones) => 08ffffffffffffff ffffffffff050607
+vinsertw 0102010201020102 0102030405060708 [6] (into zeros) => 0708000000000000 0000000000000506
+vinsertw 0102010201020102 0102030405060708 [6] (into ones) => 0708ffffffffffff ffffffffffff0506
+vinsertw 0102010201020102 0102030405060708 [7] (into zeros) => 0607080000000000 0000000000000005
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+vinsertw 0102010201020102 0102030405060708 [8] (into zeros) => 0506070800000000 0000000000000000
+vinsertw 0102010201020102 0102030405060708 [8] (into ones) => 05060708ffffffff ffffffffffffffff
+vinsertw 0102010201020102 0102030405060708 [9] (into zeros) => 0005060708000000 0000000000000000
+vinsertw 0102010201020102 0102030405060708 [9] (into ones) => ff05060708ffffff ffffffffffffffff
+vinsertw 0102010201020102 0102030405060708 [10] (into zeros) => 0000050607080000 0000000000000000
+vinsertw 0102010201020102 0102030405060708 [10] (into ones) => ffff05060708ffff ffffffffffffffff
+vinsertw 0102010201020102 0102030405060708 [11] (into zeros) => 0000000506070800 0000000000000000
+vinsertw 0102010201020102 0102030405060708 [11] (into ones) => ffffff05060708ff ffffffffffffffff
+vinsertw 0102010201020102 0102030405060708 [12] (into zeros) => 0000000005060708 0000000000000000
+vinsertw 0102010201020102 0102030405060708 [12] (into ones) => ffffffff05060708 ffffffffffffffff
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+vinsertw 7060504030201000 f0e0d0c0b0a09080 [2] (into ones) => ffffffffffffffff ffffb0a09080ffff
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [3] (into zeros) => 0000000000000000 000000b0a0908000
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [3] (into ones) => ffffffffffffffff ffffffb0a09080ff
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [4] (into zeros) => 0000000000000000 00000000b0a09080
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [4] (into ones) => ffffffffffffffff ffffffffb0a09080
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [5] (into zeros) => 8000000000000000 0000000000b0a090
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+vinsertw 7060504030201000 f0e0d0c0b0a09080 [6] (into zeros) => 9080000000000000 000000000000b0a0
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [6] (into ones) => 9080ffffffffffff ffffffffffffb0a0
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+vinsertw 7060504030201000 f0e0d0c0b0a09080 [7] (into ones) => a09080ffffffffff ffffffffffffffb0
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [8] (into zeros) => b0a0908000000000 0000000000000000
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [8] (into ones) => b0a09080ffffffff ffffffffffffffff
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [9] (into zeros) => 00b0a09080000000 0000000000000000
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [9] (into ones) => ffb0a09080ffffff ffffffffffffffff
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [10] (into zeros) => 0000b0a090800000 0000000000000000
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [10] (into ones) => ffffb0a09080ffff ffffffffffffffff
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [11] (into zeros) => 000000b0a0908000 0000000000000000
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [11] (into ones) => ffffffb0a09080ff ffffffffffffffff
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [12] (into zeros) => 00000000b0a09080 0000000000000000
+vinsertw 7060504030201000 f0e0d0c0b0a09080 [12] (into ones) => ffffffffb0a09080 ffffffffffffffff
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+vinsertd 0102010201020102 0102030405060708 [0] (into zeros) => 0000000000000000 0102030405060708
+vinsertd 0102010201020102 0102030405060708 [0] (into ones) => ffffffffffffffff 0102030405060708
+vinsertd 0102010201020102 0102030405060708 [1] (into zeros) => 0800000000000000 0001020304050607
+vinsertd 0102010201020102 0102030405060708 [1] (into ones) => 08ffffffffffffff ff01020304050607
+vinsertd 0102010201020102 0102030405060708 [2] (into zeros) => 0708000000000000 0000010203040506
+vinsertd 0102010201020102 0102030405060708 [2] (into ones) => 0708ffffffffffff ffff010203040506
+vinsertd 0102010201020102 0102030405060708 [3] (into zeros) => 0607080000000000 0000000102030405
+vinsertd 0102010201020102 0102030405060708 [3] (into ones) => 060708ffffffffff ffffff0102030405
+vinsertd 0102010201020102 0102030405060708 [4] (into zeros) => 0506070800000000 0000000001020304
+vinsertd 0102010201020102 0102030405060708 [4] (into ones) => 05060708ffffffff ffffffff01020304
+vinsertd 0102010201020102 0102030405060708 [5] (into zeros) => 0405060708000000 0000000000010203
+vinsertd 0102010201020102 0102030405060708 [5] (into ones) => 0405060708ffffff ffffffffff010203
+vinsertd 0102010201020102 0102030405060708 [6] (into zeros) => 0304050607080000 0000000000000102
+vinsertd 0102010201020102 0102030405060708 [6] (into ones) => 030405060708ffff ffffffffffff0102
+vinsertd 0102010201020102 0102030405060708 [7] (into zeros) => 0203040506070800 0000000000000001
+vinsertd 0102010201020102 0102030405060708 [7] (into ones) => 02030405060708ff ffffffffffffff01
+vinsertd 0102010201020102 0102030405060708 [8] (into zeros) => 0102030405060708 0000000000000000
+vinsertd 0102010201020102 0102030405060708 [8] (into ones) => 0102030405060708 ffffffffffffffff
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [0] (into zeros) => 0000000000000000 f0e0d0c0b0a09080
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [0] (into ones) => ffffffffffffffff f0e0d0c0b0a09080
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [1] (into zeros) => 8000000000000000 00f0e0d0c0b0a090
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [1] (into ones) => 80ffffffffffffff fff0e0d0c0b0a090
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [2] (into zeros) => 9080000000000000 0000f0e0d0c0b0a0
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [2] (into ones) => 9080ffffffffffff fffff0e0d0c0b0a0
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [3] (into zeros) => a090800000000000 000000f0e0d0c0b0
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [3] (into ones) => a09080ffffffffff fffffff0e0d0c0b0
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [4] (into zeros) => b0a0908000000000 00000000f0e0d0c0
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [4] (into ones) => b0a09080ffffffff fffffffff0e0d0c0
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [5] (into zeros) => c0b0a09080000000 0000000000f0e0d0
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [5] (into ones) => c0b0a09080ffffff fffffffffff0e0d0
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [6] (into zeros) => d0c0b0a090800000 000000000000f0e0
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [6] (into ones) => d0c0b0a09080ffff fffffffffffff0e0
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [7] (into zeros) => e0d0c0b0a0908000 00000000000000f0
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [7] (into ones) => e0d0c0b0a09080ff fffffffffffffff0
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [8] (into zeros) => f0e0d0c0b0a09080 0000000000000000
+vinsertd 7060504030201000 f0e0d0c0b0a09080 [8] (into ones) => f0e0d0c0b0a09080 ffffffffffffffff
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+vextractub 0102010201020102 0102030405060708 [0] (into zeros) => 0000000000000000 0000000000000001
+vextractub 0102010201020102 0102030405060708 [0] (into ones) => 0000000000000000 0000000000000001
+vextractub 0102010201020102 0102030405060708 [1] (into zeros) => 0000000000000000 0000000000000002
+vextractub 0102010201020102 0102030405060708 [1] (into ones) => 0000000000000000 0000000000000002
+vextractub 0102010201020102 0102030405060708 [2] (into zeros) => 0000000000000000 0000000000000003
+vextractub 0102010201020102 0102030405060708 [2] (into ones) => 0000000000000000 0000000000000003
+vextractub 0102010201020102 0102030405060708 [3] (into zeros) => 0000000000000000 0000000000000004
+vextractub 0102010201020102 0102030405060708 [3] (into ones) => 0000000000000000 0000000000000004
+vextractub 0102010201020102 0102030405060708 [4] (into zeros) => 0000000000000000 0000000000000005
+vextractub 0102010201020102 0102030405060708 [4] (into ones) => 0000000000000000 0000000000000005
+vextractub 0102010201020102 0102030405060708 [5] (into zeros) => 0000000000000000 0000000000000006
+vextractub 0102010201020102 0102030405060708 [5] (into ones) => 0000000000000000 0000000000000006
+vextractub 0102010201020102 0102030405060708 [6] (into zeros) => 0000000000000000 0000000000000007
+vextractub 0102010201020102 0102030405060708 [6] (into ones) => 0000000000000000 0000000000000007
+vextractub 0102010201020102 0102030405060708 [7] (into zeros) => 0000000000000000 0000000000000008
+vextractub 0102010201020102 0102030405060708 [7] (into ones) => 0000000000000000 0000000000000008
+vextractub 0102010201020102 0102030405060708 [8] (into zeros) => 0000000000000000 0000000000000001
+vextractub 0102010201020102 0102030405060708 [8] (into ones) => 0000000000000000 0000000000000001
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+vextractub 0102010201020102 0102030405060708 [10] (into zeros) => 0000000000000000 0000000000000001
+vextractub 0102010201020102 0102030405060708 [10] (into ones) => 0000000000000000 0000000000000001
+vextractub 0102010201020102 0102030405060708 [11] (into zeros) => 0000000000000000 0000000000000002
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+vextractub 0102010201020102 0102030405060708 [12] (into zeros) => 0000000000000000 0000000000000001
+vextractub 0102010201020102 0102030405060708 [12] (into ones) => 0000000000000000 0000000000000001
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+vextractub 0102010201020102 0102030405060708 [14] (into ones) => 0000000000000000 0000000000000001
+vextractub 0102010201020102 0102030405060708 [15] (into zeros) => 0000000000000000 0000000000000002
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+vextractub 7060504030201000 f0e0d0c0b0a09080 [2] (into zeros) => 0000000000000000 00000000000000d0
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+vextractub 7060504030201000 f0e0d0c0b0a09080 [3] (into zeros) => 0000000000000000 00000000000000c0
+vextractub 7060504030201000 f0e0d0c0b0a09080 [3] (into ones) => 0000000000000000 00000000000000c0
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+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [6] (into ones) => 9080ffffffffffff ffffffffffffb0a0
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [7] (into zeros) => a090800000000000 00000000000000b0
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [7] (into ones) => a09080ffffffffff ffffffffffffffb0
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [8] (into zeros) => b0a0908000000000 0000000000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [8] (into ones) => b0a09080ffffffff ffffffffffffffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [9] (into zeros) => 00b0a09080000000 0000000000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [9] (into ones) => ffb0a09080ffffff ffffffffffffffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [10] (into zeros) => 0000b0a090800000 0000000000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [10] (into ones) => ffffb0a09080ffff ffffffffffffffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [11] (into zeros) => 000000b0a0908000 0000000000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [11] (into ones) => ffffffb0a09080ff ffffffffffffffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [12] (into zeros) => 00000000b0a09080 0000000000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [12] (into ones) => ffffffffb0a09080 ffffffffffffffff
+
+xxextractuw 0102010201020102 0102030405060708 [0] (into zeros) => 0000000000000000 0000000001020304
+xxextractuw 0102010201020102 0102030405060708 [0] (into ones) => 0000000000000000 0000000001020304
+xxextractuw 0102010201020102 0102030405060708 [1] (into zeros) => 0000000000000000 0000000002030405
+xxextractuw 0102010201020102 0102030405060708 [1] (into ones) => 0000000000000000 0000000002030405
+xxextractuw 0102010201020102 0102030405060708 [2] (into zeros) => 0000000000000000 0000000003040506
+xxextractuw 0102010201020102 0102030405060708 [2] (into ones) => 0000000000000000 0000000003040506
+xxextractuw 0102010201020102 0102030405060708 [3] (into zeros) => 0000000000000000 0000000004050607
+xxextractuw 0102010201020102 0102030405060708 [3] (into ones) => 0000000000000000 0000000004050607
+xxextractuw 0102010201020102 0102030405060708 [4] (into zeros) => 0000000000000000 0000000005060708
+xxextractuw 0102010201020102 0102030405060708 [4] (into ones) => 0000000000000000 0000000005060708
+xxextractuw 0102010201020102 0102030405060708 [5] (into zeros) => 0000000000000000 0000000006070801
+xxextractuw 0102010201020102 0102030405060708 [5] (into ones) => 0000000000000000 0000000006070801
+xxextractuw 0102010201020102 0102030405060708 [6] (into zeros) => 0000000000000000 0000000007080102
+xxextractuw 0102010201020102 0102030405060708 [6] (into ones) => 0000000000000000 0000000007080102
+xxextractuw 0102010201020102 0102030405060708 [7] (into zeros) => 0000000000000000 0000000008010201
+xxextractuw 0102010201020102 0102030405060708 [7] (into ones) => 0000000000000000 0000000008010201
+xxextractuw 0102010201020102 0102030405060708 [8] (into zeros) => 0000000000000000 0000000001020102
+xxextractuw 0102010201020102 0102030405060708 [8] (into ones) => 0000000000000000 0000000001020102
+xxextractuw 0102010201020102 0102030405060708 [9] (into zeros) => 0000000000000000 0000000002010201
+xxextractuw 0102010201020102 0102030405060708 [9] (into ones) => 0000000000000000 0000000002010201
+xxextractuw 0102010201020102 0102030405060708 [10] (into zeros) => 0000000000000000 0000000001020102
+xxextractuw 0102010201020102 0102030405060708 [10] (into ones) => 0000000000000000 0000000001020102
+xxextractuw 0102010201020102 0102030405060708 [11] (into zeros) => 0000000000000000 0000000002010201
+xxextractuw 0102010201020102 0102030405060708 [11] (into ones) => 0000000000000000 0000000002010201
+xxextractuw 0102010201020102 0102030405060708 [12] (into zeros) => 0000000000000000 0000000001020102
+xxextractuw 0102010201020102 0102030405060708 [12] (into ones) => 0000000000000000 0000000001020102
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [0] (into zeros) => 0000000000000000 00000000f0e0d0c0
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [0] (into ones) => 0000000000000000 00000000f0e0d0c0
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [1] (into zeros) => 0000000000000000 00000000e0d0c0b0
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [1] (into ones) => 0000000000000000 00000000e0d0c0b0
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [2] (into zeros) => 0000000000000000 00000000d0c0b0a0
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [2] (into ones) => 0000000000000000 00000000d0c0b0a0
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [3] (into zeros) => 0000000000000000 00000000c0b0a090
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [3] (into ones) => 0000000000000000 00000000c0b0a090
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [4] (into zeros) => 0000000000000000 00000000b0a09080
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [4] (into ones) => 0000000000000000 00000000b0a09080
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [5] (into zeros) => 0000000000000000 00000000a0908070
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [5] (into ones) => 0000000000000000 00000000a0908070
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [6] (into zeros) => 0000000000000000 0000000090807060
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [6] (into ones) => 0000000000000000 0000000090807060
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [7] (into zeros) => 0000000000000000 0000000080706050
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [7] (into ones) => 0000000000000000 0000000080706050
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [8] (into zeros) => 0000000000000000 0000000070605040
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [8] (into ones) => 0000000000000000 0000000070605040
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [9] (into zeros) => 0000000000000000 0000000060504030
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [9] (into ones) => 0000000000000000 0000000060504030
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [10] (into zeros) => 0000000000000000 0000000050403020
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [10] (into ones) => 0000000000000000 0000000050403020
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [11] (into zeros) => 0000000000000000 0000000040302010
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [11] (into ones) => 0000000000000000 0000000040302010
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [12] (into zeros) => 0000000000000000 0000000030201000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [12] (into ones) => 0000000000000000 0000000030201000
+
+All done. Tested 100 different instructions
+ppc vector extract from vector to reg:
+Test instruction group [ppc vector extract from vector to reg]
+vextublx 0000000000000000 0000000000000000 0 => 0
+vextublx 0000000000000000 0000000000000000 1 => 0
+vextublx 0000000000000000 0000000000000000 2 => 0
+vextublx 0000000000000000 0000000000000000 3 => 0
+vextublx 0000000000000000 0000000000000000 4 => 0
+vextublx 0000000000000000 0000000000000000 5 => 0
+vextublx 0000000000000000 0000000000000000 6 => 0
+vextublx 0000000000000000 0000000000000000 7 => 0
+vextublx 0000000000000000 0000000000000000 8 => 0
+vextublx 0000000000000000 0000000000000000 9 => 0
+vextublx 0000000000000000 0000000000000000 10 => 0
+vextublx 0000000000000000 0000000000000000 11 => 0
+vextublx 0000000000000000 0000000000000000 12 => 0
+vextublx 0000000000000000 0000000000000000 13 => 0
+vextublx 0000000000000000 0000000000000000 14 => 0
+vextublx 0000000000000000 0000000000000000 15 => 0
+vextublx 0102010201020102 0102030405060708 0 => 1
+vextublx 0102010201020102 0102030405060708 1 => 2
+vextublx 0102010201020102 0102030405060708 2 => 3
+vextublx 0102010201020102 0102030405060708 3 => 4
+vextublx 0102010201020102 0102030405060708 4 => 5
+vextublx 0102010201020102 0102030405060708 5 => 6
+vextublx 0102010201020102 0102030405060708 6 => 7
+vextublx 0102010201020102 0102030405060708 7 => 8
+vextublx 0102010201020102 0102030405060708 8 => 1
+vextublx 0102010201020102 0102030405060708 9 => 2
+vextublx 0102010201020102 0102030405060708 10 => 1
+vextublx 0102010201020102 0102030405060708 11 => 2
+vextublx 0102010201020102 0102030405060708 12 => 1
+vextublx 0102010201020102 0102030405060708 13 => 2
+vextublx 0102010201020102 0102030405060708 14 => 1
+vextublx 0102010201020102 0102030405060708 15 => 2
+vextublx 8899aabbccddeeff 0011223344556677 0 => 0
+vextublx 8899aabbccddeeff 0011223344556677 1 => 11
+vextublx 8899aabbccddeeff 0011223344556677 2 => 22
+vextublx 8899aabbccddeeff 0011223344556677 3 => 33
+vextublx 8899aabbccddeeff 0011223344556677 4 => 44
+vextublx 8899aabbccddeeff 0011223344556677 5 => 55
+vextublx 8899aabbccddeeff 0011223344556677 6 => 66
+vextublx 8899aabbccddeeff 0011223344556677 7 => 77
+vextublx 8899aabbccddeeff 0011223344556677 8 => 88
+vextublx 8899aabbccddeeff 0011223344556677 9 => 99
+vextublx 8899aabbccddeeff 0011223344556677 10 => aa
+vextublx 8899aabbccddeeff 0011223344556677 11 => bb
+vextublx 8899aabbccddeeff 0011223344556677 12 => cc
+vextublx 8899aabbccddeeff 0011223344556677 13 => dd
+vextublx 8899aabbccddeeff 0011223344556677 14 => ee
+vextublx 8899aabbccddeeff 0011223344556677 15 => ff
+vextublx 7060504030201000 f0e0d0c0b0a09080 0 => f0
+vextublx 7060504030201000 f0e0d0c0b0a09080 1 => e0
+vextublx 7060504030201000 f0e0d0c0b0a09080 2 => d0
+vextublx 7060504030201000 f0e0d0c0b0a09080 3 => c0
+vextublx 7060504030201000 f0e0d0c0b0a09080 4 => b0
+vextublx 7060504030201000 f0e0d0c0b0a09080 5 => a0
+vextublx 7060504030201000 f0e0d0c0b0a09080 6 => 90
+vextublx 7060504030201000 f0e0d0c0b0a09080 7 => 80
+vextublx 7060504030201000 f0e0d0c0b0a09080 8 => 70
+vextublx 7060504030201000 f0e0d0c0b0a09080 9 => 60
+vextublx 7060504030201000 f0e0d0c0b0a09080 10 => 50
+vextublx 7060504030201000 f0e0d0c0b0a09080 11 => 40
+vextublx 7060504030201000 f0e0d0c0b0a09080 12 => 30
+vextublx 7060504030201000 f0e0d0c0b0a09080 13 => 20
+vextublx 7060504030201000 f0e0d0c0b0a09080 14 => 10
+vextublx 7060504030201000 f0e0d0c0b0a09080 15 => 0
+vextublx 0000100800001010 0000100000001002 0 => 0
+vextublx 0000100800001010 0000100000001002 1 => 0
+vextublx 0000100800001010 0000100000001002 2 => 10
+vextublx 0000100800001010 0000100000001002 3 => 0
+vextublx 0000100800001010 0000100000001002 4 => 0
+vextublx 0000100800001010 0000100000001002 5 => 0
+vextublx 0000100800001010 0000100000001002 6 => 10
+vextublx 0000100800001010 0000100000001002 7 => 2
+vextublx 0000100800001010 0000100000001002 8 => 0
+vextublx 0000100800001010 0000100000001002 9 => 0
+vextublx 0000100800001010 0000100000001002 10 => 10
+vextublx 0000100800001010 0000100000001002 11 => 8
+vextublx 0000100800001010 0000100000001002 12 => 0
+vextublx 0000100800001010 0000100000001002 13 => 0
+vextublx 0000100800001010 0000100000001002 14 => 10
+vextublx 0000100800001010 0000100000001002 15 => 10
+vextublx 0010100800101010 0010100000101002 0 => 0
+vextublx 0010100800101010 0010100000101002 1 => 10
+vextublx 0010100800101010 0010100000101002 2 => 10
+vextublx 0010100800101010 0010100000101002 3 => 0
+vextublx 0010100800101010 0010100000101002 4 => 0
+vextublx 0010100800101010 0010100000101002 5 => 10
+vextublx 0010100800101010 0010100000101002 6 => 10
+vextublx 0010100800101010 0010100000101002 7 => 2
+vextublx 0010100800101010 0010100000101002 8 => 0
+vextublx 0010100800101010 0010100000101002 9 => 10
+vextublx 0010100800101010 0010100000101002 10 => 10
+vextublx 0010100800101010 0010100000101002 11 => 8
+vextublx 0010100800101010 0010100000101002 12 => 0
+vextublx 0010100800101010 0010100000101002 13 => 10
+vextublx 0010100800101010 0010100000101002 14 => 10
+vextublx 0010100800101010 0010100000101002 15 => 10
+vextublx 00001c0800001c10 00001c0000001c02 0 => 0
+vextublx 00001c0800001c10 00001c0000001c02 1 => 0
+vextublx 00001c0800001c10 00001c0000001c02 2 => 1c
+vextublx 00001c0800001c10 00001c0000001c02 3 => 0
+vextublx 00001c0800001c10 00001c0000001c02 4 => 0
+vextublx 00001c0800001c10 00001c0000001c02 5 => 0
+vextublx 00001c0800001c10 00001c0000001c02 6 => 1c
+vextublx 00001c0800001c10 00001c0000001c02 7 => 2
+vextublx 00001c0800001c10 00001c0000001c02 8 => 0
+vextublx 00001c0800001c10 00001c0000001c02 9 => 0
+vextublx 00001c0800001c10 00001c0000001c02 10 => 1c
+vextublx 00001c0800001c10 00001c0000001c02 11 => 8
+vextublx 00001c0800001c10 00001c0000001c02 12 => 0
+vextublx 00001c0800001c10 00001c0000001c02 13 => 0
+vextublx 00001c0800001c10 00001c0000001c02 14 => 1c
+vextublx 00001c0800001c10 00001c0000001c02 15 => 10
+vextublx 00101c0800101c10 00101c0000101c02 0 => 0
+vextublx 00101c0800101c10 00101c0000101c02 1 => 10
+vextublx 00101c0800101c10 00101c0000101c02 2 => 1c
+vextublx 00101c0800101c10 00101c0000101c02 3 => 0
+vextublx 00101c0800101c10 00101c0000101c02 4 => 0
+vextublx 00101c0800101c10 00101c0000101c02 5 => 10
+vextublx 00101c0800101c10 00101c0000101c02 6 => 1c
+vextublx 00101c0800101c10 00101c0000101c02 7 => 2
+vextublx 00101c0800101c10 00101c0000101c02 8 => 0
+vextublx 00101c0800101c10 00101c0000101c02 9 => 10
+vextublx 00101c0800101c10 00101c0000101c02 10 => 1c
+vextublx 00101c0800101c10 00101c0000101c02 11 => 8
+vextublx 00101c0800101c10 00101c0000101c02 12 => 0
+vextublx 00101c0800101c10 00101c0000101c02 13 => 10
+vextublx 00101c0800101c10 00101c0000101c02 14 => 1c
+vextublx 00101c0800101c10 00101c0000101c02 15 => 10
+vextublx 00001f0800001f10 00001f0000001f02 0 => 0
+vextublx 00001f0800001f10 00001f0000001f02 1 => 0
+vextublx 00001f0800001f10 00001f0000001f02 2 => 1f
+vextublx 00001f0800001f10 00001f0000001f02 3 => 0
+vextublx 00001f0800001f10 00001f0000001f02 4 => 0
+vextublx 00001f0800001f10 00001f0000001f02 5 => 0
+vextublx 00001f0800001f10 00001f0000001f02 6 => 1f
+vextublx 00001f0800001f10 00001f0000001f02 7 => 2
+vextublx 00001f0800001f10 00001f0000001f02 8 => 0
+vextublx 00001f0800001f10 00001f0000001f02 9 => 0
+vextublx 00001f0800001f10 00001f0000001f02 10 => 1f
+vextublx 00001f0800001f10 00001f0000001f02 11 => 8
+vextublx 00001f0800001f10 00001f0000001f02 12 => 0
+vextublx 00001f0800001f10 00001f0000001f02 13 => 0
+vextublx 00001f0800001f10 00001f0000001f02 14 => 1f
+vextublx 00001f0800001f10 00001f0000001f02 15 => 10
+vextublx 00101f0800101f10 00101f0000101f02 0 => 0
+vextublx 00101f0800101f10 00101f0000101f02 1 => 10
+vextublx 00101f0800101f10 00101f0000101f02 2 => 1f
+vextublx 00101f0800101f10 00101f0000101f02 3 => 0
+vextublx 00101f0800101f10 00101f0000101f02 4 => 0
+vextublx 00101f0800101f10 00101f0000101f02 5 => 10
+vextublx 00101f0800101f10 00101f0000101f02 6 => 1f
+vextublx 00101f0800101f10 00101f0000101f02 7 => 2
+vextublx 00101f0800101f10 00101f0000101f02 8 => 0
+vextublx 00101f0800101f10 00101f0000101f02 9 => 10
+vextublx 00101f0800101f10 00101f0000101f02 10 => 1f
+vextublx 00101f0800101f10 00101f0000101f02 11 => 8
+vextublx 00101f0800101f10 00101f0000101f02 12 => 0
+vextublx 00101f0800101f10 00101f0000101f02 13 => 10
+vextublx 00101f0800101f10 00101f0000101f02 14 => 1f
+vextublx 00101f0800101f10 00101f0000101f02 15 => 10
+
+vextubrx 0000000000000000 0000000000000000 0 => 0
+vextubrx 0000000000000000 0000000000000000 1 => 0
+vextubrx 0000000000000000 0000000000000000 2 => 0
+vextubrx 0000000000000000 0000000000000000 3 => 0
+vextubrx 0000000000000000 0000000000000000 4 => 0
+vextubrx 0000000000000000 0000000000000000 5 => 0
+vextubrx 0000000000000000 0000000000000000 6 => 0
+vextubrx 0000000000000000 0000000000000000 7 => 0
+vextubrx 0000000000000000 0000000000000000 8 => 0
+vextubrx 0000000000000000 0000000000000000 9 => 0
+vextubrx 0000000000000000 0000000000000000 10 => 0
+vextubrx 0000000000000000 0000000000000000 11 => 0
+vextubrx 0000000000000000 0000000000000000 12 => 0
+vextubrx 0000000000000000 0000000000000000 13 => 0
+vextubrx 0000000000000000 0000000000000000 14 => 0
+vextubrx 0000000000000000 0000000000000000 15 => 0
+vextubrx 0102010201020102 0102030405060708 0 => 2
+vextubrx 0102010201020102 0102030405060708 1 => 1
+vextubrx 0102010201020102 0102030405060708 2 => 2
+vextubrx 0102010201020102 0102030405060708 3 => 1
+vextubrx 0102010201020102 0102030405060708 4 => 2
+vextubrx 0102010201020102 0102030405060708 5 => 1
+vextubrx 0102010201020102 0102030405060708 6 => 2
+vextubrx 0102010201020102 0102030405060708 7 => 1
+vextubrx 0102010201020102 0102030405060708 8 => 8
+vextubrx 0102010201020102 0102030405060708 9 => 7
+vextubrx 0102010201020102 0102030405060708 10 => 6
+vextubrx 0102010201020102 0102030405060708 11 => 5
+vextubrx 0102010201020102 0102030405060708 12 => 4
+vextubrx 0102010201020102 0102030405060708 13 => 3
+vextubrx 0102010201020102 0102030405060708 14 => 2
+vextubrx 0102010201020102 0102030405060708 15 => 1
+vextubrx 8899aabbccddeeff 0011223344556677 0 => ff
+vextubrx 8899aabbccddeeff 0011223344556677 1 => ee
+vextubrx 8899aabbccddeeff 0011223344556677 2 => dd
+vextubrx 8899aabbccddeeff 0011223344556677 3 => cc
+vextubrx 8899aabbccddeeff 0011223344556677 4 => bb
+vextubrx 8899aabbccddeeff 0011223344556677 5 => aa
+vextubrx 8899aabbccddeeff 0011223344556677 6 => 99
+vextubrx 8899aabbccddeeff 0011223344556677 7 => 88
+vextubrx 8899aabbccddeeff 0011223344556677 8 => 77
+vextubrx 8899aabbccddeeff 0011223344556677 9 => 66
+vextubrx 8899aabbccddeeff 0011223344556677 10 => 55
+vextubrx 8899aabbccddeeff 0011223344556677 11 => 44
+vextubrx 8899aabbccddeeff 0011223344556677 12 => 33
+vextubrx 8899aabbccddeeff 0011223344556677 13 => 22
+vextubrx 8899aabbccddeeff 0011223344556677 14 => 11
+vextubrx 8899aabbccddeeff 0011223344556677 15 => 0
+vextubrx 7060504030201000 f0e0d0c0b0a09080 0 => 0
+vextubrx 7060504030201000 f0e0d0c0b0a09080 1 => 10
+vextubrx 7060504030201000 f0e0d0c0b0a09080 2 => 20
+vextubrx 7060504030201000 f0e0d0c0b0a09080 3 => 30
+vextubrx 7060504030201000 f0e0d0c0b0a09080 4 => 40
+vextubrx 7060504030201000 f0e0d0c0b0a09080 5 => 50
+vextubrx 7060504030201000 f0e0d0c0b0a09080 6 => 60
+vextubrx 7060504030201000 f0e0d0c0b0a09080 7 => 70
+vextubrx 7060504030201000 f0e0d0c0b0a09080 8 => 80
+vextubrx 7060504030201000 f0e0d0c0b0a09080 9 => 90
+vextubrx 7060504030201000 f0e0d0c0b0a09080 10 => a0
+vextubrx 7060504030201000 f0e0d0c0b0a09080 11 => b0
+vextubrx 7060504030201000 f0e0d0c0b0a09080 12 => c0
+vextubrx 7060504030201000 f0e0d0c0b0a09080 13 => d0
+vextubrx 7060504030201000 f0e0d0c0b0a09080 14 => e0
+vextubrx 7060504030201000 f0e0d0c0b0a09080 15 => f0
+vextubrx 0000100800001010 0000100000001002 0 => 10
+vextubrx 0000100800001010 0000100000001002 1 => 10
+vextubrx 0000100800001010 0000100000001002 2 => 0
+vextubrx 0000100800001010 0000100000001002 3 => 0
+vextubrx 0000100800001010 0000100000001002 4 => 8
+vextubrx 0000100800001010 0000100000001002 5 => 10
+vextubrx 0000100800001010 0000100000001002 6 => 0
+vextubrx 0000100800001010 0000100000001002 7 => 0
+vextubrx 0000100800001010 0000100000001002 8 => 2
+vextubrx 0000100800001010 0000100000001002 9 => 10
+vextubrx 0000100800001010 0000100000001002 10 => 0
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+vextuwrx 0000100800001010 0000100000001002 12 => 1000
+vextuwrx 0000100800001010 0000100000001002 13 => 0
+vextuwrx 0000100800001010 0000100000001002 14 => 0
+vextuwrx 0000100800001010 0000100000001002 15 => 0
+vextuwrx 0010100800101010 0010100000101002 0 => 101010
+vextuwrx 0010100800101010 0010100000101002 1 => 8001010
+vextuwrx 0010100800101010 0010100000101002 2 => 10080010
+vextuwrx 0010100800101010 0010100000101002 3 => 10100800
+vextuwrx 0010100800101010 0010100000101002 4 => 101008
+vextuwrx 0010100800101010 0010100000101002 5 => 2001010
+vextuwrx 0010100800101010 0010100000101002 6 => 10020010
+vextuwrx 0010100800101010 0010100000101002 7 => 10100200
+vextuwrx 0010100800101010 0010100000101002 8 => 101002
+vextuwrx 0010100800101010 0010100000101002 9 => 1010
+vextuwrx 0010100800101010 0010100000101002 10 => 10000010
+vextuwrx 0010100800101010 0010100000101002 11 => 10100000
+vextuwrx 0010100800101010 0010100000101002 12 => 101000
+vextuwrx 0010100800101010 0010100000101002 13 => 0
+vextuwrx 0010100800101010 0010100000101002 14 => 0
+vextuwrx 0010100800101010 0010100000101002 15 => 0
+vextuwrx 00001c0800001c10 00001c0000001c02 0 => 1c10
+vextuwrx 00001c0800001c10 00001c0000001c02 1 => 800001c
+vextuwrx 00001c0800001c10 00001c0000001c02 2 => 1c080000
+vextuwrx 00001c0800001c10 00001c0000001c02 3 => 1c0800
+vextuwrx 00001c0800001c10 00001c0000001c02 4 => 1c08
+vextuwrx 00001c0800001c10 00001c0000001c02 5 => 200001c
+vextuwrx 00001c0800001c10 00001c0000001c02 6 => 1c020000
+vextuwrx 00001c0800001c10 00001c0000001c02 7 => 1c0200
+vextuwrx 00001c0800001c10 00001c0000001c02 8 => 1c02
+vextuwrx 00001c0800001c10 00001c0000001c02 9 => 1c
+vextuwrx 00001c0800001c10 00001c0000001c02 10 => 1c000000
+vextuwrx 00001c0800001c10 00001c0000001c02 11 => 1c0000
+vextuwrx 00001c0800001c10 00001c0000001c02 12 => 1c00
+vextuwrx 00001c0800001c10 00001c0000001c02 13 => 0
+vextuwrx 00001c0800001c10 00001c0000001c02 14 => 0
+vextuwrx 00001c0800001c10 00001c0000001c02 15 => 0
+vextuwrx 00101c0800101c10 00101c0000101c02 0 => 101c10
+vextuwrx 00101c0800101c10 00101c0000101c02 1 => 800101c
+vextuwrx 00101c0800101c10 00101c0000101c02 2 => 1c080010
+vextuwrx 00101c0800101c10 00101c0000101c02 3 => 101c0800
+vextuwrx 00101c0800101c10 00101c0000101c02 4 => 101c08
+vextuwrx 00101c0800101c10 00101c0000101c02 5 => 200101c
+vextuwrx 00101c0800101c10 00101c0000101c02 6 => 1c020010
+vextuwrx 00101c0800101c10 00101c0000101c02 7 => 101c0200
+vextuwrx 00101c0800101c10 00101c0000101c02 8 => 101c02
+vextuwrx 00101c0800101c10 00101c0000101c02 9 => 101c
+vextuwrx 00101c0800101c10 00101c0000101c02 10 => 1c000010
+vextuwrx 00101c0800101c10 00101c0000101c02 11 => 101c0000
+vextuwrx 00101c0800101c10 00101c0000101c02 12 => 101c00
+vextuwrx 00101c0800101c10 00101c0000101c02 13 => 0
+vextuwrx 00101c0800101c10 00101c0000101c02 14 => 0
+vextuwrx 00101c0800101c10 00101c0000101c02 15 => 0
+vextuwrx 00001f0800001f10 00001f0000001f02 0 => 1f10
+vextuwrx 00001f0800001f10 00001f0000001f02 1 => 800001f
+vextuwrx 00001f0800001f10 00001f0000001f02 2 => 1f080000
+vextuwrx 00001f0800001f10 00001f0000001f02 3 => 1f0800
+vextuwrx 00001f0800001f10 00001f0000001f02 4 => 1f08
+vextuwrx 00001f0800001f10 00001f0000001f02 5 => 200001f
+vextuwrx 00001f0800001f10 00001f0000001f02 6 => 1f020000
+vextuwrx 00001f0800001f10 00001f0000001f02 7 => 1f0200
+vextuwrx 00001f0800001f10 00001f0000001f02 8 => 1f02
+vextuwrx 00001f0800001f10 00001f0000001f02 9 => 1f
+vextuwrx 00001f0800001f10 00001f0000001f02 10 => 1f000000
+vextuwrx 00001f0800001f10 00001f0000001f02 11 => 1f0000
+vextuwrx 00001f0800001f10 00001f0000001f02 12 => 1f00
+vextuwrx 00001f0800001f10 00001f0000001f02 13 => 0
+vextuwrx 00001f0800001f10 00001f0000001f02 14 => 0
+vextuwrx 00001f0800001f10 00001f0000001f02 15 => 0
+vextuwrx 00101f0800101f10 00101f0000101f02 0 => 101f10
+vextuwrx 00101f0800101f10 00101f0000101f02 1 => 800101f
+vextuwrx 00101f0800101f10 00101f0000101f02 2 => 1f080010
+vextuwrx 00101f0800101f10 00101f0000101f02 3 => 101f0800
+vextuwrx 00101f0800101f10 00101f0000101f02 4 => 101f08
+vextuwrx 00101f0800101f10 00101f0000101f02 5 => 200101f
+vextuwrx 00101f0800101f10 00101f0000101f02 6 => 1f020010
+vextuwrx 00101f0800101f10 00101f0000101f02 7 => 101f0200
+vextuwrx 00101f0800101f10 00101f0000101f02 8 => 101f02
+vextuwrx 00101f0800101f10 00101f0000101f02 9 => 101f
+vextuwrx 00101f0800101f10 00101f0000101f02 10 => 1f000010
+vextuwrx 00101f0800101f10 00101f0000101f02 11 => 101f0000
+vextuwrx 00101f0800101f10 00101f0000101f02 12 => 101f00
+vextuwrx 00101f0800101f10 00101f0000101f02 13 => 0
+vextuwrx 00101f0800101f10 00101f0000101f02 14 => 0
+vextuwrx 00101f0800101f10 00101f0000101f02 15 => 0
+
+All done. Tested 106 different instructions
+ppc vector count leading/trailing bytes:
+Test instruction group [ppc vector count leading/trailing bytes]
+vclzlsbb 0000000000000000 0000000000000000 0 => 16
+vclzlsbb 0102010201020102 0102030405060708 0 => 0
+vclzlsbb 8899aabbccddeeff 0011223344556677 0 => 1
+vclzlsbb 7060504030201000 f0e0d0c0b0a09080 0 => 16
+vclzlsbb 0000100800001010 0000100000001002 0 => 16
+vclzlsbb 0010100800101010 0010100000101002 0 => 16
+vclzlsbb 00001c0800001c10 00001c0000001c02 0 => 16
+vclzlsbb 00101c0800101c10 00101c0000101c02 0 => 16
+vclzlsbb 00001f0800001f10 00001f0000001f02 0 => 2
+vclzlsbb 00101f0800101f10 00101f0000101f02 0 => 2
+
+vctzlsbb 0000000000000000 0000000000000000 0 => 16
+vctzlsbb 0102010201020102 0102030405060708 0 => 1
+vctzlsbb 8899aabbccddeeff 0011223344556677 0 => 0
+vctzlsbb 7060504030201000 f0e0d0c0b0a09080 0 => 16
+vctzlsbb 0000100800001010 0000100000001002 0 => 16
+vctzlsbb 0010100800101010 0010100000101002 0 => 16
+vctzlsbb 00001c0800001c10 00001c0000001c02 0 => 16
+vctzlsbb 00101c0800101c10 00101c0000101c02 0 => 16
+vctzlsbb 00001f0800001f10 00001f0000001f02 0 => 1
+vctzlsbb 00101f0800101f10 00101f0000101f02 0 => 1
+
+All done. Tested 108 different instructions
+ppc vector load/store:
+Test instruction group [ppc vector load/store]
+lxvl 0000000000000000 0000000000000000 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0000000000000000 0000000000000000 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0000000000000000 0000000000000000 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0000000000000000 0000000000000000 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0000000000000000 0000000000000000 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0000000000000000 0000000000000000 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0000000000000000 0000000000000000 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffff00000000 & 400000000000000
+lxvl 0000000000000000 0000000000000000 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020300000000 & 400000000000000
+lxvl 0000000000000000 0000000000000000 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555500000000 & 400000000000000
+lxvl 0000000000000000 0000000000000000 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 400000000000000
+lxvl 0000000000000000 0000000000000000 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffff00000000 & 400000000000000
+lxvl 0000000000000000 0000000000000000 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020300000000 & 400000000000000
+lxvl 0000000000000000 0000000000000000 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvl 0000000000000000 0000000000000000 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvl 0000000000000000 0000000000000000 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 800000000000000
+lxvl 0000000000000000 0000000000000000 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 800000000000000
+lxvl 0000000000000000 0000000000000000 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvl 0000000000000000 0000000000000000 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvl 0000000000000000 0000000000000000 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020300000000 ffffffffffffffff & c00000000000000
+lxvl 0000000000000000 0000000000000000 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555500000000 0001020304050607 & c00000000000000
+lxvl 0000000000000000 0000000000000000 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & c00000000000000
+lxvl 0000000000000000 0000000000000000 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffff00000000 0000000000000000 & c00000000000000
+lxvl 0000000000000000 0000000000000000 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020300000000 ffffffffffffffff & c00000000000000
+lxvl 0000000000000000 0000000000000000 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555500000000 0001020304050607 & c00000000000000
+lxvl 0000000000000000 0000000000000000 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvl 0000000000000000 0000000000000000 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvl 0000000000000000 0000000000000000 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 1000000000000000
+lxvl 0000000000000000 0000000000000000 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 1000000000000000
+lxvl 0000000000000000 0000000000000000 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvl 0000000000000000 0000000000000000 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvl 0102010201020102 0102030405060708 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0102010201020102 0102030405060708 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0102010201020102 0102030405060708 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0102010201020102 0102030405060708 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0102010201020102 0102030405060708 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0102010201020102 0102030405060708 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0102010201020102 0102030405060708 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffff00000000 & 400000000000000
+lxvl 0102010201020102 0102030405060708 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020300000000 & 400000000000000
+lxvl 0102010201020102 0102030405060708 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555500000000 & 400000000000000
+lxvl 0102010201020102 0102030405060708 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 400000000000000
+lxvl 0102010201020102 0102030405060708 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffff00000000 & 400000000000000
+lxvl 0102010201020102 0102030405060708 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020300000000 & 400000000000000
+lxvl 0102010201020102 0102030405060708 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvl 0102010201020102 0102030405060708 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvl 0102010201020102 0102030405060708 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 800000000000000
+lxvl 0102010201020102 0102030405060708 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 800000000000000
+lxvl 0102010201020102 0102030405060708 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvl 0102010201020102 0102030405060708 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvl 0102010201020102 0102030405060708 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020300000000 ffffffffffffffff & c00000000000000
+lxvl 0102010201020102 0102030405060708 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555500000000 0001020304050607 & c00000000000000
+lxvl 0102010201020102 0102030405060708 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & c00000000000000
+lxvl 0102010201020102 0102030405060708 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffff00000000 0000000000000000 & c00000000000000
+lxvl 0102010201020102 0102030405060708 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020300000000 ffffffffffffffff & c00000000000000
+lxvl 0102010201020102 0102030405060708 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555500000000 0001020304050607 & c00000000000000
+lxvl 0102010201020102 0102030405060708 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvl 0102010201020102 0102030405060708 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvl 0102010201020102 0102030405060708 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 1000000000000000
+lxvl 0102010201020102 0102030405060708 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 1000000000000000
+lxvl 0102010201020102 0102030405060708 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvl 0102010201020102 0102030405060708 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 8899aabbccddeeff 0011223344556677 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 8899aabbccddeeff 0011223344556677 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffff00000000 & 400000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020300000000 & 400000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555500000000 & 400000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 400000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffff00000000 & 400000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020300000000 & 400000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 800000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 800000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020300000000 ffffffffffffffff & c00000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555500000000 0001020304050607 & c00000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & c00000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffff00000000 0000000000000000 & c00000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020300000000 ffffffffffffffff & c00000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555500000000 0001020304050607 & c00000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 1000000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 1000000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffff00000000 & 400000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020300000000 & 400000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555500000000 & 400000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 400000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffff00000000 & 400000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020300000000 & 400000000000000
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+lxvll 00001f0800001f10 00001f0000001f02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffff00000000 & 400000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020300000000 & 400000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 800000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 800000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
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+lxvll 00001f0800001f10 00001f0000001f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555500000000 0001020304050607 & c00000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 1000000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 1000000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
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+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000005555 & c
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+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000405 & c
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+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000005555 & 10
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
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+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000001 & 10
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000005555 & 10
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
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+stxvl 0000000000000000 0000000000000000 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c00000000000000
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+stxvl 0000000000000000 0000000000000000 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvl 0000000000000000 0000000000000000 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvl 0000000000000000 0000000000000000 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvl 0000000000000000 0000000000000000 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvl 0000000000000000 0000000000000000 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 1000000000000000
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+stxvl 0102010201020102 0102030405060708 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 400000000000000
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+stxvl 0102010201020102 0102030405060708 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 400000000000000
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+stxvl 0102010201020102 0102030405060708 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 800000000000000
+stxvl 0102010201020102 0102030405060708 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 800000000000000
+stxvl 0102010201020102 0102030405060708 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 800000000000000
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+stxvl 0102010201020102 0102030405060708 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 800000000000000
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+stxvl 0102010201020102 0102030405060708 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c00000000000000
+stxvl 0102010201020102 0102030405060708 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & c00000000000000
+stxvl 0102010201020102 0102030405060708 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & c00000000000000
+stxvl 0102010201020102 0102030405060708 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & c00000000000000
+stxvl 0102010201020102 0102030405060708 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c00000000000000
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+stxvl 0102010201020102 0102030405060708 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 1000000000000000
+stxvl 0102010201020102 0102030405060708 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 1000000000000000
+stxvl 0102010201020102 0102030405060708 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 1000000000000000
+stxvl 0102010201020102 0102030405060708 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 1000000000000000
+stxvl 0102010201020102 0102030405060708 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 1000000000000000
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+stxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxvl 8899aabbccddeeff 0011223344556677 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxvl 8899aabbccddeeff 0011223344556677 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 400000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 400000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 400000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 400000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 400000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 400000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 800000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 800000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 800000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 800000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 800000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 800000000000000
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+stxvl 8899aabbccddeeff 0011223344556677 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & c00000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & c00000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & c00000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & c00000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & c00000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 1000000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 1000000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 1000000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 1000000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 1000000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 1000000000000000
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+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 400000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 400000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 400000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 400000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 400000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 400000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 800000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 800000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 800000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 800000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 800000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 800000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & c00000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & c00000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & c00000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & c00000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & c00000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & c00000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 1000000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 1000000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 1000000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 1000000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 1000000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 1000000000000000
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+stxvl 0000100800001010 0000100000001002 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 0
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+stxvl 0000100800001010 0000100000001002 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 0
+stxvl 0000100800001010 0000100000001002 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 0
+stxvl 0000100800001010 0000100000001002 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 400000000000000
+stxvl 0000100800001010 0000100000001002 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 400000000000000
+stxvl 0000100800001010 0000100000001002 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 400000000000000
+stxvl 0000100800001010 0000100000001002 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 400000000000000
+stxvl 0000100800001010 0000100000001002 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 400000000000000
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+stxvl 0000100800001010 0000100000001002 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 800000000000000
+stxvl 0000100800001010 0000100000001002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 800000000000000
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+stxvl 0000100800001010 0000100000001002 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 800000000000000
+stxvl 0000100800001010 0000100000001002 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 800000000000000
+stxvl 0000100800001010 0000100000001002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 800000000000000
+stxvl 0000100800001010 0000100000001002 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & c00000000000000
+stxvl 0000100800001010 0000100000001002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & c00000000000000
+stxvl 0000100800001010 0000100000001002 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & c00000000000000
+stxvl 0000100800001010 0000100000001002 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & c00000000000000
+stxvl 0000100800001010 0000100000001002 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & c00000000000000
+stxvl 0000100800001010 0000100000001002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & c00000000000000
+stxvl 0000100800001010 0000100000001002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 1000000000000000
+stxvl 0000100800001010 0000100000001002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 1000000000000000
+stxvl 0000100800001010 0000100000001002 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 1000000000000000
+stxvl 0000100800001010 0000100000001002 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 1000000000000000
+stxvl 0000100800001010 0000100000001002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 1000000000000000
+stxvl 0000100800001010 0000100000001002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 1000000000000000
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+stxvl 0010100800101010 0010100000101002 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 0
+stxvl 0010100800101010 0010100000101002 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 0
+stxvl 0010100800101010 0010100000101002 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 0
+stxvl 0010100800101010 0010100000101002 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 400000000000000
+stxvl 0010100800101010 0010100000101002 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 400000000000000
+stxvl 0010100800101010 0010100000101002 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 400000000000000
+stxvl 0010100800101010 0010100000101002 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 400000000000000
+stxvl 0010100800101010 0010100000101002 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 400000000000000
+stxvl 0010100800101010 0010100000101002 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 400000000000000
+stxvl 0010100800101010 0010100000101002 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 800000000000000
+stxvl 0010100800101010 0010100000101002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 800000000000000
+stxvl 0010100800101010 0010100000101002 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 800000000000000
+stxvl 0010100800101010 0010100000101002 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 800000000000000
+stxvl 0010100800101010 0010100000101002 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 800000000000000
+stxvl 0010100800101010 0010100000101002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 800000000000000
+stxvl 0010100800101010 0010100000101002 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & c00000000000000
+stxvl 0010100800101010 0010100000101002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c00000000000000
+stxvl 0010100800101010 0010100000101002 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & c00000000000000
+stxvl 0010100800101010 0010100000101002 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & c00000000000000
+stxvl 0010100800101010 0010100000101002 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & c00000000000000
+stxvl 0010100800101010 0010100000101002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c00000000000000
+stxvl 0010100800101010 0010100000101002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 1000000000000000
+stxvl 0010100800101010 0010100000101002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 1000000000000000
+stxvl 0010100800101010 0010100000101002 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 1000000000000000
+stxvl 0010100800101010 0010100000101002 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 1000000000000000
+stxvl 0010100800101010 0010100000101002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 1000000000000000
+stxvl 0010100800101010 0010100000101002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 1000000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxvl 00001c0800001c10 00001c0000001c02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxvl 00001c0800001c10 00001c0000001c02 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxvl 00001c0800001c10 00001c0000001c02 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxvl 00001c0800001c10 00001c0000001c02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxvl 00001c0800001c10 00001c0000001c02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxvl 00001c0800001c10 00001c0000001c02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 400000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 400000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 400000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 400000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 400000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 400000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 800000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 800000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 800000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 800000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 800000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 800000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & c00000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c00000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & c00000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & c00000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & c00000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c00000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 1000000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 1000000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 1000000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 1000000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 1000000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 1000000000000000
+stxvl 00101c0800101c10 00101c0000101c02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 0
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+stxvl 00101c0800101c10 00101c0000101c02 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 0
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+stxvl 00001f0800001f10 00001f0000001f02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c00000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c00000000000000
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+stxvl 00001f0800001f10 00001f0000001f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 1000000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 1000000000000000
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+stxvl 00001f0800001f10 00001f0000001f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 1000000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 1000000000000000
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+stxvl 00101f0800101f10 00101f0000101f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 400000000000000
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+stxvl 00101f0800101f10 00101f0000101f02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 400000000000000
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+stxvl 00101f0800101f10 00101f0000101f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 400000000000000
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+stxvl 00101f0800101f10 00101f0000101f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 800000000000000
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+stxvl 00101f0800101f10 00101f0000101f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 800000000000000
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+stxvl 00101f0800101f10 00101f0000101f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & c00000000000000
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+stxvl 00101f0800101f10 00101f0000101f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 1000000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 1000000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 1000000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 1000000000000000
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+stxvll 0000000000000000 0000000000000000 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvll 0000000000000000 0000000000000000 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvll 0000000000000000 0000000000000000 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvll 0000000000000000 0000000000000000 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 1000000000000000
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+stxvll 0102010201020102 0102030405060708 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 0
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+stxvll 0102010201020102 0102030405060708 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 400000000000000
+stxvll 0102010201020102 0102030405060708 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 400000000000000
+stxvll 0102010201020102 0102030405060708 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 400000000000000
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+stxvll 0102010201020102 0102030405060708 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 400000000000000
+stxvll 0102010201020102 0102030405060708 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 800000000000000
+stxvll 0102010201020102 0102030405060708 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 800000000000000
+stxvll 0102010201020102 0102030405060708 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 800000000000000
+stxvll 0102010201020102 0102030405060708 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 800000000000000
+stxvll 0102010201020102 0102030405060708 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 800000000000000
+stxvll 0102010201020102 0102030405060708 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 800000000000000
+stxvll 0102010201020102 0102030405060708 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & c00000000000000
+stxvll 0102010201020102 0102030405060708 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c00000000000000
+stxvll 0102010201020102 0102030405060708 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & c00000000000000
+stxvll 0102010201020102 0102030405060708 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & c00000000000000
+stxvll 0102010201020102 0102030405060708 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & c00000000000000
+stxvll 0102010201020102 0102030405060708 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c00000000000000
+stxvll 0102010201020102 0102030405060708 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 1000000000000000
+stxvll 0102010201020102 0102030405060708 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 1000000000000000
+stxvll 0102010201020102 0102030405060708 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 1000000000000000
+stxvll 0102010201020102 0102030405060708 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 1000000000000000
+stxvll 0102010201020102 0102030405060708 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 1000000000000000
+stxvll 0102010201020102 0102030405060708 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 1000000000000000
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+stxvll 8899aabbccddeeff 0011223344556677 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 800000000000000
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+stxvll 8899aabbccddeeff 0011223344556677 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 1000000000000000
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+stxvll 8899aabbccddeeff 0011223344556677 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 1000000000000000
+stxvll 8899aabbccddeeff 0011223344556677 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 1000000000000000
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+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 400000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 400000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 400000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 400000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 400000000000000
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+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 800000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 800000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 800000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 800000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 800000000000000
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+stxvll 7060504030201000 f0e0d0c0b0a09080 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & c00000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & c00000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & c00000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & c00000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & c00000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 1000000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 1000000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 1000000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 1000000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 1000000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 1000000000000000
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+stxvll 0000100800001010 0000100000001002 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 800000000000000
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+stxvll 0000100800001010 0000100000001002 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 800000000000000
+stxvll 0000100800001010 0000100000001002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 800000000000000
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+stxvll 0000100800001010 0000100000001002 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & c00000000000000
+stxvll 0000100800001010 0000100000001002 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & c00000000000000
+stxvll 0000100800001010 0000100000001002 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & c00000000000000
+stxvll 0000100800001010 0000100000001002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & c00000000000000
+stxvll 0000100800001010 0000100000001002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 1000000000000000
+stxvll 0000100800001010 0000100000001002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 1000000000000000
+stxvll 0000100800001010 0000100000001002 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 1000000000000000
+stxvll 0000100800001010 0000100000001002 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 1000000000000000
+stxvll 0000100800001010 0000100000001002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 1000000000000000
+stxvll 0000100800001010 0000100000001002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 1000000000000000
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+stxvll 0010100800101010 0010100000101002 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 0
+stxvll 0010100800101010 0010100000101002 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 400000000000000
+stxvll 0010100800101010 0010100000101002 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 400000000000000
+stxvll 0010100800101010 0010100000101002 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 400000000000000
+stxvll 0010100800101010 0010100000101002 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 400000000000000
+stxvll 0010100800101010 0010100000101002 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 400000000000000
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+stxvll 0010100800101010 0010100000101002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 800000000000000
+stxvll 0010100800101010 0010100000101002 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 800000000000000
+stxvll 0010100800101010 0010100000101002 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 800000000000000
+stxvll 0010100800101010 0010100000101002 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 800000000000000
+stxvll 0010100800101010 0010100000101002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 800000000000000
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+stxvll 0010100800101010 0010100000101002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c00000000000000
+stxvll 0010100800101010 0010100000101002 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & c00000000000000
+stxvll 0010100800101010 0010100000101002 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & c00000000000000
+stxvll 0010100800101010 0010100000101002 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & c00000000000000
+stxvll 0010100800101010 0010100000101002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c00000000000000
+stxvll 0010100800101010 0010100000101002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 1000000000000000
+stxvll 0010100800101010 0010100000101002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 1000000000000000
+stxvll 0010100800101010 0010100000101002 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 1000000000000000
+stxvll 0010100800101010 0010100000101002 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 1000000000000000
+stxvll 0010100800101010 0010100000101002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 1000000000000000
+stxvll 0010100800101010 0010100000101002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 1000000000000000
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+stxvll 00001c0800001c10 00001c0000001c02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxvll 00001c0800001c10 00001c0000001c02 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxvll 00001c0800001c10 00001c0000001c02 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxvll 00001c0800001c10 00001c0000001c02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxvll 00001c0800001c10 00001c0000001c02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxvll 00001c0800001c10 00001c0000001c02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 400000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 400000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 400000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 400000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 400000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 400000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 800000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 800000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 800000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 800000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 800000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 800000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & c00000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c00000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & c00000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & c00000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & c00000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c00000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 1000000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 1000000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 1000000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 1000000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 1000000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 1000000000000000
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+stxvll 00101c0800101c10 00101c0000101c02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 400000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 400000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 400000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 400000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 400000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 800000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 800000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 800000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 800000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 800000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 800000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & c00000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & c00000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & c00000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & c00000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & c00000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & c00000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 1000000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 1000000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 1000000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 1000000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 1000000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 1000000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxvll 00001f0800001f10 00001f0000001f02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxvll 00001f0800001f10 00001f0000001f02 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxvll 00001f0800001f10 00001f0000001f02 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxvll 00001f0800001f10 00001f0000001f02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxvll 00001f0800001f10 00001f0000001f02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxvll 00001f0800001f10 00001f0000001f02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 400000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 400000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 400000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 400000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 400000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 400000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 800000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 800000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 800000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 800000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 800000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 800000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c00000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c00000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & c00000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & c00000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c00000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c00000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 1000000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 1000000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 1000000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 1000000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 1000000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 1000000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxvll 00101f0800101f10 00101f0000101f02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxvll 00101f0800101f10 00101f0000101f02 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxvll 00101f0800101f10 00101f0000101f02 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxvll 00101f0800101f10 00101f0000101f02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxvll 00101f0800101f10 00101f0000101f02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxvll 00101f0800101f10 00101f0000101f02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 400000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 400000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 400000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 400000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 400000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 400000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 800000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 800000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 800000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 800000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 800000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 800000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & c00000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & c00000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & c00000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & c00000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & c00000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & c00000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 1000000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 1000000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 1000000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 1000000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 1000000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 1000000000000000
+
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+stxsibx 0000000000000000 0000000000000000 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 4
+stxsibx 0000000000000000 0000000000000000 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 4
+stxsibx 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+stxsibx 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
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+stxsibx 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+stxsibx 0000000000000000 0000000000000000 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 8
+stxsibx 0000000000000000 0000000000000000 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 8
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+stxsibx 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 8
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+stxsibx 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 8
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+stxsibx 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c
+stxsibx 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & c
+stxsibx 0102010201020102 0102030405060708 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & c
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+stxsibx 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 10
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+stxsibx 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 4
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+stxsibx 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 4
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+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 4
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+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 4
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+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 8
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+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 10
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+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & c
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & c
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & c
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & c
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & c
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & c
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 10
+
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+stxsihx 0000000000000000 0000000000000000 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+stxsihx 0000000000000000 0000000000000000 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+stxsihx 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+stxsihx 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxsihx 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+stxsihx 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+stxsihx 0000000000000000 0000000000000000 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 4
+stxsihx 0000000000000000 0000000000000000 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 4
+stxsihx 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+stxsihx 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+stxsihx 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+stxsihx 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+stxsihx 0000000000000000 0000000000000000 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 8
+stxsihx 0000000000000000 0000000000000000 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 8
+stxsihx 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+stxsihx 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+stxsihx 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+stxsihx 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+stxsihx 0000000000000000 0000000000000000 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & c
+stxsihx 0000000000000000 0000000000000000 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & c
+stxsihx 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+stxsihx 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+stxsihx 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+stxsihx 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+stxsihx 0000000000000000 0000000000000000 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 10
+stxsihx 0000000000000000 0000000000000000 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 10
+stxsihx 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+stxsihx 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
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+stxsihx 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 0
+stxsihx 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 4
+stxsihx 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 4
+stxsihx 0102010201020102 0102030405060708 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 4
+stxsihx 0102010201020102 0102030405060708 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 4
+stxsihx 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 4
+stxsihx 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 4
+stxsihx 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 8
+stxsihx 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 8
+stxsihx 0102010201020102 0102030405060708 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 8
+stxsihx 0102010201020102 0102030405060708 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 8
+stxsihx 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 8
+stxsihx 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 8
+stxsihx 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & c
+stxsihx 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c
+stxsihx 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & c
+stxsihx 0102010201020102 0102030405060708 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & c
+stxsihx 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & c
+stxsihx 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c
+stxsihx 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 10
+stxsihx 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 10
+stxsihx 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 10
+stxsihx 0102010201020102 0102030405060708 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 10
+stxsihx 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 10
+stxsihx 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 10
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+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 8
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 8
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 8
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 8
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 8
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 8
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & c
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & c
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & c
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & c
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & c
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & c
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 10
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+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
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+stxsihx 0010100800101010 0010100000101002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & c
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+stxsihx 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c
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+stxsihx 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 10
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+stxsihx 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 10
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+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 8
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+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 8
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+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 8
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+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & c
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & c
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+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c
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+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 10
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+lxssp 0 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 0
+lxssp 0 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 4
+lxssp 0 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 4
+lxssp 0 0102010201020102 0102030405060708 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 4
+lxssp 0 0102010201020102 0102030405060708 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 4
+lxssp 0 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 4
+lxssp 0 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 4
+lxssp 0 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 8
+lxssp 0 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 8
+lxssp 0 0102010201020102 0102030405060708 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 8
+lxssp 0 0102010201020102 0102030405060708 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 8
+lxssp 0 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 8
+lxssp 0 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 8
+lxssp 0 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & c
+lxssp 0 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c
+lxssp 0 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & c
+lxssp 0 0102010201020102 0102030405060708 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & c
+lxssp 0 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & c
+lxssp 0 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c
+lxssp 0 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 10
+lxssp 0 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 10
+lxssp 0 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 10
+lxssp 0 0102010201020102 0102030405060708 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 10
+lxssp 0 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 10
+lxssp 0 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 10
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 0
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 0
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 0
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 0
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 0
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 0
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 4
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 4
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 4
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 4
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 4
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 4
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 8
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 8
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 8
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 8
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 8
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 8
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & c
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & c
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & c
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & c
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & c
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & c
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 10
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 10
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 10
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 10
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 10
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 10
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
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+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+lxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 0
+lxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 0
+lxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 0
+lxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 0
+lxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 0
+lxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 0
+lxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 4
+lxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 4
+lxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 4
+lxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 4
+lxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 4
+lxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 4
+lxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 8
+lxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 8
+lxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 8
+lxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 8
+lxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 8
+lxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 8
+lxssp 0 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & c
+lxssp 0 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & c
+lxssp 0 0000100800001010 0000100000001002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & c
+lxssp 0 0000100800001010 0000100000001002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & c
+lxssp 0 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & c
+lxssp 0 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & c
+lxssp 0 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 10
+lxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 10
+lxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 10
+lxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 10
+lxssp 0 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 10
+lxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 10
+lxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 0
+lxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 0
+lxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 0
+lxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 0
+lxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 0
+lxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 0
+lxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 4
+lxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 4
+lxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 4
+lxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 4
+lxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 4
+lxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 4
+lxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 8
+lxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 8
+lxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 8
+lxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 8
+lxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 8
+lxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 8
+lxssp 0 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & c
+lxssp 0 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c
+lxssp 0 0010100800101010 0010100000101002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & c
+lxssp 0 0010100800101010 0010100000101002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & c
+lxssp 0 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & c
+lxssp 0 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c
+lxssp 0 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 10
+lxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 10
+lxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 10
+lxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 10
+lxssp 0 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 10
+lxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 10
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 0
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 0
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 0
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 0
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 0
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 0
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 4
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 4
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 4
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 4
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 4
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 4
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 8
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 8
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 8
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 8
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 8
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 8
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & c
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & c
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & c
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & c
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 10
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 10
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 10
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 10
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 10
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 10
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 0
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 0
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 0
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 0
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 0
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 0
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 4
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 4
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 4
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 4
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 4
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 4
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 8
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 8
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 8
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 8
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 8
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 8
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & c
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & c
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & c
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & c
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & c
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & c
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 10
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 10
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 10
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 10
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 10
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 10
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 0
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 0
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 0
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 0
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 0
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 0
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 4
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 4
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 4
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 4
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 4
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 4
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 8
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 8
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 8
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 8
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 8
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 8
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & c
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & c
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 10
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 10
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 10
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 10
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 10
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 10
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 0
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 0
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 0
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 0
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 0
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 0
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 4
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 4
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 4
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 4
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 4
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 4
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 8
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 8
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 8
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 8
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 8
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 8
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & c
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+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & c
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+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & c
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+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 10
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 10
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 10
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 10
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 10
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 10
+
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+stxssp 0 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 4
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+stxssp 0 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 8
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+stxssp 0 0102010201020102 0102030405060708 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 8
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+stxssp 0 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 8
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+stxssp 0 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c
+stxssp 0 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & c
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+stxssp 0 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & c
+stxssp 0 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c
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+stxssp 0 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 10
+stxssp 0 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 10
+stxssp 0 0102010201020102 0102030405060708 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 10
+stxssp 0 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 10
+stxssp 0 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 10
+stxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 0
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+stxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 0
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+stxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 4
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+stxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 4
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+stxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 8
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+stxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 8
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+stxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 10
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+stxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 10
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+stxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
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+stxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+stxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+stxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+stxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+stxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+stxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+stxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+stxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+stxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+stxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
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+stxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 0
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+stxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 0
+stxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 0
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+stxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 4
+stxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 4
+stxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 4
+stxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 4
+stxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 4
+stxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 8
+stxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 8
+stxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 8
+stxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 8
+stxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 8
+stxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 8
+stxssp 0 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & c
+stxssp 0 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & c
+stxssp 0 0000100800001010 0000100000001002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & c
+stxssp 0 0000100800001010 0000100000001002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & c
+stxssp 0 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & c
+stxssp 0 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & c
+stxssp 0 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 10
+stxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 10
+stxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 10
+stxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 10
+stxssp 0 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 10
+stxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 10
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+stxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 4
+stxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 4
+stxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 4
+stxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 4
+stxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 4
+stxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 8
+stxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 8
+stxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 8
+stxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 8
+stxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 8
+stxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 8
+stxssp 0 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & c
+stxssp 0 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c
+stxssp 0 0010100800101010 0010100000101002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & c
+stxssp 0 0010100800101010 0010100000101002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & c
+stxssp 0 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & c
+stxssp 0 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c
+stxssp 0 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 10
+stxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 10
+stxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 10
+stxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 10
+stxssp 0 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 10
+stxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 10
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+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 0
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+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & c
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & c
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & c
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & c
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & c
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & c
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & c
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & c
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & c
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & c
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & c
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & c
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & c
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & c
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & c
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & c
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 10
+
+lxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+lxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+lxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+lxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+lxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 4
+lxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 4
+lxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+lxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+lxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+lxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+lxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 8
+lxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 8
+lxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+lxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+lxssp 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+lxssp 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+lxssp 16 0000000000000000 0000000000000000 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & c
+lxssp 16 0000000000000000 0000000000000000 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & c
+lxssp 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+lxssp 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+lxssp 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+lxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+lxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 10
+lxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 10
+lxssp 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+lxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+lxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 0
+lxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 0
+lxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 0
+lxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 0
+lxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 0
+lxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 0
+lxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 4
+lxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 4
+lxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 4
+lxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 4
+lxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 4
+lxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 4
+lxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 8
+lxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 8
+lxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 8
+lxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 8
+lxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 8
+lxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 8
+lxssp 16 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & c
+lxssp 16 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c
+lxssp 16 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & c
+lxssp 16 0102010201020102 0102030405060708 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & c
+lxssp 16 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & c
+lxssp 16 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c
+lxssp 16 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 10
+lxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 10
+lxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 10
+lxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 10
+lxssp 16 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 10
+lxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 10
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 0
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 0
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 0
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 0
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 0
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 0
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 4
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 4
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 4
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 4
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 4
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 4
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 8
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 8
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 8
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 8
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 8
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 8
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & c
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & c
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & c
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & c
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & c
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & c
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 10
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 10
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 10
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 10
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 10
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 10
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+lxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 0
+lxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 0
+lxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 0
+lxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 0
+lxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 0
+lxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 0
+lxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 4
+lxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 4
+lxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 4
+lxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 4
+lxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 4
+lxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 4
+lxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 8
+lxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 8
+lxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 8
+lxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 8
+lxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 8
+lxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 8
+lxssp 16 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & c
+lxssp 16 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & c
+lxssp 16 0000100800001010 0000100000001002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & c
+lxssp 16 0000100800001010 0000100000001002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & c
+lxssp 16 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & c
+lxssp 16 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & c
+lxssp 16 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 10
+lxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 10
+lxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 10
+lxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 10
+lxssp 16 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 10
+lxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 10
+lxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 0
+lxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 0
+lxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 0
+lxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 0
+lxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 0
+lxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 0
+lxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 4
+lxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 4
+lxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 4
+lxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 4
+lxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 4
+lxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 4
+lxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 8
+lxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 8
+lxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 8
+lxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 8
+lxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 8
+lxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 8
+lxssp 16 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & c
+lxssp 16 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c
+lxssp 16 0010100800101010 0010100000101002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & c
+lxssp 16 0010100800101010 0010100000101002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & c
+lxssp 16 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & c
+lxssp 16 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c
+lxssp 16 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 10
+lxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 10
+lxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 10
+lxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 10
+lxssp 16 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 10
+lxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 10
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 0
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 0
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 0
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 0
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 0
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 0
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 4
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 4
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 4
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 4
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 4
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 4
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 8
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 8
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 8
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 8
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 8
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 8
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & c
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & c
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & c
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & c
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 10
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 10
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 10
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 10
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 10
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 10
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 0
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 0
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 0
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 0
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 0
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 0
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 4
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 4
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 4
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 4
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 4
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 4
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 8
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 8
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 8
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 8
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 8
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 8
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & c
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & c
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & c
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & c
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & c
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & c
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 10
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 10
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 10
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 10
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 10
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 10
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 0
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 0
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 0
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 0
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 0
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 0
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 4
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 4
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 4
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 4
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 4
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 4
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 8
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 8
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 8
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 8
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 8
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 8
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & c
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & c
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 10
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 10
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 10
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 10
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 10
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 10
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 0
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 0
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 0
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 0
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 0
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 0
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 4
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 4
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 4
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 4
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 4
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 4
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 8
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 8
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 8
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 8
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 8
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 8
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & c
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & c
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & c
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & c
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & c
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & c
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 10
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 10
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 10
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 10
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 10
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 10
+
+stxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+stxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+stxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+stxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+stxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+stxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+stxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 4
+stxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 4
+stxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+stxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+stxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+stxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+stxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 8
+stxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 8
+stxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+stxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+stxssp 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+stxssp 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+stxssp 16 0000000000000000 0000000000000000 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & c
+stxssp 16 0000000000000000 0000000000000000 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & c
+stxssp 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+stxssp 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+stxssp 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+stxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+stxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 10
+stxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 10
+stxssp 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+stxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+stxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 0
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+stxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 4
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+stxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 8
+stxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 8
+stxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 8
+stxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 8
+stxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 8
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+stxssp 16 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c
+stxssp 16 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & c
+stxssp 16 0102010201020102 0102030405060708 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & c
+stxssp 16 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & c
+stxssp 16 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c
+stxssp 16 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 10
+stxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 10
+stxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 10
+stxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 10
+stxssp 16 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 10
+stxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 10
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+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 4
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+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 4
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+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 8
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 8
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+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 10
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+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
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+stxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 0
+stxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 0
+stxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 0
+stxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 0
+stxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 4
+stxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 4
+stxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 4
+stxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 4
+stxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 4
+stxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 4
+stxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 8
+stxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 8
+stxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 8
+stxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 8
+stxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 8
+stxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 8
+stxssp 16 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & c
+stxssp 16 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & c
+stxssp 16 0000100800001010 0000100000001002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & c
+stxssp 16 0000100800001010 0000100000001002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & c
+stxssp 16 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & c
+stxssp 16 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & c
+stxssp 16 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 10
+stxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 10
+stxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 10
+stxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 10
+stxssp 16 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 10
+stxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 10
+stxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 0
+stxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 0
+stxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 0
+stxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 0
+stxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 0
+stxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 0
+stxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 4
+stxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 4
+stxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 4
+stxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 4
+stxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 4
+stxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 4
+stxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 8
+stxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 8
+stxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 8
+stxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 8
+stxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 8
+stxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 8
+stxssp 16 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & c
+stxssp 16 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c
+stxssp 16 0010100800101010 0010100000101002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & c
+stxssp 16 0010100800101010 0010100000101002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & c
+stxssp 16 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & c
+stxssp 16 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c
+stxssp 16 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 10
+stxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 10
+stxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 10
+stxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 10
+stxssp 16 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 10
+stxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 10
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & c
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & c
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & c
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & c
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & c
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & c
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & c
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & c
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & c
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & c
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 8
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+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & c
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & c
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+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 10
+
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+lxv 0 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 0
+lxv 0 0000000000000000 0000000000000000 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 0
+lxv 0 0000000000000000 0000000000000000 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 0
+lxv 0 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 0
+lxv 0 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 0
+lxv 0 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 0 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 4
+lxv 0 0000000000000000 0000000000000000 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 4
+lxv 0 0000000000000000 0000000000000000 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 0 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 0 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 4
+lxv 0 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 0 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
+lxv 0 0000000000000000 0000000000000000 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 8
+lxv 0 0000000000000000 0000000000000000 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 0 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 0 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
+lxv 0 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 0 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & c
+lxv 0 0000000000000000 0000000000000000 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & c
+lxv 0 0000000000000000 0000000000000000 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & c
+lxv 0 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 0 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & c
+lxv 0 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 0 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 10
+lxv 0 0000000000000000 0000000000000000 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 10
+lxv 0 0000000000000000 0000000000000000 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 0 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 0 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 10
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+lxv 0 0102010201020102 0102030405060708 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 4
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+lxv 0 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 0 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 4
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+lxv 0 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
+lxv 0 0102010201020102 0102030405060708 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 8
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+lxv 0 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 0 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
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+lxv 0 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & c
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+lxv 0 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & c
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+lxv 0 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 10
+lxv 0 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 10
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+lxv 0 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 10
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+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 4
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+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 4
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+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 8
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
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+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & c
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+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 10
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+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 10
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+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 4
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+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
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+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 8
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+lxv 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 10
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+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 8
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+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 8
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+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c
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+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 10
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+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 10
+
+lxv 16 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 0
+lxv 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 0
+lxv 16 0000000000000000 0000000000000000 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 0
+lxv 16 0000000000000000 0000000000000000 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 0
+lxv 16 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 0
+lxv 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 0
+lxv 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 4
+lxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 4
+lxv 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 4
+lxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 8
+lxv 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 0000000000000000 0000000000000000 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 16 0000000000000000 0000000000000000 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & c
+lxv 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 16 0000000000000000 0000000000000000 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 16 0000000000000000 0000000000000000 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 10
+lxv 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 0
+lxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 0
+lxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 0
+lxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 0
+lxv 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 0
+lxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 0
+lxv 16 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 4
+lxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 4
+lxv 16 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 4
+lxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 16 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
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+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 4
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+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 4
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 8
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+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
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+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & c
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+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 10
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
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+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
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+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 8
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
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+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
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+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 10
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+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
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+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 8
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+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
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+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
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+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 10
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
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+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
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+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
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+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 8
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
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+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & c
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+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 10
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+
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+stxv 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
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+stxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+stxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 4
+stxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 4
+stxv 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+stxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+stxv 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+stxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+stxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 8
+stxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 8
+stxv 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+stxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+stxv 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+stxv 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+stxv 16 0000000000000000 0000000000000000 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & c
+stxv 16 0000000000000000 0000000000000000 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & c
+stxv 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+stxv 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+stxv 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+stxv 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+stxv 16 0000000000000000 0000000000000000 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 10
+stxv 16 0000000000000000 0000000000000000 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 10
+stxv 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+stxv 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+stxv 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 0
+stxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 0
+stxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 0
+stxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 0
+stxv 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 0
+stxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 0
+stxv 16 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 4
+stxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 4
+stxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 4
+stxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 4
+stxv 16 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 4
+stxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 4
+stxv 16 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 8
+stxv 16 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 8
+stxv 16 0102010201020102 0102030405060708 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 8
+stxv 16 0102010201020102 0102030405060708 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 8
+stxv 16 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 8
+stxv 16 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 8
+stxv 16 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & c
+stxv 16 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c
+stxv 16 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & c
+stxv 16 0102010201020102 0102030405060708 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & c
+stxv 16 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & c
+stxv 16 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & c
+stxv 16 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 10
+stxv 16 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 10
+stxv 16 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102010201020102 0102030405060708 & 10
+stxv 16 0102010201020102 0102030405060708 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102010201020102 0102030405060708 & 10
+stxv 16 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102010201020102 0102030405060708 & 10
+stxv 16 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102010201020102 0102030405060708 & 10
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 0
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 4
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 8
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 8
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 8
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 8
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 8
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 8
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & c
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & c
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & c
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & c
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & c
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & c
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 8899aabbccddeeff 0011223344556677 & 10
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 0
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 4
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 8
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & c
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 7060504030201000 f0e0d0c0b0a09080 & 10
+stxv 16 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 0
+stxv 16 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 0
+stxv 16 0000100800001010 0000100000001002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 0
+stxv 16 0000100800001010 0000100000001002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 0
+stxv 16 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 0
+stxv 16 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 0
+stxv 16 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 4
+stxv 16 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 4
+stxv 16 0000100800001010 0000100000001002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 4
+stxv 16 0000100800001010 0000100000001002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 4
+stxv 16 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 4
+stxv 16 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 4
+stxv 16 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 8
+stxv 16 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 8
+stxv 16 0000100800001010 0000100000001002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 8
+stxv 16 0000100800001010 0000100000001002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 8
+stxv 16 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 8
+stxv 16 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 8
+stxv 16 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & c
+stxv 16 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & c
+stxv 16 0000100800001010 0000100000001002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & c
+stxv 16 0000100800001010 0000100000001002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & c
+stxv 16 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & c
+stxv 16 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & c
+stxv 16 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 10
+stxv 16 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 10
+stxv 16 0000100800001010 0000100000001002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100800001010 0000100000001002 & 10
+stxv 16 0000100800001010 0000100000001002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100800001010 0000100000001002 & 10
+stxv 16 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100800001010 0000100000001002 & 10
+stxv 16 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100800001010 0000100000001002 & 10
+stxv 16 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 0
+stxv 16 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 0
+stxv 16 0010100800101010 0010100000101002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 0
+stxv 16 0010100800101010 0010100000101002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 0
+stxv 16 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 0
+stxv 16 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 0
+stxv 16 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 4
+stxv 16 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 4
+stxv 16 0010100800101010 0010100000101002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 4
+stxv 16 0010100800101010 0010100000101002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 4
+stxv 16 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 4
+stxv 16 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 4
+stxv 16 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 8
+stxv 16 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 8
+stxv 16 0010100800101010 0010100000101002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 8
+stxv 16 0010100800101010 0010100000101002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 8
+stxv 16 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 8
+stxv 16 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 8
+stxv 16 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & c
+stxv 16 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c
+stxv 16 0010100800101010 0010100000101002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & c
+stxv 16 0010100800101010 0010100000101002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & c
+stxv 16 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & c
+stxv 16 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & c
+stxv 16 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 10
+stxv 16 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 10
+stxv 16 0010100800101010 0010100000101002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100800101010 0010100000101002 & 10
+stxv 16 0010100800101010 0010100000101002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100800101010 0010100000101002 & 10
+stxv 16 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100800101010 0010100000101002 & 10
+stxv 16 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100800101010 0010100000101002 & 10
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 0
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 4
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 8
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & c
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & c
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & c
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & c
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & c
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0800001c10 00001c0000001c02 & 10
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 0
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 4
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 8
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & c
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & c
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & c
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & c
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & c
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & c
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0800101c10 00101c0000101c02 & 10
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 0
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 4
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 8
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & c
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & c
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0800001f10 00001f0000001f02 & 10
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 0
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 4
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 8
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & c
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & c
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & c
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & c
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & c
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & c
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0800101f10 00101f0000101f02 & 10
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0800101f10 00101f0000101f02 & 10
+
+All done. Tested 128 different instructions
+ppc vector load/store:
+Test instruction group [ppc vector load/store]
+lxvx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0102010201020102 0102030405060708 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 8899aabbccddeeff 0011223344556677 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 7060504030201000 f0e0d0c0b0a09080 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0000100800001010 0000100000001002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0010100800101010 0010100000101002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 00001c0800001c10 00001c0000001c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 00101c0800101c10 00101c0000101c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 00001f0800001f10 00001f0000001f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 00101f0800101f10 00101f0000101f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 5555555555555555 0001020304050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 0000000000000000 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 0000000000000000 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ ffffffffffffffff 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx ffffffffffffffff 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 0001020304050607 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx 0001020304050607 ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 5555555555555555 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020300010203 0001020300010203 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0001020300010203 0001020300010203 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvwsx 5555555555555555 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020300010203 0001020300010203 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0102010201020102 0102030405060708 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020300010203 0001020300010203 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0001020300010203 0001020300010203 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvwsx 5555555555555555 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020300010203 0001020300010203 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 8899aabbccddeeff 0011223344556677 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020300010203 0001020300010203 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0001020300010203 0001020300010203 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvwsx 5555555555555555 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020300010203 0001020300010203 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 7060504030201000 f0e0d0c0b0a09080 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020300010203 0001020300010203 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0001020300010203 0001020300010203 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvwsx 5555555555555555 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020300010203 0001020300010203 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0000100800001010 0000100000001002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020300010203 0001020300010203 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0001020300010203 0001020300010203 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvwsx 5555555555555555 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020300010203 0001020300010203 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0010100800101010 0010100000101002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020300010203 0001020300010203 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0001020300010203 0001020300010203 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvwsx 5555555555555555 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020300010203 0001020300010203 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
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+stxvb16x 00001f0800001f10 00001f0000001f02 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 00001f0800001f10 00001f0000001f02 [ 00001f0000001f02 00001f0800001f10 0000000000000000 ffffffffffffffff ]
+stxvb16x 00001f0800001f10 00001f0000001f02 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 00001f0800001f10 00001f0000001f02 [ 00001f0000001f02 00001f0800001f10 ffffffffffffffff 0001020304050607 ]
+stxvb16x 00001f0800001f10 00001f0000001f02 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 00001f0800001f10 00001f0000001f02 [ 00001f0000001f02 00001f0800001f10 0001020304050607 5555555555555555 ]
+stxvb16x 00001f0800001f10 00001f0000001f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 00001f0800001f10 00001f0000001f02 [ 00001f0000001f02 00001f0800001f10 5555555555555555 0000000000000000 ]
+stxvb16x 00001f0800001f10 00001f0000001f02 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 00001f0800001f10 00001f0000001f02 [ 00001f0000001f02 00001f0800001f10 0000000000000000 ffffffffffffffff ]
+stxvb16x 00101f0800101f10 00101f0000101f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 5555555555555555 0000000000000000 ]
+stxvb16x 00101f0800101f10 00101f0000101f02 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 0000000000000000 ffffffffffffffff ]
+stxvb16x 00101f0800101f10 00101f0000101f02 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 ffffffffffffffff 0001020304050607 ]
+stxvb16x 00101f0800101f10 00101f0000101f02 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 0001020304050607 5555555555555555 ]
+stxvb16x 00101f0800101f10 00101f0000101f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 5555555555555555 0000000000000000 ]
+stxvb16x 00101f0800101f10 00101f0000101f02 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 00101f0800101f10 00101f0000101f02 [ 00101f0000101f02 00101f0800101f10 0000000000000000 ffffffffffffffff ]
+
+All done. Tested 135 different instructions
+ppc vector scalar compare exponents doubles:
+Test instruction group [ppc vector scalar compare exponents doubles]
+xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+
+All done. Tested 136 different instructions
+ppc vector scalar test data class tests:
+Test instruction group [ppc vector scalar test data class tests]
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+xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 DCMX=[-inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 DCMX=[-inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => ffffffffffffffff, ffffffffffffffff
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, ffffffff00000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, ffffffff00000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, ffffffffffffffff
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, ffffffff00000000
+xvtstdcsp 0000000000000000, 8000000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, ffffffff00000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, ffffffff00000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, ffffffffffffffff
+
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => ffffffffffffffff, ffffffffffffffff
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, ffffffffffffffff
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, ffffffffffffffff
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 0000000000000000, 8000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, ffffffffffffffff
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, ffffffffffffffff
+
+All done. Tested 141 different instructions
+ppc vector scalar tests against float double two args :
+Test instruction group [ppc vector scalar tests against float double two args ]
+xsiexpdp r14 = 0x0, r15 = 0x0 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x7fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 7ff0000000000000
+xsiexpdp r14 = 0x0, r15 = 0xff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0xff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 7ff0000000000000
+xsiexpdp r14 = 0x0, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 7ff0000000000000
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+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x8000000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x80007fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x8ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x8ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x0 0000000000000000 ffff7fffffffffff => 0000000000000000 8000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x7fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 8000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 8000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 8000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x8000000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 8000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x80007fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x8ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 8000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x8ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 8000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 8000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x0 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x8000000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x80007fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x8ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x8ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+
+xscvhpdp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x1ff000001ff0000 fffffe00fffffe00 01ff000001ff0000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e000000 ffffffffffffffff 7e0000007e000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff00007fff0000 fffffe00fffffe00 7fff00007fff0000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e000000 ffffffffffffffff 7e0000007e000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff00007fff0000 fffffe00fffffe00 7fff00007fff0000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff81ffffff81ff, vec_xb[0] = 0x7e0000007e000000 ffff81ffffff81ff 7e0000007e000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff8000ffff8000, vec_xb[0] = 0x7fff00007fff0000 ffff8000ffff8000 7fff00007fff0000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0x8000000080000000 ffff7fffffff7fff 8000000080000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0x81ff000081ff0000 ffff7e00ffff7e00 81ff000081ff0000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe000000fe000000 ffff7fffffff7fff fe000000fe000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff0000ffff0000 ffff7e00ffff7e00 ffff0000ffff0000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe000000fe000000 ffff7fffffff7fff fe000000fe000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff0000ffff0000 ffff7e00ffff7e00 ffff0000ffff0000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff01ffffff01ff, vec_xb[0] = 0xfe000000fe000000 ffff01ffffff01ff fe000000fe000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff0000ffff0000, vec_xb[0] = 0xffff0000ffff0000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 0000000000000000 FPCC-FE
+
+xscvdphp r14 = 0x0, r15 = 0x0 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7ff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7ff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7ff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7ff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x8000000000000000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x80007fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x8ff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x8ff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xfff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xfff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xfff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xfff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => ffffe000ffffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x1ff000001ff0000 fffffe00fffffe00 01ff000001ff0000 => ffc00000ffc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e000000 ffffffffffffffff 7e0000007e000000 => ffffe000ffffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff00007fff0000 fffffe00fffffe00 7fff00007fff0000 => ffc00000ffc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e000000 ffffffffffffffff 7e0000007e000000 => ffffe000ffffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff00007fff0000 fffffe00fffffe00 7fff00007fff0000 => ffc00000ffc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff81ffffff81ff, vec_xb[0] = 0x7e0000007e000000 ffff81ffffff81ff 7e0000007e000000 => b7ff8000b7ff8000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff8000ffff8000, vec_xb[0] = 0x7fff00007fff0000 ffff8000ffff8000 7fff00007fff0000 => 8000000080000000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0x8000000080000000 ffff7fffffff7fff 8000000080000000 => 7fffe0007fffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0x81ff000081ff0000 ffff7e00ffff7e00 81ff000081ff0000 => 7fc000007fc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe000000fe000000 ffff7fffffff7fff fe000000fe000000 => 7fffe0007fffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff0000ffff0000 ffff7e00ffff7e00 ffff0000ffff0000 => 7fc000007fc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe000000fe000000 ffff7fffffff7fff fe000000fe000000 => 7fffe0007fffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff0000ffff0000 ffff7e00ffff7e00 ffff0000ffff0000 => 7fc000007fc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff01ffffff01ff, vec_xb[0] = 0xfe000000fe000000 ffff01ffffff01ff fe000000fe000000 => 37ff800037ff8000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff0000, vec_xb[0] = 0xffff0000ffff0000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x1ff000001ff fe00fffffe00ffff 000001ff000001ff => ffffe000ffffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x1ff01ff01ff01ff fe00fe00fe00fe00 01ff01ff01ff01ff => ffc00000ffc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e0001ff7e0001ff fe00fffffe00ffff 7e0001ff7e0001ff => ffffe000ffffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff01ff7fff01ff fe00fe00fe00fe00 7fff01ff7fff01ff => ffc00000ffc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e0001ff7e0001ff fe00fffffe00ffff 7e0001ff7e0001ff => ffffe000ffffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff01ff7fff01ff fe00fe00fe00fe00 7fff01ff7fff01ff => ffc00000ffc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe0081fffe0081ff, vec_xb[0] = 0x7e0001ff7e0001ff fe0081fffe0081ff 7e0001ff7e0001ff => b7ff8000b7ff8000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe008000fe008000, vec_xb[0] = 0x7fff01ff7fff01ff fe008000fe008000 7fff01ff7fff01ff => 8000000080000000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0x800001ff800001ff fe007ffffe007fff 800001ff800001ff => 7fffe0007fffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0x81ff01ff81ff01ff fe007e00fe007e00 81ff01ff81ff01ff => 7fc000007fc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe0001fffe0001ff fe007ffffe007fff fe0001fffe0001ff => 7fffe0007fffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff01ffffff01ff fe007e00fe007e00 ffff01ffffff01ff => 7fc000007fc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe0001fffe0001ff fe007ffffe007fff fe0001fffe0001ff => 7fffe0007fffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff01ffffff01ff fe007e00fe007e00 ffff01ffffff01ff => 7fc000007fc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe0001fffe0001ff, vec_xb[0] = 0xfe0001fffe0001ff fe0001fffe0001ff fe0001fffe0001ff => 37ff800037ff8000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe000000fe000000, vec_xb[0] = 0xffff01ffffff01ff fe000000fe000000 ffff01ffffff01ff => 0000000000000000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e00 ffffffffffffffff 00007e0000007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x1ff7e0001ff7e00 fffffe00fffffe00 01ff7e0001ff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e007e007e007e00 ffffffffffffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff7e007fff7e00 fffffe00fffffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e007e007e007e00 ffffffffffffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff7e007fff7e00 fffffe00fffffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff81ffffff81ff, vec_xb[0] = 0x7e007e007e007e00 ffff81ffffff81ff 7e007e007e007e00 => b7ff8000b7ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff8000ffff8000, vec_xb[0] = 0x7fff7e007fff7e00 ffff8000ffff8000 7fff7e007fff7e00 => 8000000080000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0x80007e0080007e00 ffff7fffffff7fff 80007e0080007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0x81ff7e0081ff7e00 ffff7e00ffff7e00 81ff7e0081ff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe007e00fe007e00 ffff7fffffff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff7e00ffff7e00 ffff7e00ffff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe007e00fe007e00 ffff7fffffff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff7e00ffff7e00 ffff7e00ffff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff01ffffff01ff, vec_xb[0] = 0xfe007e00fe007e00 ffff01ffffff01ff fe007e00fe007e00 => 37ff800037ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff0000, vec_xb[0] = 0xffff7e00ffff7e00 ffff0000ffff0000 ffff7e00ffff7e00 => 0000000000000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7fff00007fff fe00fffffe00ffff 00007fff00007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x1ff7fff01ff7fff fe00fe00fe00fe00 01ff7fff01ff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e007fff7e007fff fe00fffffe00ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff7fff7fff7fff fe00fe00fe00fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e007fff7e007fff fe00fffffe00ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff7fff7fff7fff fe00fe00fe00fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe0081fffe0081ff, vec_xb[0] = 0x7e007fff7e007fff fe0081fffe0081ff 7e007fff7e007fff => b7ff8000b7ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe008000fe008000, vec_xb[0] = 0x7fff7fff7fff7fff fe008000fe008000 7fff7fff7fff7fff => 8000000080000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0x80007fff80007fff fe007ffffe007fff 80007fff80007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0x81ff7fff81ff7fff fe007e00fe007e00 81ff7fff81ff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe007ffffe007fff fe007ffffe007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff7fffffff7fff fe007e00fe007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe007ffffe007fff fe007ffffe007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff7fffffff7fff fe007e00fe007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe0001fffe0001ff, vec_xb[0] = 0xfe007ffffe007fff fe0001fffe0001ff fe007ffffe007fff => 37ff800037ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe000000, vec_xb[0] = 0xffff7fffffff7fff fe000000fe000000 ffff7fffffff7fff => 0000000000000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e00 ffffffffffffffff 00007e0000007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x1ff7e0001ff7e00 fffffe00fffffe00 01ff7e0001ff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e007e007e007e00 ffffffffffffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff7e007fff7e00 fffffe00fffffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e007e007e007e00 ffffffffffffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff7e007fff7e00 fffffe00fffffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff81ffffff81ff, vec_xb[0] = 0x7e007e007e007e00 ffff81ffffff81ff 7e007e007e007e00 => b7ff8000b7ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff8000ffff8000, vec_xb[0] = 0x7fff7e007fff7e00 ffff8000ffff8000 7fff7e007fff7e00 => 8000000080000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0x80007e0080007e00 ffff7fffffff7fff 80007e0080007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0x81ff7e0081ff7e00 ffff7e00ffff7e00 81ff7e0081ff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe007e00fe007e00 ffff7fffffff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff7e00ffff7e00 ffff7e00ffff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe007e00fe007e00 ffff7fffffff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff7e00ffff7e00 ffff7e00ffff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff01ffffff01ff, vec_xb[0] = 0xfe007e00fe007e00 ffff01ffffff01ff fe007e00fe007e00 => 37ff800037ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff0000, vec_xb[0] = 0xffff7e00ffff7e00 ffff0000ffff0000 ffff7e00ffff7e00 => 0000000000000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7fff00007fff fe00fffffe00ffff 00007fff00007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x1ff7fff01ff7fff fe00fe00fe00fe00 01ff7fff01ff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e007fff7e007fff fe00fffffe00ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff7fff7fff7fff fe00fe00fe00fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e007fff7e007fff fe00fffffe00ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff7fff7fff7fff fe00fe00fe00fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe0081fffe0081ff, vec_xb[0] = 0x7e007fff7e007fff fe0081fffe0081ff 7e007fff7e007fff => b7ff8000b7ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe008000fe008000, vec_xb[0] = 0x7fff7fff7fff7fff fe008000fe008000 7fff7fff7fff7fff => 8000000080000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0x80007fff80007fff fe007ffffe007fff 80007fff80007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0x81ff7fff81ff7fff fe007e00fe007e00 81ff7fff81ff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe007ffffe007fff fe007ffffe007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff7fffffff7fff fe007e00fe007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe007ffffe007fff fe007ffffe007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff7fffffff7fff fe007e00fe007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe0001fffe0001ff, vec_xb[0] = 0xfe007ffffe007fff fe0001fffe0001ff fe007ffffe007fff => 37ff800037ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe000000, vec_xb[0] = 0xffff7fffffff7fff fe000000fe000000 ffff7fffffff7fff => 0000000000000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x81ffffff81ffffff, vec_xb[0] = 0x7e0000007e00 81ffffff81ffffff 00007e0000007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81fffe0081fffe00, vec_xb[0] = 0x1ff7e0001ff7e00 81fffe0081fffe00 01ff7e0001ff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ffffff81ffffff, vec_xb[0] = 0x7e007e007e007e00 81ffffff81ffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81fffe0081fffe00, vec_xb[0] = 0x7fff7e007fff7e00 81fffe0081fffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ffffff81ffffff, vec_xb[0] = 0x7e007e007e007e00 81ffffff81ffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81fffe0081fffe00, vec_xb[0] = 0x7fff7e007fff7e00 81fffe0081fffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff81ff81ff81ff, vec_xb[0] = 0x7e007e007e007e00 81ff81ff81ff81ff 7e007e007e007e00 => b7ff8000b7ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff800081ff8000, vec_xb[0] = 0x7fff7e007fff7e00 81ff800081ff8000 7fff7e007fff7e00 => 8000000080000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7fff81ff7fff, vec_xb[0] = 0x80007e0080007e00 81ff7fff81ff7fff 80007e0080007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7e0081ff7e00, vec_xb[0] = 0x81ff7e0081ff7e00 81ff7e0081ff7e00 81ff7e0081ff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7fff81ff7fff, vec_xb[0] = 0xfe007e00fe007e00 81ff7fff81ff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7e0081ff7e00, vec_xb[0] = 0xffff7e00ffff7e00 81ff7e0081ff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7fff81ff7fff, vec_xb[0] = 0xfe007e00fe007e00 81ff7fff81ff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7e0081ff7e00, vec_xb[0] = 0xffff7e00ffff7e00 81ff7e0081ff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff01ff81ff01ff, vec_xb[0] = 0xfe007e00fe007e00 81ff01ff81ff01ff fe007e00fe007e00 => 37ff800037ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff000081ff0000, vec_xb[0] = 0xffff7e00ffff7e00 81ff000081ff0000 ffff7e00ffff7e00 => 0000000000000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x8000ffff8000ffff, vec_xb[0] = 0x7fff00007fff 8000ffff8000ffff 00007fff00007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000fe008000fe00, vec_xb[0] = 0x1ff7fff01ff7fff 8000fe008000fe00 01ff7fff01ff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000ffff8000ffff, vec_xb[0] = 0x7e007fff7e007fff 8000ffff8000ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000fe008000fe00, vec_xb[0] = 0x7fff7fff7fff7fff 8000fe008000fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000ffff8000ffff, vec_xb[0] = 0x7e007fff7e007fff 8000ffff8000ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000fe008000fe00, vec_xb[0] = 0x7fff7fff7fff7fff 8000fe008000fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x800081ff800081ff, vec_xb[0] = 0x7e007fff7e007fff 800081ff800081ff 7e007fff7e007fff => b7ff8000b7ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000800080008000, vec_xb[0] = 0x7fff7fff7fff7fff 8000800080008000 7fff7fff7fff7fff => 8000000080000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007fff80007fff, vec_xb[0] = 0x80007fff80007fff 80007fff80007fff 80007fff80007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007e0080007e00, vec_xb[0] = 0x81ff7fff81ff7fff 80007e0080007e00 81ff7fff81ff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007fff80007fff, vec_xb[0] = 0xfe007ffffe007fff 80007fff80007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007e0080007e00, vec_xb[0] = 0xffff7fffffff7fff 80007e0080007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007fff80007fff, vec_xb[0] = 0xfe007ffffe007fff 80007fff80007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007e0080007e00, vec_xb[0] = 0xffff7fffffff7fff 80007e0080007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x800001ff800001ff, vec_xb[0] = 0xfe007ffffe007fff 800001ff800001ff fe007ffffe007fff => 37ff800037ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000000080000000, vec_xb[0] = 0xffff7fffffff7fff 8000000080000000 ffff7fffffff7fff => 0000000000000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x800000008000 7fffffff7fffffff 0000800000008000 => ffffe000ffffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x1ff800001ff8000 7ffffe007ffffe00 01ff800001ff8000 => ffc00000ffc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e0080007e008000 7fffffff7fffffff 7e0080007e008000 => ffffe000ffffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7fff80007fff8000 7ffffe007ffffe00 7fff80007fff8000 => ffc00000ffc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e0080007e008000 7fffffff7fffffff 7e0080007e008000 => ffffe000ffffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7fff80007fff8000 7ffffe007ffffe00 7fff80007fff8000 => ffc00000ffc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff81ff7fff81ff, vec_xb[0] = 0x7e0080007e008000 7fff81ff7fff81ff 7e0080007e008000 => b7ff8000b7ff8000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff80007fff8000, vec_xb[0] = 0x7fff80007fff8000 7fff80007fff8000 7fff80007fff8000 => 8000000080000000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0x8000800080008000 7fff7fff7fff7fff 8000800080008000 => 7fffe0007fffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0x81ff800081ff8000 7fff7e007fff7e00 81ff800081ff8000 => 7fc000007fc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe008000fe008000 7fff7fff7fff7fff fe008000fe008000 => 7fffe0007fffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xffff8000ffff8000 7fff7e007fff7e00 ffff8000ffff8000 => 7fc000007fc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe008000fe008000 7fff7fff7fff7fff fe008000fe008000 => 7fffe0007fffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xffff8000ffff8000 7fff7e007fff7e00 ffff8000ffff8000 => 7fc000007fc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff01ff7fff01ff, vec_xb[0] = 0xfe008000fe008000 7fff01ff7fff01ff fe008000fe008000 => 37ff800037ff8000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff0000, vec_xb[0] = 0xffff8000ffff8000 7fff00007fff0000 ffff8000ffff8000 => 0000000000000000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x81ff000081ff 7e00ffff7e00ffff 000081ff000081ff => ffffe000ffffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x1ff81ff01ff81ff 7e00fe007e00fe00 01ff81ff01ff81ff => ffc00000ffc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e0081ff7e0081ff 7e00ffff7e00ffff 7e0081ff7e0081ff => ffffe000ffffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fff81ff7fff81ff 7e00fe007e00fe00 7fff81ff7fff81ff => ffc00000ffc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e0081ff7e0081ff 7e00ffff7e00ffff 7e0081ff7e0081ff => ffffe000ffffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fff81ff7fff81ff 7e00fe007e00fe00 7fff81ff7fff81ff => ffc00000ffc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e0081ff7e0081ff, vec_xb[0] = 0x7e0081ff7e0081ff 7e0081ff7e0081ff 7e0081ff7e0081ff => b7ff8000b7ff8000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e0080007e008000, vec_xb[0] = 0x7fff81ff7fff81ff 7e0080007e008000 7fff81ff7fff81ff => 8000000080000000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0x800081ff800081ff 7e007fff7e007fff 800081ff800081ff => 7fffe0007fffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0x81ff81ff81ff81ff 7e007e007e007e00 81ff81ff81ff81ff => 7fc000007fc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe0081fffe0081ff 7e007fff7e007fff fe0081fffe0081ff => 7fffe0007fffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffff81ffffff81ff 7e007e007e007e00 ffff81ffffff81ff => 7fc000007fc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe0081fffe0081ff 7e007fff7e007fff fe0081fffe0081ff => 7fffe0007fffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffff81ffffff81ff 7e007e007e007e00 ffff81ffffff81ff => 7fc000007fc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e0001ff7e0001ff, vec_xb[0] = 0xfe0081fffe0081ff 7e0001ff7e0001ff fe0081fffe0081ff => 37ff800037ff8000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e0000007e000000, vec_xb[0] = 0xffff81ffffff81ff 7e0000007e000000 ffff81ffffff81ff => 0000000000000000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xfe000000fe00 7fffffff7fffffff 0000fe000000fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x1fffe0001fffe00 7ffffe007ffffe00 01fffe0001fffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e00fe007e00fe00 7fffffff7fffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7ffffe007ffffe00 7ffffe007ffffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e00fe007e00fe00 7fffffff7fffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7ffffe007ffffe00 7ffffe007ffffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff81ff7fff81ff, vec_xb[0] = 0x7e00fe007e00fe00 7fff81ff7fff81ff 7e00fe007e00fe00 => b7ff8000b7ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff80007fff8000, vec_xb[0] = 0x7ffffe007ffffe00 7fff80007fff8000 7ffffe007ffffe00 => 8000000080000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0x8000fe008000fe00 7fff7fff7fff7fff 8000fe008000fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0x81fffe0081fffe00 7fff7e007fff7e00 81fffe0081fffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff7fff7fff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xfffffe00fffffe00 7fff7e007fff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff7fff7fff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xfffffe00fffffe00 7fff7e007fff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff01ff7fff01ff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff01ff7fff01ff fe00fe00fe00fe00 => 37ff800037ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff0000, vec_xb[0] = 0xfffffe00fffffe00 7fff00007fff0000 fffffe00fffffe00 => 0000000000000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0xffff0000ffff 7e00ffff7e00ffff 0000ffff0000ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x1ffffff01ffffff 7e00fe007e00fe00 01ffffff01ffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e00ffff7e00ffff 7e00ffff7e00ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fffffff7fffffff 7e00fe007e00fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e00ffff7e00ffff 7e00ffff7e00ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fffffff7fffffff 7e00fe007e00fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0081ff7e0081ff, vec_xb[0] = 0x7e00ffff7e00ffff 7e0081ff7e0081ff 7e00ffff7e00ffff => b7ff8000b7ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0080007e008000, vec_xb[0] = 0x7fffffff7fffffff 7e0080007e008000 7fffffff7fffffff => 8000000080000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0x8000ffff8000ffff 7e007fff7e007fff 8000ffff8000ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0x81ffffff81ffffff 7e007e007e007e00 81ffffff81ffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe00fffffe00ffff 7e007fff7e007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffffffffffffffff 7e007e007e007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe00fffffe00ffff 7e007fff7e007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffffffffffffffff 7e007e007e007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0001ff7e0001ff, vec_xb[0] = 0xfe00fffffe00ffff 7e0001ff7e0001ff fe00fffffe00ffff => 37ff800037ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e000000, vec_xb[0] = 0xffffffffffffffff 7e0000007e000000 ffffffffffffffff => 0000000000000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xfe000000fe00 7fffffff7fffffff 0000fe000000fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x1fffe0001fffe00 7ffffe007ffffe00 01fffe0001fffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e00fe007e00fe00 7fffffff7fffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7ffffe007ffffe00 7ffffe007ffffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e00fe007e00fe00 7fffffff7fffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7ffffe007ffffe00 7ffffe007ffffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff81ff7fff81ff, vec_xb[0] = 0x7e00fe007e00fe00 7fff81ff7fff81ff 7e00fe007e00fe00 => b7ff8000b7ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff80007fff8000, vec_xb[0] = 0x7ffffe007ffffe00 7fff80007fff8000 7ffffe007ffffe00 => 8000000080000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0x8000fe008000fe00 7fff7fff7fff7fff 8000fe008000fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0x81fffe0081fffe00 7fff7e007fff7e00 81fffe0081fffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff7fff7fff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xfffffe00fffffe00 7fff7e007fff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff7fff7fff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xfffffe00fffffe00 7fff7e007fff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff01ff7fff01ff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff01ff7fff01ff fe00fe00fe00fe00 => 37ff800037ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff0000, vec_xb[0] = 0xfffffe00fffffe00 7fff00007fff0000 fffffe00fffffe00 => 0000000000000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0xffff0000ffff 7e00ffff7e00ffff 0000ffff0000ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x1ffffff01ffffff 7e00fe007e00fe00 01ffffff01ffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e00ffff7e00ffff 7e00ffff7e00ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fffffff7fffffff 7e00fe007e00fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e00ffff7e00ffff 7e00ffff7e00ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fffffff7fffffff 7e00fe007e00fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0081ff7e0081ff, vec_xb[0] = 0x7e00ffff7e00ffff 7e0081ff7e0081ff 7e00ffff7e00ffff => b7ff8000b7ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0080007e008000, vec_xb[0] = 0x7fffffff7fffffff 7e0080007e008000 7fffffff7fffffff => 8000000080000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0x8000ffff8000ffff 7e007fff7e007fff 8000ffff8000ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0x81ffffff81ffffff 7e007e007e007e00 81ffffff81ffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe00fffffe00ffff 7e007fff7e007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffffffffffffffff 7e007e007e007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe00fffffe00ffff 7e007fff7e007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffffffffffffffff 7e007e007e007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0001ff7e0001ff, vec_xb[0] = 0xfe00fffffe00ffff 7e0001ff7e0001ff fe00fffffe00ffff => 37ff800037ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e000000, vec_xb[0] = 0xffffffffffffffff 7e0000007e000000 ffffffffffffffff => 0000000000000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x1ffffff01ffffff, vec_xb[0] = 0xfe000000fe00 01ffffff01ffffff 0000fe000000fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1fffe0001fffe00, vec_xb[0] = 0x1fffe0001fffe00 01fffe0001fffe00 01fffe0001fffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ffffff01ffffff, vec_xb[0] = 0x7e00fe007e00fe00 01ffffff01ffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1fffe0001fffe00, vec_xb[0] = 0x7ffffe007ffffe00 01fffe0001fffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ffffff01ffffff, vec_xb[0] = 0x7e00fe007e00fe00 01ffffff01ffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1fffe0001fffe00, vec_xb[0] = 0x7ffffe007ffffe00 01fffe0001fffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff81ff01ff81ff, vec_xb[0] = 0x7e00fe007e00fe00 01ff81ff01ff81ff 7e00fe007e00fe00 => b7ff8000b7ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff800001ff8000, vec_xb[0] = 0x7ffffe007ffffe00 01ff800001ff8000 7ffffe007ffffe00 => 8000000080000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7fff01ff7fff, vec_xb[0] = 0x8000fe008000fe00 01ff7fff01ff7fff 8000fe008000fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7e0001ff7e00, vec_xb[0] = 0x81fffe0081fffe00 01ff7e0001ff7e00 81fffe0081fffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7fff01ff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 01ff7fff01ff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7e0001ff7e00, vec_xb[0] = 0xfffffe00fffffe00 01ff7e0001ff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7fff01ff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 01ff7fff01ff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7e0001ff7e00, vec_xb[0] = 0xfffffe00fffffe00 01ff7e0001ff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff01ff01ff01ff, vec_xb[0] = 0xfe00fe00fe00fe00 01ff01ff01ff01ff fe00fe00fe00fe00 => 37ff800037ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff000001ff0000, vec_xb[0] = 0xfffffe00fffffe00 01ff000001ff0000 fffffe00fffffe00 => 0000000000000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff, vec_xb[0] = 0xffff0000ffff 0000ffff0000ffff 0000ffff0000ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe00, vec_xb[0] = 0x1ffffff01ffffff 0000fe000000fe00 01ffffff01ffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff, vec_xb[0] = 0x7e00ffff7e00ffff 0000ffff0000ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe00, vec_xb[0] = 0x7fffffff7fffffff 0000fe000000fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff, vec_xb[0] = 0x7e00ffff7e00ffff 0000ffff0000ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe00, vec_xb[0] = 0x7fffffff7fffffff 0000fe000000fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x81ff000081ff, vec_xb[0] = 0x7e00ffff7e00ffff 000081ff000081ff 7e00ffff7e00ffff => b7ff8000b7ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x800000008000, vec_xb[0] = 0x7fffffff7fffffff 0000800000008000 7fffffff7fffffff => 8000000080000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff, vec_xb[0] = 0x8000ffff8000ffff 00007fff00007fff 8000ffff8000ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e00, vec_xb[0] = 0x81ffffff81ffffff 00007e0000007e00 81ffffff81ffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff, vec_xb[0] = 0xfe00fffffe00ffff 00007fff00007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e00, vec_xb[0] = 0xffffffffffffffff 00007e0000007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff, vec_xb[0] = 0xfe00fffffe00ffff 00007fff00007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e00, vec_xb[0] = 0xffffffffffffffff 00007e0000007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x1ff000001ff, vec_xb[0] = 0xfe00fffffe00ffff 000001ff000001ff fe00fffffe00ffff => 37ff800037ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 ffffe000ffffe000
+
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x0 ffffffffff800000 0000000000000000 => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x0 ffffffffff800000 0000000000000000 => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x0 ffffffffff800000 0000000000000000 => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x0 ffffffff807fffff 0000000000000000 => 0000ffff00008000 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x0 ffffffff80000000 0000000000000000 => 0000ffff00008000 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x0 7fffffff7fffffff 0000000000000000 => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x0 7f8000007f800000 0000000000000000 => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x0 7fffffff7fffffff 0000000000000000 => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x0 7f8000007f800000 0000000000000000 => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x0 7fffffff7fffffff 0000000000000000 => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x0 7f8000007f800000 0000000000000000 => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x0 007fffff007fffff 0000000000000000 => 0000000000000000 0000000000000000
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x0 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffff007fffff ffffffffffffffff 007fffff007fffff => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffff007fffff ffffffffff800000 007fffff007fffff => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffff007fffff ffffffffffffffff 007fffff007fffff => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffff007fffff ffffffffff800000 007fffff007fffff => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffff007fffff ffffffffffffffff 007fffff007fffff => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffff007fffff ffffffffff800000 007fffff007fffff => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7fffff007fffff ffffffff807fffff 007fffff007fffff => 0000ffff00008000 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7fffff007fffff ffffffff80000000 007fffff007fffff => 0000ffff00008000 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffff007fffff 7fffffff7fffffff 007fffff007fffff => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffff007fffff 7f8000007f800000 007fffff007fffff => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffff007fffff 7fffffff7fffffff 007fffff007fffff => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffff007fffff 7f8000007f800000 007fffff007fffff => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffff007fffff 7fffffff7fffffff 007fffff007fffff => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffff007fffff 7f8000007f800000 007fffff007fffff => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7fffff007fffff 007fffff007fffff 007fffff007fffff => 0000000000000000 0000000000000000
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7fffff007fffff 0000000000000000 007fffff007fffff => 0000000000000000 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7f8000007f800000 ffffffff807fffff 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7f8000007f800000 ffffffff80000000 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7f8000007f800000 007fffff007fffff 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7f8000007f800000 0000000000000000 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7fffffff7fffffff ffffffff807fffff 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7fffffff7fffffff ffffffff80000000 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7fffffff7fffffff 007fffff007fffff 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7fffffff7fffffff 0000000000000000 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7f8000007f800000 ffffffff807fffff 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7f8000007f800000 ffffffff80000000 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7f8000007f800000 007fffff007fffff 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7f8000007f800000 0000000000000000 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7fffffff7fffffff ffffffff807fffff 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7fffffff7fffffff ffffffff80000000 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7fffffff7fffffff 007fffff007fffff 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7fffffff7fffffff 0000000000000000 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7f8000007f800000 ffffffff807fffff 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7f8000007f800000 ffffffff80000000 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7f8000007f800000 007fffff007fffff 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7f8000007f800000 0000000000000000 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7fffffff7fffffff ffffffff807fffff 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7fffffff7fffffff ffffffff80000000 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7fffffff7fffffff 007fffff007fffff 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7fffffff7fffffff 0000000000000000 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff80000000 ffffffffffffffff ffffffff80000000 => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff80000000 ffffffffff800000 ffffffff80000000 => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff80000000 ffffffffffffffff ffffffff80000000 => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff80000000 ffffffffff800000 ffffffff80000000 => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff80000000 ffffffffffffffff ffffffff80000000 => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff80000000 ffffffffff800000 ffffffff80000000 => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffff80000000 ffffffff807fffff ffffffff80000000 => 0000ffff00008000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffff80000000 ffffffff80000000 ffffffff80000000 => 0000ffff00008000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff80000000 7fffffff7fffffff ffffffff80000000 => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff80000000 7f8000007f800000 ffffffff80000000 => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff80000000 7fffffff7fffffff ffffffff80000000 => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff80000000 7f8000007f800000 ffffffff80000000 => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff80000000 7fffffff7fffffff ffffffff80000000 => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff80000000 7f8000007f800000 ffffffff80000000 => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffff80000000 007fffff007fffff ffffffff80000000 => 0000000000000000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffff80000000 0000000000000000 ffffffff80000000 => 0000000000000000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff807fffff ffffffffffffffff ffffffff807fffff => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff807fffff ffffffffff800000 ffffffff807fffff => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff807fffff ffffffffffffffff ffffffff807fffff => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff807fffff ffffffffff800000 ffffffff807fffff => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff807fffff ffffffffffffffff ffffffff807fffff => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff807fffff ffffffffff800000 ffffffff807fffff => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffff807fffff ffffffff807fffff ffffffff807fffff => 0000ffff00008000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffff807fffff ffffffff80000000 ffffffff807fffff => 0000ffff00008000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff807fffff 7fffffff7fffffff ffffffff807fffff => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff807fffff 7f8000007f800000 ffffffff807fffff => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff807fffff 7fffffff7fffffff ffffffff807fffff => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff807fffff 7f8000007f800000 ffffffff807fffff => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff807fffff 7fffffff7fffffff ffffffff807fffff => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff807fffff 7f8000007f800000 ffffffff807fffff => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffff807fffff 007fffff007fffff ffffffff807fffff => 0000000000000000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffff807fffff 0000000000000000 ffffffff807fffff => 0000000000000000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffff800000 ffffffff807fffff ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffff800000 ffffffff80000000 ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffff800000 007fffff007fffff ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffff800000 0000000000000000 ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffffffffff ffffffff807fffff ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffffffffff ffffffff80000000 ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffffffffff 007fffff007fffff ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffff800000 ffffffff807fffff ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffff800000 ffffffff80000000 ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffff800000 007fffff007fffff ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffff800000 0000000000000000 ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffffffffff ffffffff807fffff ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffffffffff ffffffff80000000 ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffffffffff 007fffff007fffff ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffff800000 ffffffff807fffff ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffff800000 ffffffff80000000 ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffff800000 007fffff007fffff ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffff800000 0000000000000000 ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffffffffff ffffffff807fffff ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffffffffff ffffffff80000000 ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffffffffff 007fffff007fffff ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+
+All done. Tested 146 different instructions
diff --git a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
new file mode 100644
index 0000000..63c3c89
--- /dev/null
+++ b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
@@ -0,0 +1,56233 @@
+ppc vector absolutes:
+Test instruction group [ppc vector absolutes]
+vabsdub xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vabsdub xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:0102030405060708 0102030405060708 (00000000)
+vabsdub xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0011223344556677 8899aabbccddeeff (00000000)
+vabsdub xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:010f1f2f3f4f5f6f 8797a7b7c7d7e7f7 (00000000)
+vabsdub xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010 (00000000)
+vabsdub xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:01020d0405060906 01020d0405060908 (00000000)
+vabsdub xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10 (00000000)
+vabsdub xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:0102190405061506 0102190405061508 (00000000)
+vabsdub xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10 (00000000)
+vabsdub xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:01021c0405061806 01021c0405061808 (00000000)
+
+vabsduh xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vabsduh xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:0102030405060708 0102030405060708 (00000000)
+vabsduh xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0011223344556677 8899aabbccddeeff (00000000)
+vabsduh xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:00f11f2f3f4f5f6f 8797a7b7c7d7e7f7 (00000000)
+vabsduh xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010 (00000000)
+vabsduh xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:01020cfc050608fa 01020d0405060908 (00000000)
+vabsduh xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10 (00000000)
+vabsduh xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:010218fc050614fa 0102190405061508 (00000000)
+vabsduh xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10 (00000000)
+vabsduh xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:01021bfc050617fa 01021c0405061808 (00000000)
+
+vabsduw xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vabsduw xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:0102030405060708 0102030405060708 (00000000)
+vabsduw xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0011223344556677 8899aabbccddeeff (00000000)
+vabsduw xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:00f0e0d13f4f5f6f 8797a7b7c7d7e7f7 (00000000)
+vabsduw xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010 (00000000)
+vabsduw xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:0101f3040505f706 0101f2fc0505f6f8 (00000000)
+vabsduw xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10 (00000000)
+vabsduw xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:0101e7040505eb06 0101e6fc0505eaf8 (00000000)
+vabsduw xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10 (00000000)
+vabsduw xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:0101e4040505e806 0101e3fc0505e7f8 (00000000)
+
+vcmpneb xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vcmpneb xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:00ffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000ff000000ffff 0000ffff0000ffff (00000000)
+vcmpneb xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:0000ff000000ffff 0000ffff0000ffff (00000000)
+vcmpneb xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:0000ff000000ffff 0000ffff0000ffff (00000000)
+vcmpneb xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+
+vcmpneb. xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000020)
+vcmpneb. xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:00ffffffffffffff ffffffffffffffff (00000000)
+vcmpneb. xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000ff000000ffff 0000ffff0000ffff (00000000)
+vcmpneb. xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:0000ff000000ffff 0000ffff0000ffff (00000000)
+vcmpneb. xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:0000ff000000ffff 0000ffff0000ffff (00000000)
+vcmpneb. xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+
+vcmpnezb xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+
+vcmpnezb. xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+
+vcmpneh xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vcmpneh xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000ffff0000ffff 0000ffff0000ffff (00000000)
+vcmpneh xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:0000ffff0000ffff 0000ffff0000ffff (00000000)
+vcmpneh xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:0000ffff0000ffff 0000ffff0000ffff (00000000)
+vcmpneh xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+
+vcmpneh. xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000020)
+vcmpneh. xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000ffff0000ffff 0000ffff0000ffff (00000000)
+vcmpneh. xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:0000ffff0000ffff 0000ffff0000ffff (00000000)
+vcmpneh. xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:0000ffff0000ffff 0000ffff0000ffff (00000000)
+vcmpneh. xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+
+vcmpnezh xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+
+vcmpnezh. xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+
+vcmpnew xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vcmpnew xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+
+vcmpnew. xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000020)
+vcmpnew. xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnew. xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnew. xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnew. xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnew. xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnew. xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnew. xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnew. xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnew. xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+
+vcmpnezw xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezw xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezw xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezw xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezw xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezw xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezw xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezw xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezw xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezw xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+
+vcmpnezw. xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezw. xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezw. xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezw. xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezw. xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezw. xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezw. xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezw. xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezw. xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezw. xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+
+vrlwnm xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrlwnm xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vrlwnm xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0000000000000000 8000000080000000 (00000000)
+vrlwnm xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:0000000001000000 0000000001000000 (00000000)
+vrlwnm xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrlwnm xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vrlwnm xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrlwnm xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vrlwnm xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrlwnm xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+
+vrlwmi xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrlwmi xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vrlwmi xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0000000000000000 8000000080000000 (00000000)
+vrlwmi xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:0000000001000000 0000000001000000 (00000000)
+vrlwmi xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrlwmi xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vrlwmi xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrlwmi xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vrlwmi xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrlwmi xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+
+vrldnm xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrldnm xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vrldnm xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0000000000000000 8000000000000000 (00000000)
+vrldnm xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:0100000000000000 0100000000000000 (00000000)
+vrldnm xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrldnm xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vrldnm xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrldnm xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vrldnm xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrldnm xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+
+vrldmi xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrldmi xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vrldmi xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0000000000000000 8000000000000000 (00000000)
+vrldmi xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:0100000000000000 0100000000000000 (00000000)
+vrldmi xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrldmi xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vrldmi xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrldmi xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vrldmi xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vrldmi xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+
+vbpermd xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vbpermd xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vbpermd xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0000000000000000 00000000000000ff (00000000)
+vbpermd xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000011 (00000000)
+vbpermd xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vbpermd xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vbpermd xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vbpermd xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+vbpermd xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vbpermd xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:0000000000000000 0000000000000000 (00000000)
+
+xviexpdp xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+xviexpdp xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:7080000000000000 7080000000000000 (00000000)
+xviexpdp xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0001223344556677 8009aabbccddeeff (00000000)
+xviexpdp xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:7081223344556677 f089aabbccddeeff (00000000)
+xviexpdp xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010 (00000000)
+xviexpdp xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:7080100000001002 7080100800001010 (00000000)
+xviexpdp xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10 (00000000)
+xviexpdp xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:70801c0000001c02 70801c0800001c10 (00000000)
+xviexpdp xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10 (00000000)
+xviexpdp xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:70801f0000001f02 70801f0800001f10 (00000000)
+
+xviexpsp xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+xviexpsp xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:0200000004000000 0200000004000000 (00000000)
+xviexpsp xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0011223300556677 8019aabb805deeff (00000000)
+xviexpsp xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:0211223304556677 8219aabb845deeff (00000000)
+xviexpsp xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010 (00000000)
+xviexpsp xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:0200100004001002 0200100804001010 (00000000)
+xviexpsp xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10 (00000000)
+xviexpsp xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:02001c0004001c02 02001c0804001c10 (00000000)
+xviexpsp xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10 (00000000)
+xviexpsp xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:02001f0004001f02 02001f0804001f10 (00000000)
+
+All done. Tested 22 different instructions
+ppc vector logical immediate:
+Test instruction group [ppc vector logical immediate]
+xxspltib 0000000000000000 0000000000000000 [ 0] => 0000000000000000 0000000000000000
+xxspltib ffffffffffffffff ffffffffffffffff [ 0] => 0000000000000000 0000000000000000
+xxspltib 0000000000000000 0000000000000000 [ 1] => 0101010101010101 0101010101010101
+xxspltib ffffffffffffffff ffffffffffffffff [ 1] => 0101010101010101 0101010101010101
+xxspltib 0000000000000000 0000000000000000 [aa] => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa
+xxspltib ffffffffffffffff ffffffffffffffff [aa] => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa
+xxspltib 0000000000000000 0000000000000000 [55] => 5555555555555555 5555555555555555
+xxspltib ffffffffffffffff ffffffffffffffff [55] => 5555555555555555 5555555555555555
+xxspltib 0000000000000000 0000000000000000 [ff] => ffffffffffffffff ffffffffffffffff
+xxspltib ffffffffffffffff ffffffffffffffff [ff] => ffffffffffffffff ffffffffffffffff
+
+All done. Tested 23 different instructions
+ppc vector logical one:
+Test instruction group [ppc vector logical one]
+xxbrh xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xxbrh xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xxbrh xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0201040306050807 0201020102010201
+xxbrh xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0201040306050807 0201020102010201
+xxbrh xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:1100332255447766 9988bbaaddccffee
+xxbrh xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:1100332255447766 9988bbaaddccffee
+xxbrh xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:e0f0c0d0a0b08090 6070405020300010
+xxbrh xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:e0f0c0d0a0b08090 6070405020300010
+xxbrh xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000001000000210 0000081000001010
+xxbrh xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000001000000210 0000081000001010
+xxbrh xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:1000001010000210 1000081010001010
+xxbrh xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:1000001010000210 1000081010001010
+xxbrh xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:0000001c0000021c 0000081c0000101c
+xxbrh xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:0000001c0000021c 0000081c0000101c
+xxbrh xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:1000001c1000021c 1000081c1000101c
+xxbrh xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:1000001c1000021c 1000081c1000101c
+xxbrh xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:0000001f0000021f 0000081f0000101f
+xxbrh xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:0000001f0000021f 0000081f0000101f
+xxbrh xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:1000001f1000021f 1000081f1000101f
+xxbrh xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:1000001f1000021f 1000081f1000101f
+
+xxbrw xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xxbrw xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xxbrw xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0403020108070605 0201020102010201
+xxbrw xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0403020108070605 0201020102010201
+xxbrw xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:3322110077665544 bbaa9988ffeeddcc
+xxbrw xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:3322110077665544 bbaa9988ffeeddcc
+xxbrw xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:c0d0e0f08090a0b0 4050607000102030
+xxbrw xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:c0d0e0f08090a0b0 4050607000102030
+xxbrw xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0010000002100000 0810000010100000
+xxbrw xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0010000002100000 0810000010100000
+xxbrw xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0010100002101000 0810100010101000
+xxbrw xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0010100002101000 0810100010101000
+xxbrw xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:001c0000021c0000 081c0000101c0000
+xxbrw xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:001c0000021c0000 081c0000101c0000
+xxbrw xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:001c1000021c1000 081c1000101c1000
+xxbrw xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:001c1000021c1000 081c1000101c1000
+xxbrw xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:001f0000021f0000 081f0000101f0000
+xxbrw xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:001f0000021f0000 081f0000101f0000
+xxbrw xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:001f1000021f1000 081f1000101f1000
+xxbrw xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:001f1000021f1000 081f1000101f1000
+
+xxbrd xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xxbrd xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xxbrd xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0807060504030201 0201020102010201
+xxbrd xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0807060504030201 0201020102010201
+xxbrd xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:7766554433221100 ffeeddccbbaa9988
+xxbrd xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:7766554433221100 ffeeddccbbaa9988
+xxbrd xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:8090a0b0c0d0e0f0 0010203040506070
+xxbrd xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:8090a0b0c0d0e0f0 0010203040506070
+xxbrd xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0210000000100000 1010000008100000
+xxbrd xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0210000000100000 1010000008100000
+xxbrd xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0210100000101000 1010100008101000
+xxbrd xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0210100000101000 1010100008101000
+xxbrd xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:021c0000001c0000 101c0000081c0000
+xxbrd xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:021c0000001c0000 101c0000081c0000
+xxbrd xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:021c1000001c1000 101c1000081c1000
+xxbrd xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:021c1000001c1000 101c1000081c1000
+xxbrd xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:021f0000001f0000 101f0000081f0000
+xxbrd xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:021f0000001f0000 101f0000081f0000
+xxbrd xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:021f1000001f1000 101f1000081f1000
+xxbrd xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:021f1000001f1000 101f1000081f1000
+
+xxbrq xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xxbrq xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xxbrq xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0201020102010201 0807060504030201
+xxbrq xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0201020102010201 0807060504030201
+xxbrq xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:ffeeddccbbaa9988 7766554433221100
+xxbrq xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:ffeeddccbbaa9988 7766554433221100
+xxbrq xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:0010203040506070 8090a0b0c0d0e0f0
+xxbrq xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:0010203040506070 8090a0b0c0d0e0f0
+xxbrq xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:1010000008100000 0210000000100000
+xxbrq xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:1010000008100000 0210000000100000
+xxbrq xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:1010100008101000 0210100000101000
+xxbrq xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:1010100008101000 0210100000101000
+xxbrq xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:101c0000081c0000 021c0000001c0000
+xxbrq xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:101c0000081c0000 021c0000001c0000
+xxbrq xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:101c1000081c1000 021c1000001c1000
+xxbrq xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:101c1000081c1000 021c1000001c1000
+xxbrq xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:101f0000081f0000 021f0000001f0000
+xxbrq xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:101f0000081f0000 021f0000001f0000
+xxbrq xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:101f1000081f1000 021f1000001f1000
+xxbrq xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:101f1000081f1000 021f1000001f1000
+
+xvxexpdp xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpdp xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpdp xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0000000000000010 0000000000000010
+xvxexpdp xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000010 0000000000000010
+xvxexpdp xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:0000000000000001 0000000000000089
+xvxexpdp xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000001 0000000000000089
+xvxexpdp xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:000000000000070e 0000000000000706
+xvxexpdp xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:000000000000070e 0000000000000706
+xvxexpdp xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpdp xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpdp xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0000000000000001 0000000000000001
+xvxexpdp xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000001 0000000000000001
+xvxexpdp xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpdp xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpdp xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:0000000000000001 0000000000000001
+xvxexpdp xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000001 0000000000000001
+xvxexpdp xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpdp xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpdp xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:0000000000000001 0000000000000001
+xvxexpdp xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000001 0000000000000001
+
+xvxexpsp xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:000000020000000a 0000000200000002
+xvxexpsp xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:000000020000000a 0000000200000002
+xvxexpsp xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:0000000000000088 0000001100000099
+xvxexpsp xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000088 0000001100000099
+xvxexpsp xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:000000e100000061 000000e000000060
+xvxexpsp xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:000000e100000061 000000e000000060
+xvxexpsp xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+
+xvxsigdp xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxsigdp xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxsigdp xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0012030405060708 0012010201020102
+xvxsigdp xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0012030405060708 0012010201020102
+xvxsigdp xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:0011223344556677 0019aabbccddeeff
+xvxsigdp xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:0011223344556677 0019aabbccddeeff
+xvxsigdp xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:0010d0c0b0a09080 0010504030201000
+xvxsigdp xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:0010d0c0b0a09080 0010504030201000
+xvxsigdp xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010
+xvxsigdp xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000100000001002 0000100800001010
+xvxsigdp xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0010100000101002 0010100800101010
+xvxsigdp xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0010100000101002 0010100800101010
+xvxsigdp xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10
+xvxsigdp xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:00001c0000001c02 00001c0800001c10
+xvxsigdp xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:00101c0000101c02 00101c0800101c10
+xvxsigdp xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:00101c0000101c02 00101c0800101c10
+xvxsigdp xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10
+xvxsigdp xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:00001f0000001f02 00001f0800001f10
+xvxsigdp xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:00101f0000101f02 00101f0800101f10
+xvxsigdp xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:00101f0000101f02 00101f0800101f10
+
+xvxsigsp xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxsigsp xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxsigsp xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0082030400860708 0082010200820102
+xvxsigsp xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0082030400860708 0082010200820102
+xvxsigsp xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:0011223300d56677 0099aabb00ddeeff
+xvxsigsp xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:0011223300d56677 0099aabb00ddeeff
+xvxsigsp xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:00e0d0c000a09080 00e0504000a01000
+xvxsigsp xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:00e0d0c000a09080 00e0504000a01000
+xvxsigsp xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010
+xvxsigsp xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000100000001002 0000100800001010
+xvxsigsp xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0010100000101002 0010100800101010
+xvxsigsp xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0010100000101002 0010100800101010
+xvxsigsp xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10
+xvxsigsp xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:00001c0000001c02 00001c0800001c10
+xvxsigsp xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:00101c0000101c02 00101c0800101c10
+xvxsigsp xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:00101c0000101c02 00101c0800101c10
+xvxsigsp xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10
+xvxsigsp xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:00001f0000001f02 00001f0800001f10
+xvxsigsp xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:00101f0000101f02 00101f0800101f10
+xvxsigsp xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:00101f0000101f02 00101f0800101f10
+
+xsxexpdp xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xsxexpdp xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xsxexpdp xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0102030405060708 0102010201020102
+xsxexpdp xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0102030405060708 0102010201020102
+xsxexpdp xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:0011223344556677 8899aabbccddeeff
+xsxexpdp xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:0011223344556677 8899aabbccddeeff
+xsxexpdp xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:f0e0d0c0b0a09080 7060504030201000
+xsxexpdp xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:f0e0d0c0b0a09080 7060504030201000
+xsxexpdp xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010
+xsxexpdp xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000100000001002 0000100800001010
+xsxexpdp xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0010100000101002 0010100800101010
+xsxexpdp xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0010100000101002 0010100800101010
+xsxexpdp xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10
+xsxexpdp xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:00001c0000001c02 00001c0800001c10
+xsxexpdp xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:00101c0000101c02 00101c0800101c10
+xsxexpdp xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:00101c0000101c02 00101c0800101c10
+xsxexpdp xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10
+xsxexpdp xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:00001f0000001f02 00001f0800001f10
+xsxexpdp xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:00101f0000101f02 00101f0800101f10
+xsxexpdp xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:00101f0000101f02 00101f0800101f10
+
+xsxsigdp xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xsxsigdp xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xsxsigdp xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0102030405060708 0102010201020102
+xsxsigdp xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0102030405060708 0102010201020102
+xsxsigdp xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:0011223344556677 8899aabbccddeeff
+xsxsigdp xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:0011223344556677 8899aabbccddeeff
+xsxsigdp xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:f0e0d0c0b0a09080 7060504030201000
+xsxsigdp xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:f0e0d0c0b0a09080 7060504030201000
+xsxsigdp xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010
+xsxsigdp xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000100000001002 0000100800001010
+xsxsigdp xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0010100000101002 0010100800101010
+xsxsigdp xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0010100000101002 0010100800101010
+xsxsigdp xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10
+xsxsigdp xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:00001c0000001c02 00001c0800001c10
+xsxsigdp xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:00101c0000101c02 00101c0800101c10
+xsxsigdp xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:00101c0000101c02 00101c0800101c10
+xsxsigdp xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10
+xsxsigdp xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:00001f0000001f02 00001f0800001f10
+xsxsigdp xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:00101f0000101f02 00101f0800101f10
+xsxsigdp xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:00101f0000101f02 00101f0800101f10
+
+All done. Tested 33 different instructions
+ppc vector extend sign:
+Test instruction group [ppc vector extend sign]
+vextsb2w 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vextsb2w 0102010201020102 0102030405060708 => 0000000200000002 0000000400000008
+vextsb2w 8899aabbccddeeff 0011223344556677 => ffffffbbffffffff 0000003300000077
+vextsb2w 7060504030201000 f0e0d0c0b0a09080 => 0000004000000000 ffffffc0ffffff80
+vextsb2w 0000100800001010 0000100000001002 => 0000000800000010 0000000000000002
+vextsb2w 0010100800101010 0010100000101002 => 0000000800000010 0000000000000002
+vextsb2w 00001c0800001c10 00001c0000001c02 => 0000000800000010 0000000000000002
+vextsb2w 00101c0800101c10 00101c0000101c02 => 0000000800000010 0000000000000002
+vextsb2w 00001f0800001f10 00001f0000001f02 => 0000000800000010 0000000000000002
+vextsb2w 00101f0800101f10 00101f0000101f02 => 0000000800000010 0000000000000002
+
+vextsb2d 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vextsb2d 0102010201020102 0102030405060708 => 0000000000000002 0000000000000008
+vextsb2d 8899aabbccddeeff 0011223344556677 => ffffffffffffffff 0000000000000077
+vextsb2d 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 ffffffffffffff80
+vextsb2d 0000100800001010 0000100000001002 => 0000000000000010 0000000000000002
+vextsb2d 0010100800101010 0010100000101002 => 0000000000000010 0000000000000002
+vextsb2d 00001c0800001c10 00001c0000001c02 => 0000000000000010 0000000000000002
+vextsb2d 00101c0800101c10 00101c0000101c02 => 0000000000000010 0000000000000002
+vextsb2d 00001f0800001f10 00001f0000001f02 => 0000000000000010 0000000000000002
+vextsb2d 00101f0800101f10 00101f0000101f02 => 0000000000000010 0000000000000002
+
+vextsh2w 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vextsh2w 0102010201020102 0102030405060708 => 0000010200000102 0000030400000708
+vextsh2w 8899aabbccddeeff 0011223344556677 => ffffaabbffffeeff 0000223300006677
+vextsh2w 7060504030201000 f0e0d0c0b0a09080 => 0000504000001000 ffffd0c0ffff9080
+vextsh2w 0000100800001010 0000100000001002 => 0000100800001010 0000100000001002
+vextsh2w 0010100800101010 0010100000101002 => 0000100800001010 0000100000001002
+vextsh2w 00001c0800001c10 00001c0000001c02 => 00001c0800001c10 00001c0000001c02
+vextsh2w 00101c0800101c10 00101c0000101c02 => 00001c0800001c10 00001c0000001c02
+vextsh2w 00001f0800001f10 00001f0000001f02 => 00001f0800001f10 00001f0000001f02
+vextsh2w 00101f0800101f10 00101f0000101f02 => 00001f0800001f10 00001f0000001f02
+
+vextsh2d 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vextsh2d 0102010201020102 0102030405060708 => 0000000000000102 0000000000000708
+vextsh2d 8899aabbccddeeff 0011223344556677 => ffffffffffffeeff 0000000000006677
+vextsh2d 7060504030201000 f0e0d0c0b0a09080 => 0000000000001000 ffffffffffff9080
+vextsh2d 0000100800001010 0000100000001002 => 0000000000001010 0000000000001002
+vextsh2d 0010100800101010 0010100000101002 => 0000000000001010 0000000000001002
+vextsh2d 00001c0800001c10 00001c0000001c02 => 0000000000001c10 0000000000001c02
+vextsh2d 00101c0800101c10 00101c0000101c02 => 0000000000001c10 0000000000001c02
+vextsh2d 00001f0800001f10 00001f0000001f02 => 0000000000001f10 0000000000001f02
+vextsh2d 00101f0800101f10 00101f0000101f02 => 0000000000001f10 0000000000001f02
+
+vextsw2d 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vextsw2d 0102010201020102 0102030405060708 => 0000000001020102 0000000005060708
+vextsw2d 8899aabbccddeeff 0011223344556677 => ffffffffccddeeff 0000000044556677
+vextsw2d 7060504030201000 f0e0d0c0b0a09080 => 0000000030201000 ffffffffb0a09080
+vextsw2d 0000100800001010 0000100000001002 => 0000000000001010 0000000000001002
+vextsw2d 0010100800101010 0010100000101002 => 0000000000101010 0000000000101002
+vextsw2d 00001c0800001c10 00001c0000001c02 => 0000000000001c10 0000000000001c02
+vextsw2d 00101c0800101c10 00101c0000101c02 => 0000000000101c10 0000000000101c02
+vextsw2d 00001f0800001f10 00001f0000001f02 => 0000000000001f10 0000000000001f02
+vextsw2d 00101f0800101f10 00101f0000101f02 => 0000000000101f10 0000000000101f02
+
+vnegw 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vnegw 0102010201020102 0102030405060708 => fefdfefefefdfefe fefdfcfcfaf9f8f8
+vnegw 8899aabbccddeeff 0011223344556677 => 7766554533221101 ffeeddcdbbaa9989
+vnegw 7060504030201000 f0e0d0c0b0a09080 => 8f9fafc0cfdff000 0f1f2f404f5f6f80
+vnegw 0000100800001010 0000100000001002 => ffffeff8ffffeff0 fffff000ffffeffe
+vnegw 0010100800101010 0010100000101002 => ffefeff8ffefeff0 ffeff000ffefeffe
+vnegw 00001c0800001c10 00001c0000001c02 => ffffe3f8ffffe3f0 ffffe400ffffe3fe
+vnegw 00101c0800101c10 00101c0000101c02 => ffefe3f8ffefe3f0 ffefe400ffefe3fe
+vnegw 00001f0800001f10 00001f0000001f02 => ffffe0f8ffffe0f0 ffffe100ffffe0fe
+vnegw 00101f0800101f10 00101f0000101f02 => ffefe0f8ffefe0f0 ffefe100ffefe0fe
+
+vnegd 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vnegd 0102010201020102 0102030405060708 => fefdfefdfefdfefe fefdfcfbfaf9f8f8
+vnegd 8899aabbccddeeff 0011223344556677 => 7766554433221101 ffeeddccbbaa9989
+vnegd 7060504030201000 f0e0d0c0b0a09080 => 8f9fafbfcfdff000 0f1f2f3f4f5f6f80
+vnegd 0000100800001010 0000100000001002 => ffffeff7ffffeff0 ffffefffffffeffe
+vnegd 0010100800101010 0010100000101002 => ffefeff7ffefeff0 ffefefffffefeffe
+vnegd 00001c0800001c10 00001c0000001c02 => ffffe3f7ffffe3f0 ffffe3ffffffe3fe
+vnegd 00101c0800101c10 00101c0000101c02 => ffefe3f7ffefe3f0 ffefe3ffffefe3fe
+vnegd 00001f0800001f10 00001f0000001f02 => ffffe0f7ffffe0f0 ffffe0ffffffe0fe
+vnegd 00101f0800101f10 00101f0000101f02 => ffefe0f7ffefe0f0 ffefe0ffffefe0fe
+
+vprtybw 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vprtybw 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+vprtybw 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+vprtybw 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 0000000000000000
+vprtybw 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+vprtybw 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+vprtybw 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+vprtybw 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+vprtybw 00001f0800001f10 00001f0000001f02 => 0000000100000001 0000000100000001
+vprtybw 00101f0800101f10 00101f0000101f02 => 0000000100000001 0000000100000001
+
+vprtybd 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vprtybd 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+vprtybd 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+vprtybd 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 0000000000000000
+vprtybd 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+vprtybd 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+vprtybd 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+vprtybd 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+vprtybd 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+vprtybd 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+vprtybq 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+vprtybq 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+vprtybq 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+vprtybq 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 0000000000000000
+vprtybq 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+vprtybq 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+vprtybq 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+vprtybq 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+vprtybq 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+vprtybq 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+vctzb 0000000000000000 0000000000000000 => 0808080808080808 0808080808080808
+vctzb 0102010201020102 0102030405060708 => 0001000100010001 0001000200010003
+vctzb 8899aabbccddeeff 0011223344556677 => 0300010002000100 0800010002000100
+vctzb 7060504030201000 f0e0d0c0b0a09080 => 0405040604050408 0405040604050407
+vctzb 0000100800001010 0000100000001002 => 0808040308080404 0808040808080401
+vctzb 0010100800101010 0010100000101002 => 0804040308040404 0804040808040401
+vctzb 00001c0800001c10 00001c0000001c02 => 0808020308080204 0808020808080201
+vctzb 00101c0800101c10 00101c0000101c02 => 0804020308040204 0804020808040201
+vctzb 00001f0800001f10 00001f0000001f02 => 0808000308080004 0808000808080001
+vctzb 00101f0800101f10 00101f0000101f02 => 0804000308040004 0804000808040001
+
+vctzh 0000000000000000 0000000000000000 => 0010001000100010 0010001000100010
+vctzh 0102010201020102 0102030405060708 => 0001000100010001 0001000200010003
+vctzh 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+vctzh 7060504030201000 f0e0d0c0b0a09080 => 000500060005000c 0005000600050007
+vctzh 0000100800001010 0000100000001002 => 0010000300100004 0010000c00100001
+vctzh 0010100800101010 0010100000101002 => 0004000300040004 0004000c00040001
+vctzh 00001c0800001c10 00001c0000001c02 => 0010000300100004 0010000a00100001
+vctzh 00101c0800101c10 00101c0000101c02 => 0004000300040004 0004000a00040001
+vctzh 00001f0800001f10 00001f0000001f02 => 0010000300100004 0010000800100001
+vctzh 00101f0800101f10 00101f0000101f02 => 0004000300040004 0004000800040001
+
+vctzw 0000000000000000 0000000000000000 => 0000002000000020 0000002000000020
+vctzw 0102010201020102 0102030405060708 => 0000000100000001 0000000200000003
+vctzw 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+vctzw 7060504030201000 f0e0d0c0b0a09080 => 000000060000000c 0000000600000007
+vctzw 0000100800001010 0000100000001002 => 0000000300000004 0000000c00000001
+vctzw 0010100800101010 0010100000101002 => 0000000300000004 0000000c00000001
+vctzw 00001c0800001c10 00001c0000001c02 => 0000000300000004 0000000a00000001
+vctzw 00101c0800101c10 00101c0000101c02 => 0000000300000004 0000000a00000001
+vctzw 00001f0800001f10 00001f0000001f02 => 0000000300000004 0000000800000001
+vctzw 00101f0800101f10 00101f0000101f02 => 0000000300000004 0000000800000001
+
+vctzd 0000000000000000 0000000000000000 => 0000000000000040 0000000000000040
+vctzd 0102010201020102 0102030405060708 => 0000000000000001 0000000000000003
+vctzd 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+vctzd 7060504030201000 f0e0d0c0b0a09080 => 000000000000000c 0000000000000007
+vctzd 0000100800001010 0000100000001002 => 0000000000000004 0000000000000001
+vctzd 0010100800101010 0010100000101002 => 0000000000000004 0000000000000001
+vctzd 00001c0800001c10 00001c0000001c02 => 0000000000000004 0000000000000001
+vctzd 00101c0800101c10 00101c0000101c02 => 0000000000000004 0000000000000001
+vctzd 00001f0800001f10 00001f0000001f02 => 0000000000000004 0000000000000001
+vctzd 00101f0800101f10 00101f0000101f02 => 0000000000000004 0000000000000001
+
+All done. Tested 47 different instructions
+ppc vector three quad:
+Test instruction group [ppc vector three quad]
+xsaddqp 00000000000000000000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
+xsaddqp 00000000000000000000000000000000 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
+xsaddqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 00000000000000000000000000000000 => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000007fffffffffff 00000000000000000000000000000000 => 000000000000000000007fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000000007fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff0000000000000000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff000000000000 00000000000000000000000000000000 => 000000000000000000ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 000000000000000000ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000000ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff000000000000 00000000000000000000000000000000 => 000000000000000007ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000007ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 000000000000000007ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000007ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsaddqp 00000000000000000000000000000000 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsaddqp 00000000000000000000000000000000 00000000000000007fff000000000000 00000000000000000000000000000000 => 00000000000000007fff000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007fff000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsaddqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsaddqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00000000000000007fff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007fff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 80000000000000000000000000000000 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
+xsaddqp 00000000000000000000000000000000 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
+xsaddqp 00000000000000000000000000000000 00000000000000008000000000000000 00000000000000000000000000000000 => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsaddqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000080007fffffffffff 00000000000000000000000000000000 => 000000000000000080007fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080007fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 80ff0000000000000000000000000000 00000000000000000000000000000000 => 80ff0000000000000000000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80ff0000000000000000000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => 000000000000000080ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000080ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 000000000000000080ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => 87ff0000000000000000000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87ff0000000000000000000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => 000000000000000087ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000087ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 000000000000000087ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000087ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsaddqp 00000000000000000000000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsaddqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 00000000000000000000000000000000 => 0000fffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000fffffffffffe0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff 00000000000000000000000000000000 => 00007fffffffffff00007fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff00007fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 00000000000000000000000000000000 => 00007fffffffffff00ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff00ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000000 FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000000 FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff00ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff00ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000000 FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000000 FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 00000000000000000000000000000000 => 00007fffffffffff07ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff07ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff07ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff07ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 00000000000000000000000000000000 => 00007fffffffffff7fff000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff7fff000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff7fff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff7fff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 00000000000000000000000000000000 => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 00000000000000000000000000000000 => 00007fffffffffff8000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff8000000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
+xsaddqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
+xsaddqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff 00000000000000000000000000000000 => 00007fffffffffff80007fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff80007fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 00000000000000000000000000000000 => 80ff0000000000000000000000000000 FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80ff0000000000000000000000000000 FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => 00007fffffffffff80ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff80ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff80ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff80ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => 87ff0000000000000000000000000000 FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87ff0000000000000000000000000000 FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => 00007fffffffffff87ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff87ff000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff87ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff87ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => 00007fffffffffffffff000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffffffff000000000000 FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffffffff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffffffff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 00000000000000000000000000000000 00000000000000000000000000000000 => 000000000000000000007fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000007fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 00000000000000000000000000000000 => 00007fffffffffff00007fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff00007fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff 00000000000000000000000000000000 => 00000000000000000000fffffffffffe FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000000000fffffffffffe FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 00000000000000000000000000000000 => 000000000000000000ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000000 FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000000 FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 000000000000000000fffffffffffffe FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000000fffffffffffffe FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000000 FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000000 FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 00000000000000000000000000000000 => 000000000000000007ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000007ff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 000000000000000007fffffffffffffe FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000007fffffffffffffe FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsaddqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsaddqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 00000000000000000000000000000000 => 00000000000000007fff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007fff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsaddqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsaddqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00000000000000007ffffffffffffffe FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007ffffffffffffffe FPRF-C FPCC-FG
+xsaddqp 000000000000000000007fffffffffff 80000000000000000000000000000000 00000000000000000000000000000000 => 000000000000000000007fffffffffff FPRF-C FPCC-FG
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+xsaddqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000000 FPCC-FG
+xsaddqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000000 FPCC-FG
+xsaddqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 00000000000000000000000000000000 => 00000000000000000ffe7fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000ffe7fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsaddqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsaddqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 00000000000000000ffefffffffffffe FPRF-C FPCC-FG
+xsaddqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000000ffefffffffffffe FPRF-C FPCC-FG
+xsaddqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsaddqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsaddqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 00000000000000000000000000000000 => 000000000000000087fe7fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000087fe7fffffffffff FPRF-C FPCC-FG
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+xsaddqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
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+xsaddqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80ff0000000000000000000000000000 FPCC-FL
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+xsaddqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80ff7fffffffffff0000000000000000 FPCC-FL
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+xsaddqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000088fefffffffffffe FPRF-C FPCC-FG
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+xsaddqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87ff0000000000000000000000000000 FPCC-FL
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+xsaddqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsaddqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 00000000000000008ffefffffffffffe FPRF-C FPCC-FG
+xsaddqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000008ffefffffffffffe FPRF-C FPCC-FG
+xsaddqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 00000000000000000000000000000000 => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsaddqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsaddqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 00000000000000000000000000000000 => 000000000000000107fe7fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000107fe7fffffffffff FPRF-C FPCC-FG
+xsaddqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsaddqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsaddqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 000000000000000107fefffffffffffe FPRF-C FPCC-FG
+xsaddqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000107fefffffffffffe FPRF-C FPCC-FG
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+xsaddqp 7fff0000000000000000000000000000 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsaddqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsaddqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsaddqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsaddqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsaddqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsaddqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsaddqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsaddqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsaddqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsaddqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsaddqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsaddqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsaddqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsaddqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsdivqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => b7cb554000000000e35555555555ece4 FPCC-FL
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+xsdivqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 3ffae1c5893263023ed87ab80c575c93 FPCC-FG
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+xsdivqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
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+xsdivqpo 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 482d000080004000200110010800c401 FPCC-FG
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+xsdivqpo 000000000000000007ff000000000000 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsdivqpo 000000000000000007ff7fffffffffff 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
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+xsnmaddqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffffffffffffffffffff FPRF-C FPCC-FU
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+xsnmaddqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffffffffffffffffffff FPRF-C FPCC-FU
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+xsnmaddqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffffffffffffffffffff FPRF-C FPCC-FU
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+xssubqpo 0000000000000000ffff000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => 00000000000000007f00000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007f00000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000001 FPCC-FG
+xssubqpo 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000001 FPCC-FG
+xssubqpo 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 00000000000000007eff800000000001 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007eff800000000001 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000001 FPCC-FG
+xssubqpo 0000000000000000ffff000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000001 FPCC-FG
+xssubqpo 0000000000000000ffff000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => 00000000000000007800000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007800000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000001 FPCC-FG
+xssubqpo 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000001 FPCC-FG
+xssubqpo 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 000000000000000077ff800000000001 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000077ff800000000001 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
+xssubqpo 0000000000000000ffff000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
+xssubqpo 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 800000000000000000007fffffffffff FPRF-C FPCC-FL
+xssubqpo 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 800000000000000000007fffffffffff FPRF-C FPCC-FL
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 80000000000000000000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000008000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 00000000000000000000000000000000 => 0000000000000000ffff7fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff7fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 00000000000000000000000000000000 => 80007ffffffffffe0000800000000001 FPRF-C FPCC-FL
+xssubqpo 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80007ffffffffffe0000800000000001 FPRF-C FPCC-FL
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 00000000000000000000000000000000 => 80feffffffffffffffffffffffffffff FPCC-FL
+xssubqpo 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80feffffffffffffffffffffffffffff FPCC-FL
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 00000000000000000000000000000000 => 0000000000000000ff007fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ff007fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80ff7ffffffffffeffffffffffffffff FPCC-FL
+xssubqpo 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80ff7ffffffffffeffffffffffffffff FPCC-FL
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ff00000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ff00000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 00000000000000000000000000000000 => 87feffffffffffffffffffffffffffff FPCC-FL
+xssubqpo 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87feffffffffffffffffffffffffffff FPCC-FL
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 00000000000000000000000000000000 => 0000000000000000f8007fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000f8007fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 87ff7ffffffffffeffffffffffffffff FPCC-FL
+xssubqpo 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87ff7ffffffffffeffffffffffffffff FPCC-FL
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 0000000000000000f800000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000f800000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 00000000000000000000000000000000 => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 00000000000000000000000000000000 => 000000000000000080007fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000080007fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 00000000000000000000000000000000 => 0000000000000000ffff7fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff7fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 00000000000000000000000000000000 => 00000000000000007fff7fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007fff7fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 00007fffffffffffffff7fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffffffff7fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff 00000000000000000000000000000000 => 00000000000000007fff000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007fff000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000001 FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000001 FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 00000000000000000000000000000000 => 00000000000000007f007fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007f007fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000001 FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000001 FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 00000000000000007f00000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007f00000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000001 FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000001 FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 00000000000000000000000000000000 => 000000000000000078007fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000078007fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000001 FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000001 FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 00000000000000007800000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007800000000000000 FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 00000000000000000000000000000000 => 000000000000000000007fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000007fffffffffff FPRF-C FPCC-FG
+xssubqpo 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xssubqpo 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
+xssubqpo 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
+
+All done. Tested 65 different instructions
+ppc vector scalar quad:
+Test instruction group [ppc vector scalar quad]
+xsabsqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xsabsqp 0102010201020102 0102030405060708 => 0102010201020102 0102030405060708
+xsabsqp 8899aabbccddeeff 0011223344556677 => 0899aabbccddeeff 0011223344556677
+xsabsqp 7060504030201000 f0e0d0c0b0a09080 => 7060504030201000 f0e0d0c0b0a09080
+xsabsqp 0000100800001010 0000100000001002 => 0000100800001010 0000100000001002
+xsabsqp 0010100800101010 0010100000101002 => 0010100800101010 0010100000101002
+xsabsqp 00001c0800001c10 00001c0000001c02 => 00001c0800001c10 00001c0000001c02
+xsabsqp 00101c0800101c10 00101c0000101c02 => 00101c0800101c10 00101c0000101c02
+xsabsqp 00001f0800001f10 00001f0000001f02 => 00001f0800001f10 00001f0000001f02
+xsabsqp 00101f0800101f10 00101f0000101f02 => 00101f0800101f10 00101f0000101f02
+
+xscvdpqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvdpqp 0102010201020102 0102030405060708 => 3c10201020102010 2000000000000000 FPCC-FG
+xscvdpqp 8899aabbccddeeff 0011223344556677 => bc899aabbccddeef f000000000000000 FPCC-FL
+xscvdpqp 7060504030201000 f0e0d0c0b0a09080 => 4306050403020100 0000000000000000 FPCC-FG
+xscvdpqp 0000100800001010 0000100000001002 => 3bf9008000010100 0000000000000000 FPCC-FG
+xscvdpqp 0010100800101010 0010100000101002 => 3c01010080010101 0000000000000000 FPCC-FG
+xscvdpqp 00001c0800001c10 00001c0000001c02 => 3bf9c0800001c100 0000000000000000 FPCC-FG
+xscvdpqp 00101c0800101c10 00101c0000101c02 => 3c0101c0800101c1 0000000000000000 FPCC-FG
+xscvdpqp 00001f0800001f10 00001f0000001f02 => 3bf9f0800001f100 0000000000000000 FPCC-FG
+xscvdpqp 00101f0800101f10 00101f0000101f02 => 3c0101f0800101f1 0000000000000000 FPCC-FG
+
+xscvqpdp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 8899aabbccddeeff 0011223344556677 => 8000000000000000 0000000000000000 FPRF-C FPCC-FE
+xscvqpdp 7060504030201000 f0e0d0c0b0a09080 => 7ff0000000000000 0000000000000000 FPCC-FG FPCC-FU
+xscvqpdp 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000 FPCC-FE
+
+xscvqpdpo 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdpo 0102010201020102 0102030405060708 => 0000000000000001 0000000000000000 FPRF-C FPCC-FG
+xscvqpdpo 8899aabbccddeeff 0011223344556677 => 8000000000000001 0000000000000000 FPRF-C FPCC-FL
+xscvqpdpo 7060504030201000 f0e0d0c0b0a09080 => 7fefffffffffffff 0000000000000000 FPCC-FG
+xscvqpdpo 0000100800001010 0000100000001002 => 0000000000000001 0000000000000000 FPRF-C FPCC-FG
+xscvqpdpo 0010100800101010 0010100000101002 => 0000000000000001 0000000000000000 FPRF-C FPCC-FG
+xscvqpdpo 00001c0800001c10 00001c0000001c02 => 0000000000000001 0000000000000000 FPRF-C FPCC-FG
+xscvqpdpo 00101c0800101c10 00101c0000101c02 => 0000000000000001 0000000000000000 FPRF-C FPCC-FG
+xscvqpdpo 00001f0800001f10 00001f0000001f02 => 0000000000000001 0000000000000000 FPRF-C FPCC-FG
+xscvqpdpo 00101f0800101f10 00101f0000101f02 => 0000000000000001 0000000000000000 FPRF-C FPCC-FG
+
+xscvqpsdz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpsdz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpsdz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpsdz 7060504030201000 f0e0d0c0b0a09080 => 7fffffffffffffff 0000000000000000
+xscvqpsdz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpsdz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpsdz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpsdz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpsdz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpsdz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvqpswz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpswz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpswz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpswz 7060504030201000 f0e0d0c0b0a09080 => 000000007fffffff 0000000000000000
+xscvqpswz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpswz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpswz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpswz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpswz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpswz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvqpudz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpudz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpudz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpudz 7060504030201000 f0e0d0c0b0a09080 => ffffffffffffffff 0000000000000000
+xscvqpudz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpudz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpudz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpudz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpudz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpudz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvqpuwz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpuwz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpuwz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpuwz 7060504030201000 f0e0d0c0b0a09080 => 00000000ffffffff 0000000000000000
+xscvqpuwz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpuwz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpuwz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpuwz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpuwz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpuwz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvsdqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvsdqp 0102010201020102 0102030405060708 => 4037020102010201 0200000000000000 FPCC-FG
+xscvsdqp 8899aabbccddeeff 0011223344556677 => c03ddd995510cc88 4404000000000000 FPCC-FL
+xscvsdqp 7060504030201000 f0e0d0c0b0a09080 => 403dc1814100c080 4000000000000000 FPCC-FG
+xscvsdqp 0000100800001010 0000100000001002 => 402b008000010100 0000000000000000 FPCC-FG
+xscvsdqp 0010100800101010 0010100000101002 => 4033010080010101 0000000000000000 FPCC-FG
+xscvsdqp 00001c0800001c10 00001c0000001c02 => 402bc0800001c100 0000000000000000 FPCC-FG
+xscvsdqp 00101c0800101c10 00101c0000101c02 => 403301c0800101c1 0000000000000000 FPCC-FG
+xscvsdqp 00001f0800001f10 00001f0000001f02 => 402bf0800001f100 0000000000000000 FPCC-FG
+xscvsdqp 00101f0800101f10 00101f0000101f02 => 403301f0800101f1 0000000000000000 FPCC-FG
+
+xscvudqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvudqp 0102010201020102 0102030405060708 => 4037020102010201 0200000000000000 FPCC-FG
+xscvudqp 8899aabbccddeeff 0011223344556677 => 403e1133557799bb ddfe000000000000 FPCC-FG
+xscvudqp 7060504030201000 f0e0d0c0b0a09080 => 403dc1814100c080 4000000000000000 FPCC-FG
+xscvudqp 0000100800001010 0000100000001002 => 402b008000010100 0000000000000000 FPCC-FG
+xscvudqp 0010100800101010 0010100000101002 => 4033010080010101 0000000000000000 FPCC-FG
+xscvudqp 00001c0800001c10 00001c0000001c02 => 402bc0800001c100 0000000000000000 FPCC-FG
+xscvudqp 00101c0800101c10 00101c0000101c02 => 403301c0800101c1 0000000000000000 FPCC-FG
+xscvudqp 00001f0800001f10 00001f0000001f02 => 402bf0800001f100 0000000000000000 FPCC-FG
+xscvudqp 00101f0800101f10 00101f0000101f02 => 403301f0800101f1 0000000000000000 FPCC-FG
+
+xsxexpqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xsxexpqp 0102010201020102 0102030405060708 => 0000000000000102 0000000000000000
+xsxexpqp 8899aabbccddeeff 0011223344556677 => 0000000000000899 0000000000000000
+xsxexpqp 7060504030201000 f0e0d0c0b0a09080 => 0000000000007060 0000000000000000
+xsxexpqp 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xsxexpqp 0010100800101010 0010100000101002 => 0000000000000010 0000000000000000
+xsxexpqp 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xsxexpqp 00101c0800101c10 00101c0000101c02 => 0000000000000010 0000000000000000
+xsxexpqp 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xsxexpqp 00101f0800101f10 00101f0000101f02 => 0000000000000010 0000000000000000
+
+xsxsigqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xsxsigqp 0102010201020102 0102030405060708 => 0001010201020102 0102030405060708
+xsxsigqp 8899aabbccddeeff 0011223344556677 => 0001aabbccddeeff 0011223344556677
+xsxsigqp 7060504030201000 f0e0d0c0b0a09080 => 0001504030201000 f0e0d0c0b0a09080
+xsxsigqp 0000100800001010 0000100000001002 => 0000100800001010 0000100000001002
+xsxsigqp 0010100800101010 0010100000101002 => 0001100800101010 0010100000101002
+xsxsigqp 00001c0800001c10 00001c0000001c02 => 00001c0800001c10 00001c0000001c02
+xsxsigqp 00101c0800101c10 00101c0000101c02 => 00011c0800101c10 00101c0000101c02
+xsxsigqp 00001f0800001f10 00001f0000001f02 => 00001f0800001f10 00001f0000001f02
+xsxsigqp 00101f0800101f10 00101f0000101f02 => 00011f0800101f10 00101f0000101f02
+
+xsnegqp 0000000000000000 0000000000000000 => 8000000000000000 0000000000000000
+xsnegqp 0102010201020102 0102030405060708 => 8102010201020102 0102030405060708
+xsnegqp 8899aabbccddeeff 0011223344556677 => 0899aabbccddeeff 0011223344556677
+xsnegqp 7060504030201000 f0e0d0c0b0a09080 => f060504030201000 f0e0d0c0b0a09080
+xsnegqp 0000100800001010 0000100000001002 => 8000100800001010 0000100000001002
+xsnegqp 0010100800101010 0010100000101002 => 8010100800101010 0010100000101002
+xsnegqp 00001c0800001c10 00001c0000001c02 => 80001c0800001c10 00001c0000001c02
+xsnegqp 00101c0800101c10 00101c0000101c02 => 80101c0800101c10 00101c0000101c02
+xsnegqp 00001f0800001f10 00001f0000001f02 => 80001f0800001f10 00001f0000001f02
+xsnegqp 00101f0800101f10 00101f0000101f02 => 80101f0800101f10 00101f0000101f02
+
+xsnabsqp 0000000000000000 0000000000000000 => 8000000000000000 0000000000000000
+xsnabsqp 0102010201020102 0102030405060708 => 8102010201020102 0102030405060708
+xsnabsqp 8899aabbccddeeff 0011223344556677 => 8899aabbccddeeff 0011223344556677
+xsnabsqp 7060504030201000 f0e0d0c0b0a09080 => f060504030201000 f0e0d0c0b0a09080
+xsnabsqp 0000100800001010 0000100000001002 => 8000100800001010 0000100000001002
+xsnabsqp 0010100800101010 0010100000101002 => 8010100800101010 0010100000101002
+xsnabsqp 00001c0800001c10 00001c0000001c02 => 80001c0800001c10 00001c0000001c02
+xsnabsqp 00101c0800101c10 00101c0000101c02 => 80101c0800101c10 00101c0000101c02
+xsnabsqp 00001f0800001f10 00001f0000001f02 => 80001f0800001f10 00001f0000001f02
+xsnabsqp 00101f0800101f10 00101f0000101f02 => 80101f0800101f10 00101f0000101f02
+
+xssqrtqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xssqrtqp 0102010201020102 0102030405060708 => 20806ac0283b4649 8c0632d6a11d770a FPCC-FG
+xssqrtqp 8899aabbccddeeff 0011223344556677 => 7fff800000000000 0000000000000000 FPRF-C FPCC-FU
+xssqrtqp 7060504030201000 f0e0d0c0b0a09080 => 582f9eec10deec2d 14b6d4051d1809ae FPCC-FG
+xssqrtqp 0000100800001010 0000100000001002 => 1ffe003ff8027fc0 23f26525e7dab5d6 FPCC-FG
+xssqrtqp 0010100800101010 0010100000101002 => 20077533cdc68455 038f4ca025c1dc6e FPCC-FG
+xssqrtqp 00001c0800001c10 00001c0000001c02 => 1ffe52d8584d7da4 9620bb68d1dc754f FPCC-FG
+xssqrtqp 00101c0800101c10 00101c0000101c02 => 20077d58512fcec9 1634733d8b112799 FPCC-FG
+xssqrtqp 00001f0800001f10 00001f0000001f02 => 1ffe648437fd2de6 cb7713e7fab3286e FPCC-FG
+xssqrtqp 00101f0800101f10 00101f0000101f02 => 20077f5a870e5f2b c13ab6ba2329d3e0 FPCC-FG
+
+xssqrtqpo 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xssqrtqpo 0102010201020102 0102030405060708 => 20806ac0283b4649 8c0632d6a11d770b FPCC-FG
+xssqrtqpo 8899aabbccddeeff 0011223344556677 => 7fff800000000000 0000000000000000 FPRF-C FPCC-FU
+xssqrtqpo 7060504030201000 f0e0d0c0b0a09080 => 582f9eec10deec2d 14b6d4051d1809af FPCC-FG
+xssqrtqpo 0000100800001010 0000100000001002 => 1ffe003ff8027fc0 23f26525e7dab5d5 FPCC-FG
+xssqrtqpo 0010100800101010 0010100000101002 => 20077533cdc68455 038f4ca025c1dc6f FPCC-FG
+xssqrtqpo 00001c0800001c10 00001c0000001c02 => 1ffe52d8584d7da4 9620bb68d1dc754f FPCC-FG
+xssqrtqpo 00101c0800101c10 00101c0000101c02 => 20077d58512fcec9 1634733d8b112799 FPCC-FG
+xssqrtqpo 00001f0800001f10 00001f0000001f02 => 1ffe648437fd2de6 cb7713e7fab3286f FPCC-FG
+xssqrtqpo 00101f0800101f10 00101f0000101f02 => 20077f5a870e5f2b c13ab6ba2329d3df FPCC-FG
+
+All done. Tested 81 different instructions
+ppc vector scalar compare exponents quads:
+Test instruction group [ppc vector scalar compare exponents quads]
+xscmpexpqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+
+xscmpoqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+
+xscmpuqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FE
+
+All done. Tested 84 different instructions
+ppc vector scalar rounding quads:
+Test instruction group [ppc vector scalar rounding quads]
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=2) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=2) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=0) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=1) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=2) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=3) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=0) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=1) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=2) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=3) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpi 00000000000000007fff000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000007fff000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000007fff000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00000000000000007fff000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000007fff000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000007fff000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000007fff000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00000000000000007fff000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff7fffffffffff0000000000000000 (R=0) (RMC=0) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi 7fff7fffffffffff0000000000000000 (R=0) (RMC=1) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi 7fff7fffffffffff0000000000000000 (R=0) (RMC=2) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi 7fff7fffffffffff0000000000000000 (R=0) (RMC=3) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi 7fff7fffffffffff0000000000000000 (R=1) (RMC=0) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi 7fff7fffffffffff0000000000000000 (R=1) (RMC=1) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi 7fff7fffffffffff0000000000000000 (R=1) (RMC=2) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi 7fff7fffffffffff0000000000000000 (R=1) (RMC=3) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi 00000000000000007fff7fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000007fff7fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000007fff7fffffffffff (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00000000000000007fff7fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000007fff7fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000007fff7fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000007fff7fffffffffff (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00000000000000007fff7fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80000000000000000000000000000000 (R=0) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80000000000000000000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80000000000000000000000000000000 (R=0) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80000000000000000000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80000000000000000000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80000000000000000000000000000000 (R=1) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80000000000000000000000000000000 (R=1) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80000000000000000000000000000000 (R=1) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 00000000000000008000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000008000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000008000000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00000000000000008000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000008000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000008000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000008000000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 00000000000000008000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80007fffffffffff0000000000000000 (R=0) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80007fffffffffff0000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80007fffffffffff0000000000000000 (R=0) (RMC=2) => bfff0000000000000000000000000000 FPCC-FL
+xsrqpi 80007fffffffffff0000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80007fffffffffff0000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80007fffffffffff0000000000000000 (R=1) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80007fffffffffff0000000000000000 (R=1) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80007fffffffffff0000000000000000 (R=1) (RMC=3) => bfff0000000000000000000000000000 FPCC-FL
+xsrqpi 000000000000000080007fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080007fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080007fffffffffff (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000080007fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080007fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080007fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080007fffffffffff (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000080007fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80ff0000000000000000000000000000 (R=0) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80ff0000000000000000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80ff0000000000000000000000000000 (R=0) (RMC=2) => bfff0000000000000000000000000000 FPCC-FL
+xsrqpi 80ff0000000000000000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80ff0000000000000000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80ff0000000000000000000000000000 (R=1) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80ff0000000000000000000000000000 (R=1) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80ff0000000000000000000000000000 (R=1) (RMC=3) => bfff0000000000000000000000000000 FPCC-FL
+xsrqpi 000000000000000080ff000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080ff000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080ff000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000080ff000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080ff000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080ff000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080ff000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000080ff000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 80ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80ff7fffffffffff0000000000000000 (R=0) (RMC=2) => bfff0000000000000000000000000000 FPCC-FL
+xsrqpi 80ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 80ff7fffffffffff0000000000000000 (R=1) (RMC=3) => bfff0000000000000000000000000000 FPCC-FL
+xsrqpi 000000000000000080ff7fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080ff7fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080ff7fffffffffff (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000080ff7fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080ff7fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080ff7fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000080ff7fffffffffff (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000080ff7fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 87ff0000000000000000000000000000 (R=0) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 87ff0000000000000000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 87ff0000000000000000000000000000 (R=0) (RMC=2) => bfff0000000000000000000000000000 FPCC-FL
+xsrqpi 87ff0000000000000000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 87ff0000000000000000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 87ff0000000000000000000000000000 (R=1) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 87ff0000000000000000000000000000 (R=1) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 87ff0000000000000000000000000000 (R=1) (RMC=3) => bfff0000000000000000000000000000 FPCC-FL
+xsrqpi 000000000000000087ff000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000087ff000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000087ff000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000087ff000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000087ff000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000087ff000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000087ff000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000087ff000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 87ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 87ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 87ff7fffffffffff0000000000000000 (R=0) (RMC=2) => bfff0000000000000000000000000000 FPCC-FL
+xsrqpi 87ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 87ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 87ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 87ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpi 87ff7fffffffffff0000000000000000 (R=1) (RMC=3) => bfff0000000000000000000000000000 FPCC-FL
+xsrqpi 000000000000000087ff7fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000087ff7fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000087ff7fffffffffff (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000087ff7fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000087ff7fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000087ff7fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000087ff7fffffffffff (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 000000000000000087ff7fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi ffff0000000000000000000000000000 (R=0) (RMC=0) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpi ffff0000000000000000000000000000 (R=0) (RMC=1) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpi ffff0000000000000000000000000000 (R=0) (RMC=2) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpi ffff0000000000000000000000000000 (R=0) (RMC=3) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpi ffff0000000000000000000000000000 (R=1) (RMC=0) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpi ffff0000000000000000000000000000 (R=1) (RMC=1) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpi ffff0000000000000000000000000000 (R=1) (RMC=2) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpi ffff0000000000000000000000000000 (R=1) (RMC=3) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpi 0000000000000000ffff000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 0000000000000000ffff000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 0000000000000000ffff000000000000 (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 0000000000000000ffff000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 0000000000000000ffff000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 0000000000000000ffff000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 0000000000000000ffff000000000000 (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 0000000000000000ffff000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi ffff7fffffffffff0000000000000000 (R=0) (RMC=0) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi ffff7fffffffffff0000000000000000 (R=0) (RMC=1) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi ffff7fffffffffff0000000000000000 (R=0) (RMC=2) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi ffff7fffffffffff0000000000000000 (R=0) (RMC=3) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi ffff7fffffffffff0000000000000000 (R=1) (RMC=0) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi ffff7fffffffffff0000000000000000 (R=1) (RMC=1) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi ffff7fffffffffff0000000000000000 (R=1) (RMC=2) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi ffff7fffffffffff0000000000000000 (R=1) (RMC=3) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpi 0000000000000000ffff7fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 0000000000000000ffff7fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 0000000000000000ffff7fffffffffff (R=0) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 0000000000000000ffff7fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 0000000000000000ffff7fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 0000000000000000ffff7fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 0000000000000000ffff7fffffffffff (R=1) (RMC=2) => 3fff0000000000000000000000000000 FPCC-FG
+xsrqpi 0000000000000000ffff7fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+
+xsrqpix 00000000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpix 00000000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpix 00000000000000000000000000000000 (R=0) (RMC=2) => 00000000000000000000000000000000 FPCC-FE
+xsrqpix 00000000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpix 00000000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpix 00000000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpix 00000000000000000000000000000000 (R=1) (RMC=2) => 00000000000000000000000000000000 FPCC-FE
+xsrqpix 00000000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpix 00007fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpix 00007fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
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+xsrqpxp 000000000000000000007fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpxp 000000000000000000007fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpxp 000000000000000000007fffffffffff (R=0) (RMC=2) => 00000000000000000002000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000007fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpxp 000000000000000000007fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpxp 000000000000000000007fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpxp 000000000000000000007fffffffffff (R=1) (RMC=2) => 00000000000000000002000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000007fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpxp 00ff0000000000000000000000000000 (R=0) (RMC=0) => 00ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 00ff0000000000000000000000000000 (R=0) (RMC=1) => 00ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 00ff0000000000000000000000000000 (R=0) (RMC=2) => 00ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 00ff0000000000000000000000000000 (R=0) (RMC=3) => 00ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 00ff0000000000000000000000000000 (R=1) (RMC=0) => 00ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 00ff0000000000000000000000000000 (R=1) (RMC=1) => 00ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 00ff0000000000000000000000000000 (R=1) (RMC=2) => 00ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 00ff0000000000000000000000000000 (R=1) (RMC=3) => 00ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 000000000000000000ff000000000000 (R=0) (RMC=0) => 00000000000000000100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000ff000000000000 (R=0) (RMC=1) => 00000000000000000100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000ff000000000000 (R=0) (RMC=2) => 00000000000000000100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000ff000000000000 (R=0) (RMC=3) => 00000000000000000100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000ff000000000000 (R=1) (RMC=0) => 00000000000000000100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000ff000000000000 (R=1) (RMC=1) => 000000000000000000fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000ff000000000000 (R=1) (RMC=2) => 00000000000000000100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000ff000000000000 (R=1) (RMC=3) => 000000000000000000fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 00ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 00ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 00ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 00ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 00ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 00ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 00ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 00ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 00ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 00ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 00ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 00ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 000000000000000000ff7fffffffffff (R=0) (RMC=0) => 00000000000000000100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000ff7fffffffffff (R=0) (RMC=1) => 00000000000000000100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000ff7fffffffffff (R=0) (RMC=2) => 00000000000000000100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000ff7fffffffffff (R=0) (RMC=3) => 00000000000000000100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000ff7fffffffffff (R=1) (RMC=0) => 00000000000000000100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000ff7fffffffffff (R=1) (RMC=1) => 000000000000000000fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000ff7fffffffffff (R=1) (RMC=2) => 00000000000000000100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000000ff7fffffffffff (R=1) (RMC=3) => 000000000000000000fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 07ff0000000000000000000000000000 (R=0) (RMC=0) => 07ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 07ff0000000000000000000000000000 (R=0) (RMC=1) => 07ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 07ff0000000000000000000000000000 (R=0) (RMC=2) => 07ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 07ff0000000000000000000000000000 (R=0) (RMC=3) => 07ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 07ff0000000000000000000000000000 (R=1) (RMC=0) => 07ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 07ff0000000000000000000000000000 (R=1) (RMC=1) => 07ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 07ff0000000000000000000000000000 (R=1) (RMC=2) => 07ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 07ff0000000000000000000000000000 (R=1) (RMC=3) => 07ff0000000000000000000000000000 FPCC-FG
+xsrqpxp 000000000000000007ff000000000000 (R=0) (RMC=0) => 00000000000000000800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff000000000000 (R=0) (RMC=1) => 00000000000000000800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff000000000000 (R=0) (RMC=2) => 00000000000000000800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff000000000000 (R=0) (RMC=3) => 00000000000000000800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff000000000000 (R=1) (RMC=0) => 00000000000000000800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff000000000000 (R=1) (RMC=1) => 000000000000000007fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff000000000000 (R=1) (RMC=2) => 00000000000000000800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff000000000000 (R=1) (RMC=3) => 000000000000000007fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 07ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 07ff7fffffffffff0000000000000000 FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=0) (RMC=0) => 00000000000000000800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=0) (RMC=1) => 00000000000000000800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=0) (RMC=2) => 00000000000000000800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=0) (RMC=3) => 00000000000000000800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=1) (RMC=0) => 00000000000000000800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=1) (RMC=1) => 000000000000000007fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=1) (RMC=2) => 00000000000000000800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000007ff7fffffffffff (R=1) (RMC=3) => 000000000000000007fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=0) (RMC=0) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpxp 7fff0000000000000000000000000000 (R=0) (RMC=1) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpxp 7fff0000000000000000000000000000 (R=0) (RMC=2) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpxp 7fff0000000000000000000000000000 (R=0) (RMC=3) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=0) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=1) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=2) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=3) => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=1) => 00000000000000007ffe000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=3) => 00000000000000007ffe000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=0) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=1) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=2) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=3) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=0) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=1) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=2) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=3) => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=1) => 00000000000000007ffe000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=3) => 00000000000000007ffe000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FE
+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80007fffffffffff0000000000000000 (R=0) (RMC=0) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 80007fffffffffff0000000000000000 (R=0) (RMC=1) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 80007fffffffffff0000000000000000 (R=0) (RMC=2) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 80007fffffffffff0000000000000000 (R=0) (RMC=3) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 80007fffffffffff0000000000000000 (R=1) (RMC=0) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 80007fffffffffff0000000000000000 (R=1) (RMC=1) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 80007fffffffffff0000000000000000 (R=1) (RMC=2) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 80007fffffffffff0000000000000000 (R=1) (RMC=3) => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=2) => 00000000000000008002000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=2) => 00000000000000008002000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff0000000000000000000000000000 (R=0) (RMC=0) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=0) (RMC=1) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=0) (RMC=2) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=0) (RMC=3) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=1) (RMC=0) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=1) (RMC=1) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=1) (RMC=2) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=1) (RMC=3) => 80ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 000000000000000080ff000000000000 (R=0) (RMC=0) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=0) (RMC=1) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=0) (RMC=2) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=0) (RMC=3) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=1) (RMC=0) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=1) (RMC=1) => 000000000000000080fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=1) (RMC=2) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=1) (RMC=3) => 000000000000000080fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 80ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 000000000000000080ff7fffffffffff (R=0) (RMC=0) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=0) (RMC=1) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=0) (RMC=2) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=0) (RMC=3) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=1) (RMC=0) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=1) (RMC=1) => 000000000000000080fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=1) (RMC=2) => 00000000000000008100000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=1) (RMC=3) => 000000000000000080fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff0000000000000000000000000000 (R=0) (RMC=0) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=0) (RMC=1) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=0) (RMC=2) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=0) (RMC=3) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=1) (RMC=0) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=1) (RMC=1) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=1) (RMC=2) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=1) (RMC=3) => 87ff0000000000000000000000000000 FPCC-FL
+xsrqpxp 000000000000000087ff000000000000 (R=0) (RMC=0) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=0) (RMC=1) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=0) (RMC=2) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=0) (RMC=3) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=1) (RMC=0) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=1) (RMC=1) => 000000000000000087fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=1) (RMC=2) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=1) (RMC=3) => 000000000000000087fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 87ff7fffffffffff0000000000000000 FPCC-FL
+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=0) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=1) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=2) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=3) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=1) (RMC=0) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=1) (RMC=1) => 000000000000000087fe000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=1) (RMC=2) => 00000000000000008800000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=1) (RMC=3) => 000000000000000087fe000000000000 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=0) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=1) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=2) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=3) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=0) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=1) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=2) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=3) => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=0) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=1) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=2) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=3) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=0) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=1) => 0000000000000000fffe000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=2) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=3) => 0000000000000000fffe000000000000 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=0) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=1) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=2) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=3) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=0) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=1) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=2) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=3) => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=0) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=1) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=2) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=3) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=0) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=1) => 0000000000000000fffe000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=2) => 00000000000000010000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=3) => 0000000000000000fffe000000000000 FPRF-C FPCC-FG
+
+All done. Tested 87 different instructions
+ppc vector permutes:
+Test instruction group [ppc vector permutes]
+xxperm 0000000000000000 0000000000000000 0102010201020102 0102030405060708, pcv[12021a0817141317 100d1b05070f0205] => 0100030002010202 0100040000000000 (00000000)
+xxperm 0000000000000000 0000000000000000 0102010201020102 0102030405060708, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0000000000000000 0000000000000000 (00000000)
+xxperm 8899aabbccddeeff 0011223344556677 7060504030201000 f0e0d0c0b0a09080, pcv[12021a0817141317 100d1b05070f0205] => 50aad00000304000 7055c0ddff77aadd (00000000)
+xxperm 8899aabbccddeeff 0011223344556677 7060504030201000 f0e0d0c0b0a09080, pcv[0705030a0b01ea0c 0e0c09010602080d] => ffddbb2233992244 66441199eeaa0055 (00000000)
+xxperm 0000100800001010 0000100000001002 0010100800101010 0010100000101002, pcv[12021a0817141317 100d1b05070f0205] => 1010100010000810 0000000010021000 (00000000)
+xxperm 0000100800001010 0000100000001002 0010100800101010 0010100000101002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 1000081000001000 1000000010100000 (00000000)
+xxperm 00001c0800001c10 00001c0000001c02 00101c0800101c10 00101c0000101c02, pcv[12021a0817141317 100d1b05070f0205] => 1c1c1c0010000810 0000000010021c00 (00000000)
+xxperm 00001c0800001c10 00001c0000001c02 00101c0800101c10 00101c0000101c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 1000081c00001c00 1c0000001c1c0000 (00000000)
+xxperm 00001f0800001f10 00001f0000001f02 00101f0800101f10 00101f0000101f02, pcv[12021a0817141317 100d1b05070f0205] => 1f1f1f0010000810 0000000010021f00 (00000000)
+xxperm 00001f0800001f10 00001f0000001f02 00101f0800101f10 00101f0000101f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 1000081f00001f00 1f0000001f1f0000 (00000000)
+
+xxpermr 0000000000000000 0000000000000000 0102010201020102 0102030405060708, pcv[12021a0817141317 100d1b05070f0205] => 0006000200000000 0001000301010603 (00000000)
+xxpermr 0000000000000000 0000000000000000 0102010201020102 0102030405060708, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0103050201070202 0202010702060201 (00000000)
+xxpermr 8899aabbccddeeff 0011223344556677 7060504030201000 f0e0d0c0b0a09080, pcv[12021a0817141317 100d1b05070f0205] => 55a0dd0000334400 7750ccd0f070a0d0 (00000000)
+xxpermr 8899aabbccddeeff 0011223344556677 7060504030201000 f0e0d0c0b0a09080, pcv[0705030a0b01ea0c 0e0c09010602080d] => f0d0b02030902040 60401090e0a00050 (00000000)
+xxpermr 0000100800001010 0000100000001002 0010100800101010 0010100000101002, pcv[12021a0817141317 100d1b05070f0205] => 0010001000000000 0210001000001010 (00000000)
+xxpermr 0000100800001010 0000100000001002 0010100800101010 0010100000101002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0010001000101008 1008101010101010 (00000000)
+xxpermr 00001c0800001c10 00001c0000001c02 00101c0800101c10 00101c0000101c02, pcv[12021a0817141317 100d1b05070f0205] => 0010001000000000 021c001c0000101c (00000000)
+xxpermr 00001c0800001c10 00001c0000001c02 00101c0800101c10 00101c0000101c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001c0010001c1008 10081c1c1010101c (00000000)
+xxpermr 00001f0800001f10 00001f0000001f02 00101f0800101f10 00101f0000101f02, pcv[12021a0817141317 100d1b05070f0205] => 0010001000000000 021f001f0000101f (00000000)
+xxpermr 00001f0800001f10 00001f0000001f02 00101f0800101f10 00101f0000101f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001f0010001f1008 10081f1f1010101f (00000000)
+
+All done. Tested 89 different instructions
+ppc vector three args + dest:
+Test instruction group [ppc vector three args + dest]
+vpermr 0000000000000000 0000000000000000 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => 0000000000000000 0000000000000000 (00000000)
+vpermr 0000000000000000 0000000000000000 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0000000000000000 0000000000000000 (00000000)
+vpermr 0000000000000000 0000000000000000 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => 005500ff00000000 00aa002200885522 (00000000)
+vpermr 0000000000000000 0000000000000000 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => 002244ddcc66ddbb 99bbee661155ffaa (00000000)
+vpermr 0000000000000000 0000000000000000 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => 0000001000000000 0010001000000010 (00000000)
+vpermr 0000000000000000 0000000000000000 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0010000000100008 0008101000001010 (00000000)
+vpermr 0000000000000000 0000000000000000 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => 0000001000000000 001c001c0000001c (00000000)
+vpermr 0000000000000000 0000000000000000 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001c0000001c0008 00081c1c0000101c (00000000)
+vpermr 0000000000000000 0000000000000000 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => 0000001000000000 001f001f0000001f (00000000)
+vpermr 0000000000000000 0000000000000000 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001f0000001f0008 00081f1f0000101f (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => 5500dd0000334400 7700cc0000000000 (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0000000000000000 0000000000000000 (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => 5555ddff00334400 77aacc2200885522 (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => 002244ddcc66ddbb 99bbee661155ffaa (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => 5500dd1000334400 7710cc1000000010 (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0010000000100008 0008101000001010 (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => 5500dd1000334400 771ccc1c0000001c (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001c0000001c0008 00081c1c0000101c (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => 5500dd1000334400 771fcc1f0000001f (00000000)
+vpermr 8899aabbccddeeff 0011223344556677 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001f0000001f0008 00081f1f0000101f (00000000)
+vpermr 0000100800001010 0000100000001002 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => 0000000000000000 0200000000000000 (00000000)
+vpermr 0000100800001010 0000100000001002 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0000000000000000 0000000000000000 (00000000)
+vpermr 0000100800001010 0000100000001002 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => 005500ff00000000 02aa002200885522 (00000000)
+vpermr 0000100800001010 0000100000001002 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => 002244ddcc66ddbb 99bbee661155ffaa (00000000)
+vpermr 0000100800001010 0000100000001002 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => 0000001000000000 0210001000000010 (00000000)
+vpermr 0000100800001010 0000100000001002 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0010000000100008 0008101000001010 (00000000)
+vpermr 0000100800001010 0000100000001002 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => 0000001000000000 021c001c0000001c (00000000)
+vpermr 0000100800001010 0000100000001002 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001c0000001c0008 00081c1c0000101c (00000000)
+vpermr 0000100800001010 0000100000001002 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => 0000001000000000 021f001f0000001f (00000000)
+vpermr 0000100800001010 0000100000001002 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001f0000001f0008 00081f1f0000101f (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => 0000000000000000 0200000000000000 (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0000000000000000 0000000000000000 (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => 005500ff00000000 02aa002200885522 (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => 002244ddcc66ddbb 99bbee661155ffaa (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => 0000001000000000 0210001000000010 (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0010000000100008 0008101000001010 (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => 0000001000000000 021c001c0000001c (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001c0000001c0008 00081c1c0000101c (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => 0000001000000000 021f001f0000001f (00000000)
+vpermr 00001c0800001c10 00001c0000001c02 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001f0000001f0008 00081f1f0000101f (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 0000000000000000 0000000000000000, pcv[12021a0817141317 100d1b05070f0205] => 0000000000000000 0200000000000000 (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 0000000000000000 0000000000000000, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0000000000000000 0000000000000000 (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 8899aabbccddeeff 0011223344556677, pcv[12021a0817141317 100d1b05070f0205] => 005500ff00000000 02aa002200885522 (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 8899aabbccddeeff 0011223344556677, pcv[0705030a0b01ea0c 0e0c09010602080d] => 002244ddcc66ddbb 99bbee661155ffaa (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 0000100800001010 0000100000001002, pcv[12021a0817141317 100d1b05070f0205] => 0000001000000000 0210001000000010 (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 0000100800001010 0000100000001002, pcv[0705030a0b01ea0c 0e0c09010602080d] => 0010000000100008 0008101000001010 (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 00001c0800001c10 00001c0000001c02, pcv[12021a0817141317 100d1b05070f0205] => 0000001000000000 021c001c0000001c (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 00001c0800001c10 00001c0000001c02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001c0000001c0008 00081c1c0000101c (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 00001f0800001f10 00001f0000001f02, pcv[12021a0817141317 100d1b05070f0205] => 0000001000000000 021f001f0000001f (00000000)
+vpermr 00001f0800001f10 00001f0000001f02 00001f0800001f10 00001f0000001f02, pcv[0705030a0b01ea0c 0e0c09010602080d] => 001f0000001f0008 00081f1f0000101f (00000000)
+
+All done. Tested 90 different instructions
+ppc vector inserts:
+Test instruction group [ppc vector inserts]
+vinsertb 0102010201020102 0102030405060708 [0] (into zeros) => 0200000000000000 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [0] (into ones) => 02ffffffffffffff ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [1] (into zeros) => 0002000000000000 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [1] (into ones) => ff02ffffffffffff ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [2] (into zeros) => 0000020000000000 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [2] (into ones) => ffff02ffffffffff ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [3] (into zeros) => 0000000200000000 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [3] (into ones) => ffffff02ffffffff ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [4] (into zeros) => 0000000002000000 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [4] (into ones) => ffffffff02ffffff ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [5] (into zeros) => 0000000000020000 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [5] (into ones) => ffffffffff02ffff ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [6] (into zeros) => 0000000000000200 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [6] (into ones) => ffffffffffff02ff ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [7] (into zeros) => 0000000000000002 0000000000000000
+vinsertb 0102010201020102 0102030405060708 [7] (into ones) => ffffffffffffff02 ffffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [8] (into zeros) => 0000000000000000 0200000000000000
+vinsertb 0102010201020102 0102030405060708 [8] (into ones) => ffffffffffffffff 02ffffffffffffff
+vinsertb 0102010201020102 0102030405060708 [9] (into zeros) => 0000000000000000 0002000000000000
+vinsertb 0102010201020102 0102030405060708 [9] (into ones) => ffffffffffffffff ff02ffffffffffff
+vinsertb 0102010201020102 0102030405060708 [10] (into zeros) => 0000000000000000 0000020000000000
+vinsertb 0102010201020102 0102030405060708 [10] (into ones) => ffffffffffffffff ffff02ffffffffff
+vinsertb 0102010201020102 0102030405060708 [11] (into zeros) => 0000000000000000 0000000200000000
+vinsertb 0102010201020102 0102030405060708 [11] (into ones) => ffffffffffffffff ffffff02ffffffff
+vinsertb 0102010201020102 0102030405060708 [12] (into zeros) => 0000000000000000 0000000002000000
+vinsertb 0102010201020102 0102030405060708 [12] (into ones) => ffffffffffffffff ffffffff02ffffff
+vinsertb 0102010201020102 0102030405060708 [13] (into zeros) => 0000000000000000 0000000000020000
+vinsertb 0102010201020102 0102030405060708 [13] (into ones) => ffffffffffffffff ffffffffff02ffff
+vinsertb 0102010201020102 0102030405060708 [14] (into zeros) => 0000000000000000 0000000000000200
+vinsertb 0102010201020102 0102030405060708 [14] (into ones) => ffffffffffffffff ffffffffffff02ff
+vinsertb 0102010201020102 0102030405060708 [15] (into zeros) => 0000000000000000 0000000000000002
+vinsertb 0102010201020102 0102030405060708 [15] (into ones) => ffffffffffffffff ffffffffffffff02
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [0] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [0] (into ones) => 00ffffffffffffff ffffffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [1] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [1] (into ones) => ff00ffffffffffff ffffffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [2] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [2] (into ones) => ffff00ffffffffff ffffffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [3] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [3] (into ones) => ffffff00ffffffff ffffffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [4] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [4] (into ones) => ffffffff00ffffff ffffffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [5] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [5] (into ones) => ffffffffff00ffff ffffffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [6] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [6] (into ones) => ffffffffffff00ff ffffffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [7] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [7] (into ones) => ffffffffffffff00 ffffffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [8] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [8] (into ones) => ffffffffffffffff 00ffffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [9] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [9] (into ones) => ffffffffffffffff ff00ffffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [10] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [10] (into ones) => ffffffffffffffff ffff00ffffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [11] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [11] (into ones) => ffffffffffffffff ffffff00ffffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [12] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [12] (into ones) => ffffffffffffffff ffffffff00ffffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [13] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [13] (into ones) => ffffffffffffffff ffffffffff00ffff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [14] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [14] (into ones) => ffffffffffffffff ffffffffffff00ff
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [15] (into zeros) => 0000000000000000 0000000000000000
+vinsertb 7060504030201000 f0e0d0c0b0a09080 [15] (into ones) => ffffffffffffffff ffffffffffffff00
+
+vinserth 0102010201020102 0102030405060708 [0] (into zeros) => 0102000000000000 0000000000000000
+vinserth 0102010201020102 0102030405060708 [0] (into ones) => 0102ffffffffffff ffffffffffffffff
+vinserth 0102010201020102 0102030405060708 [1] (into zeros) => 0001020000000000 0000000000000000
+vinserth 0102010201020102 0102030405060708 [1] (into ones) => ff0102ffffffffff ffffffffffffffff
+vinserth 0102010201020102 0102030405060708 [2] (into zeros) => 0000010200000000 0000000000000000
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+vextractuh 0102010201020102 0102030405060708 [0] (into zeros) => 0000000000000102 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [0] (into ones) => 0000000000000102 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [1] (into zeros) => 0000000000000201 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [1] (into ones) => 0000000000000201 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [2] (into zeros) => 0000000000000102 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [2] (into ones) => 0000000000000102 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [3] (into zeros) => 0000000000000201 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [3] (into ones) => 0000000000000201 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [4] (into zeros) => 0000000000000102 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [4] (into ones) => 0000000000000102 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [5] (into zeros) => 0000000000000201 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [5] (into ones) => 0000000000000201 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [6] (into zeros) => 0000000000000102 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [6] (into ones) => 0000000000000102 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [7] (into zeros) => 0000000000000201 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [7] (into ones) => 0000000000000201 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [8] (into zeros) => 0000000000000102 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [8] (into ones) => 0000000000000102 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [9] (into zeros) => 0000000000000203 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [9] (into ones) => 0000000000000203 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [10] (into zeros) => 0000000000000304 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [10] (into ones) => 0000000000000304 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [11] (into zeros) => 0000000000000405 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [11] (into ones) => 0000000000000405 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [12] (into zeros) => 0000000000000506 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [12] (into ones) => 0000000000000506 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [13] (into zeros) => 0000000000000607 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [13] (into ones) => 0000000000000607 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [14] (into zeros) => 0000000000000708 0000000000000000
+vextractuh 0102010201020102 0102030405060708 [14] (into ones) => 0000000000000708 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [0] (into zeros) => 0000000000007060 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [0] (into ones) => 0000000000007060 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [1] (into zeros) => 0000000000006050 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [1] (into ones) => 0000000000006050 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [2] (into zeros) => 0000000000005040 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [2] (into ones) => 0000000000005040 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [3] (into zeros) => 0000000000004030 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [3] (into ones) => 0000000000004030 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [4] (into zeros) => 0000000000003020 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [4] (into ones) => 0000000000003020 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [5] (into zeros) => 0000000000002010 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [5] (into ones) => 0000000000002010 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [6] (into zeros) => 0000000000001000 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [6] (into ones) => 0000000000001000 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [7] (into zeros) => 00000000000000f0 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [7] (into ones) => 00000000000000f0 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [8] (into zeros) => 000000000000f0e0 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [8] (into ones) => 000000000000f0e0 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [9] (into zeros) => 000000000000e0d0 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [9] (into ones) => 000000000000e0d0 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [10] (into zeros) => 000000000000d0c0 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [10] (into ones) => 000000000000d0c0 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [11] (into zeros) => 000000000000c0b0 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [11] (into ones) => 000000000000c0b0 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [12] (into zeros) => 000000000000b0a0 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [12] (into ones) => 000000000000b0a0 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [13] (into zeros) => 000000000000a090 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [13] (into ones) => 000000000000a090 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [14] (into zeros) => 0000000000009080 0000000000000000
+vextractuh 7060504030201000 f0e0d0c0b0a09080 [14] (into ones) => 0000000000009080 0000000000000000
+
+vextractuw 0102010201020102 0102030405060708 [0] (into zeros) => 0000000001020102 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [0] (into ones) => 0000000001020102 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [1] (into zeros) => 0000000002010201 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [1] (into ones) => 0000000002010201 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [2] (into zeros) => 0000000001020102 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [2] (into ones) => 0000000001020102 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [3] (into zeros) => 0000000002010201 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [3] (into ones) => 0000000002010201 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [4] (into zeros) => 0000000001020102 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [4] (into ones) => 0000000001020102 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [5] (into zeros) => 0000000002010201 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [5] (into ones) => 0000000002010201 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [6] (into zeros) => 0000000001020102 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [6] (into ones) => 0000000001020102 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [7] (into zeros) => 0000000002010203 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [7] (into ones) => 0000000002010203 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [8] (into zeros) => 0000000001020304 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [8] (into ones) => 0000000001020304 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [9] (into zeros) => 0000000002030405 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [9] (into ones) => 0000000002030405 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [10] (into zeros) => 0000000003040506 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [10] (into ones) => 0000000003040506 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [11] (into zeros) => 0000000004050607 0000000000000000
+vextractuw 0102010201020102 0102030405060708 [11] (into ones) => 0000000004050607 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [0] (into zeros) => 0000000070605040 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [0] (into ones) => 0000000070605040 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [1] (into zeros) => 0000000060504030 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [1] (into ones) => 0000000060504030 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [2] (into zeros) => 0000000050403020 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [2] (into ones) => 0000000050403020 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [3] (into zeros) => 0000000040302010 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [3] (into ones) => 0000000040302010 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [4] (into zeros) => 0000000030201000 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [4] (into ones) => 0000000030201000 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [5] (into zeros) => 00000000201000f0 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [5] (into ones) => 00000000201000f0 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [6] (into zeros) => 000000001000f0e0 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [6] (into ones) => 000000001000f0e0 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [7] (into zeros) => 0000000000f0e0d0 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [7] (into ones) => 0000000000f0e0d0 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [8] (into zeros) => 00000000f0e0d0c0 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [8] (into ones) => 00000000f0e0d0c0 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [9] (into zeros) => 00000000e0d0c0b0 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [9] (into ones) => 00000000e0d0c0b0 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [10] (into zeros) => 00000000d0c0b0a0 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [10] (into ones) => 00000000d0c0b0a0 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [11] (into zeros) => 00000000c0b0a090 0000000000000000
+vextractuw 7060504030201000 f0e0d0c0b0a09080 [11] (into ones) => 00000000c0b0a090 0000000000000000
+
+vextractd 0102010201020102 0102030405060708 [0] (into zeros) => 0102010201020102 0000000000000000
+vextractd 0102010201020102 0102030405060708 [0] (into ones) => 0102010201020102 0000000000000000
+vextractd 0102010201020102 0102030405060708 [1] (into zeros) => 0201020102010201 0000000000000000
+vextractd 0102010201020102 0102030405060708 [1] (into ones) => 0201020102010201 0000000000000000
+vextractd 0102010201020102 0102030405060708 [2] (into zeros) => 0102010201020102 0000000000000000
+vextractd 0102010201020102 0102030405060708 [2] (into ones) => 0102010201020102 0000000000000000
+vextractd 0102010201020102 0102030405060708 [3] (into zeros) => 0201020102010203 0000000000000000
+vextractd 0102010201020102 0102030405060708 [3] (into ones) => 0201020102010203 0000000000000000
+vextractd 0102010201020102 0102030405060708 [4] (into zeros) => 0102010201020304 0000000000000000
+vextractd 0102010201020102 0102030405060708 [4] (into ones) => 0102010201020304 0000000000000000
+vextractd 0102010201020102 0102030405060708 [5] (into zeros) => 0201020102030405 0000000000000000
+vextractd 0102010201020102 0102030405060708 [5] (into ones) => 0201020102030405 0000000000000000
+vextractd 0102010201020102 0102030405060708 [6] (into zeros) => 0102010203040506 0000000000000000
+vextractd 0102010201020102 0102030405060708 [6] (into ones) => 0102010203040506 0000000000000000
+vextractd 0102010201020102 0102030405060708 [7] (into zeros) => 0201020304050607 0000000000000000
+vextractd 0102010201020102 0102030405060708 [7] (into ones) => 0201020304050607 0000000000000000
+vextractd 0102010201020102 0102030405060708 [8] (into zeros) => 0102030405060708 0000000000000000
+vextractd 0102010201020102 0102030405060708 [8] (into ones) => 0102030405060708 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [0] (into zeros) => 7060504030201000 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [0] (into ones) => 7060504030201000 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [1] (into zeros) => 60504030201000f0 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [1] (into ones) => 60504030201000f0 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [2] (into zeros) => 504030201000f0e0 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [2] (into ones) => 504030201000f0e0 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [3] (into zeros) => 4030201000f0e0d0 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [3] (into ones) => 4030201000f0e0d0 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [4] (into zeros) => 30201000f0e0d0c0 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [4] (into ones) => 30201000f0e0d0c0 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [5] (into zeros) => 201000f0e0d0c0b0 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [5] (into ones) => 201000f0e0d0c0b0 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [6] (into zeros) => 1000f0e0d0c0b0a0 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [6] (into ones) => 1000f0e0d0c0b0a0 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [7] (into zeros) => 00f0e0d0c0b0a090 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [7] (into ones) => 00f0e0d0c0b0a090 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [8] (into zeros) => f0e0d0c0b0a09080 0000000000000000
+vextractd 7060504030201000 f0e0d0c0b0a09080 [8] (into ones) => f0e0d0c0b0a09080 0000000000000000
+
+xxinsertw 0102010201020102 0102030405060708 [0] (into zeros) => 0102010200000000 0000000000000000
+xxinsertw 0102010201020102 0102030405060708 [0] (into ones) => 01020102ffffffff ffffffffffffffff
+xxinsertw 0102010201020102 0102030405060708 [1] (into zeros) => 0001020102000000 0000000000000000
+xxinsertw 0102010201020102 0102030405060708 [1] (into ones) => ff01020102ffffff ffffffffffffffff
+xxinsertw 0102010201020102 0102030405060708 [2] (into zeros) => 0000010201020000 0000000000000000
+xxinsertw 0102010201020102 0102030405060708 [2] (into ones) => ffff01020102ffff ffffffffffffffff
+xxinsertw 0102010201020102 0102030405060708 [3] (into zeros) => 0000000102010200 0000000000000000
+xxinsertw 0102010201020102 0102030405060708 [3] (into ones) => ffffff01020102ff ffffffffffffffff
+xxinsertw 0102010201020102 0102030405060708 [4] (into zeros) => 0000000001020102 0000000000000000
+xxinsertw 0102010201020102 0102030405060708 [4] (into ones) => ffffffff01020102 ffffffffffffffff
+xxinsertw 0102010201020102 0102030405060708 [5] (into zeros) => 0000000000010201 0200000000000000
+xxinsertw 0102010201020102 0102030405060708 [5] (into ones) => ffffffffff010201 02ffffffffffffff
+xxinsertw 0102010201020102 0102030405060708 [6] (into zeros) => 0000000000000102 0102000000000000
+xxinsertw 0102010201020102 0102030405060708 [6] (into ones) => ffffffffffff0102 0102ffffffffffff
+xxinsertw 0102010201020102 0102030405060708 [7] (into zeros) => 0000000000000001 0201020000000000
+xxinsertw 0102010201020102 0102030405060708 [7] (into ones) => ffffffffffffff01 020102ffffffffff
+xxinsertw 0102010201020102 0102030405060708 [8] (into zeros) => 0000000000000000 0102010200000000
+xxinsertw 0102010201020102 0102030405060708 [8] (into ones) => ffffffffffffffff 01020102ffffffff
+xxinsertw 0102010201020102 0102030405060708 [9] (into zeros) => 0000000000000000 0001020102000000
+xxinsertw 0102010201020102 0102030405060708 [9] (into ones) => ffffffffffffffff ff01020102ffffff
+xxinsertw 0102010201020102 0102030405060708 [10] (into zeros) => 0000000000000000 0000010201020000
+xxinsertw 0102010201020102 0102030405060708 [10] (into ones) => ffffffffffffffff ffff01020102ffff
+xxinsertw 0102010201020102 0102030405060708 [11] (into zeros) => 0000000000000000 0000000102010200
+xxinsertw 0102010201020102 0102030405060708 [11] (into ones) => ffffffffffffffff ffffff01020102ff
+xxinsertw 0102010201020102 0102030405060708 [12] (into zeros) => 0000000000000000 0000000001020102
+xxinsertw 0102010201020102 0102030405060708 [12] (into ones) => ffffffffffffffff ffffffff01020102
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [0] (into zeros) => 3020100000000000 0000000000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [0] (into ones) => 30201000ffffffff ffffffffffffffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [1] (into zeros) => 0030201000000000 0000000000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [1] (into ones) => ff30201000ffffff ffffffffffffffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [2] (into zeros) => 0000302010000000 0000000000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [2] (into ones) => ffff30201000ffff ffffffffffffffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [3] (into zeros) => 0000003020100000 0000000000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [3] (into ones) => ffffff30201000ff ffffffffffffffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [4] (into zeros) => 0000000030201000 0000000000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [4] (into ones) => ffffffff30201000 ffffffffffffffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [5] (into zeros) => 0000000000302010 0000000000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [5] (into ones) => ffffffffff302010 00ffffffffffffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [6] (into zeros) => 0000000000003020 1000000000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [6] (into ones) => ffffffffffff3020 1000ffffffffffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [7] (into zeros) => 0000000000000030 2010000000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [7] (into ones) => ffffffffffffff30 201000ffffffffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [8] (into zeros) => 0000000000000000 3020100000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [8] (into ones) => ffffffffffffffff 30201000ffffffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [9] (into zeros) => 0000000000000000 0030201000000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [9] (into ones) => ffffffffffffffff ff30201000ffffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [10] (into zeros) => 0000000000000000 0000302010000000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [10] (into ones) => ffffffffffffffff ffff30201000ffff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [11] (into zeros) => 0000000000000000 0000003020100000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [11] (into ones) => ffffffffffffffff ffffff30201000ff
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [12] (into zeros) => 0000000000000000 0000000030201000
+xxinsertw 7060504030201000 f0e0d0c0b0a09080 [12] (into ones) => ffffffffffffffff ffffffff30201000
+
+xxextractuw 0102010201020102 0102030405060708 [0] (into zeros) => 0000000001020102 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [0] (into ones) => 0000000001020102 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [1] (into zeros) => 0000000002010201 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [1] (into ones) => 0000000002010201 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [2] (into zeros) => 0000000001020102 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [2] (into ones) => 0000000001020102 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [3] (into zeros) => 0000000002010201 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [3] (into ones) => 0000000002010201 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [4] (into zeros) => 0000000001020102 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [4] (into ones) => 0000000001020102 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [5] (into zeros) => 0000000002010201 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [5] (into ones) => 0000000002010201 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [6] (into zeros) => 0000000001020102 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [6] (into ones) => 0000000001020102 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [7] (into zeros) => 0000000002010203 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [7] (into ones) => 0000000002010203 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [8] (into zeros) => 0000000001020304 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [8] (into ones) => 0000000001020304 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [9] (into zeros) => 0000000002030405 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [9] (into ones) => 0000000002030405 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [10] (into zeros) => 0000000003040506 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [10] (into ones) => 0000000003040506 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [11] (into zeros) => 0000000004050607 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [11] (into ones) => 0000000004050607 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [12] (into zeros) => 0000000005060708 0000000000000000
+xxextractuw 0102010201020102 0102030405060708 [12] (into ones) => 0000000005060708 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [0] (into zeros) => 0000000070605040 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [0] (into ones) => 0000000070605040 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [1] (into zeros) => 0000000060504030 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [1] (into ones) => 0000000060504030 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [2] (into zeros) => 0000000050403020 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [2] (into ones) => 0000000050403020 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [3] (into zeros) => 0000000040302010 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [3] (into ones) => 0000000040302010 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [4] (into zeros) => 0000000030201000 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [4] (into ones) => 0000000030201000 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [5] (into zeros) => 00000000201000f0 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [5] (into ones) => 00000000201000f0 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [6] (into zeros) => 000000001000f0e0 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [6] (into ones) => 000000001000f0e0 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [7] (into zeros) => 0000000000f0e0d0 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [7] (into ones) => 0000000000f0e0d0 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [8] (into zeros) => 00000000f0e0d0c0 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [8] (into ones) => 00000000f0e0d0c0 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [9] (into zeros) => 00000000e0d0c0b0 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [9] (into ones) => 00000000e0d0c0b0 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [10] (into zeros) => 00000000d0c0b0a0 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [10] (into ones) => 00000000d0c0b0a0 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [11] (into zeros) => 00000000c0b0a090 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [11] (into ones) => 00000000c0b0a090 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [12] (into zeros) => 00000000b0a09080 0000000000000000
+xxextractuw 7060504030201000 f0e0d0c0b0a09080 [12] (into ones) => 00000000b0a09080 0000000000000000
+
+All done. Tested 100 different instructions
+ppc vector extract from vector to reg:
+Test instruction group [ppc vector extract from vector to reg]
+vextublx 0000000000000000 0000000000000000 0 => 0
+vextublx 0000000000000000 0000000000000000 1 => 0
+vextublx 0000000000000000 0000000000000000 2 => 0
+vextublx 0000000000000000 0000000000000000 3 => 0
+vextublx 0000000000000000 0000000000000000 4 => 0
+vextublx 0000000000000000 0000000000000000 5 => 0
+vextublx 0000000000000000 0000000000000000 6 => 0
+vextublx 0000000000000000 0000000000000000 7 => 0
+vextublx 0000000000000000 0000000000000000 8 => 0
+vextublx 0000000000000000 0000000000000000 9 => 0
+vextublx 0000000000000000 0000000000000000 10 => 0
+vextublx 0000000000000000 0000000000000000 11 => 0
+vextublx 0000000000000000 0000000000000000 12 => 0
+vextublx 0000000000000000 0000000000000000 13 => 0
+vextublx 0000000000000000 0000000000000000 14 => 0
+vextublx 0000000000000000 0000000000000000 15 => 0
+vextublx 0102010201020102 0102030405060708 0 => 1
+vextublx 0102010201020102 0102030405060708 1 => 2
+vextublx 0102010201020102 0102030405060708 2 => 1
+vextublx 0102010201020102 0102030405060708 3 => 2
+vextublx 0102010201020102 0102030405060708 4 => 1
+vextublx 0102010201020102 0102030405060708 5 => 2
+vextublx 0102010201020102 0102030405060708 6 => 1
+vextublx 0102010201020102 0102030405060708 7 => 2
+vextublx 0102010201020102 0102030405060708 8 => 1
+vextublx 0102010201020102 0102030405060708 9 => 2
+vextublx 0102010201020102 0102030405060708 10 => 3
+vextublx 0102010201020102 0102030405060708 11 => 4
+vextublx 0102010201020102 0102030405060708 12 => 5
+vextublx 0102010201020102 0102030405060708 13 => 6
+vextublx 0102010201020102 0102030405060708 14 => 7
+vextublx 0102010201020102 0102030405060708 15 => 8
+vextublx 8899aabbccddeeff 0011223344556677 0 => 88
+vextublx 8899aabbccddeeff 0011223344556677 1 => 99
+vextublx 8899aabbccddeeff 0011223344556677 2 => aa
+vextublx 8899aabbccddeeff 0011223344556677 3 => bb
+vextublx 8899aabbccddeeff 0011223344556677 4 => cc
+vextublx 8899aabbccddeeff 0011223344556677 5 => dd
+vextublx 8899aabbccddeeff 0011223344556677 6 => ee
+vextublx 8899aabbccddeeff 0011223344556677 7 => ff
+vextublx 8899aabbccddeeff 0011223344556677 8 => 0
+vextublx 8899aabbccddeeff 0011223344556677 9 => 11
+vextublx 8899aabbccddeeff 0011223344556677 10 => 22
+vextublx 8899aabbccddeeff 0011223344556677 11 => 33
+vextublx 8899aabbccddeeff 0011223344556677 12 => 44
+vextublx 8899aabbccddeeff 0011223344556677 13 => 55
+vextublx 8899aabbccddeeff 0011223344556677 14 => 66
+vextublx 8899aabbccddeeff 0011223344556677 15 => 77
+vextublx 7060504030201000 f0e0d0c0b0a09080 0 => 70
+vextublx 7060504030201000 f0e0d0c0b0a09080 1 => 60
+vextublx 7060504030201000 f0e0d0c0b0a09080 2 => 50
+vextublx 7060504030201000 f0e0d0c0b0a09080 3 => 40
+vextublx 7060504030201000 f0e0d0c0b0a09080 4 => 30
+vextublx 7060504030201000 f0e0d0c0b0a09080 5 => 20
+vextublx 7060504030201000 f0e0d0c0b0a09080 6 => 10
+vextublx 7060504030201000 f0e0d0c0b0a09080 7 => 0
+vextublx 7060504030201000 f0e0d0c0b0a09080 8 => f0
+vextublx 7060504030201000 f0e0d0c0b0a09080 9 => e0
+vextublx 7060504030201000 f0e0d0c0b0a09080 10 => d0
+vextublx 7060504030201000 f0e0d0c0b0a09080 11 => c0
+vextublx 7060504030201000 f0e0d0c0b0a09080 12 => b0
+vextublx 7060504030201000 f0e0d0c0b0a09080 13 => a0
+vextublx 7060504030201000 f0e0d0c0b0a09080 14 => 90
+vextublx 7060504030201000 f0e0d0c0b0a09080 15 => 80
+vextublx 0000100800001010 0000100000001002 0 => 0
+vextublx 0000100800001010 0000100000001002 1 => 0
+vextublx 0000100800001010 0000100000001002 2 => 10
+vextublx 0000100800001010 0000100000001002 3 => 8
+vextublx 0000100800001010 0000100000001002 4 => 0
+vextublx 0000100800001010 0000100000001002 5 => 0
+vextublx 0000100800001010 0000100000001002 6 => 10
+vextublx 0000100800001010 0000100000001002 7 => 10
+vextublx 0000100800001010 0000100000001002 8 => 0
+vextublx 0000100800001010 0000100000001002 9 => 0
+vextublx 0000100800001010 0000100000001002 10 => 10
+vextublx 0000100800001010 0000100000001002 11 => 0
+vextublx 0000100800001010 0000100000001002 12 => 0
+vextublx 0000100800001010 0000100000001002 13 => 0
+vextublx 0000100800001010 0000100000001002 14 => 10
+vextublx 0000100800001010 0000100000001002 15 => 2
+vextublx 0010100800101010 0010100000101002 0 => 0
+vextublx 0010100800101010 0010100000101002 1 => 10
+vextublx 0010100800101010 0010100000101002 2 => 10
+vextublx 0010100800101010 0010100000101002 3 => 8
+vextublx 0010100800101010 0010100000101002 4 => 0
+vextublx 0010100800101010 0010100000101002 5 => 10
+vextublx 0010100800101010 0010100000101002 6 => 10
+vextublx 0010100800101010 0010100000101002 7 => 10
+vextublx 0010100800101010 0010100000101002 8 => 0
+vextublx 0010100800101010 0010100000101002 9 => 10
+vextublx 0010100800101010 0010100000101002 10 => 10
+vextublx 0010100800101010 0010100000101002 11 => 0
+vextublx 0010100800101010 0010100000101002 12 => 0
+vextublx 0010100800101010 0010100000101002 13 => 10
+vextublx 0010100800101010 0010100000101002 14 => 10
+vextublx 0010100800101010 0010100000101002 15 => 2
+vextublx 00001c0800001c10 00001c0000001c02 0 => 0
+vextublx 00001c0800001c10 00001c0000001c02 1 => 0
+vextublx 00001c0800001c10 00001c0000001c02 2 => 1c
+vextublx 00001c0800001c10 00001c0000001c02 3 => 8
+vextublx 00001c0800001c10 00001c0000001c02 4 => 0
+vextublx 00001c0800001c10 00001c0000001c02 5 => 0
+vextublx 00001c0800001c10 00001c0000001c02 6 => 1c
+vextublx 00001c0800001c10 00001c0000001c02 7 => 10
+vextublx 00001c0800001c10 00001c0000001c02 8 => 0
+vextublx 00001c0800001c10 00001c0000001c02 9 => 0
+vextublx 00001c0800001c10 00001c0000001c02 10 => 1c
+vextublx 00001c0800001c10 00001c0000001c02 11 => 0
+vextublx 00001c0800001c10 00001c0000001c02 12 => 0
+vextublx 00001c0800001c10 00001c0000001c02 13 => 0
+vextublx 00001c0800001c10 00001c0000001c02 14 => 1c
+vextublx 00001c0800001c10 00001c0000001c02 15 => 2
+vextublx 00101c0800101c10 00101c0000101c02 0 => 0
+vextublx 00101c0800101c10 00101c0000101c02 1 => 10
+vextublx 00101c0800101c10 00101c0000101c02 2 => 1c
+vextublx 00101c0800101c10 00101c0000101c02 3 => 8
+vextublx 00101c0800101c10 00101c0000101c02 4 => 0
+vextublx 00101c0800101c10 00101c0000101c02 5 => 10
+vextublx 00101c0800101c10 00101c0000101c02 6 => 1c
+vextublx 00101c0800101c10 00101c0000101c02 7 => 10
+vextublx 00101c0800101c10 00101c0000101c02 8 => 0
+vextublx 00101c0800101c10 00101c0000101c02 9 => 10
+vextublx 00101c0800101c10 00101c0000101c02 10 => 1c
+vextublx 00101c0800101c10 00101c0000101c02 11 => 0
+vextublx 00101c0800101c10 00101c0000101c02 12 => 0
+vextublx 00101c0800101c10 00101c0000101c02 13 => 10
+vextublx 00101c0800101c10 00101c0000101c02 14 => 1c
+vextublx 00101c0800101c10 00101c0000101c02 15 => 2
+vextublx 00001f0800001f10 00001f0000001f02 0 => 0
+vextublx 00001f0800001f10 00001f0000001f02 1 => 0
+vextublx 00001f0800001f10 00001f0000001f02 2 => 1f
+vextublx 00001f0800001f10 00001f0000001f02 3 => 8
+vextublx 00001f0800001f10 00001f0000001f02 4 => 0
+vextublx 00001f0800001f10 00001f0000001f02 5 => 0
+vextublx 00001f0800001f10 00001f0000001f02 6 => 1f
+vextublx 00001f0800001f10 00001f0000001f02 7 => 10
+vextublx 00001f0800001f10 00001f0000001f02 8 => 0
+vextublx 00001f0800001f10 00001f0000001f02 9 => 0
+vextublx 00001f0800001f10 00001f0000001f02 10 => 1f
+vextublx 00001f0800001f10 00001f0000001f02 11 => 0
+vextublx 00001f0800001f10 00001f0000001f02 12 => 0
+vextublx 00001f0800001f10 00001f0000001f02 13 => 0
+vextublx 00001f0800001f10 00001f0000001f02 14 => 1f
+vextublx 00001f0800001f10 00001f0000001f02 15 => 2
+vextublx 00101f0800101f10 00101f0000101f02 0 => 0
+vextublx 00101f0800101f10 00101f0000101f02 1 => 10
+vextublx 00101f0800101f10 00101f0000101f02 2 => 1f
+vextublx 00101f0800101f10 00101f0000101f02 3 => 8
+vextublx 00101f0800101f10 00101f0000101f02 4 => 0
+vextublx 00101f0800101f10 00101f0000101f02 5 => 10
+vextublx 00101f0800101f10 00101f0000101f02 6 => 1f
+vextublx 00101f0800101f10 00101f0000101f02 7 => 10
+vextublx 00101f0800101f10 00101f0000101f02 8 => 0
+vextublx 00101f0800101f10 00101f0000101f02 9 => 10
+vextublx 00101f0800101f10 00101f0000101f02 10 => 1f
+vextublx 00101f0800101f10 00101f0000101f02 11 => 0
+vextublx 00101f0800101f10 00101f0000101f02 12 => 0
+vextublx 00101f0800101f10 00101f0000101f02 13 => 10
+vextublx 00101f0800101f10 00101f0000101f02 14 => 1f
+vextublx 00101f0800101f10 00101f0000101f02 15 => 2
+
+vextubrx 0000000000000000 0000000000000000 0 => 0
+vextubrx 0000000000000000 0000000000000000 1 => 0
+vextubrx 0000000000000000 0000000000000000 2 => 0
+vextubrx 0000000000000000 0000000000000000 3 => 0
+vextubrx 0000000000000000 0000000000000000 4 => 0
+vextubrx 0000000000000000 0000000000000000 5 => 0
+vextubrx 0000000000000000 0000000000000000 6 => 0
+vextubrx 0000000000000000 0000000000000000 7 => 0
+vextubrx 0000000000000000 0000000000000000 8 => 0
+vextubrx 0000000000000000 0000000000000000 9 => 0
+vextubrx 0000000000000000 0000000000000000 10 => 0
+vextubrx 0000000000000000 0000000000000000 11 => 0
+vextubrx 0000000000000000 0000000000000000 12 => 0
+vextubrx 0000000000000000 0000000000000000 13 => 0
+vextubrx 0000000000000000 0000000000000000 14 => 0
+vextubrx 0000000000000000 0000000000000000 15 => 0
+vextubrx 0102010201020102 0102030405060708 0 => 8
+vextubrx 0102010201020102 0102030405060708 1 => 7
+vextubrx 0102010201020102 0102030405060708 2 => 6
+vextubrx 0102010201020102 0102030405060708 3 => 5
+vextubrx 0102010201020102 0102030405060708 4 => 4
+vextubrx 0102010201020102 0102030405060708 5 => 3
+vextubrx 0102010201020102 0102030405060708 6 => 2
+vextubrx 0102010201020102 0102030405060708 7 => 1
+vextubrx 0102010201020102 0102030405060708 8 => 2
+vextubrx 0102010201020102 0102030405060708 9 => 1
+vextubrx 0102010201020102 0102030405060708 10 => 2
+vextubrx 0102010201020102 0102030405060708 11 => 1
+vextubrx 0102010201020102 0102030405060708 12 => 2
+vextubrx 0102010201020102 0102030405060708 13 => 1
+vextubrx 0102010201020102 0102030405060708 14 => 2
+vextubrx 0102010201020102 0102030405060708 15 => 1
+vextubrx 8899aabbccddeeff 0011223344556677 0 => 77
+vextubrx 8899aabbccddeeff 0011223344556677 1 => 66
+vextubrx 8899aabbccddeeff 0011223344556677 2 => 55
+vextubrx 8899aabbccddeeff 0011223344556677 3 => 44
+vextubrx 8899aabbccddeeff 0011223344556677 4 => 33
+vextubrx 8899aabbccddeeff 0011223344556677 5 => 22
+vextubrx 8899aabbccddeeff 0011223344556677 6 => 11
+vextubrx 8899aabbccddeeff 0011223344556677 7 => 0
+vextubrx 8899aabbccddeeff 0011223344556677 8 => ff
+vextubrx 8899aabbccddeeff 0011223344556677 9 => ee
+vextubrx 8899aabbccddeeff 0011223344556677 10 => dd
+vextubrx 8899aabbccddeeff 0011223344556677 11 => cc
+vextubrx 8899aabbccddeeff 0011223344556677 12 => bb
+vextubrx 8899aabbccddeeff 0011223344556677 13 => aa
+vextubrx 8899aabbccddeeff 0011223344556677 14 => 99
+vextubrx 8899aabbccddeeff 0011223344556677 15 => 88
+vextubrx 7060504030201000 f0e0d0c0b0a09080 0 => 80
+vextubrx 7060504030201000 f0e0d0c0b0a09080 1 => 90
+vextubrx 7060504030201000 f0e0d0c0b0a09080 2 => a0
+vextubrx 7060504030201000 f0e0d0c0b0a09080 3 => b0
+vextubrx 7060504030201000 f0e0d0c0b0a09080 4 => c0
+vextubrx 7060504030201000 f0e0d0c0b0a09080 5 => d0
+vextubrx 7060504030201000 f0e0d0c0b0a09080 6 => e0
+vextubrx 7060504030201000 f0e0d0c0b0a09080 7 => f0
+vextubrx 7060504030201000 f0e0d0c0b0a09080 8 => 0
+vextubrx 7060504030201000 f0e0d0c0b0a09080 9 => 10
+vextubrx 7060504030201000 f0e0d0c0b0a09080 10 => 20
+vextubrx 7060504030201000 f0e0d0c0b0a09080 11 => 30
+vextubrx 7060504030201000 f0e0d0c0b0a09080 12 => 40
+vextubrx 7060504030201000 f0e0d0c0b0a09080 13 => 50
+vextubrx 7060504030201000 f0e0d0c0b0a09080 14 => 60
+vextubrx 7060504030201000 f0e0d0c0b0a09080 15 => 70
+vextubrx 0000100800001010 0000100000001002 0 => 2
+vextubrx 0000100800001010 0000100000001002 1 => 10
+vextubrx 0000100800001010 0000100000001002 2 => 0
+vextubrx 0000100800001010 0000100000001002 3 => 0
+vextubrx 0000100800001010 0000100000001002 4 => 0
+vextubrx 0000100800001010 0000100000001002 5 => 10
+vextubrx 0000100800001010 0000100000001002 6 => 0
+vextubrx 0000100800001010 0000100000001002 7 => 0
+vextubrx 0000100800001010 0000100000001002 8 => 10
+vextubrx 0000100800001010 0000100000001002 9 => 10
+vextubrx 0000100800001010 0000100000001002 10 => 0
+vextubrx 0000100800001010 0000100000001002 11 => 0
+vextubrx 0000100800001010 0000100000001002 12 => 8
+vextubrx 0000100800001010 0000100000001002 13 => 10
+vextubrx 0000100800001010 0000100000001002 14 => 0
+vextubrx 0000100800001010 0000100000001002 15 => 0
+vextubrx 0010100800101010 0010100000101002 0 => 2
+vextubrx 0010100800101010 0010100000101002 1 => 10
+vextubrx 0010100800101010 0010100000101002 2 => 10
+vextubrx 0010100800101010 0010100000101002 3 => 0
+vextubrx 0010100800101010 0010100000101002 4 => 0
+vextubrx 0010100800101010 0010100000101002 5 => 10
+vextubrx 0010100800101010 0010100000101002 6 => 10
+vextubrx 0010100800101010 0010100000101002 7 => 0
+vextubrx 0010100800101010 0010100000101002 8 => 10
+vextubrx 0010100800101010 0010100000101002 9 => 10
+vextubrx 0010100800101010 0010100000101002 10 => 10
+vextubrx 0010100800101010 0010100000101002 11 => 0
+vextubrx 0010100800101010 0010100000101002 12 => 8
+vextubrx 0010100800101010 0010100000101002 13 => 10
+vextubrx 0010100800101010 0010100000101002 14 => 10
+vextubrx 0010100800101010 0010100000101002 15 => 0
+vextubrx 00001c0800001c10 00001c0000001c02 0 => 2
+vextubrx 00001c0800001c10 00001c0000001c02 1 => 1c
+vextubrx 00001c0800001c10 00001c0000001c02 2 => 0
+vextubrx 00001c0800001c10 00001c0000001c02 3 => 0
+vextubrx 00001c0800001c10 00001c0000001c02 4 => 0
+vextubrx 00001c0800001c10 00001c0000001c02 5 => 1c
+vextubrx 00001c0800001c10 00001c0000001c02 6 => 0
+vextubrx 00001c0800001c10 00001c0000001c02 7 => 0
+vextubrx 00001c0800001c10 00001c0000001c02 8 => 10
+vextubrx 00001c0800001c10 00001c0000001c02 9 => 1c
+vextubrx 00001c0800001c10 00001c0000001c02 10 => 0
+vextubrx 00001c0800001c10 00001c0000001c02 11 => 0
+vextubrx 00001c0800001c10 00001c0000001c02 12 => 8
+vextubrx 00001c0800001c10 00001c0000001c02 13 => 1c
+vextubrx 00001c0800001c10 00001c0000001c02 14 => 0
+vextubrx 00001c0800001c10 00001c0000001c02 15 => 0
+vextubrx 00101c0800101c10 00101c0000101c02 0 => 2
+vextubrx 00101c0800101c10 00101c0000101c02 1 => 1c
+vextubrx 00101c0800101c10 00101c0000101c02 2 => 10
+vextubrx 00101c0800101c10 00101c0000101c02 3 => 0
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+vextuwrx 00001c0800001c10 00001c0000001c02 15 => 0
+vextuwrx 00101c0800101c10 00101c0000101c02 0 => 101c02
+vextuwrx 00101c0800101c10 00101c0000101c02 1 => 101c
+vextuwrx 00101c0800101c10 00101c0000101c02 2 => 1c000010
+vextuwrx 00101c0800101c10 00101c0000101c02 3 => 101c0000
+vextuwrx 00101c0800101c10 00101c0000101c02 4 => 101c00
+vextuwrx 00101c0800101c10 00101c0000101c02 5 => 1000101c
+vextuwrx 00101c0800101c10 00101c0000101c02 6 => 1c100010
+vextuwrx 00101c0800101c10 00101c0000101c02 7 => 101c1000
+vextuwrx 00101c0800101c10 00101c0000101c02 8 => 101c10
+vextuwrx 00101c0800101c10 00101c0000101c02 9 => 800101c
+vextuwrx 00101c0800101c10 00101c0000101c02 10 => 1c080010
+vextuwrx 00101c0800101c10 00101c0000101c02 11 => 101c0800
+vextuwrx 00101c0800101c10 00101c0000101c02 12 => 101c08
+vextuwrx 00101c0800101c10 00101c0000101c02 13 => 0
+vextuwrx 00101c0800101c10 00101c0000101c02 14 => 0
+vextuwrx 00101c0800101c10 00101c0000101c02 15 => 0
+vextuwrx 00001f0800001f10 00001f0000001f02 0 => 1f02
+vextuwrx 00001f0800001f10 00001f0000001f02 1 => 1f
+vextuwrx 00001f0800001f10 00001f0000001f02 2 => 1f000000
+vextuwrx 00001f0800001f10 00001f0000001f02 3 => 1f0000
+vextuwrx 00001f0800001f10 00001f0000001f02 4 => 1f00
+vextuwrx 00001f0800001f10 00001f0000001f02 5 => 1000001f
+vextuwrx 00001f0800001f10 00001f0000001f02 6 => 1f100000
+vextuwrx 00001f0800001f10 00001f0000001f02 7 => 1f1000
+vextuwrx 00001f0800001f10 00001f0000001f02 8 => 1f10
+vextuwrx 00001f0800001f10 00001f0000001f02 9 => 800001f
+vextuwrx 00001f0800001f10 00001f0000001f02 10 => 1f080000
+vextuwrx 00001f0800001f10 00001f0000001f02 11 => 1f0800
+vextuwrx 00001f0800001f10 00001f0000001f02 12 => 1f08
+vextuwrx 00001f0800001f10 00001f0000001f02 13 => 0
+vextuwrx 00001f0800001f10 00001f0000001f02 14 => 0
+vextuwrx 00001f0800001f10 00001f0000001f02 15 => 0
+vextuwrx 00101f0800101f10 00101f0000101f02 0 => 101f02
+vextuwrx 00101f0800101f10 00101f0000101f02 1 => 101f
+vextuwrx 00101f0800101f10 00101f0000101f02 2 => 1f000010
+vextuwrx 00101f0800101f10 00101f0000101f02 3 => 101f0000
+vextuwrx 00101f0800101f10 00101f0000101f02 4 => 101f00
+vextuwrx 00101f0800101f10 00101f0000101f02 5 => 1000101f
+vextuwrx 00101f0800101f10 00101f0000101f02 6 => 1f100010
+vextuwrx 00101f0800101f10 00101f0000101f02 7 => 101f1000
+vextuwrx 00101f0800101f10 00101f0000101f02 8 => 101f10
+vextuwrx 00101f0800101f10 00101f0000101f02 9 => 800101f
+vextuwrx 00101f0800101f10 00101f0000101f02 10 => 1f080010
+vextuwrx 00101f0800101f10 00101f0000101f02 11 => 101f0800
+vextuwrx 00101f0800101f10 00101f0000101f02 12 => 101f08
+vextuwrx 00101f0800101f10 00101f0000101f02 13 => 0
+vextuwrx 00101f0800101f10 00101f0000101f02 14 => 0
+vextuwrx 00101f0800101f10 00101f0000101f02 15 => 0
+
+All done. Tested 106 different instructions
+ppc vector count leading/trailing bytes:
+Test instruction group [ppc vector count leading/trailing bytes]
+vclzlsbb 0000000000000000 0000000000000000 0 => 16
+vclzlsbb 0102010201020102 0102030405060708 0 => 0
+vclzlsbb 8899aabbccddeeff 0011223344556677 0 => 1
+vclzlsbb 7060504030201000 f0e0d0c0b0a09080 0 => 16
+vclzlsbb 0000100800001010 0000100000001002 0 => 16
+vclzlsbb 0010100800101010 0010100000101002 0 => 16
+vclzlsbb 00001c0800001c10 00001c0000001c02 0 => 16
+vclzlsbb 00101c0800101c10 00101c0000101c02 0 => 16
+vclzlsbb 00001f0800001f10 00001f0000001f02 0 => 2
+vclzlsbb 00101f0800101f10 00101f0000101f02 0 => 2
+
+vctzlsbb 0000000000000000 0000000000000000 0 => 16
+vctzlsbb 0102010201020102 0102030405060708 0 => 1
+vctzlsbb 8899aabbccddeeff 0011223344556677 0 => 0
+vctzlsbb 7060504030201000 f0e0d0c0b0a09080 0 => 16
+vctzlsbb 0000100800001010 0000100000001002 0 => 16
+vctzlsbb 0010100800101010 0010100000101002 0 => 16
+vctzlsbb 00001c0800001c10 00001c0000001c02 0 => 16
+vctzlsbb 00101c0800101c10 00101c0000101c02 0 => 16
+vctzlsbb 00001f0800001f10 00001f0000001f02 0 => 1
+vctzlsbb 00101f0800101f10 00101f0000101f02 0 => 1
+
+All done. Tested 108 different instructions
+ppc vector load/store:
+Test instruction group [ppc vector load/store]
+lxvl 0000000000000000 0000000000000000 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0000000000000000 0000000000000000 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0000000000000000 0000000000000000 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0000000000000000 0000000000000000 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0000000000000000 0000000000000000 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0000000000000000 0000000000000000 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0000000000000000 0000000000000000 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 00000000ffffffff & 400000000000000
+lxvl 0000000000000000 0000000000000000 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000004050607 & 400000000000000
+lxvl 0000000000000000 0000000000000000 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000055555555 & 400000000000000
+lxvl 0000000000000000 0000000000000000 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 400000000000000
+lxvl 0000000000000000 0000000000000000 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 00000000ffffffff & 400000000000000
+lxvl 0000000000000000 0000000000000000 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000004050607 & 400000000000000
+lxvl 0000000000000000 0000000000000000 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvl 0000000000000000 0000000000000000 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvl 0000000000000000 0000000000000000 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 800000000000000
+lxvl 0000000000000000 0000000000000000 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 800000000000000
+lxvl 0000000000000000 0000000000000000 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvl 0000000000000000 0000000000000000 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvl 0000000000000000 0000000000000000 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000004050607 ffffffffffffffff & c00000000000000
+lxvl 0000000000000000 0000000000000000 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000055555555 0001020304050607 & c00000000000000
+lxvl 0000000000000000 0000000000000000 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & c00000000000000
+lxvl 0000000000000000 0000000000000000 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00000000ffffffff 0000000000000000 & c00000000000000
+lxvl 0000000000000000 0000000000000000 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000004050607 ffffffffffffffff & c00000000000000
+lxvl 0000000000000000 0000000000000000 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000055555555 0001020304050607 & c00000000000000
+lxvl 0000000000000000 0000000000000000 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvl 0000000000000000 0000000000000000 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvl 0000000000000000 0000000000000000 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 1000000000000000
+lxvl 0000000000000000 0000000000000000 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 1000000000000000
+lxvl 0000000000000000 0000000000000000 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvl 0000000000000000 0000000000000000 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvl 0102010201020102 0102030405060708 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0102010201020102 0102030405060708 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0102010201020102 0102030405060708 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0102010201020102 0102030405060708 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0102010201020102 0102030405060708 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0102010201020102 0102030405060708 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 0102010201020102 0102030405060708 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 00000000ffffffff & 400000000000000
+lxvl 0102010201020102 0102030405060708 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000004050607 & 400000000000000
+lxvl 0102010201020102 0102030405060708 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000055555555 & 400000000000000
+lxvl 0102010201020102 0102030405060708 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 400000000000000
+lxvl 0102010201020102 0102030405060708 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 00000000ffffffff & 400000000000000
+lxvl 0102010201020102 0102030405060708 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000004050607 & 400000000000000
+lxvl 0102010201020102 0102030405060708 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvl 0102010201020102 0102030405060708 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvl 0102010201020102 0102030405060708 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 800000000000000
+lxvl 0102010201020102 0102030405060708 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 800000000000000
+lxvl 0102010201020102 0102030405060708 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvl 0102010201020102 0102030405060708 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvl 0102010201020102 0102030405060708 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000004050607 ffffffffffffffff & c00000000000000
+lxvl 0102010201020102 0102030405060708 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000055555555 0001020304050607 & c00000000000000
+lxvl 0102010201020102 0102030405060708 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & c00000000000000
+lxvl 0102010201020102 0102030405060708 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00000000ffffffff 0000000000000000 & c00000000000000
+lxvl 0102010201020102 0102030405060708 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000004050607 ffffffffffffffff & c00000000000000
+lxvl 0102010201020102 0102030405060708 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000055555555 0001020304050607 & c00000000000000
+lxvl 0102010201020102 0102030405060708 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvl 0102010201020102 0102030405060708 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvl 0102010201020102 0102030405060708 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 1000000000000000
+lxvl 0102010201020102 0102030405060708 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 1000000000000000
+lxvl 0102010201020102 0102030405060708 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvl 0102010201020102 0102030405060708 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 8899aabbccddeeff 0011223344556677 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 8899aabbccddeeff 0011223344556677 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 00000000ffffffff & 400000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000004050607 & 400000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000055555555 & 400000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 400000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 00000000ffffffff & 400000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000004050607 & 400000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 800000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 800000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000004050607 ffffffffffffffff & c00000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000055555555 0001020304050607 & c00000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & c00000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00000000ffffffff 0000000000000000 & c00000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000004050607 ffffffffffffffff & c00000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000055555555 0001020304050607 & c00000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 1000000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 1000000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvl 8899aabbccddeeff 0011223344556677 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 00000000ffffffff & 400000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000004050607 & 400000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000055555555 & 400000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 400000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 00000000ffffffff & 400000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000004050607 & 400000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 800000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 800000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 ffffffffffffffff & 800000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0001020304050607 & 800000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000004050607 ffffffffffffffff & c00000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000055555555 0001020304050607 & c00000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & c00000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00000000ffffffff 0000000000000000 & c00000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000004050607 ffffffffffffffff & c00000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000055555555 0001020304050607 & c00000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 1000000000000000
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+lxvl 00001f0800001f10 00001f0000001f02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 1000000000000000
+lxvl 00001f0800001f10 00001f0000001f02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 1000000000000000
+lxvl 00001f0800001f10 00001f0000001f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 1000000000000000
+lxvl 00001f0800001f10 00001f0000001f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+lxvl 00101f0800101f10 00101f0000101f02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 00101f0800101f10 00101f0000101f02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 00101f0800101f10 00101f0000101f02 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 00101f0800101f10 00101f0000101f02 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 00101f0800101f10 00101f0000101f02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxvl 00101f0800101f10 00101f0000101f02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxvl 00101f0800101f10 00101f0000101f02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 00000000ffffffff & 400000000000000
+lxvl 00101f0800101f10 00101f0000101f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000004050607 & 400000000000000
+lxvl 00101f0800101f10 00101f0000101f02 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000055555555 & 400000000000000
+lxvl 00101f0800101f10 00101f0000101f02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 400000000000000
+lxvl 00101f0800101f10 00101f0000101f02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 00000000ffffffff & 400000000000000
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+lxvl 00101f0800101f10 00101f0000101f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000055555555 0001020304050607 & c00000000000000
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+lxvl 00101f0800101f10 00101f0000101f02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 1000000000000000
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+lxvl 00101f0800101f10 00101f0000101f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 1000000000000000
+
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+lxvll 0000000000000000 0000000000000000 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 5555555500000000 0000000000000000 & 400000000000000
+lxvll 0000000000000000 0000000000000000 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 400000000000000
+lxvll 0000000000000000 0000000000000000 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> ffffffff00000000 0000000000000000 & 400000000000000
+lxvll 0000000000000000 0000000000000000 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0706050400000000 0000000000000000 & 400000000000000
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+lxvll 0000000000000000 0000000000000000 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 5555555555555555 0000000000000000 & 800000000000000
+lxvll 0000000000000000 0000000000000000 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 800000000000000
+lxvll 0000000000000000 0000000000000000 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> ffffffffffffffff 0000000000000000 & 800000000000000
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+lxvll 0000000000000000 0000000000000000 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0706050403020100 5555555500000000 & c00000000000000
+lxvll 0000000000000000 0000000000000000 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 5555555555555555 0000000000000000 & c00000000000000
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+lxvll 0000000000000000 0000000000000000 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> ffffffffffffffff 0706050400000000 & c00000000000000
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+lxvll 0000000000000000 0000000000000000 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 5555555555555555 0000000000000000 & 1000000000000000
+lxvll 0000000000000000 0000000000000000 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 ffffffffffffffff & 1000000000000000
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+lxvll 0000000000000000 0000000000000000 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0706050403020100 5555555555555555 & 1000000000000000
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+lxvll 00001f0800001f10 00001f0000001f02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> ffffffffffffffff 0706050400000000 & c00000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0706050403020100 5555555500000000 & c00000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> ffffffffffffffff 0706050403020100 & 1000000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0706050403020100 5555555555555555 & 1000000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 5555555555555555 0000000000000000 & 1000000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 ffffffffffffffff & 1000000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> ffffffffffffffff 0706050403020100 & 1000000000000000
+lxvll 00001f0800001f10 00001f0000001f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0706050403020100 5555555555555555 & 1000000000000000
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+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 4
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 000000000000ffff 0000000000000000 & 4
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000203 0000000000000000 & 4
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000607 0000000000000000 & 8
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000005555 0000000000000000 & 8
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 8
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 000000000000ffff 0000000000000000 & 8
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000607 0000000000000000 & 8
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000005555 0000000000000000 & 8
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000203 0000000000000000 & c
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000005555 0000000000000000 & c
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & c
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 000000000000ffff 0000000000000000 & c
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000203 0000000000000000 & c
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000005555 0000000000000000 & c
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000005555 0000000000000000 & 10
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 000000000000ffff 0000000000000000 & 10
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000607 0000000000000000 & 10
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000005555 0000000000000000 & 10
+lxsihzx 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 000000000000ffff 0000000000000000 & 0
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000607 0000000000000000 & 0
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000005555 0000000000000000 & 0
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 000000000000ffff 0000000000000000 & 0
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000607 0000000000000000 & 0
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 000000000000ffff 0000000000000000 & 4
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000203 0000000000000000 & 4
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000005555 0000000000000000 & 4
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 4
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 000000000000ffff 0000000000000000 & 4
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000203 0000000000000000 & 4
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000607 0000000000000000 & 8
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000005555 0000000000000000 & 8
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 8
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 000000000000ffff 0000000000000000 & 8
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000607 0000000000000000 & 8
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000005555 0000000000000000 & 8
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000203 0000000000000000 & c
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000005555 0000000000000000 & c
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & c
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 000000000000ffff 0000000000000000 & c
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000203 0000000000000000 & c
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000005555 0000000000000000 & c
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000005555 0000000000000000 & 10
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 000000000000ffff 0000000000000000 & 10
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000607 0000000000000000 & 10
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000005555 0000000000000000 & 10
+lxsihzx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+
+stxvl 0000000000000000 0000000000000000 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+stxvl 0000000000000000 0000000000000000 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxvl 0000000000000000 0000000000000000 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+stxvl 0000000000000000 0000000000000000 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+stxvl 0000000000000000 0000000000000000 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+stxvl 0000000000000000 0000000000000000 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxvl 0000000000000000 0000000000000000 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 400000000000000
+stxvl 0000000000000000 0000000000000000 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 400000000000000
+stxvl 0000000000000000 0000000000000000 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 400000000000000
+stxvl 0000000000000000 0000000000000000 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 400000000000000
+stxvl 0000000000000000 0000000000000000 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 400000000000000
+stxvl 0000000000000000 0000000000000000 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 400000000000000
+stxvl 0000000000000000 0000000000000000 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 800000000000000
+stxvl 0000000000000000 0000000000000000 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 800000000000000
+stxvl 0000000000000000 0000000000000000 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 800000000000000
+stxvl 0000000000000000 0000000000000000 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 800000000000000
+stxvl 0000000000000000 0000000000000000 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 800000000000000
+stxvl 0000000000000000 0000000000000000 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 800000000000000
+stxvl 0000000000000000 0000000000000000 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c00000000000000
+stxvl 0000000000000000 0000000000000000 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c00000000000000
+stxvl 0000000000000000 0000000000000000 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & c00000000000000
+stxvl 0000000000000000 0000000000000000 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & c00000000000000
+stxvl 0000000000000000 0000000000000000 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c00000000000000
+stxvl 0000000000000000 0000000000000000 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c00000000000000
+stxvl 0000000000000000 0000000000000000 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvl 0000000000000000 0000000000000000 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvl 0000000000000000 0000000000000000 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvl 0000000000000000 0000000000000000 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvl 0000000000000000 0000000000000000 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvl 0000000000000000 0000000000000000 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvl 0102010201020102 0102030405060708 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 0
+stxvl 0102010201020102 0102030405060708 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 0
+stxvl 0102010201020102 0102030405060708 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 0
+stxvl 0102010201020102 0102030405060708 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 0
+stxvl 0102010201020102 0102030405060708 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 0
+stxvl 0102010201020102 0102030405060708 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 0
+stxvl 0102010201020102 0102030405060708 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 400000000000000
+stxvl 0102010201020102 0102030405060708 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 400000000000000
+stxvl 0102010201020102 0102030405060708 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 400000000000000
+stxvl 0102010201020102 0102030405060708 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 400000000000000
+stxvl 0102010201020102 0102030405060708 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 400000000000000
+stxvl 0102010201020102 0102030405060708 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 400000000000000
+stxvl 0102010201020102 0102030405060708 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 800000000000000
+stxvl 0102010201020102 0102030405060708 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 800000000000000
+stxvl 0102010201020102 0102030405060708 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 800000000000000
+stxvl 0102010201020102 0102030405060708 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 800000000000000
+stxvl 0102010201020102 0102030405060708 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 800000000000000
+stxvl 0102010201020102 0102030405060708 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 800000000000000
+stxvl 0102010201020102 0102030405060708 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & c00000000000000
+stxvl 0102010201020102 0102030405060708 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & c00000000000000
+stxvl 0102010201020102 0102030405060708 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & c00000000000000
+stxvl 0102010201020102 0102030405060708 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & c00000000000000
+stxvl 0102010201020102 0102030405060708 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & c00000000000000
+stxvl 0102010201020102 0102030405060708 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & c00000000000000
+stxvl 0102010201020102 0102030405060708 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 1000000000000000
+stxvl 0102010201020102 0102030405060708 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 1000000000000000
+stxvl 0102010201020102 0102030405060708 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 1000000000000000
+stxvl 0102010201020102 0102030405060708 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 1000000000000000
+stxvl 0102010201020102 0102030405060708 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 1000000000000000
+stxvl 0102010201020102 0102030405060708 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 1000000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 0
+stxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 0
+stxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 0
+stxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 0
+stxvl 8899aabbccddeeff 0011223344556677 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 0
+stxvl 8899aabbccddeeff 0011223344556677 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 0
+stxvl 8899aabbccddeeff 0011223344556677 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 400000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 400000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 400000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 400000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 400000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 400000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 800000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 800000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 800000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 800000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 800000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 800000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & c00000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & c00000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & c00000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & c00000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & c00000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & c00000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 1000000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 1000000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 1000000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 1000000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 1000000000000000
+stxvl 8899aabbccddeeff 0011223344556677 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 1000000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 400000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 400000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 400000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 400000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 400000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 400000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 800000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 800000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 800000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 800000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 800000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 800000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & c00000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & c00000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & c00000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & c00000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & c00000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & c00000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 1000000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 1000000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 1000000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 1000000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 1000000000000000
+stxvl 7060504030201000 f0e0d0c0b0a09080 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 1000000000000000
+stxvl 0000100800001010 0000100000001002 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 0
+stxvl 0000100800001010 0000100000001002 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 0
+stxvl 0000100800001010 0000100000001002 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 0
+stxvl 0000100800001010 0000100000001002 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 0
+stxvl 0000100800001010 0000100000001002 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 0
+stxvl 0000100800001010 0000100000001002 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 0
+stxvl 0000100800001010 0000100000001002 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 400000000000000
+stxvl 0000100800001010 0000100000001002 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 400000000000000
+stxvl 0000100800001010 0000100000001002 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 400000000000000
+stxvl 0000100800001010 0000100000001002 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 400000000000000
+stxvl 0000100800001010 0000100000001002 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 400000000000000
+stxvl 0000100800001010 0000100000001002 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 400000000000000
+stxvl 0000100800001010 0000100000001002 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 800000000000000
+stxvl 0000100800001010 0000100000001002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 800000000000000
+stxvl 0000100800001010 0000100000001002 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 800000000000000
+stxvl 0000100800001010 0000100000001002 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 800000000000000
+stxvl 0000100800001010 0000100000001002 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 800000000000000
+stxvl 0000100800001010 0000100000001002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 800000000000000
+stxvl 0000100800001010 0000100000001002 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c00000000000000
+stxvl 0000100800001010 0000100000001002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c00000000000000
+stxvl 0000100800001010 0000100000001002 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & c00000000000000
+stxvl 0000100800001010 0000100000001002 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & c00000000000000
+stxvl 0000100800001010 0000100000001002 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c00000000000000
+stxvl 0000100800001010 0000100000001002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c00000000000000
+stxvl 0000100800001010 0000100000001002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 1000000000000000
+stxvl 0000100800001010 0000100000001002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 1000000000000000
+stxvl 0000100800001010 0000100000001002 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 1000000000000000
+stxvl 0000100800001010 0000100000001002 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 1000000000000000
+stxvl 0000100800001010 0000100000001002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 1000000000000000
+stxvl 0000100800001010 0000100000001002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 1000000000000000
+stxvl 0010100800101010 0010100000101002 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 0
+stxvl 0010100800101010 0010100000101002 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
+stxvl 0010100800101010 0010100000101002 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 0
+stxvl 0010100800101010 0010100000101002 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 0
+stxvl 0010100800101010 0010100000101002 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 0
+stxvl 0010100800101010 0010100000101002 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
+stxvl 0010100800101010 0010100000101002 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 400000000000000
+stxvl 0010100800101010 0010100000101002 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 400000000000000
+stxvl 0010100800101010 0010100000101002 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 400000000000000
+stxvl 0010100800101010 0010100000101002 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 400000000000000
+stxvl 0010100800101010 0010100000101002 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 400000000000000
+stxvl 0010100800101010 0010100000101002 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 400000000000000
+stxvl 0010100800101010 0010100000101002 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 800000000000000
+stxvl 0010100800101010 0010100000101002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 800000000000000
+stxvl 0010100800101010 0010100000101002 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 800000000000000
+stxvl 0010100800101010 0010100000101002 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 800000000000000
+stxvl 0010100800101010 0010100000101002 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 800000000000000
+stxvl 0010100800101010 0010100000101002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 800000000000000
+stxvl 0010100800101010 0010100000101002 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c00000000000000
+stxvl 0010100800101010 0010100000101002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c00000000000000
+stxvl 0010100800101010 0010100000101002 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & c00000000000000
+stxvl 0010100800101010 0010100000101002 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & c00000000000000
+stxvl 0010100800101010 0010100000101002 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c00000000000000
+stxvl 0010100800101010 0010100000101002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c00000000000000
+stxvl 0010100800101010 0010100000101002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 1000000000000000
+stxvl 0010100800101010 0010100000101002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 1000000000000000
+stxvl 0010100800101010 0010100000101002 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 1000000000000000
+stxvl 0010100800101010 0010100000101002 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 1000000000000000
+stxvl 0010100800101010 0010100000101002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 1000000000000000
+stxvl 0010100800101010 0010100000101002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 1000000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxvl 00001c0800001c10 00001c0000001c02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxvl 00001c0800001c10 00001c0000001c02 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxvl 00001c0800001c10 00001c0000001c02 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxvl 00001c0800001c10 00001c0000001c02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxvl 00001c0800001c10 00001c0000001c02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxvl 00001c0800001c10 00001c0000001c02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 400000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 400000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 400000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 400000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 400000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 400000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 800000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 800000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 800000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 800000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 800000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 800000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c00000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c00000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & c00000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & c00000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c00000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c00000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 1000000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 1000000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 1000000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 1000000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 1000000000000000
+stxvl 00001c0800001c10 00001c0000001c02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 1000000000000000
+stxvl 00101c0800101c10 00101c0000101c02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxvl 00101c0800101c10 00101c0000101c02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxvl 00101c0800101c10 00101c0000101c02 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxvl 00101c0800101c10 00101c0000101c02 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxvl 00101c0800101c10 00101c0000101c02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxvl 00101c0800101c10 00101c0000101c02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxvl 00101c0800101c10 00101c0000101c02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 400000000000000
+stxvl 00101c0800101c10 00101c0000101c02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 400000000000000
+stxvl 00101c0800101c10 00101c0000101c02 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 400000000000000
+stxvl 00101c0800101c10 00101c0000101c02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 400000000000000
+stxvl 00101c0800101c10 00101c0000101c02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 400000000000000
+stxvl 00101c0800101c10 00101c0000101c02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 400000000000000
+stxvl 00101c0800101c10 00101c0000101c02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 800000000000000
+stxvl 00101c0800101c10 00101c0000101c02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 800000000000000
+stxvl 00101c0800101c10 00101c0000101c02 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 800000000000000
+stxvl 00101c0800101c10 00101c0000101c02 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 800000000000000
+stxvl 00101c0800101c10 00101c0000101c02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 800000000000000
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+stxvl 00101c0800101c10 00101c0000101c02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c00000000000000
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+stxvl 00101c0800101c10 00101c0000101c02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 1000000000000000
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+stxvl 00001f0800001f10 00001f0000001f02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxvl 00001f0800001f10 00001f0000001f02 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxvl 00001f0800001f10 00001f0000001f02 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxvl 00001f0800001f10 00001f0000001f02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxvl 00001f0800001f10 00001f0000001f02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxvl 00001f0800001f10 00001f0000001f02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 400000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 400000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 400000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 400000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 400000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 400000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 800000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 800000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 800000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 800000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 800000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 800000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c00000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c00000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & c00000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & c00000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c00000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c00000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 1000000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 1000000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 1000000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 1000000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 1000000000000000
+stxvl 00001f0800001f10 00001f0000001f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 1000000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
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+stxvl 00101f0800101f10 00101f0000101f02 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 0
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+stxvl 00101f0800101f10 00101f0000101f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 400000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 400000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 400000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 400000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 400000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 800000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 800000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 800000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 800000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 800000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 800000000000000
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+stxvl 00101f0800101f10 00101f0000101f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c00000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & c00000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & c00000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c00000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c00000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 1000000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 1000000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 1000000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 1000000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 1000000000000000
+stxvl 00101f0800101f10 00101f0000101f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 1000000000000000
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+stxvll 0000000000000000 0000000000000000 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxvll 0000000000000000 0000000000000000 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+stxvll 0000000000000000 0000000000000000 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+stxvll 0000000000000000 0000000000000000 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+stxvll 0000000000000000 0000000000000000 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxvll 0000000000000000 0000000000000000 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 400000000000000
+stxvll 0000000000000000 0000000000000000 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 400000000000000
+stxvll 0000000000000000 0000000000000000 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 400000000000000
+stxvll 0000000000000000 0000000000000000 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 400000000000000
+stxvll 0000000000000000 0000000000000000 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 400000000000000
+stxvll 0000000000000000 0000000000000000 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 400000000000000
+stxvll 0000000000000000 0000000000000000 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 800000000000000
+stxvll 0000000000000000 0000000000000000 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 800000000000000
+stxvll 0000000000000000 0000000000000000 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 800000000000000
+stxvll 0000000000000000 0000000000000000 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 800000000000000
+stxvll 0000000000000000 0000000000000000 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 800000000000000
+stxvll 0000000000000000 0000000000000000 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 800000000000000
+stxvll 0000000000000000 0000000000000000 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c00000000000000
+stxvll 0000000000000000 0000000000000000 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c00000000000000
+stxvll 0000000000000000 0000000000000000 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & c00000000000000
+stxvll 0000000000000000 0000000000000000 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & c00000000000000
+stxvll 0000000000000000 0000000000000000 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c00000000000000
+stxvll 0000000000000000 0000000000000000 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c00000000000000
+stxvll 0000000000000000 0000000000000000 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvll 0000000000000000 0000000000000000 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvll 0000000000000000 0000000000000000 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvll 0000000000000000 0000000000000000 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvll 0000000000000000 0000000000000000 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvll 0000000000000000 0000000000000000 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 1000000000000000
+stxvll 0102010201020102 0102030405060708 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 0
+stxvll 0102010201020102 0102030405060708 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 0
+stxvll 0102010201020102 0102030405060708 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 0
+stxvll 0102010201020102 0102030405060708 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 0
+stxvll 0102010201020102 0102030405060708 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 0
+stxvll 0102010201020102 0102030405060708 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 0
+stxvll 0102010201020102 0102030405060708 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 400000000000000
+stxvll 0102010201020102 0102030405060708 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 400000000000000
+stxvll 0102010201020102 0102030405060708 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 400000000000000
+stxvll 0102010201020102 0102030405060708 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 400000000000000
+stxvll 0102010201020102 0102030405060708 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 400000000000000
+stxvll 0102010201020102 0102030405060708 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 400000000000000
+stxvll 0102010201020102 0102030405060708 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 800000000000000
+stxvll 0102010201020102 0102030405060708 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 800000000000000
+stxvll 0102010201020102 0102030405060708 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 800000000000000
+stxvll 0102010201020102 0102030405060708 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 800000000000000
+stxvll 0102010201020102 0102030405060708 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 800000000000000
+stxvll 0102010201020102 0102030405060708 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 800000000000000
+stxvll 0102010201020102 0102030405060708 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & c00000000000000
+stxvll 0102010201020102 0102030405060708 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & c00000000000000
+stxvll 0102010201020102 0102030405060708 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & c00000000000000
+stxvll 0102010201020102 0102030405060708 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & c00000000000000
+stxvll 0102010201020102 0102030405060708 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & c00000000000000
+stxvll 0102010201020102 0102030405060708 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & c00000000000000
+stxvll 0102010201020102 0102030405060708 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 1000000000000000
+stxvll 0102010201020102 0102030405060708 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 1000000000000000
+stxvll 0102010201020102 0102030405060708 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 1000000000000000
+stxvll 0102010201020102 0102030405060708 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 1000000000000000
+stxvll 0102010201020102 0102030405060708 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 1000000000000000
+stxvll 0102010201020102 0102030405060708 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 1000000000000000
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+stxvll 8899aabbccddeeff 0011223344556677 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 1000000000000000
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+stxvll 8899aabbccddeeff 0011223344556677 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 1000000000000000
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+stxvll 8899aabbccddeeff 0011223344556677 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 1000000000000000
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+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 400000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 400000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 400000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 400000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 400000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 400000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 800000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 800000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 800000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 800000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 800000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 800000000000000
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+stxvll 7060504030201000 f0e0d0c0b0a09080 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & c00000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & c00000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & c00000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & c00000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & c00000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 1000000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 1000000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 1000000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 1000000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 1000000000000000
+stxvll 7060504030201000 f0e0d0c0b0a09080 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 1000000000000000
+stxvll 0000100800001010 0000100000001002 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 0
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+stxvll 0000100800001010 0000100000001002 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 0
+stxvll 0000100800001010 0000100000001002 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 0
+stxvll 0000100800001010 0000100000001002 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 0
+stxvll 0000100800001010 0000100000001002 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 400000000000000
+stxvll 0000100800001010 0000100000001002 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 400000000000000
+stxvll 0000100800001010 0000100000001002 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 400000000000000
+stxvll 0000100800001010 0000100000001002 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 400000000000000
+stxvll 0000100800001010 0000100000001002 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 400000000000000
+stxvll 0000100800001010 0000100000001002 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 400000000000000
+stxvll 0000100800001010 0000100000001002 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 800000000000000
+stxvll 0000100800001010 0000100000001002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 800000000000000
+stxvll 0000100800001010 0000100000001002 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 800000000000000
+stxvll 0000100800001010 0000100000001002 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 800000000000000
+stxvll 0000100800001010 0000100000001002 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 800000000000000
+stxvll 0000100800001010 0000100000001002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 800000000000000
+stxvll 0000100800001010 0000100000001002 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c00000000000000
+stxvll 0000100800001010 0000100000001002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c00000000000000
+stxvll 0000100800001010 0000100000001002 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & c00000000000000
+stxvll 0000100800001010 0000100000001002 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & c00000000000000
+stxvll 0000100800001010 0000100000001002 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c00000000000000
+stxvll 0000100800001010 0000100000001002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c00000000000000
+stxvll 0000100800001010 0000100000001002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 1000000000000000
+stxvll 0000100800001010 0000100000001002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 1000000000000000
+stxvll 0000100800001010 0000100000001002 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 1000000000000000
+stxvll 0000100800001010 0000100000001002 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 1000000000000000
+stxvll 0000100800001010 0000100000001002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 1000000000000000
+stxvll 0000100800001010 0000100000001002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 1000000000000000
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+stxvll 0010100800101010 0010100000101002 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 0
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+stxvll 0010100800101010 0010100000101002 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 400000000000000
+stxvll 0010100800101010 0010100000101002 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 400000000000000
+stxvll 0010100800101010 0010100000101002 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 400000000000000
+stxvll 0010100800101010 0010100000101002 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 400000000000000
+stxvll 0010100800101010 0010100000101002 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 400000000000000
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+stxvll 0010100800101010 0010100000101002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 800000000000000
+stxvll 0010100800101010 0010100000101002 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 800000000000000
+stxvll 0010100800101010 0010100000101002 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 800000000000000
+stxvll 0010100800101010 0010100000101002 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 800000000000000
+stxvll 0010100800101010 0010100000101002 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 800000000000000
+stxvll 0010100800101010 0010100000101002 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c00000000000000
+stxvll 0010100800101010 0010100000101002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c00000000000000
+stxvll 0010100800101010 0010100000101002 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & c00000000000000
+stxvll 0010100800101010 0010100000101002 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & c00000000000000
+stxvll 0010100800101010 0010100000101002 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c00000000000000
+stxvll 0010100800101010 0010100000101002 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c00000000000000
+stxvll 0010100800101010 0010100000101002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 1000000000000000
+stxvll 0010100800101010 0010100000101002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 1000000000000000
+stxvll 0010100800101010 0010100000101002 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 1000000000000000
+stxvll 0010100800101010 0010100000101002 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 1000000000000000
+stxvll 0010100800101010 0010100000101002 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 1000000000000000
+stxvll 0010100800101010 0010100000101002 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 1000000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxvll 00001c0800001c10 00001c0000001c02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxvll 00001c0800001c10 00001c0000001c02 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxvll 00001c0800001c10 00001c0000001c02 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxvll 00001c0800001c10 00001c0000001c02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxvll 00001c0800001c10 00001c0000001c02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxvll 00001c0800001c10 00001c0000001c02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 400000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 400000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 400000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 400000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 400000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 400000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 800000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 800000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 800000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 800000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 800000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 800000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c00000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c00000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & c00000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & c00000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c00000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c00000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 1000000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 1000000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 1000000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 1000000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 1000000000000000
+stxvll 00001c0800001c10 00001c0000001c02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 1000000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxvll 00101c0800101c10 00101c0000101c02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxvll 00101c0800101c10 00101c0000101c02 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxvll 00101c0800101c10 00101c0000101c02 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxvll 00101c0800101c10 00101c0000101c02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxvll 00101c0800101c10 00101c0000101c02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxvll 00101c0800101c10 00101c0000101c02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 400000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 400000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 400000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 400000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 400000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 400000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 800000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 800000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 800000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 800000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 800000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 800000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & c00000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c00000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & c00000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & c00000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & c00000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c00000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 1000000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 1000000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 1000000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 1000000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 1000000000000000
+stxvll 00101c0800101c10 00101c0000101c02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 1000000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxvll 00001f0800001f10 00001f0000001f02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxvll 00001f0800001f10 00001f0000001f02 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxvll 00001f0800001f10 00001f0000001f02 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxvll 00001f0800001f10 00001f0000001f02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxvll 00001f0800001f10 00001f0000001f02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxvll 00001f0800001f10 00001f0000001f02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 400000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 400000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 400000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 400000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 400000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 400000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 800000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 800000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 800000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 800000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 800000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 800000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c00000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c00000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & c00000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & c00000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c00000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c00000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 1000000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 1000000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 1000000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 1000000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 1000000000000000
+stxvll 00001f0800001f10 00001f0000001f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 1000000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxvll 00101f0800101f10 00101f0000101f02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxvll 00101f0800101f10 00101f0000101f02 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxvll 00101f0800101f10 00101f0000101f02 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxvll 00101f0800101f10 00101f0000101f02 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxvll 00101f0800101f10 00101f0000101f02 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxvll 00101f0800101f10 00101f0000101f02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 400000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 400000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 400000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 400000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 400000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 400000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 800000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 800000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 800000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 800000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 800000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 800000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c00000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c00000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & c00000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & c00000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c00000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c00000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 1000000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 1000000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 1000000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 1000000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 1000000000000000
+stxvll 00101f0800101f10 00101f0000101f02 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 1000000000000000
+
+stxsibx 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+stxsibx 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxsibx 0000000000000000 0000000000000000 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+stxsibx 0000000000000000 0000000000000000 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+stxsibx 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+stxsibx 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxsibx 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
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+stxsibx 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 8
+stxsibx 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c
+stxsibx 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c
+stxsibx 0000100800001010 0000100000001002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & c
+stxsibx 0000100800001010 0000100000001002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & c
+stxsibx 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c
+stxsibx 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c
+stxsibx 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 10
+stxsibx 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 10
+stxsibx 0000100800001010 0000100000001002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 10
+stxsibx 0000100800001010 0000100000001002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 10
+stxsibx 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 10
+stxsibx 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 10
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+stxsibx 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
+stxsibx 0010100800101010 0010100000101002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 0
+stxsibx 0010100800101010 0010100000101002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 0
+stxsibx 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 0
+stxsibx 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
+stxsibx 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 4
+stxsibx 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 4
+stxsibx 0010100800101010 0010100000101002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 4
+stxsibx 0010100800101010 0010100000101002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 4
+stxsibx 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 4
+stxsibx 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 4
+stxsibx 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 8
+stxsibx 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 8
+stxsibx 0010100800101010 0010100000101002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 8
+stxsibx 0010100800101010 0010100000101002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 8
+stxsibx 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 8
+stxsibx 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 8
+stxsibx 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c
+stxsibx 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c
+stxsibx 0010100800101010 0010100000101002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & c
+stxsibx 0010100800101010 0010100000101002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & c
+stxsibx 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c
+stxsibx 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c
+stxsibx 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+stxsibx 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
+stxsibx 0010100800101010 0010100000101002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 10
+stxsibx 0010100800101010 0010100000101002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 10
+stxsibx 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+stxsibx 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxsibx 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxsibx 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxsibx 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxsibx 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
+
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+stxsihx 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxsihx 0000000000000000 0000000000000000 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+stxsihx 0000000000000000 0000000000000000 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+stxsihx 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+stxsihx 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxsihx 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+stxsihx 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+stxsihx 0000000000000000 0000000000000000 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 4
+stxsihx 0000000000000000 0000000000000000 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 4
+stxsihx 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+stxsihx 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+stxsihx 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+stxsihx 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+stxsihx 0000000000000000 0000000000000000 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 8
+stxsihx 0000000000000000 0000000000000000 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 8
+stxsihx 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+stxsihx 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+stxsihx 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+stxsihx 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+stxsihx 0000000000000000 0000000000000000 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & c
+stxsihx 0000000000000000 0000000000000000 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & c
+stxsihx 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+stxsihx 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+stxsihx 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+stxsihx 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+stxsihx 0000000000000000 0000000000000000 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 10
+stxsihx 0000000000000000 0000000000000000 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 10
+stxsihx 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+stxsihx 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+stxsihx 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 0
+stxsihx 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 0
+stxsihx 0102010201020102 0102030405060708 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 0
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+stxsihx 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 0
+stxsihx 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 0
+stxsihx 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 4
+stxsihx 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 4
+stxsihx 0102010201020102 0102030405060708 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 4
+stxsihx 0102010201020102 0102030405060708 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 4
+stxsihx 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 4
+stxsihx 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 4
+stxsihx 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 8
+stxsihx 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 8
+stxsihx 0102010201020102 0102030405060708 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 8
+stxsihx 0102010201020102 0102030405060708 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 8
+stxsihx 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 8
+stxsihx 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 8
+stxsihx 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & c
+stxsihx 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & c
+stxsihx 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & c
+stxsihx 0102010201020102 0102030405060708 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & c
+stxsihx 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & c
+stxsihx 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & c
+stxsihx 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 10
+stxsihx 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 10
+stxsihx 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 10
+stxsihx 0102010201020102 0102030405060708 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 10
+stxsihx 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 10
+stxsihx 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 10
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+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 0
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 4
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 4
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 4
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 4
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 4
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 4
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 8
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 8
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 8
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 8
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 8
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 8
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & c
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & c
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & c
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & c
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & c
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & c
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 10
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 10
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 10
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 10
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 10
+stxsihx 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 10
+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 8
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+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
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+stxsihx 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
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+stxsihx 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 0
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+stxsihx 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 4
+stxsihx 0000100800001010 0000100000001002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 4
+stxsihx 0000100800001010 0000100000001002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 4
+stxsihx 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 4
+stxsihx 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 4
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+stxsihx 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 8
+stxsihx 0000100800001010 0000100000001002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 8
+stxsihx 0000100800001010 0000100000001002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 8
+stxsihx 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 8
+stxsihx 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 8
+stxsihx 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c
+stxsihx 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c
+stxsihx 0000100800001010 0000100000001002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & c
+stxsihx 0000100800001010 0000100000001002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & c
+stxsihx 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c
+stxsihx 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c
+stxsihx 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 10
+stxsihx 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 10
+stxsihx 0000100800001010 0000100000001002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 10
+stxsihx 0000100800001010 0000100000001002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 10
+stxsihx 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 10
+stxsihx 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 10
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+stxsihx 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
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+stxsihx 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 4
+stxsihx 0010100800101010 0010100000101002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 4
+stxsihx 0010100800101010 0010100000101002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 4
+stxsihx 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 4
+stxsihx 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 4
+stxsihx 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 8
+stxsihx 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 8
+stxsihx 0010100800101010 0010100000101002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 8
+stxsihx 0010100800101010 0010100000101002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 8
+stxsihx 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 8
+stxsihx 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 8
+stxsihx 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c
+stxsihx 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c
+stxsihx 0010100800101010 0010100000101002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & c
+stxsihx 0010100800101010 0010100000101002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & c
+stxsihx 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c
+stxsihx 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c
+stxsihx 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+stxsihx 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
+stxsihx 0010100800101010 0010100000101002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 10
+stxsihx 0010100800101010 0010100000101002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 10
+stxsihx 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+stxsihx 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 0
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+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxsihx 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxsihx 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxsihx 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxsihx 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxsihx 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxsihx 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxsihx 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxsihx 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxsihx 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxsihx 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxsihx 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxsihx 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxsihx 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
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+stxsihx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxsihx 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 8
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+
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+lxssp 0 0102010201020102 0102030405060708 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 8
+lxssp 0 0102010201020102 0102030405060708 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 8
+lxssp 0 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 8
+lxssp 0 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 8
+lxssp 0 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & c
+lxssp 0 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & c
+lxssp 0 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & c
+lxssp 0 0102010201020102 0102030405060708 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & c
+lxssp 0 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & c
+lxssp 0 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & c
+lxssp 0 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 10
+lxssp 0 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 10
+lxssp 0 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 10
+lxssp 0 0102010201020102 0102030405060708 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 10
+lxssp 0 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 10
+lxssp 0 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 10
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 0
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 0
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 0
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 0
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 0
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 0
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 4
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 4
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 4
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 4
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 4
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 4
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 8
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 8
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 8
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 8
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 8
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 8
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & c
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & c
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & c
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & c
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & c
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & c
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 10
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 10
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 10
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 10
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 10
+lxssp 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 10
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & c
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & c
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+lxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+lxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 0
+lxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 0
+lxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 0
+lxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 0
+lxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 0
+lxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 0
+lxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 4
+lxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 4
+lxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 4
+lxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 4
+lxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 4
+lxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 4
+lxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 8
+lxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 8
+lxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 8
+lxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 8
+lxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 8
+lxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 8
+lxssp 0 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c
+lxssp 0 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c
+lxssp 0 0000100800001010 0000100000001002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & c
+lxssp 0 0000100800001010 0000100000001002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & c
+lxssp 0 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c
+lxssp 0 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c
+lxssp 0 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 10
+lxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 10
+lxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 10
+lxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 10
+lxssp 0 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 10
+lxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 10
+lxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 0
+lxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
+lxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 0
+lxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 0
+lxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 0
+lxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
+lxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 4
+lxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 4
+lxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 4
+lxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 4
+lxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 4
+lxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 4
+lxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 8
+lxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 8
+lxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 8
+lxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 8
+lxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 8
+lxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 8
+lxssp 0 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c
+lxssp 0 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c
+lxssp 0 0010100800101010 0010100000101002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & c
+lxssp 0 0010100800101010 0010100000101002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & c
+lxssp 0 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c
+lxssp 0 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c
+lxssp 0 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+lxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
+lxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 10
+lxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 10
+lxssp 0 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+lxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 0
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 0
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 4
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 4
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 4
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 4
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 4
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 4
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 8
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 8
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & c
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & c
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 10
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 10
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+lxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 0
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 0
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 4
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 4
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 4
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 4
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 8
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 8
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 8
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 8
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 8
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 8
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & c
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & c
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & c
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & c
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 10
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 10
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 10
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 10
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 10
+lxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 10
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 0
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 0
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 4
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 4
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 4
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 4
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 4
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 4
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 8
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 8
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 8
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 8
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & c
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & c
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 10
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 10
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 10
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 10
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 10
+lxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 10
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 0
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 0
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 4
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 4
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 4
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 4
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 4
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 4
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 8
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 8
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 8
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 8
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 8
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 8
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & c
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & c
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c
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+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 10
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 10
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 10
+lxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
+
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+stxssp 0 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 10
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+stxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+stxssp 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+stxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 0
+stxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 0
+stxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 0
+stxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 0
+stxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 0
+stxssp 0 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 0
+stxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 4
+stxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 4
+stxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 4
+stxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 4
+stxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 4
+stxssp 0 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 4
+stxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 8
+stxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 8
+stxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 8
+stxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 8
+stxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 8
+stxssp 0 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 8
+stxssp 0 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c
+stxssp 0 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c
+stxssp 0 0000100800001010 0000100000001002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & c
+stxssp 0 0000100800001010 0000100000001002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & c
+stxssp 0 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c
+stxssp 0 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c
+stxssp 0 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 10
+stxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 10
+stxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 10
+stxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 10
+stxssp 0 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 10
+stxssp 0 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 10
+stxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 0
+stxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
+stxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 0
+stxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 0
+stxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 0
+stxssp 0 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
+stxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 4
+stxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 4
+stxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 4
+stxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 4
+stxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 4
+stxssp 0 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 4
+stxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 8
+stxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 8
+stxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 8
+stxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 8
+stxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 8
+stxssp 0 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 8
+stxssp 0 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c
+stxssp 0 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c
+stxssp 0 0010100800101010 0010100000101002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & c
+stxssp 0 0010100800101010 0010100000101002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & c
+stxssp 0 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c
+stxssp 0 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c
+stxssp 0 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+stxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
+stxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 10
+stxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 10
+stxssp 0 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+stxssp 0 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxssp 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxssp 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxssp 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxssp 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
+
+lxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+lxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+lxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+lxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+lxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+lxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+lxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 4
+lxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 4
+lxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+lxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+lxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+lxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+lxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 8
+lxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 8
+lxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+lxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+lxssp 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+lxssp 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+lxssp 16 0000000000000000 0000000000000000 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & c
+lxssp 16 0000000000000000 0000000000000000 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & c
+lxssp 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+lxssp 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+lxssp 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+lxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+lxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 10
+lxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 10
+lxssp 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+lxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+lxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 0
+lxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 0
+lxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 0
+lxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 0
+lxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 0
+lxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 0
+lxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 4
+lxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 4
+lxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 4
+lxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 4
+lxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 4
+lxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 4
+lxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 8
+lxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 8
+lxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 8
+lxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 8
+lxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 8
+lxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 8
+lxssp 16 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & c
+lxssp 16 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & c
+lxssp 16 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & c
+lxssp 16 0102010201020102 0102030405060708 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & c
+lxssp 16 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & c
+lxssp 16 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & c
+lxssp 16 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 10
+lxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 10
+lxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 10
+lxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 10
+lxssp 16 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 10
+lxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 10
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 0
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 0
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 0
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 0
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 0
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 0
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 4
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 4
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 4
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 4
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 4
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 4
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 8
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 8
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 8
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 8
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 8
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 8
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & c
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & c
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & c
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & c
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & c
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & c
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 10
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 10
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 10
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 10
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 10
+lxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 10
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & c
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & c
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+lxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+lxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 0
+lxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 0
+lxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 0
+lxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 0
+lxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 0
+lxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 0
+lxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 4
+lxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 4
+lxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 4
+lxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 4
+lxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 4
+lxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 4
+lxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 8
+lxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 8
+lxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 8
+lxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 8
+lxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 8
+lxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 8
+lxssp 16 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c
+lxssp 16 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c
+lxssp 16 0000100800001010 0000100000001002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & c
+lxssp 16 0000100800001010 0000100000001002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & c
+lxssp 16 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c
+lxssp 16 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c
+lxssp 16 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 10
+lxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 10
+lxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 10
+lxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 10
+lxssp 16 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 10
+lxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 10
+lxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 0
+lxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
+lxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 0
+lxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 0
+lxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 0
+lxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
+lxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 4
+lxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 4
+lxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 4
+lxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 4
+lxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 4
+lxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 4
+lxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 8
+lxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 8
+lxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 8
+lxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 8
+lxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 8
+lxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 8
+lxssp 16 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c
+lxssp 16 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c
+lxssp 16 0010100800101010 0010100000101002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & c
+lxssp 16 0010100800101010 0010100000101002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & c
+lxssp 16 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c
+lxssp 16 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c
+lxssp 16 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+lxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
+lxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 10
+lxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 10
+lxssp 16 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+lxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 0
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 0
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 4
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 4
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 4
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 4
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 4
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 4
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 8
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 8
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & c
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & c
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 10
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 10
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+lxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 0
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 0
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 4
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 4
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 4
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 4
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 8
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 8
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 8
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 8
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 8
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 8
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & c
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & c
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & c
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & c
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 10
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 10
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 10
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 10
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 10
+lxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 10
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 0
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 0
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 4
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 4
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 4
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 4
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 4
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 4
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 8
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 8
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 8
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 8
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & c
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & c
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 10
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 10
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 10
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 10
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 10
+lxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 10
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 0
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 0
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 4
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 4
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 4
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 4
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 4
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 4
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 8
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 8
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 8
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 8
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 8
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 8
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & c
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & c
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 10
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 10
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 10
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 10
+lxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
+
+stxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+stxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+stxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+stxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+stxssp 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+stxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+stxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 4
+stxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 4
+stxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+stxssp 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+stxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+stxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+stxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 8
+stxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 8
+stxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+stxssp 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+stxssp 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+stxssp 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+stxssp 16 0000000000000000 0000000000000000 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & c
+stxssp 16 0000000000000000 0000000000000000 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & c
+stxssp 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+stxssp 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+stxssp 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+stxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+stxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 10
+stxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 10
+stxssp 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+stxssp 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+stxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 0
+stxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 0
+stxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 0
+stxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 0
+stxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 0
+stxssp 16 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 0
+stxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 4
+stxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 4
+stxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 4
+stxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 4
+stxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 4
+stxssp 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 4
+stxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 8
+stxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 8
+stxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 8
+stxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 8
+stxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 8
+stxssp 16 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 8
+stxssp 16 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & c
+stxssp 16 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & c
+stxssp 16 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & c
+stxssp 16 0102010201020102 0102030405060708 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & c
+stxssp 16 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & c
+stxssp 16 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & c
+stxssp 16 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 10
+stxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 10
+stxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 10
+stxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 10
+stxssp 16 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 10
+stxssp 16 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 10
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 0
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 0
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 0
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 0
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 0
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 0
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 4
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 4
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 4
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 4
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 4
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 4
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 8
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 8
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 8
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 8
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 8
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 8
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & c
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & c
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & c
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & c
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & c
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & c
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 10
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 10
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 10
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 10
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 10
+stxssp 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 10
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & c
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & c
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+stxssp 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+stxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 0
+stxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 0
+stxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 0
+stxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 0
+stxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 0
+stxssp 16 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 0
+stxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 4
+stxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 4
+stxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 4
+stxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 4
+stxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 4
+stxssp 16 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 4
+stxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 8
+stxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 8
+stxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 8
+stxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 8
+stxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 8
+stxssp 16 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 8
+stxssp 16 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c
+stxssp 16 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c
+stxssp 16 0000100800001010 0000100000001002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & c
+stxssp 16 0000100800001010 0000100000001002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & c
+stxssp 16 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c
+stxssp 16 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c
+stxssp 16 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 10
+stxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 10
+stxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 10
+stxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 10
+stxssp 16 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 10
+stxssp 16 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 10
+stxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 0
+stxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
+stxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 0
+stxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 0
+stxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 0
+stxssp 16 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
+stxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 4
+stxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 4
+stxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 4
+stxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 4
+stxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 4
+stxssp 16 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 4
+stxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 8
+stxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 8
+stxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 8
+stxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 8
+stxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 8
+stxssp 16 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 8
+stxssp 16 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c
+stxssp 16 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c
+stxssp 16 0010100800101010 0010100000101002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & c
+stxssp 16 0010100800101010 0010100000101002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & c
+stxssp 16 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c
+stxssp 16 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c
+stxssp 16 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+stxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
+stxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 10
+stxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 10
+stxssp 16 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+stxssp 16 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxssp 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxssp 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxssp 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxssp 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
+
+lxv 0 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 0
+lxv 0 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 0
+lxv 0 0000000000000000 0000000000000000 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 0
+lxv 0 0000000000000000 0000000000000000 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 0
+lxv 0 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 0
+lxv 0 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 0
+lxv 0 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 0 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 4
+lxv 0 0000000000000000 0000000000000000 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 4
+lxv 0 0000000000000000 0000000000000000 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 0 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 0 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 4
+lxv 0 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 0 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
+lxv 0 0000000000000000 0000000000000000 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 8
+lxv 0 0000000000000000 0000000000000000 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 0 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 0 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
+lxv 0 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 0 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & c
+lxv 0 0000000000000000 0000000000000000 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & c
+lxv 0 0000000000000000 0000000000000000 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & c
+lxv 0 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 0 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & c
+lxv 0 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 0 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 10
+lxv 0 0000000000000000 0000000000000000 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 10
+lxv 0 0000000000000000 0000000000000000 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 0 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 0 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 10
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+lxv 0 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 0
+lxv 0 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 0
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+lxv 0 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 4
+lxv 0 0102010201020102 0102030405060708 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 4
+lxv 0 0102010201020102 0102030405060708 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 0 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 0 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 4
+lxv 0 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 0 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
+lxv 0 0102010201020102 0102030405060708 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 8
+lxv 0 0102010201020102 0102030405060708 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 0 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 0 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
+lxv 0 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 0 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & c
+lxv 0 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & c
+lxv 0 0102010201020102 0102030405060708 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & c
+lxv 0 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 0 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & c
+lxv 0 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 0 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 10
+lxv 0 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 10
+lxv 0 0102010201020102 0102030405060708 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 0 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 0 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 10
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+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 4
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 4
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 4
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 8
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
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+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & c
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & c
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & c
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & c
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+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 10
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 10
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 0 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 10
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+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 4
+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 4
+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 4
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+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
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+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
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+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & c
+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & c
+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & c
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+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 10
+lxv 0 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 10
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+lxv 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 4
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+lxv 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 5555555555555555 0001020304050607 & 8
+lxv 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 5555555555555555 & 8
+lxv 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0001020304050607 ffffffffffffffff & 8
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+stxv 0 0010100800101010 0010100000101002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 10
+stxv 0 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+stxv 0 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
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+stxv 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
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+stxv 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxv 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxv 0 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
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+stxv 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+stxv 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & c
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+stxv 0 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxv 0 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+stxv 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxv 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxv 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxv 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxv 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxv 0 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
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+stxv 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxv 0 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
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+stxv 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxv 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxv 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 4
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+stxv 0 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
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+stxv 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 8
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+stxv 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxv 0 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 8
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+stxv 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxv 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxv 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxv 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxv 0 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 10
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+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxv 0 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
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+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 0
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+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
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+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxv 0 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
+
+lxv 16 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 0
+lxv 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 0
+lxv 16 0000000000000000 0000000000000000 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 0
+lxv 16 0000000000000000 0000000000000000 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 0
+lxv 16 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 0
+lxv 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 0
+lxv 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 4
+lxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 4
+lxv 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 4
+lxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 8
+lxv 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 0000000000000000 0000000000000000 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 16 0000000000000000 0000000000000000 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & c
+lxv 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 16 0000000000000000 0000000000000000 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 16 0000000000000000 0000000000000000 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 10
+lxv 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 0
+lxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 0
+lxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 0
+lxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 0
+lxv 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 0
+lxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 0
+lxv 16 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 4
+lxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 4
+lxv 16 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 4
+lxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 16 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 0102010201020102 0102030405060708 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 16 0102010201020102 0102030405060708 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 8
+lxv 16 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 16 0102010201020102 0102030405060708 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & c
+lxv 16 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 16 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 16 0102010201020102 0102030405060708 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 10
+lxv 16 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
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+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 4
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+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
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+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 8
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & c
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 10
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
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+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 0
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 0
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+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 4
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 4
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 8
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & c
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 10
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
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+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 4
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 4
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
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+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 8
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & c
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 10
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 0
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+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 0
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 0
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+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 4
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 4
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 4
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 4
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 8
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 8
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 8
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 8
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & c
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & c
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & c
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & c
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0001020304050607 ffffffffffffffff & 10
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 5555555555555555 0001020304050607 & 10
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 5555555555555555 & 10
+lxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> ffffffffffffffff 0000000000000000 & 10
+
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+stxv 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxv 16 0000000000000000 0000000000000000 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 0
+stxv 16 0000000000000000 0000000000000000 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 0
+stxv 16 0000000000000000 0000000000000000 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 0
+stxv 16 0000000000000000 0000000000000000 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 0
+stxv 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+stxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+stxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 4
+stxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 4
+stxv 16 0000000000000000 0000000000000000 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 4
+stxv 16 0000000000000000 0000000000000000 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 4
+stxv 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+stxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+stxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 8
+stxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 8
+stxv 16 0000000000000000 0000000000000000 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 8
+stxv 16 0000000000000000 0000000000000000 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 8
+stxv 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+stxv 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+stxv 16 0000000000000000 0000000000000000 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & c
+stxv 16 0000000000000000 0000000000000000 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & c
+stxv 16 0000000000000000 0000000000000000 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & c
+stxv 16 0000000000000000 0000000000000000 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & c
+stxv 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+stxv 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+stxv 16 0000000000000000 0000000000000000 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000000000000000 0000000000000000 & 10
+stxv 16 0000000000000000 0000000000000000 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000000000000000 0000000000000000 & 10
+stxv 16 0000000000000000 0000000000000000 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000000000000000 0000000000000000 & 10
+stxv 16 0000000000000000 0000000000000000 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000000000000000 0000000000000000 & 10
+stxv 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 0
+stxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 0
+stxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 0
+stxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 0
+stxv 16 0102010201020102 0102030405060708 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 0
+stxv 16 0102010201020102 0102030405060708 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 0
+stxv 16 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 4
+stxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 4
+stxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 4
+stxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 4
+stxv 16 0102010201020102 0102030405060708 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 4
+stxv 16 0102010201020102 0102030405060708 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 4
+stxv 16 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 8
+stxv 16 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 8
+stxv 16 0102010201020102 0102030405060708 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 8
+stxv 16 0102010201020102 0102030405060708 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 8
+stxv 16 0102010201020102 0102030405060708 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 8
+stxv 16 0102010201020102 0102030405060708 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 8
+stxv 16 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & c
+stxv 16 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & c
+stxv 16 0102010201020102 0102030405060708 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & c
+stxv 16 0102010201020102 0102030405060708 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & c
+stxv 16 0102010201020102 0102030405060708 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & c
+stxv 16 0102010201020102 0102030405060708 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & c
+stxv 16 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 10
+stxv 16 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 10
+stxv 16 0102010201020102 0102030405060708 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0102030405060708 0102010201020102 & 10
+stxv 16 0102010201020102 0102030405060708 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0102030405060708 0102010201020102 & 10
+stxv 16 0102010201020102 0102030405060708 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0102030405060708 0102010201020102 & 10
+stxv 16 0102010201020102 0102030405060708 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0102030405060708 0102010201020102 & 10
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 0
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 0
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 0
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 0
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 0
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 0
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 4
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 4
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 4
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 4
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 4
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 4
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 8
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 8
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 8
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 8
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 8
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 8
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & c
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & c
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & c
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & c
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & c
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & c
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 10
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 10
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0011223344556677 8899aabbccddeeff & 10
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0011223344556677 8899aabbccddeeff & 10
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0011223344556677 8899aabbccddeeff & 10
+stxv 16 8899aabbccddeeff 0011223344556677 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0011223344556677 8899aabbccddeeff & 10
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 0
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 4
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 8
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & c
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & c
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & c
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+stxv 16 7060504030201000 f0e0d0c0b0a09080 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> f0e0d0c0b0a09080 7060504030201000 & 10
+stxv 16 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 0
+stxv 16 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 0
+stxv 16 0000100800001010 0000100000001002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 0
+stxv 16 0000100800001010 0000100000001002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 0
+stxv 16 0000100800001010 0000100000001002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 0
+stxv 16 0000100800001010 0000100000001002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 0
+stxv 16 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 4
+stxv 16 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 4
+stxv 16 0000100800001010 0000100000001002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 4
+stxv 16 0000100800001010 0000100000001002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 4
+stxv 16 0000100800001010 0000100000001002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 4
+stxv 16 0000100800001010 0000100000001002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 4
+stxv 16 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 8
+stxv 16 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 8
+stxv 16 0000100800001010 0000100000001002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 8
+stxv 16 0000100800001010 0000100000001002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 8
+stxv 16 0000100800001010 0000100000001002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 8
+stxv 16 0000100800001010 0000100000001002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 8
+stxv 16 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c
+stxv 16 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c
+stxv 16 0000100800001010 0000100000001002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & c
+stxv 16 0000100800001010 0000100000001002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & c
+stxv 16 0000100800001010 0000100000001002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & c
+stxv 16 0000100800001010 0000100000001002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & c
+stxv 16 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 10
+stxv 16 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 10
+stxv 16 0000100800001010 0000100000001002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0000100000001002 0000100800001010 & 10
+stxv 16 0000100800001010 0000100000001002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0000100000001002 0000100800001010 & 10
+stxv 16 0000100800001010 0000100000001002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0000100000001002 0000100800001010 & 10
+stxv 16 0000100800001010 0000100000001002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0000100000001002 0000100800001010 & 10
+stxv 16 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 0
+stxv 16 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
+stxv 16 0010100800101010 0010100000101002 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 0
+stxv 16 0010100800101010 0010100000101002 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 0
+stxv 16 0010100800101010 0010100000101002 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 0
+stxv 16 0010100800101010 0010100000101002 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 0
+stxv 16 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 4
+stxv 16 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 4
+stxv 16 0010100800101010 0010100000101002 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 4
+stxv 16 0010100800101010 0010100000101002 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 4
+stxv 16 0010100800101010 0010100000101002 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 4
+stxv 16 0010100800101010 0010100000101002 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 4
+stxv 16 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 8
+stxv 16 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 8
+stxv 16 0010100800101010 0010100000101002 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 8
+stxv 16 0010100800101010 0010100000101002 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 8
+stxv 16 0010100800101010 0010100000101002 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 8
+stxv 16 0010100800101010 0010100000101002 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 8
+stxv 16 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c
+stxv 16 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c
+stxv 16 0010100800101010 0010100000101002 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & c
+stxv 16 0010100800101010 0010100000101002 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & c
+stxv 16 0010100800101010 0010100000101002 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & c
+stxv 16 0010100800101010 0010100000101002 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & c
+stxv 16 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+stxv 16 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
+stxv 16 0010100800101010 0010100000101002 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 0010100000101002 0010100800101010 & 10
+stxv 16 0010100800101010 0010100000101002 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 0010100000101002 0010100800101010 & 10
+stxv 16 0010100800101010 0010100000101002 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 0010100000101002 0010100800101010 & 10
+stxv 16 0010100800101010 0010100000101002 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 0010100000101002 0010100800101010 & 10
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 0
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 4
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 8
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & c
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & c
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxv 16 00001c0800001c10 00001c0000001c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001c0000001c02 00001c0800001c10 & 10
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 0
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 4
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 8
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & c
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & c
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxv 16 00101c0800101c10 00101c0000101c02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101c0000101c02 00101c0800101c10 & 10
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 0
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 4
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 8
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & c
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & c
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxv 16 00001f0800001f10 00001f0000001f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00001f0000001f02 00001f0800001f10 & 10
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 0 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 0
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 4 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 4
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x 8 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 8
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & c
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x c [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & c
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]=> 00101f0000101f02 00101f0800101f10 & 10
+stxv 16 00101f0800101f10 00101f0000101f02 l = 0x10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]=> 00101f0000101f02 00101f0800101f10 & 10
+
+All done. Tested 128 different instructions
+ppc vector load/store:
+Test instruction group [ppc vector load/store]
+lxvx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0102010201020102 0102030405060708 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 8899aabbccddeeff 0011223344556677 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 7060504030201000 f0e0d0c0b0a09080 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0000100800001010 0000100000001002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0010100800101010 0010100000101002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 00001c0800001c10 00001c0000001c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 00101c0800101c10 00101c0000101c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 00001f0800001f10 00001f0000001f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 00101f0800101f10 00101f0000101f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvx 0001020304050607 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 0000000000000000 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvx 5555555555555555 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 ffffffffffffffff [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvx 0000000000000000 ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff 0001020304050607 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvx ffffffffffffffff 0001020304050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0001020304050607 5555555555555555 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0405060704050607 0405060704050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvwsx 5555555555555555 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0102010201020102 0102030405060708 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0405060704050607 0405060704050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvwsx 5555555555555555 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 8899aabbccddeeff 0011223344556677 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0405060704050607 0405060704050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvwsx 5555555555555555 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 7060504030201000 f0e0d0c0b0a09080 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0405060704050607 0405060704050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvwsx 5555555555555555 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0000100800001010 0000100000001002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0405060704050607 0405060704050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvwsx 5555555555555555 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0010100800101010 0010100000101002 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0405060704050607 0405060704050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvwsx 5555555555555555 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 00001c0800001c10 00001c0000001c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0405060704050607 0405060704050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
+lxvwsx 5555555555555555 5555555555555555 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ] =>
+ 0000000000000000 0000000000000000 [ 0000000000000000 ffffffffffffffff 0001020304050607 5555555555555555 ]
+lxvwsx 0000000000000000 0000000000000000 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 00101c0800101c10 00101c0000101c02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ ffffffffffffffff ffffffffffffffff [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ]
+lxvwsx ffffffffffffffff ffffffffffffffff [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 0405060704050607 0405060704050607 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ]
+lxvwsx 0405060704050607 0405060704050607 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ] =>
+ 5555555555555555 5555555555555555 [ 5555555555555555 0000000000000000 ffffffffffffffff 0001020304050607 ]
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+ 00101f0800101f10 00101f0000101f02 [ 101f1000081f1000 021f1000001f1000 0001020304050607 5555555555555555 ]
+stxvb16x 00101f0800101f10 00101f0000101f02 [ ffffffffffffffff 0001020304050607 5555555555555555 0000000000000000 ] =>
+ 00101f0000101f02 00101f0800101f10 [ 021f1000001f1000 101f1000081f1000 5555555555555555 0000000000000000 ]
+stxvb16x 00101f0000101f02 00101f0800101f10 [ 0001020304050607 5555555555555555 0000000000000000 ffffffffffffffff ] =>
+ 00101f0800101f10 00101f0000101f02 [ 101f1000081f1000 021f1000001f1000 0000000000000000 ffffffffffffffff ]
+
+All done. Tested 135 different instructions
+ppc vector scalar compare exponents doubles:
+Test instruction group [ppc vector scalar compare exponents doubles]
+xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+
+All done. Tested 136 different instructions
+ppc vector scalar test data class tests:
+Test instruction group [ppc vector scalar test data class tests]
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+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 DCMX=[-inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 DCMX=[-inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => ffffffffffffffff, ffffffffffffffff
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, ffffffff00000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, ffffffff00000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, ffffffffffffffff
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, ffffffff00000000
+xvtstdcsp 0000000000000000, 8000000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, ffffffff00000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, ffffffff00000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, ffffffffffffffff
+
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => ffffffffffffffff, ffffffffffffffff
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, ffffffffffffffff
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, ffffffffffffffff
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 0000000000000000, 8000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, ffffffffffffffff
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, ffffffffffffffff
+
+All done. Tested 141 different instructions
+ppc vector scalar tests against float double two args :
+Test instruction group [ppc vector scalar tests against float double two args ]
+xsiexpdp r14 = 0x0, r15 = 0x0 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x7fffffffffff 0000000000000000 ffff7fffffffffff => 7ff0000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0xff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0xff07fffffffffff 0000000000000000 ffff7fffffffffff => 7ff0000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 7ff0000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 7ff0000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x8000000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x80007fffffffffff 0000000000000000 ffff7fffffffffff => 7ff0000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x8ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x8ff07fffffffffff 0000000000000000 ffff7fffffffffff => 7ff0000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => 7ff0000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => 7ff0000000000000 0000000000000000
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0x0 0000000000000000 ffff7fffffffffff => 00007fffffffffff 0000000000000000
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0x7fffffffffff 0000000000000000 ffff7fffffffffff => 7ff07fffffffffff 0000000000000000
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0xff0000000000000 0000000000000000 ffff7fffffffffff => 00007fffffffffff 0000000000000000
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0xff07fffffffffff 0000000000000000 ffff7fffffffffff => 7ff07fffffffffff 0000000000000000
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 00007fffffffffff 0000000000000000
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 7ff07fffffffffff 0000000000000000
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 00007fffffffffff 0000000000000000
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 7ff07fffffffffff 0000000000000000
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0x8000000000000000 0000000000000000 ffff7fffffffffff => 00007fffffffffff 0000000000000000
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0x80007fffffffffff 0000000000000000 ffff7fffffffffff => 7ff07fffffffffff 0000000000000000
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+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 8000000000000000 0000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => fff0000000000000 0000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x8000000000000000 0000000000000000 ffff7fffffffffff => 8000000000000000 0000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x80007fffffffffff 0000000000000000 ffff7fffffffffff => fff0000000000000 0000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x8ff0000000000000 0000000000000000 ffff7fffffffffff => 8000000000000000 0000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x8ff07fffffffffff 0000000000000000 ffff7fffffffffff => fff0000000000000 0000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 8000000000000000 0000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => fff0000000000000 0000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 8000000000000000 0000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => fff0000000000000 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x0 0000000000000000 ffff7fffffffffff => 80007fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7fffffffffff 0000000000000000 ffff7fffffffffff => fff07fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xff0000000000000 0000000000000000 ffff7fffffffffff => 80007fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xff07fffffffffff 0000000000000000 ffff7fffffffffff => fff07fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 80007fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => fff07fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 80007fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => fff07fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x8000000000000000 0000000000000000 ffff7fffffffffff => 80007fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x80007fffffffffff 0000000000000000 ffff7fffffffffff => fff07fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x8ff0000000000000 0000000000000000 ffff7fffffffffff => 80007fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x8ff07fffffffffff 0000000000000000 ffff7fffffffffff => fff07fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 80007fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => fff07fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 80007fffffffffff 0000000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => fff07fffffffffff 0000000000000000
+
+xscvhpdp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => fffffc0000000000 0000000000000000 FPRF-C FPCC-FU
+xscvhpdp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x1ff000001ff0000 fffffe00fffffe00 01ff000001ff0000 => fff8000000000000 0000000000000000 FPRF-C FPCC-FU
+xscvhpdp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e000000 ffffffffffffffff 7e0000007e000000 => fffffc0000000000 0000000000000000 FPRF-C FPCC-FU
+xscvhpdp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff00007fff0000 fffffe00fffffe00 7fff00007fff0000 => fff8000000000000 0000000000000000 FPRF-C FPCC-FU
+xscvhpdp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e000000 ffffffffffffffff 7e0000007e000000 => fffffc0000000000 0000000000000000 FPRF-C FPCC-FU
+xscvhpdp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff00007fff0000 fffffe00fffffe00 7fff00007fff0000 => fff8000000000000 0000000000000000 FPRF-C FPCC-FU
+xscvhpdp vec_xb[1] = 0xffff81ffffff81ff, vec_xb[0] = 0x7e0000007e000000 ffff81ffffff81ff 7e0000007e000000 => befff00000000000 0000000000000000 FPCC-FL
+xscvhpdp vec_xb[1] = 0xffff8000ffff8000, vec_xb[0] = 0x7fff00007fff0000 ffff8000ffff8000 7fff00007fff0000 => 8000000000000000 0000000000000000 FPRF-C FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0x8000000080000000 ffff7fffffff7fff 8000000080000000 => 7ffffc0000000000 0000000000000000 FPRF-C FPCC-FU
+xscvhpdp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0x81ff000081ff0000 ffff7e00ffff7e00 81ff000081ff0000 => 7ff8000000000000 0000000000000000 FPRF-C FPCC-FU
+xscvhpdp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe000000fe000000 ffff7fffffff7fff fe000000fe000000 => 7ffffc0000000000 0000000000000000 FPRF-C FPCC-FU
+xscvhpdp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff0000ffff0000 ffff7e00ffff7e00 ffff0000ffff0000 => 7ff8000000000000 0000000000000000 FPRF-C FPCC-FU
+xscvhpdp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe000000fe000000 ffff7fffffff7fff fe000000fe000000 => 7ffffc0000000000 0000000000000000 FPRF-C FPCC-FU
+xscvhpdp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff0000ffff0000 ffff7e00ffff7e00 ffff0000ffff0000 => 7ff8000000000000 0000000000000000 FPRF-C FPCC-FU
+xscvhpdp vec_xb[1] = 0xffff01ffffff01ff, vec_xb[0] = 0xfe000000fe000000 ffff01ffffff01ff fe000000fe000000 => 3efff00000000000 0000000000000000 FPCC-FG
+xscvhpdp vec_xb[1] = 0xffff0000ffff0000, vec_xb[0] = 0xffff0000ffff0000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 0000000000000000 FPCC-FE
+
+xscvdphp r14 = 0x0, r15 = 0x0 ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7ff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7ff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7ff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7ff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x8000000000000000 ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x80007fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x8ff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x8ff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xfff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xfff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xfff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xfff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 000000000000ffc0 0000000000000000 FPRF-C FPCC-FU
+
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => ffffe000ffffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x1ff000001ff0000 fffffe00fffffe00 01ff000001ff0000 => ffc00000ffc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e000000 ffffffffffffffff 7e0000007e000000 => ffffe000ffffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff00007fff0000 fffffe00fffffe00 7fff00007fff0000 => ffc00000ffc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e000000 ffffffffffffffff 7e0000007e000000 => ffffe000ffffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff00007fff0000 fffffe00fffffe00 7fff00007fff0000 => ffc00000ffc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff81ffffff81ff, vec_xb[0] = 0x7e0000007e000000 ffff81ffffff81ff 7e0000007e000000 => b7ff8000b7ff8000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff8000ffff8000, vec_xb[0] = 0x7fff00007fff0000 ffff8000ffff8000 7fff00007fff0000 => 8000000080000000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0x8000000080000000 ffff7fffffff7fff 8000000080000000 => 7fffe0007fffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0x81ff000081ff0000 ffff7e00ffff7e00 81ff000081ff0000 => 7fc000007fc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe000000fe000000 ffff7fffffff7fff fe000000fe000000 => 7fffe0007fffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff0000ffff0000 ffff7e00ffff7e00 ffff0000ffff0000 => 7fc000007fc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe000000fe000000 ffff7fffffff7fff fe000000fe000000 => 7fffe0007fffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff0000ffff0000 ffff7e00ffff7e00 ffff0000ffff0000 => 7fc000007fc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff01ffffff01ff, vec_xb[0] = 0xfe000000fe000000 ffff01ffffff01ff fe000000fe000000 => 37ff800037ff8000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff0000, vec_xb[0] = 0xffff0000ffff0000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x1ff000001ff fe00fffffe00ffff 000001ff000001ff => ffffe000ffffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x1ff01ff01ff01ff fe00fe00fe00fe00 01ff01ff01ff01ff => ffc00000ffc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e0001ff7e0001ff fe00fffffe00ffff 7e0001ff7e0001ff => ffffe000ffffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff01ff7fff01ff fe00fe00fe00fe00 7fff01ff7fff01ff => ffc00000ffc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e0001ff7e0001ff fe00fffffe00ffff 7e0001ff7e0001ff => ffffe000ffffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff01ff7fff01ff fe00fe00fe00fe00 7fff01ff7fff01ff => ffc00000ffc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe0081fffe0081ff, vec_xb[0] = 0x7e0001ff7e0001ff fe0081fffe0081ff 7e0001ff7e0001ff => b7ff8000b7ff8000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe008000fe008000, vec_xb[0] = 0x7fff01ff7fff01ff fe008000fe008000 7fff01ff7fff01ff => 8000000080000000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0x800001ff800001ff fe007ffffe007fff 800001ff800001ff => 7fffe0007fffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0x81ff01ff81ff01ff fe007e00fe007e00 81ff01ff81ff01ff => 7fc000007fc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe0001fffe0001ff fe007ffffe007fff fe0001fffe0001ff => 7fffe0007fffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff01ffffff01ff fe007e00fe007e00 ffff01ffffff01ff => 7fc000007fc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe0001fffe0001ff fe007ffffe007fff fe0001fffe0001ff => 7fffe0007fffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff01ffffff01ff fe007e00fe007e00 ffff01ffffff01ff => 7fc000007fc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe0001fffe0001ff, vec_xb[0] = 0xfe0001fffe0001ff fe0001fffe0001ff fe0001fffe0001ff => 37ff800037ff8000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe000000fe000000, vec_xb[0] = 0xffff01ffffff01ff fe000000fe000000 ffff01ffffff01ff => 0000000000000000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e00 ffffffffffffffff 00007e0000007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x1ff7e0001ff7e00 fffffe00fffffe00 01ff7e0001ff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e007e007e007e00 ffffffffffffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff7e007fff7e00 fffffe00fffffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e007e007e007e00 ffffffffffffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff7e007fff7e00 fffffe00fffffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff81ffffff81ff, vec_xb[0] = 0x7e007e007e007e00 ffff81ffffff81ff 7e007e007e007e00 => b7ff8000b7ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff8000ffff8000, vec_xb[0] = 0x7fff7e007fff7e00 ffff8000ffff8000 7fff7e007fff7e00 => 8000000080000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0x80007e0080007e00 ffff7fffffff7fff 80007e0080007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0x81ff7e0081ff7e00 ffff7e00ffff7e00 81ff7e0081ff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe007e00fe007e00 ffff7fffffff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff7e00ffff7e00 ffff7e00ffff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe007e00fe007e00 ffff7fffffff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff7e00ffff7e00 ffff7e00ffff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff01ffffff01ff, vec_xb[0] = 0xfe007e00fe007e00 ffff01ffffff01ff fe007e00fe007e00 => 37ff800037ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff0000, vec_xb[0] = 0xffff7e00ffff7e00 ffff0000ffff0000 ffff7e00ffff7e00 => 0000000000000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7fff00007fff fe00fffffe00ffff 00007fff00007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x1ff7fff01ff7fff fe00fe00fe00fe00 01ff7fff01ff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e007fff7e007fff fe00fffffe00ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff7fff7fff7fff fe00fe00fe00fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e007fff7e007fff fe00fffffe00ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff7fff7fff7fff fe00fe00fe00fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe0081fffe0081ff, vec_xb[0] = 0x7e007fff7e007fff fe0081fffe0081ff 7e007fff7e007fff => b7ff8000b7ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe008000fe008000, vec_xb[0] = 0x7fff7fff7fff7fff fe008000fe008000 7fff7fff7fff7fff => 8000000080000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0x80007fff80007fff fe007ffffe007fff 80007fff80007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0x81ff7fff81ff7fff fe007e00fe007e00 81ff7fff81ff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe007ffffe007fff fe007ffffe007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff7fffffff7fff fe007e00fe007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe007ffffe007fff fe007ffffe007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff7fffffff7fff fe007e00fe007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe0001fffe0001ff, vec_xb[0] = 0xfe007ffffe007fff fe0001fffe0001ff fe007ffffe007fff => 37ff800037ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe000000, vec_xb[0] = 0xffff7fffffff7fff fe000000fe000000 ffff7fffffff7fff => 0000000000000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e00 ffffffffffffffff 00007e0000007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x1ff7e0001ff7e00 fffffe00fffffe00 01ff7e0001ff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e007e007e007e00 ffffffffffffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff7e007fff7e00 fffffe00fffffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e007e007e007e00 ffffffffffffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff7e007fff7e00 fffffe00fffffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff81ffffff81ff, vec_xb[0] = 0x7e007e007e007e00 ffff81ffffff81ff 7e007e007e007e00 => b7ff8000b7ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff8000ffff8000, vec_xb[0] = 0x7fff7e007fff7e00 ffff8000ffff8000 7fff7e007fff7e00 => 8000000080000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0x80007e0080007e00 ffff7fffffff7fff 80007e0080007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0x81ff7e0081ff7e00 ffff7e00ffff7e00 81ff7e0081ff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe007e00fe007e00 ffff7fffffff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff7e00ffff7e00 ffff7e00ffff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe007e00fe007e00 ffff7fffffff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff7e00ffff7e00 ffff7e00ffff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff01ffffff01ff, vec_xb[0] = 0xfe007e00fe007e00 ffff01ffffff01ff fe007e00fe007e00 => 37ff800037ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff0000, vec_xb[0] = 0xffff7e00ffff7e00 ffff0000ffff0000 ffff7e00ffff7e00 => 0000000000000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7fff00007fff fe00fffffe00ffff 00007fff00007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x1ff7fff01ff7fff fe00fe00fe00fe00 01ff7fff01ff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e007fff7e007fff fe00fffffe00ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff7fff7fff7fff fe00fe00fe00fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e007fff7e007fff fe00fffffe00ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff7fff7fff7fff fe00fe00fe00fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe0081fffe0081ff, vec_xb[0] = 0x7e007fff7e007fff fe0081fffe0081ff 7e007fff7e007fff => b7ff8000b7ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe008000fe008000, vec_xb[0] = 0x7fff7fff7fff7fff fe008000fe008000 7fff7fff7fff7fff => 8000000080000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0x80007fff80007fff fe007ffffe007fff 80007fff80007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0x81ff7fff81ff7fff fe007e00fe007e00 81ff7fff81ff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe007ffffe007fff fe007ffffe007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff7fffffff7fff fe007e00fe007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe007ffffe007fff fe007ffffe007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff7fffffff7fff fe007e00fe007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe0001fffe0001ff, vec_xb[0] = 0xfe007ffffe007fff fe0001fffe0001ff fe007ffffe007fff => 37ff800037ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe000000, vec_xb[0] = 0xffff7fffffff7fff fe000000fe000000 ffff7fffffff7fff => 0000000000000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x81ffffff81ffffff, vec_xb[0] = 0x7e0000007e00 81ffffff81ffffff 00007e0000007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81fffe0081fffe00, vec_xb[0] = 0x1ff7e0001ff7e00 81fffe0081fffe00 01ff7e0001ff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ffffff81ffffff, vec_xb[0] = 0x7e007e007e007e00 81ffffff81ffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81fffe0081fffe00, vec_xb[0] = 0x7fff7e007fff7e00 81fffe0081fffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ffffff81ffffff, vec_xb[0] = 0x7e007e007e007e00 81ffffff81ffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81fffe0081fffe00, vec_xb[0] = 0x7fff7e007fff7e00 81fffe0081fffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff81ff81ff81ff, vec_xb[0] = 0x7e007e007e007e00 81ff81ff81ff81ff 7e007e007e007e00 => b7ff8000b7ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff800081ff8000, vec_xb[0] = 0x7fff7e007fff7e00 81ff800081ff8000 7fff7e007fff7e00 => 8000000080000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7fff81ff7fff, vec_xb[0] = 0x80007e0080007e00 81ff7fff81ff7fff 80007e0080007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7e0081ff7e00, vec_xb[0] = 0x81ff7e0081ff7e00 81ff7e0081ff7e00 81ff7e0081ff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7fff81ff7fff, vec_xb[0] = 0xfe007e00fe007e00 81ff7fff81ff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7e0081ff7e00, vec_xb[0] = 0xffff7e00ffff7e00 81ff7e0081ff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7fff81ff7fff, vec_xb[0] = 0xfe007e00fe007e00 81ff7fff81ff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7e0081ff7e00, vec_xb[0] = 0xffff7e00ffff7e00 81ff7e0081ff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff01ff81ff01ff, vec_xb[0] = 0xfe007e00fe007e00 81ff01ff81ff01ff fe007e00fe007e00 => 37ff800037ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff000081ff0000, vec_xb[0] = 0xffff7e00ffff7e00 81ff000081ff0000 ffff7e00ffff7e00 => 0000000000000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x8000ffff8000ffff, vec_xb[0] = 0x7fff00007fff 8000ffff8000ffff 00007fff00007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000fe008000fe00, vec_xb[0] = 0x1ff7fff01ff7fff 8000fe008000fe00 01ff7fff01ff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000ffff8000ffff, vec_xb[0] = 0x7e007fff7e007fff 8000ffff8000ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000fe008000fe00, vec_xb[0] = 0x7fff7fff7fff7fff 8000fe008000fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000ffff8000ffff, vec_xb[0] = 0x7e007fff7e007fff 8000ffff8000ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000fe008000fe00, vec_xb[0] = 0x7fff7fff7fff7fff 8000fe008000fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x800081ff800081ff, vec_xb[0] = 0x7e007fff7e007fff 800081ff800081ff 7e007fff7e007fff => b7ff8000b7ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000800080008000, vec_xb[0] = 0x7fff7fff7fff7fff 8000800080008000 7fff7fff7fff7fff => 8000000080000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007fff80007fff, vec_xb[0] = 0x80007fff80007fff 80007fff80007fff 80007fff80007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007e0080007e00, vec_xb[0] = 0x81ff7fff81ff7fff 80007e0080007e00 81ff7fff81ff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007fff80007fff, vec_xb[0] = 0xfe007ffffe007fff 80007fff80007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007e0080007e00, vec_xb[0] = 0xffff7fffffff7fff 80007e0080007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007fff80007fff, vec_xb[0] = 0xfe007ffffe007fff 80007fff80007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007e0080007e00, vec_xb[0] = 0xffff7fffffff7fff 80007e0080007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x800001ff800001ff, vec_xb[0] = 0xfe007ffffe007fff 800001ff800001ff fe007ffffe007fff => 37ff800037ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000000080000000, vec_xb[0] = 0xffff7fffffff7fff 8000000080000000 ffff7fffffff7fff => 0000000000000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x800000008000 7fffffff7fffffff 0000800000008000 => ffffe000ffffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x1ff800001ff8000 7ffffe007ffffe00 01ff800001ff8000 => ffc00000ffc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e0080007e008000 7fffffff7fffffff 7e0080007e008000 => ffffe000ffffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7fff80007fff8000 7ffffe007ffffe00 7fff80007fff8000 => ffc00000ffc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e0080007e008000 7fffffff7fffffff 7e0080007e008000 => ffffe000ffffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7fff80007fff8000 7ffffe007ffffe00 7fff80007fff8000 => ffc00000ffc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff81ff7fff81ff, vec_xb[0] = 0x7e0080007e008000 7fff81ff7fff81ff 7e0080007e008000 => b7ff8000b7ff8000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff80007fff8000, vec_xb[0] = 0x7fff80007fff8000 7fff80007fff8000 7fff80007fff8000 => 8000000080000000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0x8000800080008000 7fff7fff7fff7fff 8000800080008000 => 7fffe0007fffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0x81ff800081ff8000 7fff7e007fff7e00 81ff800081ff8000 => 7fc000007fc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe008000fe008000 7fff7fff7fff7fff fe008000fe008000 => 7fffe0007fffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xffff8000ffff8000 7fff7e007fff7e00 ffff8000ffff8000 => 7fc000007fc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe008000fe008000 7fff7fff7fff7fff fe008000fe008000 => 7fffe0007fffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xffff8000ffff8000 7fff7e007fff7e00 ffff8000ffff8000 => 7fc000007fc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff01ff7fff01ff, vec_xb[0] = 0xfe008000fe008000 7fff01ff7fff01ff fe008000fe008000 => 37ff800037ff8000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff0000, vec_xb[0] = 0xffff8000ffff8000 7fff00007fff0000 ffff8000ffff8000 => 0000000000000000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x81ff000081ff 7e00ffff7e00ffff 000081ff000081ff => ffffe000ffffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x1ff81ff01ff81ff 7e00fe007e00fe00 01ff81ff01ff81ff => ffc00000ffc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e0081ff7e0081ff 7e00ffff7e00ffff 7e0081ff7e0081ff => ffffe000ffffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fff81ff7fff81ff 7e00fe007e00fe00 7fff81ff7fff81ff => ffc00000ffc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e0081ff7e0081ff 7e00ffff7e00ffff 7e0081ff7e0081ff => ffffe000ffffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fff81ff7fff81ff 7e00fe007e00fe00 7fff81ff7fff81ff => ffc00000ffc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e0081ff7e0081ff, vec_xb[0] = 0x7e0081ff7e0081ff 7e0081ff7e0081ff 7e0081ff7e0081ff => b7ff8000b7ff8000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e0080007e008000, vec_xb[0] = 0x7fff81ff7fff81ff 7e0080007e008000 7fff81ff7fff81ff => 8000000080000000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0x800081ff800081ff 7e007fff7e007fff 800081ff800081ff => 7fffe0007fffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0x81ff81ff81ff81ff 7e007e007e007e00 81ff81ff81ff81ff => 7fc000007fc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe0081fffe0081ff 7e007fff7e007fff fe0081fffe0081ff => 7fffe0007fffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffff81ffffff81ff 7e007e007e007e00 ffff81ffffff81ff => 7fc000007fc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe0081fffe0081ff 7e007fff7e007fff fe0081fffe0081ff => 7fffe0007fffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffff81ffffff81ff 7e007e007e007e00 ffff81ffffff81ff => 7fc000007fc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e0001ff7e0001ff, vec_xb[0] = 0xfe0081fffe0081ff 7e0001ff7e0001ff fe0081fffe0081ff => 37ff800037ff8000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e0000007e000000, vec_xb[0] = 0xffff81ffffff81ff 7e0000007e000000 ffff81ffffff81ff => 0000000000000000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xfe000000fe00 7fffffff7fffffff 0000fe000000fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x1fffe0001fffe00 7ffffe007ffffe00 01fffe0001fffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e00fe007e00fe00 7fffffff7fffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7ffffe007ffffe00 7ffffe007ffffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e00fe007e00fe00 7fffffff7fffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7ffffe007ffffe00 7ffffe007ffffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff81ff7fff81ff, vec_xb[0] = 0x7e00fe007e00fe00 7fff81ff7fff81ff 7e00fe007e00fe00 => b7ff8000b7ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff80007fff8000, vec_xb[0] = 0x7ffffe007ffffe00 7fff80007fff8000 7ffffe007ffffe00 => 8000000080000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0x8000fe008000fe00 7fff7fff7fff7fff 8000fe008000fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0x81fffe0081fffe00 7fff7e007fff7e00 81fffe0081fffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff7fff7fff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xfffffe00fffffe00 7fff7e007fff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff7fff7fff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xfffffe00fffffe00 7fff7e007fff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff01ff7fff01ff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff01ff7fff01ff fe00fe00fe00fe00 => 37ff800037ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff0000, vec_xb[0] = 0xfffffe00fffffe00 7fff00007fff0000 fffffe00fffffe00 => 0000000000000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0xffff0000ffff 7e00ffff7e00ffff 0000ffff0000ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x1ffffff01ffffff 7e00fe007e00fe00 01ffffff01ffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e00ffff7e00ffff 7e00ffff7e00ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fffffff7fffffff 7e00fe007e00fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e00ffff7e00ffff 7e00ffff7e00ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fffffff7fffffff 7e00fe007e00fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0081ff7e0081ff, vec_xb[0] = 0x7e00ffff7e00ffff 7e0081ff7e0081ff 7e00ffff7e00ffff => b7ff8000b7ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0080007e008000, vec_xb[0] = 0x7fffffff7fffffff 7e0080007e008000 7fffffff7fffffff => 8000000080000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0x8000ffff8000ffff 7e007fff7e007fff 8000ffff8000ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0x81ffffff81ffffff 7e007e007e007e00 81ffffff81ffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe00fffffe00ffff 7e007fff7e007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffffffffffffffff 7e007e007e007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe00fffffe00ffff 7e007fff7e007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffffffffffffffff 7e007e007e007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0001ff7e0001ff, vec_xb[0] = 0xfe00fffffe00ffff 7e0001ff7e0001ff fe00fffffe00ffff => 37ff800037ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e000000, vec_xb[0] = 0xffffffffffffffff 7e0000007e000000 ffffffffffffffff => 0000000000000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xfe000000fe00 7fffffff7fffffff 0000fe000000fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x1fffe0001fffe00 7ffffe007ffffe00 01fffe0001fffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e00fe007e00fe00 7fffffff7fffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7ffffe007ffffe00 7ffffe007ffffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e00fe007e00fe00 7fffffff7fffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7ffffe007ffffe00 7ffffe007ffffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff81ff7fff81ff, vec_xb[0] = 0x7e00fe007e00fe00 7fff81ff7fff81ff 7e00fe007e00fe00 => b7ff8000b7ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff80007fff8000, vec_xb[0] = 0x7ffffe007ffffe00 7fff80007fff8000 7ffffe007ffffe00 => 8000000080000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0x8000fe008000fe00 7fff7fff7fff7fff 8000fe008000fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0x81fffe0081fffe00 7fff7e007fff7e00 81fffe0081fffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff7fff7fff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xfffffe00fffffe00 7fff7e007fff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff7fff7fff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xfffffe00fffffe00 7fff7e007fff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff01ff7fff01ff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff01ff7fff01ff fe00fe00fe00fe00 => 37ff800037ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff0000, vec_xb[0] = 0xfffffe00fffffe00 7fff00007fff0000 fffffe00fffffe00 => 0000000000000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0xffff0000ffff 7e00ffff7e00ffff 0000ffff0000ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x1ffffff01ffffff 7e00fe007e00fe00 01ffffff01ffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e00ffff7e00ffff 7e00ffff7e00ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fffffff7fffffff 7e00fe007e00fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e00ffff7e00ffff 7e00ffff7e00ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fffffff7fffffff 7e00fe007e00fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0081ff7e0081ff, vec_xb[0] = 0x7e00ffff7e00ffff 7e0081ff7e0081ff 7e00ffff7e00ffff => b7ff8000b7ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0080007e008000, vec_xb[0] = 0x7fffffff7fffffff 7e0080007e008000 7fffffff7fffffff => 8000000080000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0x8000ffff8000ffff 7e007fff7e007fff 8000ffff8000ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0x81ffffff81ffffff 7e007e007e007e00 81ffffff81ffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe00fffffe00ffff 7e007fff7e007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffffffffffffffff 7e007e007e007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe00fffffe00ffff 7e007fff7e007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffffffffffffffff 7e007e007e007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0001ff7e0001ff, vec_xb[0] = 0xfe00fffffe00ffff 7e0001ff7e0001ff fe00fffffe00ffff => 37ff800037ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e000000, vec_xb[0] = 0xffffffffffffffff 7e0000007e000000 ffffffffffffffff => 0000000000000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x1ffffff01ffffff, vec_xb[0] = 0xfe000000fe00 01ffffff01ffffff 0000fe000000fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1fffe0001fffe00, vec_xb[0] = 0x1fffe0001fffe00 01fffe0001fffe00 01fffe0001fffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ffffff01ffffff, vec_xb[0] = 0x7e00fe007e00fe00 01ffffff01ffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1fffe0001fffe00, vec_xb[0] = 0x7ffffe007ffffe00 01fffe0001fffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ffffff01ffffff, vec_xb[0] = 0x7e00fe007e00fe00 01ffffff01ffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1fffe0001fffe00, vec_xb[0] = 0x7ffffe007ffffe00 01fffe0001fffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff81ff01ff81ff, vec_xb[0] = 0x7e00fe007e00fe00 01ff81ff01ff81ff 7e00fe007e00fe00 => b7ff8000b7ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff800001ff8000, vec_xb[0] = 0x7ffffe007ffffe00 01ff800001ff8000 7ffffe007ffffe00 => 8000000080000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7fff01ff7fff, vec_xb[0] = 0x8000fe008000fe00 01ff7fff01ff7fff 8000fe008000fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7e0001ff7e00, vec_xb[0] = 0x81fffe0081fffe00 01ff7e0001ff7e00 81fffe0081fffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7fff01ff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 01ff7fff01ff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7e0001ff7e00, vec_xb[0] = 0xfffffe00fffffe00 01ff7e0001ff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7fff01ff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 01ff7fff01ff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7e0001ff7e00, vec_xb[0] = 0xfffffe00fffffe00 01ff7e0001ff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff01ff01ff01ff, vec_xb[0] = 0xfe00fe00fe00fe00 01ff01ff01ff01ff fe00fe00fe00fe00 => 37ff800037ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff000001ff0000, vec_xb[0] = 0xfffffe00fffffe00 01ff000001ff0000 fffffe00fffffe00 => 0000000000000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff, vec_xb[0] = 0xffff0000ffff 0000ffff0000ffff 0000ffff0000ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe00, vec_xb[0] = 0x1ffffff01ffffff 0000fe000000fe00 01ffffff01ffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff, vec_xb[0] = 0x7e00ffff7e00ffff 0000ffff0000ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe00, vec_xb[0] = 0x7fffffff7fffffff 0000fe000000fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff, vec_xb[0] = 0x7e00ffff7e00ffff 0000ffff0000ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe00, vec_xb[0] = 0x7fffffff7fffffff 0000fe000000fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x81ff000081ff, vec_xb[0] = 0x7e00ffff7e00ffff 000081ff000081ff 7e00ffff7e00ffff => b7ff8000b7ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x800000008000, vec_xb[0] = 0x7fffffff7fffffff 0000800000008000 7fffffff7fffffff => 8000000080000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff, vec_xb[0] = 0x8000ffff8000ffff 00007fff00007fff 8000ffff8000ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e00, vec_xb[0] = 0x81ffffff81ffffff 00007e0000007e00 81ffffff81ffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff, vec_xb[0] = 0xfe00fffffe00ffff 00007fff00007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e00, vec_xb[0] = 0xffffffffffffffff 00007e0000007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff, vec_xb[0] = 0xfe00fffffe00ffff 00007fff00007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e00, vec_xb[0] = 0xffffffffffffffff 00007e0000007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x1ff000001ff, vec_xb[0] = 0xfe00fffffe00ffff 000001ff000001ff fe00fffffe00ffff => 37ff800037ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 ffffe000ffffe000
+
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x0 ffffffffff800000 0000000000000000 => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x0 ffffffffff800000 0000000000000000 => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x0 ffffffffff800000 0000000000000000 => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x0 ffffffff807fffff 0000000000000000 => 0000ffff00008000 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x0 ffffffff80000000 0000000000000000 => 0000ffff00008000 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x0 7fffffff7fffffff 0000000000000000 => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x0 7f8000007f800000 0000000000000000 => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x0 7fffffff7fffffff 0000000000000000 => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x0 7f8000007f800000 0000000000000000 => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x0 7fffffff7fffffff 0000000000000000 => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x0 7f8000007f800000 0000000000000000 => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x0 007fffff007fffff 0000000000000000 => 0000000000000000 0000000000000000
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x0 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffff007fffff ffffffffffffffff 007fffff007fffff => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffff007fffff ffffffffff800000 007fffff007fffff => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffff007fffff ffffffffffffffff 007fffff007fffff => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffff007fffff ffffffffff800000 007fffff007fffff => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffff007fffff ffffffffffffffff 007fffff007fffff => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffff007fffff ffffffffff800000 007fffff007fffff => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7fffff007fffff ffffffff807fffff 007fffff007fffff => 0000ffff00008000 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7fffff007fffff ffffffff80000000 007fffff007fffff => 0000ffff00008000 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffff007fffff 7fffffff7fffffff 007fffff007fffff => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffff007fffff 7f8000007f800000 007fffff007fffff => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffff007fffff 7fffffff7fffffff 007fffff007fffff => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffff007fffff 7f8000007f800000 007fffff007fffff => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffff007fffff 7fffffff7fffffff 007fffff007fffff => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffff007fffff 7f8000007f800000 007fffff007fffff => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7fffff007fffff 007fffff007fffff 007fffff007fffff => 0000000000000000 0000000000000000
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7fffff007fffff 0000000000000000 007fffff007fffff => 0000000000000000 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7f8000007f800000 ffffffff807fffff 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7f8000007f800000 ffffffff80000000 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7f8000007f800000 007fffff007fffff 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7f8000007f800000 0000000000000000 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7fffffff7fffffff ffffffff807fffff 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7fffffff7fffffff ffffffff80000000 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7fffffff7fffffff 007fffff007fffff 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7fffffff7fffffff 0000000000000000 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7f8000007f800000 ffffffff807fffff 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7f8000007f800000 ffffffff80000000 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7f8000007f800000 007fffff007fffff 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7f8000007f800000 0000000000000000 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7fffffff7fffffff ffffffff807fffff 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7fffffff7fffffff ffffffff80000000 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7fffffff7fffffff 007fffff007fffff 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7fffffff7fffffff 0000000000000000 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7f8000007f800000 ffffffff807fffff 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7f8000007f800000 ffffffff80000000 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7f8000007f800000 007fffff007fffff 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7f8000007f800000 0000000000000000 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7fffffff7fffffff ffffffff807fffff 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7fffffff7fffffff ffffffff80000000 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7fffffff7fffffff 007fffff007fffff 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7fffffff7fffffff 0000000000000000 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff80000000 ffffffffffffffff ffffffff80000000 => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff80000000 ffffffffff800000 ffffffff80000000 => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff80000000 ffffffffffffffff ffffffff80000000 => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff80000000 ffffffffff800000 ffffffff80000000 => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff80000000 ffffffffffffffff ffffffff80000000 => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff80000000 ffffffffff800000 ffffffff80000000 => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffff80000000 ffffffff807fffff ffffffff80000000 => 0000ffff00008000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffff80000000 ffffffff80000000 ffffffff80000000 => 0000ffff00008000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff80000000 7fffffff7fffffff ffffffff80000000 => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff80000000 7f8000007f800000 ffffffff80000000 => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff80000000 7fffffff7fffffff ffffffff80000000 => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff80000000 7f8000007f800000 ffffffff80000000 => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff80000000 7fffffff7fffffff ffffffff80000000 => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff80000000 7f8000007f800000 ffffffff80000000 => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffff80000000 007fffff007fffff ffffffff80000000 => 0000000000000000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffff80000000 0000000000000000 ffffffff80000000 => 0000000000000000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff807fffff ffffffffffffffff ffffffff807fffff => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff807fffff ffffffffff800000 ffffffff807fffff => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff807fffff ffffffffffffffff ffffffff807fffff => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff807fffff ffffffffff800000 ffffffff807fffff => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff807fffff ffffffffffffffff ffffffff807fffff => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff807fffff ffffffffff800000 ffffffff807fffff => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffff807fffff ffffffff807fffff ffffffff807fffff => 0000ffff00008000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffff807fffff ffffffff80000000 ffffffff807fffff => 0000ffff00008000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff807fffff 7fffffff7fffffff ffffffff807fffff => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff807fffff 7f8000007f800000 ffffffff807fffff => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff807fffff 7fffffff7fffffff ffffffff807fffff => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff807fffff 7f8000007f800000 ffffffff807fffff => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff807fffff 7fffffff7fffffff ffffffff807fffff => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff807fffff 7f8000007f800000 ffffffff807fffff => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffff807fffff 007fffff007fffff ffffffff807fffff => 0000000000000000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffff807fffff 0000000000000000 ffffffff807fffff => 0000000000000000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffff800000 ffffffff807fffff ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffff800000 ffffffff80000000 ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffff800000 007fffff007fffff ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffff800000 0000000000000000 ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffffffffff ffffffff807fffff ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffffffffff ffffffff80000000 ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffffffffff 007fffff007fffff ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffff800000 ffffffff807fffff ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffff800000 ffffffff80000000 ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffff800000 007fffff007fffff ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffff800000 0000000000000000 ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffffffffff ffffffff807fffff ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffffffffff ffffffff80000000 ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffffffffff 007fffff007fffff ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffff800000 ffffffff807fffff ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffff800000 ffffffff80000000 ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffff800000 007fffff007fffff ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffff800000 0000000000000000 ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffffffffff ffffffff807fffff ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffffffffff ffffffff80000000 ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffffffffff 007fffff007fffff ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+
+All done. Tested 146 different instructions
diff --git a/none/tests/ppc64/test_isa_3_0_altivec.vgtest b/none/tests/ppc64/test_isa_3_0_altivec.vgtest
new file mode 100644
index 0000000..9287e5a
--- /dev/null
+++ b/none/tests/ppc64/test_isa_3_0_altivec.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_ppc64_auxv_cap arch_3_00
+prog: test_isa_3_0 -a -d -q
diff --git a/none/tests/ppc64/test_isa_3_0_other.stderr.exp b/none/tests/ppc64/test_isa_3_0_other.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/ppc64/test_isa_3_0_other.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/ppc64/test_isa_3_0_other.stdout.exp b/none/tests/ppc64/test_isa_3_0_other.stdout.exp
new file mode 100644
index 0000000..a9a8253
--- /dev/null
+++ b/none/tests/ppc64/test_isa_3_0_other.stdout.exp
@@ -0,0 +1,39735 @@
+PPC integer arith instructions with two args:
+Test instruction group [PPC integer arith instructions with two args]
+modsw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+modsw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+modsw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000)
+modsw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000)
+modsw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+modsw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000)
+modsw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+modsw ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000)
+modsw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+
+moduw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+moduw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+moduw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000)
+moduw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000)
+moduw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+moduw 0000001cbe991def, ffffffffffffffff => 00000000be991def (00000000)
+moduw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+moduw ffffffffffffffff, 0000001cbe991def => 000000004166e210 (00000000)
+moduw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+
+modsd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+modsd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+modsd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000)
+modsd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000)
+modsd 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+modsd 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000)
+modsd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+modsd ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000)
+modsd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+
+modud 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+modud 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+modud 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000)
+modud 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000)
+modud 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+modud 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000)
+modud ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+modud ffffffffffffffff, 0000001cbe991def => 000000043eb0c0b2 (00000000)
+modud ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+
+All done. Tested 4 different instructions
+ppc one argument plus shift:
+Test instruction group [ppc one argument plus shift]
+extswsli aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff
+extswsli 5152535455565758 5152535455565758 0 ffffffffffffffff => 5152535455565758 5152535455565758 0 ffffffffffffffff
+extswsli 0000000000000000 0000000000000000 0 ffffffffffffffff => 0000000000000000 0000000000000000 0 ffffffffffffffff
+extswsli ffaa5599113377cc ffaa5599113377cc 0 ffffffffffffffff => ffaa5599113377cc ffaa5599113377cc 0 ffffffffffffffff
+extswsli ffffffffffffffff ffffffffffffffff 0 aaaaaaaaaaaaaaaa => ffffffffffffffff ffffffffffffffff 0 aaaaaaaaaaaaaaaa
+extswsli 5152535455565758 5152535455565758 0 aaaaaaaaaaaaaaaa => 5152535455565758 5152535455565758 0 aaaaaaaaaaaaaaaa
+extswsli 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa => 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa
+extswsli ffaa5599113377cc ffaa5599113377cc 0 aaaaaaaaaaaaaaaa => ffaa5599113377cc ffaa5599113377cc 0 aaaaaaaaaaaaaaaa
+extswsli ffffffffffffffff ffffffffffffffff 0 5152535455565758 => ffffffffffffffff ffffffffffffffff 0 5152535455565758
+extswsli aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 5152535455565758 => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 5152535455565758
+extswsli 0000000000000000 0000000000000000 0 5152535455565758 => 0000000000000000 0000000000000000 0 5152535455565758
+extswsli ffaa5599113377cc ffaa5599113377cc 0 5152535455565758 => ffaa5599113377cc ffaa5599113377cc 0 5152535455565758
+extswsli ffffffffffffffff ffffffffffffffff 0 0000000000000000 => ffffffffffffffff ffffffffffffffff 0 0000000000000000
+extswsli aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 0000000000000000 => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 0000000000000000
+extswsli 5152535455565758 5152535455565758 0 0000000000000000 => 5152535455565758 5152535455565758 0 0000000000000000
+extswsli ffaa5599113377cc ffaa5599113377cc 0 0000000000000000 => ffaa5599113377cc ffaa5599113377cc 0 0000000000000000
+extswsli ffffffffffffffff ffffffffffffffff 0 ffaa5599113377cc => ffffffffffffffff ffffffffffffffff 0 ffaa5599113377cc
+extswsli aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc
+extswsli 5152535455565758 5152535455565758 0 ffaa5599113377cc => 5152535455565758 5152535455565758 0 ffaa5599113377cc
+extswsli 0000000000000000 0000000000000000 0 ffaa5599113377cc => 0000000000000000 0000000000000000 0 ffaa5599113377cc
+
+extswsli. aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff
+extswsli. 5152535455565758 5152535455565758 0 ffffffffffffffff => 5152535455565758 5152535455565758 0 ffffffffffffffff
+extswsli. 0000000000000000 0000000000000000 0 ffffffffffffffff => 0000000000000000 0000000000000000 0 ffffffffffffffff
+extswsli. ffaa5599113377cc ffaa5599113377cc 0 ffffffffffffffff => ffaa5599113377cc ffaa5599113377cc 0 ffffffffffffffff
+extswsli. ffffffffffffffff ffffffffffffffff 0 aaaaaaaaaaaaaaaa => ffffffffffffffff ffffffffffffffff 0 aaaaaaaaaaaaaaaa
+extswsli. 5152535455565758 5152535455565758 0 aaaaaaaaaaaaaaaa => 5152535455565758 5152535455565758 0 aaaaaaaaaaaaaaaa
+extswsli. 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa => 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa
+extswsli. ffaa5599113377cc ffaa5599113377cc 0 aaaaaaaaaaaaaaaa => ffaa5599113377cc ffaa5599113377cc 0 aaaaaaaaaaaaaaaa
+extswsli. ffffffffffffffff ffffffffffffffff 0 5152535455565758 => ffffffffffffffff ffffffffffffffff 0 5152535455565758
+extswsli. aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 5152535455565758 => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 5152535455565758
+extswsli. 0000000000000000 0000000000000000 0 5152535455565758 => 0000000000000000 0000000000000000 0 5152535455565758
+extswsli. ffaa5599113377cc ffaa5599113377cc 0 5152535455565758 => ffaa5599113377cc ffaa5599113377cc 0 5152535455565758
+extswsli. ffffffffffffffff ffffffffffffffff 0 0000000000000000 => ffffffffffffffff ffffffffffffffff 0 0000000000000000
+extswsli. aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 0000000000000000 => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 0000000000000000
+extswsli. 5152535455565758 5152535455565758 0 0000000000000000 => 5152535455565758 5152535455565758 0 0000000000000000
+extswsli. ffaa5599113377cc ffaa5599113377cc 0 0000000000000000 => ffaa5599113377cc ffaa5599113377cc 0 0000000000000000
+extswsli. ffffffffffffffff ffffffffffffffff 0 ffaa5599113377cc => ffffffffffffffff ffffffffffffffff 0 ffaa5599113377cc
+extswsli. aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc
+extswsli. 5152535455565758 5152535455565758 0 ffaa5599113377cc => 5152535455565758 5152535455565758 0 ffaa5599113377cc
+extswsli. 0000000000000000 0000000000000000 0 ffaa5599113377cc => 0000000000000000 0000000000000000 0 ffaa5599113377cc
+
+All done. Tested 6 different instructions
+ppc three parameter ops:
+Test instruction group [ppc three parameter ops]
+maddhd 0000000000000000, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddhd 0000000000000000, 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd 0000000000000000, 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
+maddhd 0000000000000000, 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000)
+maddhd 0000000000000000, 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd 0000000000000000, 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000)
+maddhd 0000000000000000, ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+maddhd 0000000000000000, ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd 0000000000000000, ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000)
+maddhd 0000001cbe991def, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddhd 0000001cbe991def, 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd 0000001cbe991def, 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
+maddhd 0000001cbe991def, 0000001cbe991def, 0000000000000000 => 000000000000033a (00000000)
+maddhd 0000001cbe991def, 0000001cbe991def, 0000001cbe991def => 000000000000033a (00000000)
+maddhd 0000001cbe991def, 0000001cbe991def, ffffffffffffffff => 000000000000033a (00000000)
+maddhd 0000001cbe991def, ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000)
+maddhd 0000001cbe991def, ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd 0000001cbe991def, ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000)
+maddhd ffffffffffffffff, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddhd ffffffffffffffff, 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd ffffffffffffffff, 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
+maddhd ffffffffffffffff, 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000)
+maddhd ffffffffffffffff, 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd ffffffffffffffff, 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000)
+maddhd ffffffffffffffff, ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+maddhd ffffffffffffffff, ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd ffffffffffffffff, ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+
+maddhdu 0000000000000000, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddhdu 0000000000000000, 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+maddhdu 0000000000000000, 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000)
+maddhdu 0000000000000000, 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000)
+maddhdu 0000000000000000, 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+maddhdu 0000000000000000, 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000)
+maddhdu 0000000000000000, ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+maddhdu 0000000000000000, ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000)
+maddhdu 0000000000000000, ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+maddhdu 0000001cbe991def, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddhdu 0000001cbe991def, 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+maddhdu 0000001cbe991def, 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000)
+maddhdu 0000001cbe991def, 0000001cbe991def, 0000000000000000 => 000000000000033a (00000000)
+maddhdu 0000001cbe991def, 0000001cbe991def, 0000001cbe991def => 000000000000033a (00000000)
+maddhdu 0000001cbe991def, 0000001cbe991def, ffffffffffffffff => 000000000000033b (00000000)
+maddhdu 0000001cbe991def, ffffffffffffffff, 0000000000000000 => 0000001cbe991dee (00000000)
+maddhdu 0000001cbe991def, ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000)
+maddhdu 0000001cbe991def, ffffffffffffffff, ffffffffffffffff => 0000001cbe991def (00000000)
+maddhdu ffffffffffffffff, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddhdu ffffffffffffffff, 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+maddhdu ffffffffffffffff, 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000)
+maddhdu ffffffffffffffff, 0000001cbe991def, 0000000000000000 => 0000001cbe991dee (00000000)
+maddhdu ffffffffffffffff, 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000)
+maddhdu ffffffffffffffff, 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000)
+maddhdu ffffffffffffffff, ffffffffffffffff, 0000000000000000 => fffffffffffffffe (00000000)
+maddhdu ffffffffffffffff, ffffffffffffffff, 0000001cbe991def => fffffffffffffffe (00000000)
+maddhdu ffffffffffffffff, ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000)
+
+maddld 0000000000000000, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddld 0000000000000000, 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000)
+maddld 0000000000000000, 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
+maddld 0000000000000000, 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000)
+maddld 0000000000000000, 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000)
+maddld 0000000000000000, 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000)
+maddld 0000000000000000, ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+maddld 0000000000000000, ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000)
+maddld 0000000000000000, ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000)
+maddld 0000001cbe991def, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddld 0000001cbe991def, 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000)
+maddld 0000001cbe991def, 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
+maddld 0000001cbe991def, 0000001cbe991def, 0000000000000000 => 3f66304b8f2e0521 (00000000)
+maddld 0000001cbe991def, 0000001cbe991def, 0000001cbe991def => 3f6630684dc72310 (00000000)
+maddld 0000001cbe991def, 0000001cbe991def, ffffffffffffffff => 3f66304b8f2e0520 (00000000)
+maddld 0000001cbe991def, ffffffffffffffff, 0000000000000000 => ffffffe34166e211 (00000000)
+maddld 0000001cbe991def, ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000)
+maddld 0000001cbe991def, ffffffffffffffff, ffffffffffffffff => ffffffe34166e210 (00000000)
+maddld ffffffffffffffff, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddld ffffffffffffffff, 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000)
+maddld ffffffffffffffff, 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
+maddld ffffffffffffffff, 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000)
+maddld ffffffffffffffff, 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+maddld ffffffffffffffff, 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000)
+maddld ffffffffffffffff, ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000)
+maddld ffffffffffffffff, ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000)
+maddld ffffffffffffffff, ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+
+All done. Tested 9 different instructions
+ppc count zeros:
+Test instruction group [ppc count zeros]
+cnttzw 0000000000000000 => 0000000000000020
+cnttzw 0000001cbe991def => 0000000000000000
+cnttzw ffffffffffffffff => 0000000000000000
+
+cnttzd 0000000000000000 => 0000000000000040
+cnttzd 0000001cbe991def => 0000000000000000
+cnttzd ffffffffffffffff => 0000000000000000
+
+cnttzw. 0000000000000000 => 0000000000000020 Expected cr0 to be zero, it is (40000000)
+
+cnttzw. 0000001cbe991def => 0000000000000000 Expected cr0 to be zero, it is (20000000)
+
+cnttzw. ffffffffffffffff => 0000000000000000 Expected cr0 to be zero, it is (20000000)
+
+
+cnttzd. 0000000000000000 => 0000000000000040 Expected cr0 to be zero, it is (40000000)
+
+cnttzd. 0000001cbe991def => 0000000000000000 Expected cr0 to be zero, it is (20000000)
+
+cnttzd. ffffffffffffffff => 0000000000000000 Expected cr0 to be zero, it is (20000000)
+
+
+All done. Tested 13 different instructions
+ppc set boolean:
+Test instruction group [ppc set boolean]
+setb cr_field:0 cr_value::00000000 => 0000000000000000
+setb cr_field:0 cr_value::10000000 => 0000000000000000
+setb cr_field:0 cr_value::20000000 => 0000000000000000
+setb cr_field:0 cr_value::30000000 => 0000000000000000
+setb cr_field:0 cr_value::40000000 => 0000000000000001
+setb cr_field:0 cr_value::50000000 => 0000000000000001
+setb cr_field:0 cr_value::60000000 => 0000000000000001
+setb cr_field:0 cr_value::70000000 => 0000000000000001
+setb cr_field:0 cr_value::80000000 => ffffffffffffffff
+setb cr_field:1 cr_value::00000000 => 0000000000000000
+setb cr_field:1 cr_value::01000000 => 0000000000000000
+setb cr_field:1 cr_value::02000000 => 0000000000000000
+setb cr_field:1 cr_value::03000000 => 0000000000000000
+setb cr_field:1 cr_value::04000000 => 0000000000000001
+setb cr_field:1 cr_value::05000000 => 0000000000000001
+setb cr_field:1 cr_value::06000000 => 0000000000000001
+setb cr_field:1 cr_value::07000000 => 0000000000000001
+setb cr_field:1 cr_value::08000000 => ffffffffffffffff
+setb cr_field:2 cr_value::00000000 => 0000000000000000
+setb cr_field:2 cr_value::00100000 => 0000000000000000
+setb cr_field:2 cr_value::00200000 => 0000000000000000
+setb cr_field:2 cr_value::00300000 => 0000000000000000
+setb cr_field:2 cr_value::00400000 => 0000000000000001
+setb cr_field:2 cr_value::00500000 => 0000000000000001
+setb cr_field:2 cr_value::00600000 => 0000000000000001
+setb cr_field:2 cr_value::00700000 => 0000000000000001
+setb cr_field:2 cr_value::00800000 => ffffffffffffffff
+setb cr_field:3 cr_value::00000000 => 0000000000000000
+setb cr_field:3 cr_value::00010000 => 0000000000000000
+setb cr_field:3 cr_value::00020000 => 0000000000000000
+setb cr_field:3 cr_value::00030000 => 0000000000000000
+setb cr_field:3 cr_value::00040000 => 0000000000000001
+setb cr_field:3 cr_value::00050000 => 0000000000000001
+setb cr_field:3 cr_value::00060000 => 0000000000000001
+setb cr_field:3 cr_value::00070000 => 0000000000000001
+setb cr_field:3 cr_value::00080000 => ffffffffffffffff
+setb cr_field:4 cr_value::00000000 => 0000000000000000
+setb cr_field:4 cr_value::00001000 => 0000000000000000
+setb cr_field:4 cr_value::00002000 => 0000000000000000
+setb cr_field:4 cr_value::00003000 => 0000000000000000
+setb cr_field:4 cr_value::00004000 => 0000000000000001
+setb cr_field:4 cr_value::00005000 => 0000000000000001
+setb cr_field:4 cr_value::00006000 => 0000000000000001
+setb cr_field:4 cr_value::00007000 => 0000000000000001
+setb cr_field:4 cr_value::00008000 => ffffffffffffffff
+setb cr_field:5 cr_value::00000000 => 0000000000000000
+setb cr_field:5 cr_value::00000100 => 0000000000000000
+setb cr_field:5 cr_value::00000200 => 0000000000000000
+setb cr_field:5 cr_value::00000300 => 0000000000000000
+setb cr_field:5 cr_value::00000400 => 0000000000000001
+setb cr_field:5 cr_value::00000500 => 0000000000000001
+setb cr_field:5 cr_value::00000600 => 0000000000000001
+setb cr_field:5 cr_value::00000700 => 0000000000000001
+setb cr_field:5 cr_value::00000800 => ffffffffffffffff
+setb cr_field:6 cr_value::00000000 => 0000000000000000
+setb cr_field:6 cr_value::00000010 => 0000000000000000
+setb cr_field:6 cr_value::00000020 => 0000000000000000
+setb cr_field:6 cr_value::00000030 => 0000000000000000
+setb cr_field:6 cr_value::00000040 => 0000000000000001
+setb cr_field:6 cr_value::00000050 => 0000000000000001
+setb cr_field:6 cr_value::00000060 => 0000000000000001
+setb cr_field:6 cr_value::00000070 => 0000000000000001
+setb cr_field:6 cr_value::00000080 => ffffffffffffffff
+setb cr_field:7 cr_value::00000000 => 0000000000000000
+setb cr_field:7 cr_value::00000001 => 0000000000000000
+setb cr_field:7 cr_value::00000002 => 0000000000000000
+setb cr_field:7 cr_value::00000003 => 0000000000000000
+setb cr_field:7 cr_value::00000004 => 0000000000000001
+setb cr_field:7 cr_value::00000005 => 0000000000000001
+setb cr_field:7 cr_value::00000006 => 0000000000000001
+setb cr_field:7 cr_value::00000007 => 0000000000000001
+setb cr_field:7 cr_value::00000008 => ffffffffffffffff
+
+All done. Tested 14 different instructions
+ppc char compare:
+Test instruction group [ppc char compare]
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
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+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
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+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+
+cmprb l=1 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=1 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=1 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=1 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=1 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmprb l=1 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
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+cmprb l=1 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=1 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmprb l=1 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
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+cmprb l=1 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=1 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=1 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=1 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+
+cmpeqb 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+
+All done. Tested 17 different instructions
+ppc vector scalar quad:
+Test instruction group [ppc vector scalar quad]
+xsabsqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xsabsqp 0102010201020102 0102030405060708 => 0102010201020102 0102030405060708
+xsabsqp 8899aabbccddeeff 0011223344556677 => 8899aabbccddeeff 0011223344556677
+xsabsqp 7060504030201000 f0e0d0c0b0a09080 => 7060504030201000 70e0d0c0b0a09080
+xsabsqp 0000100800001010 0000100000001002 => 0000100800001010 0000100000001002
+xsabsqp 0010100800101010 0010100000101002 => 0010100800101010 0010100000101002
+xsabsqp 00001c0800001c10 00001c0000001c02 => 00001c0800001c10 00001c0000001c02
+xsabsqp 00101c0800101c10 00101c0000101c02 => 00101c0800101c10 00101c0000101c02
+xsabsqp 00001f0800001f10 00001f0000001f02 => 00001f0800001f10 00001f0000001f02
+xsabsqp 00101f0800101f10 00101f0000101f02 => 00101f0800101f10 00101f0000101f02
+
+xscvdpqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvdpqp 0102010201020102 0102030405060708 => 8000000000000000 3c10203040506070 FPCC-FG
+xscvdpqp 8899aabbccddeeff 0011223344556677 => 7000000000000000 3c01122334455667 FPCC-FG
+xscvdpqp 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 c30e0d0c0b0a0908 FPCC-FL
+xscvdpqp 0000100800001010 0000100000001002 => 0000000000000000 3bf9000000010020 FPCC-FG
+xscvdpqp 0010100800101010 0010100000101002 => 2000000000000000 3c01010000010100 FPCC-FG
+xscvdpqp 00001c0800001c10 00001c0000001c02 => 0000000000000000 3bf9c0000001c020 FPCC-FG
+xscvdpqp 00101c0800101c10 00101c0000101c02 => 2000000000000000 3c0101c0000101c0 FPCC-FG
+xscvdpqp 00001f0800001f10 00001f0000001f02 => 0000000000000000 3bf9f0000001f020 FPCC-FG
+xscvdpqp 00101f0800101f10 00101f0000101f02 => 2000000000000000 3c0101f0000101f0 FPCC-FG
+
+xscvqpdp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 fff0000000000000 FPCC-FL FPCC-FU
+xscvqpdp 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdp 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000 FPCC-FE
+
+xscvqpdpo 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvqpdpo 0102010201020102 0102030405060708 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+xscvqpdpo 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+xscvqpdpo 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 ffefffffffffffff FPCC-FL
+xscvqpdpo 0000100800001010 0000100000001002 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+xscvqpdpo 0010100800101010 0010100000101002 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+xscvqpdpo 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+xscvqpdpo 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+xscvqpdpo 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+xscvqpdpo 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000001 FPRF-C FPCC-FG
+
+xscvqpsdz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpsdz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpsdz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpsdz 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 8000000000000000
+xscvqpsdz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpsdz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpsdz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpsdz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpsdz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpsdz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvqpswz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpswz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpswz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpswz 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 ffffffff80000000
+xscvqpswz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpswz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpswz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpswz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpswz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpswz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvqpudz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpudz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpudz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpudz 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 0000000000000000
+xscvqpudz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpudz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpudz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpudz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpudz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpudz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvqpuwz 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xscvqpuwz 0102010201020102 0102030405060708 => 0000000000000000 0000000000000000
+xscvqpuwz 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000000
+xscvqpuwz 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 0000000000000000
+xscvqpuwz 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xscvqpuwz 0010100800101010 0010100000101002 => 0000000000000000 0000000000000000
+xscvqpuwz 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xscvqpuwz 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000000
+xscvqpuwz 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xscvqpuwz 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000000
+
+xscvsdqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvsdqp 0102010201020102 0102030405060708 => 0800000000000000 4037020304050607 FPCC-FG
+xscvsdqp 8899aabbccddeeff 0011223344556677 => 7000000000000000 4033122334455667 FPCC-FG
+xscvsdqp 7060504030201000 f0e0d0c0b0a09080 => f000000000000000 c03ae3e5e7e9ebed FPCC-FL
+xscvsdqp 0000100800001010 0000100000001002 => 0000000000000000 402b000000010020 FPCC-FG
+xscvsdqp 0010100800101010 0010100000101002 => 2000000000000000 4033010000010100 FPCC-FG
+xscvsdqp 00001c0800001c10 00001c0000001c02 => 0000000000000000 402bc0000001c020 FPCC-FG
+xscvsdqp 00101c0800101c10 00101c0000101c02 => 2000000000000000 403301c0000101c0 FPCC-FG
+xscvsdqp 00001f0800001f10 00001f0000001f02 => 0000000000000000 402bf0000001f020 FPCC-FG
+xscvsdqp 00101f0800101f10 00101f0000101f02 => 2000000000000000 403301f0000101f0 FPCC-FG
+
+xscvudqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvudqp 0102010201020102 0102030405060708 => 0800000000000000 4037020304050607 FPCC-FG
+xscvudqp 8899aabbccddeeff 0011223344556677 => 7000000000000000 4033122334455667 FPCC-FG
+xscvudqp 7060504030201000 f0e0d0c0b0a09080 => 2100000000000000 403ee1c1a1816141 FPCC-FG
+xscvudqp 0000100800001010 0000100000001002 => 0000000000000000 402b000000010020 FPCC-FG
+xscvudqp 0010100800101010 0010100000101002 => 2000000000000000 4033010000010100 FPCC-FG
+xscvudqp 00001c0800001c10 00001c0000001c02 => 0000000000000000 402bc0000001c020 FPCC-FG
+xscvudqp 00101c0800101c10 00101c0000101c02 => 2000000000000000 403301c0000101c0 FPCC-FG
+xscvudqp 00001f0800001f10 00001f0000001f02 => 0000000000000000 402bf0000001f020 FPCC-FG
+xscvudqp 00101f0800101f10 00101f0000101f02 => 2000000000000000 403301f0000101f0 FPCC-FG
+
+xsxexpqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xsxexpqp 0102010201020102 0102030405060708 => 0000000000000000 0000000000000102
+xsxexpqp 8899aabbccddeeff 0011223344556677 => 0000000000000000 0000000000000011
+xsxexpqp 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 00000000000070e0
+xsxexpqp 0000100800001010 0000100000001002 => 0000000000000000 0000000000000000
+xsxexpqp 0010100800101010 0010100000101002 => 0000000000000000 0000000000000010
+xsxexpqp 00001c0800001c10 00001c0000001c02 => 0000000000000000 0000000000000000
+xsxexpqp 00101c0800101c10 00101c0000101c02 => 0000000000000000 0000000000000010
+xsxexpqp 00001f0800001f10 00001f0000001f02 => 0000000000000000 0000000000000000
+xsxexpqp 00101f0800101f10 00101f0000101f02 => 0000000000000000 0000000000000010
+
+xsxsigqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xsxsigqp 0102010201020102 0102030405060708 => 0102010201020102 0001030405060708
+xsxsigqp 8899aabbccddeeff 0011223344556677 => 8899aabbccddeeff 0001223344556677
+xsxsigqp 7060504030201000 f0e0d0c0b0a09080 => 7060504030201000 0001d0c0b0a09080
+xsxsigqp 0000100800001010 0000100000001002 => 0000100800001010 0000100000001002
+xsxsigqp 0010100800101010 0010100000101002 => 0010100800101010 0001100000101002
+xsxsigqp 00001c0800001c10 00001c0000001c02 => 00001c0800001c10 00001c0000001c02
+xsxsigqp 00101c0800101c10 00101c0000101c02 => 00101c0800101c10 00011c0000101c02
+xsxsigqp 00001f0800001f10 00001f0000001f02 => 00001f0800001f10 00001f0000001f02
+xsxsigqp 00101f0800101f10 00101f0000101f02 => 00101f0800101f10 00011f0000101f02
+
+xsnegqp 0000000000000000 0000000000000000 => 0000000000000000 8000000000000000
+xsnegqp 0102010201020102 0102030405060708 => 0102010201020102 8102030405060708
+xsnegqp 8899aabbccddeeff 0011223344556677 => 8899aabbccddeeff 8011223344556677
+xsnegqp 7060504030201000 f0e0d0c0b0a09080 => 7060504030201000 70e0d0c0b0a09080
+xsnegqp 0000100800001010 0000100000001002 => 0000100800001010 8000100000001002
+xsnegqp 0010100800101010 0010100000101002 => 0010100800101010 8010100000101002
+xsnegqp 00001c0800001c10 00001c0000001c02 => 00001c0800001c10 80001c0000001c02
+xsnegqp 00101c0800101c10 00101c0000101c02 => 00101c0800101c10 80101c0000101c02
+xsnegqp 00001f0800001f10 00001f0000001f02 => 00001f0800001f10 80001f0000001f02
+xsnegqp 00101f0800101f10 00101f0000101f02 => 00101f0800101f10 80101f0000101f02
+
+xsnabsqp 0000000000000000 0000000000000000 => 0000000000000000 8000000000000000
+xsnabsqp 0102010201020102 0102030405060708 => 0102010201020102 8102030405060708
+xsnabsqp 8899aabbccddeeff 0011223344556677 => 8899aabbccddeeff 8011223344556677
+xsnabsqp 7060504030201000 f0e0d0c0b0a09080 => 7060504030201000 f0e0d0c0b0a09080
+xsnabsqp 0000100800001010 0000100000001002 => 0000100800001010 8000100000001002
+xsnabsqp 0010100800101010 0010100000101002 => 0010100800101010 8010100000101002
+xsnabsqp 00001c0800001c10 00001c0000001c02 => 00001c0800001c10 80001c0000001c02
+xsnabsqp 00101c0800101c10 00101c0000101c02 => 00101c0800101c10 80101c0000101c02
+xsnabsqp 00001f0800001f10 00001f0000001f02 => 00001f0800001f10 80001f0000001f02
+xsnabsqp 00101f0800101f10 00101f0000101f02 => 00101f0800101f10 80101f0000101f02
+
+xssqrtqp 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xssqrtqp 0102010201020102 0102030405060708 => 464bd73a50214d13 20806c2a33b95561 FPCC-FG
+xssqrtqp 8899aabbccddeeff 0011223344556677 => dc52638df54a24e2 200810907245f32e FPCC-FG
+xssqrtqp 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 7fff800000000000 FPRF-C FPCC-FU
+xssqrtqp 0000100800001010 0000100000001002 => 00006037ff80505e 1ffe000000008010 FPCC-FG
+xssqrtqp 0010100800101010 0010100000101002 => 830aae4bdadf703a 2007752e50e63f0a FPCC-FG
+xssqrtqp 00001c0800001c10 00001c0000001c02 => b110f1988f82fedd 1ffe52a7fa9dd8ee FPCC-FG
+xssqrtqp 00101c0800101c10 00101c0000101c02 => 77d067a08499cf9c 20077d52f24f5140 FPCC-FG
+xssqrtqp 00001f0800001f10 00001f0000001f02 => d618e68f6c3361e0 1ffe645640573e52 FPCC-FG
+xssqrtqp 00101f0800101f10 00101f0000101f02 => f52595ef36141b67 20077f552f622b76 FPCC-FG
+
+xssqrtqpo 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xssqrtqpo 0102010201020102 0102030405060708 => 464bd73a50214d13 20806c2a33b95561 FPCC-FG
+xssqrtqpo 8899aabbccddeeff 0011223344556677 => dc52638df54a24e3 200810907245f32e FPCC-FG
+xssqrtqpo 7060504030201000 f0e0d0c0b0a09080 => 0000000000000000 7fff800000000000 FPRF-C FPCC-FU
+xssqrtqpo 0000100800001010 0000100000001002 => 00006037ff80505d 1ffe000000008010 FPCC-FG
+xssqrtqpo 0010100800101010 0010100000101002 => 830aae4bdadf7039 2007752e50e63f0a FPCC-FG
+xssqrtqpo 00001c0800001c10 00001c0000001c02 => b110f1988f82fedd 1ffe52a7fa9dd8ee FPCC-FG
+xssqrtqpo 00101c0800101c10 00101c0000101c02 => 77d067a08499cf9d 20077d52f24f5140 FPCC-FG
+xssqrtqpo 00001f0800001f10 00001f0000001f02 => d618e68f6c3361df 1ffe645640573e52 FPCC-FG
+xssqrtqpo 00101f0800101f10 00101f0000101f02 => f52595ef36141b67 20077f552f622b76 FPCC-FG
+
+All done. Tested 33 different instructions
+ppc vector scalar compare exponents quads:
+Test instruction group [ppc vector scalar compare exponents quads]
+xscmpexpqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpexpqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpexpqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FL
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpexpqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpexpqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+
+xscmpoqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpoqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpoqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpoqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpoqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpoqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpoqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpoqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpoqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+
+xscmpuqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000000ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000000ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 07ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 07ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 07ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 07ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000007ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000007ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 7fff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000007fff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 7fff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 7fff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 7fff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000007fff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80000000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80000000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80000000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000008000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 00000000000000008000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 00000000000000008000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 00000000000000008000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80007fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080007fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080007fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 80ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 80ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 80ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000080ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000080ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 87ff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 87ff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 87ff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 87ff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FE(EQ)
+xscmpuqp 000000000000000087ff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FE
+xscmpuqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 000000000000000087ff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 000000000000000087ff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp ffff0000000000000000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FE
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff0000000000000000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff0000000000000000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FE
+xscmpuqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp 0000000000000000ffff000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FL
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000007fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000000ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000007ff7fffffffffff (cr#2) => FPCC-FL
+xscmpuqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#0) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#1) => FPCC-FL(LT)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff000000000000 (cr#2) => FPCC-FL
+xscmpuqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80000000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 00000000000000008000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80007fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080007fffffffffff (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000080ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 000000000000000087ff7fffffffffff (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff0000000000000000000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#0) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#1) => FPCC-FG(GT)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff000000000000 (cr#2) => FPCC-FG
+xscmpuqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FE(EQ)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FE(EQ)
+xscmpuqp ffff7fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FE
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp ffff7fffffffffff0000000000000000 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000000ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 07ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000007ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 7fff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000007fff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80000000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 00000000000000008000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80007fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080007fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 80ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000080ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 87ff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 000000000000000087ff7fffffffffff (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff0000000000000000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff ffff7fffffffffff0000000000000000 (cr#2) => FPCC-FU
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#0) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#1) => FPCC-FU(SO)
+xscmpuqp 0000000000000000ffff7fffffffffff 0000000000000000ffff7fffffffffff (cr#2) => FPCC-FU
+
+All done. Tested 36 different instructions
+ppc vector scalar rounding quads:
+Test instruction group [ppc vector scalar rounding quads]
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=2) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=2) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 00007fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 00007fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000000007fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000000007fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 00ff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 00ff0000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000000ff000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000000ff000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 00ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 00ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000000ff7fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000000ff7fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 07ff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 07ff0000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000007ff000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000007ff000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 07ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 07ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000007ff7fffffffffff (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 000000000000000007ff7fffffffffff (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 7fff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=1) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=2) => 00000000000000003fff000000000000 FPCC-FG
+xsrqpi 7fff0000000000000000000000000000 (R=1) (RMC=3) => 00000000000000000000000000000000 FPCC-FE
+xsrqpi 00000000000000007fff000000000000 (R=0) (RMC=0) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpi 00000000000000007fff000000000000 (R=0) (RMC=1) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpi 00000000000000007fff000000000000 (R=0) (RMC=2) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
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+xsrqpxp 7fff0000000000000000000000000000 (R=0) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=0) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=1) => 7ffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff0000000000000000000000000000 (R=1) (RMC=3) => 7ffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=0) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=1) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=2) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=0) (RMC=3) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=0) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=1) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=2) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 00000000000000007fff000000000000 (R=1) (RMC=3) => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=1) => 7ffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 7fff7fffffffffff0000000000000000 (R=1) (RMC=3) => 7ffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=0) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=1) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=2) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=0) (RMC=3) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=0) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=1) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=2) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 00000000000000007fff7fffffffffff (R=1) (RMC=3) => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=2) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80000000000000000000000000000000 (R=1) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpxp 00000000000000008000000000000000 (R=0) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=0) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=1) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=2) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpxp 00000000000000008000000000000000 (R=1) (RMC=3) => 00000000000000008000000000000000 FPRF-C FPCC-FE
+xsrqpxp 80007fffffffffff0000000000000000 (R=0) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80007fffffffffff0000000000000000 (R=0) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80007fffffffffff0000000000000000 (R=0) (RMC=2) => 80020000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80007fffffffffff0000000000000000 (R=0) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80007fffffffffff0000000000000000 (R=1) (RMC=0) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80007fffffffffff0000000000000000 (R=1) (RMC=1) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80007fffffffffff0000000000000000 (R=1) (RMC=2) => 80020000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80007fffffffffff0000000000000000 (R=1) (RMC=3) => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=0) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=1) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=2) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=0) (RMC=3) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=0) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=1) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=2) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 000000000000000080007fffffffffff (R=1) (RMC=3) => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsrqpxp 80ff0000000000000000000000000000 (R=0) (RMC=0) => 81000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff0000000000000000000000000000 (R=0) (RMC=1) => 81000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff0000000000000000000000000000 (R=0) (RMC=2) => 81000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff0000000000000000000000000000 (R=0) (RMC=3) => 81000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff0000000000000000000000000000 (R=1) (RMC=0) => 81000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff0000000000000000000000000000 (R=1) (RMC=1) => 80fe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff0000000000000000000000000000 (R=1) (RMC=2) => 81000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff0000000000000000000000000000 (R=1) (RMC=3) => 80fe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff000000000000 (R=0) (RMC=0) => 000000000000000080ff000000000000 FPCC-FL
+xsrqpxp 000000000000000080ff000000000000 (R=0) (RMC=1) => 000000000000000080ff000000000000 FPCC-FL
+xsrqpxp 000000000000000080ff000000000000 (R=0) (RMC=2) => 000000000000000080ff000000000000 FPCC-FL
+xsrqpxp 000000000000000080ff000000000000 (R=0) (RMC=3) => 000000000000000080ff000000000000 FPCC-FL
+xsrqpxp 000000000000000080ff000000000000 (R=1) (RMC=0) => 000000000000000080ff000000000000 FPCC-FL
+xsrqpxp 000000000000000080ff000000000000 (R=1) (RMC=1) => 000000000000000080ff000000000000 FPCC-FL
+xsrqpxp 000000000000000080ff000000000000 (R=1) (RMC=2) => 000000000000000080ff000000000000 FPCC-FL
+xsrqpxp 000000000000000080ff000000000000 (R=1) (RMC=3) => 000000000000000080ff000000000000 FPCC-FL
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 81000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 81000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 81000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 81000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 81000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 80fe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 81000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 80ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 80fe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000080ff7fffffffffff (R=0) (RMC=0) => 000000000000000080ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000080ff7fffffffffff (R=0) (RMC=1) => 000000000000000080ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000080ff7fffffffffff (R=0) (RMC=2) => 000000000000000080ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000080ff7fffffffffff (R=0) (RMC=3) => 000000000000000080ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000080ff7fffffffffff (R=1) (RMC=0) => 000000000000000080ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000080ff7fffffffffff (R=1) (RMC=1) => 000000000000000080ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000080ff7fffffffffff (R=1) (RMC=2) => 000000000000000080ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000080ff7fffffffffff (R=1) (RMC=3) => 000000000000000080ff7fffffffffff FPCC-FL
+xsrqpxp 87ff0000000000000000000000000000 (R=0) (RMC=0) => 88000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff0000000000000000000000000000 (R=0) (RMC=1) => 88000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff0000000000000000000000000000 (R=0) (RMC=2) => 88000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff0000000000000000000000000000 (R=0) (RMC=3) => 88000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff0000000000000000000000000000 (R=1) (RMC=0) => 88000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff0000000000000000000000000000 (R=1) (RMC=1) => 87fe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff0000000000000000000000000000 (R=1) (RMC=2) => 88000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff0000000000000000000000000000 (R=1) (RMC=3) => 87fe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff000000000000 (R=0) (RMC=0) => 000000000000000087ff000000000000 FPCC-FL
+xsrqpxp 000000000000000087ff000000000000 (R=0) (RMC=1) => 000000000000000087ff000000000000 FPCC-FL
+xsrqpxp 000000000000000087ff000000000000 (R=0) (RMC=2) => 000000000000000087ff000000000000 FPCC-FL
+xsrqpxp 000000000000000087ff000000000000 (R=0) (RMC=3) => 000000000000000087ff000000000000 FPCC-FL
+xsrqpxp 000000000000000087ff000000000000 (R=1) (RMC=0) => 000000000000000087ff000000000000 FPCC-FL
+xsrqpxp 000000000000000087ff000000000000 (R=1) (RMC=1) => 000000000000000087ff000000000000 FPCC-FL
+xsrqpxp 000000000000000087ff000000000000 (R=1) (RMC=2) => 000000000000000087ff000000000000 FPCC-FL
+xsrqpxp 000000000000000087ff000000000000 (R=1) (RMC=3) => 000000000000000087ff000000000000 FPCC-FL
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=0) (RMC=0) => 88000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=0) (RMC=1) => 88000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=0) (RMC=2) => 88000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=0) (RMC=3) => 88000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=1) (RMC=0) => 88000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=1) (RMC=1) => 87fe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=1) (RMC=2) => 88000000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 87ff7fffffffffff0000000000000000 (R=1) (RMC=3) => 87fe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=0) => 000000000000000087ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=1) => 000000000000000087ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=2) => 000000000000000087ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000087ff7fffffffffff (R=0) (RMC=3) => 000000000000000087ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000087ff7fffffffffff (R=1) (RMC=0) => 000000000000000087ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000087ff7fffffffffff (R=1) (RMC=1) => 000000000000000087ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000087ff7fffffffffff (R=1) (RMC=2) => 000000000000000087ff7fffffffffff FPCC-FL
+xsrqpxp 000000000000000087ff7fffffffffff (R=1) (RMC=3) => 000000000000000087ff7fffffffffff FPCC-FL
+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=2) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=1) => fffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=2) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff0000000000000000000000000000 (R=1) (RMC=3) => fffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=0) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=1) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=2) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=0) (RMC=3) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=0) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=1) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=2) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp 0000000000000000ffff000000000000 (R=1) (RMC=3) => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=0) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=1) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=2) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=0) (RMC=3) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=0) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=1) => fffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=2) => 00000000000000000000000000000001 FPRF-C FPCC-FG
+xsrqpxp ffff7fffffffffff0000000000000000 (R=1) (RMC=3) => fffe0000000000000000000000000000 FPRF-C FPCC-FG
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=0) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=1) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=2) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=0) (RMC=3) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=0) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=1) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=2) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsrqpxp 0000000000000000ffff7fffffffffff (R=1) (RMC=3) => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+
+All done. Tested 39 different instructions
+ppc vector scalar move to/from:
+Test instruction group [ppc vector scalar move to/from]
+mfvsrld aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa ffffffffffffffff
+mfvsrld 5152535455565758 5152535455565758 0 ffffffffffffffff => 5152535455565758 5152535455565758 5152535455565758 ffffffffffffffff
+mfvsrld 0000000000000000 0000000000000000 0 ffffffffffffffff => 0000000000000000 0000000000000000 0 ffffffffffffffff
+mfvsrld ffaa5599113377cc ffaa5599113377cc 0 ffffffffffffffff => ffaa5599113377cc ffaa5599113377cc ffaa5599113377cc ffffffffffffffff
+mfvsrld ffffffffffffffff ffffffffffffffff 0 aaaaaaaaaaaaaaaa => ffffffffffffffff ffffffffffffffff ffffffffffffffff aaaaaaaaaaaaaaaa
+mfvsrld 5152535455565758 5152535455565758 0 aaaaaaaaaaaaaaaa => 5152535455565758 5152535455565758 5152535455565758 aaaaaaaaaaaaaaaa
+mfvsrld 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa => 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa
+mfvsrld ffaa5599113377cc ffaa5599113377cc 0 aaaaaaaaaaaaaaaa => ffaa5599113377cc ffaa5599113377cc ffaa5599113377cc aaaaaaaaaaaaaaaa
+mfvsrld ffffffffffffffff ffffffffffffffff 0 5152535455565758 => ffffffffffffffff ffffffffffffffff ffffffffffffffff 5152535455565758
+mfvsrld aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 5152535455565758 => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 5152535455565758
+mfvsrld 0000000000000000 0000000000000000 0 5152535455565758 => 0000000000000000 0000000000000000 0 5152535455565758
+mfvsrld ffaa5599113377cc ffaa5599113377cc 0 5152535455565758 => ffaa5599113377cc ffaa5599113377cc ffaa5599113377cc 5152535455565758
+mfvsrld ffffffffffffffff ffffffffffffffff 0 0000000000000000 => ffffffffffffffff ffffffffffffffff ffffffffffffffff 0000000000000000
+mfvsrld aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 0000000000000000 => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0000000000000000
+mfvsrld 5152535455565758 5152535455565758 0 0000000000000000 => 5152535455565758 5152535455565758 5152535455565758 0000000000000000
+mfvsrld ffaa5599113377cc ffaa5599113377cc 0 0000000000000000 => ffaa5599113377cc ffaa5599113377cc ffaa5599113377cc 0000000000000000
+mfvsrld ffffffffffffffff ffffffffffffffff 0 ffaa5599113377cc => ffffffffffffffff ffffffffffffffff ffffffffffffffff ffaa5599113377cc
+mfvsrld aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa ffaa5599113377cc
+mfvsrld 5152535455565758 5152535455565758 0 ffaa5599113377cc => 5152535455565758 5152535455565758 5152535455565758 ffaa5599113377cc
+mfvsrld 0000000000000000 0000000000000000 0 ffaa5599113377cc => 0000000000000000 0000000000000000 0 ffaa5599113377cc
+
+mtvsrdd aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => ffffffffffffffff 0000000000000000 0 ffffffffffffffff
+mtvsrdd 5152535455565758 5152535455565758 0 ffffffffffffffff => ffffffffffffffff 0000000000000000 0 ffffffffffffffff
+mtvsrdd 0000000000000000 0000000000000000 0 ffffffffffffffff => ffffffffffffffff 0000000000000000 0 ffffffffffffffff
+mtvsrdd ffaa5599113377cc ffaa5599113377cc 0 ffffffffffffffff => ffffffffffffffff 0000000000000000 0 ffffffffffffffff
+mtvsrdd ffffffffffffffff ffffffffffffffff 0 aaaaaaaaaaaaaaaa => aaaaaaaaaaaaaaaa 0000000000000000 0 aaaaaaaaaaaaaaaa
+mtvsrdd 5152535455565758 5152535455565758 0 aaaaaaaaaaaaaaaa => aaaaaaaaaaaaaaaa 0000000000000000 0 aaaaaaaaaaaaaaaa
+mtvsrdd 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa => aaaaaaaaaaaaaaaa 0000000000000000 0 aaaaaaaaaaaaaaaa
+mtvsrdd ffaa5599113377cc ffaa5599113377cc 0 aaaaaaaaaaaaaaaa => aaaaaaaaaaaaaaaa 0000000000000000 0 aaaaaaaaaaaaaaaa
+mtvsrdd ffffffffffffffff ffffffffffffffff 0 5152535455565758 => 5152535455565758 0000000000000000 0 5152535455565758
+mtvsrdd aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 5152535455565758 => 5152535455565758 0000000000000000 0 5152535455565758
+mtvsrdd 0000000000000000 0000000000000000 0 5152535455565758 => 5152535455565758 0000000000000000 0 5152535455565758
+mtvsrdd ffaa5599113377cc ffaa5599113377cc 0 5152535455565758 => 5152535455565758 0000000000000000 0 5152535455565758
+mtvsrdd ffffffffffffffff ffffffffffffffff 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrdd aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrdd 5152535455565758 5152535455565758 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrdd ffaa5599113377cc ffaa5599113377cc 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrdd ffffffffffffffff ffffffffffffffff 0 ffaa5599113377cc => ffaa5599113377cc 0000000000000000 0 ffaa5599113377cc
+mtvsrdd aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => ffaa5599113377cc 0000000000000000 0 ffaa5599113377cc
+mtvsrdd 5152535455565758 5152535455565758 0 ffaa5599113377cc => ffaa5599113377cc 0000000000000000 0 ffaa5599113377cc
+mtvsrdd 0000000000000000 0000000000000000 0 ffaa5599113377cc => ffaa5599113377cc 0000000000000000 0 ffaa5599113377cc
+
+mtvsrws aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => ffffffffffffffff ffffffffffffffff 0 ffffffffffffffff
+mtvsrws 5152535455565758 5152535455565758 0 ffffffffffffffff => ffffffffffffffff ffffffffffffffff 0 ffffffffffffffff
+mtvsrws 0000000000000000 0000000000000000 0 ffffffffffffffff => ffffffffffffffff ffffffffffffffff 0 ffffffffffffffff
+mtvsrws ffaa5599113377cc ffaa5599113377cc 0 ffffffffffffffff => ffffffffffffffff ffffffffffffffff 0 ffffffffffffffff
+mtvsrws ffffffffffffffff ffffffffffffffff 0 aaaaaaaaaaaaaaaa => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 aaaaaaaaaaaaaaaa
+mtvsrws 5152535455565758 5152535455565758 0 aaaaaaaaaaaaaaaa => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 aaaaaaaaaaaaaaaa
+mtvsrws 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 aaaaaaaaaaaaaaaa
+mtvsrws ffaa5599113377cc ffaa5599113377cc 0 aaaaaaaaaaaaaaaa => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 aaaaaaaaaaaaaaaa
+mtvsrws ffffffffffffffff ffffffffffffffff 0 5152535455565758 => 5556575855565758 5556575855565758 0 5152535455565758
+mtvsrws aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 5152535455565758 => 5556575855565758 5556575855565758 0 5152535455565758
+mtvsrws 0000000000000000 0000000000000000 0 5152535455565758 => 5556575855565758 5556575855565758 0 5152535455565758
+mtvsrws ffaa5599113377cc ffaa5599113377cc 0 5152535455565758 => 5556575855565758 5556575855565758 0 5152535455565758
+mtvsrws ffffffffffffffff ffffffffffffffff 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrws aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrws 5152535455565758 5152535455565758 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrws ffaa5599113377cc ffaa5599113377cc 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrws ffffffffffffffff ffffffffffffffff 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
+mtvsrws aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
+mtvsrws 5152535455565758 5152535455565758 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
+mtvsrws 0000000000000000 0000000000000000 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
+
+All done. Tested 42 different instructions
+ppc vector scalar compare exponents doubles:
+Test instruction group [ppc vector scalar compare exponents doubles]
+xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0000000000000000 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 0000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 00007fffffffffff 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 00007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff0000000000000 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 0ff07fffffffffff 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 0ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff0000000000000 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 7ff07fffffffffff 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 7ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8000000000000000 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 8000000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 80007fffffffffff 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 80007fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff0000000000000 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp 8ff07fffffffffff 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 8ff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff0000000000000 fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff0000000000000 fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 0000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 00007fffffffffff 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff0000000000000 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 0ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 0ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff0000000000000 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 7ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 7ff07fffffffffff 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 8000000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8000000000000000 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 80007fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 80007fffffffffff 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff0000000000000 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff 8ff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff 8ff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000 => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FE(EQ)
+xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FE(EQ)
+
+All done. Tested 43 different instructions
+ppc vector scalar test data class tests:
+Test instruction group [ppc vector scalar test data class tests]
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+xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
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+xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
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+xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
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+xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
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+xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
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+xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
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+xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
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+xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
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+xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
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+xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
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+xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
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+xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
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+xststdcqp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
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+xststdcqp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
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+xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcqp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 7fff7fffffffffff DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 DCMX=[-inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcdp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcdp 0000000000000000, ffff7fffffffffff DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcdp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 00ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 00ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 07ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff DCMX=[+inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 07ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 0000000000000000, 7fff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 7fff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 7fff7fffffffffff DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)(SO)
+xststdcsp 0000000000000000, 7fff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 8000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 DCMX=[-inf] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 8000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80007fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80007fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 80ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 80ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 87ff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff DCMX=[NaN] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, 87ff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff000000000000 DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)
+xststdcsp 0000000000000000, ffff000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 DCMX=[+zero] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (EQ)
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp ffff7fffffffffff, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+xststdcsp 0000000000000000, ffff7fffffffffff DCMX=[-denormal] => Match. 0505050505050505, 0a0a0a0a0a0a0a0a (LT)(EQ)(SO)
+xststdcsp 0000000000000000, ffff7fffffffffff => 0505050505050505, 0a0a0a0a0a0a0a0a
+
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => ffffffffffffffff, ffffffffffffffff
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00007fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, ffffffff00000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00007fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 00ff7fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 07ff7fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff000000000000, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff000000000000 => 0000000000000000, ffffffff00000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 7fff7fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 7fff7fffffffffff => 0000000000000000, ffffffffffffffff
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, ffffffff00000000
+xvtstdcsp 0000000000000000, 8000000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80007fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, ffffffff00000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80007fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 80ff7fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 87ff7fffffffffff, 0000000000000000 => 00000000ffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 00000000ffffffff
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => 00000000ffffffff, ffffffffffffffff
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff000000000000, 0000000000000000 => ffffffff00000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => ffffffffffffffff, 00000000ffffffff
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff000000000000 => 0000000000000000, ffffffff00000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcsp ffff7fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcsp 0000000000000000, ffff7fffffffffff => 0000000000000000, ffffffffffffffff
+
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => ffffffffffffffff, ffffffffffffffff
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, ffffffffffffffff
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 00ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 00ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 07ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 07ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff000000000000, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 7fff7fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 7fff7fffffffffff => 0000000000000000, ffffffffffffffff
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 8000000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 0000000000000000, 8000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 8000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80007fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, ffffffffffffffff
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80007fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 80ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 80ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 87ff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, 87ff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff000000000000, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, ffffffffffffffff
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => 0000000000000000, 0000000000000000
+xvtstdcdp ffff7fffffffffff, 0000000000000000 => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => ffffffffffffffff, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
+xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, ffffffffffffffff
+
+All done. Tested 48 different instructions
+ppc vector scalar tests against float double two args :
+Test instruction group [ppc vector scalar tests against float double two args ]
+xsiexpdp r14 = 0x0, r15 = 0x0 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x7fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 7ff0000000000000
+xsiexpdp r14 = 0x0, r15 = 0xff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0xff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 7ff0000000000000
+xsiexpdp r14 = 0x0, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 7ff0000000000000
+xsiexpdp r14 = 0x0, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 7ff0000000000000
+xsiexpdp r14 = 0x0, r15 = 0x8000000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x80007fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 7ff0000000000000
+xsiexpdp r14 = 0x0, r15 = 0x8ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0x8ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 7ff0000000000000
+xsiexpdp r14 = 0x0, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 7ff0000000000000
+xsiexpdp r14 = 0x0, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
+xsiexpdp r14 = 0x0, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 7ff0000000000000
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0x0 0000000000000000 ffff7fffffffffff => 0000000000000000 00007fffffffffff
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0x7fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 7ff07fffffffffff
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0xff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 00007fffffffffff
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0xff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 7ff07fffffffffff
+xsiexpdp r14 = 0x7fffffffffff, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 00007fffffffffff
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+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 8000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 8000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x8000000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 8000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x80007fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x8ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 8000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0x8ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 8000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 8000000000000000
+xsiexpdp r14 = 0xfff0000000000000, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff0000000000000
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x0 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x7ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x8000000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x80007fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x8ff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0x8ff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff0000000000000 0000000000000000 ffff7fffffffffff => 0000000000000000 80007fffffffffff
+xsiexpdp r14 = 0xfff07fffffffffff, r15 = 0xfff07fffffffffff 0000000000000000 ffff7fffffffffff => 0000000000000000 fff07fffffffffff
+
+xscvhpdp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x1ff000001ff0000 fffffe00fffffe00 01ff000001ff0000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e000000 ffffffffffffffff 7e0000007e000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff00007fff0000 fffffe00fffffe00 7fff00007fff0000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e000000 ffffffffffffffff 7e0000007e000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff00007fff0000 fffffe00fffffe00 7fff00007fff0000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff81ffffff81ff, vec_xb[0] = 0x7e0000007e000000 ffff81ffffff81ff 7e0000007e000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff8000ffff8000, vec_xb[0] = 0x7fff00007fff0000 ffff8000ffff8000 7fff00007fff0000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0x8000000080000000 ffff7fffffff7fff 8000000080000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0x81ff000081ff0000 ffff7e00ffff7e00 81ff000081ff0000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe000000fe000000 ffff7fffffff7fff fe000000fe000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff0000ffff0000 ffff7e00ffff7e00 ffff0000ffff0000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe000000fe000000 ffff7fffffff7fff fe000000fe000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff0000ffff0000 ffff7e00ffff7e00 ffff0000ffff0000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff01ffffff01ff, vec_xb[0] = 0xfe000000fe000000 ffff01ffffff01ff fe000000fe000000 => 0000000000000000 0000000000000000 FPCC-FE
+xscvhpdp vec_xb[1] = 0xffff0000ffff0000, vec_xb[0] = 0xffff0000ffff0000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 0000000000000000 FPCC-FE
+
+xscvdphp r14 = 0x0, r15 = 0x0 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7ff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7ff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7ff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x7ff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x8000000000000000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x80007fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x8ff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0x8ff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xfff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xfff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xfff0000000000000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+xscvdphp r14 = 0x0, r15 = 0xfff07fffffffffff ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 000000000000ffc0 FPRF-C FPCC-FU
+
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => ffffe000ffffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x1ff000001ff0000 fffffe00fffffe00 01ff000001ff0000 => ffc00000ffc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e000000 ffffffffffffffff 7e0000007e000000 => ffffe000ffffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff00007fff0000 fffffe00fffffe00 7fff00007fff0000 => ffc00000ffc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e000000 ffffffffffffffff 7e0000007e000000 => ffffe000ffffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff00007fff0000 fffffe00fffffe00 7fff00007fff0000 => ffc00000ffc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff81ffffff81ff, vec_xb[0] = 0x7e0000007e000000 ffff81ffffff81ff 7e0000007e000000 => b7ff8000b7ff8000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff8000ffff8000, vec_xb[0] = 0x7fff00007fff0000 ffff8000ffff8000 7fff00007fff0000 => 8000000080000000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0x8000000080000000 ffff7fffffff7fff 8000000080000000 => 7fffe0007fffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0x81ff000081ff0000 ffff7e00ffff7e00 81ff000081ff0000 => 7fc000007fc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe000000fe000000 ffff7fffffff7fff fe000000fe000000 => 7fffe0007fffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff0000ffff0000 ffff7e00ffff7e00 ffff0000ffff0000 => 7fc000007fc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe000000fe000000 ffff7fffffff7fff fe000000fe000000 => 7fffe0007fffe000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff0000ffff0000 ffff7e00ffff7e00 ffff0000ffff0000 => 7fc000007fc00000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff01ffffff01ff, vec_xb[0] = 0xfe000000fe000000 ffff01ffffff01ff fe000000fe000000 => 37ff800037ff8000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff0000, vec_xb[0] = 0xffff0000ffff0000 ffff0000ffff0000 ffff0000ffff0000 => 0000000000000000 0000000000000000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x1ff000001ff fe00fffffe00ffff 000001ff000001ff => ffffe000ffffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x1ff01ff01ff01ff fe00fe00fe00fe00 01ff01ff01ff01ff => ffc00000ffc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e0001ff7e0001ff fe00fffffe00ffff 7e0001ff7e0001ff => ffffe000ffffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff01ff7fff01ff fe00fe00fe00fe00 7fff01ff7fff01ff => ffc00000ffc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e0001ff7e0001ff fe00fffffe00ffff 7e0001ff7e0001ff => ffffe000ffffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff01ff7fff01ff fe00fe00fe00fe00 7fff01ff7fff01ff => ffc00000ffc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe0081fffe0081ff, vec_xb[0] = 0x7e0001ff7e0001ff fe0081fffe0081ff 7e0001ff7e0001ff => b7ff8000b7ff8000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe008000fe008000, vec_xb[0] = 0x7fff01ff7fff01ff fe008000fe008000 7fff01ff7fff01ff => 8000000080000000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0x800001ff800001ff fe007ffffe007fff 800001ff800001ff => 7fffe0007fffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0x81ff01ff81ff01ff fe007e00fe007e00 81ff01ff81ff01ff => 7fc000007fc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe0001fffe0001ff fe007ffffe007fff fe0001fffe0001ff => 7fffe0007fffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff01ffffff01ff fe007e00fe007e00 ffff01ffffff01ff => 7fc000007fc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe0001fffe0001ff fe007ffffe007fff fe0001fffe0001ff => 7fffe0007fffe000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff01ffffff01ff fe007e00fe007e00 ffff01ffffff01ff => 7fc000007fc00000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe0001fffe0001ff, vec_xb[0] = 0xfe0001fffe0001ff fe0001fffe0001ff fe0001fffe0001ff => 37ff800037ff8000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xfe000000fe000000, vec_xb[0] = 0xffff01ffffff01ff fe000000fe000000 ffff01ffffff01ff => 0000000000000000 37ff800037ff8000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e00 ffffffffffffffff 00007e0000007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x1ff7e0001ff7e00 fffffe00fffffe00 01ff7e0001ff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e007e007e007e00 ffffffffffffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff7e007fff7e00 fffffe00fffffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e007e007e007e00 ffffffffffffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff7e007fff7e00 fffffe00fffffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff81ffffff81ff, vec_xb[0] = 0x7e007e007e007e00 ffff81ffffff81ff 7e007e007e007e00 => b7ff8000b7ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff8000ffff8000, vec_xb[0] = 0x7fff7e007fff7e00 ffff8000ffff8000 7fff7e007fff7e00 => 8000000080000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0x80007e0080007e00 ffff7fffffff7fff 80007e0080007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0x81ff7e0081ff7e00 ffff7e00ffff7e00 81ff7e0081ff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe007e00fe007e00 ffff7fffffff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff7e00ffff7e00 ffff7e00ffff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe007e00fe007e00 ffff7fffffff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff7e00ffff7e00 ffff7e00ffff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff01ffffff01ff, vec_xb[0] = 0xfe007e00fe007e00 ffff01ffffff01ff fe007e00fe007e00 => 37ff800037ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff0000, vec_xb[0] = 0xffff7e00ffff7e00 ffff0000ffff0000 ffff7e00ffff7e00 => 0000000000000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7fff00007fff fe00fffffe00ffff 00007fff00007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x1ff7fff01ff7fff fe00fe00fe00fe00 01ff7fff01ff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e007fff7e007fff fe00fffffe00ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff7fff7fff7fff fe00fe00fe00fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e007fff7e007fff fe00fffffe00ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff7fff7fff7fff fe00fe00fe00fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe0081fffe0081ff, vec_xb[0] = 0x7e007fff7e007fff fe0081fffe0081ff 7e007fff7e007fff => b7ff8000b7ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe008000fe008000, vec_xb[0] = 0x7fff7fff7fff7fff fe008000fe008000 7fff7fff7fff7fff => 8000000080000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0x80007fff80007fff fe007ffffe007fff 80007fff80007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0x81ff7fff81ff7fff fe007e00fe007e00 81ff7fff81ff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe007ffffe007fff fe007ffffe007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff7fffffff7fff fe007e00fe007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe007ffffe007fff fe007ffffe007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff7fffffff7fff fe007e00fe007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe0001fffe0001ff, vec_xb[0] = 0xfe007ffffe007fff fe0001fffe0001ff fe007ffffe007fff => 37ff800037ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe000000, vec_xb[0] = 0xffff7fffffff7fff fe000000fe000000 ffff7fffffff7fff => 0000000000000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e0000007e00 ffffffffffffffff 00007e0000007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x1ff7e0001ff7e00 fffffe00fffffe00 01ff7e0001ff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e007e007e007e00 ffffffffffffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff7e007fff7e00 fffffe00fffffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7e007e007e007e00 ffffffffffffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfffffe00fffffe00, vec_xb[0] = 0x7fff7e007fff7e00 fffffe00fffffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff81ffffff81ff, vec_xb[0] = 0x7e007e007e007e00 ffff81ffffff81ff 7e007e007e007e00 => b7ff8000b7ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff8000ffff8000, vec_xb[0] = 0x7fff7e007fff7e00 ffff8000ffff8000 7fff7e007fff7e00 => 8000000080000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0x80007e0080007e00 ffff7fffffff7fff 80007e0080007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0x81ff7e0081ff7e00 ffff7e00ffff7e00 81ff7e0081ff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe007e00fe007e00 ffff7fffffff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff7e00ffff7e00 ffff7e00ffff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7fffffff7fff, vec_xb[0] = 0xfe007e00fe007e00 ffff7fffffff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff7e00ffff7e00, vec_xb[0] = 0xffff7e00ffff7e00 ffff7e00ffff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff01ffffff01ff, vec_xb[0] = 0xfe007e00fe007e00 ffff01ffffff01ff fe007e00fe007e00 => 37ff800037ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff0000, vec_xb[0] = 0xffff7e00ffff7e00 ffff0000ffff0000 ffff7e00ffff7e00 => 0000000000000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7fff00007fff fe00fffffe00ffff 00007fff00007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x1ff7fff01ff7fff fe00fe00fe00fe00 01ff7fff01ff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e007fff7e007fff fe00fffffe00ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff7fff7fff7fff fe00fe00fe00fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fffffe00ffff, vec_xb[0] = 0x7e007fff7e007fff fe00fffffe00ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe00fe00fe00fe00, vec_xb[0] = 0x7fff7fff7fff7fff fe00fe00fe00fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe0081fffe0081ff, vec_xb[0] = 0x7e007fff7e007fff fe0081fffe0081ff 7e007fff7e007fff => b7ff8000b7ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe008000fe008000, vec_xb[0] = 0x7fff7fff7fff7fff fe008000fe008000 7fff7fff7fff7fff => 8000000080000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0x80007fff80007fff fe007ffffe007fff 80007fff80007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0x81ff7fff81ff7fff fe007e00fe007e00 81ff7fff81ff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe007ffffe007fff fe007ffffe007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff7fffffff7fff fe007e00fe007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007ffffe007fff, vec_xb[0] = 0xfe007ffffe007fff fe007ffffe007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe007e00fe007e00, vec_xb[0] = 0xffff7fffffff7fff fe007e00fe007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe0001fffe0001ff, vec_xb[0] = 0xfe007ffffe007fff fe0001fffe0001ff fe007ffffe007fff => 37ff800037ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe000000, vec_xb[0] = 0xffff7fffffff7fff fe000000fe000000 ffff7fffffff7fff => 0000000000000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x81ffffff81ffffff, vec_xb[0] = 0x7e0000007e00 81ffffff81ffffff 00007e0000007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81fffe0081fffe00, vec_xb[0] = 0x1ff7e0001ff7e00 81fffe0081fffe00 01ff7e0001ff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ffffff81ffffff, vec_xb[0] = 0x7e007e007e007e00 81ffffff81ffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81fffe0081fffe00, vec_xb[0] = 0x7fff7e007fff7e00 81fffe0081fffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ffffff81ffffff, vec_xb[0] = 0x7e007e007e007e00 81ffffff81ffffff 7e007e007e007e00 => ffffe000ffffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81fffe0081fffe00, vec_xb[0] = 0x7fff7e007fff7e00 81fffe0081fffe00 7fff7e007fff7e00 => ffc00000ffc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff81ff81ff81ff, vec_xb[0] = 0x7e007e007e007e00 81ff81ff81ff81ff 7e007e007e007e00 => b7ff8000b7ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff800081ff8000, vec_xb[0] = 0x7fff7e007fff7e00 81ff800081ff8000 7fff7e007fff7e00 => 8000000080000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7fff81ff7fff, vec_xb[0] = 0x80007e0080007e00 81ff7fff81ff7fff 80007e0080007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7e0081ff7e00, vec_xb[0] = 0x81ff7e0081ff7e00 81ff7e0081ff7e00 81ff7e0081ff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7fff81ff7fff, vec_xb[0] = 0xfe007e00fe007e00 81ff7fff81ff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7e0081ff7e00, vec_xb[0] = 0xffff7e00ffff7e00 81ff7e0081ff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7fff81ff7fff, vec_xb[0] = 0xfe007e00fe007e00 81ff7fff81ff7fff fe007e00fe007e00 => 7fffe0007fffe000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff7e0081ff7e00, vec_xb[0] = 0xffff7e00ffff7e00 81ff7e0081ff7e00 ffff7e00ffff7e00 => 7fc000007fc00000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff01ff81ff01ff, vec_xb[0] = 0xfe007e00fe007e00 81ff01ff81ff01ff fe007e00fe007e00 => 37ff800037ff8000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x81ff000081ff0000, vec_xb[0] = 0xffff7e00ffff7e00 81ff000081ff0000 ffff7e00ffff7e00 => 0000000000000000 7fc000007fc00000
+xvcvhpsp vec_xb[1] = 0x8000ffff8000ffff, vec_xb[0] = 0x7fff00007fff 8000ffff8000ffff 00007fff00007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000fe008000fe00, vec_xb[0] = 0x1ff7fff01ff7fff 8000fe008000fe00 01ff7fff01ff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000ffff8000ffff, vec_xb[0] = 0x7e007fff7e007fff 8000ffff8000ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000fe008000fe00, vec_xb[0] = 0x7fff7fff7fff7fff 8000fe008000fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000ffff8000ffff, vec_xb[0] = 0x7e007fff7e007fff 8000ffff8000ffff 7e007fff7e007fff => ffffe000ffffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000fe008000fe00, vec_xb[0] = 0x7fff7fff7fff7fff 8000fe008000fe00 7fff7fff7fff7fff => ffc00000ffc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x800081ff800081ff, vec_xb[0] = 0x7e007fff7e007fff 800081ff800081ff 7e007fff7e007fff => b7ff8000b7ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000800080008000, vec_xb[0] = 0x7fff7fff7fff7fff 8000800080008000 7fff7fff7fff7fff => 8000000080000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007fff80007fff, vec_xb[0] = 0x80007fff80007fff 80007fff80007fff 80007fff80007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007e0080007e00, vec_xb[0] = 0x81ff7fff81ff7fff 80007e0080007e00 81ff7fff81ff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007fff80007fff, vec_xb[0] = 0xfe007ffffe007fff 80007fff80007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007e0080007e00, vec_xb[0] = 0xffff7fffffff7fff 80007e0080007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007fff80007fff, vec_xb[0] = 0xfe007ffffe007fff 80007fff80007fff fe007ffffe007fff => 7fffe0007fffe000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x80007e0080007e00, vec_xb[0] = 0xffff7fffffff7fff 80007e0080007e00 ffff7fffffff7fff => 7fc000007fc00000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x800001ff800001ff, vec_xb[0] = 0xfe007ffffe007fff 800001ff800001ff fe007ffffe007fff => 37ff800037ff8000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x8000000080000000, vec_xb[0] = 0xffff7fffffff7fff 8000000080000000 ffff7fffffff7fff => 0000000000000000 7fffe0007fffe000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x800000008000 7fffffff7fffffff 0000800000008000 => ffffe000ffffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x1ff800001ff8000 7ffffe007ffffe00 01ff800001ff8000 => ffc00000ffc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e0080007e008000 7fffffff7fffffff 7e0080007e008000 => ffffe000ffffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7fff80007fff8000 7ffffe007ffffe00 7fff80007fff8000 => ffc00000ffc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e0080007e008000 7fffffff7fffffff 7e0080007e008000 => ffffe000ffffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7fff80007fff8000 7ffffe007ffffe00 7fff80007fff8000 => ffc00000ffc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff81ff7fff81ff, vec_xb[0] = 0x7e0080007e008000 7fff81ff7fff81ff 7e0080007e008000 => b7ff8000b7ff8000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff80007fff8000, vec_xb[0] = 0x7fff80007fff8000 7fff80007fff8000 7fff80007fff8000 => 8000000080000000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0x8000800080008000 7fff7fff7fff7fff 8000800080008000 => 7fffe0007fffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0x81ff800081ff8000 7fff7e007fff7e00 81ff800081ff8000 => 7fc000007fc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe008000fe008000 7fff7fff7fff7fff fe008000fe008000 => 7fffe0007fffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xffff8000ffff8000 7fff7e007fff7e00 ffff8000ffff8000 => 7fc000007fc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe008000fe008000 7fff7fff7fff7fff fe008000fe008000 => 7fffe0007fffe000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xffff8000ffff8000 7fff7e007fff7e00 ffff8000ffff8000 => 7fc000007fc00000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff01ff7fff01ff, vec_xb[0] = 0xfe008000fe008000 7fff01ff7fff01ff fe008000fe008000 => 37ff800037ff8000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff0000, vec_xb[0] = 0xffff8000ffff8000 7fff00007fff0000 ffff8000ffff8000 => 0000000000000000 8000000080000000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x81ff000081ff 7e00ffff7e00ffff 000081ff000081ff => ffffe000ffffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x1ff81ff01ff81ff 7e00fe007e00fe00 01ff81ff01ff81ff => ffc00000ffc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e0081ff7e0081ff 7e00ffff7e00ffff 7e0081ff7e0081ff => ffffe000ffffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fff81ff7fff81ff 7e00fe007e00fe00 7fff81ff7fff81ff => ffc00000ffc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e0081ff7e0081ff 7e00ffff7e00ffff 7e0081ff7e0081ff => ffffe000ffffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fff81ff7fff81ff 7e00fe007e00fe00 7fff81ff7fff81ff => ffc00000ffc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e0081ff7e0081ff, vec_xb[0] = 0x7e0081ff7e0081ff 7e0081ff7e0081ff 7e0081ff7e0081ff => b7ff8000b7ff8000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e0080007e008000, vec_xb[0] = 0x7fff81ff7fff81ff 7e0080007e008000 7fff81ff7fff81ff => 8000000080000000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0x800081ff800081ff 7e007fff7e007fff 800081ff800081ff => 7fffe0007fffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0x81ff81ff81ff81ff 7e007e007e007e00 81ff81ff81ff81ff => 7fc000007fc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe0081fffe0081ff 7e007fff7e007fff fe0081fffe0081ff => 7fffe0007fffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffff81ffffff81ff 7e007e007e007e00 ffff81ffffff81ff => 7fc000007fc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe0081fffe0081ff 7e007fff7e007fff fe0081fffe0081ff => 7fffe0007fffe000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffff81ffffff81ff 7e007e007e007e00 ffff81ffffff81ff => 7fc000007fc00000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e0001ff7e0001ff, vec_xb[0] = 0xfe0081fffe0081ff 7e0001ff7e0001ff fe0081fffe0081ff => 37ff800037ff8000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7e0000007e000000, vec_xb[0] = 0xffff81ffffff81ff 7e0000007e000000 ffff81ffffff81ff => 0000000000000000 b7ff8000b7ff8000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xfe000000fe00 7fffffff7fffffff 0000fe000000fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x1fffe0001fffe00 7ffffe007ffffe00 01fffe0001fffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e00fe007e00fe00 7fffffff7fffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7ffffe007ffffe00 7ffffe007ffffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e00fe007e00fe00 7fffffff7fffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7ffffe007ffffe00 7ffffe007ffffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff81ff7fff81ff, vec_xb[0] = 0x7e00fe007e00fe00 7fff81ff7fff81ff 7e00fe007e00fe00 => b7ff8000b7ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff80007fff8000, vec_xb[0] = 0x7ffffe007ffffe00 7fff80007fff8000 7ffffe007ffffe00 => 8000000080000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0x8000fe008000fe00 7fff7fff7fff7fff 8000fe008000fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0x81fffe0081fffe00 7fff7e007fff7e00 81fffe0081fffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff7fff7fff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xfffffe00fffffe00 7fff7e007fff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff7fff7fff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xfffffe00fffffe00 7fff7e007fff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff01ff7fff01ff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff01ff7fff01ff fe00fe00fe00fe00 => 37ff800037ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff0000, vec_xb[0] = 0xfffffe00fffffe00 7fff00007fff0000 fffffe00fffffe00 => 0000000000000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0xffff0000ffff 7e00ffff7e00ffff 0000ffff0000ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x1ffffff01ffffff 7e00fe007e00fe00 01ffffff01ffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e00ffff7e00ffff 7e00ffff7e00ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fffffff7fffffff 7e00fe007e00fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e00ffff7e00ffff 7e00ffff7e00ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fffffff7fffffff 7e00fe007e00fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0081ff7e0081ff, vec_xb[0] = 0x7e00ffff7e00ffff 7e0081ff7e0081ff 7e00ffff7e00ffff => b7ff8000b7ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0080007e008000, vec_xb[0] = 0x7fffffff7fffffff 7e0080007e008000 7fffffff7fffffff => 8000000080000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0x8000ffff8000ffff 7e007fff7e007fff 8000ffff8000ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0x81ffffff81ffffff 7e007e007e007e00 81ffffff81ffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe00fffffe00ffff 7e007fff7e007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffffffffffffffff 7e007e007e007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe00fffffe00ffff 7e007fff7e007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffffffffffffffff 7e007e007e007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0001ff7e0001ff, vec_xb[0] = 0xfe00fffffe00ffff 7e0001ff7e0001ff fe00fffffe00ffff => 37ff800037ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e000000, vec_xb[0] = 0xffffffffffffffff 7e0000007e000000 ffffffffffffffff => 0000000000000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xfe000000fe00 7fffffff7fffffff 0000fe000000fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x1fffe0001fffe00 7ffffe007ffffe00 01fffe0001fffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e00fe007e00fe00 7fffffff7fffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7ffffe007ffffe00 7ffffe007ffffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7e00fe007e00fe00 7fffffff7fffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7ffffe007ffffe00, vec_xb[0] = 0x7ffffe007ffffe00 7ffffe007ffffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff81ff7fff81ff, vec_xb[0] = 0x7e00fe007e00fe00 7fff81ff7fff81ff 7e00fe007e00fe00 => b7ff8000b7ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff80007fff8000, vec_xb[0] = 0x7ffffe007ffffe00 7fff80007fff8000 7ffffe007ffffe00 => 8000000080000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0x8000fe008000fe00 7fff7fff7fff7fff 8000fe008000fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0x81fffe0081fffe00 7fff7e007fff7e00 81fffe0081fffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff7fff7fff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xfffffe00fffffe00 7fff7e007fff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7fff7fff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff7fff7fff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff7e007fff7e00, vec_xb[0] = 0xfffffe00fffffe00 7fff7e007fff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff01ff7fff01ff, vec_xb[0] = 0xfe00fe00fe00fe00 7fff01ff7fff01ff fe00fe00fe00fe00 => 37ff800037ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff0000, vec_xb[0] = 0xfffffe00fffffe00 7fff00007fff0000 fffffe00fffffe00 => 0000000000000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0xffff0000ffff 7e00ffff7e00ffff 0000ffff0000ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x1ffffff01ffffff 7e00fe007e00fe00 01ffffff01ffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e00ffff7e00ffff 7e00ffff7e00ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fffffff7fffffff 7e00fe007e00fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00ffff7e00ffff, vec_xb[0] = 0x7e00ffff7e00ffff 7e00ffff7e00ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e00fe007e00fe00, vec_xb[0] = 0x7fffffff7fffffff 7e00fe007e00fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0081ff7e0081ff, vec_xb[0] = 0x7e00ffff7e00ffff 7e0081ff7e0081ff 7e00ffff7e00ffff => b7ff8000b7ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0080007e008000, vec_xb[0] = 0x7fffffff7fffffff 7e0080007e008000 7fffffff7fffffff => 8000000080000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0x8000ffff8000ffff 7e007fff7e007fff 8000ffff8000ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0x81ffffff81ffffff 7e007e007e007e00 81ffffff81ffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe00fffffe00ffff 7e007fff7e007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffffffffffffffff 7e007e007e007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007fff7e007fff, vec_xb[0] = 0xfe00fffffe00ffff 7e007fff7e007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e007e007e007e00, vec_xb[0] = 0xffffffffffffffff 7e007e007e007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0001ff7e0001ff, vec_xb[0] = 0xfe00fffffe00ffff 7e0001ff7e0001ff fe00fffffe00ffff => 37ff800037ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e000000, vec_xb[0] = 0xffffffffffffffff 7e0000007e000000 ffffffffffffffff => 0000000000000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x1ffffff01ffffff, vec_xb[0] = 0xfe000000fe00 01ffffff01ffffff 0000fe000000fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1fffe0001fffe00, vec_xb[0] = 0x1fffe0001fffe00 01fffe0001fffe00 01fffe0001fffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ffffff01ffffff, vec_xb[0] = 0x7e00fe007e00fe00 01ffffff01ffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1fffe0001fffe00, vec_xb[0] = 0x7ffffe007ffffe00 01fffe0001fffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ffffff01ffffff, vec_xb[0] = 0x7e00fe007e00fe00 01ffffff01ffffff 7e00fe007e00fe00 => ffffe000ffffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1fffe0001fffe00, vec_xb[0] = 0x7ffffe007ffffe00 01fffe0001fffe00 7ffffe007ffffe00 => ffc00000ffc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff81ff01ff81ff, vec_xb[0] = 0x7e00fe007e00fe00 01ff81ff01ff81ff 7e00fe007e00fe00 => b7ff8000b7ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff800001ff8000, vec_xb[0] = 0x7ffffe007ffffe00 01ff800001ff8000 7ffffe007ffffe00 => 8000000080000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7fff01ff7fff, vec_xb[0] = 0x8000fe008000fe00 01ff7fff01ff7fff 8000fe008000fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7e0001ff7e00, vec_xb[0] = 0x81fffe0081fffe00 01ff7e0001ff7e00 81fffe0081fffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7fff01ff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 01ff7fff01ff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7e0001ff7e00, vec_xb[0] = 0xfffffe00fffffe00 01ff7e0001ff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7fff01ff7fff, vec_xb[0] = 0xfe00fe00fe00fe00 01ff7fff01ff7fff fe00fe00fe00fe00 => 7fffe0007fffe000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff7e0001ff7e00, vec_xb[0] = 0xfffffe00fffffe00 01ff7e0001ff7e00 fffffe00fffffe00 => 7fc000007fc00000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff01ff01ff01ff, vec_xb[0] = 0xfe00fe00fe00fe00 01ff01ff01ff01ff fe00fe00fe00fe00 => 37ff800037ff8000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0x1ff000001ff0000, vec_xb[0] = 0xfffffe00fffffe00 01ff000001ff0000 fffffe00fffffe00 => 0000000000000000 ffc00000ffc00000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff, vec_xb[0] = 0xffff0000ffff 0000ffff0000ffff 0000ffff0000ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe00, vec_xb[0] = 0x1ffffff01ffffff 0000fe000000fe00 01ffffff01ffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff, vec_xb[0] = 0x7e00ffff7e00ffff 0000ffff0000ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe00, vec_xb[0] = 0x7fffffff7fffffff 0000fe000000fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xffff0000ffff, vec_xb[0] = 0x7e00ffff7e00ffff 0000ffff0000ffff 7e00ffff7e00ffff => ffffe000ffffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0xfe000000fe00, vec_xb[0] = 0x7fffffff7fffffff 0000fe000000fe00 7fffffff7fffffff => ffc00000ffc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x81ff000081ff, vec_xb[0] = 0x7e00ffff7e00ffff 000081ff000081ff 7e00ffff7e00ffff => b7ff8000b7ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x800000008000, vec_xb[0] = 0x7fffffff7fffffff 0000800000008000 7fffffff7fffffff => 8000000080000000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff, vec_xb[0] = 0x8000ffff8000ffff 00007fff00007fff 8000ffff8000ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e00, vec_xb[0] = 0x81ffffff81ffffff 00007e0000007e00 81ffffff81ffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff, vec_xb[0] = 0xfe00fffffe00ffff 00007fff00007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e00, vec_xb[0] = 0xffffffffffffffff 00007e0000007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7fff00007fff, vec_xb[0] = 0xfe00fffffe00ffff 00007fff00007fff fe00fffffe00ffff => 7fffe0007fffe000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x7e0000007e00, vec_xb[0] = 0xffffffffffffffff 00007e0000007e00 ffffffffffffffff => 7fc000007fc00000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x1ff000001ff, vec_xb[0] = 0xfe00fffffe00ffff 000001ff000001ff fe00fffffe00ffff => 37ff800037ff8000 ffffe000ffffe000
+xvcvhpsp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 ffffe000ffffe000
+
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x0 ffffffffff800000 0000000000000000 => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x0 ffffffffff800000 0000000000000000 => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x0 ffffffffffffffff 0000000000000000 => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x0 ffffffffff800000 0000000000000000 => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x0 ffffffff807fffff 0000000000000000 => 0000ffff00008000 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x0 ffffffff80000000 0000000000000000 => 0000ffff00008000 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x0 7fffffff7fffffff 0000000000000000 => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x0 7f8000007f800000 0000000000000000 => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x0 7fffffff7fffffff 0000000000000000 => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x0 7f8000007f800000 0000000000000000 => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x0 7fffffff7fffffff 0000000000000000 => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x0 7f8000007f800000 0000000000000000 => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x0 007fffff007fffff 0000000000000000 => 0000000000000000 0000000000000000
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x0 0000000000000000 0000000000000000 => 0000000000000000 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffff007fffff ffffffffffffffff 007fffff007fffff => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffff007fffff ffffffffff800000 007fffff007fffff => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffff007fffff ffffffffffffffff 007fffff007fffff => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffff007fffff ffffffffff800000 007fffff007fffff => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffff007fffff ffffffffffffffff 007fffff007fffff => 0000ffff0000ffff 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffff007fffff ffffffffff800000 007fffff007fffff => 0000ffff0000fc00 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7fffff007fffff ffffffff807fffff 007fffff007fffff => 0000ffff00008000 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7fffff007fffff ffffffff80000000 007fffff007fffff => 0000ffff00008000 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffff007fffff 7fffffff7fffffff 007fffff007fffff => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffff007fffff 7f8000007f800000 007fffff007fffff => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffff007fffff 7fffffff7fffffff 007fffff007fffff => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffff007fffff 7f8000007f800000 007fffff007fffff => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffff007fffff 7fffffff7fffffff 007fffff007fffff => 00007fff00007fff 0000000000000000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffff007fffff 7f8000007f800000 007fffff007fffff => 00007c0000007c00 0000000000000000
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7fffff007fffff 007fffff007fffff 007fffff007fffff => 0000000000000000 0000000000000000
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7fffff007fffff 0000000000000000 007fffff007fffff => 0000000000000000 0000000000000000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7f8000007f800000 ffffffff807fffff 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7f8000007f800000 ffffffff80000000 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7f8000007f800000 007fffff007fffff 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7f8000007f800000 0000000000000000 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7fffffff7fffffff ffffffff807fffff 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7fffffff7fffffff ffffffff80000000 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7fffffff7fffffff 007fffff007fffff 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7fffffff7fffffff 0000000000000000 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7f8000007f800000 ffffffff807fffff 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7f8000007f800000 ffffffff80000000 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7f8000007f800000 007fffff007fffff 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7f8000007f800000 0000000000000000 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7fffffff7fffffff ffffffff807fffff 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7fffffff7fffffff ffffffff80000000 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7fffffff7fffffff 007fffff007fffff 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7fffffff7fffffff 0000000000000000 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7f8000007f800000 ffffffffffffffff 7f8000007f800000 => 0000ffff0000ffff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7f8000007f800000 ffffffffff800000 7f8000007f800000 => 0000ffff0000fc00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7f8000007f800000 ffffffff807fffff 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7f8000007f800000 ffffffff80000000 7f8000007f800000 => 0000ffff00008000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7f8000007f800000 7fffffff7fffffff 7f8000007f800000 => 00007fff00007fff 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7f8000007f800000 7f8000007f800000 7f8000007f800000 => 00007c0000007c00 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7f8000007f800000 007fffff007fffff 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7f8000007f800000 0000000000000000 7f8000007f800000 => 0000000000000000 00007c0000007c00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0x7fffffff7fffffff ffffffffffffffff 7fffffff7fffffff => 0000ffff0000ffff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0x7fffffff7fffffff ffffffffff800000 7fffffff7fffffff => 0000ffff0000fc00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0x7fffffff7fffffff ffffffff807fffff 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0x7fffffff7fffffff ffffffff80000000 7fffffff7fffffff => 0000ffff00008000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0x7fffffff7fffffff 7fffffff7fffffff 7fffffff7fffffff => 00007fff00007fff 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0x7fffffff7fffffff 7f8000007f800000 7fffffff7fffffff => 00007c0000007c00 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0x7fffffff7fffffff 007fffff007fffff 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0x7fffffff7fffffff 0000000000000000 7fffffff7fffffff => 0000000000000000 00007fff00007fff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff80000000 ffffffffffffffff ffffffff80000000 => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff80000000 ffffffffff800000 ffffffff80000000 => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff80000000 ffffffffffffffff ffffffff80000000 => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff80000000 ffffffffff800000 ffffffff80000000 => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff80000000 ffffffffffffffff ffffffff80000000 => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff80000000 ffffffffff800000 ffffffff80000000 => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffff80000000 ffffffff807fffff ffffffff80000000 => 0000ffff00008000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffff80000000 ffffffff80000000 ffffffff80000000 => 0000ffff00008000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff80000000 7fffffff7fffffff ffffffff80000000 => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff80000000 7f8000007f800000 ffffffff80000000 => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff80000000 7fffffff7fffffff ffffffff80000000 => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff80000000 7f8000007f800000 ffffffff80000000 => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff80000000 7fffffff7fffffff ffffffff80000000 => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff80000000 7f8000007f800000 ffffffff80000000 => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffff80000000 007fffff007fffff ffffffff80000000 => 0000000000000000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffff80000000 0000000000000000 ffffffff80000000 => 0000000000000000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff807fffff ffffffffffffffff ffffffff807fffff => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff807fffff ffffffffff800000 ffffffff807fffff => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff807fffff ffffffffffffffff ffffffff807fffff => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff807fffff ffffffffff800000 ffffffff807fffff => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffff807fffff ffffffffffffffff ffffffff807fffff => 0000ffff0000ffff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffff807fffff ffffffffff800000 ffffffff807fffff => 0000ffff0000fc00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffff807fffff ffffffff807fffff ffffffff807fffff => 0000ffff00008000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffff807fffff ffffffff80000000 ffffffff807fffff => 0000ffff00008000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff807fffff 7fffffff7fffffff ffffffff807fffff => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff807fffff 7f8000007f800000 ffffffff807fffff => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff807fffff 7fffffff7fffffff ffffffff807fffff => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff807fffff 7f8000007f800000 ffffffff807fffff => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffff807fffff 7fffffff7fffffff ffffffff807fffff => 00007fff00007fff 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffff807fffff 7f8000007f800000 ffffffff807fffff => 00007c0000007c00 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffff807fffff 007fffff007fffff ffffffff807fffff => 0000000000000000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffff807fffff 0000000000000000 ffffffff807fffff => 0000000000000000 0000ffff00008000
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffff800000 ffffffff807fffff ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffff800000 ffffffff80000000 ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffff800000 007fffff007fffff ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffff800000 0000000000000000 ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffffffffff ffffffff807fffff ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffffffffff ffffffff80000000 ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffffffffff 007fffff007fffff ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffff800000 ffffffff807fffff ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffff800000 ffffffff80000000 ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffff800000 007fffff007fffff ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffff800000 0000000000000000 ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffffffffff ffffffff807fffff ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffffffffff ffffffff80000000 ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffffffffff 007fffff007fffff ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffff800000 ffffffffffffffff ffffffffff800000 => 0000ffff0000ffff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffff800000 ffffffffff800000 ffffffffff800000 => 0000ffff0000fc00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffff800000 ffffffff807fffff ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffff800000 ffffffff80000000 ffffffffff800000 => 0000ffff00008000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffff800000 7fffffff7fffffff ffffffffff800000 => 00007fff00007fff 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffff800000 7f8000007f800000 ffffffffff800000 => 00007c0000007c00 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffff800000 007fffff007fffff ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffff800000 0000000000000000 ffffffffff800000 => 0000000000000000 0000ffff0000fc00
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffffffffff, vec_xb[0] = 0xffffffffffffffff ffffffffffffffff ffffffffffffffff => 0000ffff0000ffff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffffff800000, vec_xb[0] = 0xffffffffffffffff ffffffffff800000 ffffffffffffffff => 0000ffff0000fc00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff807fffff, vec_xb[0] = 0xffffffffffffffff ffffffff807fffff ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0xffffffff80000000, vec_xb[0] = 0xffffffffffffffff ffffffff80000000 ffffffffffffffff => 0000ffff00008000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffffff7fffffff, vec_xb[0] = 0xffffffffffffffff 7fffffff7fffffff ffffffffffffffff => 00007fff00007fff 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f8000007f800000 ffffffffffffffff => 00007c0000007c00 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffffffffff 007fffff007fffff ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 0000ffff0000ffff
+
+All done. Tested 53 different instructions
+ppc dfp significance:
+Test instruction group [ppc dfp significance]
+dtstsfi significance(0x00) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x04) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x08) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x10) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x18) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x20) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x30) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x3f) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x00) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x04) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x08) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x10) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x18) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x20) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x30) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x3f) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x00) +Finite 9999999999999999 * 10 ^ 369 (GT) (4)
+dtstsfi significance(0x04) +Finite 9999999999999999 * 10 ^ 369 (LT) (8)
+dtstsfi significance(0x08) +Finite 9999999999999999 * 10 ^ 369 (LT) (8)
+dtstsfi significance(0x10) +Finite 9999999999999999 * 10 ^ 369 (EQ) (2)
+dtstsfi significance(0x18) +Finite 9999999999999999 * 10 ^ 369 (GT) (4)
+dtstsfi significance(0x20) +Finite 9999999999999999 * 10 ^ 369 (GT) (4)
+dtstsfi significance(0x30) +Finite 9999999999999999 * 10 ^ 369 (GT) (4)
+dtstsfi significance(0x3f) +Finite 9999999999999999 * 10 ^ 369 (GT) (4)
+dtstsfi significance(0x00) -SNaN (SO) (1)
+dtstsfi significance(0x04) -SNaN (SO) (1)
+dtstsfi significance(0x08) -SNaN (SO) (1)
+dtstsfi significance(0x10) -SNaN (SO) (1)
+dtstsfi significance(0x18) -SNaN (SO) (1)
+dtstsfi significance(0x20) -SNaN (SO) (1)
+dtstsfi significance(0x30) -SNaN (SO) (1)
+dtstsfi significance(0x3f) -SNaN (SO) (1)
+
+dtstsfiq significance(0x00) +Finite 001 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x04) +Finite 001 * 10 ^ 0 (LT) (8)
+dtstsfiq significance(0x08) +Finite 001 * 10 ^ 0 (LT) (8)
+dtstsfiq significance(0x10) +Finite 001 * 10 ^ 0 (LT) (8)
+dtstsfiq significance(0x18) +Finite 001 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x20) +Finite 001 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x30) +Finite 001 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x3f) +Finite 001 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x00) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x04) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x08) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x10) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x18) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x20) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x30) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x3f) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x00) -Finite 0 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x04) -Finite 0 * 10 ^ 0 (LT) (8)
+dtstsfiq significance(0x08) -Finite 0 * 10 ^ 0 (LT) (8)
+dtstsfiq significance(0x10) -Finite 0 * 10 ^ 0 (LT) (8)
+dtstsfiq significance(0x18) -Finite 0 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x20) -Finite 0 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x30) -Finite 0 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x3f) -Finite 0 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x00) -QNaN (GT) (4)
+dtstsfiq significance(0x04) -QNaN (LT) (8)
+dtstsfiq significance(0x08) -QNaN (LT) (8)
+dtstsfiq significance(0x10) -QNaN (LT) (8)
+dtstsfiq significance(0x18) -QNaN (LT) (8)
+dtstsfiq significance(0x20) -QNaN (GT) (4)
+dtstsfiq significance(0x30) -QNaN (GT) (4)
+dtstsfiq significance(0x3f) -QNaN (GT) (4)
+dtstsfiq significance(0x00) +SNaN (SO) (1)
+dtstsfiq significance(0x04) +SNaN (SO) (1)
+dtstsfiq significance(0x08) +SNaN (SO) (1)
+dtstsfiq significance(0x10) +SNaN (SO) (1)
+dtstsfiq significance(0x18) +SNaN (SO) (1)
+dtstsfiq significance(0x20) +SNaN (SO) (1)
+dtstsfiq significance(0x30) +SNaN (SO) (1)
+dtstsfiq significance(0x3f) +SNaN (SO) (1)
+dtstsfiq significance(0x00) -inf (GT) (4)
+dtstsfiq significance(0x04) -inf (LT) (8)
+dtstsfiq significance(0x08) -inf (LT) (8)
+dtstsfiq significance(0x10) -inf (LT) (8)
+dtstsfiq significance(0x18) -inf (GT) (4)
+dtstsfiq significance(0x20) -inf (GT) (4)
+dtstsfiq significance(0x30) -inf (GT) (4)
+dtstsfiq significance(0x3f) -inf (GT) (4)
+dtstsfiq significance(0x00) +Finite 9637219475339437290889339376194061 * 10 ^ 2421 (GT) (4)
+dtstsfiq significance(0x04) +Finite 9637219475339437290889339376194061 * 10 ^ 2421 (LT) (8)
+dtstsfiq significance(0x08) +Finite 9637219475339437290889339376194061 * 10 ^ 2421 (LT) (8)
+dtstsfiq significance(0x10) +Finite 9637219475339437290889339376194061 * 10 ^ 2421 (LT) (8)
+dtstsfiq significance(0x18) +Finite 9637219475339437290889339376194061 * 10 ^ 2421 (LT) (8)
+dtstsfiq significance(0x20) +Finite 9637219475339437290889339376194061 * 10 ^ 2421 (LT) (8)
+dtstsfiq significance(0x30) +Finite 9637219475339437290889339376194061 * 10 ^ 2421 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 9637219475339437290889339376194061 * 10 ^ 2421 (LT) (8)
+dtstsfiq significance(0x00) +Finite 8436795270305626240000000000000000 * 10 ^ 4445 (GT) (4)
+dtstsfiq significance(0x04) +Finite 8436795270305626240000000000000000 * 10 ^ 4445 (LT) (8)
+dtstsfiq significance(0x08) +Finite 8436795270305626240000000000000000 * 10 ^ 4445 (LT) (8)
+dtstsfiq significance(0x10) +Finite 8436795270305626240000000000000000 * 10 ^ 4445 (LT) (8)
+dtstsfiq significance(0x18) +Finite 8436795270305626240000000000000000 * 10 ^ 4445 (LT) (8)
+dtstsfiq significance(0x20) +Finite 8436795270305626240000000000000000 * 10 ^ 4445 (LT) (8)
+dtstsfiq significance(0x30) +Finite 8436795270305626240000000000000000 * 10 ^ 4445 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 8436795270305626240000000000000000 * 10 ^ 4445 (LT) (8)
+dtstsfiq significance(0x00) +Finite 8516619099319546758274873667198099 * 10 ^ -3659 (GT) (4)
+dtstsfiq significance(0x04) +Finite 8516619099319546758274873667198099 * 10 ^ -3659 (LT) (8)
+dtstsfiq significance(0x08) +Finite 8516619099319546758274873667198099 * 10 ^ -3659 (LT) (8)
+dtstsfiq significance(0x10) +Finite 8516619099319546758274873667198099 * 10 ^ -3659 (LT) (8)
+dtstsfiq significance(0x18) +Finite 8516619099319546758274873667198099 * 10 ^ -3659 (LT) (8)
+dtstsfiq significance(0x20) +Finite 8516619099319546758274873667198099 * 10 ^ -3659 (LT) (8)
+dtstsfiq significance(0x30) +Finite 8516619099319546758274873667198099 * 10 ^ -3659 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 8516619099319546758274873667198099 * 10 ^ -3659 (LT) (8)
+dtstsfiq significance(0x00) +Finite 9426619273000006911269331445758469 * 10 ^ 2405 (GT) (4)
+dtstsfiq significance(0x04) +Finite 9426619273000006911269331445758469 * 10 ^ 2405 (LT) (8)
+dtstsfiq significance(0x08) +Finite 9426619273000006911269331445758469 * 10 ^ 2405 (LT) (8)
+dtstsfiq significance(0x10) +Finite 9426619273000006911269331445758469 * 10 ^ 2405 (LT) (8)
+dtstsfiq significance(0x18) +Finite 9426619273000006911269331445758469 * 10 ^ 2405 (LT) (8)
+dtstsfiq significance(0x20) +Finite 9426619273000006911269331445758469 * 10 ^ 2405 (LT) (8)
+dtstsfiq significance(0x30) +Finite 9426619273000006911269331445758469 * 10 ^ 2405 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 9426619273000006911269331445758469 * 10 ^ 2405 (LT) (8)
+dtstsfiq significance(0x00) +Finite 9627844232161376391889305640000000 * 10 ^ 357 (GT) (4)
+dtstsfiq significance(0x04) +Finite 9627844232161376391889305640000000 * 10 ^ 357 (LT) (8)
+dtstsfiq significance(0x08) +Finite 9627844232161376391889305640000000 * 10 ^ 357 (LT) (8)
+dtstsfiq significance(0x10) +Finite 9627844232161376391889305640000000 * 10 ^ 357 (LT) (8)
+dtstsfiq significance(0x18) +Finite 9627844232161376391889305640000000 * 10 ^ 357 (LT) (8)
+dtstsfiq significance(0x20) +Finite 9627844232161376391889305640000000 * 10 ^ 357 (LT) (8)
+dtstsfiq significance(0x30) +Finite 9627844232161376391889305640000000 * 10 ^ 357 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 9627844232161376391889305640000000 * 10 ^ 357 (LT) (8)
+dtstsfiq significance(0x00) +Finite 8516619099309516718272364663217666 * 10 ^ -3659 (GT) (4)
+dtstsfiq significance(0x04) +Finite 8516619099309516718272364663217666 * 10 ^ -3659 (LT) (8)
+dtstsfiq significance(0x08) +Finite 8516619099309516718272364663217666 * 10 ^ -3659 (LT) (8)
+dtstsfiq significance(0x10) +Finite 8516619099309516718272364663217666 * 10 ^ -3659 (LT) (8)
+dtstsfiq significance(0x18) +Finite 8516619099309516718272364663217666 * 10 ^ -3659 (LT) (8)
+dtstsfiq significance(0x20) +Finite 8516619099309516718272364663217666 * 10 ^ -3659 (LT) (8)
+dtstsfiq significance(0x30) +Finite 8516619099309516718272364663217666 * 10 ^ -3659 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 8516619099309516718272364663217666 * 10 ^ -3659 (LT) (8)
+
+All done. Tested 55 different instructions
+ppc bcd misc:
+Test instruction group [ppc bcd misc]
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (SO) (1) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (SO) (1) xt:0000000000000000 0000000000000000
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+bcdcfsq. p1 xa:000000000000000c 0000000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdcfsq. p1 xa:000000000000000c 0000000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:0005634002748764 707957313110016f(?04)
+
+
+All done. Tested 84 different instructions
+ppc noop misc:
+Test instruction group [ppc noop misc]
+wait =>
+
+All done. Tested 85 different instructions
+ppc addpc_misc:
+Test instruction group [ppc addpc_misc]
+addpcis 0000000000000000 => 000000001000341c
+addpcis 0000000000000001 => 0000000010013424
+addpcis 0000000000000002 => 000000001002342c
+addpcis 0000000000000003 => 0000000010403434
+addpcis 0000000000000004 => 000000001800343c
+addpcis 0000000000000005 => 0000000030003444
+addpcis 0000000000000006 => 000000008fff344c
+addpcis 0000000000000007 => ffffffff90003454
+addpcis 0000000000000008 => 000000001000345c
+addpcis 0000000000000009 => 000000000fff3464
+addpcis 000000000000000a => 000000000ffe346c
+addpcis 000000000000000b => 000000000fc03474
+addpcis 000000000000000c => 000000000800347c
+addpcis 000000000000000d => fffffffff0003484
+addpcis 000000000000000e => ffffffff9001348c
+addpcis 000000000000000f => ffffffff90003494
+
+subpcis 0000000000000000 => 0000000010003518
+subpcis 0000000000000001 => 000000000fff3520
+subpcis 0000000000000002 => 000000000ffe3528
+subpcis 0000000000000003 => 000000000fc03530
+subpcis 0000000000000004 => 0000000008003538
+subpcis 0000000000000005 => fffffffff0003540
+subpcis 0000000000000006 => ffffffff90013548
+subpcis 0000000000000007 => ffffffff90003550
+subpcis 0000000000000008 => 0000000010003558
+subpcis 0000000000000009 => 0000000010013560
+subpcis 000000000000000a => 0000000010023568
+subpcis 000000000000000b => 0000000010403570
+subpcis 000000000000000c => 0000000010803578
+subpcis 000000000000000d => 0000000012003580
+subpcis 000000000000000e => 000000008fff3588
+subpcis 000000000000000f => ffffffff90003590
+
+All done. Tested 87 different instructions
diff --git a/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
new file mode 100644
index 0000000..35a4e99
--- /dev/null
+++ b/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
@@ -0,0 +1,33439 @@
+PPC integer arith instructions with two args:
+Test instruction group [PPC integer arith instructions with two args]
+modsw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+modsw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+modsw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000)
+modsw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000)
+modsw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+modsw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000)
+modsw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+modsw ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000)
+modsw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+
+moduw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+moduw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+moduw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000)
+moduw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000)
+moduw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+moduw 0000001cbe991def, ffffffffffffffff => 00000000be991def (00000000)
+moduw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+moduw ffffffffffffffff, 0000001cbe991def => 000000004166e210 (00000000)
+moduw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+
+modsd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+modsd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+modsd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000)
+modsd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000)
+modsd 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+modsd 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000)
+modsd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+modsd ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000)
+modsd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+
+modud 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+modud 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+modud 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000)
+modud 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000)
+modud 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+modud 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000)
+modud ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+modud ffffffffffffffff, 0000001cbe991def => 000000043eb0c0b2 (00000000)
+modud ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+
+All done. Tested 4 different instructions
+ppc one argument plus shift:
+Test instruction group [ppc one argument plus shift]
+extswsli aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff
+extswsli 5152535455565758 5152535455565758 0 ffffffffffffffff => 5152535455565758 5152535455565758 0 ffffffffffffffff
+extswsli 0000000000000000 0000000000000000 0 ffffffffffffffff => 0000000000000000 0000000000000000 0 ffffffffffffffff
+extswsli ffaa5599113377cc ffaa5599113377cc 0 ffffffffffffffff => ffaa5599113377cc ffaa5599113377cc 0 ffffffffffffffff
+extswsli ffffffffffffffff ffffffffffffffff 0 aaaaaaaaaaaaaaaa => ffffffffffffffff ffffffffffffffff 0 aaaaaaaaaaaaaaaa
+extswsli 5152535455565758 5152535455565758 0 aaaaaaaaaaaaaaaa => 5152535455565758 5152535455565758 0 aaaaaaaaaaaaaaaa
+extswsli 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa => 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa
+extswsli ffaa5599113377cc ffaa5599113377cc 0 aaaaaaaaaaaaaaaa => ffaa5599113377cc ffaa5599113377cc 0 aaaaaaaaaaaaaaaa
+extswsli ffffffffffffffff ffffffffffffffff 0 5152535455565758 => ffffffffffffffff ffffffffffffffff 0 5152535455565758
+extswsli aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 5152535455565758 => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 5152535455565758
+extswsli 0000000000000000 0000000000000000 0 5152535455565758 => 0000000000000000 0000000000000000 0 5152535455565758
+extswsli ffaa5599113377cc ffaa5599113377cc 0 5152535455565758 => ffaa5599113377cc ffaa5599113377cc 0 5152535455565758
+extswsli ffffffffffffffff ffffffffffffffff 0 0000000000000000 => ffffffffffffffff ffffffffffffffff 0 0000000000000000
+extswsli aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 0000000000000000 => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 0000000000000000
+extswsli 5152535455565758 5152535455565758 0 0000000000000000 => 5152535455565758 5152535455565758 0 0000000000000000
+extswsli ffaa5599113377cc ffaa5599113377cc 0 0000000000000000 => ffaa5599113377cc ffaa5599113377cc 0 0000000000000000
+extswsli ffffffffffffffff ffffffffffffffff 0 ffaa5599113377cc => ffffffffffffffff ffffffffffffffff 0 ffaa5599113377cc
+extswsli aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc
+extswsli 5152535455565758 5152535455565758 0 ffaa5599113377cc => 5152535455565758 5152535455565758 0 ffaa5599113377cc
+extswsli 0000000000000000 0000000000000000 0 ffaa5599113377cc => 0000000000000000 0000000000000000 0 ffaa5599113377cc
+
+extswsli. aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff
+extswsli. 5152535455565758 5152535455565758 0 ffffffffffffffff => 5152535455565758 5152535455565758 0 ffffffffffffffff
+extswsli. 0000000000000000 0000000000000000 0 ffffffffffffffff => 0000000000000000 0000000000000000 0 ffffffffffffffff
+extswsli. ffaa5599113377cc ffaa5599113377cc 0 ffffffffffffffff => ffaa5599113377cc ffaa5599113377cc 0 ffffffffffffffff
+extswsli. ffffffffffffffff ffffffffffffffff 0 aaaaaaaaaaaaaaaa => ffffffffffffffff ffffffffffffffff 0 aaaaaaaaaaaaaaaa
+extswsli. 5152535455565758 5152535455565758 0 aaaaaaaaaaaaaaaa => 5152535455565758 5152535455565758 0 aaaaaaaaaaaaaaaa
+extswsli. 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa => 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa
+extswsli. ffaa5599113377cc ffaa5599113377cc 0 aaaaaaaaaaaaaaaa => ffaa5599113377cc ffaa5599113377cc 0 aaaaaaaaaaaaaaaa
+extswsli. ffffffffffffffff ffffffffffffffff 0 5152535455565758 => ffffffffffffffff ffffffffffffffff 0 5152535455565758
+extswsli. aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 5152535455565758 => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 5152535455565758
+extswsli. 0000000000000000 0000000000000000 0 5152535455565758 => 0000000000000000 0000000000000000 0 5152535455565758
+extswsli. ffaa5599113377cc ffaa5599113377cc 0 5152535455565758 => ffaa5599113377cc ffaa5599113377cc 0 5152535455565758
+extswsli. ffffffffffffffff ffffffffffffffff 0 0000000000000000 => ffffffffffffffff ffffffffffffffff 0 0000000000000000
+extswsli. aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 0000000000000000 => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 0000000000000000
+extswsli. 5152535455565758 5152535455565758 0 0000000000000000 => 5152535455565758 5152535455565758 0 0000000000000000
+extswsli. ffaa5599113377cc ffaa5599113377cc 0 0000000000000000 => ffaa5599113377cc ffaa5599113377cc 0 0000000000000000
+extswsli. ffffffffffffffff ffffffffffffffff 0 ffaa5599113377cc => ffffffffffffffff ffffffffffffffff 0 ffaa5599113377cc
+extswsli. aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc
+extswsli. 5152535455565758 5152535455565758 0 ffaa5599113377cc => 5152535455565758 5152535455565758 0 ffaa5599113377cc
+extswsli. 0000000000000000 0000000000000000 0 ffaa5599113377cc => 0000000000000000 0000000000000000 0 ffaa5599113377cc
+
+All done. Tested 6 different instructions
+ppc three parameter ops:
+Test instruction group [ppc three parameter ops]
+maddhd 0000000000000000, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddhd 0000000000000000, 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd 0000000000000000, 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
+maddhd 0000000000000000, 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000)
+maddhd 0000000000000000, 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd 0000000000000000, 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000)
+maddhd 0000000000000000, ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+maddhd 0000000000000000, ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd 0000000000000000, ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000)
+maddhd 0000001cbe991def, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddhd 0000001cbe991def, 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd 0000001cbe991def, 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
+maddhd 0000001cbe991def, 0000001cbe991def, 0000000000000000 => 000000000000033a (00000000)
+maddhd 0000001cbe991def, 0000001cbe991def, 0000001cbe991def => 000000000000033a (00000000)
+maddhd 0000001cbe991def, 0000001cbe991def, ffffffffffffffff => 000000000000033a (00000000)
+maddhd 0000001cbe991def, ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000)
+maddhd 0000001cbe991def, ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd 0000001cbe991def, ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000)
+maddhd ffffffffffffffff, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddhd ffffffffffffffff, 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd ffffffffffffffff, 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
+maddhd ffffffffffffffff, 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000)
+maddhd ffffffffffffffff, 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd ffffffffffffffff, 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000)
+maddhd ffffffffffffffff, ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+maddhd ffffffffffffffff, ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000)
+maddhd ffffffffffffffff, ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+
+maddhdu 0000000000000000, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddhdu 0000000000000000, 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+maddhdu 0000000000000000, 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000)
+maddhdu 0000000000000000, 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000)
+maddhdu 0000000000000000, 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+maddhdu 0000000000000000, 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000)
+maddhdu 0000000000000000, ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+maddhdu 0000000000000000, ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000)
+maddhdu 0000000000000000, ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+maddhdu 0000001cbe991def, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddhdu 0000001cbe991def, 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+maddhdu 0000001cbe991def, 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000)
+maddhdu 0000001cbe991def, 0000001cbe991def, 0000000000000000 => 000000000000033a (00000000)
+maddhdu 0000001cbe991def, 0000001cbe991def, 0000001cbe991def => 000000000000033a (00000000)
+maddhdu 0000001cbe991def, 0000001cbe991def, ffffffffffffffff => 000000000000033b (00000000)
+maddhdu 0000001cbe991def, ffffffffffffffff, 0000000000000000 => 0000001cbe991dee (00000000)
+maddhdu 0000001cbe991def, ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000)
+maddhdu 0000001cbe991def, ffffffffffffffff, ffffffffffffffff => 0000001cbe991def (00000000)
+maddhdu ffffffffffffffff, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddhdu ffffffffffffffff, 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000)
+maddhdu ffffffffffffffff, 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000)
+maddhdu ffffffffffffffff, 0000001cbe991def, 0000000000000000 => 0000001cbe991dee (00000000)
+maddhdu ffffffffffffffff, 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000)
+maddhdu ffffffffffffffff, 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000)
+maddhdu ffffffffffffffff, ffffffffffffffff, 0000000000000000 => fffffffffffffffe (00000000)
+maddhdu ffffffffffffffff, ffffffffffffffff, 0000001cbe991def => fffffffffffffffe (00000000)
+maddhdu ffffffffffffffff, ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000)
+
+maddld 0000000000000000, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddld 0000000000000000, 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000)
+maddld 0000000000000000, 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
+maddld 0000000000000000, 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000)
+maddld 0000000000000000, 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000)
+maddld 0000000000000000, 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000)
+maddld 0000000000000000, ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
+maddld 0000000000000000, ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000)
+maddld 0000000000000000, ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000)
+maddld 0000001cbe991def, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddld 0000001cbe991def, 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000)
+maddld 0000001cbe991def, 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
+maddld 0000001cbe991def, 0000001cbe991def, 0000000000000000 => 3f66304b8f2e0521 (00000000)
+maddld 0000001cbe991def, 0000001cbe991def, 0000001cbe991def => 3f6630684dc72310 (00000000)
+maddld 0000001cbe991def, 0000001cbe991def, ffffffffffffffff => 3f66304b8f2e0520 (00000000)
+maddld 0000001cbe991def, ffffffffffffffff, 0000000000000000 => ffffffe34166e211 (00000000)
+maddld 0000001cbe991def, ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000)
+maddld 0000001cbe991def, ffffffffffffffff, ffffffffffffffff => ffffffe34166e210 (00000000)
+maddld ffffffffffffffff, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+maddld ffffffffffffffff, 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000)
+maddld ffffffffffffffff, 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
+maddld ffffffffffffffff, 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000)
+maddld ffffffffffffffff, 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000)
+maddld ffffffffffffffff, 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000)
+maddld ffffffffffffffff, ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000)
+maddld ffffffffffffffff, ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000)
+maddld ffffffffffffffff, ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
+
+All done. Tested 9 different instructions
+ppc count zeros:
+Test instruction group [ppc count zeros]
+cnttzw 0000000000000000 => 0000000000000020
+cnttzw 0000001cbe991def => 0000000000000000
+cnttzw ffffffffffffffff => 0000000000000000
+
+cnttzd 0000000000000000 => 0000000000000040
+cnttzd 0000001cbe991def => 0000000000000000
+cnttzd ffffffffffffffff => 0000000000000000
+
+cnttzw. 0000000000000000 => 0000000000000020 Expected cr0 to be zero, it is (40000000)
+
+cnttzw. 0000001cbe991def => 0000000000000000 Expected cr0 to be zero, it is (20000000)
+
+cnttzw. ffffffffffffffff => 0000000000000000 Expected cr0 to be zero, it is (20000000)
+
+
+cnttzd. 0000000000000000 => 0000000000000040 Expected cr0 to be zero, it is (40000000)
+
+cnttzd. 0000001cbe991def => 0000000000000000 Expected cr0 to be zero, it is (20000000)
+
+cnttzd. ffffffffffffffff => 0000000000000000 Expected cr0 to be zero, it is (20000000)
+
+
+All done. Tested 13 different instructions
+ppc set boolean:
+Test instruction group [ppc set boolean]
+setb cr_field:0 cr_value::00000000 => 0000000000000000
+setb cr_field:0 cr_value::10000000 => 0000000000000000
+setb cr_field:0 cr_value::20000000 => 0000000000000000
+setb cr_field:0 cr_value::30000000 => 0000000000000000
+setb cr_field:0 cr_value::40000000 => 0000000000000001
+setb cr_field:0 cr_value::50000000 => 0000000000000001
+setb cr_field:0 cr_value::60000000 => 0000000000000001
+setb cr_field:0 cr_value::70000000 => 0000000000000001
+setb cr_field:0 cr_value::80000000 => ffffffffffffffff
+setb cr_field:1 cr_value::00000000 => 0000000000000000
+setb cr_field:1 cr_value::01000000 => 0000000000000000
+setb cr_field:1 cr_value::02000000 => 0000000000000000
+setb cr_field:1 cr_value::03000000 => 0000000000000000
+setb cr_field:1 cr_value::04000000 => 0000000000000001
+setb cr_field:1 cr_value::05000000 => 0000000000000001
+setb cr_field:1 cr_value::06000000 => 0000000000000001
+setb cr_field:1 cr_value::07000000 => 0000000000000001
+setb cr_field:1 cr_value::08000000 => ffffffffffffffff
+setb cr_field:2 cr_value::00000000 => 0000000000000000
+setb cr_field:2 cr_value::00100000 => 0000000000000000
+setb cr_field:2 cr_value::00200000 => 0000000000000000
+setb cr_field:2 cr_value::00300000 => 0000000000000000
+setb cr_field:2 cr_value::00400000 => 0000000000000001
+setb cr_field:2 cr_value::00500000 => 0000000000000001
+setb cr_field:2 cr_value::00600000 => 0000000000000001
+setb cr_field:2 cr_value::00700000 => 0000000000000001
+setb cr_field:2 cr_value::00800000 => ffffffffffffffff
+setb cr_field:3 cr_value::00000000 => 0000000000000000
+setb cr_field:3 cr_value::00010000 => 0000000000000000
+setb cr_field:3 cr_value::00020000 => 0000000000000000
+setb cr_field:3 cr_value::00030000 => 0000000000000000
+setb cr_field:3 cr_value::00040000 => 0000000000000001
+setb cr_field:3 cr_value::00050000 => 0000000000000001
+setb cr_field:3 cr_value::00060000 => 0000000000000001
+setb cr_field:3 cr_value::00070000 => 0000000000000001
+setb cr_field:3 cr_value::00080000 => ffffffffffffffff
+setb cr_field:4 cr_value::00000000 => 0000000000000000
+setb cr_field:4 cr_value::00001000 => 0000000000000000
+setb cr_field:4 cr_value::00002000 => 0000000000000000
+setb cr_field:4 cr_value::00003000 => 0000000000000000
+setb cr_field:4 cr_value::00004000 => 0000000000000001
+setb cr_field:4 cr_value::00005000 => 0000000000000001
+setb cr_field:4 cr_value::00006000 => 0000000000000001
+setb cr_field:4 cr_value::00007000 => 0000000000000001
+setb cr_field:4 cr_value::00008000 => ffffffffffffffff
+setb cr_field:5 cr_value::00000000 => 0000000000000000
+setb cr_field:5 cr_value::00000100 => 0000000000000000
+setb cr_field:5 cr_value::00000200 => 0000000000000000
+setb cr_field:5 cr_value::00000300 => 0000000000000000
+setb cr_field:5 cr_value::00000400 => 0000000000000001
+setb cr_field:5 cr_value::00000500 => 0000000000000001
+setb cr_field:5 cr_value::00000600 => 0000000000000001
+setb cr_field:5 cr_value::00000700 => 0000000000000001
+setb cr_field:5 cr_value::00000800 => ffffffffffffffff
+setb cr_field:6 cr_value::00000000 => 0000000000000000
+setb cr_field:6 cr_value::00000010 => 0000000000000000
+setb cr_field:6 cr_value::00000020 => 0000000000000000
+setb cr_field:6 cr_value::00000030 => 0000000000000000
+setb cr_field:6 cr_value::00000040 => 0000000000000001
+setb cr_field:6 cr_value::00000050 => 0000000000000001
+setb cr_field:6 cr_value::00000060 => 0000000000000001
+setb cr_field:6 cr_value::00000070 => 0000000000000001
+setb cr_field:6 cr_value::00000080 => ffffffffffffffff
+setb cr_field:7 cr_value::00000000 => 0000000000000000
+setb cr_field:7 cr_value::00000001 => 0000000000000000
+setb cr_field:7 cr_value::00000002 => 0000000000000000
+setb cr_field:7 cr_value::00000003 => 0000000000000000
+setb cr_field:7 cr_value::00000004 => 0000000000000001
+setb cr_field:7 cr_value::00000005 => 0000000000000001
+setb cr_field:7 cr_value::00000006 => 0000000000000001
+setb cr_field:7 cr_value::00000007 => 0000000000000001
+setb cr_field:7 cr_value::00000008 => ffffffffffffffff
+
+All done. Tested 14 different instructions
+ppc char compare:
+Test instruction group [ppc char compare]
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
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+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
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+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=0 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmprb l=0 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=0 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=0 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=0 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+
+cmprb l=1 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
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+cmprb l=1 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
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+cmprb l=1 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmprb l=1 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmprb l=1 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmprb l=1 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmprb l=1 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
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+cmprb l=1 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
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+cmprb l=1 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmprb l=1 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
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+cmprb l=1 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmprb l=1 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=1 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmprb l=1 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
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+cmprb l=1 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmprb l=1 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
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+cmprb l=1 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
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+cmprb l=1 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmprb l=1 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmprb l=1 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+
+cmpeqb 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
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+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
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+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
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+cmpeqb 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x6d (m) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x36 (6) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
+cmpeqb 0x5d (]) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x67 (g) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x6d (m) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x73 (s) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x79 (y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x30 (0) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) => in range/found
+cmpeqb 0x36 (6) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x41 (A) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x47 (G) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x4d (M) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x53 (S) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2b (+) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2d (-) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x2f (/) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5b ([) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5d (]) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x60 (`) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x5f (_) (cmpeq:0x7b673a317a663930) (cmprb:src22(0-9) src21(f-z)) =>
+cmpeqb 0x61 (a) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x67 (g) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x6d (m) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x73 (s) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x79 (y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x30 (0) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x36 (6) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x41 (A) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) => in range/found
+cmpeqb 0x47 (G) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x4d (M) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x53 (S) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x59 (Y) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x20 ( ) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2b (+) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2d (-) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x2f (/) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5b ([) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
+
+All done. Tested 17 different instructions
+ppc vector scalar move to/from:
+Test instruction group [ppc vector scalar move to/from]
+mfvsrld aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa ffffffffffffffff
+mfvsrld 5152535455565758 5152535455565758 0 ffffffffffffffff => 5152535455565758 5152535455565758 5152535455565758 ffffffffffffffff
+mfvsrld 0000000000000000 0000000000000000 0 ffffffffffffffff => 0000000000000000 0000000000000000 0 ffffffffffffffff
+mfvsrld ffaa5599113377cc ffaa5599113377cc 0 ffffffffffffffff => ffaa5599113377cc ffaa5599113377cc ffaa5599113377cc ffffffffffffffff
+mfvsrld ffffffffffffffff ffffffffffffffff 0 aaaaaaaaaaaaaaaa => ffffffffffffffff ffffffffffffffff ffffffffffffffff aaaaaaaaaaaaaaaa
+mfvsrld 5152535455565758 5152535455565758 0 aaaaaaaaaaaaaaaa => 5152535455565758 5152535455565758 5152535455565758 aaaaaaaaaaaaaaaa
+mfvsrld 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa => 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa
+mfvsrld ffaa5599113377cc ffaa5599113377cc 0 aaaaaaaaaaaaaaaa => ffaa5599113377cc ffaa5599113377cc ffaa5599113377cc aaaaaaaaaaaaaaaa
+mfvsrld ffffffffffffffff ffffffffffffffff 0 5152535455565758 => ffffffffffffffff ffffffffffffffff ffffffffffffffff 5152535455565758
+mfvsrld aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 5152535455565758 => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 5152535455565758
+mfvsrld 0000000000000000 0000000000000000 0 5152535455565758 => 0000000000000000 0000000000000000 0 5152535455565758
+mfvsrld ffaa5599113377cc ffaa5599113377cc 0 5152535455565758 => ffaa5599113377cc ffaa5599113377cc ffaa5599113377cc 5152535455565758
+mfvsrld ffffffffffffffff ffffffffffffffff 0 0000000000000000 => ffffffffffffffff ffffffffffffffff ffffffffffffffff 0000000000000000
+mfvsrld aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 0000000000000000 => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0000000000000000
+mfvsrld 5152535455565758 5152535455565758 0 0000000000000000 => 5152535455565758 5152535455565758 5152535455565758 0000000000000000
+mfvsrld ffaa5599113377cc ffaa5599113377cc 0 0000000000000000 => ffaa5599113377cc ffaa5599113377cc ffaa5599113377cc 0000000000000000
+mfvsrld ffffffffffffffff ffffffffffffffff 0 ffaa5599113377cc => ffffffffffffffff ffffffffffffffff ffffffffffffffff ffaa5599113377cc
+mfvsrld aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa ffaa5599113377cc
+mfvsrld 5152535455565758 5152535455565758 0 ffaa5599113377cc => 5152535455565758 5152535455565758 5152535455565758 ffaa5599113377cc
+mfvsrld 0000000000000000 0000000000000000 0 ffaa5599113377cc => 0000000000000000 0000000000000000 0 ffaa5599113377cc
+
+mtvsrdd aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => 0000000000000000 ffffffffffffffff 0 ffffffffffffffff
+mtvsrdd 5152535455565758 5152535455565758 0 ffffffffffffffff => 0000000000000000 ffffffffffffffff 0 ffffffffffffffff
+mtvsrdd 0000000000000000 0000000000000000 0 ffffffffffffffff => 0000000000000000 ffffffffffffffff 0 ffffffffffffffff
+mtvsrdd ffaa5599113377cc ffaa5599113377cc 0 ffffffffffffffff => 0000000000000000 ffffffffffffffff 0 ffffffffffffffff
+mtvsrdd ffffffffffffffff ffffffffffffffff 0 aaaaaaaaaaaaaaaa => 0000000000000000 aaaaaaaaaaaaaaaa 0 aaaaaaaaaaaaaaaa
+mtvsrdd 5152535455565758 5152535455565758 0 aaaaaaaaaaaaaaaa => 0000000000000000 aaaaaaaaaaaaaaaa 0 aaaaaaaaaaaaaaaa
+mtvsrdd 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa => 0000000000000000 aaaaaaaaaaaaaaaa 0 aaaaaaaaaaaaaaaa
+mtvsrdd ffaa5599113377cc ffaa5599113377cc 0 aaaaaaaaaaaaaaaa => 0000000000000000 aaaaaaaaaaaaaaaa 0 aaaaaaaaaaaaaaaa
+mtvsrdd ffffffffffffffff ffffffffffffffff 0 5152535455565758 => 0000000000000000 5152535455565758 0 5152535455565758
+mtvsrdd aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 5152535455565758 => 0000000000000000 5152535455565758 0 5152535455565758
+mtvsrdd 0000000000000000 0000000000000000 0 5152535455565758 => 0000000000000000 5152535455565758 0 5152535455565758
+mtvsrdd ffaa5599113377cc ffaa5599113377cc 0 5152535455565758 => 0000000000000000 5152535455565758 0 5152535455565758
+mtvsrdd ffffffffffffffff ffffffffffffffff 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrdd aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrdd 5152535455565758 5152535455565758 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrdd ffaa5599113377cc ffaa5599113377cc 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrdd ffffffffffffffff ffffffffffffffff 0 ffaa5599113377cc => 0000000000000000 ffaa5599113377cc 0 ffaa5599113377cc
+mtvsrdd aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => 0000000000000000 ffaa5599113377cc 0 ffaa5599113377cc
+mtvsrdd 5152535455565758 5152535455565758 0 ffaa5599113377cc => 0000000000000000 ffaa5599113377cc 0 ffaa5599113377cc
+mtvsrdd 0000000000000000 0000000000000000 0 ffaa5599113377cc => 0000000000000000 ffaa5599113377cc 0 ffaa5599113377cc
+
+mtvsrws aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => ffffffffffffffff ffffffffffffffff 0 ffffffffffffffff
+mtvsrws 5152535455565758 5152535455565758 0 ffffffffffffffff => ffffffffffffffff ffffffffffffffff 0 ffffffffffffffff
+mtvsrws 0000000000000000 0000000000000000 0 ffffffffffffffff => ffffffffffffffff ffffffffffffffff 0 ffffffffffffffff
+mtvsrws ffaa5599113377cc ffaa5599113377cc 0 ffffffffffffffff => ffffffffffffffff ffffffffffffffff 0 ffffffffffffffff
+mtvsrws ffffffffffffffff ffffffffffffffff 0 aaaaaaaaaaaaaaaa => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 aaaaaaaaaaaaaaaa
+mtvsrws 5152535455565758 5152535455565758 0 aaaaaaaaaaaaaaaa => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 aaaaaaaaaaaaaaaa
+mtvsrws 0000000000000000 0000000000000000 0 aaaaaaaaaaaaaaaa => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 aaaaaaaaaaaaaaaa
+mtvsrws ffaa5599113377cc ffaa5599113377cc 0 aaaaaaaaaaaaaaaa => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 aaaaaaaaaaaaaaaa
+mtvsrws ffffffffffffffff ffffffffffffffff 0 5152535455565758 => 5556575855565758 5556575855565758 0 5152535455565758
+mtvsrws aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 5152535455565758 => 5556575855565758 5556575855565758 0 5152535455565758
+mtvsrws 0000000000000000 0000000000000000 0 5152535455565758 => 5556575855565758 5556575855565758 0 5152535455565758
+mtvsrws ffaa5599113377cc ffaa5599113377cc 0 5152535455565758 => 5556575855565758 5556575855565758 0 5152535455565758
+mtvsrws ffffffffffffffff ffffffffffffffff 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrws aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrws 5152535455565758 5152535455565758 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrws ffaa5599113377cc ffaa5599113377cc 0 0000000000000000 => 0000000000000000 0000000000000000 0 0000000000000000
+mtvsrws ffffffffffffffff ffffffffffffffff 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
+mtvsrws aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
+mtvsrws 5152535455565758 5152535455565758 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
+mtvsrws 0000000000000000 0000000000000000 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
+
+All done. Tested 20 different instructions
+ppc dfp significance:
+Test instruction group [ppc dfp significance]
+dtstsfi significance(0x00) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x04) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x08) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x10) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x18) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x20) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x30) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x3f) +Finite 0 * 10 ^ -12 (GT) (4)
+dtstsfi significance(0x00) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x04) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x08) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x10) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x18) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x20) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x30) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x3f) +Finite 001 * 10 ^ -398 (GT) (4)
+dtstsfi significance(0x00) +Finite 9999999999999999 * 10 ^ 369 (GT) (4)
+dtstsfi significance(0x04) +Finite 9999999999999999 * 10 ^ 369 (LT) (8)
+dtstsfi significance(0x08) +Finite 9999999999999999 * 10 ^ 369 (LT) (8)
+dtstsfi significance(0x10) +Finite 9999999999999999 * 10 ^ 369 (EQ) (2)
+dtstsfi significance(0x18) +Finite 9999999999999999 * 10 ^ 369 (GT) (4)
+dtstsfi significance(0x20) +Finite 9999999999999999 * 10 ^ 369 (GT) (4)
+dtstsfi significance(0x30) +Finite 9999999999999999 * 10 ^ 369 (GT) (4)
+dtstsfi significance(0x3f) +Finite 9999999999999999 * 10 ^ 369 (GT) (4)
+dtstsfi significance(0x00) -SNaN (SO) (1)
+dtstsfi significance(0x04) -SNaN (SO) (1)
+dtstsfi significance(0x08) -SNaN (SO) (1)
+dtstsfi significance(0x10) -SNaN (SO) (1)
+dtstsfi significance(0x18) -SNaN (SO) (1)
+dtstsfi significance(0x20) -SNaN (SO) (1)
+dtstsfi significance(0x30) -SNaN (SO) (1)
+dtstsfi significance(0x3f) -SNaN (SO) (1)
+
+dtstsfiq significance(0x00) +Finite 001 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x04) +Finite 001 * 10 ^ 0 (LT) (8)
+dtstsfiq significance(0x08) +Finite 001 * 10 ^ 0 (LT) (8)
+dtstsfiq significance(0x10) +Finite 001 * 10 ^ 0 (LT) (8)
+dtstsfiq significance(0x18) +Finite 001 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x20) +Finite 001 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x30) +Finite 001 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x3f) +Finite 001 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x00) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x04) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x08) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x10) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x18) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x20) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x30) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x3f) +Finite 9999999999999999999999999999999999 * 10 ^ 6111 (SO) (1)
+dtstsfiq significance(0x00) -Finite 0 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x04) -Finite 0 * 10 ^ 0 (LT) (8)
+dtstsfiq significance(0x08) -Finite 0 * 10 ^ 0 (LT) (8)
+dtstsfiq significance(0x10) -Finite 0 * 10 ^ 0 (LT) (8)
+dtstsfiq significance(0x18) -Finite 0 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x20) -Finite 0 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x30) -Finite 0 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x3f) -Finite 0 * 10 ^ 0 (GT) (4)
+dtstsfiq significance(0x00) -QNaN (GT) (4)
+dtstsfiq significance(0x04) -QNaN (LT) (8)
+dtstsfiq significance(0x08) -QNaN (LT) (8)
+dtstsfiq significance(0x10) -QNaN (LT) (8)
+dtstsfiq significance(0x18) -QNaN (LT) (8)
+dtstsfiq significance(0x20) -QNaN (GT) (4)
+dtstsfiq significance(0x30) -QNaN (GT) (4)
+dtstsfiq significance(0x3f) -QNaN (GT) (4)
+dtstsfiq significance(0x00) +SNaN (SO) (1)
+dtstsfiq significance(0x04) +SNaN (SO) (1)
+dtstsfiq significance(0x08) +SNaN (SO) (1)
+dtstsfiq significance(0x10) +SNaN (SO) (1)
+dtstsfiq significance(0x18) +SNaN (SO) (1)
+dtstsfiq significance(0x20) +SNaN (SO) (1)
+dtstsfiq significance(0x30) +SNaN (SO) (1)
+dtstsfiq significance(0x3f) +SNaN (SO) (1)
+dtstsfiq significance(0x00) -inf (GT) (4)
+dtstsfiq significance(0x04) -inf (LT) (8)
+dtstsfiq significance(0x08) -inf (LT) (8)
+dtstsfiq significance(0x10) -inf (LT) (8)
+dtstsfiq significance(0x18) -inf (GT) (4)
+dtstsfiq significance(0x20) -inf (GT) (4)
+dtstsfiq significance(0x30) -inf (GT) (4)
+dtstsfiq significance(0x3f) -inf (GT) (4)
+dtstsfiq significance(0x00) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (GT) (4)
+dtstsfiq significance(0x04) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x08) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x10) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x18) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x20) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x30) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x00) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (GT) (4)
+dtstsfiq significance(0x04) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (LT) (8)
+dtstsfiq significance(0x08) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (LT) (8)
+dtstsfiq significance(0x10) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (LT) (8)
+dtstsfiq significance(0x18) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (LT) (8)
+dtstsfiq significance(0x20) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (LT) (8)
+dtstsfiq significance(0x30) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 9437157672933646850861933435956461 * 10 ^ -1691 (LT) (8)
+dtstsfiq significance(0x00) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (GT) (4)
+dtstsfiq significance(0x04) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (LT) (8)
+dtstsfiq significance(0x08) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (LT) (8)
+dtstsfiq significance(0x10) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (LT) (8)
+dtstsfiq significance(0x18) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (LT) (8)
+dtstsfiq significance(0x20) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (GT) (4)
+dtstsfiq significance(0x30) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (GT) (4)
+dtstsfiq significance(0x3f) +Finite 9607419299315620000000315546911889 * 10 ^ -5795 (GT) (4)
+dtstsfiq significance(0x00) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (GT) (4)
+dtstsfiq significance(0x04) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x08) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x10) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x18) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x20) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x30) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 8656913073315646159276873566794274 * 10 ^ -2663 (LT) (8)
+dtstsfiq significance(0x00) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (GT) (4)
+dtstsfiq significance(0x04) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (LT) (8)
+dtstsfiq significance(0x08) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (LT) (8)
+dtstsfiq significance(0x10) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (LT) (8)
+dtstsfiq significance(0x18) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (LT) (8)
+dtstsfiq significance(0x20) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (LT) (8)
+dtstsfiq significance(0x30) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 9437157672933645758274305445956461 * 10 ^ -1691 (LT) (8)
+dtstsfiq significance(0x00) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (GT) (4)
+dtstsfiq significance(0x04) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (LT) (8)
+dtstsfiq significance(0x08) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (LT) (8)
+dtstsfiq significance(0x10) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (LT) (8)
+dtstsfiq significance(0x18) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (LT) (8)
+dtstsfiq significance(0x20) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (LT) (8)
+dtstsfiq significance(0x30) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (LT) (8)
+dtstsfiq significance(0x3f) +Finite 007950661331436195475319647159274 * 10 ^ -6176 (LT) (8)
+
+All done. Tested 22 different instructions
+ppc bcd misc:
+Test instruction group [ppc bcd misc]
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p0 xa:000000000000000c 0000000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:111111112345678c 1111111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:111111111111111c 1141111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:111111112345678c 1111111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:111111111111111c 1141111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p0 xa:111111111111111c 1111111111111111 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:111111109876544c 1111111111111111(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:222222223456789c 2222222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:222222222222222c 2252222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:222222223456789c 2222222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:222222222222222c 2252222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p0 xa:222222222222222c 2222222222222222 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:222222220987655c 2222222222222222(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:333333334567900c 3333333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:333333333333333c 3363333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:333333334567900c 3333333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:333333333333333c 3363333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:333333333333333c 3333333333333333 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:333333332098766c 3333333333333333(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:444444445679011c 4444444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:444444444444444c 4474444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:444444445679011c 4444444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:444444444444444c 4474444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:444444444444444c 4444444444444444 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:444444443209877c 4444444444444444(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:555555556790122c 5555555555555555(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:555555555555555c 5585555555555555(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:555555556790122c 5555555555555555(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:555555555555555c 5585555555555555(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:555555555555555c 5555555555555555 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:555555554320988c 5555555555555555(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:666666667901233c 6666666666666666(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:666666666666666c 6696666666666666(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:666666667901233c 6666666666666666(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:666666666666666c 6696666666666666(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:666666666666666c 6666666666666666 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:666666665432099c 6666666666666666(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:777777779012344c 7777777777777777(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:777777777777777c 7807777777777777(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:777777779012344c 7777777777777777(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:777777777777777c 7807777777777777(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:777777777777777c 7777777777777777 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:777777776543210c 7777777777777777(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
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+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:888888888888888c 8918888888888888(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
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+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:888888890123455c 8888888888888888(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:888888888888888c 8918888888888888(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:888888888888888c 8888888888888888 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:888888887654321c 8888888888888888(+|0)
+
+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
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+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
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+
+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
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+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
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+
+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:999999999999999c 9999999999999999 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:999999998765432c 9999999999999999(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111112345678c 1111111111111111(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222223456789c 2222222222222222(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333334567900c 3333333333333333(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444445679011c 4444444444444444(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555556790122c 5555555555555555(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666667901233c 6666666666666666(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777779012344c 7777777777777777(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888890123455c 8888888888888888(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
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+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000001234567c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111112345678c 1111111111111111(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222223456789c 2222222222222222(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333334567900c 3333333333333333(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444445679011c 4444444444444444(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555556790122c 5555555555555555(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666667901233c 6666666666666666(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777779012344c 7777777777777777(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888890123455c 8888888888888888(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000002469134c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000001234567c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111109876544d 1111111111111111( - )
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222220987655d 2222222222222222( - )
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333332098766d 3333333333333333( - )
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444443209877d 4444444444444444( - )
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555554320988d 5555555555555555( - )
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666665432099d 6666666666666666( - )
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777776543210d 7777777777777777( - )
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888887654321d 8888888888888888( - )
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999998765432d 9999999999999999( - )
+
+bcdadd. p0 xa:000000001234567c 0000000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111111111111c 1141111111111111(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222222222222c 2252222222222222(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333333333333c 3363333333333333(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444444444444c 4474444444444444(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555555555555c 5585555555555555(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666666666666c 6696666666666666(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777777777777c 7807777777777777(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888888888888c 8918888888888888(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000000000000c 0060000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111111111111c 1141111111111111(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222222222222c 2252222222222222(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333333333333c 3363333333333333(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444444444444c 4474444444444444(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555555555555c 5585555555555555(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666666666666c 6696666666666666(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777777777777c 7807777777777777(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888888888888c 8918888888888888(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000000000000c 0060000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111111111111d 1081111111111111( - )
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222222222222d 2192222222222222( - )
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333333333333d 3303333333333333( - )
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444444444444d 4414444444444444( - )
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555555555555d 5525555555555555( - )
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666666666666d 6636666666666666( - )
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777777777777d 7747777777777777( - )
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888888888888d 8858888888888888( - )
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999999999999d 9969999999999999( - )
+
+bcdadd. p0 xa:000000000000000c 0030000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:999999998765433c 0029999999999999(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p0 xa:000000000000000f 0000000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:111111112345678c 1111111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:111111111111111c 1141111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:111111112345678c 1111111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:111111111111111c 1141111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p0 xa:111111111111111f 1111111111111111 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:111111109876544c 1111111111111111(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:222222223456789c 2222222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:222222222222222c 2252222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:222222223456789c 2222222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:222222222222222c 2252222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p0 xa:222222222222222f 2222222222222222 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:222222220987655c 2222222222222222(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:333333334567900c 3333333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:333333333333333c 3363333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:333333334567900c 3333333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:333333333333333c 3363333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:333333333333333f 3333333333333333 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:333333332098766c 3333333333333333(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:444444445679011c 4444444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:444444444444444c 4474444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:444444445679011c 4444444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:444444444444444c 4474444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:444444444444444f 4444444444444444 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:444444443209877c 4444444444444444(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:555555556790122c 5555555555555555(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:555555555555555c 5585555555555555(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:555555556790122c 5555555555555555(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:555555555555555c 5585555555555555(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:555555555555555f 5555555555555555 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:555555554320988c 5555555555555555(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:666666667901233c 6666666666666666(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:666666666666666c 6696666666666666(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:666666667901233c 6666666666666666(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:666666666666666c 6696666666666666(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:666666666666666f 6666666666666666 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:666666665432099c 6666666666666666(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:777777779012344c 7777777777777777(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:777777777777777c 7807777777777777(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:777777779012344c 7777777777777777(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:777777777777777c 7807777777777777(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:777777777777777f 7777777777777777 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:777777776543210c 7777777777777777(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:888888890123455c 8888888888888888(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:888888888888888c 8918888888888888(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:888888890123455c 8888888888888888(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:888888888888888c 8918888888888888(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:888888888888888f 8888888888888888 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:888888887654321c 8888888888888888(+|0)
+
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:999999999999999f 9999999999999999 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:999999998765432c 9999999999999999(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111112345678c 1111111111111111(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222223456789c 2222222222222222(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333334567900c 3333333333333333(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444445679011c 4444444444444444(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555556790122c 5555555555555555(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666667901233c 6666666666666666(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777779012344c 7777777777777777(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888890123455c 8888888888888888(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000002469134c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000001234567c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111112345678c 1111111111111111(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222223456789c 2222222222222222(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333334567900c 3333333333333333(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444445679011c 4444444444444444(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555556790122c 5555555555555555(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666667901233c 6666666666666666(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777779012344c 7777777777777777(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888890123455c 8888888888888888(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000002469134c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000001234567c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111109876544d 1111111111111111( - )
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222220987655d 2222222222222222( - )
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333332098766d 3333333333333333( - )
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444443209877d 4444444444444444( - )
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555554320988d 5555555555555555( - )
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666665432099d 6666666666666666( - )
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777776543210d 7777777777777777( - )
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888887654321d 8888888888888888( - )
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999998765432d 9999999999999999( - )
+
+bcdadd. p0 xa:000000001234567f 0000000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111111111111c 1141111111111111(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222222222222c 2252222222222222(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333333333333c 3363333333333333(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444444444444c 4474444444444444(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555555555555c 5585555555555555(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666666666666c 6696666666666666(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777777777777c 7807777777777777(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888888888888c 8918888888888888(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000000000000c 0060000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111111111111c 1141111111111111(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222222222222c 2252222222222222(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333333333333c 3363333333333333(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444444444444c 4474444444444444(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555555555555c 5585555555555555(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666666666666c 6696666666666666(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777777777777c 7807777777777777(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888888888888c 8918888888888888(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000000000000c 0060000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111111111111d 1081111111111111( - )
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222222222222d 2192222222222222( - )
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333333333333d 3303333333333333( - )
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444444444444d 4414444444444444( - )
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555555555555d 5525555555555555( - )
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666666666666d 6636666666666666( - )
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777777777777d 7747777777777777( - )
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888888888888d 8858888888888888( - )
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999999999999d 9969999999999999( - )
+
+bcdadd. p0 xa:000000000000000f 0030000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:999999998765433c 0029999999999999(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p0 xa:000000000000000d 0000000000000000 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (LT) (8) xt:111111109876544d 1111111111111111( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (LT) (8) xt:111111111111111d 1081111111111111( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (LT) (8) xt:111111109876544d 1111111111111111( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (LT) (8) xt:111111111111111d 1081111111111111( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:111111111111111d 1111111111111111 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:111111112345678d 1111111111111111( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (LT) (8) xt:222222220987655d 2222222222222222( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (LT) (8) xt:222222222222222d 2192222222222222( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (LT) (8) xt:222222220987655d 2222222222222222( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (LT) (8) xt:222222222222222d 2192222222222222( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:222222222222222d 2222222222222222 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:222222223456789d 2222222222222222( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (LT) (8) xt:333333332098766d 3333333333333333( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (LT) (8) xt:333333333333333d 3303333333333333( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (LT) (8) xt:333333332098766d 3333333333333333( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (LT) (8) xt:333333333333333d 3303333333333333( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:333333333333333d 3333333333333333 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:333333334567900d 3333333333333333( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (LT) (8) xt:444444443209877d 4444444444444444( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (LT) (8) xt:444444444444444d 4414444444444444( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (LT) (8) xt:444444443209877d 4444444444444444( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (LT) (8) xt:444444444444444d 4414444444444444( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:444444444444444d 4444444444444444 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:444444445679011d 4444444444444444( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (LT) (8) xt:555555554320988d 5555555555555555( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (LT) (8) xt:555555555555555d 5525555555555555( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (LT) (8) xt:555555554320988d 5555555555555555( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (LT) (8) xt:555555555555555d 5525555555555555( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:555555555555555d 5555555555555555 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:555555556790122d 5555555555555555( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (LT) (8) xt:666666665432099d 6666666666666666( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (LT) (8) xt:666666666666666d 6636666666666666( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (LT) (8) xt:666666665432099d 6666666666666666( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (LT) (8) xt:666666666666666d 6636666666666666( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p0 xa:666666666666666d 6666666666666666 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:666666667901233d 6666666666666666( - )
+
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p1 xa:000000000000000c 0000000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:111111112345678f 1111111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:111111111111111f 1141111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:111111112345678f 1111111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:111111111111111f 1141111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p1 xa:111111111111111c 1111111111111111 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:111111109876544f 1111111111111111(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:222222223456789f 2222222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:222222222222222f 2252222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:222222223456789f 2222222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:222222222222222f 2252222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p1 xa:222222222222222c 2222222222222222 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:222222220987655f 2222222222222222(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:333333334567900f 3333333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:333333333333333f 3363333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:333333334567900f 3333333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:333333333333333f 3363333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:333333333333333c 3333333333333333 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:333333332098766f 3333333333333333(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:444444445679011f 4444444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:444444444444444f 4474444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:444444445679011f 4444444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:444444444444444f 4474444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:444444444444444c 4444444444444444 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:444444443209877f 4444444444444444(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:555555556790122f 5555555555555555(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:555555555555555f 5585555555555555(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:555555556790122f 5555555555555555(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:555555555555555f 5585555555555555(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:555555555555555c 5555555555555555 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:555555554320988f 5555555555555555(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:666666667901233f 6666666666666666(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:666666666666666f 6696666666666666(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:666666667901233f 6666666666666666(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:666666666666666f 6696666666666666(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:666666666666666c 6666666666666666 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:666666665432099f 6666666666666666(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:777777779012344f 7777777777777777(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:777777777777777f 7807777777777777(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:777777779012344f 7777777777777777(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:777777777777777f 7807777777777777(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:777777777777777c 7777777777777777 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:777777776543210f 7777777777777777(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:888888890123455f 8888888888888888(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:888888888888888f 8918888888888888(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:888888890123455f 8888888888888888(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:888888888888888f 8918888888888888(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:888888888888888c 8888888888888888 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:888888887654321f 8888888888888888(+|0)
+
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:999999999999999c 9999999999999999 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:999999998765432f 9999999999999999(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111112345678f 1111111111111111(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222223456789f 2222222222222222(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333334567900f 3333333333333333(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444445679011f 4444444444444444(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555556790122f 5555555555555555(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666667901233f 6666666666666666(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777779012344f 7777777777777777(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888890123455f 8888888888888888(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000002469134f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000001234567f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111112345678f 1111111111111111(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222223456789f 2222222222222222(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333334567900f 3333333333333333(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444445679011f 4444444444444444(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555556790122f 5555555555555555(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666667901233f 6666666666666666(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777779012344f 7777777777777777(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888890123455f 8888888888888888(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000002469134f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000001234567f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111109876544d 1111111111111111( - )
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222220987655d 2222222222222222( - )
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333332098766d 3333333333333333( - )
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444443209877d 4444444444444444( - )
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555554320988d 5555555555555555( - )
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666665432099d 6666666666666666( - )
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777776543210d 7777777777777777( - )
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888887654321d 8888888888888888( - )
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999998765432d 9999999999999999( - )
+
+bcdadd. p1 xa:000000001234567c 0000000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111111111111f 1141111111111111(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222222222222f 2252222222222222(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333333333333f 3363333333333333(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444444444444f 4474444444444444(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555555555555f 5585555555555555(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666666666666f 6696666666666666(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777777777777f 7807777777777777(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888888888888f 8918888888888888(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000000000000f 0060000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111111111111f 1141111111111111(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222222222222f 2252222222222222(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333333333333f 3363333333333333(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444444444444f 4474444444444444(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555555555555f 5585555555555555(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666666666666f 6696666666666666(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777777777777f 7807777777777777(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888888888888f 8918888888888888(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000000000000f 0060000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111111111111d 1081111111111111( - )
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222222222222d 2192222222222222( - )
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333333333333d 3303333333333333( - )
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444444444444d 4414444444444444( - )
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555555555555d 5525555555555555( - )
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666666666666d 6636666666666666( - )
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777777777777d 7747777777777777( - )
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888888888888d 8858888888888888( - )
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999999999999d 9969999999999999( - )
+
+bcdadd. p1 xa:000000000000000c 0030000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:999999998765433f 0029999999999999(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p1 xa:000000000000000f 0000000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:111111112345678f 1111111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:111111111111111f 1141111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:111111112345678f 1111111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:111111111111111f 1141111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p1 xa:111111111111111f 1111111111111111 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:111111109876544f 1111111111111111(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:222222223456789f 2222222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:222222222222222f 2252222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:222222223456789f 2222222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:222222222222222f 2252222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p1 xa:222222222222222f 2222222222222222 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:222222220987655f 2222222222222222(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:333333334567900f 3333333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:333333333333333f 3363333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:333333334567900f 3333333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:333333333333333f 3363333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:333333333333333f 3333333333333333 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:333333332098766f 3333333333333333(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:444444445679011f 4444444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:444444444444444f 4474444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:444444445679011f 4444444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:444444444444444f 4474444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:444444444444444f 4444444444444444 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:444444443209877f 4444444444444444(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:555555556790122f 5555555555555555(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:555555555555555f 5585555555555555(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:555555556790122f 5555555555555555(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:555555555555555f 5585555555555555(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:555555555555555f 5555555555555555 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:555555554320988f 5555555555555555(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:666666667901233f 6666666666666666(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:666666666666666f 6696666666666666(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:666666667901233f 6666666666666666(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:666666666666666f 6696666666666666(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:666666666666666f 6666666666666666 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:666666665432099f 6666666666666666(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:777777779012344f 7777777777777777(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:777777777777777f 7807777777777777(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:777777779012344f 7777777777777777(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:777777777777777f 7807777777777777(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:777777777777777f 7777777777777777 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:777777776543210f 7777777777777777(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:888888890123455f 8888888888888888(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:888888888888888f 8918888888888888(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:888888890123455f 8888888888888888(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:888888888888888f 8918888888888888(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:888888888888888f 8888888888888888 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:888888887654321f 8888888888888888(+|0)
+
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:999999999999999f 9999999999999999 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:999999998765432f 9999999999999999(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111112345678f 1111111111111111(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222223456789f 2222222222222222(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333334567900f 3333333333333333(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444445679011f 4444444444444444(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555556790122f 5555555555555555(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666667901233f 6666666666666666(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777779012344f 7777777777777777(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888890123455f 8888888888888888(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000002469134f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000001234567f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111112345678f 1111111111111111(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222223456789f 2222222222222222(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333334567900f 3333333333333333(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444445679011f 4444444444444444(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555556790122f 5555555555555555(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666667901233f 6666666666666666(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777779012344f 7777777777777777(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888890123455f 8888888888888888(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000002469134f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000001234567f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111109876544d 1111111111111111( - )
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222220987655d 2222222222222222( - )
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333332098766d 3333333333333333( - )
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444443209877d 4444444444444444( - )
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555554320988d 5555555555555555( - )
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666665432099d 6666666666666666( - )
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777776543210d 7777777777777777( - )
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888887654321d 8888888888888888( - )
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999998765432d 9999999999999999( - )
+
+bcdadd. p1 xa:000000001234567f 0000000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111111111111f 1141111111111111(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222222222222f 2252222222222222(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333333333333f 3363333333333333(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444444444444f 4474444444444444(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555555555555f 5585555555555555(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666666666666f 6696666666666666(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777777777777f 7807777777777777(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888888888888f 8918888888888888(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000000000000f 0060000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111111111111f 1141111111111111(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222222222222f 2252222222222222(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333333333333f 3363333333333333(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444444444444f 4474444444444444(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555555555555f 5585555555555555(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666666666666f 6696666666666666(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777777777777f 7807777777777777(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888888888888f 8918888888888888(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000000000000f 0060000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111111111111d 1081111111111111( - )
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222222222222d 2192222222222222( - )
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333333333333d 3303333333333333( - )
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444444444444d 4414444444444444( - )
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555555555555d 5525555555555555( - )
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666666666666d 6636666666666666( - )
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777777777777d 7747777777777777( - )
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888888888888d 8858888888888888( - )
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999999999999d 9969999999999999( - )
+
+bcdadd. p1 xa:000000000000000f 0030000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:999999998765433f 0029999999999999(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p1 xa:000000000000000d 0000000000000000 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (LT) (8) xt:111111109876544d 1111111111111111( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (LT) (8) xt:111111111111111d 1081111111111111( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (LT) (8) xt:111111109876544d 1111111111111111( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (LT) (8) xt:111111111111111d 1081111111111111( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:111111111111111d 1111111111111111 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:111111112345678d 1111111111111111( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (LT) (8) xt:222222220987655d 2222222222222222( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (LT) (8) xt:222222222222222d 2192222222222222( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (LT) (8) xt:222222220987655d 2222222222222222( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (LT) (8) xt:222222222222222d 2192222222222222( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:222222222222222d 2222222222222222 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:222222223456789d 2222222222222222( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (LT) (8) xt:333333332098766d 3333333333333333( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (LT) (8) xt:333333333333333d 3303333333333333( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (LT) (8) xt:333333332098766d 3333333333333333( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (LT) (8) xt:333333333333333d 3303333333333333( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:333333333333333d 3333333333333333 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:333333334567900d 3333333333333333( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (LT) (8) xt:444444443209877d 4444444444444444( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (LT) (8) xt:444444444444444d 4414444444444444( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (LT) (8) xt:444444443209877d 4444444444444444( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (LT) (8) xt:444444444444444d 4414444444444444( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:444444444444444d 4444444444444444 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:444444445679011d 4444444444444444( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (LT) (8) xt:555555554320988d 5555555555555555( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (LT) (8) xt:555555555555555d 5525555555555555( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (LT) (8) xt:555555554320988d 5555555555555555( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (LT) (8) xt:555555555555555d 5525555555555555( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:555555555555555d 5555555555555555 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:555555556790122d 5555555555555555( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (LT) (8) xt:666666665432099d 6666666666666666( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (LT) (8) xt:666666666666666d 6636666666666666( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (LT) (8) xt:666666665432099d 6666666666666666( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (LT) (8) xt:666666666666666d 6636666666666666( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdadd. p1 xa:666666666666666d 6666666666666666 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:666666667901233d 6666666666666666( - )
+
+
+bcdsub. p0 xa:0000000000000000 0000000000000000 xb:000000000000000c 0000000000000000 => (SO) (1) xt:0000000000000000 0000000000000000
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+bcdcpsgn. xa:111111111111111c 1111111111111111 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111c 1111111111111111 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111c 1111111111111111 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222c 2222222222222222 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333c 3333333333333333 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444c 4444444444444444 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555c 5555555555555555 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666c 6666666666666666 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777c 7777777777777777 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888c 8888888888888888 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999c 9999999999999999 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567c 0000000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000c 0030000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0000000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111f 1111111111111111 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222f 2222222222222222 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333f 3333333333333333 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444f 4444444444444444 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555f 5555555555555555 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666f 6666666666666666 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:777777777777777c 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:777777777777777f 7777777777777777(+|0)
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:777777777777777f 7777777777777777 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:777777777777777d 7777777777777777( - )
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:888888888888888c 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:888888888888888f 8888888888888888(+|0)
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:888888888888888f 8888888888888888 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:888888888888888d 8888888888888888( - )
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:999999999999999c 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:999999999999999f 9999999999999999(+|0)
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:999999999999999f 9999999999999999 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:999999999999999d 9999999999999999( - )
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000001234567c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000001234567f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000001234567f 0000000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:000000001234567d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:000000000000000c 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:000000000000000f 0030000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000f 0030000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:000000000000000d 0030000000000000( - )
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (EQ) (2) xt:000000000000000c 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (EQ) (2) xt:000000000000000f 0000000000000000(+|0)
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:000000000000000d 0000000000000000 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (EQ) (2) xt:000000000000000d 0000000000000000( - )
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:111111111111111c 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:111111111111111f 1111111111111111(+|0)
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:111111111111111d 1111111111111111 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:111111111111111d 1111111111111111( - )
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:222222222222222c 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:222222222222222f 2222222222222222(+|0)
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:222222222222222d 2222222222222222 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:222222222222222d 2222222222222222( - )
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:333333333333333c 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:333333333333333f 3333333333333333(+|0)
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:333333333333333d 3333333333333333 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:333333333333333d 3333333333333333( - )
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:444444444444444c 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:444444444444444f 4444444444444444(+|0)
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:444444444444444d 4444444444444444 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:444444444444444d 4444444444444444( - )
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:555555555555555c 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:555555555555555f 5555555555555555(+|0)
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:555555555555555d 5555555555555555 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:555555555555555d 5555555555555555( - )
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000c 0000000000000000 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:111111111111111c 1111111111111111 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:222222222222222c 2222222222222222 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:333333333333333c 3333333333333333 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:444444444444444c 4444444444444444 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:555555555555555c 5555555555555555 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:666666666666666c 6666666666666666 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:777777777777777c 7777777777777777 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:888888888888888c 8888888888888888 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:999999999999999c 9999999999999999 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:000000001234567c 0000000000000000 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000c 0030000000000000 (+|0) => (GT) (4) xt:666666666666666c 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000f 0000000000000000 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:111111111111111f 1111111111111111 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:222222222222222f 2222222222222222 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:333333333333333f 3333333333333333 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:444444444444444f 4444444444444444 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:555555555555555f 5555555555555555 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:666666666666666f 6666666666666666 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:777777777777777f 7777777777777777 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:888888888888888f 8888888888888888 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:999999999999999f 9999999999999999 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:000000001234567f 0000000000000000 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000f 0030000000000000 (+|0) => (GT) (4) xt:666666666666666f 6666666666666666(+|0)
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:000000000000000d 0000000000000000 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:111111111111111d 1111111111111111 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:222222222222222d 2222222222222222 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:333333333333333d 3333333333333333 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:444444444444444d 4444444444444444 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:555555555555555d 5555555555555555 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:666666666666666d 6666666666666666 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:777777777777777d 7777777777777777 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:888888888888888d 8888888888888888 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:999999999999999d 9999999999999999 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+bcdcpsgn. xa:666666666666666d 6666666666666666 ( - ) xb:000000001234567d 0000000000000000 ( - ) => (LT) (8) xt:666666666666666d 6666666666666666( - )
+
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:000000000000000c 0000000000000000 => (EQ) (2) xt:000000000000000c 0000000000000000
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:111111111111111c 1111111111111111 => (GT) (4) xt:111111111111111c 1111111111111111
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:222222222222222c 2222222222222222 => (GT) (4) xt:222222222222222c 2222222222222222
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:333333333333333c 3333333333333333 => (GT) (4) xt:333333333333333c 3333333333333333
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:444444444444444c 4444444444444444 => (GT) (4) xt:444444444444444c 4444444444444444
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:555555555555555c 5555555555555555 => (GT) (4) xt:555555555555555c 5555555555555555
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:666666666666666c 6666666666666666 => (GT) (4) xt:666666666666666c 6666666666666666
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:777777777777777c 7777777777777777 => (GT) (4) xt:777777777777777c 7777777777777777
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:888888888888888c 8888888888888888 => (GT) (4) xt:888888888888888c 8888888888888888
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:999999999999999c 9999999999999999 => (GT) (4) xt:999999999999999c 9999999999999999
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:000000001234567c 0000000000000000 => (GT) (4) xt:000000001234567c 0000000000000000
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:000000000000000c 0030000000000000 => (GT) (4) xt:000000000000000c 0030000000000000
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:000000000000000f 0000000000000000 => (EQ) (2) xt:000000000000000c 0000000000000000
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:111111111111111f 1111111111111111 => (GT) (4) xt:111111111111111c 1111111111111111
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:222222222222222f 2222222222222222 => (GT) (4) xt:222222222222222c 2222222222222222
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:333333333333333f 3333333333333333 => (GT) (4) xt:333333333333333c 3333333333333333
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:444444444444444f 4444444444444444 => (GT) (4) xt:444444444444444c 4444444444444444
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:555555555555555f 5555555555555555 => (GT) (4) xt:555555555555555c 5555555555555555
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:666666666666666f 6666666666666666 => (GT) (4) xt:666666666666666c 6666666666666666
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:777777777777777f 7777777777777777 => (GT) (4) xt:777777777777777c 7777777777777777
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:888888888888888f 8888888888888888 => (GT) (4) xt:888888888888888c 8888888888888888
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:999999999999999f 9999999999999999 => (GT) (4) xt:999999999999999c 9999999999999999
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:000000001234567f 0000000000000000 => (GT) (4) xt:000000001234567c 0000000000000000
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:000000000000000f 0030000000000000 => (GT) (4) xt:000000000000000c 0030000000000000
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:000000000000000d 0000000000000000 => (EQ) (2) xt:000000000000000d 0000000000000000
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:111111111111111d 1111111111111111 => (LT) (8) xt:111111111111111d 1111111111111111
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:222222222222222d 2222222222222222 => (LT) (8) xt:222222222222222d 2222222222222222
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:333333333333333d 3333333333333333 => (LT) (8) xt:333333333333333d 3333333333333333
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:444444444444444d 4444444444444444 => (LT) (8) xt:444444444444444d 4444444444444444
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:555555555555555d 5555555555555555 => (LT) (8) xt:555555555555555d 5555555555555555
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:666666666666666d 6666666666666666 => (LT) (8) xt:666666666666666d 6666666666666666
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:777777777777777d 7777777777777777 => (LT) (8) xt:777777777777777d 7777777777777777
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:888888888888888d 8888888888888888 => (LT) (8) xt:888888888888888d 8888888888888888
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:999999999999999d 9999999999999999 => (LT) (8) xt:999999999999999d 9999999999999999
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000000 xb:000000001234567d 0000000000000000 => (LT) (8) xt:000000001234567d 0000000000000000
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000001 xb:000000000000000c 0000000000000000 => (EQ) (2) xt:000000000000000c 0000000000000000
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000001 xb:111111111111111c 1111111111111111 => (GT) (4) xt:111111111111111c 1111111111111111
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000001 xb:222222222222222c 2222222222222222 => (GT) (4) xt:222222222222222c 2222222222222222
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000001 xb:333333333333333c 3333333333333333 => (GT) (4) xt:333333333333333c 3333333333333333
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000001 xb:444444444444444c 4444444444444444 => (GT) (4) xt:444444444444444c 4444444444444444
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000001 xb:555555555555555c 5555555555555555 => (GT) (4) xt:555555555555555c 5555555555555555
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000001 xb:666666666666666c 6666666666666666 => (GT) (4) xt:666666666666666c 6666666666666666
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000001 xb:777777777777777c 7777777777777777 => (GT) (4) xt:777777777777777c 7777777777777777
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000001 xb:888888888888888c 8888888888888888 => (GT) (4) xt:888888888888888c 8888888888888888
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000001 xb:999999999999999c 9999999999999999 => (GT) (4) xt:999999999999999c 9999999999999999
+
+bcdsetsgn. p0 xa:0000000000000000 0000000000000001 xb:000000001234567c 0000000000000000 => (GT) (4) xt:000000001234567c 0000000000000000
+
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+
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+bcdcfsq. p1 xa:000000000000000c 0000000000000000 (+|0) xb:000000000000000d 0000000000000000 ( - ) => (GT) (4) xt:000000000000013f 0000000000000000(+|0)
+
+bcdcfsq. p1 xa:000000000000000c 0000000000000000 (+|0) xb:111111111111111d 1111111111111111 ( - ) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdcfsq. p1 xa:000000000000000c 0000000000000000 (+|0) xb:222222222222222d 2222222222222222 ( - ) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdcfsq. p1 xa:000000000000000c 0000000000000000 (+|0) xb:333333333333333d 3333333333333333 ( - ) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdcfsq. p1 xa:000000000000000c 0000000000000000 (+|0) xb:444444444444444d 4444444444444444 ( - ) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdcfsq. p1 xa:000000000000000c 0000000000000000 (+|0) xb:555555555555555d 5555555555555555 ( - ) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdcfsq. p1 xa:000000000000000c 0000000000000000 (+|0) xb:666666666666666d 6666666666666666 ( - ) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdcfsq. p1 xa:000000000000000c 0000000000000000 (+|0) xb:777777777777777d 7777777777777777 ( - ) => (GT)(SO) (5) xt:0000000000000000 0000000000000000
+bcdcfsq. p1 xa:000000000000000c 0000000000000000 (+|0) xb:888888888888888d 8888888888888888 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdcfsq. p1 xa:000000000000000c 0000000000000000 (+|0) xb:999999999999999d 9999999999999999 ( - ) => (LT)(SO) (9) xt:0000000000000000 0000000000000000
+bcdcfsq. p1 xa:000000000000000c 0000000000000000 (+|0) xb:000000001234567d 0000000000000000 ( - ) => (GT) (4) xt:000000305419901f 0000000000000000(+|0)
+
+
+All done. Tested 51 different instructions
+ppc noop misc:
+Test instruction group [ppc noop misc]
+wait =>
+
+All done. Tested 52 different instructions
+ppc addpc_misc:
+Test instruction group [ppc addpc_misc]
+addpcis 0000000000000000 => 0000000010003de4
+addpcis 0000000000000001 => 0000000010013dec
+addpcis 0000000000000002 => 0000000010023df4
+addpcis 0000000000000003 => 0000000010403dfc
+addpcis 0000000000000004 => 0000000018003e04
+addpcis 0000000000000005 => 0000000030003e0c
+addpcis 0000000000000006 => 000000008fff3e14
+addpcis 0000000000000007 => ffffffff90003e1c
+addpcis 0000000000000008 => 0000000010003e24
+addpcis 0000000000000009 => 000000000fff3e2c
+addpcis 000000000000000a => 000000000ffe3e34
+addpcis 000000000000000b => 000000000fc03e3c
+addpcis 000000000000000c => 0000000008003e44
+addpcis 000000000000000d => fffffffff0003e4c
+addpcis 000000000000000e => ffffffff90013e54
+addpcis 000000000000000f => ffffffff90003e5c
+
+subpcis 0000000000000000 => 0000000010003ee8
+subpcis 0000000000000001 => 000000000fff3ef0
+subpcis 0000000000000002 => 000000000ffe3ef8
+subpcis 0000000000000003 => 000000000fc03f00
+subpcis 0000000000000004 => 0000000008003f08
+subpcis 0000000000000005 => fffffffff0003f10
+subpcis 0000000000000006 => ffffffff90013f18
+subpcis 0000000000000007 => ffffffff90003f20
+subpcis 0000000000000008 => 0000000010003f28
+subpcis 0000000000000009 => 0000000010013f30
+subpcis 000000000000000a => 0000000010023f38
+subpcis 000000000000000b => 0000000010403f40
+subpcis 000000000000000c => 0000000010803f48
+subpcis 000000000000000d => 0000000012003f50
+subpcis 000000000000000e => 000000008fff3f58
+subpcis 000000000000000f => ffffffff90003f60
+
+All done. Tested 54 different instructions
diff --git a/none/tests/ppc64/test_isa_3_0_other.vgtest b/none/tests/ppc64/test_isa_3_0_other.vgtest
new file mode 100644
index 0000000..817f7ef
--- /dev/null
+++ b/none/tests/ppc64/test_isa_3_0_other.vgtest
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_ppc64_auxv_cap arch_3_00
+prog: test_isa_3_0 -i -m -D -B -N -P
diff --git a/none/tests/ppoll_alarm.c b/none/tests/ppoll_alarm.c
new file mode 100644
index 0000000..1b1794b
--- /dev/null
+++ b/none/tests/ppoll_alarm.c
@@ -0,0 +1,55 @@
+/* Tries to exploit bug in ppoll mask handling:
+ https://bugs.kde.org/show_bug.cgi?id=359871
+ where client program was able to successfully block VG_SIGVGKILL. */
+
+#define _GNU_SOURCE /* for ppoll */
+#include <poll.h>
+#include <pthread.h>
+#include <signal.h>
+#include <stdio.h>
+#include <unistd.h>
+
+static int ready = 0;
+static pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
+static pthread_cond_t cond = PTHREAD_COND_INITIALIZER;
+
+static void *
+mythr(void *ignore)
+{
+ pthread_mutex_lock(&mutex);
+ ready = 1;
+ pthread_cond_signal(&cond);
+ pthread_mutex_unlock(&mutex);
+
+ sigset_t ss;
+ sigfillset(&ss);
+ while (1) {
+ struct timespec ts = {10000, 0};
+ ppoll(NULL, 0, &ts, &ss);
+ }
+
+ return NULL;
+}
+
+int
+main()
+{
+ pthread_t thr;
+ int ret = pthread_create(&thr, NULL, mythr, NULL);
+ if (ret != 0) {
+ fprintf(stderr, "pthread_create failed\n");
+ return 1;
+ }
+
+ pthread_mutex_lock(&mutex);
+ while (ready == 0) {
+ pthread_cond_wait(&cond, &mutex);
+ }
+ pthread_mutex_unlock(&mutex);
+
+ alarm(1); /* Unhandled SIGALRM should cause exit. */
+ while (1)
+ sleep(1);
+
+ return 0;
+}
diff --git a/none/tests/ppoll_alarm.stderr.exp b/none/tests/ppoll_alarm.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/ppoll_alarm.stderr.exp
diff --git a/none/tests/ppoll_alarm.stdout.exp b/none/tests/ppoll_alarm.stdout.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/ppoll_alarm.stdout.exp
diff --git a/none/tests/ppoll_alarm.vgtest b/none/tests/ppoll_alarm.vgtest
new file mode 100644
index 0000000..c08d37a
--- /dev/null
+++ b/none/tests/ppoll_alarm.vgtest
@@ -0,0 +1,4 @@
+prereq: ../../tests/os_test linux || ../../tests/os_test solaris
+prog: ppoll_alarm
+vgopts: -q
+stderr_filter: filter_stderr
diff --git a/none/tests/pselect_alarm.c b/none/tests/pselect_alarm.c
new file mode 100644
index 0000000..7a68ec0
--- /dev/null
+++ b/none/tests/pselect_alarm.c
@@ -0,0 +1,61 @@
+/* Tries to exploit bug in pselect mask handling:
+ https://bugs.kde.org/show_bug.cgi?id=359871
+ where client program was able to successfully block VG_SIGVGKILL. */
+
+#include <sys/select.h>
+#include <assert.h>
+#include <errno.h>
+#include <pthread.h>
+#include <signal.h>
+#include <stdio.h>
+#include <unistd.h>
+
+static int ready = 0;
+static pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
+static pthread_cond_t cond = PTHREAD_COND_INITIALIZER;
+
+static void *
+mythr(void *ignore)
+{
+ pthread_mutex_lock(&mutex);
+ ready = 1;
+ pthread_cond_signal(&cond);
+ pthread_mutex_unlock(&mutex);
+
+ sigset_t ss;
+ sigfillset(&ss);
+ while (1) {
+ struct timespec ts = {10000, 0};
+ pselect(0, NULL, NULL, NULL, &ts, &ss);
+ }
+
+ return NULL;
+}
+
+int
+main()
+{
+ pthread_t thr;
+ int ret = pthread_create(&thr, NULL, mythr, NULL);
+ if (ret != 0) {
+ fprintf(stderr, "pthread_create failed\n");
+ return 1;
+ }
+
+ pthread_mutex_lock(&mutex);
+ while (ready == 0) {
+ pthread_cond_wait(&cond, &mutex);
+ }
+ pthread_mutex_unlock(&mutex);
+
+#if defined(VGO_linux)
+ assert(pselect(0, NULL, NULL, NULL, NULL, (sigset_t *)12) == -1);
+ assert(errno == EFAULT);
+#endif
+
+ alarm(1); /* Unhandled SIGALRM should cause exit. */
+ while (1)
+ sleep(1);
+
+ return 0;
+}
diff --git a/none/tests/pselect_alarm.stderr.exp b/none/tests/pselect_alarm.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/pselect_alarm.stderr.exp
diff --git a/none/tests/pselect_alarm.stdout.exp b/none/tests/pselect_alarm.stdout.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/pselect_alarm.stdout.exp
diff --git a/none/tests/pselect_alarm.vgtest b/none/tests/pselect_alarm.vgtest
new file mode 100644
index 0000000..84cc674
--- /dev/null
+++ b/none/tests/pselect_alarm.vgtest
@@ -0,0 +1,3 @@
+prog: pselect_alarm
+vgopts: -q
+stderr_filter: filter_stderr
diff --git a/none/tests/pselect_sigmask_null.c b/none/tests/pselect_sigmask_null.c
new file mode 100644
index 0000000..c4a0b55
--- /dev/null
+++ b/none/tests/pselect_sigmask_null.c
@@ -0,0 +1,26 @@
+/* Make sure handling of NULL sigmask is correct.
+ https://bugs.kde.org/show_bug.cgi?id=364413
+ We might try to make a copy and adjust the mask.
+ Testcase provided by Paul Eggert <eggert@cs.ucla.edu> */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/select.h>
+
+int
+main (void)
+{
+ struct timespec timeout;
+ timeout.tv_sec = 1;
+ timeout.tv_nsec = 0;
+ switch (pselect (0, 0, 0, 0, &timeout, 0))
+ {
+ default:
+ abort ();
+ case -1:
+ perror ("pselect");
+ return 1;
+ case 0:
+ return 0;
+ }
+}
diff --git a/none/tests/pselect_sigmask_null.stderr.exp b/none/tests/pselect_sigmask_null.stderr.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/pselect_sigmask_null.stderr.exp
diff --git a/none/tests/pselect_sigmask_null.stdout.exp b/none/tests/pselect_sigmask_null.stdout.exp
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/none/tests/pselect_sigmask_null.stdout.exp
diff --git a/none/tests/pselect_sigmask_null.vgtest b/none/tests/pselect_sigmask_null.vgtest
new file mode 100644
index 0000000..e59688c
--- /dev/null
+++ b/none/tests/pselect_sigmask_null.vgtest
@@ -0,0 +1,2 @@
+prog: pselect_sigmask_null
+vgopts: -q
diff --git a/none/tests/pth_term_signal.c b/none/tests/pth_term_signal.c
new file mode 100644
index 0000000..9d8f05c
--- /dev/null
+++ b/none/tests/pth_term_signal.c
@@ -0,0 +1,91 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <signal.h>
+#include <pthread.h>
+#include <assert.h>
+
+#include <sys/wait.h>
+
+void *
+slavethread(void *arg)
+{
+ sigset_t sigmask;
+
+ if (sigfillset(&sigmask))
+ {
+ fprintf(stderr, "Error line %u\n", __LINE__);
+ _exit(255);
+ }
+
+ if (pthread_sigmask(SIG_UNBLOCK, &sigmask, 0))
+ {
+ fprintf(stderr, "Error line %u\n", __LINE__);
+ _exit(255);
+ }
+
+ while (1)
+ sleep(1);
+}
+
+void
+childprocess()
+{
+ pthread_t slave;
+
+ if (pthread_create(&slave, 0, &slavethread, 0))
+ {
+ fprintf(stderr, "Error line %u\n", __LINE__);
+ _exit(255);
+ }
+
+ while (1)
+ sleep(1);
+}
+
+int main(int argc, char **argv)
+{
+ sigset_t sigmask;
+
+ if (sigfillset(&sigmask))
+ {
+ fprintf(stderr, "Error line %u\n", __LINE__);
+ return 255;
+ }
+
+ if (pthread_sigmask(SIG_BLOCK, &sigmask, 0))
+ {
+ fprintf(stderr, "Error line %u\n", __LINE__);
+ return 255;
+ }
+
+ int childpid = fork();
+
+ if (-1 == childpid)
+ {
+ fprintf(stderr, "Error line %u\n", __LINE__);
+ return 255;
+ }
+
+ if ( ! childpid)
+ childprocess();
+
+ if (kill(childpid, SIGTERM))
+ {
+ fprintf(stderr, "Error line %u\n", __LINE__);
+ return 255;
+ }
+
+ int status;
+ if (childpid != waitpid(childpid, &status, 0))
+ {
+ fprintf(stderr, "Error line %u\n", __LINE__);
+ return 255;
+ }
+
+ assert(WIFSIGNALED(status));
+
+ fprintf(stderr, "Signal %d\n", WTERMSIG(status));
+ assert(WTERMSIG(status) == SIGTERM);
+
+ return 0;
+}
diff --git a/none/tests/pth_term_signal.stderr.exp b/none/tests/pth_term_signal.stderr.exp
new file mode 100644
index 0000000..272cf31
--- /dev/null
+++ b/none/tests/pth_term_signal.stderr.exp
@@ -0,0 +1 @@
+Signal 15
diff --git a/none/tests/pth_term_signal.vgtest b/none/tests/pth_term_signal.vgtest
new file mode 100644
index 0000000..9591605
--- /dev/null
+++ b/none/tests/pth_term_signal.vgtest
@@ -0,0 +1,2 @@
+prog: pth_term_signal
+vgopts: -q
diff --git a/none/tests/res_search.vgtest b/none/tests/res_search.vgtest
index 24a35fc..2a32cf3 100644
--- a/none/tests/res_search.vgtest
+++ b/none/tests/res_search.vgtest
@@ -1,4 +1,4 @@
-prereq: which host >/dev/null 2>/dev/null && host www.yahoo.com > /dev/null && ! ../../tests/os_test darwin
+prereq: test $(command -v host) && host www.yahoo.com > /dev/null && ! ../../tests/os_test darwin
prog: res_search
args: www.yahoo.com
vgopts: -q
diff --git a/none/tests/s390x/Makefile.am b/none/tests/s390x/Makefile.am
index 6545117..ff10dc5 100644
--- a/none/tests/s390x/Makefile.am
+++ b/none/tests/s390x/Makefile.am
@@ -11,7 +11,8 @@
ex_sig ex_clone cu14 cu14_1 cu41 fpconv ecag fpext_warn \
rounding-1 rounding-2 rounding-3 rounding-4 rounding-5 bfp-1 \
bfp-2 bfp-3 bfp-4 srnm srnmb comp-1 comp-2 exrl tmll tm stmg \
- ex clst mvc test_fork test_sig rounding-6 rxsbg\
+ ex clst mvc test_fork test_sig rounding-6 rxsbg popcnt \
+ high-word \
spechelper-alr spechelper-algr \
spechelper-slr spechelper-slgr \
spechelper-cr spechelper-clr \
@@ -63,4 +64,4 @@
cu24_1_CFLAGS = $(AM_CFLAGS) -DM3=1
fixbr_CFLAGS = $(AM_CFLAGS) @FLAG_MLONG_DOUBLE_128@
fpext_CFLAGS = $(AM_CFLAGS) @FLAG_MLONG_DOUBLE_128@
-ex_clone_LDFLAGS = -lpthread
+ex_clone_LDADD = -lpthread
diff --git a/none/tests/s390x/Makefile.in b/none/tests/s390x/Makefile.in
new file mode 100644
index 0000000..ee07464
--- /dev/null
+++ b/none/tests/s390x/Makefile.in
@@ -0,0 +1,2162 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+am__is_gnu_make = { \
+ if test -z '$(MAKELEVEL)'; then \
+ false; \
+ elif test -n '$(MAKE_HOST)'; then \
+ true; \
+ elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
+ true; \
+ else \
+ false; \
+ fi; \
+}
+am__make_running_with_option = \
+ case $${target_option-} in \
+ ?) ;; \
+ *) echo "am__make_running_with_option: internal error: invalid" \
+ "target option '$${target_option-}' specified" >&2; \
+ exit 1;; \
+ esac; \
+ has_opt=no; \
+ sane_makeflags=$$MAKEFLAGS; \
+ if $(am__is_gnu_make); then \
+ sane_makeflags=$$MFLAGS; \
+ else \
+ case $$MAKEFLAGS in \
+ *\\[\ \ ]*) \
+ bs=\\; \
+ sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
+ | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \
+ esac; \
+ fi; \
+ skip_next=no; \
+ strip_trailopt () \
+ { \
+ flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
+ }; \
+ for flg in $$sane_makeflags; do \
+ test $$skip_next = yes && { skip_next=no; continue; }; \
+ case $$flg in \
+ *=*|--*) continue;; \
+ -*I) strip_trailopt 'I'; skip_next=yes;; \
+ -*I?*) strip_trailopt 'I';; \
+ -*O) strip_trailopt 'O'; skip_next=yes;; \
+ -*O?*) strip_trailopt 'O';; \
+ -*l) strip_trailopt 'l'; skip_next=yes;; \
+ -*l?*) strip_trailopt 'l';; \
+ -[dEDm]) skip_next=yes;; \
+ -[JT]) skip_next=yes;; \
+ esac; \
+ case $$flg in \
+ *$$target_option*) has_opt=yes; break;; \
+ esac; \
+ done; \
+ test $$has_opt = yes
+am__make_dryrun = (target_option=n; $(am__make_running_with_option))
+am__make_keepgoing = (target_option=k; $(am__make_running_with_option))
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+@COMPILER_IS_CLANG_TRUE@am__append_1 = -Wno-cast-align -Wno-self-assign \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-compare
+
+@SOLARIS_XPG_SYMBOLS_PRESENT_TRUE@am__append_2 = -Wl,-M,$(top_srcdir)/solaris/vgpreload-solaris.mapfile
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_3 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+
+# Make sure that all test programs have threaded errno.
+# Disable largefile support as there are test cases explictly enabling it.
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
+@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
+@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-constant-out-of-range-compare \
+@COMPILER_IS_CLANG_TRUE@ -Wno-self-assign -Wno-string-plus-int \
+@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
+@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
+@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
+@BUILD_DFP_TESTS_TRUE@am__append_8 = dfp-1 dfp-2 dfp-3 dfp-4 dfptest dfpext dfpconv srnmt pfpo
+@HAS_MLONG_DOUBLE_128_TRUE@am__append_9 = fpext fixbr
+check_PROGRAMS = $(am__EXEEXT_3) allexec$(EXEEXT) op00$(EXEEXT)
+subdir = none/tests/s390x
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.ac
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+DIST_COMMON = $(srcdir)/Makefile.am $(dist_noinst_SCRIPTS) \
+ $(am__DIST_COMMON)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+@BUILD_DFP_TESTS_TRUE@am__EXEEXT_1 = dfp-1$(EXEEXT) dfp-2$(EXEEXT) \
+@BUILD_DFP_TESTS_TRUE@ dfp-3$(EXEEXT) dfp-4$(EXEEXT) \
+@BUILD_DFP_TESTS_TRUE@ dfptest$(EXEEXT) dfpext$(EXEEXT) \
+@BUILD_DFP_TESTS_TRUE@ dfpconv$(EXEEXT) srnmt$(EXEEXT) \
+@BUILD_DFP_TESTS_TRUE@ pfpo$(EXEEXT)
+@HAS_MLONG_DOUBLE_128_TRUE@am__EXEEXT_2 = fpext$(EXEEXT) \
+@HAS_MLONG_DOUBLE_128_TRUE@ fixbr$(EXEEXT)
+am__EXEEXT_3 = clc$(EXEEXT) clcle$(EXEEXT) cvb$(EXEEXT) cvd$(EXEEXT) \
+ icm$(EXEEXT) lpr$(EXEEXT) tcxb$(EXEEXT) lam_stam$(EXEEXT) \
+ xc$(EXEEXT) mvst$(EXEEXT) add$(EXEEXT) sub$(EXEEXT) \
+ mul$(EXEEXT) and$(EXEEXT) or$(EXEEXT) xor$(EXEEXT) \
+ insert$(EXEEXT) div$(EXEEXT) srst$(EXEEXT) fold_And16$(EXEEXT) \
+ flogr$(EXEEXT) sub_EI$(EXEEXT) add_EI$(EXEEXT) and_EI$(EXEEXT) \
+ or_EI$(EXEEXT) xor_EI$(EXEEXT) insert_EI$(EXEEXT) \
+ mul_GE$(EXEEXT) add_GE$(EXEEXT) condloadstore$(EXEEXT) \
+ op_exception$(EXEEXT) fgx$(EXEEXT) stck$(EXEEXT) \
+ stckf$(EXEEXT) stcke$(EXEEXT) stfle$(EXEEXT) cksm$(EXEEXT) \
+ mvcl$(EXEEXT) clcl$(EXEEXT) troo$(EXEEXT) trto$(EXEEXT) \
+ trot$(EXEEXT) trtt$(EXEEXT) tr$(EXEEXT) tre$(EXEEXT) \
+ cij$(EXEEXT) cgij$(EXEEXT) clij$(EXEEXT) clgij$(EXEEXT) \
+ crj$(EXEEXT) cgrj$(EXEEXT) clrj$(EXEEXT) clgrj$(EXEEXT) \
+ cs$(EXEEXT) csg$(EXEEXT) cds$(EXEEXT) cdsg$(EXEEXT) \
+ cu21$(EXEEXT) cu21_1$(EXEEXT) cu24$(EXEEXT) cu24_1$(EXEEXT) \
+ cu42$(EXEEXT) cu12$(EXEEXT) cu12_1$(EXEEXT) ex_sig$(EXEEXT) \
+ ex_clone$(EXEEXT) cu14$(EXEEXT) cu14_1$(EXEEXT) cu41$(EXEEXT) \
+ fpconv$(EXEEXT) ecag$(EXEEXT) fpext_warn$(EXEEXT) \
+ rounding-1$(EXEEXT) rounding-2$(EXEEXT) rounding-3$(EXEEXT) \
+ rounding-4$(EXEEXT) rounding-5$(EXEEXT) bfp-1$(EXEEXT) \
+ bfp-2$(EXEEXT) bfp-3$(EXEEXT) bfp-4$(EXEEXT) srnm$(EXEEXT) \
+ srnmb$(EXEEXT) comp-1$(EXEEXT) comp-2$(EXEEXT) exrl$(EXEEXT) \
+ tmll$(EXEEXT) tm$(EXEEXT) stmg$(EXEEXT) ex$(EXEEXT) \
+ clst$(EXEEXT) mvc$(EXEEXT) test_fork$(EXEEXT) \
+ test_sig$(EXEEXT) rounding-6$(EXEEXT) rxsbg$(EXEEXT) \
+ popcnt$(EXEEXT) high-word$(EXEEXT) spechelper-alr$(EXEEXT) \
+ spechelper-algr$(EXEEXT) spechelper-slr$(EXEEXT) \
+ spechelper-slgr$(EXEEXT) spechelper-cr$(EXEEXT) \
+ spechelper-clr$(EXEEXT) spechelper-ltr$(EXEEXT) \
+ spechelper-or$(EXEEXT) spechelper-icm-1$(EXEEXT) \
+ spechelper-icm-2$(EXEEXT) spechelper-tmll$(EXEEXT) \
+ spechelper-tm$(EXEEXT) laa$(EXEEXT) $(am__EXEEXT_1) \
+ $(am__EXEEXT_2)
+add_SOURCES = add.c
+add_OBJECTS = add.$(OBJEXT)
+add_LDADD = $(LDADD)
+add_EI_SOURCES = add_EI.c
+add_EI_OBJECTS = add_EI.$(OBJEXT)
+add_EI_LDADD = $(LDADD)
+add_GE_SOURCES = add_GE.c
+add_GE_OBJECTS = add_GE.$(OBJEXT)
+add_GE_LDADD = $(LDADD)
+allexec_SOURCES = allexec.c
+allexec_OBJECTS = allexec-allexec.$(OBJEXT)
+allexec_LDADD = $(LDADD)
+allexec_LINK = $(CCLD) $(allexec_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+and_SOURCES = and.c
+and_OBJECTS = and.$(OBJEXT)
+and_LDADD = $(LDADD)
+and_EI_SOURCES = and_EI.c
+and_EI_OBJECTS = and_EI.$(OBJEXT)
+and_EI_LDADD = $(LDADD)
+bfp_1_SOURCES = bfp-1.c
+bfp_1_OBJECTS = bfp-1.$(OBJEXT)
+bfp_1_LDADD = $(LDADD)
+bfp_2_SOURCES = bfp-2.c
+bfp_2_OBJECTS = bfp-2.$(OBJEXT)
+bfp_2_LDADD = $(LDADD)
+bfp_3_SOURCES = bfp-3.c
+bfp_3_OBJECTS = bfp-3.$(OBJEXT)
+bfp_3_LDADD = $(LDADD)
+bfp_4_SOURCES = bfp-4.c
+bfp_4_OBJECTS = bfp-4.$(OBJEXT)
+bfp_4_LDADD = $(LDADD)
+cds_SOURCES = cds.c
+cds_OBJECTS = cds.$(OBJEXT)
+cds_LDADD = $(LDADD)
+cdsg_SOURCES = cdsg.c
+cdsg_OBJECTS = cdsg.$(OBJEXT)
+cdsg_LDADD = $(LDADD)
+cgij_SOURCES = cgij.c
+cgij_OBJECTS = cgij.$(OBJEXT)
+cgij_LDADD = $(LDADD)
+cgrj_SOURCES = cgrj.c
+cgrj_OBJECTS = cgrj.$(OBJEXT)
+cgrj_LDADD = $(LDADD)
+cij_SOURCES = cij.c
+cij_OBJECTS = cij.$(OBJEXT)
+cij_LDADD = $(LDADD)
+cksm_SOURCES = cksm.c
+cksm_OBJECTS = cksm.$(OBJEXT)
+cksm_LDADD = $(LDADD)
+clc_SOURCES = clc.c
+clc_OBJECTS = clc.$(OBJEXT)
+clc_LDADD = $(LDADD)
+clcl_SOURCES = clcl.c
+clcl_OBJECTS = clcl.$(OBJEXT)
+clcl_LDADD = $(LDADD)
+clcle_SOURCES = clcle.c
+clcle_OBJECTS = clcle.$(OBJEXT)
+clcle_LDADD = $(LDADD)
+clgij_SOURCES = clgij.c
+clgij_OBJECTS = clgij.$(OBJEXT)
+clgij_LDADD = $(LDADD)
+clgrj_SOURCES = clgrj.c
+clgrj_OBJECTS = clgrj.$(OBJEXT)
+clgrj_LDADD = $(LDADD)
+clij_SOURCES = clij.c
+clij_OBJECTS = clij.$(OBJEXT)
+clij_LDADD = $(LDADD)
+clrj_SOURCES = clrj.c
+clrj_OBJECTS = clrj.$(OBJEXT)
+clrj_LDADD = $(LDADD)
+clst_SOURCES = clst.c
+clst_OBJECTS = clst.$(OBJEXT)
+clst_LDADD = $(LDADD)
+comp_1_SOURCES = comp-1.c
+comp_1_OBJECTS = comp-1.$(OBJEXT)
+comp_1_LDADD = $(LDADD)
+comp_2_SOURCES = comp-2.c
+comp_2_OBJECTS = comp-2.$(OBJEXT)
+comp_2_LDADD = $(LDADD)
+condloadstore_SOURCES = condloadstore.c
+condloadstore_OBJECTS = condloadstore.$(OBJEXT)
+condloadstore_LDADD = $(LDADD)
+crj_SOURCES = crj.c
+crj_OBJECTS = crj.$(OBJEXT)
+crj_LDADD = $(LDADD)
+cs_SOURCES = cs.c
+cs_OBJECTS = cs.$(OBJEXT)
+cs_LDADD = $(LDADD)
+csg_SOURCES = csg.c
+csg_OBJECTS = csg.$(OBJEXT)
+csg_LDADD = $(LDADD)
+cu12_SOURCES = cu12.c
+cu12_OBJECTS = cu12.$(OBJEXT)
+cu12_LDADD = $(LDADD)
+cu12_1_SOURCES = cu12_1.c
+cu12_1_OBJECTS = cu12_1-cu12_1.$(OBJEXT)
+cu12_1_LDADD = $(LDADD)
+cu12_1_LINK = $(CCLD) $(cu12_1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+cu14_SOURCES = cu14.c
+cu14_OBJECTS = cu14.$(OBJEXT)
+cu14_LDADD = $(LDADD)
+cu14_1_SOURCES = cu14_1.c
+cu14_1_OBJECTS = cu14_1-cu14_1.$(OBJEXT)
+cu14_1_LDADD = $(LDADD)
+cu14_1_LINK = $(CCLD) $(cu14_1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+cu21_SOURCES = cu21.c
+cu21_OBJECTS = cu21.$(OBJEXT)
+cu21_LDADD = $(LDADD)
+cu21_1_SOURCES = cu21_1.c
+cu21_1_OBJECTS = cu21_1-cu21_1.$(OBJEXT)
+cu21_1_LDADD = $(LDADD)
+cu21_1_LINK = $(CCLD) $(cu21_1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+cu24_SOURCES = cu24.c
+cu24_OBJECTS = cu24.$(OBJEXT)
+cu24_LDADD = $(LDADD)
+cu24_1_SOURCES = cu24_1.c
+cu24_1_OBJECTS = cu24_1-cu24_1.$(OBJEXT)
+cu24_1_LDADD = $(LDADD)
+cu24_1_LINK = $(CCLD) $(cu24_1_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+cu41_SOURCES = cu41.c
+cu41_OBJECTS = cu41.$(OBJEXT)
+cu41_LDADD = $(LDADD)
+cu42_SOURCES = cu42.c
+cu42_OBJECTS = cu42.$(OBJEXT)
+cu42_LDADD = $(LDADD)
+cvb_SOURCES = cvb.c
+cvb_OBJECTS = cvb.$(OBJEXT)
+cvb_LDADD = $(LDADD)
+cvd_SOURCES = cvd.c
+cvd_OBJECTS = cvd.$(OBJEXT)
+cvd_LDADD = $(LDADD)
+dfp_1_SOURCES = dfp-1.c
+dfp_1_OBJECTS = dfp-1.$(OBJEXT)
+dfp_1_LDADD = $(LDADD)
+dfp_2_SOURCES = dfp-2.c
+dfp_2_OBJECTS = dfp-2.$(OBJEXT)
+dfp_2_LDADD = $(LDADD)
+dfp_3_SOURCES = dfp-3.c
+dfp_3_OBJECTS = dfp-3.$(OBJEXT)
+dfp_3_LDADD = $(LDADD)
+dfp_4_SOURCES = dfp-4.c
+dfp_4_OBJECTS = dfp-4.$(OBJEXT)
+dfp_4_LDADD = $(LDADD)
+dfpconv_SOURCES = dfpconv.c
+dfpconv_OBJECTS = dfpconv.$(OBJEXT)
+dfpconv_LDADD = $(LDADD)
+dfpext_SOURCES = dfpext.c
+dfpext_OBJECTS = dfpext.$(OBJEXT)
+dfpext_LDADD = $(LDADD)
+dfptest_SOURCES = dfptest.c
+dfptest_OBJECTS = dfptest.$(OBJEXT)
+dfptest_LDADD = $(LDADD)
+div_SOURCES = div.c
+div_OBJECTS = div.$(OBJEXT)
+div_LDADD = $(LDADD)
+ecag_SOURCES = ecag.c
+ecag_OBJECTS = ecag.$(OBJEXT)
+ecag_LDADD = $(LDADD)
+ex_SOURCES = ex.c
+ex_OBJECTS = ex.$(OBJEXT)
+ex_LDADD = $(LDADD)
+ex_clone_SOURCES = ex_clone.c
+ex_clone_OBJECTS = ex_clone.$(OBJEXT)
+ex_clone_DEPENDENCIES =
+ex_sig_SOURCES = ex_sig.c
+ex_sig_OBJECTS = ex_sig.$(OBJEXT)
+ex_sig_LDADD = $(LDADD)
+exrl_SOURCES = exrl.c
+exrl_OBJECTS = exrl.$(OBJEXT)
+exrl_LDADD = $(LDADD)
+fgx_SOURCES = fgx.c
+fgx_OBJECTS = fgx.$(OBJEXT)
+fgx_LDADD = $(LDADD)
+fixbr_SOURCES = fixbr.c
+fixbr_OBJECTS = fixbr-fixbr.$(OBJEXT)
+fixbr_LDADD = $(LDADD)
+fixbr_LINK = $(CCLD) $(fixbr_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+flogr_SOURCES = flogr.c
+flogr_OBJECTS = flogr.$(OBJEXT)
+flogr_LDADD = $(LDADD)
+fold_And16_SOURCES = fold_And16.c
+fold_And16_OBJECTS = fold_And16.$(OBJEXT)
+fold_And16_LDADD = $(LDADD)
+fpconv_SOURCES = fpconv.c
+fpconv_OBJECTS = fpconv.$(OBJEXT)
+fpconv_LDADD = $(LDADD)
+fpext_SOURCES = fpext.c
+fpext_OBJECTS = fpext-fpext.$(OBJEXT)
+fpext_LDADD = $(LDADD)
+fpext_LINK = $(CCLD) $(fpext_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+fpext_warn_SOURCES = fpext_warn.c
+fpext_warn_OBJECTS = fpext_warn.$(OBJEXT)
+fpext_warn_LDADD = $(LDADD)
+high_word_SOURCES = high-word.c
+high_word_OBJECTS = high-word.$(OBJEXT)
+high_word_LDADD = $(LDADD)
+icm_SOURCES = icm.c
+icm_OBJECTS = icm.$(OBJEXT)
+icm_LDADD = $(LDADD)
+insert_SOURCES = insert.c
+insert_OBJECTS = insert.$(OBJEXT)
+insert_LDADD = $(LDADD)
+insert_EI_SOURCES = insert_EI.c
+insert_EI_OBJECTS = insert_EI.$(OBJEXT)
+insert_EI_LDADD = $(LDADD)
+laa_SOURCES = laa.c
+laa_OBJECTS = laa.$(OBJEXT)
+laa_LDADD = $(LDADD)
+lam_stam_SOURCES = lam_stam.c
+lam_stam_OBJECTS = lam_stam.$(OBJEXT)
+lam_stam_LDADD = $(LDADD)
+lpr_SOURCES = lpr.c
+lpr_OBJECTS = lpr.$(OBJEXT)
+lpr_LDADD = $(LDADD)
+mul_SOURCES = mul.c
+mul_OBJECTS = mul.$(OBJEXT)
+mul_LDADD = $(LDADD)
+mul_GE_SOURCES = mul_GE.c
+mul_GE_OBJECTS = mul_GE.$(OBJEXT)
+mul_GE_LDADD = $(LDADD)
+mvc_SOURCES = mvc.c
+mvc_OBJECTS = mvc.$(OBJEXT)
+mvc_LDADD = $(LDADD)
+mvcl_SOURCES = mvcl.c
+mvcl_OBJECTS = mvcl.$(OBJEXT)
+mvcl_LDADD = $(LDADD)
+mvst_SOURCES = mvst.c
+mvst_OBJECTS = mvst.$(OBJEXT)
+mvst_LDADD = $(LDADD)
+op00_SOURCES = op00.c
+op00_OBJECTS = op00.$(OBJEXT)
+op00_LDADD = $(LDADD)
+op_exception_SOURCES = op_exception.c
+op_exception_OBJECTS = op_exception.$(OBJEXT)
+op_exception_LDADD = $(LDADD)
+or_SOURCES = or.c
+or_OBJECTS = or.$(OBJEXT)
+or_LDADD = $(LDADD)
+or_EI_SOURCES = or_EI.c
+or_EI_OBJECTS = or_EI.$(OBJEXT)
+or_EI_LDADD = $(LDADD)
+pfpo_SOURCES = pfpo.c
+pfpo_OBJECTS = pfpo.$(OBJEXT)
+pfpo_LDADD = $(LDADD)
+popcnt_SOURCES = popcnt.c
+popcnt_OBJECTS = popcnt.$(OBJEXT)
+popcnt_LDADD = $(LDADD)
+rounding_1_SOURCES = rounding-1.c
+rounding_1_OBJECTS = rounding-1.$(OBJEXT)
+rounding_1_LDADD = $(LDADD)
+rounding_2_SOURCES = rounding-2.c
+rounding_2_OBJECTS = rounding-2.$(OBJEXT)
+rounding_2_LDADD = $(LDADD)
+rounding_3_SOURCES = rounding-3.c
+rounding_3_OBJECTS = rounding-3.$(OBJEXT)
+rounding_3_LDADD = $(LDADD)
+rounding_4_SOURCES = rounding-4.c
+rounding_4_OBJECTS = rounding-4.$(OBJEXT)
+rounding_4_LDADD = $(LDADD)
+rounding_5_SOURCES = rounding-5.c
+rounding_5_OBJECTS = rounding-5.$(OBJEXT)
+rounding_5_LDADD = $(LDADD)
+rounding_6_SOURCES = rounding-6.c
+rounding_6_OBJECTS = rounding-6.$(OBJEXT)
+rounding_6_LDADD = $(LDADD)
+rxsbg_SOURCES = rxsbg.c
+rxsbg_OBJECTS = rxsbg.$(OBJEXT)
+rxsbg_LDADD = $(LDADD)
+spechelper_algr_SOURCES = spechelper-algr.c
+spechelper_algr_OBJECTS = spechelper-algr.$(OBJEXT)
+spechelper_algr_LDADD = $(LDADD)
+spechelper_alr_SOURCES = spechelper-alr.c
+spechelper_alr_OBJECTS = spechelper-alr.$(OBJEXT)
+spechelper_alr_LDADD = $(LDADD)
+spechelper_clr_SOURCES = spechelper-clr.c
+spechelper_clr_OBJECTS = spechelper-clr.$(OBJEXT)
+spechelper_clr_LDADD = $(LDADD)
+spechelper_cr_SOURCES = spechelper-cr.c
+spechelper_cr_OBJECTS = spechelper-cr.$(OBJEXT)
+spechelper_cr_LDADD = $(LDADD)
+spechelper_icm_1_SOURCES = spechelper-icm-1.c
+spechelper_icm_1_OBJECTS = spechelper-icm-1.$(OBJEXT)
+spechelper_icm_1_LDADD = $(LDADD)
+spechelper_icm_2_SOURCES = spechelper-icm-2.c
+spechelper_icm_2_OBJECTS = spechelper-icm-2.$(OBJEXT)
+spechelper_icm_2_LDADD = $(LDADD)
+spechelper_ltr_SOURCES = spechelper-ltr.c
+spechelper_ltr_OBJECTS = spechelper-ltr.$(OBJEXT)
+spechelper_ltr_LDADD = $(LDADD)
+spechelper_or_SOURCES = spechelper-or.c
+spechelper_or_OBJECTS = spechelper-or.$(OBJEXT)
+spechelper_or_LDADD = $(LDADD)
+spechelper_slgr_SOURCES = spechelper-slgr.c
+spechelper_slgr_OBJECTS = spechelper-slgr.$(OBJEXT)
+spechelper_slgr_LDADD = $(LDADD)
+spechelper_slr_SOURCES = spechelper-slr.c
+spechelper_slr_OBJECTS = spechelper-slr.$(OBJEXT)
+spechelper_slr_LDADD = $(LDADD)
+spechelper_tm_SOURCES = spechelper-tm.c
+spechelper_tm_OBJECTS = spechelper-tm.$(OBJEXT)
+spechelper_tm_LDADD = $(LDADD)
+spechelper_tmll_SOURCES = spechelper-tmll.c
+spechelper_tmll_OBJECTS = spechelper-tmll.$(OBJEXT)
+spechelper_tmll_LDADD = $(LDADD)
+srnm_SOURCES = srnm.c
+srnm_OBJECTS = srnm.$(OBJEXT)
+srnm_LDADD = $(LDADD)
+srnmb_SOURCES = srnmb.c
+srnmb_OBJECTS = srnmb.$(OBJEXT)
+srnmb_LDADD = $(LDADD)
+srnmt_SOURCES = srnmt.c
+srnmt_OBJECTS = srnmt.$(OBJEXT)
+srnmt_LDADD = $(LDADD)
+srst_SOURCES = srst.c
+srst_OBJECTS = srst.$(OBJEXT)
+srst_LDADD = $(LDADD)
+stck_SOURCES = stck.c
+stck_OBJECTS = stck.$(OBJEXT)
+stck_LDADD = $(LDADD)
+stcke_SOURCES = stcke.c
+stcke_OBJECTS = stcke.$(OBJEXT)
+stcke_LDADD = $(LDADD)
+stckf_SOURCES = stckf.c
+stckf_OBJECTS = stckf.$(OBJEXT)
+stckf_LDADD = $(LDADD)
+stfle_SOURCES = stfle.c
+stfle_OBJECTS = stfle.$(OBJEXT)
+stfle_LDADD = $(LDADD)
+stmg_SOURCES = stmg.c
+stmg_OBJECTS = stmg.$(OBJEXT)
+stmg_LDADD = $(LDADD)
+sub_SOURCES = sub.c
+sub_OBJECTS = sub.$(OBJEXT)
+sub_LDADD = $(LDADD)
+sub_EI_SOURCES = sub_EI.c
+sub_EI_OBJECTS = sub_EI.$(OBJEXT)
+sub_EI_LDADD = $(LDADD)
+tcxb_SOURCES = tcxb.c
+tcxb_OBJECTS = tcxb-tcxb.$(OBJEXT)
+tcxb_LDADD = $(LDADD)
+tcxb_LINK = $(CCLD) $(tcxb_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) \
+ -o $@
+test_fork_SOURCES = test_fork.c
+test_fork_OBJECTS = test_fork.$(OBJEXT)
+test_fork_LDADD = $(LDADD)
+test_sig_SOURCES = test_sig.c
+test_sig_OBJECTS = test_sig.$(OBJEXT)
+test_sig_LDADD = $(LDADD)
+tm_SOURCES = tm.c
+tm_OBJECTS = tm.$(OBJEXT)
+tm_LDADD = $(LDADD)
+tmll_SOURCES = tmll.c
+tmll_OBJECTS = tmll.$(OBJEXT)
+tmll_LDADD = $(LDADD)
+tr_SOURCES = tr.c
+tr_OBJECTS = tr.$(OBJEXT)
+tr_LDADD = $(LDADD)
+tre_SOURCES = tre.c
+tre_OBJECTS = tre.$(OBJEXT)
+tre_LDADD = $(LDADD)
+troo_SOURCES = troo.c
+troo_OBJECTS = troo.$(OBJEXT)
+troo_LDADD = $(LDADD)
+trot_SOURCES = trot.c
+trot_OBJECTS = trot.$(OBJEXT)
+trot_LDADD = $(LDADD)
+trto_SOURCES = trto.c
+trto_OBJECTS = trto.$(OBJEXT)
+trto_LDADD = $(LDADD)
+trtt_SOURCES = trtt.c
+trtt_OBJECTS = trtt.$(OBJEXT)
+trtt_LDADD = $(LDADD)
+xc_SOURCES = xc.c
+xc_OBJECTS = xc.$(OBJEXT)
+xc_LDADD = $(LDADD)
+xor_SOURCES = xor.c
+xor_OBJECTS = xor.$(OBJEXT)
+xor_LDADD = $(LDADD)
+xor_EI_SOURCES = xor_EI.c
+xor_EI_OBJECTS = xor_EI.$(OBJEXT)
+xor_EI_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+AM_V_P = $(am__v_P_@AM_V@)
+am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
+am__v_P_0 = false
+am__v_P_1 = :
+AM_V_GEN = $(am__v_GEN_@AM_V@)
+am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@)
+am__v_GEN_0 = @echo " GEN " $@;
+am__v_GEN_1 =
+AM_V_at = $(am__v_at_@AM_V@)
+am__v_at_ = $(am__v_at_@AM_DEFAULT_V@)
+am__v_at_0 = @
+am__v_at_1 =
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+AM_V_lt = $(am__v_lt_@AM_V@)
+am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)
+am__v_lt_0 = --silent
+am__v_lt_1 =
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+AM_V_CC = $(am__v_CC_@AM_V@)
+am__v_CC_ = $(am__v_CC_@AM_DEFAULT_V@)
+am__v_CC_0 = @echo " CC " $@;
+am__v_CC_1 =
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+AM_V_CCLD = $(am__v_CCLD_@AM_V@)
+am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
+am__v_CCLD_0 = @echo " CCLD " $@;
+am__v_CCLD_1 =
+SOURCES = add.c add_EI.c add_GE.c allexec.c and.c and_EI.c bfp-1.c \
+ bfp-2.c bfp-3.c bfp-4.c cds.c cdsg.c cgij.c cgrj.c cij.c \
+ cksm.c clc.c clcl.c clcle.c clgij.c clgrj.c clij.c clrj.c \
+ clst.c comp-1.c comp-2.c condloadstore.c crj.c cs.c csg.c \
+ cu12.c cu12_1.c cu14.c cu14_1.c cu21.c cu21_1.c cu24.c \
+ cu24_1.c cu41.c cu42.c cvb.c cvd.c dfp-1.c dfp-2.c dfp-3.c \
+ dfp-4.c dfpconv.c dfpext.c dfptest.c div.c ecag.c ex.c \
+ ex_clone.c ex_sig.c exrl.c fgx.c fixbr.c flogr.c fold_And16.c \
+ fpconv.c fpext.c fpext_warn.c high-word.c icm.c insert.c \
+ insert_EI.c laa.c lam_stam.c lpr.c mul.c mul_GE.c mvc.c mvcl.c \
+ mvst.c op00.c op_exception.c or.c or_EI.c pfpo.c popcnt.c \
+ rounding-1.c rounding-2.c rounding-3.c rounding-4.c \
+ rounding-5.c rounding-6.c rxsbg.c spechelper-algr.c \
+ spechelper-alr.c spechelper-clr.c spechelper-cr.c \
+ spechelper-icm-1.c spechelper-icm-2.c spechelper-ltr.c \
+ spechelper-or.c spechelper-slgr.c spechelper-slr.c \
+ spechelper-tm.c spechelper-tmll.c srnm.c srnmb.c srnmt.c \
+ srst.c stck.c stcke.c stckf.c stfle.c stmg.c sub.c sub_EI.c \
+ tcxb.c test_fork.c test_sig.c tm.c tmll.c tr.c tre.c troo.c \
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+ cij.c cksm.c clc.c clcl.c clcle.c clgij.c clgrj.c clij.c \
+ clrj.c clst.c comp-1.c comp-2.c condloadstore.c crj.c cs.c \
+ csg.c cu12.c cu12_1.c cu14.c cu14_1.c cu21.c cu21_1.c cu24.c \
+ cu24_1.c cu41.c cu42.c cvb.c cvd.c dfp-1.c dfp-2.c dfp-3.c \
+ dfp-4.c dfpconv.c dfpext.c dfptest.c div.c ecag.c ex.c \
+ ex_clone.c ex_sig.c exrl.c fgx.c fixbr.c flogr.c fold_And16.c \
+ fpconv.c fpext.c fpext_warn.c high-word.c icm.c insert.c \
+ insert_EI.c laa.c lam_stam.c lpr.c mul.c mul_GE.c mvc.c mvcl.c \
+ mvst.c op00.c op_exception.c or.c or_EI.c pfpo.c popcnt.c \
+ rounding-1.c rounding-2.c rounding-3.c rounding-4.c \
+ rounding-5.c rounding-6.c rxsbg.c spechelper-algr.c \
+ spechelper-alr.c spechelper-clr.c spechelper-cr.c \
+ spechelper-icm-1.c spechelper-icm-2.c spechelper-ltr.c \
+ spechelper-or.c spechelper-slgr.c spechelper-slr.c \
+ spechelper-tm.c spechelper-tmll.c srnm.c srnmb.c srnmt.c \
+ srst.c stck.c stcke.c stckf.c stfle.c stmg.c sub.c sub_EI.c \
+ tcxb.c test_fork.c test_sig.c tm.c tmll.c tr.c tre.c troo.c \
+ trot.c trto.c trtt.c xc.c xor.c xor_EI.c
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+#----------------------------------------------------------------------------
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+# Baseline flags for all compilations. Aim here is to maximise
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+
+
+# These flags are used for building the preload shared objects (PSOs).
+# The aim is to give reasonable performance but also to have good
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+
+# Flags for specific targets.
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+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
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+
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+
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+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
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+ -mmacosx-version-min=10.6 -fno-stack-protector
+
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+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
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+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
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+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
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+
+# Baseline link flags for making vgpreload shared objects.
+#
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+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
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+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
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+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
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+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
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+ mul and or xor insert div srst fold_And16 flogr sub_EI add_EI \
+ and_EI or_EI xor_EI insert_EI mul_GE add_GE condloadstore \
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+ ex clst mvc test_fork test_sig rounding-6 rxsbg popcnt \
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+ fixbr.vgtest fixbr.stderr.exp fixbr.stdout.exp \
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+ test.h opcodes.h add.h and.h div.h insert.h dfp_utils.h \
+ mul.h or.h sub.h xor.h table.h svc.h rounding.h \
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+ dfp-2.stderr.exp dfp-2.stdout.exp dfp-2.vgtest \
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+ dfpconv.stderr.exp dfpconv.stdout.exp dfpconv.vgtest \
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+ pfpo.stderr.exp pfpo.stdout.exp pfpo.vgtest
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+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/fpext-fpext.Tpo $(DEPDIR)/fpext-fpext.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='fpext.c' object='fpext-fpext.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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+
+fpext-fpext.obj: fpext.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(fpext_CFLAGS) $(CFLAGS) -MT fpext-fpext.obj -MD -MP -MF $(DEPDIR)/fpext-fpext.Tpo -c -o fpext-fpext.obj `if test -f 'fpext.c'; then $(CYGPATH_W) 'fpext.c'; else $(CYGPATH_W) '$(srcdir)/fpext.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/fpext-fpext.Tpo $(DEPDIR)/fpext-fpext.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='fpext.c' object='fpext-fpext.obj' libtool=no @AMDEPBACKSLASH@
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+
+tcxb-tcxb.o: tcxb.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tcxb_CFLAGS) $(CFLAGS) -MT tcxb-tcxb.o -MD -MP -MF $(DEPDIR)/tcxb-tcxb.Tpo -c -o tcxb-tcxb.o `test -f 'tcxb.c' || echo '$(srcdir)/'`tcxb.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tcxb-tcxb.Tpo $(DEPDIR)/tcxb-tcxb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='tcxb.c' object='tcxb-tcxb.o' libtool=no @AMDEPBACKSLASH@
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+
+tcxb-tcxb.obj: tcxb.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tcxb_CFLAGS) $(CFLAGS) -MT tcxb-tcxb.obj -MD -MP -MF $(DEPDIR)/tcxb-tcxb.Tpo -c -o tcxb-tcxb.obj `if test -f 'tcxb.c'; then $(CYGPATH_W) 'tcxb.c'; else $(CYGPATH_W) '$(srcdir)/tcxb.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tcxb-tcxb.Tpo $(DEPDIR)/tcxb-tcxb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='tcxb.c' object='tcxb-tcxb.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tcxb_CFLAGS) $(CFLAGS) -c -o tcxb-tcxb.obj `if test -f 'tcxb.c'; then $(CYGPATH_W) 'tcxb.c'; else $(CYGPATH_W) '$(srcdir)/tcxb.c'; fi`
+
+ID: $(am__tagged_files)
+ $(am__define_uniq_tagged_files); mkid -fID $$unique
+tags: tags-am
+TAGS: tags
+
+tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+ set x; \
+ here=`pwd`; \
+ $(am__define_uniq_tagged_files); \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: ctags-am
+
+CTAGS: ctags
+ctags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+ $(am__define_uniq_tagged_files); \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+cscopelist: cscopelist-am
+
+cscopelist-am: $(am__tagged_files)
+ list='$(am__tagged_files)'; \
+ case "$(srcdir)" in \
+ [\\/]* | ?:[\\/]*) sdir="$(srcdir)" ;; \
+ *) sdir=$(subdir)/$(srcdir) ;; \
+ esac; \
+ for i in $$list; do \
+ if test -f "$$i"; then \
+ echo "$(subdir)/$$i"; \
+ else \
+ echo "$$sdir/$$i"; \
+ fi; \
+ done >> $(top_builddir)/cscope.files
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
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+install-am: all-am
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+installcheck: installcheck-am
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+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ install; \
+ else \
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \
+ fi
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
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+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
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+.PHONY: CTAGS GTAGS TAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local cscopelist-am \
+ ctags ctags-am distclean distclean-compile distclean-generic \
+ distclean-tags distdir dvi dvi-am html html-am info info-am \
+ install install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-html \
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+ maintainer-clean maintainer-clean-generic mostlyclean \
+ mostlyclean-compile mostlyclean-generic pdf pdf-am ps ps-am \
+ tags tags-am uninstall uninstall-am
+
+.PRECIOUS: Makefile
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
+# It needs to be depended on by an 'uninstall-local' rule.
+uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
+uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/none/tests/s390x/allexec.c b/none/tests/s390x/allexec.c
deleted file mode 120000
index 6d6a9cf..0000000
--- a/none/tests/s390x/allexec.c
+++ /dev/null
@@ -1 +0,0 @@
-../allexec.c
\ No newline at end of file
diff --git a/none/tests/allexec.c b/none/tests/s390x/allexec.c
similarity index 100%
copy from none/tests/allexec.c
copy to none/tests/s390x/allexec.c
diff --git a/none/tests/s390x/bfp-2.c b/none/tests/s390x/bfp-2.c
index 5dae5ff..a4295da 100644
--- a/none/tests/s390x/bfp-2.c
+++ b/none/tests/s390x/bfp-2.c
@@ -71,6 +71,26 @@
printf("lcdbr %f -> %f\n", in, out);
}
+void lder(double prev, float in)
+{
+ unsigned long out;
+
+ __asm__ volatile("lder %[prev],%[in]\n\t"
+ "std %[prev],%[out]" :
+ [out]"=R"(out) : [prev]"f"(prev), [in]"f"(in));
+ printf("lder %f -> %lx\n", in, out);
+}
+
+void lde(double prev, float in)
+{
+ unsigned long out;
+
+ __asm__ volatile("lde %[prev],%[in]\n\t"
+ "std %[prev],%[out]" :
+ [out]"=R"(out) : [prev]"f"(prev), [in]"R"(in));
+ printf("lde %f -> %lx\n", in, out);
+}
+
int main(void)
{
// square root
@@ -98,5 +118,11 @@
lcdbr(-17.5); // 8 byte values
lcdbr(234.5); // 8 byte values
+ // load lengthened
+ lder(0.2, 321.5f);
+ lder(0.9, -8388607.f);
+ lde(0.2, -321.5f);
+ lde(0.9, 8388607.f);
+
return 0;
}
diff --git a/none/tests/s390x/bfp-2.stdout.exp b/none/tests/s390x/bfp-2.stdout.exp
index 074180a..b1bc484 100644
--- a/none/tests/s390x/bfp-2.stdout.exp
+++ b/none/tests/s390x/bfp-2.stdout.exp
@@ -12,3 +12,7 @@
lcebr 123.500000 -> -123.500000
lcdbr -17.500000 -> 17.500000
lcdbr 234.500000 -> -234.500000
+lder 321.500000 -> 43a0c00000000000
+lder -8388607.000000 -> cafffffe00000000
+lde -321.500000 -> c3a0c00000000000
+lde 8388607.000000 -> 4afffffe00000000
diff --git a/none/tests/s390x/cu12_1.c b/none/tests/s390x/cu12_1.c
deleted file mode 120000
index a331548..0000000
--- a/none/tests/s390x/cu12_1.c
+++ /dev/null
@@ -1 +0,0 @@
-cu12.c
\ No newline at end of file
diff --git a/none/tests/s390x/cu12_1.c b/none/tests/s390x/cu12_1.c
new file mode 100644
index 0000000..1281118
--- /dev/null
+++ b/none/tests/s390x/cu12_1.c
@@ -0,0 +1,595 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "opcodes.h"
+
+#ifndef M3
+#define M3 0
+#endif
+
+/* The abstracted result of an CU12 insn */
+typedef struct {
+ uint64_t addr1; // target
+ uint64_t len1;
+ uint64_t addr2; // source
+ uint64_t len2;
+ uint32_t cc;
+} cu12_t;
+
+/* Define various input buffers. */
+
+/* 1-byte UTF-8 character */
+uint8_t pattern1[] = {
+ 0x00, 0x01, 0x02, 0x03
+};
+
+/* 2-byte UTF-8 character */
+uint8_t pattern2[] = {
+ 0xc2, 0x80,
+ 0xc2, 0x81,
+ 0xc2, 0x82,
+ 0xc2, 0x83,
+};
+
+/* 3-byte UTF-8 character */
+uint8_t pattern3[] = {
+ 0xe1, 0x80, 0x80,
+ 0xe1, 0x80, 0x81,
+ 0xe1, 0x80, 0x82,
+ 0xe1, 0x80, 0x83,
+};
+
+/* 4-byte UTF-8 character */
+uint8_t pattern4[] = {
+ 0xf4, 0x80, 0x80, 0x80,
+ 0xf4, 0x80, 0x80, 0x81,
+ 0xf4, 0x80, 0x80, 0x82,
+ 0xf4, 0x80, 0x80, 0x83,
+};
+
+
+/* Mixed bytes */
+uint8_t mixed[] = {
+ 0x01, // 1 byte
+ 0xc3, 0x80, // 2 bytes
+ 0x12, // 1 byte
+ 0xe1, 0x90, 0x93, // 3 bytes
+ 0x23, // 1 byte
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0x34, // 1 byte
+ 0xc4, 0x8c, // 2 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+ 0xc5, 0x8a, // 2 bytes
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0xc5, 0x8a, // 2 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+};
+
+/* This is the buffer for the converted bytes. */
+uint16_t buff[1000]; /* Large so we con'don't have to worry about it */
+
+
+static cu12_t
+do_cu12(uint16_t *dst, uint64_t dst_len, uint8_t *src, uint64_t src_len)
+{
+ int cc = 42;
+ cu12_t regs;
+
+ /* build up the register pairs */
+ register uint8_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint16_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU12(M3,2,4)
+ "ipm %2\n\t"
+ "srl %2,28\n\t"
+ : "+d"(dest), "+d"(source), "=d"(cc),
+ "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+
+ /* Capture register contents at end of cu12 */
+ regs.addr1 = (uint64_t)dest;
+ regs.len1 = dest_len;
+ regs.addr2 = (uint64_t)source;
+ regs.len2 = source_len;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void
+run_test(uint16_t *dst, uint64_t dst_len, uint8_t *src, uint64_t src_len)
+{
+ int i;
+ cu12_t result;
+
+ printf("UTF8: ");
+ if (src_len == 0)
+ printf(" <none>");
+ else {
+ for(i = 0; i < src_len; ++i)
+ printf(" %02x", src[i]);
+ }
+ printf("\n");
+
+ result = do_cu12(dst, dst_len, src, src_len);
+
+ // Write out the converted byte, if any
+ printf("UTF16: ");
+ if (dst_len - result.len1 == 0)
+ printf(" <none>");
+ else {
+ uint64_t num_bytes = dst_len - result.len1;
+
+ /* The number of bytes that were written must be divisible by 2 */
+ if (num_bytes % 2 != 0)
+ fprintf(stderr, "*** number of bytes is not a multiple of 2\n");
+
+ for (i = 0; i < num_bytes / 2; i++) {
+ printf(" %04x", dst[i]);
+ }
+ }
+ printf("\n");
+
+ printf(" cc = %d\n", result.cc);
+ if (dst != NULL)
+ printf(" dst address difference: %"PRId64, result.addr1 - (uint64_t)dst);
+ printf(" dst len: %"PRId64"\n", result.len1);
+
+ if (src != NULL)
+ printf(" src address difference: %"PRId64, result.addr2 - (uint64_t)src);
+ printf(" src len: %"PRId64"\n", result.len2);
+}
+
+// Test conversion of a one-byte character
+void convert_1_byte(void)
+{
+ int i;
+
+ printf("===== Conversion of a one-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ uint8_t valid[] = {
+ 0x00, 0x7f, // corner cases
+ 0x01, 0x10, 0x7e, 0x5d // misc
+ };
+ run_test(buff, sizeof buff, valid, sizeof valid);
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters -----\n");
+ uint8_t always_invalid[] = {
+ 0x80, 0xbf, // corner cases
+ 0xf8, 0xff, // corner cases
+ 0x81, 0xbe, 0x95, 0xab // misc
+ };
+ for (i = 0; i < sizeof always_invalid; ++i) {
+ uint8_t invalid_char[1];
+ invalid_char[0] = always_invalid[i];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ // In case of m3 == 0 we get cc=0 indicating exhaustion of source
+ printf("\n----- Invalid characters if m3 == 1 -----\n");
+ uint8_t invalid_if_m3[] = { // contains all such invalid characters
+ 0xc0, 0xc1,
+ 0xf5, 0xf6, 0xf7
+ };
+ for (i = 0; i < sizeof invalid_if_m3; ++i) {
+ uint8_t invalid_char[1];
+ invalid_char[0] = invalid_if_m3[i];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0x10, // valid
+ 0xaa // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a two-byte character
+void convert_2_bytes(void)
+{
+ int i;
+
+ printf("\n===== Conversion of a two-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ uint8_t valid[] = {
+ 0xc2, 0x80, // corner case
+ 0xc2, 0xbf, // corner case
+ 0xdf, 0x80, // corner case
+ 0xdf, 0xbf, // corner case
+ 0xc3, 0xbe, 0xda, 0xbc // misc
+ };
+ run_test(buff, sizeof buff, valid, sizeof valid);
+
+ printf("\n----- Valid characters if m3 == 0 -----\n");
+ // First char is 0xc0 or 0xc1
+ uint8_t valid_if_not_m3[] = {
+ 0xc0, 0x80,
+ 0xc0, 0xbf,
+ 0xc1, 0x80,
+ 0xc0, 0xbf
+ };
+ run_test(buff, sizeof buff, valid_if_not_m3, sizeof valid_if_not_m3);
+
+ // Test for invalid two-byte characters where the 1st byte is valid
+ // The 2nd byte is invalid if not in range 0x80..0xbf, inclusive
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters if m3 == 1 -----\n");
+ uint8_t always_invalid[] = {
+ 0xc2, 0x00,
+ 0xc2, 0x7f,
+ 0xc2, 0xc0,
+ 0xc2, 0xff
+ };
+ for (i = 0; i < sizeof always_invalid; i += 2) {
+ uint8_t invalid_char[2];
+ invalid_char[0] = always_invalid[i];
+ invalid_char[1] = always_invalid[i+1];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ /* Nb: for a two-byte character we need not test the case where
+ invalidity of the character (cc=2) takes precedence over exhaustion
+ of the 1st operand (cc=1). Invalidity of the character has already
+ been tested when testing the 1st byte. */
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xc3, 0x81, // valid
+ 0xc4, 0x00 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a three-byte character
+void
+convert_3_bytes(void)
+{
+ int i;
+
+ printf("\n===== Conversion of a three-byte character =====\n");
+
+ /* Exhaustively test the 1st byte E0 - EF, and the interval boundaries for
+ the 2nd and 3rd bytes */
+ printf("\n----- Valid characters -----\n");
+ uint8_t e0[] = {
+ 0xe0, 0xa0, 0x80,
+ 0xe0, 0xbf, 0x80,
+ 0xe0, 0xa0, 0xbf,
+ 0xe0, 0xbf, 0xbf,
+ 0xe0, 0xaa, 0xbb, // random e0 .. ..
+ };
+ run_test(buff, sizeof buff, e0, sizeof e0);
+
+ uint8_t ed[] = {
+ 0xed, 0x80, 0x80,
+ 0xed, 0x9f, 0x80,
+ 0xed, 0x80, 0xbf,
+ 0xed, 0x9f, 0xbf,
+ 0xed, 0x8a, 0xbb, // random ed .. ..
+ };
+ run_test(buff, sizeof buff, ed, sizeof ed);
+
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0x80, 0x80 };
+ uint8_t exxx_2[3] = { 0x0, 0xbf, 0x80 };
+ uint8_t exxx_3[3] = { 0x0, 0x80, 0xbf };
+ uint8_t exxx_4[3] = { 0x0, 0xbf, 0xbf };
+
+ if (i == 0x00) continue; // special case e0
+ if (i == 0x0d) continue; // special case ed
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ exxx_3[0] = 0xe0 | i;
+ exxx_4[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ run_test(buff, sizeof buff, exxx_3, sizeof exxx_3);
+ run_test(buff, sizeof buff, exxx_4, sizeof exxx_4);
+ };
+
+ printf("\n----- Invalid characters (2nd byte is invalid) -----\n");
+ // Test for invalid three-byte characters where the 1st byte is valid
+ // The 2nd byte is invalid.
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ e0[0] = 0xe0; // valid
+ e0[1] = 0x9f; // invalid because outside [0xa0 .. 0xbf]
+ e0[2] = 0x80; // valid
+ run_test(buff, sizeof buff, e0, sizeof e0);
+ e0[1] = 0xc0; // invalid because outside [0xa0 .. 0xbf]
+ run_test(buff, sizeof buff, e0, sizeof e0);
+
+ ed[0] = 0xed; // valid
+ ed[1] = 0x7f; // invalid because outside [0x80 .. 0x9f]
+ ed[2] = 0x80; // valid
+ run_test(buff, sizeof buff, ed, sizeof ed);
+ ed[1] = 0xa0; // invalid because outside [0x80 .. 0x9f]
+ run_test(buff, sizeof buff, ed, sizeof ed);
+
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0x7f, 0x80 };
+ uint8_t exxx_2[3] = { 0x0, 0xc0, 0x80 };
+
+ if (i == 0x00) continue; // special case e0
+ if (i == 0x0d) continue; // special case ed
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ };
+
+ printf("\n----- Invalid characters (3rd byte is invalid) -----\n");
+ // For all 1st bytes 0xe0 .. 0xef the 3rd bytes must be in [0x80 .. 0xbf]
+ // No need to special case 0xe0 and 0xed
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0xab, 0x7f };
+ uint8_t exxx_2[3] = { 0x0, 0xab, 0xc0 };
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ };
+
+ printf("\n----- Invalid 2nd char AND output exhausted -----\n");
+ /* The character is invalid in its 2nd byte AND the output buffer is
+ exhausted (2 bytes are needed) */
+ uint8_t pat1[] = {
+ 0xe0, 0x00, 0x80
+ };
+ run_test(buff, 1, pat1, 3);
+
+ printf("\n----- Invalid 3rd char AND output exhausted -----\n");
+ /* The character is invalid in its 3rd byte AND the output buffer is
+ exhausted (2 bytes are needed) */
+ uint8_t pat2[] = {
+ 0xe4, 0x84, 0x00
+ };
+ run_test(buff, 1, pat2, 3);
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xe1, 0x90, 0x90, // valid
+ 0xe1, 0x00, 0x90 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a four-byte character
+void
+convert_4_bytes(void)
+{
+ int i, j;
+
+ printf("\n===== Conversion of a four-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ for (i = 0; i <= 4; ++i) {
+ uint8_t valid[4];
+
+ valid[0] = 0xf0 | i;
+
+ for (j = 0; j <= 1; ++j) {
+ // Byte 2
+ if (i == 0) {
+ valid[1] = j == 0 ? 0x90 : 0xbf; // 0xf0
+ } else if (i == 4) {
+ valid[1] = j == 0 ? 0x80 : 0x8f; // 0xf4
+ } else {
+ valid[1] = j == 0 ? 0x80 : 0xbf; // 0xf1 .. 0xf3
+ }
+ // Byte 3 and byte 4 have same interval 0x80 .. 0xbf
+ valid[2] = 0x80;
+ valid[3] = 0x80;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0x80;
+ valid[3] = 0xbf;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0xbf;
+ valid[3] = 0x80;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0xbf;
+ valid[3] = 0xbf;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ }
+ }
+
+ printf("\n----- Valid characters if m3 == 0 -----\n");
+ // First char is 0xf5 .. 0xf7
+ uint8_t valid_if_not_m3[] = {
+ 0xf5, 0x00, 0x00, 0x00,
+ 0xf6, 0x11, 0x22, 0x33,
+ 0xf7, 0x44, 0x55, 0x66,
+ };
+ run_test(buff, sizeof buff, valid_if_not_m3, sizeof valid_if_not_m3);
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters (2nd byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 2nd byte is invalid.
+ // All other bytes are valid
+ uint8_t f0[4], f4[4];
+
+ f0[0] = 0xf0; // valid
+ f0[1] = 0x8f; // invalid because outside [0x90 .. 0xbf]
+ f0[2] = 0x80; // valid
+ f0[3] = 0x80; // valid
+ run_test(buff, sizeof buff, f0, sizeof f0);
+ f0[1] = 0xc0; // invalid because outside [0x90 .. 0xbf]
+ run_test(buff, sizeof buff, f0, sizeof f0);
+
+ f4[0] = 0xf4; // valid
+ f4[1] = 0x7f; // invalid because outside [0x80 .. 0x8f]
+ f4[2] = 0x80; // valid
+ f4[3] = 0x80; // valid
+ run_test(buff, sizeof buff, f4, sizeof f4);
+ f4[1] = 0x90; // invalid because outside [0x80 .. 0x9f]
+ run_test(buff, sizeof buff, f4, sizeof f4);
+
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx_1[4] = { 0x0, 0x7f, 0x80, 0x80 };
+ uint8_t fxxx_2[4] = { 0x0, 0xc0, 0x80, 0x80 };
+
+ if (i == 0) continue; // special case f0
+ if (i == 4) continue; // special case f4
+
+ fxxx_1[0] = 0xf0 | i;
+ fxxx_2[0] = 0xf0 | i;
+ run_test(buff, sizeof buff, fxxx_1, sizeof fxxx_1);
+ run_test(buff, sizeof buff, fxxx_2, sizeof fxxx_2);
+ };
+
+ printf("\n----- Invalid characters (3rd byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 3rd byte is invalid.
+ // All other bytes are valid
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx[4] = { 0x0, 0x0, 0x0, 0x80 };
+
+ fxxx[0] = 0xf0 | i;
+ fxxx[1] = (i == 0) ? 0x94 : 0x84;
+ fxxx[2] = 0x7f;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ fxxx[2] = 0xc0;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ };
+
+ printf("\n----- Invalid characters (4th byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 3rd byte is invalid.
+ // All other bytes are valid
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx[4] = { 0x0, 0x0, 0x80, 0x0 };
+
+ fxxx[0] = 0xf0 | i;
+ fxxx[1] = (i == 0) ? 0x94 : 0x84;
+ fxxx[3] = 0x7f;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ fxxx[3] = 0xc0;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ };
+
+ printf("\n----- Invalid 2nd char AND output exhausted -----\n");
+ /* The character is invalid in its 2nd byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat1[] = {
+ 0xf0, 0x00, 0x80, 0x80
+ };
+ run_test(buff, 1, pat1, 4);
+
+ printf("\n----- Invalid 3rd char AND output exhausted -----\n");
+ /* The character is invalid in its 3rd byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat2[] = {
+ 0xf0, 0xaa, 0x00, 0x80
+ };
+ run_test(buff, 3, pat2, 4);
+
+ printf("\n----- Invalid 4th char AND output exhausted -----\n");
+ /* The character is invalid in its 4th byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat3[] = {
+ 0xf0, 0xaa, 0xaa, 0x00
+ };
+ run_test(buff, 3, pat3, 4);
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xf0, 0xaa, 0xaa, 0xaa, // valid
+ 0xf0, 0x00, 0x00, 0x00 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+
+int main()
+{
+ convert_1_byte();
+ convert_2_bytes();
+ convert_3_bytes();
+ convert_4_bytes();
+
+ /* Length == 0, no memory should be read or written */
+ printf("\n------------- test1 ----------------\n");
+ run_test(NULL, 0, NULL, 0);
+
+ /* Test exhaustion of source length (source bytes are valid) */
+ printf("\n------------- test2.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+ run_test(buff, sizeof buff, NULL, 0);
+ run_test(buff, sizeof buff, pattern1, 0);
+ run_test(buff, sizeof buff, pattern2, 0);
+ run_test(buff, sizeof buff, pattern2, 1);
+ run_test(buff, sizeof buff, pattern3, 0);
+ run_test(buff, sizeof buff, pattern3, 1);
+ run_test(buff, sizeof buff, pattern3, 2);
+ run_test(buff, sizeof buff, pattern4, 0);
+ run_test(buff, sizeof buff, pattern4, 1);
+ run_test(buff, sizeof buff, pattern4, 2);
+ run_test(buff, sizeof buff, pattern4, 3);
+
+ printf("\n------------- test2.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, sizeof buff, pattern1, 2);
+ run_test(buff, sizeof buff, pattern2, 5);
+ run_test(buff, sizeof buff, pattern3, 6);
+ run_test(buff, sizeof buff, pattern4, 9);
+
+ /* Test exhaustion of destination length (source bytes are valid) */
+ printf("\n------------- test3.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+
+ /* Want to write 2 or 4 bytes at a time */
+ run_test(NULL, 0, pattern1, sizeof pattern1); // 2-byte result
+ run_test(NULL, 0, pattern2, sizeof pattern2); // 2-byte result
+ run_test(NULL, 1, pattern2, sizeof pattern2); // 2-byte result
+ run_test(NULL, 0, pattern3, sizeof pattern3); // 2-byte result
+ run_test(NULL, 1, pattern3, sizeof pattern3); // 2-byte result
+ run_test(NULL, 0, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 1, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 2, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 3, pattern4, sizeof pattern4); // 4-byte result
+
+ printf("\n------------- test3.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, 4, pattern1, sizeof pattern1);
+ run_test(buff, 5, pattern1, sizeof pattern2);
+ run_test(buff, 6, pattern1, sizeof pattern3);
+ run_test(buff, 7, pattern1, sizeof pattern4);
+
+ /* Convert buffer with mixed characters */
+ printf("\n------------- test4 ----------------\n");
+ run_test(buff, sizeof buff, mixed, sizeof mixed);
+
+ return 0;
+}
diff --git a/none/tests/s390x/cu14_1.c b/none/tests/s390x/cu14_1.c
deleted file mode 120000
index d0d84e8..0000000
--- a/none/tests/s390x/cu14_1.c
+++ /dev/null
@@ -1 +0,0 @@
-cu14.c
\ No newline at end of file
diff --git a/none/tests/s390x/cu14_1.c b/none/tests/s390x/cu14_1.c
new file mode 100644
index 0000000..44738c7
--- /dev/null
+++ b/none/tests/s390x/cu14_1.c
@@ -0,0 +1,595 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "opcodes.h"
+
+#ifndef M3
+#define M3 0
+#endif
+
+/* The abstracted result of an CU14 insn */
+typedef struct {
+ uint64_t addr1; // target
+ uint64_t len1;
+ uint64_t addr2; // source
+ uint64_t len2;
+ uint32_t cc;
+} cu14_t;
+
+/* Define various input buffers. */
+
+/* 1-byte UTF-8 character */
+uint8_t pattern1[] = {
+ 0x00, 0x01, 0x02, 0x03
+};
+
+/* 2-byte UTF-8 character */
+uint8_t pattern2[] = {
+ 0xc2, 0x80,
+ 0xc2, 0x81,
+ 0xc2, 0x82,
+ 0xc2, 0x83,
+};
+
+/* 3-byte UTF-8 character */
+uint8_t pattern3[] = {
+ 0xe1, 0x80, 0x80,
+ 0xe1, 0x80, 0x81,
+ 0xe1, 0x80, 0x82,
+ 0xe1, 0x80, 0x83,
+};
+
+/* 4-byte UTF-8 character */
+uint8_t pattern4[] = {
+ 0xf4, 0x80, 0x80, 0x80,
+ 0xf4, 0x80, 0x80, 0x81,
+ 0xf4, 0x80, 0x80, 0x82,
+ 0xf4, 0x80, 0x80, 0x83,
+};
+
+
+/* Mixed bytes */
+uint8_t mixed[] = {
+ 0x01, // 1 byte
+ 0xc3, 0x80, // 2 bytes
+ 0x12, // 1 byte
+ 0xe1, 0x90, 0x93, // 3 bytes
+ 0x23, // 1 byte
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0x34, // 1 byte
+ 0xc4, 0x8c, // 2 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+ 0xc5, 0x8a, // 2 bytes
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0xc5, 0x8a, // 2 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+ 0xf4, 0x80, 0x90, 0x8a, // 4 bytes
+ 0xe1, 0x91, 0x94, // 3 bytes
+};
+
+/* This is the buffer for the converted bytes. */
+uint32_t buff[500]; /* Large so we con'don't have to worry about it */
+
+
+static cu14_t
+do_cu14(uint32_t *dst, uint64_t dst_len, uint8_t *src, uint64_t src_len)
+{
+ int cc = 42;
+ cu14_t regs;
+
+ /* build up the register pairs */
+ register uint8_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint32_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU14(M3,2,4)
+ "ipm %2\n\t"
+ "srl %2,28\n\t"
+ : "+d"(dest), "+d"(source), "=d"(cc),
+ "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+
+ /* Capture register contents at end of cu14 */
+ regs.addr1 = (uint64_t)dest;
+ regs.len1 = dest_len;
+ regs.addr2 = (uint64_t)source;
+ regs.len2 = source_len;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void
+run_test(uint32_t *dst, uint64_t dst_len, uint8_t *src, uint64_t src_len)
+{
+ int i;
+ cu14_t result;
+
+ printf("UTF8: ");
+ if (src_len == 0)
+ printf(" <none>");
+ else {
+ for(i = 0; i < src_len; ++i)
+ printf(" %02x", src[i]);
+ }
+ printf("\n");
+
+ result = do_cu14(dst, dst_len, src, src_len);
+
+ // Write out the converted bytes, if any
+ printf("UTF32: ");
+ if (dst_len - result.len1 == 0)
+ printf(" <none>");
+ else {
+ uint64_t num_bytes = dst_len - result.len1;
+
+ /* The number of bytes that were written must be divisible by 4 */
+ if (num_bytes % 4 != 0)
+ fprintf(stderr, "*** number of bytes is not a multiple of 4\n");
+
+ for (i = 0; i < num_bytes / 4; i++) {
+ printf(" %08x", dst[i]);
+ }
+ }
+ printf("\n");
+
+ printf(" cc = %d\n", result.cc);
+ if (dst != NULL)
+ printf(" dst address difference: %"PRId64, result.addr1 - (uint64_t)dst);
+ printf(" dst len: %"PRId64"\n", result.len1);
+
+ if (src != NULL)
+ printf(" src address difference: %"PRId64, result.addr2 - (uint64_t)src);
+ printf(" src len: %"PRId64"\n", result.len2);
+}
+
+// Test conversion of a one-byte character
+void convert_1_byte(void)
+{
+ int i;
+
+ printf("===== Conversion of a one-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ uint8_t valid[] = {
+ 0x00, 0x7f, // corner cases
+ 0x01, 0x10, 0x7e, 0x5d // misc
+ };
+ run_test(buff, sizeof buff, valid, sizeof valid);
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters -----\n");
+ uint8_t always_invalid[] = {
+ 0x80, 0xbf, // corner cases
+ 0xf8, 0xff, // corner cases
+ 0x81, 0xbe, 0x95, 0xab // misc
+ };
+ for (i = 0; i < sizeof always_invalid; ++i) {
+ uint8_t invalid_char[1];
+ invalid_char[0] = always_invalid[i];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ // In case of m3 == 0 we get cc=0 indicating exhaustion of source
+ printf("\n----- Invalid characters if m3 == 1 -----\n");
+ uint8_t invalid_if_m3[] = { // contains all such invalid characters
+ 0xc0, 0xc1,
+ 0xf5, 0xf6, 0xf7
+ };
+ for (i = 0; i < sizeof invalid_if_m3; ++i) {
+ uint8_t invalid_char[1];
+ invalid_char[0] = invalid_if_m3[i];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0x10, // valid
+ 0xaa // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a two-byte character
+void convert_2_bytes(void)
+{
+ int i;
+
+ printf("\n===== Conversion of a two-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ uint8_t valid[] = {
+ 0xc2, 0x80, // corner case
+ 0xc2, 0xbf, // corner case
+ 0xdf, 0x80, // corner case
+ 0xdf, 0xbf, // corner case
+ 0xc3, 0xbe, 0xda, 0xbc // misc
+ };
+ run_test(buff, sizeof buff, valid, sizeof valid);
+
+ printf("\n----- Valid characters if m3 == 0 -----\n");
+ // First char is 0xc0 or 0xc1
+ uint8_t valid_if_not_m3[] = {
+ 0xc0, 0x80,
+ 0xc0, 0xbf,
+ 0xc1, 0x80,
+ 0xc0, 0xbf
+ };
+ run_test(buff, sizeof buff, valid_if_not_m3, sizeof valid_if_not_m3);
+
+ // Test for invalid two-byte characters where the 1st byte is valid
+ // The 2nd byte is invalid if not in range 0x80..0xbf, inclusive
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters if m3 == 1 -----\n");
+ uint8_t always_invalid[] = {
+ 0xc2, 0x00,
+ 0xc2, 0x7f,
+ 0xc2, 0xc0,
+ 0xc2, 0xff
+ };
+ for (i = 0; i < sizeof always_invalid; i += 2) {
+ uint8_t invalid_char[2];
+ invalid_char[0] = always_invalid[i];
+ invalid_char[1] = always_invalid[i+1];
+ run_test(buff, sizeof buff, invalid_char, sizeof invalid_char);
+ }
+
+ /* Nb: for a two-byte character we need not test the case where
+ invalidity of the character (cc=2) takes precedence over exhaustion
+ of the 1st operand (cc=1). Invalidity of the character has already
+ been tested when testing the 1st byte. */
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xc3, 0x81, // valid
+ 0xc4, 0x00 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a three-byte character
+void
+convert_3_bytes(void)
+{
+ int i;
+
+ printf("\n===== Conversion of a three-byte character =====\n");
+
+ /* Exhaustively test the 1st byte E0 - EF, and the interval boundaries for
+ the 2nd and 3rd bytes */
+ printf("\n----- Valid characters -----\n");
+ uint8_t e0[] = {
+ 0xe0, 0xa0, 0x80,
+ 0xe0, 0xbf, 0x80,
+ 0xe0, 0xa0, 0xbf,
+ 0xe0, 0xbf, 0xbf,
+ 0xe0, 0xaa, 0xbb, // random e0 .. ..
+ };
+ run_test(buff, sizeof buff, e0, sizeof e0);
+
+ uint8_t ed[] = {
+ 0xed, 0x80, 0x80,
+ 0xed, 0x9f, 0x80,
+ 0xed, 0x80, 0xbf,
+ 0xed, 0x9f, 0xbf,
+ 0xed, 0x8a, 0xbb, // random ed .. ..
+ };
+ run_test(buff, sizeof buff, ed, sizeof ed);
+
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0x80, 0x80 };
+ uint8_t exxx_2[3] = { 0x0, 0xbf, 0x80 };
+ uint8_t exxx_3[3] = { 0x0, 0x80, 0xbf };
+ uint8_t exxx_4[3] = { 0x0, 0xbf, 0xbf };
+
+ if (i == 0x00) continue; // special case e0
+ if (i == 0x0d) continue; // special case ed
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ exxx_3[0] = 0xe0 | i;
+ exxx_4[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ run_test(buff, sizeof buff, exxx_3, sizeof exxx_3);
+ run_test(buff, sizeof buff, exxx_4, sizeof exxx_4);
+ };
+
+ printf("\n----- Invalid characters (2nd byte is invalid) -----\n");
+ // Test for invalid three-byte characters where the 1st byte is valid
+ // The 2nd byte is invalid.
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ e0[0] = 0xe0; // valid
+ e0[1] = 0x9f; // invalid because outside [0xa0 .. 0xbf]
+ e0[2] = 0x80; // valid
+ run_test(buff, sizeof buff, e0, sizeof e0);
+ e0[1] = 0xc0; // invalid because outside [0xa0 .. 0xbf]
+ run_test(buff, sizeof buff, e0, sizeof e0);
+
+ ed[0] = 0xed; // valid
+ ed[1] = 0x7f; // invalid because outside [0x80 .. 0x9f]
+ ed[2] = 0x80; // valid
+ run_test(buff, sizeof buff, ed, sizeof ed);
+ ed[1] = 0xa0; // invalid because outside [0x80 .. 0x9f]
+ run_test(buff, sizeof buff, ed, sizeof ed);
+
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0x7f, 0x80 };
+ uint8_t exxx_2[3] = { 0x0, 0xc0, 0x80 };
+
+ if (i == 0x00) continue; // special case e0
+ if (i == 0x0d) continue; // special case ed
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ };
+
+ printf("\n----- Invalid characters (3rd byte is invalid) -----\n");
+ // For all 1st bytes 0xe0 .. 0xef the 3rd bytes must be in [0x80 .. 0xbf]
+ // No need to special case 0xe0 and 0xed
+ for (i = 0; i <= 0xf; ++i) {
+ uint8_t exxx_1[3] = { 0x0, 0xab, 0x7f };
+ uint8_t exxx_2[3] = { 0x0, 0xab, 0xc0 };
+
+ exxx_1[0] = 0xe0 | i;
+ exxx_2[0] = 0xe0 | i;
+ run_test(buff, sizeof buff, exxx_1, sizeof exxx_1);
+ run_test(buff, sizeof buff, exxx_2, sizeof exxx_2);
+ };
+
+ printf("\n----- Invalid 2nd char AND output exhausted -----\n");
+ /* The character is invalid in its 2nd byte AND the output buffer is
+ exhausted (2 bytes are needed) */
+ uint8_t pat1[] = {
+ 0xe0, 0x00, 0x80
+ };
+ run_test(buff, 1, pat1, 3);
+
+ printf("\n----- Invalid 3rd char AND output exhausted -----\n");
+ /* The character is invalid in its 3rd byte AND the output buffer is
+ exhausted (2 bytes are needed) */
+ uint8_t pat2[] = {
+ 0xe4, 0x84, 0x00
+ };
+ run_test(buff, 1, pat2, 3);
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xe1, 0x90, 0x90, // valid
+ 0xe1, 0x00, 0x90 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+// Test conversion of a four-byte character
+void
+convert_4_bytes(void)
+{
+ int i, j;
+
+ printf("\n===== Conversion of a four-byte character =====\n");
+
+ printf("\n----- Valid characters -----\n");
+ for (i = 0; i <= 4; ++i) {
+ uint8_t valid[4];
+
+ valid[0] = 0xf0 | i;
+
+ for (j = 0; j <= 1; ++j) {
+ // Byte 2
+ if (i == 0) {
+ valid[1] = j == 0 ? 0x90 : 0xbf; // 0xf0
+ } else if (i == 4) {
+ valid[1] = j == 0 ? 0x80 : 0x8f; // 0xf4
+ } else {
+ valid[1] = j == 0 ? 0x80 : 0xbf; // 0xf1 .. 0xf3
+ }
+ // Byte 3 and byte 4 have same interval 0x80 .. 0xbf
+ valid[2] = 0x80;
+ valid[3] = 0x80;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0x80;
+ valid[3] = 0xbf;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0xbf;
+ valid[3] = 0x80;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ valid[2] = 0xbf;
+ valid[3] = 0xbf;
+ run_test(buff, sizeof buff, valid, sizeof valid);
+ }
+ }
+
+ printf("\n----- Valid characters if m3 == 0 -----\n");
+ // First char is 0xf5 .. 0xf7
+ uint8_t valid_if_not_m3[] = {
+ 0xf5, 0x00, 0x00, 0x00,
+ 0xf6, 0x11, 0x22, 0x33,
+ 0xf7, 0x44, 0x55, 0x66,
+ };
+ run_test(buff, sizeof buff, valid_if_not_m3, sizeof valid_if_not_m3);
+
+ // As conversion stops upon encountering an invalid character, we
+ // need to test each invalid character separately, to make sure it
+ // is recognized as invalid.
+
+ printf("\n----- Invalid characters (2nd byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 2nd byte is invalid.
+ // All other bytes are valid
+ uint8_t f0[4], f4[4];
+
+ f0[0] = 0xf0; // valid
+ f0[1] = 0x8f; // invalid because outside [0x90 .. 0xbf]
+ f0[2] = 0x80; // valid
+ f0[3] = 0x80; // valid
+ run_test(buff, sizeof buff, f0, sizeof f0);
+ f0[1] = 0xc0; // invalid because outside [0x90 .. 0xbf]
+ run_test(buff, sizeof buff, f0, sizeof f0);
+
+ f4[0] = 0xf4; // valid
+ f4[1] = 0x7f; // invalid because outside [0x80 .. 0x8f]
+ f4[2] = 0x80; // valid
+ f4[3] = 0x80; // valid
+ run_test(buff, sizeof buff, f4, sizeof f4);
+ f4[1] = 0x90; // invalid because outside [0x80 .. 0x9f]
+ run_test(buff, sizeof buff, f4, sizeof f4);
+
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx_1[4] = { 0x0, 0x7f, 0x80, 0x80 };
+ uint8_t fxxx_2[4] = { 0x0, 0xc0, 0x80, 0x80 };
+
+ if (i == 0) continue; // special case f0
+ if (i == 4) continue; // special case f4
+
+ fxxx_1[0] = 0xf0 | i;
+ fxxx_2[0] = 0xf0 | i;
+ run_test(buff, sizeof buff, fxxx_1, sizeof fxxx_1);
+ run_test(buff, sizeof buff, fxxx_2, sizeof fxxx_2);
+ };
+
+ printf("\n----- Invalid characters (3rd byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 3rd byte is invalid.
+ // All other bytes are valid
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx[4] = { 0x0, 0x0, 0x0, 0x80 };
+
+ fxxx[0] = 0xf0 | i;
+ fxxx[1] = (i == 0) ? 0x94 : 0x84;
+ fxxx[2] = 0x7f;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ fxxx[2] = 0xc0;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ };
+
+ printf("\n----- Invalid characters (4th byte is invalid) -----\n");
+ // Test for invalid four-byte characters where the 3rd byte is invalid.
+ // All other bytes are valid
+ for (i = 0; i <= 0x4; ++i) {
+ uint8_t fxxx[4] = { 0x0, 0x0, 0x80, 0x0 };
+
+ fxxx[0] = 0xf0 | i;
+ fxxx[1] = (i == 0) ? 0x94 : 0x84;
+ fxxx[3] = 0x7f;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ fxxx[3] = 0xc0;
+ run_test(buff, sizeof buff, fxxx, sizeof fxxx);
+ };
+
+ printf("\n----- Invalid 2nd char AND output exhausted -----\n");
+ /* The character is invalid in its 2nd byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat1[] = {
+ 0xf0, 0x00, 0x80, 0x80
+ };
+ run_test(buff, 1, pat1, 4);
+
+ printf("\n----- Invalid 3rd char AND output exhausted -----\n");
+ /* The character is invalid in its 3rd byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat2[] = {
+ 0xf0, 0xaa, 0x00, 0x80
+ };
+ run_test(buff, 3, pat2, 4);
+
+ printf("\n----- Invalid 4th char AND output exhausted -----\n");
+ /* The character is invalid in its 4th byte AND the output buffer is
+ exhausted (4 bytes are needed) */
+ uint8_t pat3[] = {
+ 0xf0, 0xaa, 0xaa, 0x00
+ };
+ run_test(buff, 3, pat3, 4);
+
+ printf("\n----- 1st char valid, 2nd char invalid -----\n");
+ uint8_t valid_invalid[] = {
+ 0xf0, 0xaa, 0xaa, 0xaa, // valid
+ 0xf0, 0x00, 0x00, 0x00 // invalid
+ };
+ run_test(buff, sizeof buff, valid_invalid, sizeof valid_invalid);
+}
+
+
+int main()
+{
+ convert_1_byte();
+ convert_2_bytes();
+ convert_3_bytes();
+ convert_4_bytes();
+
+ /* Length == 0, no memory should be read or written */
+ printf("\n------------- test1 ----------------\n");
+ run_test(NULL, 0, NULL, 0);
+
+ /* Test exhaustion of source length (source bytes are valid) */
+ printf("\n------------- test2.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+ run_test(buff, sizeof buff, NULL, 0);
+ run_test(buff, sizeof buff, pattern1, 0);
+ run_test(buff, sizeof buff, pattern2, 0);
+ run_test(buff, sizeof buff, pattern2, 1);
+ run_test(buff, sizeof buff, pattern3, 0);
+ run_test(buff, sizeof buff, pattern3, 1);
+ run_test(buff, sizeof buff, pattern3, 2);
+ run_test(buff, sizeof buff, pattern4, 0);
+ run_test(buff, sizeof buff, pattern4, 1);
+ run_test(buff, sizeof buff, pattern4, 2);
+ run_test(buff, sizeof buff, pattern4, 3);
+
+ printf("\n------------- test2.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, sizeof buff, pattern1, 2);
+ run_test(buff, sizeof buff, pattern2, 5);
+ run_test(buff, sizeof buff, pattern3, 6);
+ run_test(buff, sizeof buff, pattern4, 9);
+
+ /* Test exhaustion of destination length (source bytes are valid) */
+ printf("\n------------- test3.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+
+ /* Want to write 2 or 4 bytes at a time */
+ run_test(NULL, 0, pattern1, sizeof pattern1); // 2-byte result
+ run_test(NULL, 0, pattern2, sizeof pattern2); // 2-byte result
+ run_test(NULL, 1, pattern2, sizeof pattern2); // 2-byte result
+ run_test(NULL, 0, pattern3, sizeof pattern3); // 2-byte result
+ run_test(NULL, 1, pattern3, sizeof pattern3); // 2-byte result
+ run_test(NULL, 0, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 1, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 2, pattern4, sizeof pattern4); // 4-byte result
+ run_test(NULL, 3, pattern4, sizeof pattern4); // 4-byte result
+
+ printf("\n------------- test3.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, 4, pattern1, sizeof pattern1);
+ run_test(buff, 5, pattern1, sizeof pattern2);
+ run_test(buff, 6, pattern1, sizeof pattern3);
+ run_test(buff, 7, pattern1, sizeof pattern4);
+
+ /* Convert buffer with mixed characters */
+ printf("\n------------- test4 ----------------\n");
+ run_test(buff, sizeof buff, mixed, sizeof mixed);
+
+ return 0;
+}
diff --git a/none/tests/s390x/cu21_1.c b/none/tests/s390x/cu21_1.c
deleted file mode 120000
index d919a51..0000000
--- a/none/tests/s390x/cu21_1.c
+++ /dev/null
@@ -1 +0,0 @@
-cu21.c
\ No newline at end of file
diff --git a/none/tests/s390x/cu21_1.c b/none/tests/s390x/cu21_1.c
new file mode 100644
index 0000000..d2d1f11
--- /dev/null
+++ b/none/tests/s390x/cu21_1.c
@@ -0,0 +1,270 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "opcodes.h"
+
+#ifndef M3
+#define M3 0
+#endif
+
+/* The abstracted result of an CU21 insn */
+typedef struct {
+ uint64_t addr1; // target
+ uint64_t len1;
+ uint64_t addr2; // source
+ uint64_t len2;
+ uint32_t cc;
+} cu21_t;
+
+/* Define various input buffers. */
+
+/* U+0000 to U+007f: Result is 1 byte for each uint16_t */
+uint16_t pattern1[] = {
+ 0x0000, 0x007f, /* corner cases */
+ 0x0047, 0x0056, 0x0045, 0x0021, 0x007b, 0x003a /* misc */
+};
+
+/* U+0080 to U+07ff: Result is 2 bytes for each uint16_t */
+uint16_t pattern2[] = {
+ 0x0080, 0x07ff, /* corner cases */
+ 0x07df, 0x008f, 0x0100, 0x017f, 0x052f, 0x0600, 0x06ff /* misc */
+};
+
+/* U+0800 to U+d7ff: Result is 3 bytes for each uint16_t
+ U+dc00 to U+ffff: Result is 3 bytes for each uint16_t */
+uint16_t pattern3[] = {
+ 0x0800, 0xd7ff, /* corner cases */
+ 0xdc00, 0xffff, /* corner cases */
+ 0x083f, 0x1a21, 0x1b10, 0x2200, 0x225e, 0x22c9, 0xe001 /* misc */
+};
+
+/* U+d800 to U+dbff: Result is 4 bytes for each uint16_t pair */
+uint16_t pattern4[] = {
+ 0xd800, 0xdc00, /* left corner case */
+ 0xdbff, 0xdfff, /* right corner case */
+ 0xdada, 0xdddd, 0xdeaf, 0xdcdc /* misc */
+};
+
+/* Invalid low surrogate */
+uint16_t invalid[] = { 0xd801, 0x0098 };
+
+/* Mixed bytes */
+uint16_t mixed[] = {
+ 0x0078 /* 1 byte */,
+ 0x0200 /* 2 bytes */,
+ 0xffff /* 3 bytes */,
+ 0xd800, 0xdc01 /* 4 bytes */
+};
+
+/* This is the buffer for the converted bytes. */
+uint8_t buff[1000]; /* Large so we con'don't have to worry about it */
+
+void write_and_check(uint16_t *, unsigned, unsigned);
+
+
+static cu21_t
+do_cu21(uint8_t *dst, uint64_t dst_len, uint16_t *src, uint64_t src_len)
+{
+ int cc = 42;
+ cu21_t regs;
+
+ /* build up the register pairs */
+ register uint16_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint8_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU21(M3,2,4)
+ "ipm %2\n\t"
+ "srl %2,28\n\t"
+ : "+d"(dest), "+d"(source), "=d"(cc),
+ "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+
+ /* Capture register contents at end of cu21 */
+ regs.addr1 = (uint64_t)dest;
+ regs.len1 = dest_len;
+ regs.addr2 = (uint64_t)source;
+ regs.len2 = source_len;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void
+run_test(uint8_t *dst, uint64_t dst_len, uint16_t *src, uint64_t src_len)
+{
+ int i;
+ cu21_t result;
+
+ result = do_cu21(dst, dst_len, src, src_len);
+
+ // Write out the converted bytes, if any
+ printf("UTF8: ");
+ if (dst_len - result.len1 == 0)
+ printf(" <none>");
+ else
+ for (i = 0; i < dst_len - result.len1; i++) {
+ printf(" %02x", dst[i]);
+ }
+ printf("\n");
+
+ printf(" cc = %d\n", result.cc);
+ if (dst != NULL)
+ printf(" dst address difference: %"PRId64, result.addr1 - (uint64_t)dst);
+ printf(" dst len: %"PRId64"\n", result.len1);
+
+ if (src != NULL)
+ printf(" src address difference: %"PRId64, result.addr2 - (uint64_t)src);
+ printf(" src len: %"PRId64"\n", result.len2);
+}
+
+int main()
+{
+ /* Length == 0, no memory should be read or written */
+ printf("\n------------- test1 ----------------\n");
+ run_test(NULL, 0, NULL, 0);
+
+ /* Test exhaustion of source length (source bytes are valid) */
+ printf("\n------------- test2.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+ run_test(buff, sizeof buff, NULL, 1);
+ run_test(buff, sizeof buff, pattern1, 1);
+ run_test(buff, sizeof buff, pattern2, 1);
+ run_test(buff, sizeof buff, pattern3, 1);
+ run_test(buff, sizeof buff, pattern4, 1);
+ run_test(buff, sizeof buff, pattern4, 2);
+ run_test(buff, sizeof buff, pattern4, 3);
+
+ printf("\n------------- test2.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, sizeof buff, pattern1, 3);
+ run_test(buff, sizeof buff, pattern2, 5);
+ run_test(buff, sizeof buff, pattern3, 7);
+ run_test(buff, sizeof buff, pattern4, 9);
+ run_test(buff, sizeof buff, pattern4, 10);
+ run_test(buff, sizeof buff, pattern4, 11);
+
+ /* Test exhaustion of destination length (source bytes are valid) */
+ printf("\n------------- test3.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+
+ /* Want to write a single byte */
+ run_test(NULL, 0, pattern1, sizeof pattern1);
+
+ /* Want to write two bytes */
+ run_test(NULL, 0, pattern2, sizeof pattern2);
+ run_test(NULL, 1, pattern2, sizeof pattern2);
+
+ /* Want to write three bytes */
+ run_test(NULL, 0, pattern3, sizeof pattern3);
+ run_test(NULL, 1, pattern3, sizeof pattern3);
+ run_test(NULL, 2, pattern3, sizeof pattern3);
+
+ /* Want to write four bytes */
+ run_test(NULL, 0, pattern4, sizeof pattern4);
+ run_test(NULL, 1, pattern4, sizeof pattern4);
+ run_test(NULL, 2, pattern4, sizeof pattern4);
+ run_test(NULL, 3, pattern4, sizeof pattern4);
+
+ printf("\n------------- test3.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, 3, pattern1, sizeof pattern1);
+
+ run_test(buff, 5, pattern2, sizeof pattern2);
+
+ run_test(buff, 7, pattern3, sizeof pattern3);
+ run_test(buff, 8, pattern3, sizeof pattern3);
+
+ run_test(buff, 9, pattern4, sizeof pattern4);
+ run_test(buff, 10, pattern4, sizeof pattern4);
+ run_test(buff, 11, pattern4, sizeof pattern4);
+
+ /* When both operands are exhausted, cc=0 takes precedence.
+ (test1 tests this for len == 0) */
+ printf("\n------------- test4 ----------------\n");
+ run_test(buff, 6, pattern1, 6);
+
+ /* Input has invalid low surrogate. */
+ printf("\n------------- test5 ----------------\n");
+ run_test(buff, sizeof buff, invalid, sizeof invalid);
+ run_test(buff, 0, invalid, sizeof invalid);
+
+ /* Convert all pattern buffers */
+ printf("\n------------- test6 ----------------\n");
+ run_test(buff, sizeof buff, pattern1, sizeof pattern1);
+ run_test(buff, sizeof buff, pattern2, sizeof pattern2);
+ run_test(buff, sizeof buff, pattern3, sizeof pattern3);
+ run_test(buff, sizeof buff, pattern4, sizeof pattern4);
+ run_test(buff, sizeof buff, mixed, sizeof mixed);
+
+ /* Make sure we only write the exact number of bytes (and not more) */
+ uint16_t pat[2];
+
+ /* Write 1 byte */
+ printf("\n------------- test7.1 ----------------\n");
+ pat[0] = 0x10;
+ write_and_check(pat, 2, 1);
+
+ /* Write 2 bytes */
+ printf("\n------------- test7.2 ----------------\n");
+ pat[0] = 0x8f;
+ write_and_check(pat, 2, 2);
+
+ /* Write 3 bytes */
+ printf("\n------------- test7.3 ----------------\n");
+ pat[0] = 0x842;
+ write_and_check(pat, 2, 3);
+
+ /* Write 4 bytes */
+ printf("\n------------- test7.4 ----------------\n");
+ pat[0] = 0xd842;
+ pat[1] = 0xdc42;
+ write_and_check(pat, 2, 4);
+
+ return 0;
+}
+
+
+void
+write_and_check_aux(uint16_t *input, unsigned num_input_bytes,
+ unsigned num_expected_output_bytes,
+ unsigned fill_byte)
+{
+ int num_errors, i;
+
+ /* Fill output buffer with FILL_BYTE */
+ memset(buff, fill_byte, sizeof buff);
+
+ /* Execute cu21 */
+ run_test(buff, sizeof buff, input, num_input_bytes);
+
+ /* Make sure the rest of the buffer is unmodified. */
+ num_errors = 0;
+ for (i = num_expected_output_bytes; i < sizeof buff; ++i)
+ if (buff[i] != fill_byte) ++num_errors;
+ if (num_errors)
+ fprintf(stderr, "*** wrote more than %u bytes\n",
+ num_expected_output_bytes);
+}
+
+void
+write_and_check(uint16_t *input, unsigned num_input_bytes,
+ unsigned num_expected_output_bytes)
+{
+ write_and_check_aux(input, num_input_bytes, num_expected_output_bytes, 0x0);
+
+ /* Run again with different fill pattern to make sure we did not write
+ an extra 0x0 byte */
+ write_and_check_aux(input, num_input_bytes, num_expected_output_bytes, 0xFF);
+}
diff --git a/none/tests/s390x/cu24_1.c b/none/tests/s390x/cu24_1.c
deleted file mode 120000
index 85676fa..0000000
--- a/none/tests/s390x/cu24_1.c
+++ /dev/null
@@ -1 +0,0 @@
-cu24.c
\ No newline at end of file
diff --git a/none/tests/s390x/cu24_1.c b/none/tests/s390x/cu24_1.c
new file mode 100644
index 0000000..2cd8828
--- /dev/null
+++ b/none/tests/s390x/cu24_1.c
@@ -0,0 +1,183 @@
+#include <stdint.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include "opcodes.h"
+
+#ifndef M3
+#define M3 0
+#endif
+
+/* The abstracted result of an CU24 insn */
+typedef struct {
+ uint64_t addr1; // target
+ uint64_t len1;
+ uint64_t addr2; // source
+ uint64_t len2;
+ uint32_t cc;
+} cu24_t;
+
+/* Define various input buffers. */
+
+/* Single UTF-16 value */
+uint16_t pattern1[] = {
+ 0x0000, 0xd7ff, /* [0000 ... d7ff] corner cases */
+ 0xdc00, 0xffff, /* [dc00 ... ffff] corner cases */
+ 0x0047, 0x0156, 0x1245, 0xa021, 0xfffe /* misc */
+};
+
+/* UTF-16 surrogate pair */
+uint16_t pattern2[] = {
+ 0xd800, 0xdc00, /* left corner case */
+ 0xdbff, 0xdfff, /* right corner case */
+ 0xdada, 0xdddd, 0xdeaf, 0xdcdc /* misc */
+};
+
+/* Invalid low surrogate */
+uint16_t invalid[] = { 0xd801, 0x0098 };
+
+/* Mixed bytes */
+uint16_t mixed[] = {
+ 0x0078,
+ 0x0200,
+ 0xffff,
+ 0xd800, 0xdc01,
+ 0xde00, 0xdd00,
+ 0xc0c0
+};
+
+/* This is the buffer for the converted bytes. */
+uint32_t buff[1000]; /* Large so we con'don't have to worry about it */
+
+
+static cu24_t
+do_cu24(uint32_t *dst, uint64_t dst_len, uint16_t *src, uint64_t src_len)
+{
+ int cc = 42;
+ cu24_t regs;
+
+ /* build up the register pairs */
+ register uint16_t *source asm("4") = src;
+ register uint64_t source_len asm("5") = src_len;
+ register uint32_t *dest asm("2") = dst;
+ register uint64_t dest_len asm("3") = dst_len;
+
+ asm volatile(
+ CU24(M3,2,4)
+ "ipm %2\n\t"
+ "srl %2,28\n\t"
+ : "+d"(dest), "+d"(source), "=d"(cc),
+ "+d"(source_len), "+d"(dest_len)
+ :
+ : "memory", "cc");
+
+ /* Capture register contents at end of cu24 */
+ regs.addr1 = (uint64_t)dest;
+ regs.len1 = dest_len;
+ regs.addr2 = (uint64_t)source;
+ regs.len2 = source_len;
+ regs.cc = cc;
+
+ return regs;
+}
+
+void
+run_test(uint32_t *dst, uint64_t dst_len, uint16_t *src, uint64_t src_len)
+{
+ int i;
+ cu24_t result;
+
+ result = do_cu24(dst, dst_len, src, src_len);
+
+ // Write out the converted byte, if any
+ printf("UTF32: ");
+ if (dst_len - result.len1 == 0)
+ printf(" <none>");
+ else {
+ uint64_t num_bytes = dst_len - result.len1;
+
+ /* The number of bytes that were written must be divisible by 4 */
+ if (num_bytes % 4 != 0)
+ fprintf(stderr, "*** number of bytes is not a multiple of 4\n");
+
+ for (i = 0; i < num_bytes / 4; i++) {
+ printf(" %02x", dst[i]);
+ }
+ }
+ printf("\n");
+
+ printf(" cc = %d\n", result.cc);
+ if (dst != NULL)
+ printf(" dst address difference: %"PRId64, result.addr1 - (uint64_t)dst);
+ printf(" dst len: %"PRId64"\n", result.len1);
+
+ if (src != NULL)
+ printf(" src address difference: %"PRId64, result.addr2 - (uint64_t)src);
+ printf(" src len: %"PRId64"\n", result.len2);
+}
+
+int main()
+{
+ /* Length == 0, no memory should be read or written */
+ printf("\n------------- test1 ----------------\n");
+ run_test(NULL, 0, NULL, 0);
+
+ /* Test exhaustion of source length (source bytes are valid) */
+ printf("\n------------- test2.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+ run_test(buff, sizeof buff, NULL, 1);
+ run_test(buff, sizeof buff, pattern1, 1);
+ run_test(buff, sizeof buff, pattern2, 1);
+ run_test(buff, sizeof buff, pattern2, 2);
+ run_test(buff, sizeof buff, pattern2, 3);
+
+ printf("\n------------- test2.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, sizeof buff, pattern1, 3);
+ run_test(buff, sizeof buff, pattern1, 5);
+ run_test(buff, sizeof buff, pattern2, 2);
+ run_test(buff, sizeof buff, pattern2, 5);
+ run_test(buff, sizeof buff, pattern2, 7);
+
+ /* Test exhaustion of destination length (source bytes are valid) */
+ printf("\n------------- test3.1 ----------------\n");
+
+ /* No character will be written to BUFF, i.e. loop in jitted code
+ is not iterated */
+
+ /* Want to write 4 bytes at a time */
+ run_test(NULL, 0, pattern1, sizeof pattern1);
+ run_test(NULL, 1, pattern1, sizeof pattern1);
+ run_test(NULL, 2, pattern1, sizeof pattern1);
+ run_test(NULL, 3, pattern1, sizeof pattern1);
+
+ printf("\n------------- test3.2 ----------------\n");
+ /* At least one character will be written to BUFF, i.e. loop in jitted
+ code is iterated */
+ run_test(buff, 4, pattern1, sizeof pattern1);
+ run_test(buff, 5, pattern1, sizeof pattern1);
+ run_test(buff, 6, pattern1, sizeof pattern1);
+ run_test(buff, 7, pattern1, sizeof pattern1);
+
+ /* When both operands are exhausted, cc=0 takes precedence.
+ (test1 tests this for len == 0) */
+ printf("\n------------- test4 ----------------\n");
+ run_test(buff, 4, pattern1, 2); // no iteration
+ run_test(buff, 8, pattern1, 4); // iteration
+
+ /* Input has invalid low surrogate. */
+ printf("\n------------- test5 ----------------\n");
+ run_test(buff, sizeof buff, invalid, sizeof invalid);
+ run_test(buff, 0, invalid, sizeof invalid);
+
+ /* Convert all pattern buffers */
+ printf("\n------------- test6 ----------------\n");
+ run_test(buff, sizeof buff, pattern1, sizeof pattern1);
+ run_test(buff, sizeof buff, pattern2, sizeof pattern2);
+
+ return 0;
+}
diff --git a/none/tests/s390x/high-word.c b/none/tests/s390x/high-word.c
new file mode 100644
index 0000000..3328aaf
--- /dev/null
+++ b/none/tests/s390x/high-word.c
@@ -0,0 +1,84 @@
+#include <stdio.h>
+#include <stdint.h>
+#include "opcodes.h"
+
+#define BRASLCLOBBER "0","1","2","3","4","5","14", \
+ "f0","f1","f2","f3","f4","f5","f6","f7","memory","cc"
+
+void inner_iter() { putchar('.'); }
+void outer_iter() { putchar('+'); }
+
+static void
+check_brcth(int m, int n)
+{
+ unsigned long cnt = ((unsigned long) m << 32) | n;
+
+ printf("brcth %d x %d (cnt=0x%lx): ", m, n, cnt);
+ fflush(stdout);
+ asm volatile("1: lr %[cnt],%[n]\n\t"
+ "2: brasl 14,inner_iter\n\t"
+ "brct %[cnt],2b\n\t"
+ "brasl 14,outer_iter\n\t"
+ ".insn ril,0xcc0600000000,%[cnt],1b\n\t" // BRCTH
+ : [cnt]"+r" (cnt)
+ : [n]"r" (n)
+ : BRASLCLOBBER);
+ printf(" (cnt=0x%lx)\n", cnt);
+}
+
+#define DO_RISBXG(insn, _r1, _r2, i3, i4, i5) \
+ ({ \
+ register unsigned long r1 asm ("1") = _r1; \
+ register unsigned long r2 asm ("2") = _r2; \
+ asm volatile(insn(1,2, i3, i4, i5) \
+ : "+d" (r1) \
+ : "d" (r1), "d" (r2)); \
+ printf(#insn " r1(==%16.16lx),r2(==%16.16lx),0x" #i3 ",0x" #i4 \
+ ",0x" #i5 " = %16.16lx\n", _r1, _r2, r1); \
+ })
+
+/* Some "random" 64-bit numbers. */
+
+#define VAL_A 0x3a41e0a2afde1559
+#define VAL_B 0x765487c11cd04ac4
+#define VAL_C 0xb9cd1bdd399bef32
+#define VAL_D 0xf8efadb884334ddd
+
+static void
+check_risbxg(void)
+{
+ /* Full copy low -> low */
+ DO_RISBXG(RISBLG, VAL_A, VAL_B, 00, 1f, 00);
+ DO_RISBXG(RISBLG, VAL_B, VAL_A, 00, 9f, 00);
+ /* Full copy high -> low */
+ DO_RISBXG(RISBLG, VAL_B, VAL_A, 00, 1f, 20);
+ DO_RISBXG(RISBLG, VAL_A, VAL_B, 00, 9f, 20);
+ /* Full copy high -> high */
+ DO_RISBXG(RISBHG, VAL_C, VAL_D, 00, 1f, 00);
+ DO_RISBXG(RISBHG, VAL_D, VAL_C, 00, 9f, 00);
+ /* Full copy low -> high */
+ DO_RISBXG(RISBHG, VAL_D, VAL_C, 00, 1f, 20);
+ DO_RISBXG(RISBHG, VAL_C, VAL_D, 00, 9f, 20);
+ /* Middle copy */
+ DO_RISBXG(RISBLG, VAL_C, VAL_A, 0b, 13, 05);
+ DO_RISBXG(RISBLG, VAL_C, VAL_A, 0b, 93, 05);
+ DO_RISBXG(RISBHG, VAL_A, VAL_C, 03, 0c, 25);
+ DO_RISBXG(RISBHG, VAL_A, VAL_C, 03, 8c, 25);
+ /* "Outer" copy (start > end) */
+ DO_RISBXG(RISBLG, VAL_B, VAL_D, 1d, 07, 0c);
+ DO_RISBXG(RISBLG, VAL_B, VAL_D, 1d, 87, 0c);
+ DO_RISBXG(RISBHG, VAL_D, VAL_B, 0c, 03, 25);
+ DO_RISBXG(RISBHG, VAL_D, VAL_B, 0c, 83, 25);
+}
+
+/* Test high-word facility instructions. */
+
+int main()
+{
+ check_brcth(5, 3);
+ check_brcth(1, 30);
+ check_brcth(16, 1);
+
+ check_risbxg();
+ return 0;
+}
diff --git a/none/tests/s390x/high-word.stderr.exp b/none/tests/s390x/high-word.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/s390x/high-word.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/s390x/high-word.stdout.exp b/none/tests/s390x/high-word.stdout.exp
new file mode 100644
index 0000000..3ce7c84
--- /dev/null
+++ b/none/tests/s390x/high-word.stdout.exp
@@ -0,0 +1,19 @@
+brcth 5 x 3 (cnt=0x500000003): ...+...+...+...+...+ (cnt=0x0)
+brcth 1 x 30 (cnt=0x10000001e): ..............................+ (cnt=0x0)
+brcth 16 x 1 (cnt=0x1000000001): .+.+.+.+.+.+.+.+.+.+.+.+.+.+.+.+ (cnt=0x0)
+RISBLG r1(==3a41e0a2afde1559),r2(==765487c11cd04ac4),0x00,0x1f,0x00 = 3a41e0a21cd04ac4
+RISBLG r1(==765487c11cd04ac4),r2(==3a41e0a2afde1559),0x00,0x9f,0x00 = 765487c1afde1559
+RISBLG r1(==765487c11cd04ac4),r2(==3a41e0a2afde1559),0x00,0x1f,0x20 = 765487c13a41e0a2
+RISBLG r1(==3a41e0a2afde1559),r2(==765487c11cd04ac4),0x00,0x9f,0x20 = 3a41e0a2765487c1
+RISBHG r1(==b9cd1bdd399bef32),r2(==f8efadb884334ddd),0x00,0x1f,0x00 = f8efadb8399bef32
+RISBHG r1(==f8efadb884334ddd),r2(==b9cd1bdd399bef32),0x00,0x9f,0x00 = b9cd1bdd84334ddd
+RISBHG r1(==f8efadb884334ddd),r2(==b9cd1bdd399bef32),0x00,0x1f,0x20 = 399bef3284334ddd
+RISBHG r1(==b9cd1bdd399bef32),r2(==f8efadb884334ddd),0x00,0x9f,0x20 = 84334ddd399bef32
+RISBLG r1(==b9cd1bdd399bef32),r2(==3a41e0a2afde1559),0x0b,0x13,0x05 = b9cd1bdd3982af32
+RISBLG r1(==b9cd1bdd399bef32),r2(==3a41e0a2afde1559),0x0b,0x93,0x05 = b9cd1bdd0002a000
+RISBHG r1(==3a41e0a2afde1559),r2(==b9cd1bdd399bef32),0x03,0x0c,0x25 = 3379e0a2afde1559
+RISBHG r1(==3a41e0a2afde1559),r2(==b9cd1bdd399bef32),0x03,0x8c,0x25 = 13780000afde1559
+RISBLG r1(==765487c11cd04ac4),r2(==f8efadb884334ddd),0x1d,0x07,0x0c = 765487c134d04ac6
+RISBLG r1(==765487c11cd04ac4),r2(==f8efadb884334ddd),0x1d,0x87,0x0c = 765487c134000006
+RISBHG r1(==f8efadb884334ddd),r2(==765487c11cd04ac4),0x0c,0x03,0x25 = 98e9588e84334ddd
+RISBHG r1(==f8efadb884334ddd),r2(==765487c11cd04ac4),0x0c,0x83,0x25 = 9009588e84334ddd
diff --git a/none/tests/s390x/high-word.vgtest b/none/tests/s390x/high-word.vgtest
new file mode 100644
index 0000000..7c42937
--- /dev/null
+++ b/none/tests/s390x/high-word.vgtest
@@ -0,0 +1,2 @@
+prog: high-word
+prereq: ../../../tests/s390x_features 's390x-highw'
diff --git a/none/tests/s390x/mvc.c b/none/tests/s390x/mvc.c
index 3d5c496..636234b 100644
--- a/none/tests/s390x/mvc.c
+++ b/none/tests/s390x/mvc.c
@@ -57,6 +57,13 @@
asm volatile( "mvc 0(5,%0),10(%1)\n"
::"a" (buf),"a" (buf): "memory");
printf("after: buf = |%s|\n", buf);
-
+ printf("\n");
+
+ /* Move inverse (mvcin) */
+ printf("------- Move inverse 17 bytes from BUFFER to TARGET\n");
+ printf("before: target = |%s|\n", target);
+ asm volatile( "mvcin 0(17,%0),0(%1)\n"
+ ::"a" (target),"a" (buffer + 16): "memory");
+ printf("after: target = |%s|\n", target);
return 0;
}
diff --git a/none/tests/s390x/mvc.stdout.exp b/none/tests/s390x/mvc.stdout.exp
index 7ad5cc0..e4f3b2d 100644
--- a/none/tests/s390x/mvc.stdout.exp
+++ b/none/tests/s390x/mvc.stdout.exp
@@ -15,3 +15,7 @@
------- Non-destructive overlap buf[0:4] = buf[10:14]
before: buf = |0123456789abcde|
after: buf = |abcde56789abcde|
+
+------- Move inverse 17 bytes from BUFFER to TARGET
+before: target = |-xxx-----------------|
+after: target = |Xfedcba9876543210----|
diff --git a/none/tests/s390x/opcodes.h b/none/tests/s390x/opcodes.h
index f8a55e2..d91a4d7 100644
--- a/none/tests/s390x/opcodes.h
+++ b/none/tests/s390x/opcodes.h
@@ -324,10 +324,14 @@
#define OY(r1,x2,b2,dl2,dh2) RXY_RRRD(e3,r1,x2,b2,dl2,dh2,56)
#define PFD(r1,x2,b2,dl2,dh2) RXY_URRD(e3,r1,x2,b2,dl2,dh2,36)
#define PFDRL(r1,i2) RIL_UP(c6,r1,2,i2)
+#define POPCNT(r1,r2) RRE_RR(b9e1,00,r1,r2)
#define RISBG(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,55)
#define RNSBG(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,54)
#define ROSBG(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,56)
#define RXSBG(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,57)
+#define RISBGN(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,59)
+#define RISBHG(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,5d)
+#define RISBLG(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,51)
#define SFPC(r1) RRE_R0(b384,r1)
#define SGRK(r3,r1,r2) RRF_R0RR2(b9e9,r3,0,r1,r2)
#define SHHHR(r3,r1,r2) RRF_R0RR2(b9c9,r3,0,r1,r2)
diff --git a/none/tests/s390x/popcnt.c b/none/tests/s390x/popcnt.c
new file mode 100644
index 0000000..d9bc466
--- /dev/null
+++ b/none/tests/s390x/popcnt.c
@@ -0,0 +1,30 @@
+#include <stdio.h>
+#include <stdint.h>
+
+
+static void check_popcnt(uint64_t in, uint64_t expected_result,
+ int expected_cc)
+{
+ uint64_t out = ~expected_result;
+ int cc = ~expected_cc;
+
+ asm volatile(".insn rre, 0xb9e10000, %[out], %[in]\n\t"
+ "ipm %[cc]\n\t"
+ "srl %[cc],28\n\t"
+ : [cc]"=d" (cc), [out]"=d" (out)
+ : [in]"d" (in)
+ : "cc");
+ printf("popcnt %16lx -> %16lx %s cc=%d %s\n",
+ in, out, (out == expected_result ? " " : "ERR"),
+ cc, (cc == expected_cc ? " " : "ERR"));
+}
+
+int main()
+{
+ check_popcnt(0, 0, 0);
+ check_popcnt(1, 1, 1);
+ check_popcnt(0x8000000000000000ULL, 0x0100000000000000ULL, 1);
+ check_popcnt(0xffffffffffffffffULL, 0x0808080808080808ULL, 1);
+ check_popcnt(0xff427e3800556bcdULL, 0x0802060300040505ULL, 1);
+ return 0;
+}
diff --git a/none/tests/s390x/popcnt.stderr.exp b/none/tests/s390x/popcnt.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/s390x/popcnt.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/s390x/popcnt.stdout.exp b/none/tests/s390x/popcnt.stdout.exp
new file mode 100644
index 0000000..0bb7afe
--- /dev/null
+++ b/none/tests/s390x/popcnt.stdout.exp
@@ -0,0 +1,5 @@
+popcnt 0 -> 0 cc=0
+popcnt 1 -> 1 cc=1
+popcnt 8000000000000000 -> 100000000000000 cc=1
+popcnt ffffffffffffffff -> 808080808080808 cc=1
+popcnt ff427e3800556bcd -> 802060300040505 cc=1
diff --git a/none/tests/s390x/popcnt.vgtest b/none/tests/s390x/popcnt.vgtest
new file mode 100644
index 0000000..78ad704
--- /dev/null
+++ b/none/tests/s390x/popcnt.vgtest
@@ -0,0 +1 @@
+prog: popcnt
diff --git a/none/tests/s390x/rxsbg.c b/none/tests/s390x/rxsbg.c
index 6e15325..f6ab4cd 100644
--- a/none/tests/s390x/rxsbg.c
+++ b/none/tests/s390x/rxsbg.c
@@ -6,11 +6,12 @@
register unsigned long r1 asm ("1") = _r1; \
register unsigned long r2 asm ("2") = _r2; \
int cc; \
- asm volatile( insn(1,2, i3, i4, i5) \
+ asm volatile( "clgr 1,2\n" \
+ insn(1,2, i3, i4, i5) \
"ipm %1\n" \
"srl %1,28\n" \
: "+d" (r1), "=d" (cc) \
- : "d" (r1), "d" (r2) \
+ : "d" (r1), "d" (r2) \
: "cc"); \
printf(#insn " r1(==%16.16lX),r2(==%16.16lX),0x" #i3 ",0x" #i4 ",0x" #i5 " = %16.16lX (cc=%d)\n", _r1, _r2, r1, cc); \
})
@@ -73,6 +74,7 @@
i5sweep(RNSBG);
i5sweep(ROSBG);
i5sweep(RXSBG);
+ i5sweep(RISBGN);
return 0;
}
diff --git a/none/tests/s390x/rxsbg.stdout.exp b/none/tests/s390x/rxsbg.stdout.exp
index 9f1d918..4bab353 100644
--- a/none/tests/s390x/rxsbg.stdout.exp
+++ b/none/tests/s390x/rxsbg.stdout.exp
@@ -6478,3 +6478,1623 @@
RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = 0000000000000000 (cc=1)
RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1)
RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 8000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x00 = 0000F00000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x00 = 7FFFF00000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = 00000CCCFFFF0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = 0000FCCCFFFF0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = 7FFFFCCCFFFF0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = 8000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x00 = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = 8000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = 8000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x00 = 0000FFFF80000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x00 = 7FFFFFFF80000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = 000000007FFF0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = 0000FFFFFFFF0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = 7FFFFFFFFFFF0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = 800000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = 8000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x00 = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = 8000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x00 = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x00 = 00000000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = 5555CCCCFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = 5555CCCCFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = 5555CCCCFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = FFFFFFFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = FFFFFFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x00 = 0000F000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x00 = FFFFF000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = 00000CCCFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = 0000FCCCFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = FFFFFCCCFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = 00000FFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = 0000FFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x00 = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x00 = 00000000001FFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = 5555CCCCFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = 5555CCCCFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = 5555CCCCFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = FFFFFFFFFFE00001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = FFFFFFFFFFECAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x00 = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x00 = 00000000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = 5555CCCCFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = 5555CCCCFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = 5555CCCCFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = FFFFFFFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = FFFFFFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x00 = 0000FFFF800CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x00 = FFFFFFFF801FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = 000000007FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = 0000FFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = 000000007FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = 0000FFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x00 = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x00 = 00000000001FFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = 5555CCCCFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = 5555CCCCFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = 5555CCCCFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = FFFFFFFFFFE00001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = FFFFFFFFFFECAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = 5555CCCCFFFF0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = 5555CCCCFFFF0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = 5555CCCCFFFF0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x00 = 0000F00000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x00 = FFFFF00000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = 00000CCCFFFF0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = 0000FCCCFFFF0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = FFFFFCCCFFFF0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = 0000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = 5555CCCCFFFF0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = 5555CCCCFFFF0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = 5555CCCCFFFF0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x00 = 0000FFFF80000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x00 = FFFFFFFF80000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = 000000007FFF0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = 0000FFFFFFFF0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = FFFFFFFFFFFF0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = 000000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = 0000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = 8000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = 8000000000000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = 00000CCCFFFF0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = 00000CCCFFFF0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = 00000CCCFFFF0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = 80000FFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = 8000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = 8000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = 8000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = 8000000000000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = 000000007FFF0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = 000000007FFF0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = 000000007FFF0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = 800000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = 800000007FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = 800000007FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = 8000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = 8000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = 5555CCCC00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = 5555CCCC00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = 5555CCCC00000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = FFFFFFFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = 00000CCC00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = 00000CCC00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = 00000CCC00000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = 00000FFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = 00000FFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = 00000FFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = 5555CCCC00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = 5555CCCC00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = 5555CCCC00000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = FFFFFFFE00000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = 5555CCCC00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = 5555CCCC00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = 5555CCCC00000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = FFFFFFFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = 5555CCCC7FFF0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = 5555CCCC7FFF0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = 5555CCCC7FFF0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = FFFFFFFE7FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = FFFFFFFE7FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = FFFFFFFE7FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = 5555CCCC00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = 5555CCCC00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = 5555CCCC00000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = FFFFFFFE00000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = 5555CCCCFFFF0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = 5555CCCCFFFF0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = 5555CCCCFFFF0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = 00000CCCFFFF0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = 00000CCCFFFF0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = 00000CCCFFFF0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = 00000FFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = 0000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = 0000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = 5555CCCCFFFF0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = 5555CCCCFFFF0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = 5555CCCCFFFF0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = 000000007FFF0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = 000000007FFF0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = 000000007FFF0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = 000000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = 000000007FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = 000000007FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x00 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = 0000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = 0000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x01 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x01 = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x01 = 0000F00000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x01 = 7FFFF00000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = 80000999FFFE0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = 8000F999FFFE0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = FFFFF999FFFE0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = 8000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x01 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x01 = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = 8000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x01 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x01 = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x01 = 0000FFFF80000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x01 = 7FFFFFFF80000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = 800000007FFE0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = 8000FFFFFFFE0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = FFFFFFFFFFFE0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = 800000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = 8000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x01 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x01 = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = 8000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x01 = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x01 = 00000000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = AAAB9999FFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = AAAB9999FFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = AAAB9999FFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = FFFFFFFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = FFFFFFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x01 = 0000F000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x01 = FFFFF000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = 00000999FFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = 0000F999FFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = FFFFF999FFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = 00000FFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = 0000FFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x01 = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x01 = 00000000001FFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = AAAB9999FFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = AAAB9999FFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = AAAB9999FFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = FFFFFFFFFFE00001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = FFFFFFFFFFECAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x01 = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x01 = 00000000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = AAAB9999FFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = AAAB9999FFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = AAAB9999FFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = FFFFFFFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = FFFFFFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x01 = 0000FFFF800CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x01 = FFFFFFFF801FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = 000000007FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = 0000FFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = 000000007FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = 0000FFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x01 = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x01 = 00000000001FFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = AAAB9999FFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = AAAB9999FFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = AAAB9999FFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = FFFFFFFFFFE00001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = FFFFFFFFFFECAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = AAAB9999FFFE0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = AAAB9999FFFE0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = AAAB9999FFFE0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x01 = 0000F00000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x01 = FFFFF00000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = 00000999FFFE0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = 0000F999FFFE0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = FFFFF999FFFE0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = 0000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = AAAB9999FFFE0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = AAAB9999FFFE0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = AAAB9999FFFE0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x01 = 0000FFFF80000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x01 = FFFFFFFF80000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = 000000007FFE0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = 0000FFFFFFFE0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = FFFFFFFFFFFE0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = 000000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = 0000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = 8000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = 8000000000000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = 80000999FFFE0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = 80000999FFFE0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = 80000999FFFE0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = 80000FFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = 8000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = 8000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = 8000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = 8000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = 8000000000000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = 800000007FFE0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = 800000007FFE0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = 800000007FFE0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = 800000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = 800000007FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = 800000007FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = 8000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = 8000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = 8000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = 8000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = AAAB999800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = AAAB999800000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = AAAB999800000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = FFFFFFFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = 0000099800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = 0000099800000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = 0000099800000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = 00000FFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = 00000FFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = 00000FFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = AAAB999800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = AAAB999800000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = AAAB999800000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = FFFFFFFE00000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = AAAB999800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = AAAB999800000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = AAAB999800000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = FFFFFFFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = AAAB99987FFE0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = AAAB99987FFE0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = AAAB99987FFE0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = FFFFFFFE7FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = FFFFFFFE7FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = FFFFFFFE7FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = AAAB999800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = AAAB999800000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = AAAB999800000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = FFFFFFFE00000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = AAAB9999FFFE0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = AAAB9999FFFE0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = AAAB9999FFFE0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = 00000999FFFE0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = 00000999FFFE0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = 00000999FFFE0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = 00000FFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = 0000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = 0000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = AAAB9999FFFE0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = AAAB9999FFFE0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = AAAB9999FFFE0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = 000000007FFE0000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = 000000007FFE0000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = 000000007FFE0000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = 000000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = 000000007FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = 000000007FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x01 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = 0000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = 0000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x13 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x13 = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = 8000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x13 = 0000F00000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x13 = 7FFFF00000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = 00000FF80002AAAE (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = 0000FFF80002AAAE (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = 7FFFFFF80002AAAE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = 8000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x13 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x13 = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = 8000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x13 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x13 = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = 8000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x13 = 0000FFFF80000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x13 = 7FFFFFFF80000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = 000000000002AAAE (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = 0000FFFF8002AAAE (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = 7FFFFFFF8002AAAE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = 800000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = 8000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x13 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x13 = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = 8000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x13 = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x13 = 00000000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = 6667FFF800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = 6667FFF8000CAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = 6667FFF8001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = FFFFFFFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = FFFFFFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x13 = 0000F000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x13 = FFFFF000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = 00000FF800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = 0000FFF8000CAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = FFFFFFF8001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = 00000FFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = 0000FFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x13 = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x13 = 00000000001FFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = 6667FFF800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = 6667FFF8000CAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = 6667FFF8001FFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = FFFFFFFFFFE00001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = FFFFFFFFFFECAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x13 = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x13 = 00000000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = 6667FFF800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = 6667FFF8000CAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = 6667FFF8001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = FFFFFFFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = FFFFFFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x13 = 0000FFFF800CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x13 = FFFFFFFF801FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = 0000FFFF800CAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = FFFFFFFF801FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = 000000007FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = 0000FFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x13 = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x13 = 00000000001FFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = 6667FFF800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = 6667FFF8000CAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = 6667FFF8001FFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = FFFFFFFFFFE00001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = FFFFFFFFFFECAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = 6667FFF80002AAAE (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = 6667FFF80002AAAE (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = 6667FFF80002AAAE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x13 = 0000F00000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x13 = FFFFF00000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = 00000FF80002AAAE (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = 0000FFF80002AAAE (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = FFFFFFF80002AAAE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = 0000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = 6667FFF80002AAAE (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = 6667FFF80002AAAE (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = 6667FFF80002AAAE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x13 = 0000FFFF80000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x13 = FFFFFFFF80000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = 000000000002AAAE (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = 0000FFFF8002AAAE (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = FFFFFFFF8002AAAE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = 000000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = 0000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = 8000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = 8000000000000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = 00000FF80002AAAE (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = 00000FF80002AAAE (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = 00000FF80002AAAE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = 80000FFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = 8000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = 8000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = 8000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = 8000000000000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = 000000000002AAAE (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = 000000000002AAAE (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = 000000000002AAAE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = 800000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = 800000007FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = 800000007FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = 8000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = 8000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = 6667FFF800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = 6667FFF800000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = 6667FFF800000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = FFFFFFFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = 00000FF800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = 00000FF800000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = 00000FF800000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = 00000FFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = 00000FFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = 00000FFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = 6667FFF800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = 6667FFF800000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = 6667FFF800000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = FFFFFFFE00000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = 6667FFF800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = 6667FFF800000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = 6667FFF800000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = FFFFFFFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = 6667FFF80002AAAE (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = 6667FFF80002AAAE (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = 6667FFF80002AAAE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = FFFFFFFE7FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = FFFFFFFE7FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = FFFFFFFE7FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = 6667FFF800000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = 6667FFF800000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = 6667FFF800000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = FFFFFFFE00000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = 6667FFF80002AAAE (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = 6667FFF80002AAAE (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = 6667FFF80002AAAE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = 00000FF80002AAAE (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = 00000FF80002AAAE (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = 00000FF80002AAAE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = 00000FFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = 0000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = 0000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = 6667FFF80002AAAE (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = 6667FFF80002AAAE (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = 6667FFF80002AAAE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = 000000000002AAAE (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = 000000000002AAAE (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = 000000000002AAAE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = 000000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = 000000007FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = 000000007FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x13 = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = 0000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = 0000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x3e = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x3e = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = 8000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x3e = 0000F00000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x3e = 7FFFF00000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = 000003333FFFC000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = 0000F3333FFFC000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = 7FFFF3333FFFC000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = 8000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x3e = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x3e = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = 8000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x3e = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x3e = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = 8000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x3e = 0000FFFF80000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x3e = 7FFFFFFF80000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = 000000003FFFC000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = 0000FFFFBFFFC000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = 7FFFFFFFBFFFC000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = 800000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = 8000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x3e = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x3e = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = 8000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x3e = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x3e = 00000000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = 155573333FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = 155573333FECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = 155573333FFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = FFFFFFFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = FFFFFFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x3e = 0000F000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x3e = FFFFF000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = 000003333FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = 0000F3333FECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = FFFFF3333FFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = 00000FFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = 0000FFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x3e = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x3e = 00000000001FFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = 155573333FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = 155573333FECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = 155573333FFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = FFFFFFFFFFE00001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = FFFFFFFFFFECAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x3e = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x3e = 00000000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = 155573333FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = 155573333FECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = 155573333FFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = FFFFFFFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = FFFFFFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x3e = 0000FFFF800CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x3e = FFFFFFFF801FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = 000000003FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = 0000FFFFBFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = FFFFFFFFBFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = 000000007FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = 0000FFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x3e = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x3e = 00000000001FFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = 155573333FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = 155573333FECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = 155573333FFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = FFFFFFFFFFE00001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = FFFFFFFFFFECAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = 155573333FFFC000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = 155573333FFFC000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = 155573333FFFC000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x3e = 0000F00000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x3e = FFFFF00000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = 000003333FFFC000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = 0000F3333FFFC000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = FFFFF3333FFFC000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = 0000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = 155573333FFFC000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = 155573333FFFC000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = 155573333FFFC000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x3e = 0000FFFF80000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x3e = FFFFFFFF80000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = 000000003FFFC000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = 0000FFFFBFFFC000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = FFFFFFFFBFFFC000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = 000000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = 0000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = 8000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = 8000000000000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = 000003333FFFC000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = 000003333FFFC000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = 000003333FFFC000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = 80000FFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = 8000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = 8000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = 8000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = 8000000000000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = 000000003FFFC000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = 000000003FFFC000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = 000000003FFFC000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = 800000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = 800000007FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = 800000007FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = 8000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = 8000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = 1555733200000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = 1555733200000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = 1555733200000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = FFFFFFFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = 0000033200000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = 0000033200000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = 0000033200000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = 00000FFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = 00000FFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = 00000FFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = 1555733200000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = 1555733200000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = 1555733200000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = FFFFFFFE00000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = 1555733200000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = 1555733200000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = 1555733200000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = FFFFFFFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = 155573323FFFC000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = 155573323FFFC000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = 155573323FFFC000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = FFFFFFFE7FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = FFFFFFFE7FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = FFFFFFFE7FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = 1555733200000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = 1555733200000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = 1555733200000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = FFFFFFFE00000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = 155573333FFFC000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = 155573333FFFC000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = 155573333FFFC000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = 000003333FFFC000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = 000003333FFFC000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = 000003333FFFC000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = 00000FFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = 0000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = 0000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = 155573333FFFC000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = 155573333FFFC000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = 155573333FFFC000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = 000000003FFFC000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = 000000003FFFC000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = 000000003FFFC000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = 000000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = 000000007FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = 000000007FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x3e = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = 0000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = 0000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x3f = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x3f = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = 8000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x3f = 0000F00000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x3f = 7FFFF00000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = 000006667FFF8000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = 0000F6667FFF8000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = 7FFFF6667FFF8000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = 8000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x3f = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x3f = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = 8000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x3f = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x3f = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = 7FFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = 8000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x3f = 0000FFFF80000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x3f = 7FFFFFFF80000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = 000000007FFF8000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = 0000FFFFFFFF8000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = 7FFFFFFFFFFF8000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = 800000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = 8000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x3f = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x3f = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = 7FFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = 8000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x3f = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x3f = 00000000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = 2AAAE6667FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = 2AAAE6667FECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = 2AAAE6667FFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = FFFFFFFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = FFFFFFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x3f = 0000F000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x3f = FFFFF000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = 000006667FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = 0000F6667FECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = FFFFF6667FFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = 00000FFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = 0000FFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x3f = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x3f = 00000000001FFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = 2AAAE6667FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = 2AAAE6667FECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = 2AAAE6667FFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = FFFFFFFFFFE00001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = FFFFFFFFFFECAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x3f = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x3f = 00000000001FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = 2AAAE6667FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = 2AAAE6667FECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = 2AAAE6667FFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = FFFFFFFFFFE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = FFFFFFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x3f = 0000FFFF800CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x3f = FFFFFFFF801FFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = 000000007FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = 0000FFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = 000000007FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = 0000FFFFFFECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x3f = 00000000000CAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x3f = 00000000001FFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = 2AAAE6667FE00000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = 2AAAE6667FECAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = 2AAAE6667FFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = FFFFFFFFFFE00001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = FFFFFFFFFFECAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = 2AAAE6667FFF8000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = 2AAAE6667FFF8000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = 2AAAE6667FFF8000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x3f = 0000F00000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x3f = FFFFF00000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = 000006667FFF8000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = 0000F6667FFF8000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = FFFFF6667FFF8000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = 0000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = 2AAAE6667FFF8000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = 2AAAE6667FFF8000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = 2AAAE6667FFF8000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x3f = 0000FFFF80000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x3f = FFFFFFFF80000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = 000000007FFF8000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = 0000FFFFFFFF8000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = FFFFFFFFFFFF8000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = 000000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = 0000FFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFE (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAB (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = 8000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = 8000000000000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = 000006667FFF8000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = 000006667FFF8000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = 000006667FFF8000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = 80000FFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = 80000FFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = 8000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = 8000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = 8000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = 8000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = 8000000000000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = 000000007FFF8000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = 000000007FFF8000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = 000000007FFF8000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = 800000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = 800000007FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = 800000007FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = 8000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = 8000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = 8000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = 2AAAE66600000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = 2AAAE66600000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = 2AAAE66600000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = FFFFFFFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = 0000066600000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = 0000066600000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = 0000066600000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = 00000FFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = 00000FFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = 00000FFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = 2AAAE66600000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = 2AAAE66600000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = 2AAAE66600000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = FFFFFFFE00000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = 2AAAE66600000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = 2AAAE66600000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = 2AAAE66600000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = FFFFFFFE00000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = FFFFFFFE00000000 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = 2AAAE6667FFF8000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = 2AAAE6667FFF8000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = 2AAAE6667FFF8000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = FFFFFFFE7FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = FFFFFFFE7FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = FFFFFFFE7FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = 2AAAE66600000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = 2AAAE66600000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = 2AAAE66600000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = FFFFFFFE00000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = FFFFFFFE00000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = 2AAAE6667FFF8000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = 2AAAE6667FFF8000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = 2AAAE6667FFF8000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = 000006667FFF8000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = 000006667FFF8000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = 000006667FFF8000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = 00000FFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = 00000FFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = 0000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = 0000000000000001 (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = 2AAAE6667FFF8000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = 2AAAE6667FFF8000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = 2AAAE6667FFF8000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = 000000007FFF8000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = 000000007FFF8000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = 000000007FFF8000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = 000000007FFFFFFF (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = 000000007FFFFFFF (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = 000000007FFFFFFF (cc=0)
+RISBGN r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x3f = 0000000000000000 (cc=0)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = 0000000000000000 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = 0000000000000000 (cc=2)
+RISBGN r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = 0000000000000001 (cc=1)
+RISBGN r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = 0000000000000001 (cc=1)
+RISBGN r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = 0000000000000001 (cc=0)
diff --git a/none/tests/scripts/Makefile.in b/none/tests/scripts/Makefile.in
new file mode 100644
index 0000000..eece669
--- /dev/null
+++ b/none/tests/scripts/Makefile.in
@@ -0,0 +1,826 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+am__is_gnu_make = { \
+ if test -z '$(MAKELEVEL)'; then \
+ false; \
+ elif test -n '$(MAKE_HOST)'; then \
+ true; \
+ elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
+ true; \
+ else \
+ false; \
+ fi; \
+}
+am__make_running_with_option = \
+ case $${target_option-} in \
+ ?) ;; \
+ *) echo "am__make_running_with_option: internal error: invalid" \
+ "target option '$${target_option-}' specified" >&2; \
+ exit 1;; \
+ esac; \
+ has_opt=no; \
+ sane_makeflags=$$MAKEFLAGS; \
+ if $(am__is_gnu_make); then \
+ sane_makeflags=$$MFLAGS; \
+ else \
+ case $$MAKEFLAGS in \
+ *\\[\ \ ]*) \
+ bs=\\; \
+ sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
+ | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \
+ esac; \
+ fi; \
+ skip_next=no; \
+ strip_trailopt () \
+ { \
+ flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
+ }; \
+ for flg in $$sane_makeflags; do \
+ test $$skip_next = yes && { skip_next=no; continue; }; \
+ case $$flg in \
+ *=*|--*) continue;; \
+ -*I) strip_trailopt 'I'; skip_next=yes;; \
+ -*I?*) strip_trailopt 'I';; \
+ -*O) strip_trailopt 'O'; skip_next=yes;; \
+ -*O?*) strip_trailopt 'O';; \
+ -*l) strip_trailopt 'l'; skip_next=yes;; \
+ -*l?*) strip_trailopt 'l';; \
+ -[dEDm]) skip_next=yes;; \
+ -[JT]) skip_next=yes;; \
+ esac; \
+ case $$flg in \
+ *$$target_option*) has_opt=yes; break;; \
+ esac; \
+ done; \
+ test $$has_opt = yes
+am__make_dryrun = (target_option=n; $(am__make_running_with_option))
+am__make_keepgoing = (target_option=k; $(am__make_running_with_option))
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+@COMPILER_IS_CLANG_TRUE@am__append_1 = -Wno-cast-align -Wno-self-assign \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-compare
+
+@SOLARIS_XPG_SYMBOLS_PRESENT_TRUE@am__append_2 = -Wl,-M,$(top_srcdir)/solaris/vgpreload-solaris.mapfile
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_3 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+
+# Make sure that all test programs have threaded errno.
+# Disable largefile support as there are test cases explictly enabling it.
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
+@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
+@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-constant-out-of-range-compare \
+@COMPILER_IS_CLANG_TRUE@ -Wno-self-assign -Wno-string-plus-int \
+@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
+@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
+@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
+subdir = none/tests/scripts
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.ac
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+DIST_COMMON = $(srcdir)/Makefile.am $(dist_noinst_SCRIPTS) \
+ $(am__DIST_COMMON)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+SCRIPTS = $(dist_noinst_SCRIPTS)
+AM_V_P = $(am__v_P_@AM_V@)
+am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
+am__v_P_0 = false
+am__v_P_1 = :
+AM_V_GEN = $(am__v_GEN_@AM_V@)
+am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@)
+am__v_GEN_0 = @echo " GEN " $@;
+am__v_GEN_1 =
+AM_V_at = $(am__v_at_@AM_V@)
+am__v_at_ = $(am__v_at_@AM_DEFAULT_V@)
+am__v_at_0 = @
+am__v_at_1 =
+SOURCES =
+DIST_SOURCES =
+am__can_run_installinfo = \
+ case $$AM_UPDATE_INFO_DIR in \
+ n|no|NO) false;; \
+ *) (install-info --version) >/dev/null 2>&1;; \
+ esac
+am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) $(LISP)
+am__DIST_COMMON = $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+ $(top_srcdir)/Makefile.tool-tests.am
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AM_DEFAULT_VERBOSITY = @AM_DEFAULT_VERBOSITY@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CFLAGS_MPI = @CFLAGS_MPI@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+DIS_PATH = @DIS_PATH@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_IPA_ICF = @FLAG_FNO_IPA_ICF@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_FSANITIZE = @FLAG_FSANITIZE@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MIPS32 = @FLAG_MIPS32@
+FLAG_MIPS64 = @FLAG_MIPS64@
+FLAG_MLONG_DOUBLE_128 = @FLAG_MLONG_DOUBLE_128@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_OCTEON = @FLAG_OCTEON@
+FLAG_OCTEON2 = @FLAG_OCTEON2@
+FLAG_T_TEXT = @FLAG_T_TEXT@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_CAST_ALIGN = @FLAG_W_CAST_ALIGN@
+FLAG_W_CAST_QUAL = @FLAG_W_CAST_QUAL@
+FLAG_W_EMPTY_BODY = @FLAG_W_EMPTY_BODY@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_FORMAT = @FLAG_W_FORMAT@
+FLAG_W_FORMAT_SECURITY = @FLAG_W_FORMAT_SECURITY@
+FLAG_W_FORMAT_SIGNEDNESS = @FLAG_W_FORMAT_SIGNEDNESS@
+FLAG_W_IGNORED_QUALIFIERS = @FLAG_W_IGNORED_QUALIFIERS@
+FLAG_W_MISSING_PARAMETER_TYPE = @FLAG_W_MISSING_PARAMETER_TYPE@
+FLAG_W_NO_INFINITE_RECURSION = @FLAG_W_NO_INFINITE_RECURSION@
+FLAG_W_NO_MEMSET_TRANSPOSED_ARGS = @FLAG_W_NO_MEMSET_TRANSPOSED_ARGS@
+FLAG_W_NO_MISMATCHED_NEW_DELETE = @FLAG_W_NO_MISMATCHED_NEW_DELETE@
+FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@
+FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@
+FLAG_W_NO_POINTER_SIGN = @FLAG_W_NO_POINTER_SIGN@
+FLAG_W_NO_STATIC_LOCAL_IN_INLINE = @FLAG_W_NO_STATIC_LOCAL_IN_INLINE@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+FLAG_W_NO_UNUSED_FUNCTION = @FLAG_W_NO_UNUSED_FUNCTION@
+FLAG_W_OLD_STYLE_DECLARATION = @FLAG_W_OLD_STYLE_DECLARATION@
+FLAG_W_WRITE_STRINGS = @FLAG_W_WRITE_STRINGS@
+GDB = @GDB@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+HWCAP_HAS_ALTIVEC = @HWCAP_HAS_ALTIVEC@
+HWCAP_HAS_DFP = @HWCAP_HAS_DFP@
+HWCAP_HAS_HTM = @HWCAP_HAS_HTM@
+HWCAP_HAS_ISA_2_05 = @HWCAP_HAS_ISA_2_05@
+HWCAP_HAS_ISA_2_06 = @HWCAP_HAS_ISA_2_06@
+HWCAP_HAS_ISA_2_07 = @HWCAP_HAS_ISA_2_07@
+HWCAP_HAS_ISA_3_00 = @HWCAP_HAS_ISA_3_00@
+HWCAP_HAS_VSX = @HWCAP_HAS_VSX@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_MPI = @LDFLAGS_MPI@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LIB_UBSAN = @LIB_UBSAN@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PREFERRED_STACK_BOUNDARY_2 = @PREFERRED_STACK_BOUNDARY_2@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+SOLARIS_UNDEF_LARGESOURCE = @SOLARIS_UNDEF_LARGESOURCE@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@
+VG_TMPDIR = @VG_TMPDIR@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = -O2 -g -std=gnu99 -Wall -Wmissing-prototypes -Wshadow \
+ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \
+ @FLAG_W_CAST_ALIGN@ @FLAG_W_CAST_QUAL@ @FLAG_W_WRITE_STRINGS@ \
+ @FLAG_W_EMPTY_BODY@ @FLAG_W_FORMAT@ @FLAG_W_FORMAT_SIGNEDNESS@ \
+ @FLAG_W_FORMAT_SECURITY@ @FLAG_W_IGNORED_QUALIFIERS@ \
+ @FLAG_W_MISSING_PARAMETER_TYPE@ @FLAG_W_OLD_STYLE_DECLARATION@ \
+ @FLAG_FNO_STACK_PROTECTOR@ @FLAG_FSANITIZE@ \
+ -fno-strict-aliasing -fno-builtin $(am__append_1)
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fpic -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# These flags are used for building the preload shared objects (PSOs).
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads. Also, we must use any
+# -mpreferred-stack-boundary flag to build the preload shared
+# objects, since that risks misaligning the client's stack and
+# results in segfaults like (eg) #324050.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \
+@VGCONF_OS_IS_DARWIN_TRUE@ -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
+ -I$(top_srcdir)/VEX/pub \
+ -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
+ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
+AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
+AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
+AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
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+ proc_auxv_multiple.c proc_psinfo.c pthread-stack.c \
+ reserve_sysstat_addr.c reserve_sysstat_zone_addr.c resolv.c \
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+ context_link2.c context_null.c context_stack.c \
+ coredump_many_segments.c coredump_many_threads.c \
+ mmap_noreserve.c posix_spawn.c proc_aout.c proc_auxv.c \
+ proc_auxv_multiple.c proc_psinfo.c pthread-stack.c \
+ reserve_sysstat_addr.c reserve_sysstat_zone_addr.c resolv.c \
+ sigresend.c stack-overflow.c stack_prot.c threads_exitall.c
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+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
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+
+
+# These flags are used for building the preload shared objects (PSOs).
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads. Also, we must use any
+# -mpreferred-stack-boundary flag to build the preload shared
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+
+# Flags for specific targets.
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+ -I$(top_builddir)/VEX/pub \
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+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
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+
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+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
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+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
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+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
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+ $(AM_CFLAGS_PSO_BASE)
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+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
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+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
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+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS TAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local cscopelist-am \
+ ctags ctags-am distclean distclean-compile distclean-generic \
+ distclean-tags distdir dvi dvi-am html html-am info info-am \
+ install install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-html \
+ install-html-am install-info install-info-am install-man \
+ install-pdf install-pdf-am install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ maintainer-clean maintainer-clean-generic mostlyclean \
+ mostlyclean-compile mostlyclean-generic pdf pdf-am ps ps-am \
+ tags tags-am uninstall uninstall-am
+
+.PRECIOUS: Makefile
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
+# It needs to be depended on by an 'uninstall-local' rule.
+uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
+uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/none/tests/solaris/context_link2.c b/none/tests/solaris/context_link2.c
index 9d64b6b..7979b73 100644
--- a/none/tests/solaris/context_link2.c
+++ b/none/tests/solaris/context_link2.c
@@ -5,13 +5,13 @@
#include <stdio.h>
#include <ucontext.h>
-static void sighandler(int sig, siginfo_t *sip, ucontext_t *ucp)
+static void sighandler(int sig, siginfo_t *sip, void *arg)
{
ucontext_t uc2;
- /* Current uc_link value has to be equal to ucp. */
+ /* Current uc_link value has to be equal to (ucontext_t *) arg. */
getcontext(&uc2);
- assert(uc2.uc_link == ucp);
+ assert(uc2.uc_link == arg);
}
int main(void)
@@ -26,7 +26,7 @@
}
assert(!uc.uc_link);
- sa.sa_handler = sighandler;
+ sa.sa_sigaction = sighandler;
sa.sa_flags = SA_SIGINFO;
if (sigfillset(&sa.sa_mask)) {
perror("sigfillset");
diff --git a/none/tests/solaris/coredump_many_threads.post.exp b/none/tests/solaris/coredump_many_threads.post.exp
index 5c94dc2..a595635 100644
--- a/none/tests/solaris/coredump_many_threads.post.exp
+++ b/none/tests/solaris/coredump_many_threads.post.exp
@@ -1,7 +1,6 @@
---Status---
debugging core file of coredump_many_t from ...
initial argv: ./coredump_many_threads
-threading model: native threads
status: process terminated by SIGSEGV (Segmentation Fault), addr=........
---Stacks---
@@ -12,48 +11,48 @@
1 UNPARKED <NONE> 1
libc.so.1`sleep
-coredump_many_threads`main
-coredump_many_threads`_start
+main
+_start
2 UNPARKED <NONE> 1
libc.so.1`sleep
-coredump_many_threads`thread_func2
+thread_func2
libc.so.1`_thrp_setup
libc.so.1`_lwp_start
3 UNPARKED <NONE> 1
libc.so.1`sleep
-coredump_many_threads`thread_func3
+thread_func3
libc.so.1`_thrp_setup
libc.so.1`_lwp_start
4 UNPARKED <NONE> 1
libc.so.1`sleep
-coredump_many_threads`thread_func4
+thread_func4
libc.so.1`_thrp_setup
libc.so.1`_lwp_start
6 UNPARKED <NONE> 1
libc.so.1`sleep
-coredump_many_threads`thread_func6
+thread_func6
libc.so.1`_thrp_setup
libc.so.1`_lwp_start
7 UNPARKED <NONE> 1
libc.so.1`sleep
-coredump_many_threads`thread_func7
+thread_func7
libc.so.1`_thrp_setup
libc.so.1`_lwp_start
8 UNPARKED <NONE> 1
libc.so.1`sleep
-coredump_many_threads`thread_func8
+thread_func8
libc.so.1`_thrp_setup
libc.so.1`_lwp_start
9 UNPARKED <NONE> 1
libc.so.1`sleep
-coredump_many_threads`thread_func9
+thread_func9
libc.so.1`_thrp_setup
libc.so.1`_lwp_start
diff --git a/none/tests/solaris/filter_coredump_many_threads_post b/none/tests/solaris/filter_coredump_many_threads_post
index 5a893a2..2d03370 100755
--- a/none/tests/solaris/filter_coredump_many_threads_post
+++ b/none/tests/solaris/filter_coredump_many_threads_post
@@ -7,6 +7,7 @@
echo "::status" | /usr/bin/mdb vgcore.* | \
perl -p -e 's/\(.*\) from \S*$/from .../' | \
perl -0 -p -e 's/^file: .+?^(initial argv:)/$1/ms' | \
+sed '/^threading model:/ d' | \
perl -p -e 's/addr=[0-9A-Fa-f]+/addr=......../g'
echo "\n---Stacks---"
@@ -14,5 +15,5 @@
perl -p -e 's/^(THREAD)\s+(STATE)\s+(SOBJ)\s+(COUNT)\s*$/$1 $2 $3 $4\n/' | \
perl -p -e 's/^(\d+)\s+(UNPARKED)\s+(\S+)\s+(\d+)/$1 $2 $3 $4/g' | \
perl -p -e 's/^\s*libc.*.so.1/libc.so.1/g' | \
-perl -p -e 's/^\s*(coredump_many_threads)/$1/g' | \
-perl -p -e 's/\+0x[0-9A-Fa-f]+//g'
+perl -p -e 's/\+0x[0-9A-Fa-f]+//g' |
+sed 's/^ *//g'
diff --git a/none/tests/solaris/reserve_sysstat_addr.stderr.exp b/none/tests/solaris/reserve_sysstat_addr.stderr.exp
index 05d2cc6..73ba489 100644
--- a/none/tests/solaris/reserve_sysstat_addr.stderr.exp
+++ b/none/tests/solaris/reserve_sysstat_addr.stderr.exp
@@ -11,4 +11,5 @@
sched status:
- running_tid=0
+ scheduler not yet initialised
+
diff --git a/none/tests/solaris/reserve_sysstat_zone_addr.stderr.exp b/none/tests/solaris/reserve_sysstat_zone_addr.stderr.exp
index e907920..32b0439 100644
--- a/none/tests/solaris/reserve_sysstat_zone_addr.stderr.exp
+++ b/none/tests/solaris/reserve_sysstat_zone_addr.stderr.exp
@@ -11,4 +11,5 @@
sched status:
- running_tid=0
+ scheduler not yet initialised
+
diff --git a/none/tests/solaris/stack-overflow.c b/none/tests/solaris/stack-overflow.c
index 0ebbfbb..60f1b7e 100644
--- a/none/tests/solaris/stack-overflow.c
+++ b/none/tests/solaris/stack-overflow.c
@@ -2,4 +2,4 @@
Written in a single line so there is no confusion on what line
the overflow occurs. */
-int main(int argc, char *argv[]) { volatile int arr[1000]; return main(arr[argc%2], 0); }
+int main(int argc, char *argv[]) { volatile int arr[1000] = {0}; return main(arr[argc%2], 0); }
diff --git a/none/tests/solaris/stack-overflow.vgtest b/none/tests/solaris/stack-overflow.vgtest
index 3b9ffd4..e7b4f29 100644
--- a/none/tests/solaris/stack-overflow.vgtest
+++ b/none/tests/solaris/stack-overflow.vgtest
@@ -1 +1,2 @@
prog: stack-overflow
+cleanup: rm -f vgcore.*
diff --git a/none/tests/tilegx/Makefile.in b/none/tests/tilegx/Makefile.in
new file mode 100644
index 0000000..1d19f73
--- /dev/null
+++ b/none/tests/tilegx/Makefile.in
@@ -0,0 +1,7162 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+
+VPATH = @srcdir@
+am__is_gnu_make = { \
+ if test -z '$(MAKELEVEL)'; then \
+ false; \
+ elif test -n '$(MAKE_HOST)'; then \
+ true; \
+ elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
+ true; \
+ else \
+ false; \
+ fi; \
+}
+am__make_running_with_option = \
+ case $${target_option-} in \
+ ?) ;; \
+ *) echo "am__make_running_with_option: internal error: invalid" \
+ "target option '$${target_option-}' specified" >&2; \
+ exit 1;; \
+ esac; \
+ has_opt=no; \
+ sane_makeflags=$$MAKEFLAGS; \
+ if $(am__is_gnu_make); then \
+ sane_makeflags=$$MFLAGS; \
+ else \
+ case $$MAKEFLAGS in \
+ *\\[\ \ ]*) \
+ bs=\\; \
+ sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
+ | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \
+ esac; \
+ fi; \
+ skip_next=no; \
+ strip_trailopt () \
+ { \
+ flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
+ }; \
+ for flg in $$sane_makeflags; do \
+ test $$skip_next = yes && { skip_next=no; continue; }; \
+ case $$flg in \
+ *=*|--*) continue;; \
+ -*I) strip_trailopt 'I'; skip_next=yes;; \
+ -*I?*) strip_trailopt 'I';; \
+ -*O) strip_trailopt 'O'; skip_next=yes;; \
+ -*O?*) strip_trailopt 'O';; \
+ -*l) strip_trailopt 'l'; skip_next=yes;; \
+ -*l?*) strip_trailopt 'l';; \
+ -[dEDm]) skip_next=yes;; \
+ -[JT]) skip_next=yes;; \
+ esac; \
+ case $$flg in \
+ *$$target_option*) has_opt=yes; break;; \
+ esac; \
+ done; \
+ test $$has_opt = yes
+am__make_dryrun = (target_option=n; $(am__make_running_with_option))
+am__make_keepgoing = (target_option=k; $(am__make_running_with_option))
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+@COMPILER_IS_CLANG_TRUE@am__append_1 = -Wno-cast-align -Wno-self-assign \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-compare
+
+@SOLARIS_XPG_SYMBOLS_PRESENT_TRUE@am__append_2 = -Wl,-M,$(top_srcdir)/solaris/vgpreload-solaris.mapfile
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_3 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+
+# Make sure that all test programs have threaded errno.
+# Disable largefile support as there are test cases explictly enabling it.
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
+@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
+@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-constant-out-of-range-compare \
+@COMPILER_IS_CLANG_TRUE@ -Wno-self-assign -Wno-string-plus-int \
+@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
+@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
+@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@am__append_8 = \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_X0.stdout.exp insn_test_move_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_X1.stdout.exp insn_test_move_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_Y0.stdout.exp insn_test_move_Y0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_Y0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_Y1.stdout.exp insn_test_move_Y1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_move_Y1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_X0.stdout.exp insn_test_movei_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_X1.stdout.exp insn_test_movei_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_Y0.stdout.exp insn_test_movei_Y0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_Y0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_Y1.stdout.exp insn_test_movei_Y1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_movei_Y1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_moveli_X0.stdout.exp insn_test_moveli_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_moveli_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_moveli_X1.stdout.exp insn_test_moveli_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_moveli_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_X1.stdout.exp insn_test_prefetch_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_Y2.stdout.exp insn_test_prefetch_Y2.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_Y2.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l1_X1.stdout.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l1_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l1_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l1_Y2.stdout.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l1_Y2.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l1_Y2.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l2_X1.stdout.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l2_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l2_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l2_Y2.stdout.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l2_Y2.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l2_Y2.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l3_X1.stdout.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l3_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l3_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l3_Y2.stdout.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l3_Y2.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_prefetch_l3_Y2.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_X0.stdout.exp insn_test_add_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_X1.stdout.exp insn_test_add_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_Y0.stdout.exp insn_test_add_Y0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_Y0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_Y1.stdout.exp insn_test_add_Y1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_add_Y1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addi_X0.stdout.exp insn_test_addi_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addi_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addi_X1.stdout.exp insn_test_addi_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addi_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addi_Y0.stdout.exp insn_test_addi_Y0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_addi_Y0.vgtest \
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+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sub_X0.stdout.exp insn_test_v2sub_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sub_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sub_X1.stdout.exp insn_test_v2sub_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2sub_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2subsc_X0.stdout.exp insn_test_v2subsc_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2subsc_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2subsc_X1.stdout.exp insn_test_v2subsc_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v2subsc_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4add_X0.stdout.exp insn_test_v4add_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4add_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4add_X1.stdout.exp insn_test_v4add_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4add_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4addsc_X0.stdout.exp insn_test_v4addsc_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4addsc_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4addsc_X1.stdout.exp insn_test_v4addsc_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4addsc_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_h_X0.stdout.exp insn_test_v4int_h_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_h_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_h_X1.stdout.exp insn_test_v4int_h_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_h_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_l_X0.stdout.exp insn_test_v4int_l_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_l_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_l_X1.stdout.exp insn_test_v4int_l_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4int_l_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4packsc_X0.stdout.exp insn_test_v4packsc_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4packsc_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4packsc_X1.stdout.exp insn_test_v4packsc_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4packsc_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shl_X0.stdout.exp insn_test_v4shl_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shl_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shl_X1.stdout.exp insn_test_v4shl_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shl_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shlsc_X0.stdout.exp insn_test_v4shlsc_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shlsc_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shlsc_X1.stdout.exp insn_test_v4shlsc_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shlsc_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shrs_X0.stdout.exp insn_test_v4shrs_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shrs_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shrs_X1.stdout.exp insn_test_v4shrs_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shrs_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shru_X0.stdout.exp insn_test_v4shru_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shru_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shru_X1.stdout.exp insn_test_v4shru_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4shru_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4sub_X0.stdout.exp insn_test_v4sub_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4sub_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4sub_X1.stdout.exp insn_test_v4sub_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4sub_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4subsc_X0.stdout.exp insn_test_v4subsc_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4subsc_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4subsc_X1.stdout.exp insn_test_v4subsc_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_v4subsc_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_wh64_X1.stdout.exp insn_test_wh64_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_wh64_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_X0.stdout.exp insn_test_xor_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_X1.stdout.exp insn_test_xor_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_X1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_Y0.stdout.exp insn_test_xor_Y0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_Y0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_Y1.stdout.exp insn_test_xor_Y1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xor_Y1.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xori_X0.stdout.exp insn_test_xori_X0.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xori_X0.vgtest \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xori_X1.stdout.exp insn_test_xori_X1.stderr.exp \
+@VGCONF_ARCHS_INCLUDE_TILEGX_TRUE@ insn_test_xori_X1.vgtest
+
+bin_PROGRAMS = gen_insn_test$(EXEEXT)
+check_PROGRAMS = allexec$(EXEEXT) $(am__EXEEXT_1)
+subdir = none/tests/tilegx
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.ac
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+DIST_COMMON = $(srcdir)/Makefile.am $(dist_noinst_SCRIPTS) \
+ $(am__DIST_COMMON)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+am__installdirs = "$(DESTDIR)$(bindir)"
+am__EXEEXT_1 = insn_test_move_X0$(EXEEXT) insn_test_move_X1$(EXEEXT) \
+ insn_test_move_Y0$(EXEEXT) insn_test_move_Y1$(EXEEXT) \
+ insn_test_movei_X0$(EXEEXT) insn_test_movei_X1$(EXEEXT) \
+ insn_test_movei_Y0$(EXEEXT) insn_test_movei_Y1$(EXEEXT) \
+ insn_test_moveli_X0$(EXEEXT) insn_test_moveli_X1$(EXEEXT) \
+ insn_test_prefetch_X1$(EXEEXT) insn_test_prefetch_Y2$(EXEEXT) \
+ insn_test_prefetch_l1_X1$(EXEEXT) \
+ insn_test_prefetch_l1_Y2$(EXEEXT) \
+ insn_test_prefetch_l2_X1$(EXEEXT) \
+ insn_test_prefetch_l2_Y2$(EXEEXT) \
+ insn_test_prefetch_l3_X1$(EXEEXT) \
+ insn_test_prefetch_l3_Y2$(EXEEXT) insn_test_add_X0$(EXEEXT) \
+ insn_test_add_X1$(EXEEXT) insn_test_add_Y0$(EXEEXT) \
+ insn_test_add_Y1$(EXEEXT) insn_test_addi_X0$(EXEEXT) \
+ insn_test_addi_X1$(EXEEXT) insn_test_addi_Y0$(EXEEXT) \
+ insn_test_addi_Y1$(EXEEXT) insn_test_addli_X0$(EXEEXT) \
+ insn_test_addli_X1$(EXEEXT) insn_test_addx_X0$(EXEEXT) \
+ insn_test_addx_X1$(EXEEXT) insn_test_addx_Y0$(EXEEXT) \
+ insn_test_addx_Y1$(EXEEXT) insn_test_addxi_X0$(EXEEXT) \
+ insn_test_addxi_X1$(EXEEXT) insn_test_addxi_Y0$(EXEEXT) \
+ insn_test_addxi_Y1$(EXEEXT) insn_test_addxli_X0$(EXEEXT) \
+ insn_test_addxli_X1$(EXEEXT) insn_test_addxsc_X0$(EXEEXT) \
+ insn_test_addxsc_X1$(EXEEXT) insn_test_and_X0$(EXEEXT) \
+ insn_test_and_X1$(EXEEXT) insn_test_and_Y0$(EXEEXT) \
+ insn_test_and_Y1$(EXEEXT) insn_test_andi_X0$(EXEEXT) \
+ insn_test_andi_X1$(EXEEXT) insn_test_andi_Y0$(EXEEXT) \
+ insn_test_andi_Y1$(EXEEXT) insn_test_beqz_X1$(EXEEXT) \
+ insn_test_beqzt_X1$(EXEEXT) insn_test_bfexts_X0$(EXEEXT) \
+ insn_test_bfextu_X0$(EXEEXT) insn_test_bfins_X0$(EXEEXT) \
+ insn_test_bgez_X1$(EXEEXT) insn_test_bgezt_X1$(EXEEXT) \
+ insn_test_bgtz_X1$(EXEEXT) insn_test_bgtzt_X1$(EXEEXT) \
+ insn_test_blbc_X1$(EXEEXT) insn_test_blbct_X1$(EXEEXT) \
+ insn_test_blbs_X1$(EXEEXT) insn_test_blbst_X1$(EXEEXT) \
+ insn_test_blez_X1$(EXEEXT) insn_test_blezt_X1$(EXEEXT) \
+ insn_test_bltz_X1$(EXEEXT) insn_test_bltzt_X1$(EXEEXT) \
+ insn_test_bnez_X1$(EXEEXT) insn_test_bnezt_X1$(EXEEXT) \
+ insn_test_clz_X0$(EXEEXT) insn_test_clz_Y0$(EXEEXT) \
+ insn_test_cmoveqz_X0$(EXEEXT) insn_test_cmoveqz_Y0$(EXEEXT) \
+ insn_test_cmovnez_X0$(EXEEXT) insn_test_cmovnez_Y0$(EXEEXT) \
+ insn_test_cmpeq_X0$(EXEEXT) insn_test_cmpeq_X1$(EXEEXT) \
+ insn_test_cmpeq_Y0$(EXEEXT) insn_test_cmpeq_Y1$(EXEEXT) \
+ insn_test_cmpeqi_X0$(EXEEXT) insn_test_cmpeqi_X1$(EXEEXT) \
+ insn_test_cmpeqi_Y0$(EXEEXT) insn_test_cmpeqi_Y1$(EXEEXT) \
+ insn_test_cmples_X0$(EXEEXT) insn_test_cmples_X1$(EXEEXT) \
+ insn_test_cmples_Y0$(EXEEXT) insn_test_cmples_Y1$(EXEEXT) \
+ insn_test_cmpleu_X0$(EXEEXT) insn_test_cmpleu_X1$(EXEEXT) \
+ insn_test_cmpleu_Y0$(EXEEXT) insn_test_cmpleu_Y1$(EXEEXT) \
+ insn_test_cmplts_X0$(EXEEXT) insn_test_cmplts_X1$(EXEEXT) \
+ insn_test_cmplts_Y0$(EXEEXT) insn_test_cmplts_Y1$(EXEEXT) \
+ insn_test_cmpltsi_X0$(EXEEXT) insn_test_cmpltsi_X1$(EXEEXT) \
+ insn_test_cmpltsi_Y0$(EXEEXT) insn_test_cmpltsi_Y1$(EXEEXT) \
+ insn_test_cmpltu_X0$(EXEEXT) insn_test_cmpltu_X1$(EXEEXT) \
+ insn_test_cmpltu_Y0$(EXEEXT) insn_test_cmpltu_Y1$(EXEEXT) \
+ insn_test_cmpltui_X0$(EXEEXT) insn_test_cmpltui_X1$(EXEEXT) \
+ insn_test_cmpne_X0$(EXEEXT) insn_test_cmpne_X1$(EXEEXT) \
+ insn_test_cmpne_Y0$(EXEEXT) insn_test_cmpne_Y1$(EXEEXT) \
+ insn_test_cmul_X0$(EXEEXT) insn_test_cmula_X0$(EXEEXT) \
+ insn_test_cmulaf_X0$(EXEEXT) insn_test_cmulf_X0$(EXEEXT) \
+ insn_test_cmulfr_X0$(EXEEXT) insn_test_cmulh_X0$(EXEEXT) \
+ insn_test_cmulhr_X0$(EXEEXT) insn_test_crc32_32_X0$(EXEEXT) \
+ insn_test_crc32_8_X0$(EXEEXT) insn_test_ctz_X0$(EXEEXT) \
+ insn_test_ctz_Y0$(EXEEXT) insn_test_dblalign_X0$(EXEEXT) \
+ insn_test_dblalign2_X0$(EXEEXT) \
+ insn_test_dblalign2_X1$(EXEEXT) \
+ insn_test_dblalign4_X0$(EXEEXT) \
+ insn_test_dblalign4_X1$(EXEEXT) \
+ insn_test_dblalign6_X0$(EXEEXT) \
+ insn_test_dblalign6_X1$(EXEEXT) insn_test_dtlbpr_X1$(EXEEXT) \
+ insn_test_fdouble_add_flags_X0$(EXEEXT) \
+ insn_test_fdouble_addsub_X0$(EXEEXT) \
+ insn_test_fdouble_mul_flags_X0$(EXEEXT) \
+ insn_test_fdouble_pack1_X0$(EXEEXT) \
+ insn_test_fdouble_pack2_X0$(EXEEXT) \
+ insn_test_fdouble_sub_flags_X0$(EXEEXT) \
+ insn_test_fdouble_unpack_max_X0$(EXEEXT) \
+ insn_test_fdouble_unpack_min_X0$(EXEEXT) \
+ insn_test_flushwb_X1$(EXEEXT) insn_test_fnop_X0$(EXEEXT) \
+ insn_test_fnop_X1$(EXEEXT) insn_test_fnop_Y0$(EXEEXT) \
+ insn_test_fnop_Y1$(EXEEXT) insn_test_fsingle_add1_X0$(EXEEXT) \
+ insn_test_fsingle_addsub2_X0$(EXEEXT) \
+ insn_test_fsingle_mul1_X0$(EXEEXT) \
+ insn_test_fsingle_mul2_X0$(EXEEXT) \
+ insn_test_fsingle_pack1_X0$(EXEEXT) \
+ insn_test_fsingle_pack1_Y0$(EXEEXT) \
+ insn_test_fsingle_pack2_X0$(EXEEXT) \
+ insn_test_fsingle_sub1_X0$(EXEEXT) insn_test_icoh_X1$(EXEEXT) \
+ insn_test_j_X1$(EXEEXT) insn_test_jal_X1$(EXEEXT) \
+ insn_test_jalr_X1$(EXEEXT) insn_test_jalr_Y1$(EXEEXT) \
+ insn_test_jalrp_X1$(EXEEXT) insn_test_jalrp_Y1$(EXEEXT) \
+ insn_test_jr_X1$(EXEEXT) insn_test_jr_Y1$(EXEEXT) \
+ insn_test_jrp_X1$(EXEEXT) insn_test_jrp_Y1$(EXEEXT) \
+ insn_test_ld_X1$(EXEEXT) insn_test_ld_Y2$(EXEEXT) \
+ insn_test_ld1s_X1$(EXEEXT) insn_test_ld1s_Y2$(EXEEXT) \
+ insn_test_ld1s_add_X1$(EXEEXT) insn_test_ld1u_X1$(EXEEXT) \
+ insn_test_ld1u_Y2$(EXEEXT) insn_test_ld1u_add_X1$(EXEEXT) \
+ insn_test_ld2s_X1$(EXEEXT) insn_test_ld2s_Y2$(EXEEXT) \
+ insn_test_ld2u_X1$(EXEEXT) insn_test_ld2u_Y2$(EXEEXT) \
+ insn_test_ld4s_X1$(EXEEXT) insn_test_ld4s_add_X1$(EXEEXT) \
+ insn_test_ld4u_X1$(EXEEXT) insn_test_ld4u_Y2$(EXEEXT) \
+ insn_test_ld4u_add_X1$(EXEEXT) insn_test_ld_add_X1$(EXEEXT) \
+ insn_test_ldna_X1$(EXEEXT) insn_test_ldna_add_X1$(EXEEXT) \
+ insn_test_ldnt_X1$(EXEEXT) insn_test_ldnt1s_X1$(EXEEXT) \
+ insn_test_ldnt1s_add_X1$(EXEEXT) insn_test_ldnt1u_X1$(EXEEXT) \
+ insn_test_ldnt1u_add_X1$(EXEEXT) insn_test_ldnt2s_X1$(EXEEXT) \
+ insn_test_ldnt2s_add_X1$(EXEEXT) \
+ insn_test_ldnt2u_add_X1$(EXEEXT) insn_test_ldnt4s_X1$(EXEEXT) \
+ insn_test_ldnt4s_add_X1$(EXEEXT) insn_test_ldnt4u_X1$(EXEEXT) \
+ insn_test_ldnt4u_add_X1$(EXEEXT) \
+ insn_test_ldnt_add_X1$(EXEEXT) insn_test_lnk_X1$(EXEEXT) \
+ insn_test_lnk_Y1$(EXEEXT) insn_test_mf_X1$(EXEEXT) \
+ insn_test_mm_X0$(EXEEXT) insn_test_mnz_X0$(EXEEXT) \
+ insn_test_mnz_X1$(EXEEXT) insn_test_mnz_Y0$(EXEEXT) \
+ insn_test_mnz_Y1$(EXEEXT) insn_test_mul_hs_hs_X0$(EXEEXT) \
+ insn_test_mul_hs_hs_Y0$(EXEEXT) \
+ insn_test_mul_hs_hu_X0$(EXEEXT) \
+ insn_test_mul_hs_ls_X0$(EXEEXT) \
+ insn_test_mul_hs_lu_X0$(EXEEXT) \
+ insn_test_mul_hu_hu_X0$(EXEEXT) \
+ insn_test_mul_hu_hu_Y0$(EXEEXT) \
+ insn_test_mul_hu_lu_X0$(EXEEXT) \
+ insn_test_mul_ls_ls_X0$(EXEEXT) \
+ insn_test_mul_ls_ls_Y0$(EXEEXT) \
+ insn_test_mul_ls_lu_X0$(EXEEXT) \
+ insn_test_mul_lu_lu_X0$(EXEEXT) \
+ insn_test_mul_lu_lu_Y0$(EXEEXT) \
+ insn_test_mula_hs_hs_X0$(EXEEXT) \
+ insn_test_mula_hs_hs_Y0$(EXEEXT) \
+ insn_test_mula_hs_hu_X0$(EXEEXT) \
+ insn_test_mula_hs_ls_X0$(EXEEXT) \
+ insn_test_mula_hs_lu_X0$(EXEEXT) \
+ insn_test_mula_hu_hu_X0$(EXEEXT) \
+ insn_test_mula_hu_hu_Y0$(EXEEXT) \
+ insn_test_mula_hu_ls_X0$(EXEEXT) \
+ insn_test_mula_hu_lu_X0$(EXEEXT) \
+ insn_test_mula_ls_ls_X0$(EXEEXT) \
+ insn_test_mula_ls_ls_Y0$(EXEEXT) \
+ insn_test_mula_ls_lu_X0$(EXEEXT) \
+ insn_test_mula_lu_lu_X0$(EXEEXT) \
+ insn_test_mula_lu_lu_Y0$(EXEEXT) insn_test_mulax_X0$(EXEEXT) \
+ insn_test_mulax_Y0$(EXEEXT) insn_test_mulx_X0$(EXEEXT) \
+ insn_test_mulx_Y0$(EXEEXT) insn_test_mz_X0$(EXEEXT) \
+ insn_test_mz_X1$(EXEEXT) insn_test_mz_Y0$(EXEEXT) \
+ insn_test_mz_Y1$(EXEEXT) insn_test_nop_X0$(EXEEXT) \
+ insn_test_nop_X1$(EXEEXT) insn_test_nop_Y0$(EXEEXT) \
+ insn_test_nop_Y1$(EXEEXT) insn_test_nor_X0$(EXEEXT) \
+ insn_test_nor_X1$(EXEEXT) insn_test_nor_Y0$(EXEEXT) \
+ insn_test_nor_Y1$(EXEEXT) insn_test_or_X0$(EXEEXT) \
+ insn_test_or_X1$(EXEEXT) insn_test_or_Y0$(EXEEXT) \
+ insn_test_or_Y1$(EXEEXT) insn_test_ori_X0$(EXEEXT) \
+ insn_test_ori_X1$(EXEEXT) insn_test_pcnt_X0$(EXEEXT) \
+ insn_test_pcnt_Y0$(EXEEXT) insn_test_revbits_X0$(EXEEXT) \
+ insn_test_revbits_Y0$(EXEEXT) insn_test_revbytes_X0$(EXEEXT) \
+ insn_test_revbytes_Y0$(EXEEXT) insn_test_rotl_X0$(EXEEXT) \
+ insn_test_rotl_X1$(EXEEXT) insn_test_rotl_Y0$(EXEEXT) \
+ insn_test_rotl_Y1$(EXEEXT) insn_test_rotli_X0$(EXEEXT) \
+ insn_test_rotli_X1$(EXEEXT) insn_test_rotli_Y0$(EXEEXT) \
+ insn_test_rotli_Y1$(EXEEXT) insn_test_shl_X0$(EXEEXT) \
+ insn_test_shl_X1$(EXEEXT) insn_test_shl_Y0$(EXEEXT) \
+ insn_test_shl_Y1$(EXEEXT) insn_test_shl16insli_X0$(EXEEXT) \
+ insn_test_shl16insli_X1$(EXEEXT) insn_test_shl1add_X0$(EXEEXT) \
+ insn_test_shl1add_X1$(EXEEXT) insn_test_shl1add_Y0$(EXEEXT) \
+ insn_test_shl1add_Y1$(EXEEXT) insn_test_shl1addx_X0$(EXEEXT) \
+ insn_test_shl1addx_X1$(EXEEXT) insn_test_shl1addx_Y0$(EXEEXT) \
+ insn_test_shl1addx_Y1$(EXEEXT) insn_test_shl2add_X0$(EXEEXT) \
+ insn_test_shl2add_X1$(EXEEXT) insn_test_shl2add_Y0$(EXEEXT) \
+ insn_test_shl2add_Y1$(EXEEXT) insn_test_shl2addx_X0$(EXEEXT) \
+ insn_test_shl2addx_X1$(EXEEXT) insn_test_shl2addx_Y0$(EXEEXT) \
+ insn_test_shl2addx_Y1$(EXEEXT) insn_test_shl3add_X0$(EXEEXT) \
+ insn_test_shl3add_X1$(EXEEXT) insn_test_shl3add_Y0$(EXEEXT) \
+ insn_test_shl3add_Y1$(EXEEXT) insn_test_shl3addx_X0$(EXEEXT) \
+ insn_test_shl3addx_X1$(EXEEXT) insn_test_shl3addx_Y0$(EXEEXT) \
+ insn_test_shl3addx_Y1$(EXEEXT) insn_test_shli_X0$(EXEEXT) \
+ insn_test_shli_X1$(EXEEXT) insn_test_shli_Y0$(EXEEXT) \
+ insn_test_shli_Y1$(EXEEXT) insn_test_shlx_X0$(EXEEXT) \
+ insn_test_shlx_X1$(EXEEXT) insn_test_shlxi_X0$(EXEEXT) \
+ insn_test_shlxi_X1$(EXEEXT) insn_test_shrs_X0$(EXEEXT) \
+ insn_test_shrs_X1$(EXEEXT) insn_test_shrs_Y0$(EXEEXT) \
+ insn_test_shrs_Y1$(EXEEXT) insn_test_shrsi_X0$(EXEEXT) \
+ insn_test_shrsi_X1$(EXEEXT) insn_test_shrsi_Y0$(EXEEXT) \
+ insn_test_shrsi_Y1$(EXEEXT) insn_test_shru_X0$(EXEEXT) \
+ insn_test_shru_X1$(EXEEXT) insn_test_shru_Y0$(EXEEXT) \
+ insn_test_shru_Y1$(EXEEXT) insn_test_shrui_X0$(EXEEXT) \
+ insn_test_shrui_X1$(EXEEXT) insn_test_shrui_Y0$(EXEEXT) \
+ insn_test_shrui_Y1$(EXEEXT) insn_test_shrux_X0$(EXEEXT) \
+ insn_test_shrux_X1$(EXEEXT) insn_test_shufflebytes_X0$(EXEEXT) \
+ insn_test_st_X1$(EXEEXT) insn_test_st_Y2$(EXEEXT) \
+ insn_test_st1_X1$(EXEEXT) insn_test_st1_Y2$(EXEEXT) \
+ insn_test_st1_add_X1$(EXEEXT) insn_test_st2_X1$(EXEEXT) \
+ insn_test_st2_Y2$(EXEEXT) insn_test_st2_add_X1$(EXEEXT) \
+ insn_test_st4_X1$(EXEEXT) insn_test_st4_Y2$(EXEEXT) \
+ insn_test_st4_add_X1$(EXEEXT) insn_test_st_add_X1$(EXEEXT) \
+ insn_test_stnt_X1$(EXEEXT) insn_test_stnt1_X1$(EXEEXT) \
+ insn_test_stnt2_X1$(EXEEXT) insn_test_stnt2_add_X1$(EXEEXT) \
+ insn_test_stnt4_X1$(EXEEXT) insn_test_stnt4_add_X1$(EXEEXT) \
+ insn_test_stnt_add_X1$(EXEEXT) insn_test_sub_X0$(EXEEXT) \
+ insn_test_sub_X1$(EXEEXT) insn_test_sub_Y0$(EXEEXT) \
+ insn_test_sub_Y1$(EXEEXT) insn_test_subx_X0$(EXEEXT) \
+ insn_test_subx_X1$(EXEEXT) insn_test_subx_Y0$(EXEEXT) \
+ insn_test_subx_Y1$(EXEEXT) insn_test_tblidxb0_X0$(EXEEXT) \
+ insn_test_tblidxb0_Y0$(EXEEXT) insn_test_tblidxb1_X0$(EXEEXT) \
+ insn_test_tblidxb1_Y0$(EXEEXT) insn_test_tblidxb2_X0$(EXEEXT) \
+ insn_test_tblidxb2_Y0$(EXEEXT) insn_test_tblidxb3_X0$(EXEEXT) \
+ insn_test_tblidxb3_Y0$(EXEEXT) insn_test_v1add_X0$(EXEEXT) \
+ insn_test_v1add_X1$(EXEEXT) insn_test_v1adduc_X0$(EXEEXT) \
+ insn_test_v1adduc_X1$(EXEEXT) insn_test_v1adiffu_X0$(EXEEXT) \
+ insn_test_v1avgu_X0$(EXEEXT) insn_test_v1cmpeq_X0$(EXEEXT) \
+ insn_test_v1cmpeq_X1$(EXEEXT) insn_test_v1cmpeqi_X0$(EXEEXT) \
+ insn_test_v1cmpeqi_X1$(EXEEXT) insn_test_v1cmples_X0$(EXEEXT) \
+ insn_test_v1cmples_X1$(EXEEXT) insn_test_v1cmpleu_X0$(EXEEXT) \
+ insn_test_v1cmpleu_X1$(EXEEXT) insn_test_v1cmplts_X0$(EXEEXT) \
+ insn_test_v1cmplts_X1$(EXEEXT) insn_test_v1cmpltu_X0$(EXEEXT) \
+ insn_test_v1cmpltu_X1$(EXEEXT) insn_test_v1cmpne_X0$(EXEEXT) \
+ insn_test_v1cmpne_X1$(EXEEXT) insn_test_v1ddotpu_X0$(EXEEXT) \
+ insn_test_v1ddotpua_X0$(EXEEXT) \
+ insn_test_v1ddotpus_X0$(EXEEXT) \
+ insn_test_v1ddotpusa_X0$(EXEEXT) insn_test_v1dotp_X0$(EXEEXT) \
+ insn_test_v1dotpa_X0$(EXEEXT) insn_test_v1dotpu_X0$(EXEEXT) \
+ insn_test_v1dotpua_X0$(EXEEXT) insn_test_v1dotpus_X0$(EXEEXT) \
+ insn_test_v1dotpusa_X0$(EXEEXT) insn_test_v1int_h_X0$(EXEEXT) \
+ insn_test_v1int_h_X1$(EXEEXT) insn_test_v1int_l_X0$(EXEEXT) \
+ insn_test_v1int_l_X1$(EXEEXT) insn_test_v1maxu_X0$(EXEEXT) \
+ insn_test_v1maxu_X1$(EXEEXT) insn_test_v1minu_X0$(EXEEXT) \
+ insn_test_v1minu_X1$(EXEEXT) insn_test_v1mnz_X0$(EXEEXT) \
+ insn_test_v1mnz_X1$(EXEEXT) insn_test_v1multu_X0$(EXEEXT) \
+ insn_test_v1mulu_X0$(EXEEXT) insn_test_v1mulus_X0$(EXEEXT) \
+ insn_test_v1mz_X0$(EXEEXT) insn_test_v1mz_X1$(EXEEXT) \
+ insn_test_v1sadau_X0$(EXEEXT) insn_test_v1sadu_X0$(EXEEXT) \
+ insn_test_v1shl_X0$(EXEEXT) insn_test_v1shl_X1$(EXEEXT) \
+ insn_test_v1shli_X0$(EXEEXT) insn_test_v1shli_X1$(EXEEXT) \
+ insn_test_v1shrs_X0$(EXEEXT) insn_test_v1shrs_X1$(EXEEXT) \
+ insn_test_v1shrsi_X0$(EXEEXT) insn_test_v1shrsi_X1$(EXEEXT) \
+ insn_test_v1shru_X0$(EXEEXT) insn_test_v1shru_X1$(EXEEXT) \
+ insn_test_v1shrui_X0$(EXEEXT) insn_test_v1shrui_X1$(EXEEXT) \
+ insn_test_v1sub_X0$(EXEEXT) insn_test_v1sub_X1$(EXEEXT) \
+ insn_test_v1subuc_X0$(EXEEXT) insn_test_v1subuc_X1$(EXEEXT) \
+ insn_test_v2add_X0$(EXEEXT) insn_test_v2add_X1$(EXEEXT) \
+ insn_test_v2addsc_X0$(EXEEXT) insn_test_v2addsc_X1$(EXEEXT) \
+ insn_test_v2adiffs_X0$(EXEEXT) insn_test_v2avgs_X0$(EXEEXT) \
+ insn_test_v2cmpeq_X0$(EXEEXT) insn_test_v2cmpeq_X1$(EXEEXT) \
+ insn_test_v2cmpeqi_X0$(EXEEXT) insn_test_v2cmpeqi_X1$(EXEEXT) \
+ insn_test_v2cmples_X0$(EXEEXT) insn_test_v2cmples_X1$(EXEEXT) \
+ insn_test_v2cmpleu_X0$(EXEEXT) insn_test_v2cmpleu_X1$(EXEEXT) \
+ insn_test_v2cmplts_X0$(EXEEXT) insn_test_v2cmplts_X1$(EXEEXT) \
+ insn_test_v2cmpltsi_X0$(EXEEXT) \
+ insn_test_v2cmpltsi_X1$(EXEEXT) insn_test_v2cmpltu_X0$(EXEEXT) \
+ insn_test_v2cmpltu_X1$(EXEEXT) insn_test_v2cmpltui_X0$(EXEEXT) \
+ insn_test_v2cmpltui_X1$(EXEEXT) insn_test_v2cmpne_X0$(EXEEXT) \
+ insn_test_v2cmpne_X1$(EXEEXT) insn_test_v2dotp_X0$(EXEEXT) \
+ insn_test_v2dotpa_X0$(EXEEXT) insn_test_v2int_h_X0$(EXEEXT) \
+ insn_test_v2int_h_X1$(EXEEXT) insn_test_v2int_l_X0$(EXEEXT) \
+ insn_test_v2int_l_X1$(EXEEXT) insn_test_v2maxs_X0$(EXEEXT) \
+ insn_test_v2maxs_X1$(EXEEXT) insn_test_v2mins_X0$(EXEEXT) \
+ insn_test_v2mins_X1$(EXEEXT) insn_test_v2mnz_X0$(EXEEXT) \
+ insn_test_v2mnz_X1$(EXEEXT) insn_test_v2mulfsc_X0$(EXEEXT) \
+ insn_test_v2muls_X0$(EXEEXT) insn_test_v2mults_X0$(EXEEXT) \
+ insn_test_v2mz_X0$(EXEEXT) insn_test_v2mz_X1$(EXEEXT) \
+ insn_test_v2packh_X0$(EXEEXT) insn_test_v2packh_X1$(EXEEXT) \
+ insn_test_v2packl_X0$(EXEEXT) insn_test_v2packl_X1$(EXEEXT) \
+ insn_test_v2packuc_X0$(EXEEXT) insn_test_v2packuc_X1$(EXEEXT) \
+ insn_test_v2sadas_X0$(EXEEXT) insn_test_v2sadau_X0$(EXEEXT) \
+ insn_test_v2sads_X0$(EXEEXT) insn_test_v2sadu_X0$(EXEEXT) \
+ insn_test_v2shl_X0$(EXEEXT) insn_test_v2shl_X1$(EXEEXT) \
+ insn_test_v2shli_X0$(EXEEXT) insn_test_v2shli_X1$(EXEEXT) \
+ insn_test_v2shlsc_X0$(EXEEXT) insn_test_v2shlsc_X1$(EXEEXT) \
+ insn_test_v2shrs_X0$(EXEEXT) insn_test_v2shrs_X1$(EXEEXT) \
+ insn_test_v2shrsi_X0$(EXEEXT) insn_test_v2shrsi_X1$(EXEEXT) \
+ insn_test_v2shru_X0$(EXEEXT) insn_test_v2shru_X1$(EXEEXT) \
+ insn_test_v2shrui_X0$(EXEEXT) insn_test_v2shrui_X1$(EXEEXT) \
+ insn_test_v2sub_X0$(EXEEXT) insn_test_v2sub_X1$(EXEEXT) \
+ insn_test_v2subsc_X0$(EXEEXT) insn_test_v2subsc_X1$(EXEEXT) \
+ insn_test_v4add_X0$(EXEEXT) insn_test_v4add_X1$(EXEEXT) \
+ insn_test_v4addsc_X0$(EXEEXT) insn_test_v4addsc_X1$(EXEEXT) \
+ insn_test_v4int_h_X0$(EXEEXT) insn_test_v4int_h_X1$(EXEEXT) \
+ insn_test_v4int_l_X0$(EXEEXT) insn_test_v4int_l_X1$(EXEEXT) \
+ insn_test_v4packsc_X0$(EXEEXT) insn_test_v4packsc_X1$(EXEEXT) \
+ insn_test_v4shl_X0$(EXEEXT) insn_test_v4shl_X1$(EXEEXT) \
+ insn_test_v4shlsc_X0$(EXEEXT) insn_test_v4shlsc_X1$(EXEEXT) \
+ insn_test_v4shrs_X0$(EXEEXT) insn_test_v4shrs_X1$(EXEEXT) \
+ insn_test_v4shru_X0$(EXEEXT) insn_test_v4shru_X1$(EXEEXT) \
+ insn_test_v4sub_X0$(EXEEXT) insn_test_v4sub_X1$(EXEEXT) \
+ insn_test_v4subsc_X0$(EXEEXT) insn_test_v4subsc_X1$(EXEEXT) \
+ insn_test_wh64_X1$(EXEEXT) insn_test_xor_X0$(EXEEXT) \
+ insn_test_xor_X1$(EXEEXT) insn_test_xor_Y0$(EXEEXT) \
+ insn_test_xor_Y1$(EXEEXT) insn_test_xori_X0$(EXEEXT) \
+ insn_test_xori_X1$(EXEEXT)
+PROGRAMS = $(bin_PROGRAMS)
+allexec_SOURCES = allexec.c
+allexec_OBJECTS = allexec-allexec.$(OBJEXT)
+allexec_LDADD = $(LDADD)
+allexec_LINK = $(CCLD) $(allexec_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+gen_insn_test_SOURCES = gen_insn_test.c
+gen_insn_test_OBJECTS = gen_insn_test-gen_insn_test.$(OBJEXT)
+gen_insn_test_DEPENDENCIES = ../../../VEX/priv/tilegx_disasm.o
+gen_insn_test_LINK = $(CCLD) $(gen_insn_test_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+insn_test_add_X0_SOURCES = insn_test_add_X0.c
+insn_test_add_X0_OBJECTS = insn_test_add_X0.$(OBJEXT)
+insn_test_add_X0_LDADD = $(LDADD)
+insn_test_add_X1_SOURCES = insn_test_add_X1.c
+insn_test_add_X1_OBJECTS = insn_test_add_X1.$(OBJEXT)
+insn_test_add_X1_LDADD = $(LDADD)
+insn_test_add_Y0_SOURCES = insn_test_add_Y0.c
+insn_test_add_Y0_OBJECTS = insn_test_add_Y0.$(OBJEXT)
+insn_test_add_Y0_LDADD = $(LDADD)
+insn_test_add_Y1_SOURCES = insn_test_add_Y1.c
+insn_test_add_Y1_OBJECTS = insn_test_add_Y1.$(OBJEXT)
+insn_test_add_Y1_LDADD = $(LDADD)
+insn_test_addi_X0_SOURCES = insn_test_addi_X0.c
+insn_test_addi_X0_OBJECTS = insn_test_addi_X0.$(OBJEXT)
+insn_test_addi_X0_LDADD = $(LDADD)
+insn_test_addi_X1_SOURCES = insn_test_addi_X1.c
+insn_test_addi_X1_OBJECTS = insn_test_addi_X1.$(OBJEXT)
+insn_test_addi_X1_LDADD = $(LDADD)
+insn_test_addi_Y0_SOURCES = insn_test_addi_Y0.c
+insn_test_addi_Y0_OBJECTS = insn_test_addi_Y0.$(OBJEXT)
+insn_test_addi_Y0_LDADD = $(LDADD)
+insn_test_addi_Y1_SOURCES = insn_test_addi_Y1.c
+insn_test_addi_Y1_OBJECTS = insn_test_addi_Y1.$(OBJEXT)
+insn_test_addi_Y1_LDADD = $(LDADD)
+insn_test_addli_X0_SOURCES = insn_test_addli_X0.c
+insn_test_addli_X0_OBJECTS = insn_test_addli_X0.$(OBJEXT)
+insn_test_addli_X0_LDADD = $(LDADD)
+insn_test_addli_X1_SOURCES = insn_test_addli_X1.c
+insn_test_addli_X1_OBJECTS = insn_test_addli_X1.$(OBJEXT)
+insn_test_addli_X1_LDADD = $(LDADD)
+insn_test_addx_X0_SOURCES = insn_test_addx_X0.c
+insn_test_addx_X0_OBJECTS = insn_test_addx_X0.$(OBJEXT)
+insn_test_addx_X0_LDADD = $(LDADD)
+insn_test_addx_X1_SOURCES = insn_test_addx_X1.c
+insn_test_addx_X1_OBJECTS = insn_test_addx_X1.$(OBJEXT)
+insn_test_addx_X1_LDADD = $(LDADD)
+insn_test_addx_Y0_SOURCES = insn_test_addx_Y0.c
+insn_test_addx_Y0_OBJECTS = insn_test_addx_Y0.$(OBJEXT)
+insn_test_addx_Y0_LDADD = $(LDADD)
+insn_test_addx_Y1_SOURCES = insn_test_addx_Y1.c
+insn_test_addx_Y1_OBJECTS = insn_test_addx_Y1.$(OBJEXT)
+insn_test_addx_Y1_LDADD = $(LDADD)
+insn_test_addxi_X0_SOURCES = insn_test_addxi_X0.c
+insn_test_addxi_X0_OBJECTS = insn_test_addxi_X0.$(OBJEXT)
+insn_test_addxi_X0_LDADD = $(LDADD)
+insn_test_addxi_X1_SOURCES = insn_test_addxi_X1.c
+insn_test_addxi_X1_OBJECTS = insn_test_addxi_X1.$(OBJEXT)
+insn_test_addxi_X1_LDADD = $(LDADD)
+insn_test_addxi_Y0_SOURCES = insn_test_addxi_Y0.c
+insn_test_addxi_Y0_OBJECTS = insn_test_addxi_Y0.$(OBJEXT)
+insn_test_addxi_Y0_LDADD = $(LDADD)
+insn_test_addxi_Y1_SOURCES = insn_test_addxi_Y1.c
+insn_test_addxi_Y1_OBJECTS = insn_test_addxi_Y1.$(OBJEXT)
+insn_test_addxi_Y1_LDADD = $(LDADD)
+insn_test_addxli_X0_SOURCES = insn_test_addxli_X0.c
+insn_test_addxli_X0_OBJECTS = insn_test_addxli_X0.$(OBJEXT)
+insn_test_addxli_X0_LDADD = $(LDADD)
+insn_test_addxli_X1_SOURCES = insn_test_addxli_X1.c
+insn_test_addxli_X1_OBJECTS = insn_test_addxli_X1.$(OBJEXT)
+insn_test_addxli_X1_LDADD = $(LDADD)
+insn_test_addxsc_X0_SOURCES = insn_test_addxsc_X0.c
+insn_test_addxsc_X0_OBJECTS = insn_test_addxsc_X0.$(OBJEXT)
+insn_test_addxsc_X0_LDADD = $(LDADD)
+insn_test_addxsc_X1_SOURCES = insn_test_addxsc_X1.c
+insn_test_addxsc_X1_OBJECTS = insn_test_addxsc_X1.$(OBJEXT)
+insn_test_addxsc_X1_LDADD = $(LDADD)
+insn_test_and_X0_SOURCES = insn_test_and_X0.c
+insn_test_and_X0_OBJECTS = insn_test_and_X0.$(OBJEXT)
+insn_test_and_X0_LDADD = $(LDADD)
+insn_test_and_X1_SOURCES = insn_test_and_X1.c
+insn_test_and_X1_OBJECTS = insn_test_and_X1.$(OBJEXT)
+insn_test_and_X1_LDADD = $(LDADD)
+insn_test_and_Y0_SOURCES = insn_test_and_Y0.c
+insn_test_and_Y0_OBJECTS = insn_test_and_Y0.$(OBJEXT)
+insn_test_and_Y0_LDADD = $(LDADD)
+insn_test_and_Y1_SOURCES = insn_test_and_Y1.c
+insn_test_and_Y1_OBJECTS = insn_test_and_Y1.$(OBJEXT)
+insn_test_and_Y1_LDADD = $(LDADD)
+insn_test_andi_X0_SOURCES = insn_test_andi_X0.c
+insn_test_andi_X0_OBJECTS = insn_test_andi_X0.$(OBJEXT)
+insn_test_andi_X0_LDADD = $(LDADD)
+insn_test_andi_X1_SOURCES = insn_test_andi_X1.c
+insn_test_andi_X1_OBJECTS = insn_test_andi_X1.$(OBJEXT)
+insn_test_andi_X1_LDADD = $(LDADD)
+insn_test_andi_Y0_SOURCES = insn_test_andi_Y0.c
+insn_test_andi_Y0_OBJECTS = insn_test_andi_Y0.$(OBJEXT)
+insn_test_andi_Y0_LDADD = $(LDADD)
+insn_test_andi_Y1_SOURCES = insn_test_andi_Y1.c
+insn_test_andi_Y1_OBJECTS = insn_test_andi_Y1.$(OBJEXT)
+insn_test_andi_Y1_LDADD = $(LDADD)
+insn_test_beqz_X1_SOURCES = insn_test_beqz_X1.c
+insn_test_beqz_X1_OBJECTS = insn_test_beqz_X1.$(OBJEXT)
+insn_test_beqz_X1_LDADD = $(LDADD)
+insn_test_beqzt_X1_SOURCES = insn_test_beqzt_X1.c
+insn_test_beqzt_X1_OBJECTS = insn_test_beqzt_X1.$(OBJEXT)
+insn_test_beqzt_X1_LDADD = $(LDADD)
+insn_test_bfexts_X0_SOURCES = insn_test_bfexts_X0.c
+insn_test_bfexts_X0_OBJECTS = insn_test_bfexts_X0.$(OBJEXT)
+insn_test_bfexts_X0_LDADD = $(LDADD)
+insn_test_bfextu_X0_SOURCES = insn_test_bfextu_X0.c
+insn_test_bfextu_X0_OBJECTS = insn_test_bfextu_X0.$(OBJEXT)
+insn_test_bfextu_X0_LDADD = $(LDADD)
+insn_test_bfins_X0_SOURCES = insn_test_bfins_X0.c
+insn_test_bfins_X0_OBJECTS = insn_test_bfins_X0.$(OBJEXT)
+insn_test_bfins_X0_LDADD = $(LDADD)
+insn_test_bgez_X1_SOURCES = insn_test_bgez_X1.c
+insn_test_bgez_X1_OBJECTS = insn_test_bgez_X1.$(OBJEXT)
+insn_test_bgez_X1_LDADD = $(LDADD)
+insn_test_bgezt_X1_SOURCES = insn_test_bgezt_X1.c
+insn_test_bgezt_X1_OBJECTS = insn_test_bgezt_X1.$(OBJEXT)
+insn_test_bgezt_X1_LDADD = $(LDADD)
+insn_test_bgtz_X1_SOURCES = insn_test_bgtz_X1.c
+insn_test_bgtz_X1_OBJECTS = insn_test_bgtz_X1.$(OBJEXT)
+insn_test_bgtz_X1_LDADD = $(LDADD)
+insn_test_bgtzt_X1_SOURCES = insn_test_bgtzt_X1.c
+insn_test_bgtzt_X1_OBJECTS = insn_test_bgtzt_X1.$(OBJEXT)
+insn_test_bgtzt_X1_LDADD = $(LDADD)
+insn_test_blbc_X1_SOURCES = insn_test_blbc_X1.c
+insn_test_blbc_X1_OBJECTS = insn_test_blbc_X1.$(OBJEXT)
+insn_test_blbc_X1_LDADD = $(LDADD)
+insn_test_blbct_X1_SOURCES = insn_test_blbct_X1.c
+insn_test_blbct_X1_OBJECTS = insn_test_blbct_X1.$(OBJEXT)
+insn_test_blbct_X1_LDADD = $(LDADD)
+insn_test_blbs_X1_SOURCES = insn_test_blbs_X1.c
+insn_test_blbs_X1_OBJECTS = insn_test_blbs_X1.$(OBJEXT)
+insn_test_blbs_X1_LDADD = $(LDADD)
+insn_test_blbst_X1_SOURCES = insn_test_blbst_X1.c
+insn_test_blbst_X1_OBJECTS = insn_test_blbst_X1.$(OBJEXT)
+insn_test_blbst_X1_LDADD = $(LDADD)
+insn_test_blez_X1_SOURCES = insn_test_blez_X1.c
+insn_test_blez_X1_OBJECTS = insn_test_blez_X1.$(OBJEXT)
+insn_test_blez_X1_LDADD = $(LDADD)
+insn_test_blezt_X1_SOURCES = insn_test_blezt_X1.c
+insn_test_blezt_X1_OBJECTS = insn_test_blezt_X1.$(OBJEXT)
+insn_test_blezt_X1_LDADD = $(LDADD)
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+insn_test_bltz_X1_OBJECTS = insn_test_bltz_X1.$(OBJEXT)
+insn_test_bltz_X1_LDADD = $(LDADD)
+insn_test_bltzt_X1_SOURCES = insn_test_bltzt_X1.c
+insn_test_bltzt_X1_OBJECTS = insn_test_bltzt_X1.$(OBJEXT)
+insn_test_bltzt_X1_LDADD = $(LDADD)
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+insn_test_bnez_X1_OBJECTS = insn_test_bnez_X1.$(OBJEXT)
+insn_test_bnez_X1_LDADD = $(LDADD)
+insn_test_bnezt_X1_SOURCES = insn_test_bnezt_X1.c
+insn_test_bnezt_X1_OBJECTS = insn_test_bnezt_X1.$(OBJEXT)
+insn_test_bnezt_X1_LDADD = $(LDADD)
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+insn_test_clz_X0_OBJECTS = insn_test_clz_X0.$(OBJEXT)
+insn_test_clz_X0_LDADD = $(LDADD)
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+insn_test_clz_Y0_OBJECTS = insn_test_clz_Y0.$(OBJEXT)
+insn_test_clz_Y0_LDADD = $(LDADD)
+insn_test_cmoveqz_X0_SOURCES = insn_test_cmoveqz_X0.c
+insn_test_cmoveqz_X0_OBJECTS = insn_test_cmoveqz_X0.$(OBJEXT)
+insn_test_cmoveqz_X0_LDADD = $(LDADD)
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+insn_test_cmoveqz_Y0_OBJECTS = insn_test_cmoveqz_Y0.$(OBJEXT)
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+insn_test_cmovnez_X0_OBJECTS = insn_test_cmovnez_X0.$(OBJEXT)
+insn_test_cmovnez_X0_LDADD = $(LDADD)
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+insn_test_cmovnez_Y0_OBJECTS = insn_test_cmovnez_Y0.$(OBJEXT)
+insn_test_cmovnez_Y0_LDADD = $(LDADD)
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+insn_test_cmpeq_X0_OBJECTS = insn_test_cmpeq_X0.$(OBJEXT)
+insn_test_cmpeq_X0_LDADD = $(LDADD)
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+insn_test_cmpeq_X1_OBJECTS = insn_test_cmpeq_X1.$(OBJEXT)
+insn_test_cmpeq_X1_LDADD = $(LDADD)
+insn_test_cmpeq_Y0_SOURCES = insn_test_cmpeq_Y0.c
+insn_test_cmpeq_Y0_OBJECTS = insn_test_cmpeq_Y0.$(OBJEXT)
+insn_test_cmpeq_Y0_LDADD = $(LDADD)
+insn_test_cmpeq_Y1_SOURCES = insn_test_cmpeq_Y1.c
+insn_test_cmpeq_Y1_OBJECTS = insn_test_cmpeq_Y1.$(OBJEXT)
+insn_test_cmpeq_Y1_LDADD = $(LDADD)
+insn_test_cmpeqi_X0_SOURCES = insn_test_cmpeqi_X0.c
+insn_test_cmpeqi_X0_OBJECTS = insn_test_cmpeqi_X0.$(OBJEXT)
+insn_test_cmpeqi_X0_LDADD = $(LDADD)
+insn_test_cmpeqi_X1_SOURCES = insn_test_cmpeqi_X1.c
+insn_test_cmpeqi_X1_OBJECTS = insn_test_cmpeqi_X1.$(OBJEXT)
+insn_test_cmpeqi_X1_LDADD = $(LDADD)
+insn_test_cmpeqi_Y0_SOURCES = insn_test_cmpeqi_Y0.c
+insn_test_cmpeqi_Y0_OBJECTS = insn_test_cmpeqi_Y0.$(OBJEXT)
+insn_test_cmpeqi_Y0_LDADD = $(LDADD)
+insn_test_cmpeqi_Y1_SOURCES = insn_test_cmpeqi_Y1.c
+insn_test_cmpeqi_Y1_OBJECTS = insn_test_cmpeqi_Y1.$(OBJEXT)
+insn_test_cmpeqi_Y1_LDADD = $(LDADD)
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+insn_test_cmples_X0_OBJECTS = insn_test_cmples_X0.$(OBJEXT)
+insn_test_cmples_X0_LDADD = $(LDADD)
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+insn_test_cmples_X1_OBJECTS = insn_test_cmples_X1.$(OBJEXT)
+insn_test_cmples_X1_LDADD = $(LDADD)
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+insn_test_cmples_Y0_OBJECTS = insn_test_cmples_Y0.$(OBJEXT)
+insn_test_cmples_Y0_LDADD = $(LDADD)
+insn_test_cmples_Y1_SOURCES = insn_test_cmples_Y1.c
+insn_test_cmples_Y1_OBJECTS = insn_test_cmples_Y1.$(OBJEXT)
+insn_test_cmples_Y1_LDADD = $(LDADD)
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+insn_test_cmpleu_X0_OBJECTS = insn_test_cmpleu_X0.$(OBJEXT)
+insn_test_cmpleu_X0_LDADD = $(LDADD)
+insn_test_cmpleu_X1_SOURCES = insn_test_cmpleu_X1.c
+insn_test_cmpleu_X1_OBJECTS = insn_test_cmpleu_X1.$(OBJEXT)
+insn_test_cmpleu_X1_LDADD = $(LDADD)
+insn_test_cmpleu_Y0_SOURCES = insn_test_cmpleu_Y0.c
+insn_test_cmpleu_Y0_OBJECTS = insn_test_cmpleu_Y0.$(OBJEXT)
+insn_test_cmpleu_Y0_LDADD = $(LDADD)
+insn_test_cmpleu_Y1_SOURCES = insn_test_cmpleu_Y1.c
+insn_test_cmpleu_Y1_OBJECTS = insn_test_cmpleu_Y1.$(OBJEXT)
+insn_test_cmpleu_Y1_LDADD = $(LDADD)
+insn_test_cmplts_X0_SOURCES = insn_test_cmplts_X0.c
+insn_test_cmplts_X0_OBJECTS = insn_test_cmplts_X0.$(OBJEXT)
+insn_test_cmplts_X0_LDADD = $(LDADD)
+insn_test_cmplts_X1_SOURCES = insn_test_cmplts_X1.c
+insn_test_cmplts_X1_OBJECTS = insn_test_cmplts_X1.$(OBJEXT)
+insn_test_cmplts_X1_LDADD = $(LDADD)
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+insn_test_cmplts_Y0_OBJECTS = insn_test_cmplts_Y0.$(OBJEXT)
+insn_test_cmplts_Y0_LDADD = $(LDADD)
+insn_test_cmplts_Y1_SOURCES = insn_test_cmplts_Y1.c
+insn_test_cmplts_Y1_OBJECTS = insn_test_cmplts_Y1.$(OBJEXT)
+insn_test_cmplts_Y1_LDADD = $(LDADD)
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+insn_test_cmpltsi_X0_OBJECTS = insn_test_cmpltsi_X0.$(OBJEXT)
+insn_test_cmpltsi_X0_LDADD = $(LDADD)
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+insn_test_cmpltsi_X1_OBJECTS = insn_test_cmpltsi_X1.$(OBJEXT)
+insn_test_cmpltsi_X1_LDADD = $(LDADD)
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+insn_test_cmpltsi_Y0_OBJECTS = insn_test_cmpltsi_Y0.$(OBJEXT)
+insn_test_cmpltsi_Y0_LDADD = $(LDADD)
+insn_test_cmpltsi_Y1_SOURCES = insn_test_cmpltsi_Y1.c
+insn_test_cmpltsi_Y1_OBJECTS = insn_test_cmpltsi_Y1.$(OBJEXT)
+insn_test_cmpltsi_Y1_LDADD = $(LDADD)
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+insn_test_cmpltu_X0_OBJECTS = insn_test_cmpltu_X0.$(OBJEXT)
+insn_test_cmpltu_X0_LDADD = $(LDADD)
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+insn_test_cmpltu_X1_OBJECTS = insn_test_cmpltu_X1.$(OBJEXT)
+insn_test_cmpltu_X1_LDADD = $(LDADD)
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+insn_test_cmpltu_Y0_OBJECTS = insn_test_cmpltu_Y0.$(OBJEXT)
+insn_test_cmpltu_Y0_LDADD = $(LDADD)
+insn_test_cmpltu_Y1_SOURCES = insn_test_cmpltu_Y1.c
+insn_test_cmpltu_Y1_OBJECTS = insn_test_cmpltu_Y1.$(OBJEXT)
+insn_test_cmpltu_Y1_LDADD = $(LDADD)
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+insn_test_cmpltui_X0_OBJECTS = insn_test_cmpltui_X0.$(OBJEXT)
+insn_test_cmpltui_X0_LDADD = $(LDADD)
+insn_test_cmpltui_X1_SOURCES = insn_test_cmpltui_X1.c
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+insn_test_cmpltui_X1_LDADD = $(LDADD)
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+insn_test_cmpne_X0_OBJECTS = insn_test_cmpne_X0.$(OBJEXT)
+insn_test_cmpne_X0_LDADD = $(LDADD)
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+insn_test_cmpne_X1_OBJECTS = insn_test_cmpne_X1.$(OBJEXT)
+insn_test_cmpne_X1_LDADD = $(LDADD)
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+insn_test_cmpne_Y0_OBJECTS = insn_test_cmpne_Y0.$(OBJEXT)
+insn_test_cmpne_Y0_LDADD = $(LDADD)
+insn_test_cmpne_Y1_SOURCES = insn_test_cmpne_Y1.c
+insn_test_cmpne_Y1_OBJECTS = insn_test_cmpne_Y1.$(OBJEXT)
+insn_test_cmpne_Y1_LDADD = $(LDADD)
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+insn_test_cmul_X0_OBJECTS = insn_test_cmul_X0.$(OBJEXT)
+insn_test_cmul_X0_LDADD = $(LDADD)
+insn_test_cmula_X0_SOURCES = insn_test_cmula_X0.c
+insn_test_cmula_X0_OBJECTS = insn_test_cmula_X0.$(OBJEXT)
+insn_test_cmula_X0_LDADD = $(LDADD)
+insn_test_cmulaf_X0_SOURCES = insn_test_cmulaf_X0.c
+insn_test_cmulaf_X0_OBJECTS = insn_test_cmulaf_X0.$(OBJEXT)
+insn_test_cmulaf_X0_LDADD = $(LDADD)
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+insn_test_cmulf_X0_OBJECTS = insn_test_cmulf_X0.$(OBJEXT)
+insn_test_cmulf_X0_LDADD = $(LDADD)
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+insn_test_cmulfr_X0_OBJECTS = insn_test_cmulfr_X0.$(OBJEXT)
+insn_test_cmulfr_X0_LDADD = $(LDADD)
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+insn_test_cmulh_X0_OBJECTS = insn_test_cmulh_X0.$(OBJEXT)
+insn_test_cmulh_X0_LDADD = $(LDADD)
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+insn_test_cmulhr_X0_OBJECTS = insn_test_cmulhr_X0.$(OBJEXT)
+insn_test_cmulhr_X0_LDADD = $(LDADD)
+insn_test_crc32_32_X0_SOURCES = insn_test_crc32_32_X0.c
+insn_test_crc32_32_X0_OBJECTS = insn_test_crc32_32_X0.$(OBJEXT)
+insn_test_crc32_32_X0_LDADD = $(LDADD)
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+insn_test_crc32_8_X0_OBJECTS = insn_test_crc32_8_X0.$(OBJEXT)
+insn_test_crc32_8_X0_LDADD = $(LDADD)
+insn_test_ctz_X0_SOURCES = insn_test_ctz_X0.c
+insn_test_ctz_X0_OBJECTS = insn_test_ctz_X0.$(OBJEXT)
+insn_test_ctz_X0_LDADD = $(LDADD)
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+insn_test_ctz_Y0_OBJECTS = insn_test_ctz_Y0.$(OBJEXT)
+insn_test_ctz_Y0_LDADD = $(LDADD)
+insn_test_dblalign2_X0_SOURCES = insn_test_dblalign2_X0.c
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+insn_test_dblalign2_X0_LDADD = $(LDADD)
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+insn_test_dblalign2_X1_OBJECTS = insn_test_dblalign2_X1.$(OBJEXT)
+insn_test_dblalign2_X1_LDADD = $(LDADD)
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+insn_test_dblalign4_X0_LDADD = $(LDADD)
+insn_test_dblalign4_X1_SOURCES = insn_test_dblalign4_X1.c
+insn_test_dblalign4_X1_OBJECTS = insn_test_dblalign4_X1.$(OBJEXT)
+insn_test_dblalign4_X1_LDADD = $(LDADD)
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+insn_test_dblalign6_X0_LDADD = $(LDADD)
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+insn_test_dblalign6_X1_LDADD = $(LDADD)
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+insn_test_dblalign_X0_OBJECTS = insn_test_dblalign_X0.$(OBJEXT)
+insn_test_dblalign_X0_LDADD = $(LDADD)
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+insn_test_dtlbpr_X1_OBJECTS = insn_test_dtlbpr_X1.$(OBJEXT)
+insn_test_dtlbpr_X1_LDADD = $(LDADD)
+insn_test_fdouble_add_flags_X0_SOURCES = \
+ insn_test_fdouble_add_flags_X0.c
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+ insn_test_fdouble_add_flags_X0.$(OBJEXT)
+insn_test_fdouble_add_flags_X0_LDADD = $(LDADD)
+insn_test_fdouble_addsub_X0_SOURCES = insn_test_fdouble_addsub_X0.c
+insn_test_fdouble_addsub_X0_OBJECTS = \
+ insn_test_fdouble_addsub_X0.$(OBJEXT)
+insn_test_fdouble_addsub_X0_LDADD = $(LDADD)
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+ insn_test_fdouble_mul_flags_X0.c
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+ insn_test_fdouble_mul_flags_X0.$(OBJEXT)
+insn_test_fdouble_mul_flags_X0_LDADD = $(LDADD)
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+insn_test_fdouble_pack1_X0_OBJECTS = \
+ insn_test_fdouble_pack1_X0.$(OBJEXT)
+insn_test_fdouble_pack1_X0_LDADD = $(LDADD)
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+insn_test_fdouble_pack2_X0_OBJECTS = \
+ insn_test_fdouble_pack2_X0.$(OBJEXT)
+insn_test_fdouble_pack2_X0_LDADD = $(LDADD)
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+ insn_test_fdouble_sub_flags_X0.c
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+ insn_test_fdouble_sub_flags_X0.$(OBJEXT)
+insn_test_fdouble_sub_flags_X0_LDADD = $(LDADD)
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+ insn_test_fdouble_unpack_max_X0.c
+insn_test_fdouble_unpack_max_X0_OBJECTS = \
+ insn_test_fdouble_unpack_max_X0.$(OBJEXT)
+insn_test_fdouble_unpack_max_X0_LDADD = $(LDADD)
+insn_test_fdouble_unpack_min_X0_SOURCES = \
+ insn_test_fdouble_unpack_min_X0.c
+insn_test_fdouble_unpack_min_X0_OBJECTS = \
+ insn_test_fdouble_unpack_min_X0.$(OBJEXT)
+insn_test_fdouble_unpack_min_X0_LDADD = $(LDADD)
+insn_test_flushwb_X1_SOURCES = insn_test_flushwb_X1.c
+insn_test_flushwb_X1_OBJECTS = insn_test_flushwb_X1.$(OBJEXT)
+insn_test_flushwb_X1_LDADD = $(LDADD)
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+insn_test_fnop_X1_OBJECTS = insn_test_fnop_X1.$(OBJEXT)
+insn_test_fnop_X1_LDADD = $(LDADD)
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+insn_test_fnop_Y0_OBJECTS = insn_test_fnop_Y0.$(OBJEXT)
+insn_test_fnop_Y0_LDADD = $(LDADD)
+insn_test_fnop_Y1_SOURCES = insn_test_fnop_Y1.c
+insn_test_fnop_Y1_OBJECTS = insn_test_fnop_Y1.$(OBJEXT)
+insn_test_fnop_Y1_LDADD = $(LDADD)
+insn_test_fsingle_add1_X0_SOURCES = insn_test_fsingle_add1_X0.c
+insn_test_fsingle_add1_X0_OBJECTS = \
+ insn_test_fsingle_add1_X0.$(OBJEXT)
+insn_test_fsingle_add1_X0_LDADD = $(LDADD)
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+insn_test_fsingle_addsub2_X0_OBJECTS = \
+ insn_test_fsingle_addsub2_X0.$(OBJEXT)
+insn_test_fsingle_addsub2_X0_LDADD = $(LDADD)
+insn_test_fsingle_mul1_X0_SOURCES = insn_test_fsingle_mul1_X0.c
+insn_test_fsingle_mul1_X0_OBJECTS = \
+ insn_test_fsingle_mul1_X0.$(OBJEXT)
+insn_test_fsingle_mul1_X0_LDADD = $(LDADD)
+insn_test_fsingle_mul2_X0_SOURCES = insn_test_fsingle_mul2_X0.c
+insn_test_fsingle_mul2_X0_OBJECTS = \
+ insn_test_fsingle_mul2_X0.$(OBJEXT)
+insn_test_fsingle_mul2_X0_LDADD = $(LDADD)
+insn_test_fsingle_pack1_X0_SOURCES = insn_test_fsingle_pack1_X0.c
+insn_test_fsingle_pack1_X0_OBJECTS = \
+ insn_test_fsingle_pack1_X0.$(OBJEXT)
+insn_test_fsingle_pack1_X0_LDADD = $(LDADD)
+insn_test_fsingle_pack1_Y0_SOURCES = insn_test_fsingle_pack1_Y0.c
+insn_test_fsingle_pack1_Y0_OBJECTS = \
+ insn_test_fsingle_pack1_Y0.$(OBJEXT)
+insn_test_fsingle_pack1_Y0_LDADD = $(LDADD)
+insn_test_fsingle_pack2_X0_SOURCES = insn_test_fsingle_pack2_X0.c
+insn_test_fsingle_pack2_X0_OBJECTS = \
+ insn_test_fsingle_pack2_X0.$(OBJEXT)
+insn_test_fsingle_pack2_X0_LDADD = $(LDADD)
+insn_test_fsingle_sub1_X0_SOURCES = insn_test_fsingle_sub1_X0.c
+insn_test_fsingle_sub1_X0_OBJECTS = \
+ insn_test_fsingle_sub1_X0.$(OBJEXT)
+insn_test_fsingle_sub1_X0_LDADD = $(LDADD)
+insn_test_icoh_X1_SOURCES = insn_test_icoh_X1.c
+insn_test_icoh_X1_OBJECTS = insn_test_icoh_X1.$(OBJEXT)
+insn_test_icoh_X1_LDADD = $(LDADD)
+insn_test_j_X1_SOURCES = insn_test_j_X1.c
+insn_test_j_X1_OBJECTS = insn_test_j_X1.$(OBJEXT)
+insn_test_j_X1_LDADD = $(LDADD)
+insn_test_jal_X1_SOURCES = insn_test_jal_X1.c
+insn_test_jal_X1_OBJECTS = insn_test_jal_X1.$(OBJEXT)
+insn_test_jal_X1_LDADD = $(LDADD)
+insn_test_jalr_X1_SOURCES = insn_test_jalr_X1.c
+insn_test_jalr_X1_OBJECTS = insn_test_jalr_X1.$(OBJEXT)
+insn_test_jalr_X1_LDADD = $(LDADD)
+insn_test_jalr_Y1_SOURCES = insn_test_jalr_Y1.c
+insn_test_jalr_Y1_OBJECTS = insn_test_jalr_Y1.$(OBJEXT)
+insn_test_jalr_Y1_LDADD = $(LDADD)
+insn_test_jalrp_X1_SOURCES = insn_test_jalrp_X1.c
+insn_test_jalrp_X1_OBJECTS = insn_test_jalrp_X1.$(OBJEXT)
+insn_test_jalrp_X1_LDADD = $(LDADD)
+insn_test_jalrp_Y1_SOURCES = insn_test_jalrp_Y1.c
+insn_test_jalrp_Y1_OBJECTS = insn_test_jalrp_Y1.$(OBJEXT)
+insn_test_jalrp_Y1_LDADD = $(LDADD)
+insn_test_jr_X1_SOURCES = insn_test_jr_X1.c
+insn_test_jr_X1_OBJECTS = insn_test_jr_X1.$(OBJEXT)
+insn_test_jr_X1_LDADD = $(LDADD)
+insn_test_jr_Y1_SOURCES = insn_test_jr_Y1.c
+insn_test_jr_Y1_OBJECTS = insn_test_jr_Y1.$(OBJEXT)
+insn_test_jr_Y1_LDADD = $(LDADD)
+insn_test_jrp_X1_SOURCES = insn_test_jrp_X1.c
+insn_test_jrp_X1_OBJECTS = insn_test_jrp_X1.$(OBJEXT)
+insn_test_jrp_X1_LDADD = $(LDADD)
+insn_test_jrp_Y1_SOURCES = insn_test_jrp_Y1.c
+insn_test_jrp_Y1_OBJECTS = insn_test_jrp_Y1.$(OBJEXT)
+insn_test_jrp_Y1_LDADD = $(LDADD)
+insn_test_ld1s_X1_SOURCES = insn_test_ld1s_X1.c
+insn_test_ld1s_X1_OBJECTS = insn_test_ld1s_X1.$(OBJEXT)
+insn_test_ld1s_X1_LDADD = $(LDADD)
+insn_test_ld1s_Y2_SOURCES = insn_test_ld1s_Y2.c
+insn_test_ld1s_Y2_OBJECTS = insn_test_ld1s_Y2.$(OBJEXT)
+insn_test_ld1s_Y2_LDADD = $(LDADD)
+insn_test_ld1s_add_X1_SOURCES = insn_test_ld1s_add_X1.c
+insn_test_ld1s_add_X1_OBJECTS = insn_test_ld1s_add_X1.$(OBJEXT)
+insn_test_ld1s_add_X1_LDADD = $(LDADD)
+insn_test_ld1u_X1_SOURCES = insn_test_ld1u_X1.c
+insn_test_ld1u_X1_OBJECTS = insn_test_ld1u_X1.$(OBJEXT)
+insn_test_ld1u_X1_LDADD = $(LDADD)
+insn_test_ld1u_Y2_SOURCES = insn_test_ld1u_Y2.c
+insn_test_ld1u_Y2_OBJECTS = insn_test_ld1u_Y2.$(OBJEXT)
+insn_test_ld1u_Y2_LDADD = $(LDADD)
+insn_test_ld1u_add_X1_SOURCES = insn_test_ld1u_add_X1.c
+insn_test_ld1u_add_X1_OBJECTS = insn_test_ld1u_add_X1.$(OBJEXT)
+insn_test_ld1u_add_X1_LDADD = $(LDADD)
+insn_test_ld2s_X1_SOURCES = insn_test_ld2s_X1.c
+insn_test_ld2s_X1_OBJECTS = insn_test_ld2s_X1.$(OBJEXT)
+insn_test_ld2s_X1_LDADD = $(LDADD)
+insn_test_ld2s_Y2_SOURCES = insn_test_ld2s_Y2.c
+insn_test_ld2s_Y2_OBJECTS = insn_test_ld2s_Y2.$(OBJEXT)
+insn_test_ld2s_Y2_LDADD = $(LDADD)
+insn_test_ld2u_X1_SOURCES = insn_test_ld2u_X1.c
+insn_test_ld2u_X1_OBJECTS = insn_test_ld2u_X1.$(OBJEXT)
+insn_test_ld2u_X1_LDADD = $(LDADD)
+insn_test_ld2u_Y2_SOURCES = insn_test_ld2u_Y2.c
+insn_test_ld2u_Y2_OBJECTS = insn_test_ld2u_Y2.$(OBJEXT)
+insn_test_ld2u_Y2_LDADD = $(LDADD)
+insn_test_ld4s_X1_SOURCES = insn_test_ld4s_X1.c
+insn_test_ld4s_X1_OBJECTS = insn_test_ld4s_X1.$(OBJEXT)
+insn_test_ld4s_X1_LDADD = $(LDADD)
+insn_test_ld4s_add_X1_SOURCES = insn_test_ld4s_add_X1.c
+insn_test_ld4s_add_X1_OBJECTS = insn_test_ld4s_add_X1.$(OBJEXT)
+insn_test_ld4s_add_X1_LDADD = $(LDADD)
+insn_test_ld4u_X1_SOURCES = insn_test_ld4u_X1.c
+insn_test_ld4u_X1_OBJECTS = insn_test_ld4u_X1.$(OBJEXT)
+insn_test_ld4u_X1_LDADD = $(LDADD)
+insn_test_ld4u_Y2_SOURCES = insn_test_ld4u_Y2.c
+insn_test_ld4u_Y2_OBJECTS = insn_test_ld4u_Y2.$(OBJEXT)
+insn_test_ld4u_Y2_LDADD = $(LDADD)
+insn_test_ld4u_add_X1_SOURCES = insn_test_ld4u_add_X1.c
+insn_test_ld4u_add_X1_OBJECTS = insn_test_ld4u_add_X1.$(OBJEXT)
+insn_test_ld4u_add_X1_LDADD = $(LDADD)
+insn_test_ld_X1_SOURCES = insn_test_ld_X1.c
+insn_test_ld_X1_OBJECTS = insn_test_ld_X1.$(OBJEXT)
+insn_test_ld_X1_LDADD = $(LDADD)
+insn_test_ld_Y2_SOURCES = insn_test_ld_Y2.c
+insn_test_ld_Y2_OBJECTS = insn_test_ld_Y2.$(OBJEXT)
+insn_test_ld_Y2_LDADD = $(LDADD)
+insn_test_ld_add_X1_SOURCES = insn_test_ld_add_X1.c
+insn_test_ld_add_X1_OBJECTS = insn_test_ld_add_X1.$(OBJEXT)
+insn_test_ld_add_X1_LDADD = $(LDADD)
+insn_test_ldna_X1_SOURCES = insn_test_ldna_X1.c
+insn_test_ldna_X1_OBJECTS = insn_test_ldna_X1.$(OBJEXT)
+insn_test_ldna_X1_LDADD = $(LDADD)
+insn_test_ldna_add_X1_SOURCES = insn_test_ldna_add_X1.c
+insn_test_ldna_add_X1_OBJECTS = insn_test_ldna_add_X1.$(OBJEXT)
+insn_test_ldna_add_X1_LDADD = $(LDADD)
+insn_test_ldnt1s_X1_SOURCES = insn_test_ldnt1s_X1.c
+insn_test_ldnt1s_X1_OBJECTS = insn_test_ldnt1s_X1.$(OBJEXT)
+insn_test_ldnt1s_X1_LDADD = $(LDADD)
+insn_test_ldnt1s_add_X1_SOURCES = insn_test_ldnt1s_add_X1.c
+insn_test_ldnt1s_add_X1_OBJECTS = insn_test_ldnt1s_add_X1.$(OBJEXT)
+insn_test_ldnt1s_add_X1_LDADD = $(LDADD)
+insn_test_ldnt1u_X1_SOURCES = insn_test_ldnt1u_X1.c
+insn_test_ldnt1u_X1_OBJECTS = insn_test_ldnt1u_X1.$(OBJEXT)
+insn_test_ldnt1u_X1_LDADD = $(LDADD)
+insn_test_ldnt1u_add_X1_SOURCES = insn_test_ldnt1u_add_X1.c
+insn_test_ldnt1u_add_X1_OBJECTS = insn_test_ldnt1u_add_X1.$(OBJEXT)
+insn_test_ldnt1u_add_X1_LDADD = $(LDADD)
+insn_test_ldnt2s_X1_SOURCES = insn_test_ldnt2s_X1.c
+insn_test_ldnt2s_X1_OBJECTS = insn_test_ldnt2s_X1.$(OBJEXT)
+insn_test_ldnt2s_X1_LDADD = $(LDADD)
+insn_test_ldnt2s_add_X1_SOURCES = insn_test_ldnt2s_add_X1.c
+insn_test_ldnt2s_add_X1_OBJECTS = insn_test_ldnt2s_add_X1.$(OBJEXT)
+insn_test_ldnt2s_add_X1_LDADD = $(LDADD)
+insn_test_ldnt2u_add_X1_SOURCES = insn_test_ldnt2u_add_X1.c
+insn_test_ldnt2u_add_X1_OBJECTS = insn_test_ldnt2u_add_X1.$(OBJEXT)
+insn_test_ldnt2u_add_X1_LDADD = $(LDADD)
+insn_test_ldnt4s_X1_SOURCES = insn_test_ldnt4s_X1.c
+insn_test_ldnt4s_X1_OBJECTS = insn_test_ldnt4s_X1.$(OBJEXT)
+insn_test_ldnt4s_X1_LDADD = $(LDADD)
+insn_test_ldnt4s_add_X1_SOURCES = insn_test_ldnt4s_add_X1.c
+insn_test_ldnt4s_add_X1_OBJECTS = insn_test_ldnt4s_add_X1.$(OBJEXT)
+insn_test_ldnt4s_add_X1_LDADD = $(LDADD)
+insn_test_ldnt4u_X1_SOURCES = insn_test_ldnt4u_X1.c
+insn_test_ldnt4u_X1_OBJECTS = insn_test_ldnt4u_X1.$(OBJEXT)
+insn_test_ldnt4u_X1_LDADD = $(LDADD)
+insn_test_ldnt4u_add_X1_SOURCES = insn_test_ldnt4u_add_X1.c
+insn_test_ldnt4u_add_X1_OBJECTS = insn_test_ldnt4u_add_X1.$(OBJEXT)
+insn_test_ldnt4u_add_X1_LDADD = $(LDADD)
+insn_test_ldnt_X1_SOURCES = insn_test_ldnt_X1.c
+insn_test_ldnt_X1_OBJECTS = insn_test_ldnt_X1.$(OBJEXT)
+insn_test_ldnt_X1_LDADD = $(LDADD)
+insn_test_ldnt_add_X1_SOURCES = insn_test_ldnt_add_X1.c
+insn_test_ldnt_add_X1_OBJECTS = insn_test_ldnt_add_X1.$(OBJEXT)
+insn_test_ldnt_add_X1_LDADD = $(LDADD)
+insn_test_lnk_X1_SOURCES = insn_test_lnk_X1.c
+insn_test_lnk_X1_OBJECTS = insn_test_lnk_X1.$(OBJEXT)
+insn_test_lnk_X1_LDADD = $(LDADD)
+insn_test_lnk_Y1_SOURCES = insn_test_lnk_Y1.c
+insn_test_lnk_Y1_OBJECTS = insn_test_lnk_Y1.$(OBJEXT)
+insn_test_lnk_Y1_LDADD = $(LDADD)
+insn_test_mf_X1_SOURCES = insn_test_mf_X1.c
+insn_test_mf_X1_OBJECTS = insn_test_mf_X1.$(OBJEXT)
+insn_test_mf_X1_LDADD = $(LDADD)
+insn_test_mm_X0_SOURCES = insn_test_mm_X0.c
+insn_test_mm_X0_OBJECTS = insn_test_mm_X0.$(OBJEXT)
+insn_test_mm_X0_LDADD = $(LDADD)
+insn_test_mnz_X0_SOURCES = insn_test_mnz_X0.c
+insn_test_mnz_X0_OBJECTS = insn_test_mnz_X0.$(OBJEXT)
+insn_test_mnz_X0_LDADD = $(LDADD)
+insn_test_mnz_X1_SOURCES = insn_test_mnz_X1.c
+insn_test_mnz_X1_OBJECTS = insn_test_mnz_X1.$(OBJEXT)
+insn_test_mnz_X1_LDADD = $(LDADD)
+insn_test_mnz_Y0_SOURCES = insn_test_mnz_Y0.c
+insn_test_mnz_Y0_OBJECTS = insn_test_mnz_Y0.$(OBJEXT)
+insn_test_mnz_Y0_LDADD = $(LDADD)
+insn_test_mnz_Y1_SOURCES = insn_test_mnz_Y1.c
+insn_test_mnz_Y1_OBJECTS = insn_test_mnz_Y1.$(OBJEXT)
+insn_test_mnz_Y1_LDADD = $(LDADD)
+insn_test_move_X0_SOURCES = insn_test_move_X0.c
+insn_test_move_X0_OBJECTS = insn_test_move_X0.$(OBJEXT)
+insn_test_move_X0_LDADD = $(LDADD)
+insn_test_move_X1_SOURCES = insn_test_move_X1.c
+insn_test_move_X1_OBJECTS = insn_test_move_X1.$(OBJEXT)
+insn_test_move_X1_LDADD = $(LDADD)
+insn_test_move_Y0_SOURCES = insn_test_move_Y0.c
+insn_test_move_Y0_OBJECTS = insn_test_move_Y0.$(OBJEXT)
+insn_test_move_Y0_LDADD = $(LDADD)
+insn_test_move_Y1_SOURCES = insn_test_move_Y1.c
+insn_test_move_Y1_OBJECTS = insn_test_move_Y1.$(OBJEXT)
+insn_test_move_Y1_LDADD = $(LDADD)
+insn_test_movei_X0_SOURCES = insn_test_movei_X0.c
+insn_test_movei_X0_OBJECTS = insn_test_movei_X0.$(OBJEXT)
+insn_test_movei_X0_LDADD = $(LDADD)
+insn_test_movei_X1_SOURCES = insn_test_movei_X1.c
+insn_test_movei_X1_OBJECTS = insn_test_movei_X1.$(OBJEXT)
+insn_test_movei_X1_LDADD = $(LDADD)
+insn_test_movei_Y0_SOURCES = insn_test_movei_Y0.c
+insn_test_movei_Y0_OBJECTS = insn_test_movei_Y0.$(OBJEXT)
+insn_test_movei_Y0_LDADD = $(LDADD)
+insn_test_movei_Y1_SOURCES = insn_test_movei_Y1.c
+insn_test_movei_Y1_OBJECTS = insn_test_movei_Y1.$(OBJEXT)
+insn_test_movei_Y1_LDADD = $(LDADD)
+insn_test_moveli_X0_SOURCES = insn_test_moveli_X0.c
+insn_test_moveli_X0_OBJECTS = insn_test_moveli_X0.$(OBJEXT)
+insn_test_moveli_X0_LDADD = $(LDADD)
+insn_test_moveli_X1_SOURCES = insn_test_moveli_X1.c
+insn_test_moveli_X1_OBJECTS = insn_test_moveli_X1.$(OBJEXT)
+insn_test_moveli_X1_LDADD = $(LDADD)
+insn_test_mul_hs_hs_X0_SOURCES = insn_test_mul_hs_hs_X0.c
+insn_test_mul_hs_hs_X0_OBJECTS = insn_test_mul_hs_hs_X0.$(OBJEXT)
+insn_test_mul_hs_hs_X0_LDADD = $(LDADD)
+insn_test_mul_hs_hs_Y0_SOURCES = insn_test_mul_hs_hs_Y0.c
+insn_test_mul_hs_hs_Y0_OBJECTS = insn_test_mul_hs_hs_Y0.$(OBJEXT)
+insn_test_mul_hs_hs_Y0_LDADD = $(LDADD)
+insn_test_mul_hs_hu_X0_SOURCES = insn_test_mul_hs_hu_X0.c
+insn_test_mul_hs_hu_X0_OBJECTS = insn_test_mul_hs_hu_X0.$(OBJEXT)
+insn_test_mul_hs_hu_X0_LDADD = $(LDADD)
+insn_test_mul_hs_ls_X0_SOURCES = insn_test_mul_hs_ls_X0.c
+insn_test_mul_hs_ls_X0_OBJECTS = insn_test_mul_hs_ls_X0.$(OBJEXT)
+insn_test_mul_hs_ls_X0_LDADD = $(LDADD)
+insn_test_mul_hs_lu_X0_SOURCES = insn_test_mul_hs_lu_X0.c
+insn_test_mul_hs_lu_X0_OBJECTS = insn_test_mul_hs_lu_X0.$(OBJEXT)
+insn_test_mul_hs_lu_X0_LDADD = $(LDADD)
+insn_test_mul_hu_hu_X0_SOURCES = insn_test_mul_hu_hu_X0.c
+insn_test_mul_hu_hu_X0_OBJECTS = insn_test_mul_hu_hu_X0.$(OBJEXT)
+insn_test_mul_hu_hu_X0_LDADD = $(LDADD)
+insn_test_mul_hu_hu_Y0_SOURCES = insn_test_mul_hu_hu_Y0.c
+insn_test_mul_hu_hu_Y0_OBJECTS = insn_test_mul_hu_hu_Y0.$(OBJEXT)
+insn_test_mul_hu_hu_Y0_LDADD = $(LDADD)
+insn_test_mul_hu_lu_X0_SOURCES = insn_test_mul_hu_lu_X0.c
+insn_test_mul_hu_lu_X0_OBJECTS = insn_test_mul_hu_lu_X0.$(OBJEXT)
+insn_test_mul_hu_lu_X0_LDADD = $(LDADD)
+insn_test_mul_ls_ls_X0_SOURCES = insn_test_mul_ls_ls_X0.c
+insn_test_mul_ls_ls_X0_OBJECTS = insn_test_mul_ls_ls_X0.$(OBJEXT)
+insn_test_mul_ls_ls_X0_LDADD = $(LDADD)
+insn_test_mul_ls_ls_Y0_SOURCES = insn_test_mul_ls_ls_Y0.c
+insn_test_mul_ls_ls_Y0_OBJECTS = insn_test_mul_ls_ls_Y0.$(OBJEXT)
+insn_test_mul_ls_ls_Y0_LDADD = $(LDADD)
+insn_test_mul_ls_lu_X0_SOURCES = insn_test_mul_ls_lu_X0.c
+insn_test_mul_ls_lu_X0_OBJECTS = insn_test_mul_ls_lu_X0.$(OBJEXT)
+insn_test_mul_ls_lu_X0_LDADD = $(LDADD)
+insn_test_mul_lu_lu_X0_SOURCES = insn_test_mul_lu_lu_X0.c
+insn_test_mul_lu_lu_X0_OBJECTS = insn_test_mul_lu_lu_X0.$(OBJEXT)
+insn_test_mul_lu_lu_X0_LDADD = $(LDADD)
+insn_test_mul_lu_lu_Y0_SOURCES = insn_test_mul_lu_lu_Y0.c
+insn_test_mul_lu_lu_Y0_OBJECTS = insn_test_mul_lu_lu_Y0.$(OBJEXT)
+insn_test_mul_lu_lu_Y0_LDADD = $(LDADD)
+insn_test_mula_hs_hs_X0_SOURCES = insn_test_mula_hs_hs_X0.c
+insn_test_mula_hs_hs_X0_OBJECTS = insn_test_mula_hs_hs_X0.$(OBJEXT)
+insn_test_mula_hs_hs_X0_LDADD = $(LDADD)
+insn_test_mula_hs_hs_Y0_SOURCES = insn_test_mula_hs_hs_Y0.c
+insn_test_mula_hs_hs_Y0_OBJECTS = insn_test_mula_hs_hs_Y0.$(OBJEXT)
+insn_test_mula_hs_hs_Y0_LDADD = $(LDADD)
+insn_test_mula_hs_hu_X0_SOURCES = insn_test_mula_hs_hu_X0.c
+insn_test_mula_hs_hu_X0_OBJECTS = insn_test_mula_hs_hu_X0.$(OBJEXT)
+insn_test_mula_hs_hu_X0_LDADD = $(LDADD)
+insn_test_mula_hs_ls_X0_SOURCES = insn_test_mula_hs_ls_X0.c
+insn_test_mula_hs_ls_X0_OBJECTS = insn_test_mula_hs_ls_X0.$(OBJEXT)
+insn_test_mula_hs_ls_X0_LDADD = $(LDADD)
+insn_test_mula_hs_lu_X0_SOURCES = insn_test_mula_hs_lu_X0.c
+insn_test_mula_hs_lu_X0_OBJECTS = insn_test_mula_hs_lu_X0.$(OBJEXT)
+insn_test_mula_hs_lu_X0_LDADD = $(LDADD)
+insn_test_mula_hu_hu_X0_SOURCES = insn_test_mula_hu_hu_X0.c
+insn_test_mula_hu_hu_X0_OBJECTS = insn_test_mula_hu_hu_X0.$(OBJEXT)
+insn_test_mula_hu_hu_X0_LDADD = $(LDADD)
+insn_test_mula_hu_hu_Y0_SOURCES = insn_test_mula_hu_hu_Y0.c
+insn_test_mula_hu_hu_Y0_OBJECTS = insn_test_mula_hu_hu_Y0.$(OBJEXT)
+insn_test_mula_hu_hu_Y0_LDADD = $(LDADD)
+insn_test_mula_hu_ls_X0_SOURCES = insn_test_mula_hu_ls_X0.c
+insn_test_mula_hu_ls_X0_OBJECTS = insn_test_mula_hu_ls_X0.$(OBJEXT)
+insn_test_mula_hu_ls_X0_LDADD = $(LDADD)
+insn_test_mula_hu_lu_X0_SOURCES = insn_test_mula_hu_lu_X0.c
+insn_test_mula_hu_lu_X0_OBJECTS = insn_test_mula_hu_lu_X0.$(OBJEXT)
+insn_test_mula_hu_lu_X0_LDADD = $(LDADD)
+insn_test_mula_ls_ls_X0_SOURCES = insn_test_mula_ls_ls_X0.c
+insn_test_mula_ls_ls_X0_OBJECTS = insn_test_mula_ls_ls_X0.$(OBJEXT)
+insn_test_mula_ls_ls_X0_LDADD = $(LDADD)
+insn_test_mula_ls_ls_Y0_SOURCES = insn_test_mula_ls_ls_Y0.c
+insn_test_mula_ls_ls_Y0_OBJECTS = insn_test_mula_ls_ls_Y0.$(OBJEXT)
+insn_test_mula_ls_ls_Y0_LDADD = $(LDADD)
+insn_test_mula_ls_lu_X0_SOURCES = insn_test_mula_ls_lu_X0.c
+insn_test_mula_ls_lu_X0_OBJECTS = insn_test_mula_ls_lu_X0.$(OBJEXT)
+insn_test_mula_ls_lu_X0_LDADD = $(LDADD)
+insn_test_mula_lu_lu_X0_SOURCES = insn_test_mula_lu_lu_X0.c
+insn_test_mula_lu_lu_X0_OBJECTS = insn_test_mula_lu_lu_X0.$(OBJEXT)
+insn_test_mula_lu_lu_X0_LDADD = $(LDADD)
+insn_test_mula_lu_lu_Y0_SOURCES = insn_test_mula_lu_lu_Y0.c
+insn_test_mula_lu_lu_Y0_OBJECTS = insn_test_mula_lu_lu_Y0.$(OBJEXT)
+insn_test_mula_lu_lu_Y0_LDADD = $(LDADD)
+insn_test_mulax_X0_SOURCES = insn_test_mulax_X0.c
+insn_test_mulax_X0_OBJECTS = insn_test_mulax_X0.$(OBJEXT)
+insn_test_mulax_X0_LDADD = $(LDADD)
+insn_test_mulax_Y0_SOURCES = insn_test_mulax_Y0.c
+insn_test_mulax_Y0_OBJECTS = insn_test_mulax_Y0.$(OBJEXT)
+insn_test_mulax_Y0_LDADD = $(LDADD)
+insn_test_mulx_X0_SOURCES = insn_test_mulx_X0.c
+insn_test_mulx_X0_OBJECTS = insn_test_mulx_X0.$(OBJEXT)
+insn_test_mulx_X0_LDADD = $(LDADD)
+insn_test_mulx_Y0_SOURCES = insn_test_mulx_Y0.c
+insn_test_mulx_Y0_OBJECTS = insn_test_mulx_Y0.$(OBJEXT)
+insn_test_mulx_Y0_LDADD = $(LDADD)
+insn_test_mz_X0_SOURCES = insn_test_mz_X0.c
+insn_test_mz_X0_OBJECTS = insn_test_mz_X0.$(OBJEXT)
+insn_test_mz_X0_LDADD = $(LDADD)
+insn_test_mz_X1_SOURCES = insn_test_mz_X1.c
+insn_test_mz_X1_OBJECTS = insn_test_mz_X1.$(OBJEXT)
+insn_test_mz_X1_LDADD = $(LDADD)
+insn_test_mz_Y0_SOURCES = insn_test_mz_Y0.c
+insn_test_mz_Y0_OBJECTS = insn_test_mz_Y0.$(OBJEXT)
+insn_test_mz_Y0_LDADD = $(LDADD)
+insn_test_mz_Y1_SOURCES = insn_test_mz_Y1.c
+insn_test_mz_Y1_OBJECTS = insn_test_mz_Y1.$(OBJEXT)
+insn_test_mz_Y1_LDADD = $(LDADD)
+insn_test_nop_X0_SOURCES = insn_test_nop_X0.c
+insn_test_nop_X0_OBJECTS = insn_test_nop_X0.$(OBJEXT)
+insn_test_nop_X0_LDADD = $(LDADD)
+insn_test_nop_X1_SOURCES = insn_test_nop_X1.c
+insn_test_nop_X1_OBJECTS = insn_test_nop_X1.$(OBJEXT)
+insn_test_nop_X1_LDADD = $(LDADD)
+insn_test_nop_Y0_SOURCES = insn_test_nop_Y0.c
+insn_test_nop_Y0_OBJECTS = insn_test_nop_Y0.$(OBJEXT)
+insn_test_nop_Y0_LDADD = $(LDADD)
+insn_test_nop_Y1_SOURCES = insn_test_nop_Y1.c
+insn_test_nop_Y1_OBJECTS = insn_test_nop_Y1.$(OBJEXT)
+insn_test_nop_Y1_LDADD = $(LDADD)
+insn_test_nor_X0_SOURCES = insn_test_nor_X0.c
+insn_test_nor_X0_OBJECTS = insn_test_nor_X0.$(OBJEXT)
+insn_test_nor_X0_LDADD = $(LDADD)
+insn_test_nor_X1_SOURCES = insn_test_nor_X1.c
+insn_test_nor_X1_OBJECTS = insn_test_nor_X1.$(OBJEXT)
+insn_test_nor_X1_LDADD = $(LDADD)
+insn_test_nor_Y0_SOURCES = insn_test_nor_Y0.c
+insn_test_nor_Y0_OBJECTS = insn_test_nor_Y0.$(OBJEXT)
+insn_test_nor_Y0_LDADD = $(LDADD)
+insn_test_nor_Y1_SOURCES = insn_test_nor_Y1.c
+insn_test_nor_Y1_OBJECTS = insn_test_nor_Y1.$(OBJEXT)
+insn_test_nor_Y1_LDADD = $(LDADD)
+insn_test_or_X0_SOURCES = insn_test_or_X0.c
+insn_test_or_X0_OBJECTS = insn_test_or_X0.$(OBJEXT)
+insn_test_or_X0_LDADD = $(LDADD)
+insn_test_or_X1_SOURCES = insn_test_or_X1.c
+insn_test_or_X1_OBJECTS = insn_test_or_X1.$(OBJEXT)
+insn_test_or_X1_LDADD = $(LDADD)
+insn_test_or_Y0_SOURCES = insn_test_or_Y0.c
+insn_test_or_Y0_OBJECTS = insn_test_or_Y0.$(OBJEXT)
+insn_test_or_Y0_LDADD = $(LDADD)
+insn_test_or_Y1_SOURCES = insn_test_or_Y1.c
+insn_test_or_Y1_OBJECTS = insn_test_or_Y1.$(OBJEXT)
+insn_test_or_Y1_LDADD = $(LDADD)
+insn_test_ori_X0_SOURCES = insn_test_ori_X0.c
+insn_test_ori_X0_OBJECTS = insn_test_ori_X0.$(OBJEXT)
+insn_test_ori_X0_LDADD = $(LDADD)
+insn_test_ori_X1_SOURCES = insn_test_ori_X1.c
+insn_test_ori_X1_OBJECTS = insn_test_ori_X1.$(OBJEXT)
+insn_test_ori_X1_LDADD = $(LDADD)
+insn_test_pcnt_X0_SOURCES = insn_test_pcnt_X0.c
+insn_test_pcnt_X0_OBJECTS = insn_test_pcnt_X0.$(OBJEXT)
+insn_test_pcnt_X0_LDADD = $(LDADD)
+insn_test_pcnt_Y0_SOURCES = insn_test_pcnt_Y0.c
+insn_test_pcnt_Y0_OBJECTS = insn_test_pcnt_Y0.$(OBJEXT)
+insn_test_pcnt_Y0_LDADD = $(LDADD)
+insn_test_prefetch_X1_SOURCES = insn_test_prefetch_X1.c
+insn_test_prefetch_X1_OBJECTS = insn_test_prefetch_X1.$(OBJEXT)
+insn_test_prefetch_X1_LDADD = $(LDADD)
+insn_test_prefetch_Y2_SOURCES = insn_test_prefetch_Y2.c
+insn_test_prefetch_Y2_OBJECTS = insn_test_prefetch_Y2.$(OBJEXT)
+insn_test_prefetch_Y2_LDADD = $(LDADD)
+insn_test_prefetch_l1_X1_SOURCES = insn_test_prefetch_l1_X1.c
+insn_test_prefetch_l1_X1_OBJECTS = insn_test_prefetch_l1_X1.$(OBJEXT)
+insn_test_prefetch_l1_X1_LDADD = $(LDADD)
+insn_test_prefetch_l1_Y2_SOURCES = insn_test_prefetch_l1_Y2.c
+insn_test_prefetch_l1_Y2_OBJECTS = insn_test_prefetch_l1_Y2.$(OBJEXT)
+insn_test_prefetch_l1_Y2_LDADD = $(LDADD)
+insn_test_prefetch_l2_X1_SOURCES = insn_test_prefetch_l2_X1.c
+insn_test_prefetch_l2_X1_OBJECTS = insn_test_prefetch_l2_X1.$(OBJEXT)
+insn_test_prefetch_l2_X1_LDADD = $(LDADD)
+insn_test_prefetch_l2_Y2_SOURCES = insn_test_prefetch_l2_Y2.c
+insn_test_prefetch_l2_Y2_OBJECTS = insn_test_prefetch_l2_Y2.$(OBJEXT)
+insn_test_prefetch_l2_Y2_LDADD = $(LDADD)
+insn_test_prefetch_l3_X1_SOURCES = insn_test_prefetch_l3_X1.c
+insn_test_prefetch_l3_X1_OBJECTS = insn_test_prefetch_l3_X1.$(OBJEXT)
+insn_test_prefetch_l3_X1_LDADD = $(LDADD)
+insn_test_prefetch_l3_Y2_SOURCES = insn_test_prefetch_l3_Y2.c
+insn_test_prefetch_l3_Y2_OBJECTS = insn_test_prefetch_l3_Y2.$(OBJEXT)
+insn_test_prefetch_l3_Y2_LDADD = $(LDADD)
+insn_test_revbits_X0_SOURCES = insn_test_revbits_X0.c
+insn_test_revbits_X0_OBJECTS = insn_test_revbits_X0.$(OBJEXT)
+insn_test_revbits_X0_LDADD = $(LDADD)
+insn_test_revbits_Y0_SOURCES = insn_test_revbits_Y0.c
+insn_test_revbits_Y0_OBJECTS = insn_test_revbits_Y0.$(OBJEXT)
+insn_test_revbits_Y0_LDADD = $(LDADD)
+insn_test_revbytes_X0_SOURCES = insn_test_revbytes_X0.c
+insn_test_revbytes_X0_OBJECTS = insn_test_revbytes_X0.$(OBJEXT)
+insn_test_revbytes_X0_LDADD = $(LDADD)
+insn_test_revbytes_Y0_SOURCES = insn_test_revbytes_Y0.c
+insn_test_revbytes_Y0_OBJECTS = insn_test_revbytes_Y0.$(OBJEXT)
+insn_test_revbytes_Y0_LDADD = $(LDADD)
+insn_test_rotl_X0_SOURCES = insn_test_rotl_X0.c
+insn_test_rotl_X0_OBJECTS = insn_test_rotl_X0.$(OBJEXT)
+insn_test_rotl_X0_LDADD = $(LDADD)
+insn_test_rotl_X1_SOURCES = insn_test_rotl_X1.c
+insn_test_rotl_X1_OBJECTS = insn_test_rotl_X1.$(OBJEXT)
+insn_test_rotl_X1_LDADD = $(LDADD)
+insn_test_rotl_Y0_SOURCES = insn_test_rotl_Y0.c
+insn_test_rotl_Y0_OBJECTS = insn_test_rotl_Y0.$(OBJEXT)
+insn_test_rotl_Y0_LDADD = $(LDADD)
+insn_test_rotl_Y1_SOURCES = insn_test_rotl_Y1.c
+insn_test_rotl_Y1_OBJECTS = insn_test_rotl_Y1.$(OBJEXT)
+insn_test_rotl_Y1_LDADD = $(LDADD)
+insn_test_rotli_X0_SOURCES = insn_test_rotli_X0.c
+insn_test_rotli_X0_OBJECTS = insn_test_rotli_X0.$(OBJEXT)
+insn_test_rotli_X0_LDADD = $(LDADD)
+insn_test_rotli_X1_SOURCES = insn_test_rotli_X1.c
+insn_test_rotli_X1_OBJECTS = insn_test_rotli_X1.$(OBJEXT)
+insn_test_rotli_X1_LDADD = $(LDADD)
+insn_test_rotli_Y0_SOURCES = insn_test_rotli_Y0.c
+insn_test_rotli_Y0_OBJECTS = insn_test_rotli_Y0.$(OBJEXT)
+insn_test_rotli_Y0_LDADD = $(LDADD)
+insn_test_rotli_Y1_SOURCES = insn_test_rotli_Y1.c
+insn_test_rotli_Y1_OBJECTS = insn_test_rotli_Y1.$(OBJEXT)
+insn_test_rotli_Y1_LDADD = $(LDADD)
+insn_test_shl16insli_X0_SOURCES = insn_test_shl16insli_X0.c
+insn_test_shl16insli_X0_OBJECTS = insn_test_shl16insli_X0.$(OBJEXT)
+insn_test_shl16insli_X0_LDADD = $(LDADD)
+insn_test_shl16insli_X1_SOURCES = insn_test_shl16insli_X1.c
+insn_test_shl16insli_X1_OBJECTS = insn_test_shl16insli_X1.$(OBJEXT)
+insn_test_shl16insli_X1_LDADD = $(LDADD)
+insn_test_shl1add_X0_SOURCES = insn_test_shl1add_X0.c
+insn_test_shl1add_X0_OBJECTS = insn_test_shl1add_X0.$(OBJEXT)
+insn_test_shl1add_X0_LDADD = $(LDADD)
+insn_test_shl1add_X1_SOURCES = insn_test_shl1add_X1.c
+insn_test_shl1add_X1_OBJECTS = insn_test_shl1add_X1.$(OBJEXT)
+insn_test_shl1add_X1_LDADD = $(LDADD)
+insn_test_shl1add_Y0_SOURCES = insn_test_shl1add_Y0.c
+insn_test_shl1add_Y0_OBJECTS = insn_test_shl1add_Y0.$(OBJEXT)
+insn_test_shl1add_Y0_LDADD = $(LDADD)
+insn_test_shl1add_Y1_SOURCES = insn_test_shl1add_Y1.c
+insn_test_shl1add_Y1_OBJECTS = insn_test_shl1add_Y1.$(OBJEXT)
+insn_test_shl1add_Y1_LDADD = $(LDADD)
+insn_test_shl1addx_X0_SOURCES = insn_test_shl1addx_X0.c
+insn_test_shl1addx_X0_OBJECTS = insn_test_shl1addx_X0.$(OBJEXT)
+insn_test_shl1addx_X0_LDADD = $(LDADD)
+insn_test_shl1addx_X1_SOURCES = insn_test_shl1addx_X1.c
+insn_test_shl1addx_X1_OBJECTS = insn_test_shl1addx_X1.$(OBJEXT)
+insn_test_shl1addx_X1_LDADD = $(LDADD)
+insn_test_shl1addx_Y0_SOURCES = insn_test_shl1addx_Y0.c
+insn_test_shl1addx_Y0_OBJECTS = insn_test_shl1addx_Y0.$(OBJEXT)
+insn_test_shl1addx_Y0_LDADD = $(LDADD)
+insn_test_shl1addx_Y1_SOURCES = insn_test_shl1addx_Y1.c
+insn_test_shl1addx_Y1_OBJECTS = insn_test_shl1addx_Y1.$(OBJEXT)
+insn_test_shl1addx_Y1_LDADD = $(LDADD)
+insn_test_shl2add_X0_SOURCES = insn_test_shl2add_X0.c
+insn_test_shl2add_X0_OBJECTS = insn_test_shl2add_X0.$(OBJEXT)
+insn_test_shl2add_X0_LDADD = $(LDADD)
+insn_test_shl2add_X1_SOURCES = insn_test_shl2add_X1.c
+insn_test_shl2add_X1_OBJECTS = insn_test_shl2add_X1.$(OBJEXT)
+insn_test_shl2add_X1_LDADD = $(LDADD)
+insn_test_shl2add_Y0_SOURCES = insn_test_shl2add_Y0.c
+insn_test_shl2add_Y0_OBJECTS = insn_test_shl2add_Y0.$(OBJEXT)
+insn_test_shl2add_Y0_LDADD = $(LDADD)
+insn_test_shl2add_Y1_SOURCES = insn_test_shl2add_Y1.c
+insn_test_shl2add_Y1_OBJECTS = insn_test_shl2add_Y1.$(OBJEXT)
+insn_test_shl2add_Y1_LDADD = $(LDADD)
+insn_test_shl2addx_X0_SOURCES = insn_test_shl2addx_X0.c
+insn_test_shl2addx_X0_OBJECTS = insn_test_shl2addx_X0.$(OBJEXT)
+insn_test_shl2addx_X0_LDADD = $(LDADD)
+insn_test_shl2addx_X1_SOURCES = insn_test_shl2addx_X1.c
+insn_test_shl2addx_X1_OBJECTS = insn_test_shl2addx_X1.$(OBJEXT)
+insn_test_shl2addx_X1_LDADD = $(LDADD)
+insn_test_shl2addx_Y0_SOURCES = insn_test_shl2addx_Y0.c
+insn_test_shl2addx_Y0_OBJECTS = insn_test_shl2addx_Y0.$(OBJEXT)
+insn_test_shl2addx_Y0_LDADD = $(LDADD)
+insn_test_shl2addx_Y1_SOURCES = insn_test_shl2addx_Y1.c
+insn_test_shl2addx_Y1_OBJECTS = insn_test_shl2addx_Y1.$(OBJEXT)
+insn_test_shl2addx_Y1_LDADD = $(LDADD)
+insn_test_shl3add_X0_SOURCES = insn_test_shl3add_X0.c
+insn_test_shl3add_X0_OBJECTS = insn_test_shl3add_X0.$(OBJEXT)
+insn_test_shl3add_X0_LDADD = $(LDADD)
+insn_test_shl3add_X1_SOURCES = insn_test_shl3add_X1.c
+insn_test_shl3add_X1_OBJECTS = insn_test_shl3add_X1.$(OBJEXT)
+insn_test_shl3add_X1_LDADD = $(LDADD)
+insn_test_shl3add_Y0_SOURCES = insn_test_shl3add_Y0.c
+insn_test_shl3add_Y0_OBJECTS = insn_test_shl3add_Y0.$(OBJEXT)
+insn_test_shl3add_Y0_LDADD = $(LDADD)
+insn_test_shl3add_Y1_SOURCES = insn_test_shl3add_Y1.c
+insn_test_shl3add_Y1_OBJECTS = insn_test_shl3add_Y1.$(OBJEXT)
+insn_test_shl3add_Y1_LDADD = $(LDADD)
+insn_test_shl3addx_X0_SOURCES = insn_test_shl3addx_X0.c
+insn_test_shl3addx_X0_OBJECTS = insn_test_shl3addx_X0.$(OBJEXT)
+insn_test_shl3addx_X0_LDADD = $(LDADD)
+insn_test_shl3addx_X1_SOURCES = insn_test_shl3addx_X1.c
+insn_test_shl3addx_X1_OBJECTS = insn_test_shl3addx_X1.$(OBJEXT)
+insn_test_shl3addx_X1_LDADD = $(LDADD)
+insn_test_shl3addx_Y0_SOURCES = insn_test_shl3addx_Y0.c
+insn_test_shl3addx_Y0_OBJECTS = insn_test_shl3addx_Y0.$(OBJEXT)
+insn_test_shl3addx_Y0_LDADD = $(LDADD)
+insn_test_shl3addx_Y1_SOURCES = insn_test_shl3addx_Y1.c
+insn_test_shl3addx_Y1_OBJECTS = insn_test_shl3addx_Y1.$(OBJEXT)
+insn_test_shl3addx_Y1_LDADD = $(LDADD)
+insn_test_shl_X0_SOURCES = insn_test_shl_X0.c
+insn_test_shl_X0_OBJECTS = insn_test_shl_X0.$(OBJEXT)
+insn_test_shl_X0_LDADD = $(LDADD)
+insn_test_shl_X1_SOURCES = insn_test_shl_X1.c
+insn_test_shl_X1_OBJECTS = insn_test_shl_X1.$(OBJEXT)
+insn_test_shl_X1_LDADD = $(LDADD)
+insn_test_shl_Y0_SOURCES = insn_test_shl_Y0.c
+insn_test_shl_Y0_OBJECTS = insn_test_shl_Y0.$(OBJEXT)
+insn_test_shl_Y0_LDADD = $(LDADD)
+insn_test_shl_Y1_SOURCES = insn_test_shl_Y1.c
+insn_test_shl_Y1_OBJECTS = insn_test_shl_Y1.$(OBJEXT)
+insn_test_shl_Y1_LDADD = $(LDADD)
+insn_test_shli_X0_SOURCES = insn_test_shli_X0.c
+insn_test_shli_X0_OBJECTS = insn_test_shli_X0.$(OBJEXT)
+insn_test_shli_X0_LDADD = $(LDADD)
+insn_test_shli_X1_SOURCES = insn_test_shli_X1.c
+insn_test_shli_X1_OBJECTS = insn_test_shli_X1.$(OBJEXT)
+insn_test_shli_X1_LDADD = $(LDADD)
+insn_test_shli_Y0_SOURCES = insn_test_shli_Y0.c
+insn_test_shli_Y0_OBJECTS = insn_test_shli_Y0.$(OBJEXT)
+insn_test_shli_Y0_LDADD = $(LDADD)
+insn_test_shli_Y1_SOURCES = insn_test_shli_Y1.c
+insn_test_shli_Y1_OBJECTS = insn_test_shli_Y1.$(OBJEXT)
+insn_test_shli_Y1_LDADD = $(LDADD)
+insn_test_shlx_X0_SOURCES = insn_test_shlx_X0.c
+insn_test_shlx_X0_OBJECTS = insn_test_shlx_X0.$(OBJEXT)
+insn_test_shlx_X0_LDADD = $(LDADD)
+insn_test_shlx_X1_SOURCES = insn_test_shlx_X1.c
+insn_test_shlx_X1_OBJECTS = insn_test_shlx_X1.$(OBJEXT)
+insn_test_shlx_X1_LDADD = $(LDADD)
+insn_test_shlxi_X0_SOURCES = insn_test_shlxi_X0.c
+insn_test_shlxi_X0_OBJECTS = insn_test_shlxi_X0.$(OBJEXT)
+insn_test_shlxi_X0_LDADD = $(LDADD)
+insn_test_shlxi_X1_SOURCES = insn_test_shlxi_X1.c
+insn_test_shlxi_X1_OBJECTS = insn_test_shlxi_X1.$(OBJEXT)
+insn_test_shlxi_X1_LDADD = $(LDADD)
+insn_test_shrs_X0_SOURCES = insn_test_shrs_X0.c
+insn_test_shrs_X0_OBJECTS = insn_test_shrs_X0.$(OBJEXT)
+insn_test_shrs_X0_LDADD = $(LDADD)
+insn_test_shrs_X1_SOURCES = insn_test_shrs_X1.c
+insn_test_shrs_X1_OBJECTS = insn_test_shrs_X1.$(OBJEXT)
+insn_test_shrs_X1_LDADD = $(LDADD)
+insn_test_shrs_Y0_SOURCES = insn_test_shrs_Y0.c
+insn_test_shrs_Y0_OBJECTS = insn_test_shrs_Y0.$(OBJEXT)
+insn_test_shrs_Y0_LDADD = $(LDADD)
+insn_test_shrs_Y1_SOURCES = insn_test_shrs_Y1.c
+insn_test_shrs_Y1_OBJECTS = insn_test_shrs_Y1.$(OBJEXT)
+insn_test_shrs_Y1_LDADD = $(LDADD)
+insn_test_shrsi_X0_SOURCES = insn_test_shrsi_X0.c
+insn_test_shrsi_X0_OBJECTS = insn_test_shrsi_X0.$(OBJEXT)
+insn_test_shrsi_X0_LDADD = $(LDADD)
+insn_test_shrsi_X1_SOURCES = insn_test_shrsi_X1.c
+insn_test_shrsi_X1_OBJECTS = insn_test_shrsi_X1.$(OBJEXT)
+insn_test_shrsi_X1_LDADD = $(LDADD)
+insn_test_shrsi_Y0_SOURCES = insn_test_shrsi_Y0.c
+insn_test_shrsi_Y0_OBJECTS = insn_test_shrsi_Y0.$(OBJEXT)
+insn_test_shrsi_Y0_LDADD = $(LDADD)
+insn_test_shrsi_Y1_SOURCES = insn_test_shrsi_Y1.c
+insn_test_shrsi_Y1_OBJECTS = insn_test_shrsi_Y1.$(OBJEXT)
+insn_test_shrsi_Y1_LDADD = $(LDADD)
+insn_test_shru_X0_SOURCES = insn_test_shru_X0.c
+insn_test_shru_X0_OBJECTS = insn_test_shru_X0.$(OBJEXT)
+insn_test_shru_X0_LDADD = $(LDADD)
+insn_test_shru_X1_SOURCES = insn_test_shru_X1.c
+insn_test_shru_X1_OBJECTS = insn_test_shru_X1.$(OBJEXT)
+insn_test_shru_X1_LDADD = $(LDADD)
+insn_test_shru_Y0_SOURCES = insn_test_shru_Y0.c
+insn_test_shru_Y0_OBJECTS = insn_test_shru_Y0.$(OBJEXT)
+insn_test_shru_Y0_LDADD = $(LDADD)
+insn_test_shru_Y1_SOURCES = insn_test_shru_Y1.c
+insn_test_shru_Y1_OBJECTS = insn_test_shru_Y1.$(OBJEXT)
+insn_test_shru_Y1_LDADD = $(LDADD)
+insn_test_shrui_X0_SOURCES = insn_test_shrui_X0.c
+insn_test_shrui_X0_OBJECTS = insn_test_shrui_X0.$(OBJEXT)
+insn_test_shrui_X0_LDADD = $(LDADD)
+insn_test_shrui_X1_SOURCES = insn_test_shrui_X1.c
+insn_test_shrui_X1_OBJECTS = insn_test_shrui_X1.$(OBJEXT)
+insn_test_shrui_X1_LDADD = $(LDADD)
+insn_test_shrui_Y0_SOURCES = insn_test_shrui_Y0.c
+insn_test_shrui_Y0_OBJECTS = insn_test_shrui_Y0.$(OBJEXT)
+insn_test_shrui_Y0_LDADD = $(LDADD)
+insn_test_shrui_Y1_SOURCES = insn_test_shrui_Y1.c
+insn_test_shrui_Y1_OBJECTS = insn_test_shrui_Y1.$(OBJEXT)
+insn_test_shrui_Y1_LDADD = $(LDADD)
+insn_test_shrux_X0_SOURCES = insn_test_shrux_X0.c
+insn_test_shrux_X0_OBJECTS = insn_test_shrux_X0.$(OBJEXT)
+insn_test_shrux_X0_LDADD = $(LDADD)
+insn_test_shrux_X1_SOURCES = insn_test_shrux_X1.c
+insn_test_shrux_X1_OBJECTS = insn_test_shrux_X1.$(OBJEXT)
+insn_test_shrux_X1_LDADD = $(LDADD)
+insn_test_shufflebytes_X0_SOURCES = insn_test_shufflebytes_X0.c
+insn_test_shufflebytes_X0_OBJECTS = \
+ insn_test_shufflebytes_X0.$(OBJEXT)
+insn_test_shufflebytes_X0_LDADD = $(LDADD)
+insn_test_st1_X1_SOURCES = insn_test_st1_X1.c
+insn_test_st1_X1_OBJECTS = insn_test_st1_X1.$(OBJEXT)
+insn_test_st1_X1_LDADD = $(LDADD)
+insn_test_st1_Y2_SOURCES = insn_test_st1_Y2.c
+insn_test_st1_Y2_OBJECTS = insn_test_st1_Y2.$(OBJEXT)
+insn_test_st1_Y2_LDADD = $(LDADD)
+insn_test_st1_add_X1_SOURCES = insn_test_st1_add_X1.c
+insn_test_st1_add_X1_OBJECTS = insn_test_st1_add_X1.$(OBJEXT)
+insn_test_st1_add_X1_LDADD = $(LDADD)
+insn_test_st2_X1_SOURCES = insn_test_st2_X1.c
+insn_test_st2_X1_OBJECTS = insn_test_st2_X1.$(OBJEXT)
+insn_test_st2_X1_LDADD = $(LDADD)
+insn_test_st2_Y2_SOURCES = insn_test_st2_Y2.c
+insn_test_st2_Y2_OBJECTS = insn_test_st2_Y2.$(OBJEXT)
+insn_test_st2_Y2_LDADD = $(LDADD)
+insn_test_st2_add_X1_SOURCES = insn_test_st2_add_X1.c
+insn_test_st2_add_X1_OBJECTS = insn_test_st2_add_X1.$(OBJEXT)
+insn_test_st2_add_X1_LDADD = $(LDADD)
+insn_test_st4_X1_SOURCES = insn_test_st4_X1.c
+insn_test_st4_X1_OBJECTS = insn_test_st4_X1.$(OBJEXT)
+insn_test_st4_X1_LDADD = $(LDADD)
+insn_test_st4_Y2_SOURCES = insn_test_st4_Y2.c
+insn_test_st4_Y2_OBJECTS = insn_test_st4_Y2.$(OBJEXT)
+insn_test_st4_Y2_LDADD = $(LDADD)
+insn_test_st4_add_X1_SOURCES = insn_test_st4_add_X1.c
+insn_test_st4_add_X1_OBJECTS = insn_test_st4_add_X1.$(OBJEXT)
+insn_test_st4_add_X1_LDADD = $(LDADD)
+insn_test_st_X1_SOURCES = insn_test_st_X1.c
+insn_test_st_X1_OBJECTS = insn_test_st_X1.$(OBJEXT)
+insn_test_st_X1_LDADD = $(LDADD)
+insn_test_st_Y2_SOURCES = insn_test_st_Y2.c
+insn_test_st_Y2_OBJECTS = insn_test_st_Y2.$(OBJEXT)
+insn_test_st_Y2_LDADD = $(LDADD)
+insn_test_st_add_X1_SOURCES = insn_test_st_add_X1.c
+insn_test_st_add_X1_OBJECTS = insn_test_st_add_X1.$(OBJEXT)
+insn_test_st_add_X1_LDADD = $(LDADD)
+insn_test_stnt1_X1_SOURCES = insn_test_stnt1_X1.c
+insn_test_stnt1_X1_OBJECTS = insn_test_stnt1_X1.$(OBJEXT)
+insn_test_stnt1_X1_LDADD = $(LDADD)
+insn_test_stnt2_X1_SOURCES = insn_test_stnt2_X1.c
+insn_test_stnt2_X1_OBJECTS = insn_test_stnt2_X1.$(OBJEXT)
+insn_test_stnt2_X1_LDADD = $(LDADD)
+insn_test_stnt2_add_X1_SOURCES = insn_test_stnt2_add_X1.c
+insn_test_stnt2_add_X1_OBJECTS = insn_test_stnt2_add_X1.$(OBJEXT)
+insn_test_stnt2_add_X1_LDADD = $(LDADD)
+insn_test_stnt4_X1_SOURCES = insn_test_stnt4_X1.c
+insn_test_stnt4_X1_OBJECTS = insn_test_stnt4_X1.$(OBJEXT)
+insn_test_stnt4_X1_LDADD = $(LDADD)
+insn_test_stnt4_add_X1_SOURCES = insn_test_stnt4_add_X1.c
+insn_test_stnt4_add_X1_OBJECTS = insn_test_stnt4_add_X1.$(OBJEXT)
+insn_test_stnt4_add_X1_LDADD = $(LDADD)
+insn_test_stnt_X1_SOURCES = insn_test_stnt_X1.c
+insn_test_stnt_X1_OBJECTS = insn_test_stnt_X1.$(OBJEXT)
+insn_test_stnt_X1_LDADD = $(LDADD)
+insn_test_stnt_add_X1_SOURCES = insn_test_stnt_add_X1.c
+insn_test_stnt_add_X1_OBJECTS = insn_test_stnt_add_X1.$(OBJEXT)
+insn_test_stnt_add_X1_LDADD = $(LDADD)
+insn_test_sub_X0_SOURCES = insn_test_sub_X0.c
+insn_test_sub_X0_OBJECTS = insn_test_sub_X0.$(OBJEXT)
+insn_test_sub_X0_LDADD = $(LDADD)
+insn_test_sub_X1_SOURCES = insn_test_sub_X1.c
+insn_test_sub_X1_OBJECTS = insn_test_sub_X1.$(OBJEXT)
+insn_test_sub_X1_LDADD = $(LDADD)
+insn_test_sub_Y0_SOURCES = insn_test_sub_Y0.c
+insn_test_sub_Y0_OBJECTS = insn_test_sub_Y0.$(OBJEXT)
+insn_test_sub_Y0_LDADD = $(LDADD)
+insn_test_sub_Y1_SOURCES = insn_test_sub_Y1.c
+insn_test_sub_Y1_OBJECTS = insn_test_sub_Y1.$(OBJEXT)
+insn_test_sub_Y1_LDADD = $(LDADD)
+insn_test_subx_X0_SOURCES = insn_test_subx_X0.c
+insn_test_subx_X0_OBJECTS = insn_test_subx_X0.$(OBJEXT)
+insn_test_subx_X0_LDADD = $(LDADD)
+insn_test_subx_X1_SOURCES = insn_test_subx_X1.c
+insn_test_subx_X1_OBJECTS = insn_test_subx_X1.$(OBJEXT)
+insn_test_subx_X1_LDADD = $(LDADD)
+insn_test_subx_Y0_SOURCES = insn_test_subx_Y0.c
+insn_test_subx_Y0_OBJECTS = insn_test_subx_Y0.$(OBJEXT)
+insn_test_subx_Y0_LDADD = $(LDADD)
+insn_test_subx_Y1_SOURCES = insn_test_subx_Y1.c
+insn_test_subx_Y1_OBJECTS = insn_test_subx_Y1.$(OBJEXT)
+insn_test_subx_Y1_LDADD = $(LDADD)
+insn_test_tblidxb0_X0_SOURCES = insn_test_tblidxb0_X0.c
+insn_test_tblidxb0_X0_OBJECTS = insn_test_tblidxb0_X0.$(OBJEXT)
+insn_test_tblidxb0_X0_LDADD = $(LDADD)
+insn_test_tblidxb0_Y0_SOURCES = insn_test_tblidxb0_Y0.c
+insn_test_tblidxb0_Y0_OBJECTS = insn_test_tblidxb0_Y0.$(OBJEXT)
+insn_test_tblidxb0_Y0_LDADD = $(LDADD)
+insn_test_tblidxb1_X0_SOURCES = insn_test_tblidxb1_X0.c
+insn_test_tblidxb1_X0_OBJECTS = insn_test_tblidxb1_X0.$(OBJEXT)
+insn_test_tblidxb1_X0_LDADD = $(LDADD)
+insn_test_tblidxb1_Y0_SOURCES = insn_test_tblidxb1_Y0.c
+insn_test_tblidxb1_Y0_OBJECTS = insn_test_tblidxb1_Y0.$(OBJEXT)
+insn_test_tblidxb1_Y0_LDADD = $(LDADD)
+insn_test_tblidxb2_X0_SOURCES = insn_test_tblidxb2_X0.c
+insn_test_tblidxb2_X0_OBJECTS = insn_test_tblidxb2_X0.$(OBJEXT)
+insn_test_tblidxb2_X0_LDADD = $(LDADD)
+insn_test_tblidxb2_Y0_SOURCES = insn_test_tblidxb2_Y0.c
+insn_test_tblidxb2_Y0_OBJECTS = insn_test_tblidxb2_Y0.$(OBJEXT)
+insn_test_tblidxb2_Y0_LDADD = $(LDADD)
+insn_test_tblidxb3_X0_SOURCES = insn_test_tblidxb3_X0.c
+insn_test_tblidxb3_X0_OBJECTS = insn_test_tblidxb3_X0.$(OBJEXT)
+insn_test_tblidxb3_X0_LDADD = $(LDADD)
+insn_test_tblidxb3_Y0_SOURCES = insn_test_tblidxb3_Y0.c
+insn_test_tblidxb3_Y0_OBJECTS = insn_test_tblidxb3_Y0.$(OBJEXT)
+insn_test_tblidxb3_Y0_LDADD = $(LDADD)
+insn_test_v1add_X0_SOURCES = insn_test_v1add_X0.c
+insn_test_v1add_X0_OBJECTS = insn_test_v1add_X0.$(OBJEXT)
+insn_test_v1add_X0_LDADD = $(LDADD)
+insn_test_v1add_X1_SOURCES = insn_test_v1add_X1.c
+insn_test_v1add_X1_OBJECTS = insn_test_v1add_X1.$(OBJEXT)
+insn_test_v1add_X1_LDADD = $(LDADD)
+insn_test_v1adduc_X0_SOURCES = insn_test_v1adduc_X0.c
+insn_test_v1adduc_X0_OBJECTS = insn_test_v1adduc_X0.$(OBJEXT)
+insn_test_v1adduc_X0_LDADD = $(LDADD)
+insn_test_v1adduc_X1_SOURCES = insn_test_v1adduc_X1.c
+insn_test_v1adduc_X1_OBJECTS = insn_test_v1adduc_X1.$(OBJEXT)
+insn_test_v1adduc_X1_LDADD = $(LDADD)
+insn_test_v1adiffu_X0_SOURCES = insn_test_v1adiffu_X0.c
+insn_test_v1adiffu_X0_OBJECTS = insn_test_v1adiffu_X0.$(OBJEXT)
+insn_test_v1adiffu_X0_LDADD = $(LDADD)
+insn_test_v1avgu_X0_SOURCES = insn_test_v1avgu_X0.c
+insn_test_v1avgu_X0_OBJECTS = insn_test_v1avgu_X0.$(OBJEXT)
+insn_test_v1avgu_X0_LDADD = $(LDADD)
+insn_test_v1cmpeq_X0_SOURCES = insn_test_v1cmpeq_X0.c
+insn_test_v1cmpeq_X0_OBJECTS = insn_test_v1cmpeq_X0.$(OBJEXT)
+insn_test_v1cmpeq_X0_LDADD = $(LDADD)
+insn_test_v1cmpeq_X1_SOURCES = insn_test_v1cmpeq_X1.c
+insn_test_v1cmpeq_X1_OBJECTS = insn_test_v1cmpeq_X1.$(OBJEXT)
+insn_test_v1cmpeq_X1_LDADD = $(LDADD)
+insn_test_v1cmpeqi_X0_SOURCES = insn_test_v1cmpeqi_X0.c
+insn_test_v1cmpeqi_X0_OBJECTS = insn_test_v1cmpeqi_X0.$(OBJEXT)
+insn_test_v1cmpeqi_X0_LDADD = $(LDADD)
+insn_test_v1cmpeqi_X1_SOURCES = insn_test_v1cmpeqi_X1.c
+insn_test_v1cmpeqi_X1_OBJECTS = insn_test_v1cmpeqi_X1.$(OBJEXT)
+insn_test_v1cmpeqi_X1_LDADD = $(LDADD)
+insn_test_v1cmples_X0_SOURCES = insn_test_v1cmples_X0.c
+insn_test_v1cmples_X0_OBJECTS = insn_test_v1cmples_X0.$(OBJEXT)
+insn_test_v1cmples_X0_LDADD = $(LDADD)
+insn_test_v1cmples_X1_SOURCES = insn_test_v1cmples_X1.c
+insn_test_v1cmples_X1_OBJECTS = insn_test_v1cmples_X1.$(OBJEXT)
+insn_test_v1cmples_X1_LDADD = $(LDADD)
+insn_test_v1cmpleu_X0_SOURCES = insn_test_v1cmpleu_X0.c
+insn_test_v1cmpleu_X0_OBJECTS = insn_test_v1cmpleu_X0.$(OBJEXT)
+insn_test_v1cmpleu_X0_LDADD = $(LDADD)
+insn_test_v1cmpleu_X1_SOURCES = insn_test_v1cmpleu_X1.c
+insn_test_v1cmpleu_X1_OBJECTS = insn_test_v1cmpleu_X1.$(OBJEXT)
+insn_test_v1cmpleu_X1_LDADD = $(LDADD)
+insn_test_v1cmplts_X0_SOURCES = insn_test_v1cmplts_X0.c
+insn_test_v1cmplts_X0_OBJECTS = insn_test_v1cmplts_X0.$(OBJEXT)
+insn_test_v1cmplts_X0_LDADD = $(LDADD)
+insn_test_v1cmplts_X1_SOURCES = insn_test_v1cmplts_X1.c
+insn_test_v1cmplts_X1_OBJECTS = insn_test_v1cmplts_X1.$(OBJEXT)
+insn_test_v1cmplts_X1_LDADD = $(LDADD)
+insn_test_v1cmpltu_X0_SOURCES = insn_test_v1cmpltu_X0.c
+insn_test_v1cmpltu_X0_OBJECTS = insn_test_v1cmpltu_X0.$(OBJEXT)
+insn_test_v1cmpltu_X0_LDADD = $(LDADD)
+insn_test_v1cmpltu_X1_SOURCES = insn_test_v1cmpltu_X1.c
+insn_test_v1cmpltu_X1_OBJECTS = insn_test_v1cmpltu_X1.$(OBJEXT)
+insn_test_v1cmpltu_X1_LDADD = $(LDADD)
+insn_test_v1cmpne_X0_SOURCES = insn_test_v1cmpne_X0.c
+insn_test_v1cmpne_X0_OBJECTS = insn_test_v1cmpne_X0.$(OBJEXT)
+insn_test_v1cmpne_X0_LDADD = $(LDADD)
+insn_test_v1cmpne_X1_SOURCES = insn_test_v1cmpne_X1.c
+insn_test_v1cmpne_X1_OBJECTS = insn_test_v1cmpne_X1.$(OBJEXT)
+insn_test_v1cmpne_X1_LDADD = $(LDADD)
+insn_test_v1ddotpu_X0_SOURCES = insn_test_v1ddotpu_X0.c
+insn_test_v1ddotpu_X0_OBJECTS = insn_test_v1ddotpu_X0.$(OBJEXT)
+insn_test_v1ddotpu_X0_LDADD = $(LDADD)
+insn_test_v1ddotpua_X0_SOURCES = insn_test_v1ddotpua_X0.c
+insn_test_v1ddotpua_X0_OBJECTS = insn_test_v1ddotpua_X0.$(OBJEXT)
+insn_test_v1ddotpua_X0_LDADD = $(LDADD)
+insn_test_v1ddotpus_X0_SOURCES = insn_test_v1ddotpus_X0.c
+insn_test_v1ddotpus_X0_OBJECTS = insn_test_v1ddotpus_X0.$(OBJEXT)
+insn_test_v1ddotpus_X0_LDADD = $(LDADD)
+insn_test_v1ddotpusa_X0_SOURCES = insn_test_v1ddotpusa_X0.c
+insn_test_v1ddotpusa_X0_OBJECTS = insn_test_v1ddotpusa_X0.$(OBJEXT)
+insn_test_v1ddotpusa_X0_LDADD = $(LDADD)
+insn_test_v1dotp_X0_SOURCES = insn_test_v1dotp_X0.c
+insn_test_v1dotp_X0_OBJECTS = insn_test_v1dotp_X0.$(OBJEXT)
+insn_test_v1dotp_X0_LDADD = $(LDADD)
+insn_test_v1dotpa_X0_SOURCES = insn_test_v1dotpa_X0.c
+insn_test_v1dotpa_X0_OBJECTS = insn_test_v1dotpa_X0.$(OBJEXT)
+insn_test_v1dotpa_X0_LDADD = $(LDADD)
+insn_test_v1dotpu_X0_SOURCES = insn_test_v1dotpu_X0.c
+insn_test_v1dotpu_X0_OBJECTS = insn_test_v1dotpu_X0.$(OBJEXT)
+insn_test_v1dotpu_X0_LDADD = $(LDADD)
+insn_test_v1dotpua_X0_SOURCES = insn_test_v1dotpua_X0.c
+insn_test_v1dotpua_X0_OBJECTS = insn_test_v1dotpua_X0.$(OBJEXT)
+insn_test_v1dotpua_X0_LDADD = $(LDADD)
+insn_test_v1dotpus_X0_SOURCES = insn_test_v1dotpus_X0.c
+insn_test_v1dotpus_X0_OBJECTS = insn_test_v1dotpus_X0.$(OBJEXT)
+insn_test_v1dotpus_X0_LDADD = $(LDADD)
+insn_test_v1dotpusa_X0_SOURCES = insn_test_v1dotpusa_X0.c
+insn_test_v1dotpusa_X0_OBJECTS = insn_test_v1dotpusa_X0.$(OBJEXT)
+insn_test_v1dotpusa_X0_LDADD = $(LDADD)
+insn_test_v1int_h_X0_SOURCES = insn_test_v1int_h_X0.c
+insn_test_v1int_h_X0_OBJECTS = insn_test_v1int_h_X0.$(OBJEXT)
+insn_test_v1int_h_X0_LDADD = $(LDADD)
+insn_test_v1int_h_X1_SOURCES = insn_test_v1int_h_X1.c
+insn_test_v1int_h_X1_OBJECTS = insn_test_v1int_h_X1.$(OBJEXT)
+insn_test_v1int_h_X1_LDADD = $(LDADD)
+insn_test_v1int_l_X0_SOURCES = insn_test_v1int_l_X0.c
+insn_test_v1int_l_X0_OBJECTS = insn_test_v1int_l_X0.$(OBJEXT)
+insn_test_v1int_l_X0_LDADD = $(LDADD)
+insn_test_v1int_l_X1_SOURCES = insn_test_v1int_l_X1.c
+insn_test_v1int_l_X1_OBJECTS = insn_test_v1int_l_X1.$(OBJEXT)
+insn_test_v1int_l_X1_LDADD = $(LDADD)
+insn_test_v1maxu_X0_SOURCES = insn_test_v1maxu_X0.c
+insn_test_v1maxu_X0_OBJECTS = insn_test_v1maxu_X0.$(OBJEXT)
+insn_test_v1maxu_X0_LDADD = $(LDADD)
+insn_test_v1maxu_X1_SOURCES = insn_test_v1maxu_X1.c
+insn_test_v1maxu_X1_OBJECTS = insn_test_v1maxu_X1.$(OBJEXT)
+insn_test_v1maxu_X1_LDADD = $(LDADD)
+insn_test_v1minu_X0_SOURCES = insn_test_v1minu_X0.c
+insn_test_v1minu_X0_OBJECTS = insn_test_v1minu_X0.$(OBJEXT)
+insn_test_v1minu_X0_LDADD = $(LDADD)
+insn_test_v1minu_X1_SOURCES = insn_test_v1minu_X1.c
+insn_test_v1minu_X1_OBJECTS = insn_test_v1minu_X1.$(OBJEXT)
+insn_test_v1minu_X1_LDADD = $(LDADD)
+insn_test_v1mnz_X0_SOURCES = insn_test_v1mnz_X0.c
+insn_test_v1mnz_X0_OBJECTS = insn_test_v1mnz_X0.$(OBJEXT)
+insn_test_v1mnz_X0_LDADD = $(LDADD)
+insn_test_v1mnz_X1_SOURCES = insn_test_v1mnz_X1.c
+insn_test_v1mnz_X1_OBJECTS = insn_test_v1mnz_X1.$(OBJEXT)
+insn_test_v1mnz_X1_LDADD = $(LDADD)
+insn_test_v1multu_X0_SOURCES = insn_test_v1multu_X0.c
+insn_test_v1multu_X0_OBJECTS = insn_test_v1multu_X0.$(OBJEXT)
+insn_test_v1multu_X0_LDADD = $(LDADD)
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+insn_test_v1mulu_X0_OBJECTS = insn_test_v1mulu_X0.$(OBJEXT)
+insn_test_v1mulu_X0_LDADD = $(LDADD)
+insn_test_v1mulus_X0_SOURCES = insn_test_v1mulus_X0.c
+insn_test_v1mulus_X0_OBJECTS = insn_test_v1mulus_X0.$(OBJEXT)
+insn_test_v1mulus_X0_LDADD = $(LDADD)
+insn_test_v1mz_X0_SOURCES = insn_test_v1mz_X0.c
+insn_test_v1mz_X0_OBJECTS = insn_test_v1mz_X0.$(OBJEXT)
+insn_test_v1mz_X0_LDADD = $(LDADD)
+insn_test_v1mz_X1_SOURCES = insn_test_v1mz_X1.c
+insn_test_v1mz_X1_OBJECTS = insn_test_v1mz_X1.$(OBJEXT)
+insn_test_v1mz_X1_LDADD = $(LDADD)
+insn_test_v1sadau_X0_SOURCES = insn_test_v1sadau_X0.c
+insn_test_v1sadau_X0_OBJECTS = insn_test_v1sadau_X0.$(OBJEXT)
+insn_test_v1sadau_X0_LDADD = $(LDADD)
+insn_test_v1sadu_X0_SOURCES = insn_test_v1sadu_X0.c
+insn_test_v1sadu_X0_OBJECTS = insn_test_v1sadu_X0.$(OBJEXT)
+insn_test_v1sadu_X0_LDADD = $(LDADD)
+insn_test_v1shl_X0_SOURCES = insn_test_v1shl_X0.c
+insn_test_v1shl_X0_OBJECTS = insn_test_v1shl_X0.$(OBJEXT)
+insn_test_v1shl_X0_LDADD = $(LDADD)
+insn_test_v1shl_X1_SOURCES = insn_test_v1shl_X1.c
+insn_test_v1shl_X1_OBJECTS = insn_test_v1shl_X1.$(OBJEXT)
+insn_test_v1shl_X1_LDADD = $(LDADD)
+insn_test_v1shli_X0_SOURCES = insn_test_v1shli_X0.c
+insn_test_v1shli_X0_OBJECTS = insn_test_v1shli_X0.$(OBJEXT)
+insn_test_v1shli_X0_LDADD = $(LDADD)
+insn_test_v1shli_X1_SOURCES = insn_test_v1shli_X1.c
+insn_test_v1shli_X1_OBJECTS = insn_test_v1shli_X1.$(OBJEXT)
+insn_test_v1shli_X1_LDADD = $(LDADD)
+insn_test_v1shrs_X0_SOURCES = insn_test_v1shrs_X0.c
+insn_test_v1shrs_X0_OBJECTS = insn_test_v1shrs_X0.$(OBJEXT)
+insn_test_v1shrs_X0_LDADD = $(LDADD)
+insn_test_v1shrs_X1_SOURCES = insn_test_v1shrs_X1.c
+insn_test_v1shrs_X1_OBJECTS = insn_test_v1shrs_X1.$(OBJEXT)
+insn_test_v1shrs_X1_LDADD = $(LDADD)
+insn_test_v1shrsi_X0_SOURCES = insn_test_v1shrsi_X0.c
+insn_test_v1shrsi_X0_OBJECTS = insn_test_v1shrsi_X0.$(OBJEXT)
+insn_test_v1shrsi_X0_LDADD = $(LDADD)
+insn_test_v1shrsi_X1_SOURCES = insn_test_v1shrsi_X1.c
+insn_test_v1shrsi_X1_OBJECTS = insn_test_v1shrsi_X1.$(OBJEXT)
+insn_test_v1shrsi_X1_LDADD = $(LDADD)
+insn_test_v1shru_X0_SOURCES = insn_test_v1shru_X0.c
+insn_test_v1shru_X0_OBJECTS = insn_test_v1shru_X0.$(OBJEXT)
+insn_test_v1shru_X0_LDADD = $(LDADD)
+insn_test_v1shru_X1_SOURCES = insn_test_v1shru_X1.c
+insn_test_v1shru_X1_OBJECTS = insn_test_v1shru_X1.$(OBJEXT)
+insn_test_v1shru_X1_LDADD = $(LDADD)
+insn_test_v1shrui_X0_SOURCES = insn_test_v1shrui_X0.c
+insn_test_v1shrui_X0_OBJECTS = insn_test_v1shrui_X0.$(OBJEXT)
+insn_test_v1shrui_X0_LDADD = $(LDADD)
+insn_test_v1shrui_X1_SOURCES = insn_test_v1shrui_X1.c
+insn_test_v1shrui_X1_OBJECTS = insn_test_v1shrui_X1.$(OBJEXT)
+insn_test_v1shrui_X1_LDADD = $(LDADD)
+insn_test_v1sub_X0_SOURCES = insn_test_v1sub_X0.c
+insn_test_v1sub_X0_OBJECTS = insn_test_v1sub_X0.$(OBJEXT)
+insn_test_v1sub_X0_LDADD = $(LDADD)
+insn_test_v1sub_X1_SOURCES = insn_test_v1sub_X1.c
+insn_test_v1sub_X1_OBJECTS = insn_test_v1sub_X1.$(OBJEXT)
+insn_test_v1sub_X1_LDADD = $(LDADD)
+insn_test_v1subuc_X0_SOURCES = insn_test_v1subuc_X0.c
+insn_test_v1subuc_X0_OBJECTS = insn_test_v1subuc_X0.$(OBJEXT)
+insn_test_v1subuc_X0_LDADD = $(LDADD)
+insn_test_v1subuc_X1_SOURCES = insn_test_v1subuc_X1.c
+insn_test_v1subuc_X1_OBJECTS = insn_test_v1subuc_X1.$(OBJEXT)
+insn_test_v1subuc_X1_LDADD = $(LDADD)
+insn_test_v2add_X0_SOURCES = insn_test_v2add_X0.c
+insn_test_v2add_X0_OBJECTS = insn_test_v2add_X0.$(OBJEXT)
+insn_test_v2add_X0_LDADD = $(LDADD)
+insn_test_v2add_X1_SOURCES = insn_test_v2add_X1.c
+insn_test_v2add_X1_OBJECTS = insn_test_v2add_X1.$(OBJEXT)
+insn_test_v2add_X1_LDADD = $(LDADD)
+insn_test_v2addsc_X0_SOURCES = insn_test_v2addsc_X0.c
+insn_test_v2addsc_X0_OBJECTS = insn_test_v2addsc_X0.$(OBJEXT)
+insn_test_v2addsc_X0_LDADD = $(LDADD)
+insn_test_v2addsc_X1_SOURCES = insn_test_v2addsc_X1.c
+insn_test_v2addsc_X1_OBJECTS = insn_test_v2addsc_X1.$(OBJEXT)
+insn_test_v2addsc_X1_LDADD = $(LDADD)
+insn_test_v2adiffs_X0_SOURCES = insn_test_v2adiffs_X0.c
+insn_test_v2adiffs_X0_OBJECTS = insn_test_v2adiffs_X0.$(OBJEXT)
+insn_test_v2adiffs_X0_LDADD = $(LDADD)
+insn_test_v2avgs_X0_SOURCES = insn_test_v2avgs_X0.c
+insn_test_v2avgs_X0_OBJECTS = insn_test_v2avgs_X0.$(OBJEXT)
+insn_test_v2avgs_X0_LDADD = $(LDADD)
+insn_test_v2cmpeq_X0_SOURCES = insn_test_v2cmpeq_X0.c
+insn_test_v2cmpeq_X0_OBJECTS = insn_test_v2cmpeq_X0.$(OBJEXT)
+insn_test_v2cmpeq_X0_LDADD = $(LDADD)
+insn_test_v2cmpeq_X1_SOURCES = insn_test_v2cmpeq_X1.c
+insn_test_v2cmpeq_X1_OBJECTS = insn_test_v2cmpeq_X1.$(OBJEXT)
+insn_test_v2cmpeq_X1_LDADD = $(LDADD)
+insn_test_v2cmpeqi_X0_SOURCES = insn_test_v2cmpeqi_X0.c
+insn_test_v2cmpeqi_X0_OBJECTS = insn_test_v2cmpeqi_X0.$(OBJEXT)
+insn_test_v2cmpeqi_X0_LDADD = $(LDADD)
+insn_test_v2cmpeqi_X1_SOURCES = insn_test_v2cmpeqi_X1.c
+insn_test_v2cmpeqi_X1_OBJECTS = insn_test_v2cmpeqi_X1.$(OBJEXT)
+insn_test_v2cmpeqi_X1_LDADD = $(LDADD)
+insn_test_v2cmples_X0_SOURCES = insn_test_v2cmples_X0.c
+insn_test_v2cmples_X0_OBJECTS = insn_test_v2cmples_X0.$(OBJEXT)
+insn_test_v2cmples_X0_LDADD = $(LDADD)
+insn_test_v2cmples_X1_SOURCES = insn_test_v2cmples_X1.c
+insn_test_v2cmples_X1_OBJECTS = insn_test_v2cmples_X1.$(OBJEXT)
+insn_test_v2cmples_X1_LDADD = $(LDADD)
+insn_test_v2cmpleu_X0_SOURCES = insn_test_v2cmpleu_X0.c
+insn_test_v2cmpleu_X0_OBJECTS = insn_test_v2cmpleu_X0.$(OBJEXT)
+insn_test_v2cmpleu_X0_LDADD = $(LDADD)
+insn_test_v2cmpleu_X1_SOURCES = insn_test_v2cmpleu_X1.c
+insn_test_v2cmpleu_X1_OBJECTS = insn_test_v2cmpleu_X1.$(OBJEXT)
+insn_test_v2cmpleu_X1_LDADD = $(LDADD)
+insn_test_v2cmplts_X0_SOURCES = insn_test_v2cmplts_X0.c
+insn_test_v2cmplts_X0_OBJECTS = insn_test_v2cmplts_X0.$(OBJEXT)
+insn_test_v2cmplts_X0_LDADD = $(LDADD)
+insn_test_v2cmplts_X1_SOURCES = insn_test_v2cmplts_X1.c
+insn_test_v2cmplts_X1_OBJECTS = insn_test_v2cmplts_X1.$(OBJEXT)
+insn_test_v2cmplts_X1_LDADD = $(LDADD)
+insn_test_v2cmpltsi_X0_SOURCES = insn_test_v2cmpltsi_X0.c
+insn_test_v2cmpltsi_X0_OBJECTS = insn_test_v2cmpltsi_X0.$(OBJEXT)
+insn_test_v2cmpltsi_X0_LDADD = $(LDADD)
+insn_test_v2cmpltsi_X1_SOURCES = insn_test_v2cmpltsi_X1.c
+insn_test_v2cmpltsi_X1_OBJECTS = insn_test_v2cmpltsi_X1.$(OBJEXT)
+insn_test_v2cmpltsi_X1_LDADD = $(LDADD)
+insn_test_v2cmpltu_X0_SOURCES = insn_test_v2cmpltu_X0.c
+insn_test_v2cmpltu_X0_OBJECTS = insn_test_v2cmpltu_X0.$(OBJEXT)
+insn_test_v2cmpltu_X0_LDADD = $(LDADD)
+insn_test_v2cmpltu_X1_SOURCES = insn_test_v2cmpltu_X1.c
+insn_test_v2cmpltu_X1_OBJECTS = insn_test_v2cmpltu_X1.$(OBJEXT)
+insn_test_v2cmpltu_X1_LDADD = $(LDADD)
+insn_test_v2cmpltui_X0_SOURCES = insn_test_v2cmpltui_X0.c
+insn_test_v2cmpltui_X0_OBJECTS = insn_test_v2cmpltui_X0.$(OBJEXT)
+insn_test_v2cmpltui_X0_LDADD = $(LDADD)
+insn_test_v2cmpltui_X1_SOURCES = insn_test_v2cmpltui_X1.c
+insn_test_v2cmpltui_X1_OBJECTS = insn_test_v2cmpltui_X1.$(OBJEXT)
+insn_test_v2cmpltui_X1_LDADD = $(LDADD)
+insn_test_v2cmpne_X0_SOURCES = insn_test_v2cmpne_X0.c
+insn_test_v2cmpne_X0_OBJECTS = insn_test_v2cmpne_X0.$(OBJEXT)
+insn_test_v2cmpne_X0_LDADD = $(LDADD)
+insn_test_v2cmpne_X1_SOURCES = insn_test_v2cmpne_X1.c
+insn_test_v2cmpne_X1_OBJECTS = insn_test_v2cmpne_X1.$(OBJEXT)
+insn_test_v2cmpne_X1_LDADD = $(LDADD)
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+insn_test_v2dotp_X0_OBJECTS = insn_test_v2dotp_X0.$(OBJEXT)
+insn_test_v2dotp_X0_LDADD = $(LDADD)
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+insn_test_v2dotpa_X0_OBJECTS = insn_test_v2dotpa_X0.$(OBJEXT)
+insn_test_v2dotpa_X0_LDADD = $(LDADD)
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+insn_test_v2int_h_X0_OBJECTS = insn_test_v2int_h_X0.$(OBJEXT)
+insn_test_v2int_h_X0_LDADD = $(LDADD)
+insn_test_v2int_h_X1_SOURCES = insn_test_v2int_h_X1.c
+insn_test_v2int_h_X1_OBJECTS = insn_test_v2int_h_X1.$(OBJEXT)
+insn_test_v2int_h_X1_LDADD = $(LDADD)
+insn_test_v2int_l_X0_SOURCES = insn_test_v2int_l_X0.c
+insn_test_v2int_l_X0_OBJECTS = insn_test_v2int_l_X0.$(OBJEXT)
+insn_test_v2int_l_X0_LDADD = $(LDADD)
+insn_test_v2int_l_X1_SOURCES = insn_test_v2int_l_X1.c
+insn_test_v2int_l_X1_OBJECTS = insn_test_v2int_l_X1.$(OBJEXT)
+insn_test_v2int_l_X1_LDADD = $(LDADD)
+insn_test_v2maxs_X0_SOURCES = insn_test_v2maxs_X0.c
+insn_test_v2maxs_X0_OBJECTS = insn_test_v2maxs_X0.$(OBJEXT)
+insn_test_v2maxs_X0_LDADD = $(LDADD)
+insn_test_v2maxs_X1_SOURCES = insn_test_v2maxs_X1.c
+insn_test_v2maxs_X1_OBJECTS = insn_test_v2maxs_X1.$(OBJEXT)
+insn_test_v2maxs_X1_LDADD = $(LDADD)
+insn_test_v2mins_X0_SOURCES = insn_test_v2mins_X0.c
+insn_test_v2mins_X0_OBJECTS = insn_test_v2mins_X0.$(OBJEXT)
+insn_test_v2mins_X0_LDADD = $(LDADD)
+insn_test_v2mins_X1_SOURCES = insn_test_v2mins_X1.c
+insn_test_v2mins_X1_OBJECTS = insn_test_v2mins_X1.$(OBJEXT)
+insn_test_v2mins_X1_LDADD = $(LDADD)
+insn_test_v2mnz_X0_SOURCES = insn_test_v2mnz_X0.c
+insn_test_v2mnz_X0_OBJECTS = insn_test_v2mnz_X0.$(OBJEXT)
+insn_test_v2mnz_X0_LDADD = $(LDADD)
+insn_test_v2mnz_X1_SOURCES = insn_test_v2mnz_X1.c
+insn_test_v2mnz_X1_OBJECTS = insn_test_v2mnz_X1.$(OBJEXT)
+insn_test_v2mnz_X1_LDADD = $(LDADD)
+insn_test_v2mulfsc_X0_SOURCES = insn_test_v2mulfsc_X0.c
+insn_test_v2mulfsc_X0_OBJECTS = insn_test_v2mulfsc_X0.$(OBJEXT)
+insn_test_v2mulfsc_X0_LDADD = $(LDADD)
+insn_test_v2muls_X0_SOURCES = insn_test_v2muls_X0.c
+insn_test_v2muls_X0_OBJECTS = insn_test_v2muls_X0.$(OBJEXT)
+insn_test_v2muls_X0_LDADD = $(LDADD)
+insn_test_v2mults_X0_SOURCES = insn_test_v2mults_X0.c
+insn_test_v2mults_X0_OBJECTS = insn_test_v2mults_X0.$(OBJEXT)
+insn_test_v2mults_X0_LDADD = $(LDADD)
+insn_test_v2mz_X0_SOURCES = insn_test_v2mz_X0.c
+insn_test_v2mz_X0_OBJECTS = insn_test_v2mz_X0.$(OBJEXT)
+insn_test_v2mz_X0_LDADD = $(LDADD)
+insn_test_v2mz_X1_SOURCES = insn_test_v2mz_X1.c
+insn_test_v2mz_X1_OBJECTS = insn_test_v2mz_X1.$(OBJEXT)
+insn_test_v2mz_X1_LDADD = $(LDADD)
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+insn_test_v2packh_X0_OBJECTS = insn_test_v2packh_X0.$(OBJEXT)
+insn_test_v2packh_X0_LDADD = $(LDADD)
+insn_test_v2packh_X1_SOURCES = insn_test_v2packh_X1.c
+insn_test_v2packh_X1_OBJECTS = insn_test_v2packh_X1.$(OBJEXT)
+insn_test_v2packh_X1_LDADD = $(LDADD)
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+insn_test_v2packl_X0_OBJECTS = insn_test_v2packl_X0.$(OBJEXT)
+insn_test_v2packl_X0_LDADD = $(LDADD)
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+insn_test_v2packl_X1_OBJECTS = insn_test_v2packl_X1.$(OBJEXT)
+insn_test_v2packl_X1_LDADD = $(LDADD)
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+insn_test_v2packuc_X0_OBJECTS = insn_test_v2packuc_X0.$(OBJEXT)
+insn_test_v2packuc_X0_LDADD = $(LDADD)
+insn_test_v2packuc_X1_SOURCES = insn_test_v2packuc_X1.c
+insn_test_v2packuc_X1_OBJECTS = insn_test_v2packuc_X1.$(OBJEXT)
+insn_test_v2packuc_X1_LDADD = $(LDADD)
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+insn_test_v2sadas_X0_OBJECTS = insn_test_v2sadas_X0.$(OBJEXT)
+insn_test_v2sadas_X0_LDADD = $(LDADD)
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+insn_test_v2sadau_X0_OBJECTS = insn_test_v2sadau_X0.$(OBJEXT)
+insn_test_v2sadau_X0_LDADD = $(LDADD)
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+insn_test_v2sads_X0_OBJECTS = insn_test_v2sads_X0.$(OBJEXT)
+insn_test_v2sads_X0_LDADD = $(LDADD)
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+insn_test_v2sadu_X0_OBJECTS = insn_test_v2sadu_X0.$(OBJEXT)
+insn_test_v2sadu_X0_LDADD = $(LDADD)
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+insn_test_v2shl_X0_OBJECTS = insn_test_v2shl_X0.$(OBJEXT)
+insn_test_v2shl_X0_LDADD = $(LDADD)
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+insn_test_v2shl_X1_OBJECTS = insn_test_v2shl_X1.$(OBJEXT)
+insn_test_v2shl_X1_LDADD = $(LDADD)
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+insn_test_v2shli_X0_OBJECTS = insn_test_v2shli_X0.$(OBJEXT)
+insn_test_v2shli_X0_LDADD = $(LDADD)
+insn_test_v2shli_X1_SOURCES = insn_test_v2shli_X1.c
+insn_test_v2shli_X1_OBJECTS = insn_test_v2shli_X1.$(OBJEXT)
+insn_test_v2shli_X1_LDADD = $(LDADD)
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+insn_test_v2shlsc_X0_OBJECTS = insn_test_v2shlsc_X0.$(OBJEXT)
+insn_test_v2shlsc_X0_LDADD = $(LDADD)
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+insn_test_v2shlsc_X1_OBJECTS = insn_test_v2shlsc_X1.$(OBJEXT)
+insn_test_v2shlsc_X1_LDADD = $(LDADD)
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+insn_test_v2shrs_X0_LDADD = $(LDADD)
+insn_test_v2shrs_X1_SOURCES = insn_test_v2shrs_X1.c
+insn_test_v2shrs_X1_OBJECTS = insn_test_v2shrs_X1.$(OBJEXT)
+insn_test_v2shrs_X1_LDADD = $(LDADD)
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+insn_test_v2shrsi_X0_OBJECTS = insn_test_v2shrsi_X0.$(OBJEXT)
+insn_test_v2shrsi_X0_LDADD = $(LDADD)
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+insn_test_v2shrsi_X1_OBJECTS = insn_test_v2shrsi_X1.$(OBJEXT)
+insn_test_v2shrsi_X1_LDADD = $(LDADD)
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+insn_test_v2shru_X0_OBJECTS = insn_test_v2shru_X0.$(OBJEXT)
+insn_test_v2shru_X0_LDADD = $(LDADD)
+insn_test_v2shru_X1_SOURCES = insn_test_v2shru_X1.c
+insn_test_v2shru_X1_OBJECTS = insn_test_v2shru_X1.$(OBJEXT)
+insn_test_v2shru_X1_LDADD = $(LDADD)
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+insn_test_v2shrui_X0_OBJECTS = insn_test_v2shrui_X0.$(OBJEXT)
+insn_test_v2shrui_X0_LDADD = $(LDADD)
+insn_test_v2shrui_X1_SOURCES = insn_test_v2shrui_X1.c
+insn_test_v2shrui_X1_OBJECTS = insn_test_v2shrui_X1.$(OBJEXT)
+insn_test_v2shrui_X1_LDADD = $(LDADD)
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+insn_test_v2sub_X0_OBJECTS = insn_test_v2sub_X0.$(OBJEXT)
+insn_test_v2sub_X0_LDADD = $(LDADD)
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+insn_test_v2sub_X1_OBJECTS = insn_test_v2sub_X1.$(OBJEXT)
+insn_test_v2sub_X1_LDADD = $(LDADD)
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+insn_test_v2subsc_X0_OBJECTS = insn_test_v2subsc_X0.$(OBJEXT)
+insn_test_v2subsc_X0_LDADD = $(LDADD)
+insn_test_v2subsc_X1_SOURCES = insn_test_v2subsc_X1.c
+insn_test_v2subsc_X1_OBJECTS = insn_test_v2subsc_X1.$(OBJEXT)
+insn_test_v2subsc_X1_LDADD = $(LDADD)
+insn_test_v4add_X0_SOURCES = insn_test_v4add_X0.c
+insn_test_v4add_X0_OBJECTS = insn_test_v4add_X0.$(OBJEXT)
+insn_test_v4add_X0_LDADD = $(LDADD)
+insn_test_v4add_X1_SOURCES = insn_test_v4add_X1.c
+insn_test_v4add_X1_OBJECTS = insn_test_v4add_X1.$(OBJEXT)
+insn_test_v4add_X1_LDADD = $(LDADD)
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+insn_test_v4addsc_X0_OBJECTS = insn_test_v4addsc_X0.$(OBJEXT)
+insn_test_v4addsc_X0_LDADD = $(LDADD)
+insn_test_v4addsc_X1_SOURCES = insn_test_v4addsc_X1.c
+insn_test_v4addsc_X1_OBJECTS = insn_test_v4addsc_X1.$(OBJEXT)
+insn_test_v4addsc_X1_LDADD = $(LDADD)
+insn_test_v4int_h_X0_SOURCES = insn_test_v4int_h_X0.c
+insn_test_v4int_h_X0_OBJECTS = insn_test_v4int_h_X0.$(OBJEXT)
+insn_test_v4int_h_X0_LDADD = $(LDADD)
+insn_test_v4int_h_X1_SOURCES = insn_test_v4int_h_X1.c
+insn_test_v4int_h_X1_OBJECTS = insn_test_v4int_h_X1.$(OBJEXT)
+insn_test_v4int_h_X1_LDADD = $(LDADD)
+insn_test_v4int_l_X0_SOURCES = insn_test_v4int_l_X0.c
+insn_test_v4int_l_X0_OBJECTS = insn_test_v4int_l_X0.$(OBJEXT)
+insn_test_v4int_l_X0_LDADD = $(LDADD)
+insn_test_v4int_l_X1_SOURCES = insn_test_v4int_l_X1.c
+insn_test_v4int_l_X1_OBJECTS = insn_test_v4int_l_X1.$(OBJEXT)
+insn_test_v4int_l_X1_LDADD = $(LDADD)
+insn_test_v4packsc_X0_SOURCES = insn_test_v4packsc_X0.c
+insn_test_v4packsc_X0_OBJECTS = insn_test_v4packsc_X0.$(OBJEXT)
+insn_test_v4packsc_X0_LDADD = $(LDADD)
+insn_test_v4packsc_X1_SOURCES = insn_test_v4packsc_X1.c
+insn_test_v4packsc_X1_OBJECTS = insn_test_v4packsc_X1.$(OBJEXT)
+insn_test_v4packsc_X1_LDADD = $(LDADD)
+insn_test_v4shl_X0_SOURCES = insn_test_v4shl_X0.c
+insn_test_v4shl_X0_OBJECTS = insn_test_v4shl_X0.$(OBJEXT)
+insn_test_v4shl_X0_LDADD = $(LDADD)
+insn_test_v4shl_X1_SOURCES = insn_test_v4shl_X1.c
+insn_test_v4shl_X1_OBJECTS = insn_test_v4shl_X1.$(OBJEXT)
+insn_test_v4shl_X1_LDADD = $(LDADD)
+insn_test_v4shlsc_X0_SOURCES = insn_test_v4shlsc_X0.c
+insn_test_v4shlsc_X0_OBJECTS = insn_test_v4shlsc_X0.$(OBJEXT)
+insn_test_v4shlsc_X0_LDADD = $(LDADD)
+insn_test_v4shlsc_X1_SOURCES = insn_test_v4shlsc_X1.c
+insn_test_v4shlsc_X1_OBJECTS = insn_test_v4shlsc_X1.$(OBJEXT)
+insn_test_v4shlsc_X1_LDADD = $(LDADD)
+insn_test_v4shrs_X0_SOURCES = insn_test_v4shrs_X0.c
+insn_test_v4shrs_X0_OBJECTS = insn_test_v4shrs_X0.$(OBJEXT)
+insn_test_v4shrs_X0_LDADD = $(LDADD)
+insn_test_v4shrs_X1_SOURCES = insn_test_v4shrs_X1.c
+insn_test_v4shrs_X1_OBJECTS = insn_test_v4shrs_X1.$(OBJEXT)
+insn_test_v4shrs_X1_LDADD = $(LDADD)
+insn_test_v4shru_X0_SOURCES = insn_test_v4shru_X0.c
+insn_test_v4shru_X0_OBJECTS = insn_test_v4shru_X0.$(OBJEXT)
+insn_test_v4shru_X0_LDADD = $(LDADD)
+insn_test_v4shru_X1_SOURCES = insn_test_v4shru_X1.c
+insn_test_v4shru_X1_OBJECTS = insn_test_v4shru_X1.$(OBJEXT)
+insn_test_v4shru_X1_LDADD = $(LDADD)
+insn_test_v4sub_X0_SOURCES = insn_test_v4sub_X0.c
+insn_test_v4sub_X0_OBJECTS = insn_test_v4sub_X0.$(OBJEXT)
+insn_test_v4sub_X0_LDADD = $(LDADD)
+insn_test_v4sub_X1_SOURCES = insn_test_v4sub_X1.c
+insn_test_v4sub_X1_OBJECTS = insn_test_v4sub_X1.$(OBJEXT)
+insn_test_v4sub_X1_LDADD = $(LDADD)
+insn_test_v4subsc_X0_SOURCES = insn_test_v4subsc_X0.c
+insn_test_v4subsc_X0_OBJECTS = insn_test_v4subsc_X0.$(OBJEXT)
+insn_test_v4subsc_X0_LDADD = $(LDADD)
+insn_test_v4subsc_X1_SOURCES = insn_test_v4subsc_X1.c
+insn_test_v4subsc_X1_OBJECTS = insn_test_v4subsc_X1.$(OBJEXT)
+insn_test_v4subsc_X1_LDADD = $(LDADD)
+insn_test_wh64_X1_SOURCES = insn_test_wh64_X1.c
+insn_test_wh64_X1_OBJECTS = insn_test_wh64_X1.$(OBJEXT)
+insn_test_wh64_X1_LDADD = $(LDADD)
+insn_test_xor_X0_SOURCES = insn_test_xor_X0.c
+insn_test_xor_X0_OBJECTS = insn_test_xor_X0.$(OBJEXT)
+insn_test_xor_X0_LDADD = $(LDADD)
+insn_test_xor_X1_SOURCES = insn_test_xor_X1.c
+insn_test_xor_X1_OBJECTS = insn_test_xor_X1.$(OBJEXT)
+insn_test_xor_X1_LDADD = $(LDADD)
+insn_test_xor_Y0_SOURCES = insn_test_xor_Y0.c
+insn_test_xor_Y0_OBJECTS = insn_test_xor_Y0.$(OBJEXT)
+insn_test_xor_Y0_LDADD = $(LDADD)
+insn_test_xor_Y1_SOURCES = insn_test_xor_Y1.c
+insn_test_xor_Y1_OBJECTS = insn_test_xor_Y1.$(OBJEXT)
+insn_test_xor_Y1_LDADD = $(LDADD)
+insn_test_xori_X0_SOURCES = insn_test_xori_X0.c
+insn_test_xori_X0_OBJECTS = insn_test_xori_X0.$(OBJEXT)
+insn_test_xori_X0_LDADD = $(LDADD)
+insn_test_xori_X1_SOURCES = insn_test_xori_X1.c
+insn_test_xori_X1_OBJECTS = insn_test_xori_X1.$(OBJEXT)
+insn_test_xori_X1_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+AM_V_P = $(am__v_P_@AM_V@)
+am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
+am__v_P_0 = false
+am__v_P_1 = :
+AM_V_GEN = $(am__v_GEN_@AM_V@)
+am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@)
+am__v_GEN_0 = @echo " GEN " $@;
+am__v_GEN_1 =
+AM_V_at = $(am__v_at_@AM_V@)
+am__v_at_ = $(am__v_at_@AM_DEFAULT_V@)
+am__v_at_0 = @
+am__v_at_1 =
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+AM_V_lt = $(am__v_lt_@AM_V@)
+am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)
+am__v_lt_0 = --silent
+am__v_lt_1 =
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+AM_V_CC = $(am__v_CC_@AM_V@)
+am__v_CC_ = $(am__v_CC_@AM_DEFAULT_V@)
+am__v_CC_0 = @echo " CC " $@;
+am__v_CC_1 =
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+AM_V_CCLD = $(am__v_CCLD_@AM_V@)
+am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
+am__v_CCLD_0 = @echo " CCLD " $@;
+am__v_CCLD_1 =
+SOURCES = allexec.c gen_insn_test.c insn_test_add_X0.c \
+ insn_test_add_X1.c insn_test_add_Y0.c insn_test_add_Y1.c \
+ insn_test_addi_X0.c insn_test_addi_X1.c insn_test_addi_Y0.c \
+ insn_test_addi_Y1.c insn_test_addli_X0.c insn_test_addli_X1.c \
+ insn_test_addx_X0.c insn_test_addx_X1.c insn_test_addx_Y0.c \
+ insn_test_addx_Y1.c insn_test_addxi_X0.c insn_test_addxi_X1.c \
+ insn_test_addxi_Y0.c insn_test_addxi_Y1.c \
+ insn_test_addxli_X0.c insn_test_addxli_X1.c \
+ insn_test_addxsc_X0.c insn_test_addxsc_X1.c insn_test_and_X0.c \
+ insn_test_and_X1.c insn_test_and_Y0.c insn_test_and_Y1.c \
+ insn_test_andi_X0.c insn_test_andi_X1.c insn_test_andi_Y0.c \
+ insn_test_andi_Y1.c insn_test_beqz_X1.c insn_test_beqzt_X1.c \
+ insn_test_bfexts_X0.c insn_test_bfextu_X0.c \
+ insn_test_bfins_X0.c insn_test_bgez_X1.c insn_test_bgezt_X1.c \
+ insn_test_bgtz_X1.c insn_test_bgtzt_X1.c insn_test_blbc_X1.c \
+ insn_test_blbct_X1.c insn_test_blbs_X1.c insn_test_blbst_X1.c \
+ insn_test_blez_X1.c insn_test_blezt_X1.c insn_test_bltz_X1.c \
+ insn_test_bltzt_X1.c insn_test_bnez_X1.c insn_test_bnezt_X1.c \
+ insn_test_clz_X0.c insn_test_clz_Y0.c insn_test_cmoveqz_X0.c \
+ insn_test_cmoveqz_Y0.c insn_test_cmovnez_X0.c \
+ insn_test_cmovnez_Y0.c insn_test_cmpeq_X0.c \
+ insn_test_cmpeq_X1.c insn_test_cmpeq_Y0.c insn_test_cmpeq_Y1.c \
+ insn_test_cmpeqi_X0.c insn_test_cmpeqi_X1.c \
+ insn_test_cmpeqi_Y0.c insn_test_cmpeqi_Y1.c \
+ insn_test_cmples_X0.c insn_test_cmples_X1.c \
+ insn_test_cmples_Y0.c insn_test_cmples_Y1.c \
+ insn_test_cmpleu_X0.c insn_test_cmpleu_X1.c \
+ insn_test_cmpleu_Y0.c insn_test_cmpleu_Y1.c \
+ insn_test_cmplts_X0.c insn_test_cmplts_X1.c \
+ insn_test_cmplts_Y0.c insn_test_cmplts_Y1.c \
+ insn_test_cmpltsi_X0.c insn_test_cmpltsi_X1.c \
+ insn_test_cmpltsi_Y0.c insn_test_cmpltsi_Y1.c \
+ insn_test_cmpltu_X0.c insn_test_cmpltu_X1.c \
+ insn_test_cmpltu_Y0.c insn_test_cmpltu_Y1.c \
+ insn_test_cmpltui_X0.c insn_test_cmpltui_X1.c \
+ insn_test_cmpne_X0.c insn_test_cmpne_X1.c insn_test_cmpne_Y0.c \
+ insn_test_cmpne_Y1.c insn_test_cmul_X0.c insn_test_cmula_X0.c \
+ insn_test_cmulaf_X0.c insn_test_cmulf_X0.c \
+ insn_test_cmulfr_X0.c insn_test_cmulh_X0.c \
+ insn_test_cmulhr_X0.c insn_test_crc32_32_X0.c \
+ insn_test_crc32_8_X0.c insn_test_ctz_X0.c insn_test_ctz_Y0.c \
+ insn_test_dblalign2_X0.c insn_test_dblalign2_X1.c \
+ insn_test_dblalign4_X0.c insn_test_dblalign4_X1.c \
+ insn_test_dblalign6_X0.c insn_test_dblalign6_X1.c \
+ insn_test_dblalign_X0.c insn_test_dtlbpr_X1.c \
+ insn_test_fdouble_add_flags_X0.c insn_test_fdouble_addsub_X0.c \
+ insn_test_fdouble_mul_flags_X0.c insn_test_fdouble_pack1_X0.c \
+ insn_test_fdouble_pack2_X0.c insn_test_fdouble_sub_flags_X0.c \
+ insn_test_fdouble_unpack_max_X0.c \
+ insn_test_fdouble_unpack_min_X0.c insn_test_flushwb_X1.c \
+ insn_test_fnop_X0.c insn_test_fnop_X1.c insn_test_fnop_Y0.c \
+ insn_test_fnop_Y1.c insn_test_fsingle_add1_X0.c \
+ insn_test_fsingle_addsub2_X0.c insn_test_fsingle_mul1_X0.c \
+ insn_test_fsingle_mul2_X0.c insn_test_fsingle_pack1_X0.c \
+ insn_test_fsingle_pack1_Y0.c insn_test_fsingle_pack2_X0.c \
+ insn_test_fsingle_sub1_X0.c insn_test_icoh_X1.c \
+ insn_test_j_X1.c insn_test_jal_X1.c insn_test_jalr_X1.c \
+ insn_test_jalr_Y1.c insn_test_jalrp_X1.c insn_test_jalrp_Y1.c \
+ insn_test_jr_X1.c insn_test_jr_Y1.c insn_test_jrp_X1.c \
+ insn_test_jrp_Y1.c insn_test_ld1s_X1.c insn_test_ld1s_Y2.c \
+ insn_test_ld1s_add_X1.c insn_test_ld1u_X1.c \
+ insn_test_ld1u_Y2.c insn_test_ld1u_add_X1.c \
+ insn_test_ld2s_X1.c insn_test_ld2s_Y2.c insn_test_ld2u_X1.c \
+ insn_test_ld2u_Y2.c insn_test_ld4s_X1.c \
+ insn_test_ld4s_add_X1.c insn_test_ld4u_X1.c \
+ insn_test_ld4u_Y2.c insn_test_ld4u_add_X1.c insn_test_ld_X1.c \
+ insn_test_ld_Y2.c insn_test_ld_add_X1.c insn_test_ldna_X1.c \
+ insn_test_ldna_add_X1.c insn_test_ldnt1s_X1.c \
+ insn_test_ldnt1s_add_X1.c insn_test_ldnt1u_X1.c \
+ insn_test_ldnt1u_add_X1.c insn_test_ldnt2s_X1.c \
+ insn_test_ldnt2s_add_X1.c insn_test_ldnt2u_add_X1.c \
+ insn_test_ldnt4s_X1.c insn_test_ldnt4s_add_X1.c \
+ insn_test_ldnt4u_X1.c insn_test_ldnt4u_add_X1.c \
+ insn_test_ldnt_X1.c insn_test_ldnt_add_X1.c insn_test_lnk_X1.c \
+ insn_test_lnk_Y1.c insn_test_mf_X1.c insn_test_mm_X0.c \
+ insn_test_mnz_X0.c insn_test_mnz_X1.c insn_test_mnz_Y0.c \
+ insn_test_mnz_Y1.c insn_test_move_X0.c insn_test_move_X1.c \
+ insn_test_move_Y0.c insn_test_move_Y1.c insn_test_movei_X0.c \
+ insn_test_movei_X1.c insn_test_movei_Y0.c insn_test_movei_Y1.c \
+ insn_test_moveli_X0.c insn_test_moveli_X1.c \
+ insn_test_mul_hs_hs_X0.c insn_test_mul_hs_hs_Y0.c \
+ insn_test_mul_hs_hu_X0.c insn_test_mul_hs_ls_X0.c \
+ insn_test_mul_hs_lu_X0.c insn_test_mul_hu_hu_X0.c \
+ insn_test_mul_hu_hu_Y0.c insn_test_mul_hu_lu_X0.c \
+ insn_test_mul_ls_ls_X0.c insn_test_mul_ls_ls_Y0.c \
+ insn_test_mul_ls_lu_X0.c insn_test_mul_lu_lu_X0.c \
+ insn_test_mul_lu_lu_Y0.c insn_test_mula_hs_hs_X0.c \
+ insn_test_mula_hs_hs_Y0.c insn_test_mula_hs_hu_X0.c \
+ insn_test_mula_hs_ls_X0.c insn_test_mula_hs_lu_X0.c \
+ insn_test_mula_hu_hu_X0.c insn_test_mula_hu_hu_Y0.c \
+ insn_test_mula_hu_ls_X0.c insn_test_mula_hu_lu_X0.c \
+ insn_test_mula_ls_ls_X0.c insn_test_mula_ls_ls_Y0.c \
+ insn_test_mula_ls_lu_X0.c insn_test_mula_lu_lu_X0.c \
+ insn_test_mula_lu_lu_Y0.c insn_test_mulax_X0.c \
+ insn_test_mulax_Y0.c insn_test_mulx_X0.c insn_test_mulx_Y0.c \
+ insn_test_mz_X0.c insn_test_mz_X1.c insn_test_mz_Y0.c \
+ insn_test_mz_Y1.c insn_test_nop_X0.c insn_test_nop_X1.c \
+ insn_test_nop_Y0.c insn_test_nop_Y1.c insn_test_nor_X0.c \
+ insn_test_nor_X1.c insn_test_nor_Y0.c insn_test_nor_Y1.c \
+ insn_test_or_X0.c insn_test_or_X1.c insn_test_or_Y0.c \
+ insn_test_or_Y1.c insn_test_ori_X0.c insn_test_ori_X1.c \
+ insn_test_pcnt_X0.c insn_test_pcnt_Y0.c \
+ insn_test_prefetch_X1.c insn_test_prefetch_Y2.c \
+ insn_test_prefetch_l1_X1.c insn_test_prefetch_l1_Y2.c \
+ insn_test_prefetch_l2_X1.c insn_test_prefetch_l2_Y2.c \
+ insn_test_prefetch_l3_X1.c insn_test_prefetch_l3_Y2.c \
+ insn_test_revbits_X0.c insn_test_revbits_Y0.c \
+ insn_test_revbytes_X0.c insn_test_revbytes_Y0.c \
+ insn_test_rotl_X0.c insn_test_rotl_X1.c insn_test_rotl_Y0.c \
+ insn_test_rotl_Y1.c insn_test_rotli_X0.c insn_test_rotli_X1.c \
+ insn_test_rotli_Y0.c insn_test_rotli_Y1.c \
+ insn_test_shl16insli_X0.c insn_test_shl16insli_X1.c \
+ insn_test_shl1add_X0.c insn_test_shl1add_X1.c \
+ insn_test_shl1add_Y0.c insn_test_shl1add_Y1.c \
+ insn_test_shl1addx_X0.c insn_test_shl1addx_X1.c \
+ insn_test_shl1addx_Y0.c insn_test_shl1addx_Y1.c \
+ insn_test_shl2add_X0.c insn_test_shl2add_X1.c \
+ insn_test_shl2add_Y0.c insn_test_shl2add_Y1.c \
+ insn_test_shl2addx_X0.c insn_test_shl2addx_X1.c \
+ insn_test_shl2addx_Y0.c insn_test_shl2addx_Y1.c \
+ insn_test_shl3add_X0.c insn_test_shl3add_X1.c \
+ insn_test_shl3add_Y0.c insn_test_shl3add_Y1.c \
+ insn_test_shl3addx_X0.c insn_test_shl3addx_X1.c \
+ insn_test_shl3addx_Y0.c insn_test_shl3addx_Y1.c \
+ insn_test_shl_X0.c insn_test_shl_X1.c insn_test_shl_Y0.c \
+ insn_test_shl_Y1.c insn_test_shli_X0.c insn_test_shli_X1.c \
+ insn_test_shli_Y0.c insn_test_shli_Y1.c insn_test_shlx_X0.c \
+ insn_test_shlx_X1.c insn_test_shlxi_X0.c insn_test_shlxi_X1.c \
+ insn_test_shrs_X0.c insn_test_shrs_X1.c insn_test_shrs_Y0.c \
+ insn_test_shrs_Y1.c insn_test_shrsi_X0.c insn_test_shrsi_X1.c \
+ insn_test_shrsi_Y0.c insn_test_shrsi_Y1.c insn_test_shru_X0.c \
+ insn_test_shru_X1.c insn_test_shru_Y0.c insn_test_shru_Y1.c \
+ insn_test_shrui_X0.c insn_test_shrui_X1.c insn_test_shrui_Y0.c \
+ insn_test_shrui_Y1.c insn_test_shrux_X0.c insn_test_shrux_X1.c \
+ insn_test_shufflebytes_X0.c insn_test_st1_X1.c \
+ insn_test_st1_Y2.c insn_test_st1_add_X1.c insn_test_st2_X1.c \
+ insn_test_st2_Y2.c insn_test_st2_add_X1.c insn_test_st4_X1.c \
+ insn_test_st4_Y2.c insn_test_st4_add_X1.c insn_test_st_X1.c \
+ insn_test_st_Y2.c insn_test_st_add_X1.c insn_test_stnt1_X1.c \
+ insn_test_stnt2_X1.c insn_test_stnt2_add_X1.c \
+ insn_test_stnt4_X1.c insn_test_stnt4_add_X1.c \
+ insn_test_stnt_X1.c insn_test_stnt_add_X1.c insn_test_sub_X0.c \
+ insn_test_sub_X1.c insn_test_sub_Y0.c insn_test_sub_Y1.c \
+ insn_test_subx_X0.c insn_test_subx_X1.c insn_test_subx_Y0.c \
+ insn_test_subx_Y1.c insn_test_tblidxb0_X0.c \
+ insn_test_tblidxb0_Y0.c insn_test_tblidxb1_X0.c \
+ insn_test_tblidxb1_Y0.c insn_test_tblidxb2_X0.c \
+ insn_test_tblidxb2_Y0.c insn_test_tblidxb3_X0.c \
+ insn_test_tblidxb3_Y0.c insn_test_v1add_X0.c \
+ insn_test_v1add_X1.c insn_test_v1adduc_X0.c \
+ insn_test_v1adduc_X1.c insn_test_v1adiffu_X0.c \
+ insn_test_v1avgu_X0.c insn_test_v1cmpeq_X0.c \
+ insn_test_v1cmpeq_X1.c insn_test_v1cmpeqi_X0.c \
+ insn_test_v1cmpeqi_X1.c insn_test_v1cmples_X0.c \
+ insn_test_v1cmples_X1.c insn_test_v1cmpleu_X0.c \
+ insn_test_v1cmpleu_X1.c insn_test_v1cmplts_X0.c \
+ insn_test_v1cmplts_X1.c insn_test_v1cmpltu_X0.c \
+ insn_test_v1cmpltu_X1.c insn_test_v1cmpne_X0.c \
+ insn_test_v1cmpne_X1.c insn_test_v1ddotpu_X0.c \
+ insn_test_v1ddotpua_X0.c insn_test_v1ddotpus_X0.c \
+ insn_test_v1ddotpusa_X0.c insn_test_v1dotp_X0.c \
+ insn_test_v1dotpa_X0.c insn_test_v1dotpu_X0.c \
+ insn_test_v1dotpua_X0.c insn_test_v1dotpus_X0.c \
+ insn_test_v1dotpusa_X0.c insn_test_v1int_h_X0.c \
+ insn_test_v1int_h_X1.c insn_test_v1int_l_X0.c \
+ insn_test_v1int_l_X1.c insn_test_v1maxu_X0.c \
+ insn_test_v1maxu_X1.c insn_test_v1minu_X0.c \
+ insn_test_v1minu_X1.c insn_test_v1mnz_X0.c \
+ insn_test_v1mnz_X1.c insn_test_v1multu_X0.c \
+ insn_test_v1mulu_X0.c insn_test_v1mulus_X0.c \
+ insn_test_v1mz_X0.c insn_test_v1mz_X1.c insn_test_v1sadau_X0.c \
+ insn_test_v1sadu_X0.c insn_test_v1shl_X0.c \
+ insn_test_v1shl_X1.c insn_test_v1shli_X0.c \
+ insn_test_v1shli_X1.c insn_test_v1shrs_X0.c \
+ insn_test_v1shrs_X1.c insn_test_v1shrsi_X0.c \
+ insn_test_v1shrsi_X1.c insn_test_v1shru_X0.c \
+ insn_test_v1shru_X1.c insn_test_v1shrui_X0.c \
+ insn_test_v1shrui_X1.c insn_test_v1sub_X0.c \
+ insn_test_v1sub_X1.c insn_test_v1subuc_X0.c \
+ insn_test_v1subuc_X1.c insn_test_v2add_X0.c \
+ insn_test_v2add_X1.c insn_test_v2addsc_X0.c \
+ insn_test_v2addsc_X1.c insn_test_v2adiffs_X0.c \
+ insn_test_v2avgs_X0.c insn_test_v2cmpeq_X0.c \
+ insn_test_v2cmpeq_X1.c insn_test_v2cmpeqi_X0.c \
+ insn_test_v2cmpeqi_X1.c insn_test_v2cmples_X0.c \
+ insn_test_v2cmples_X1.c insn_test_v2cmpleu_X0.c \
+ insn_test_v2cmpleu_X1.c insn_test_v2cmplts_X0.c \
+ insn_test_v2cmplts_X1.c insn_test_v2cmpltsi_X0.c \
+ insn_test_v2cmpltsi_X1.c insn_test_v2cmpltu_X0.c \
+ insn_test_v2cmpltu_X1.c insn_test_v2cmpltui_X0.c \
+ insn_test_v2cmpltui_X1.c insn_test_v2cmpne_X0.c \
+ insn_test_v2cmpne_X1.c insn_test_v2dotp_X0.c \
+ insn_test_v2dotpa_X0.c insn_test_v2int_h_X0.c \
+ insn_test_v2int_h_X1.c insn_test_v2int_l_X0.c \
+ insn_test_v2int_l_X1.c insn_test_v2maxs_X0.c \
+ insn_test_v2maxs_X1.c insn_test_v2mins_X0.c \
+ insn_test_v2mins_X1.c insn_test_v2mnz_X0.c \
+ insn_test_v2mnz_X1.c insn_test_v2mulfsc_X0.c \
+ insn_test_v2muls_X0.c insn_test_v2mults_X0.c \
+ insn_test_v2mz_X0.c insn_test_v2mz_X1.c insn_test_v2packh_X0.c \
+ insn_test_v2packh_X1.c insn_test_v2packl_X0.c \
+ insn_test_v2packl_X1.c insn_test_v2packuc_X0.c \
+ insn_test_v2packuc_X1.c insn_test_v2sadas_X0.c \
+ insn_test_v2sadau_X0.c insn_test_v2sads_X0.c \
+ insn_test_v2sadu_X0.c insn_test_v2shl_X0.c \
+ insn_test_v2shl_X1.c insn_test_v2shli_X0.c \
+ insn_test_v2shli_X1.c insn_test_v2shlsc_X0.c \
+ insn_test_v2shlsc_X1.c insn_test_v2shrs_X0.c \
+ insn_test_v2shrs_X1.c insn_test_v2shrsi_X0.c \
+ insn_test_v2shrsi_X1.c insn_test_v2shru_X0.c \
+ insn_test_v2shru_X1.c insn_test_v2shrui_X0.c \
+ insn_test_v2shrui_X1.c insn_test_v2sub_X0.c \
+ insn_test_v2sub_X1.c insn_test_v2subsc_X0.c \
+ insn_test_v2subsc_X1.c insn_test_v4add_X0.c \
+ insn_test_v4add_X1.c insn_test_v4addsc_X0.c \
+ insn_test_v4addsc_X1.c insn_test_v4int_h_X0.c \
+ insn_test_v4int_h_X1.c insn_test_v4int_l_X0.c \
+ insn_test_v4int_l_X1.c insn_test_v4packsc_X0.c \
+ insn_test_v4packsc_X1.c insn_test_v4shl_X0.c \
+ insn_test_v4shl_X1.c insn_test_v4shlsc_X0.c \
+ insn_test_v4shlsc_X1.c insn_test_v4shrs_X0.c \
+ insn_test_v4shrs_X1.c insn_test_v4shru_X0.c \
+ insn_test_v4shru_X1.c insn_test_v4sub_X0.c \
+ insn_test_v4sub_X1.c insn_test_v4subsc_X0.c \
+ insn_test_v4subsc_X1.c insn_test_wh64_X1.c insn_test_xor_X0.c \
+ insn_test_xor_X1.c insn_test_xor_Y0.c insn_test_xor_Y1.c \
+ insn_test_xori_X0.c insn_test_xori_X1.c
+DIST_SOURCES = allexec.c gen_insn_test.c insn_test_add_X0.c \
+ insn_test_add_X1.c insn_test_add_Y0.c insn_test_add_Y1.c \
+ insn_test_addi_X0.c insn_test_addi_X1.c insn_test_addi_Y0.c \
+ insn_test_addi_Y1.c insn_test_addli_X0.c insn_test_addli_X1.c \
+ insn_test_addx_X0.c insn_test_addx_X1.c insn_test_addx_Y0.c \
+ insn_test_addx_Y1.c insn_test_addxi_X0.c insn_test_addxi_X1.c \
+ insn_test_addxi_Y0.c insn_test_addxi_Y1.c \
+ insn_test_addxli_X0.c insn_test_addxli_X1.c \
+ insn_test_addxsc_X0.c insn_test_addxsc_X1.c insn_test_and_X0.c \
+ insn_test_and_X1.c insn_test_and_Y0.c insn_test_and_Y1.c \
+ insn_test_andi_X0.c insn_test_andi_X1.c insn_test_andi_Y0.c \
+ insn_test_andi_Y1.c insn_test_beqz_X1.c insn_test_beqzt_X1.c \
+ insn_test_bfexts_X0.c insn_test_bfextu_X0.c \
+ insn_test_bfins_X0.c insn_test_bgez_X1.c insn_test_bgezt_X1.c \
+ insn_test_bgtz_X1.c insn_test_bgtzt_X1.c insn_test_blbc_X1.c \
+ insn_test_blbct_X1.c insn_test_blbs_X1.c insn_test_blbst_X1.c \
+ insn_test_blez_X1.c insn_test_blezt_X1.c insn_test_bltz_X1.c \
+ insn_test_bltzt_X1.c insn_test_bnez_X1.c insn_test_bnezt_X1.c \
+ insn_test_clz_X0.c insn_test_clz_Y0.c insn_test_cmoveqz_X0.c \
+ insn_test_cmoveqz_Y0.c insn_test_cmovnez_X0.c \
+ insn_test_cmovnez_Y0.c insn_test_cmpeq_X0.c \
+ insn_test_cmpeq_X1.c insn_test_cmpeq_Y0.c insn_test_cmpeq_Y1.c \
+ insn_test_cmpeqi_X0.c insn_test_cmpeqi_X1.c \
+ insn_test_cmpeqi_Y0.c insn_test_cmpeqi_Y1.c \
+ insn_test_cmples_X0.c insn_test_cmples_X1.c \
+ insn_test_cmples_Y0.c insn_test_cmples_Y1.c \
+ insn_test_cmpleu_X0.c insn_test_cmpleu_X1.c \
+ insn_test_cmpleu_Y0.c insn_test_cmpleu_Y1.c \
+ insn_test_cmplts_X0.c insn_test_cmplts_X1.c \
+ insn_test_cmplts_Y0.c insn_test_cmplts_Y1.c \
+ insn_test_cmpltsi_X0.c insn_test_cmpltsi_X1.c \
+ insn_test_cmpltsi_Y0.c insn_test_cmpltsi_Y1.c \
+ insn_test_cmpltu_X0.c insn_test_cmpltu_X1.c \
+ insn_test_cmpltu_Y0.c insn_test_cmpltu_Y1.c \
+ insn_test_cmpltui_X0.c insn_test_cmpltui_X1.c \
+ insn_test_cmpne_X0.c insn_test_cmpne_X1.c insn_test_cmpne_Y0.c \
+ insn_test_cmpne_Y1.c insn_test_cmul_X0.c insn_test_cmula_X0.c \
+ insn_test_cmulaf_X0.c insn_test_cmulf_X0.c \
+ insn_test_cmulfr_X0.c insn_test_cmulh_X0.c \
+ insn_test_cmulhr_X0.c insn_test_crc32_32_X0.c \
+ insn_test_crc32_8_X0.c insn_test_ctz_X0.c insn_test_ctz_Y0.c \
+ insn_test_dblalign2_X0.c insn_test_dblalign2_X1.c \
+ insn_test_dblalign4_X0.c insn_test_dblalign4_X1.c \
+ insn_test_dblalign6_X0.c insn_test_dblalign6_X1.c \
+ insn_test_dblalign_X0.c insn_test_dtlbpr_X1.c \
+ insn_test_fdouble_add_flags_X0.c insn_test_fdouble_addsub_X0.c \
+ insn_test_fdouble_mul_flags_X0.c insn_test_fdouble_pack1_X0.c \
+ insn_test_fdouble_pack2_X0.c insn_test_fdouble_sub_flags_X0.c \
+ insn_test_fdouble_unpack_max_X0.c \
+ insn_test_fdouble_unpack_min_X0.c insn_test_flushwb_X1.c \
+ insn_test_fnop_X0.c insn_test_fnop_X1.c insn_test_fnop_Y0.c \
+ insn_test_fnop_Y1.c insn_test_fsingle_add1_X0.c \
+ insn_test_fsingle_addsub2_X0.c insn_test_fsingle_mul1_X0.c \
+ insn_test_fsingle_mul2_X0.c insn_test_fsingle_pack1_X0.c \
+ insn_test_fsingle_pack1_Y0.c insn_test_fsingle_pack2_X0.c \
+ insn_test_fsingle_sub1_X0.c insn_test_icoh_X1.c \
+ insn_test_j_X1.c insn_test_jal_X1.c insn_test_jalr_X1.c \
+ insn_test_jalr_Y1.c insn_test_jalrp_X1.c insn_test_jalrp_Y1.c \
+ insn_test_jr_X1.c insn_test_jr_Y1.c insn_test_jrp_X1.c \
+ insn_test_jrp_Y1.c insn_test_ld1s_X1.c insn_test_ld1s_Y2.c \
+ insn_test_ld1s_add_X1.c insn_test_ld1u_X1.c \
+ insn_test_ld1u_Y2.c insn_test_ld1u_add_X1.c \
+ insn_test_ld2s_X1.c insn_test_ld2s_Y2.c insn_test_ld2u_X1.c \
+ insn_test_ld2u_Y2.c insn_test_ld4s_X1.c \
+ insn_test_ld4s_add_X1.c insn_test_ld4u_X1.c \
+ insn_test_ld4u_Y2.c insn_test_ld4u_add_X1.c insn_test_ld_X1.c \
+ insn_test_ld_Y2.c insn_test_ld_add_X1.c insn_test_ldna_X1.c \
+ insn_test_ldna_add_X1.c insn_test_ldnt1s_X1.c \
+ insn_test_ldnt1s_add_X1.c insn_test_ldnt1u_X1.c \
+ insn_test_ldnt1u_add_X1.c insn_test_ldnt2s_X1.c \
+ insn_test_ldnt2s_add_X1.c insn_test_ldnt2u_add_X1.c \
+ insn_test_ldnt4s_X1.c insn_test_ldnt4s_add_X1.c \
+ insn_test_ldnt4u_X1.c insn_test_ldnt4u_add_X1.c \
+ insn_test_ldnt_X1.c insn_test_ldnt_add_X1.c insn_test_lnk_X1.c \
+ insn_test_lnk_Y1.c insn_test_mf_X1.c insn_test_mm_X0.c \
+ insn_test_mnz_X0.c insn_test_mnz_X1.c insn_test_mnz_Y0.c \
+ insn_test_mnz_Y1.c insn_test_move_X0.c insn_test_move_X1.c \
+ insn_test_move_Y0.c insn_test_move_Y1.c insn_test_movei_X0.c \
+ insn_test_movei_X1.c insn_test_movei_Y0.c insn_test_movei_Y1.c \
+ insn_test_moveli_X0.c insn_test_moveli_X1.c \
+ insn_test_mul_hs_hs_X0.c insn_test_mul_hs_hs_Y0.c \
+ insn_test_mul_hs_hu_X0.c insn_test_mul_hs_ls_X0.c \
+ insn_test_mul_hs_lu_X0.c insn_test_mul_hu_hu_X0.c \
+ insn_test_mul_hu_hu_Y0.c insn_test_mul_hu_lu_X0.c \
+ insn_test_mul_ls_ls_X0.c insn_test_mul_ls_ls_Y0.c \
+ insn_test_mul_ls_lu_X0.c insn_test_mul_lu_lu_X0.c \
+ insn_test_mul_lu_lu_Y0.c insn_test_mula_hs_hs_X0.c \
+ insn_test_mula_hs_hs_Y0.c insn_test_mula_hs_hu_X0.c \
+ insn_test_mula_hs_ls_X0.c insn_test_mula_hs_lu_X0.c \
+ insn_test_mula_hu_hu_X0.c insn_test_mula_hu_hu_Y0.c \
+ insn_test_mula_hu_ls_X0.c insn_test_mula_hu_lu_X0.c \
+ insn_test_mula_ls_ls_X0.c insn_test_mula_ls_ls_Y0.c \
+ insn_test_mula_ls_lu_X0.c insn_test_mula_lu_lu_X0.c \
+ insn_test_mula_lu_lu_Y0.c insn_test_mulax_X0.c \
+ insn_test_mulax_Y0.c insn_test_mulx_X0.c insn_test_mulx_Y0.c \
+ insn_test_mz_X0.c insn_test_mz_X1.c insn_test_mz_Y0.c \
+ insn_test_mz_Y1.c insn_test_nop_X0.c insn_test_nop_X1.c \
+ insn_test_nop_Y0.c insn_test_nop_Y1.c insn_test_nor_X0.c \
+ insn_test_nor_X1.c insn_test_nor_Y0.c insn_test_nor_Y1.c \
+ insn_test_or_X0.c insn_test_or_X1.c insn_test_or_Y0.c \
+ insn_test_or_Y1.c insn_test_ori_X0.c insn_test_ori_X1.c \
+ insn_test_pcnt_X0.c insn_test_pcnt_Y0.c \
+ insn_test_prefetch_X1.c insn_test_prefetch_Y2.c \
+ insn_test_prefetch_l1_X1.c insn_test_prefetch_l1_Y2.c \
+ insn_test_prefetch_l2_X1.c insn_test_prefetch_l2_Y2.c \
+ insn_test_prefetch_l3_X1.c insn_test_prefetch_l3_Y2.c \
+ insn_test_revbits_X0.c insn_test_revbits_Y0.c \
+ insn_test_revbytes_X0.c insn_test_revbytes_Y0.c \
+ insn_test_rotl_X0.c insn_test_rotl_X1.c insn_test_rotl_Y0.c \
+ insn_test_rotl_Y1.c insn_test_rotli_X0.c insn_test_rotli_X1.c \
+ insn_test_rotli_Y0.c insn_test_rotli_Y1.c \
+ insn_test_shl16insli_X0.c insn_test_shl16insli_X1.c \
+ insn_test_shl1add_X0.c insn_test_shl1add_X1.c \
+ insn_test_shl1add_Y0.c insn_test_shl1add_Y1.c \
+ insn_test_shl1addx_X0.c insn_test_shl1addx_X1.c \
+ insn_test_shl1addx_Y0.c insn_test_shl1addx_Y1.c \
+ insn_test_shl2add_X0.c insn_test_shl2add_X1.c \
+ insn_test_shl2add_Y0.c insn_test_shl2add_Y1.c \
+ insn_test_shl2addx_X0.c insn_test_shl2addx_X1.c \
+ insn_test_shl2addx_Y0.c insn_test_shl2addx_Y1.c \
+ insn_test_shl3add_X0.c insn_test_shl3add_X1.c \
+ insn_test_shl3add_Y0.c insn_test_shl3add_Y1.c \
+ insn_test_shl3addx_X0.c insn_test_shl3addx_X1.c \
+ insn_test_shl3addx_Y0.c insn_test_shl3addx_Y1.c \
+ insn_test_shl_X0.c insn_test_shl_X1.c insn_test_shl_Y0.c \
+ insn_test_shl_Y1.c insn_test_shli_X0.c insn_test_shli_X1.c \
+ insn_test_shli_Y0.c insn_test_shli_Y1.c insn_test_shlx_X0.c \
+ insn_test_shlx_X1.c insn_test_shlxi_X0.c insn_test_shlxi_X1.c \
+ insn_test_shrs_X0.c insn_test_shrs_X1.c insn_test_shrs_Y0.c \
+ insn_test_shrs_Y1.c insn_test_shrsi_X0.c insn_test_shrsi_X1.c \
+ insn_test_shrsi_Y0.c insn_test_shrsi_Y1.c insn_test_shru_X0.c \
+ insn_test_shru_X1.c insn_test_shru_Y0.c insn_test_shru_Y1.c \
+ insn_test_shrui_X0.c insn_test_shrui_X1.c insn_test_shrui_Y0.c \
+ insn_test_shrui_Y1.c insn_test_shrux_X0.c insn_test_shrux_X1.c \
+ insn_test_shufflebytes_X0.c insn_test_st1_X1.c \
+ insn_test_st1_Y2.c insn_test_st1_add_X1.c insn_test_st2_X1.c \
+ insn_test_st2_Y2.c insn_test_st2_add_X1.c insn_test_st4_X1.c \
+ insn_test_st4_Y2.c insn_test_st4_add_X1.c insn_test_st_X1.c \
+ insn_test_st_Y2.c insn_test_st_add_X1.c insn_test_stnt1_X1.c \
+ insn_test_stnt2_X1.c insn_test_stnt2_add_X1.c \
+ insn_test_stnt4_X1.c insn_test_stnt4_add_X1.c \
+ insn_test_stnt_X1.c insn_test_stnt_add_X1.c insn_test_sub_X0.c \
+ insn_test_sub_X1.c insn_test_sub_Y0.c insn_test_sub_Y1.c \
+ insn_test_subx_X0.c insn_test_subx_X1.c insn_test_subx_Y0.c \
+ insn_test_subx_Y1.c insn_test_tblidxb0_X0.c \
+ insn_test_tblidxb0_Y0.c insn_test_tblidxb1_X0.c \
+ insn_test_tblidxb1_Y0.c insn_test_tblidxb2_X0.c \
+ insn_test_tblidxb2_Y0.c insn_test_tblidxb3_X0.c \
+ insn_test_tblidxb3_Y0.c insn_test_v1add_X0.c \
+ insn_test_v1add_X1.c insn_test_v1adduc_X0.c \
+ insn_test_v1adduc_X1.c insn_test_v1adiffu_X0.c \
+ insn_test_v1avgu_X0.c insn_test_v1cmpeq_X0.c \
+ insn_test_v1cmpeq_X1.c insn_test_v1cmpeqi_X0.c \
+ insn_test_v1cmpeqi_X1.c insn_test_v1cmples_X0.c \
+ insn_test_v1cmples_X1.c insn_test_v1cmpleu_X0.c \
+ insn_test_v1cmpleu_X1.c insn_test_v1cmplts_X0.c \
+ insn_test_v1cmplts_X1.c insn_test_v1cmpltu_X0.c \
+ insn_test_v1cmpltu_X1.c insn_test_v1cmpne_X0.c \
+ insn_test_v1cmpne_X1.c insn_test_v1ddotpu_X0.c \
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+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations. Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+# -fno-builtin is important for defeating LLVM's idiom recognition
+# that somehow causes VG_(memset) to get into infinite recursion.
+AM_CFLAGS_BASE = -O2 -g -std=gnu99 -Wall -Wmissing-prototypes -Wshadow \
+ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \
+ @FLAG_W_CAST_ALIGN@ @FLAG_W_CAST_QUAL@ @FLAG_W_WRITE_STRINGS@ \
+ @FLAG_W_EMPTY_BODY@ @FLAG_W_FORMAT@ @FLAG_W_FORMAT_SIGNEDNESS@ \
+ @FLAG_W_FORMAT_SECURITY@ @FLAG_W_IGNORED_QUALIFIERS@ \
+ @FLAG_W_MISSING_PARAMETER_TYPE@ @FLAG_W_OLD_STYLE_DECLARATION@ \
+ @FLAG_FNO_STACK_PROTECTOR@ @FLAG_FSANITIZE@ \
+ -fno-strict-aliasing -fno-builtin $(am__append_1)
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_FALSE@ -fpic -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# These flags are used for building the preload shared objects (PSOs).
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending
+# into (and through) the preloads. Also, we must use any
+# -mpreferred-stack-boundary flag to build the preload shared
+# objects, since that risks misaligning the client's stack and
+# results in segfaults like (eg) #324050.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \
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+@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@
+
+
+# Flags for specific targets.
+#
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+# For building the core, coregrind/Makefile.am files add some extra things.
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+ -I$(top_srcdir) \
+ -I$(top_srcdir)/include \
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+ -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 \
+ -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \
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+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
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+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \
+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
+
+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
+ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
+ -marm -mcpu=cortex-a8 -g
+
+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@
+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
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+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
+AM_FLAG_M3264_X86_DARWIN = -arch i386
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+ -mmacosx-version-min=10.6 \
+ -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
+AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@
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+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
+AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@
+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@
+AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
+AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@
+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@
+AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ \
+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ @FLAG_M64@ -w
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) @FLAG_M64@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = \
+ filter_stderr
+
+EXTRA_DIST = gen_test.sh $(am__append_8)
+insn_tests = insn_test_move_X0 insn_test_move_X1 insn_test_move_Y0 \
+ insn_test_move_Y1 insn_test_movei_X0 insn_test_movei_X1 \
+ insn_test_movei_Y0 insn_test_movei_Y1 insn_test_moveli_X0 \
+ insn_test_moveli_X1 insn_test_prefetch_X1 \
+ insn_test_prefetch_Y2 insn_test_prefetch_l1_X1 \
+ insn_test_prefetch_l1_Y2 insn_test_prefetch_l2_X1 \
+ insn_test_prefetch_l2_Y2 insn_test_prefetch_l3_X1 \
+ insn_test_prefetch_l3_Y2 insn_test_add_X0 insn_test_add_X1 \
+ insn_test_add_Y0 insn_test_add_Y1 insn_test_addi_X0 \
+ insn_test_addi_X1 insn_test_addi_Y0 insn_test_addi_Y1 \
+ insn_test_addli_X0 insn_test_addli_X1 insn_test_addx_X0 \
+ insn_test_addx_X1 insn_test_addx_Y0 insn_test_addx_Y1 \
+ insn_test_addxi_X0 insn_test_addxi_X1 insn_test_addxi_Y0 \
+ insn_test_addxi_Y1 insn_test_addxli_X0 insn_test_addxli_X1 \
+ insn_test_addxsc_X0 insn_test_addxsc_X1 insn_test_and_X0 \
+ insn_test_and_X1 insn_test_and_Y0 insn_test_and_Y1 \
+ insn_test_andi_X0 insn_test_andi_X1 insn_test_andi_Y0 \
+ insn_test_andi_Y1 insn_test_beqz_X1 insn_test_beqzt_X1 \
+ insn_test_bfexts_X0 insn_test_bfextu_X0 insn_test_bfins_X0 \
+ insn_test_bgez_X1 insn_test_bgezt_X1 insn_test_bgtz_X1 \
+ insn_test_bgtzt_X1 insn_test_blbc_X1 insn_test_blbct_X1 \
+ insn_test_blbs_X1 insn_test_blbst_X1 insn_test_blez_X1 \
+ insn_test_blezt_X1 insn_test_bltz_X1 insn_test_bltzt_X1 \
+ insn_test_bnez_X1 insn_test_bnezt_X1 insn_test_clz_X0 \
+ insn_test_clz_Y0 insn_test_cmoveqz_X0 insn_test_cmoveqz_Y0 \
+ insn_test_cmovnez_X0 insn_test_cmovnez_Y0 insn_test_cmpeq_X0 \
+ insn_test_cmpeq_X1 insn_test_cmpeq_Y0 insn_test_cmpeq_Y1 \
+ insn_test_cmpeqi_X0 insn_test_cmpeqi_X1 insn_test_cmpeqi_Y0 \
+ insn_test_cmpeqi_Y1 insn_test_cmples_X0 insn_test_cmples_X1 \
+ insn_test_cmples_Y0 insn_test_cmples_Y1 insn_test_cmpleu_X0 \
+ insn_test_cmpleu_X1 insn_test_cmpleu_Y0 insn_test_cmpleu_Y1 \
+ insn_test_cmplts_X0 insn_test_cmplts_X1 insn_test_cmplts_Y0 \
+ insn_test_cmplts_Y1 insn_test_cmpltsi_X0 insn_test_cmpltsi_X1 \
+ insn_test_cmpltsi_Y0 insn_test_cmpltsi_Y1 insn_test_cmpltu_X0 \
+ insn_test_cmpltu_X1 insn_test_cmpltu_Y0 insn_test_cmpltu_Y1 \
+ insn_test_cmpltui_X0 insn_test_cmpltui_X1 insn_test_cmpne_X0 \
+ insn_test_cmpne_X1 insn_test_cmpne_Y0 insn_test_cmpne_Y1 \
+ insn_test_cmul_X0 insn_test_cmula_X0 insn_test_cmulaf_X0 \
+ insn_test_cmulf_X0 insn_test_cmulfr_X0 insn_test_cmulh_X0 \
+ insn_test_cmulhr_X0 insn_test_crc32_32_X0 insn_test_crc32_8_X0 \
+ insn_test_ctz_X0 insn_test_ctz_Y0 insn_test_dblalign_X0 \
+ insn_test_dblalign2_X0 insn_test_dblalign2_X1 \
+ insn_test_dblalign4_X0 insn_test_dblalign4_X1 \
+ insn_test_dblalign6_X0 insn_test_dblalign6_X1 \
+ insn_test_dtlbpr_X1 insn_test_fdouble_add_flags_X0 \
+ insn_test_fdouble_addsub_X0 insn_test_fdouble_mul_flags_X0 \
+ insn_test_fdouble_pack1_X0 insn_test_fdouble_pack2_X0 \
+ insn_test_fdouble_sub_flags_X0 insn_test_fdouble_unpack_max_X0 \
+ insn_test_fdouble_unpack_min_X0 insn_test_flushwb_X1 \
+ insn_test_fnop_X0 insn_test_fnop_X1 insn_test_fnop_Y0 \
+ insn_test_fnop_Y1 insn_test_fsingle_add1_X0 \
+ insn_test_fsingle_addsub2_X0 insn_test_fsingle_mul1_X0 \
+ insn_test_fsingle_mul2_X0 insn_test_fsingle_pack1_X0 \
+ insn_test_fsingle_pack1_Y0 insn_test_fsingle_pack2_X0 \
+ insn_test_fsingle_sub1_X0 insn_test_icoh_X1 insn_test_j_X1 \
+ insn_test_jal_X1 insn_test_jalr_X1 insn_test_jalr_Y1 \
+ insn_test_jalrp_X1 insn_test_jalrp_Y1 insn_test_jr_X1 \
+ insn_test_jr_Y1 insn_test_jrp_X1 insn_test_jrp_Y1 \
+ insn_test_ld_X1 insn_test_ld_Y2 insn_test_ld1s_X1 \
+ insn_test_ld1s_Y2 insn_test_ld1s_add_X1 insn_test_ld1u_X1 \
+ insn_test_ld1u_Y2 insn_test_ld1u_add_X1 insn_test_ld2s_X1 \
+ insn_test_ld2s_Y2 insn_test_ld2u_X1 insn_test_ld2u_Y2 \
+ insn_test_ld4s_X1 insn_test_ld4s_add_X1 insn_test_ld4u_X1 \
+ insn_test_ld4u_Y2 insn_test_ld4u_add_X1 insn_test_ld_add_X1 \
+ insn_test_ldna_X1 insn_test_ldna_add_X1 insn_test_ldnt_X1 \
+ insn_test_ldnt1s_X1 insn_test_ldnt1s_add_X1 \
+ insn_test_ldnt1u_X1 insn_test_ldnt1u_add_X1 \
+ insn_test_ldnt2s_X1 insn_test_ldnt2s_add_X1 \
+ insn_test_ldnt2u_add_X1 insn_test_ldnt4s_X1 \
+ insn_test_ldnt4s_add_X1 insn_test_ldnt4u_X1 \
+ insn_test_ldnt4u_add_X1 insn_test_ldnt_add_X1 insn_test_lnk_X1 \
+ insn_test_lnk_Y1 insn_test_mf_X1 insn_test_mm_X0 \
+ insn_test_mnz_X0 insn_test_mnz_X1 insn_test_mnz_Y0 \
+ insn_test_mnz_Y1 insn_test_mul_hs_hs_X0 insn_test_mul_hs_hs_Y0 \
+ insn_test_mul_hs_hu_X0 insn_test_mul_hs_ls_X0 \
+ insn_test_mul_hs_lu_X0 insn_test_mul_hu_hu_X0 \
+ insn_test_mul_hu_hu_Y0 insn_test_mul_hu_lu_X0 \
+ insn_test_mul_ls_ls_X0 insn_test_mul_ls_ls_Y0 \
+ insn_test_mul_ls_lu_X0 insn_test_mul_lu_lu_X0 \
+ insn_test_mul_lu_lu_Y0 insn_test_mula_hs_hs_X0 \
+ insn_test_mula_hs_hs_Y0 insn_test_mula_hs_hu_X0 \
+ insn_test_mula_hs_ls_X0 insn_test_mula_hs_lu_X0 \
+ insn_test_mula_hu_hu_X0 insn_test_mula_hu_hu_Y0 \
+ insn_test_mula_hu_ls_X0 insn_test_mula_hu_lu_X0 \
+ insn_test_mula_ls_ls_X0 insn_test_mula_ls_ls_Y0 \
+ insn_test_mula_ls_lu_X0 insn_test_mula_lu_lu_X0 \
+ insn_test_mula_lu_lu_Y0 insn_test_mulax_X0 insn_test_mulax_Y0 \
+ insn_test_mulx_X0 insn_test_mulx_Y0 insn_test_mz_X0 \
+ insn_test_mz_X1 insn_test_mz_Y0 insn_test_mz_Y1 \
+ insn_test_nop_X0 insn_test_nop_X1 insn_test_nop_Y0 \
+ insn_test_nop_Y1 insn_test_nor_X0 insn_test_nor_X1 \
+ insn_test_nor_Y0 insn_test_nor_Y1 insn_test_or_X0 \
+ insn_test_or_X1 insn_test_or_Y0 insn_test_or_Y1 \
+ insn_test_ori_X0 insn_test_ori_X1 insn_test_pcnt_X0 \
+ insn_test_pcnt_Y0 insn_test_revbits_X0 insn_test_revbits_Y0 \
+ insn_test_revbytes_X0 insn_test_revbytes_Y0 insn_test_rotl_X0 \
+ insn_test_rotl_X1 insn_test_rotl_Y0 insn_test_rotl_Y1 \
+ insn_test_rotli_X0 insn_test_rotli_X1 insn_test_rotli_Y0 \
+ insn_test_rotli_Y1 insn_test_shl_X0 insn_test_shl_X1 \
+ insn_test_shl_Y0 insn_test_shl_Y1 insn_test_shl16insli_X0 \
+ insn_test_shl16insli_X1 insn_test_shl1add_X0 \
+ insn_test_shl1add_X1 insn_test_shl1add_Y0 insn_test_shl1add_Y1 \
+ insn_test_shl1addx_X0 insn_test_shl1addx_X1 \
+ insn_test_shl1addx_Y0 insn_test_shl1addx_Y1 \
+ insn_test_shl2add_X0 insn_test_shl2add_X1 insn_test_shl2add_Y0 \
+ insn_test_shl2add_Y1 insn_test_shl2addx_X0 \
+ insn_test_shl2addx_X1 insn_test_shl2addx_Y0 \
+ insn_test_shl2addx_Y1 insn_test_shl3add_X0 \
+ insn_test_shl3add_X1 insn_test_shl3add_Y0 insn_test_shl3add_Y1 \
+ insn_test_shl3addx_X0 insn_test_shl3addx_X1 \
+ insn_test_shl3addx_Y0 insn_test_shl3addx_Y1 insn_test_shli_X0 \
+ insn_test_shli_X1 insn_test_shli_Y0 insn_test_shli_Y1 \
+ insn_test_shlx_X0 insn_test_shlx_X1 insn_test_shlxi_X0 \
+ insn_test_shlxi_X1 insn_test_shrs_X0 insn_test_shrs_X1 \
+ insn_test_shrs_Y0 insn_test_shrs_Y1 insn_test_shrsi_X0 \
+ insn_test_shrsi_X1 insn_test_shrsi_Y0 insn_test_shrsi_Y1 \
+ insn_test_shru_X0 insn_test_shru_X1 insn_test_shru_Y0 \
+ insn_test_shru_Y1 insn_test_shrui_X0 insn_test_shrui_X1 \
+ insn_test_shrui_Y0 insn_test_shrui_Y1 insn_test_shrux_X0 \
+ insn_test_shrux_X1 insn_test_shufflebytes_X0 insn_test_st_X1 \
+ insn_test_st_Y2 insn_test_st1_X1 insn_test_st1_Y2 \
+ insn_test_st1_add_X1 insn_test_st2_X1 insn_test_st2_Y2 \
+ insn_test_st2_add_X1 insn_test_st4_X1 insn_test_st4_Y2 \
+ insn_test_st4_add_X1 insn_test_st_add_X1 insn_test_stnt_X1 \
+ insn_test_stnt1_X1 insn_test_stnt2_X1 insn_test_stnt2_add_X1 \
+ insn_test_stnt4_X1 insn_test_stnt4_add_X1 \
+ insn_test_stnt_add_X1 insn_test_sub_X0 insn_test_sub_X1 \
+ insn_test_sub_Y0 insn_test_sub_Y1 insn_test_subx_X0 \
+ insn_test_subx_X1 insn_test_subx_Y0 insn_test_subx_Y1 \
+ insn_test_tblidxb0_X0 insn_test_tblidxb0_Y0 \
+ insn_test_tblidxb1_X0 insn_test_tblidxb1_Y0 \
+ insn_test_tblidxb2_X0 insn_test_tblidxb2_Y0 \
+ insn_test_tblidxb3_X0 insn_test_tblidxb3_Y0 insn_test_v1add_X0 \
+ insn_test_v1add_X1 insn_test_v1adduc_X0 insn_test_v1adduc_X1 \
+ insn_test_v1adiffu_X0 insn_test_v1avgu_X0 insn_test_v1cmpeq_X0 \
+ insn_test_v1cmpeq_X1 insn_test_v1cmpeqi_X0 \
+ insn_test_v1cmpeqi_X1 insn_test_v1cmples_X0 \
+ insn_test_v1cmples_X1 insn_test_v1cmpleu_X0 \
+ insn_test_v1cmpleu_X1 insn_test_v1cmplts_X0 \
+ insn_test_v1cmplts_X1 insn_test_v1cmpltu_X0 \
+ insn_test_v1cmpltu_X1 insn_test_v1cmpne_X0 \
+ insn_test_v1cmpne_X1 insn_test_v1ddotpu_X0 \
+ insn_test_v1ddotpua_X0 insn_test_v1ddotpus_X0 \
+ insn_test_v1ddotpusa_X0 insn_test_v1dotp_X0 \
+ insn_test_v1dotpa_X0 insn_test_v1dotpu_X0 \
+ insn_test_v1dotpua_X0 insn_test_v1dotpus_X0 \
+ insn_test_v1dotpusa_X0 insn_test_v1int_h_X0 \
+ insn_test_v1int_h_X1 insn_test_v1int_l_X0 insn_test_v1int_l_X1 \
+ insn_test_v1maxu_X0 insn_test_v1maxu_X1 insn_test_v1minu_X0 \
+ insn_test_v1minu_X1 insn_test_v1mnz_X0 insn_test_v1mnz_X1 \
+ insn_test_v1multu_X0 insn_test_v1mulu_X0 insn_test_v1mulus_X0 \
+ insn_test_v1mz_X0 insn_test_v1mz_X1 insn_test_v1sadau_X0 \
+ insn_test_v1sadu_X0 insn_test_v1shl_X0 insn_test_v1shl_X1 \
+ insn_test_v1shli_X0 insn_test_v1shli_X1 insn_test_v1shrs_X0 \
+ insn_test_v1shrs_X1 insn_test_v1shrsi_X0 insn_test_v1shrsi_X1 \
+ insn_test_v1shru_X0 insn_test_v1shru_X1 insn_test_v1shrui_X0 \
+ insn_test_v1shrui_X1 insn_test_v1sub_X0 insn_test_v1sub_X1 \
+ insn_test_v1subuc_X0 insn_test_v1subuc_X1 insn_test_v2add_X0 \
+ insn_test_v2add_X1 insn_test_v2addsc_X0 insn_test_v2addsc_X1 \
+ insn_test_v2adiffs_X0 insn_test_v2avgs_X0 insn_test_v2cmpeq_X0 \
+ insn_test_v2cmpeq_X1 insn_test_v2cmpeqi_X0 \
+ insn_test_v2cmpeqi_X1 insn_test_v2cmples_X0 \
+ insn_test_v2cmples_X1 insn_test_v2cmpleu_X0 \
+ insn_test_v2cmpleu_X1 insn_test_v2cmplts_X0 \
+ insn_test_v2cmplts_X1 insn_test_v2cmpltsi_X0 \
+ insn_test_v2cmpltsi_X1 insn_test_v2cmpltu_X0 \
+ insn_test_v2cmpltu_X1 insn_test_v2cmpltui_X0 \
+ insn_test_v2cmpltui_X1 insn_test_v2cmpne_X0 \
+ insn_test_v2cmpne_X1 insn_test_v2dotp_X0 insn_test_v2dotpa_X0 \
+ insn_test_v2int_h_X0 insn_test_v2int_h_X1 insn_test_v2int_l_X0 \
+ insn_test_v2int_l_X1 insn_test_v2maxs_X0 insn_test_v2maxs_X1 \
+ insn_test_v2mins_X0 insn_test_v2mins_X1 insn_test_v2mnz_X0 \
+ insn_test_v2mnz_X1 insn_test_v2mulfsc_X0 insn_test_v2muls_X0 \
+ insn_test_v2mults_X0 insn_test_v2mz_X0 insn_test_v2mz_X1 \
+ insn_test_v2packh_X0 insn_test_v2packh_X1 insn_test_v2packl_X0 \
+ insn_test_v2packl_X1 insn_test_v2packuc_X0 \
+ insn_test_v2packuc_X1 insn_test_v2sadas_X0 \
+ insn_test_v2sadau_X0 insn_test_v2sads_X0 insn_test_v2sadu_X0 \
+ insn_test_v2shl_X0 insn_test_v2shl_X1 insn_test_v2shli_X0 \
+ insn_test_v2shli_X1 insn_test_v2shlsc_X0 insn_test_v2shlsc_X1 \
+ insn_test_v2shrs_X0 insn_test_v2shrs_X1 insn_test_v2shrsi_X0 \
+ insn_test_v2shrsi_X1 insn_test_v2shru_X0 insn_test_v2shru_X1 \
+ insn_test_v2shrui_X0 insn_test_v2shrui_X1 insn_test_v2sub_X0 \
+ insn_test_v2sub_X1 insn_test_v2subsc_X0 insn_test_v2subsc_X1 \
+ insn_test_v4add_X0 insn_test_v4add_X1 insn_test_v4addsc_X0 \
+ insn_test_v4addsc_X1 insn_test_v4int_h_X0 insn_test_v4int_h_X1 \
+ insn_test_v4int_l_X0 insn_test_v4int_l_X1 \
+ insn_test_v4packsc_X0 insn_test_v4packsc_X1 insn_test_v4shl_X0 \
+ insn_test_v4shl_X1 insn_test_v4shlsc_X0 insn_test_v4shlsc_X1 \
+ insn_test_v4shrs_X0 insn_test_v4shrs_X1 insn_test_v4shru_X0 \
+ insn_test_v4shru_X1 insn_test_v4sub_X0 insn_test_v4sub_X1 \
+ insn_test_v4subsc_X0 insn_test_v4subsc_X1 insn_test_wh64_X1 \
+ insn_test_xor_X0 insn_test_xor_X1 insn_test_xor_Y0 \
+ insn_test_xor_Y1 insn_test_xori_X0 insn_test_xori_X1
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+gen_insn_test_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@ -I$(top_srcdir)/VEX/priv
+gen_insn_test_LDADD = ../../../VEX/priv/tilegx_disasm.o
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/tilegx/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/tilegx/Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+$(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__empty):
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+install-binPROGRAMS: $(bin_PROGRAMS)
+ @$(NORMAL_INSTALL)
+ @list='$(bin_PROGRAMS)'; test -n "$(bindir)" || list=; \
+ if test -n "$$list"; then \
+ echo " $(MKDIR_P) '$(DESTDIR)$(bindir)'"; \
+ $(MKDIR_P) "$(DESTDIR)$(bindir)" || exit 1; \
+ fi; \
+ for p in $$list; do echo "$$p $$p"; done | \
+ sed 's/$(EXEEXT)$$//' | \
+ while read p p1; do if test -f $$p \
+ ; then echo "$$p"; echo "$$p"; else :; fi; \
+ done | \
+ sed -e 'p;s,.*/,,;n;h' \
+ -e 's|.*|.|' \
+ -e 'p;x;s,.*/,,;s/$(EXEEXT)$$//;$(transform);s/$$/$(EXEEXT)/' | \
+ sed 'N;N;N;s,\n, ,g' | \
+ $(AWK) 'BEGIN { files["."] = ""; dirs["."] = 1 } \
+ { d=$$3; if (dirs[d] != 1) { print "d", d; dirs[d] = 1 } \
+ if ($$2 == $$4) files[d] = files[d] " " $$1; \
+ else { print "f", $$3 "/" $$4, $$1; } } \
+ END { for (d in files) print "f", d, files[d] }' | \
+ while read type dir files; do \
+ if test "$$dir" = .; then dir=; else dir=/$$dir; fi; \
+ test -z "$$files" || { \
+ echo " $(INSTALL_PROGRAM_ENV) $(INSTALL_PROGRAM) $$files '$(DESTDIR)$(bindir)$$dir'"; \
+ $(INSTALL_PROGRAM_ENV) $(INSTALL_PROGRAM) $$files "$(DESTDIR)$(bindir)$$dir" || exit $$?; \
+ } \
+ ; done
+
+uninstall-binPROGRAMS:
+ @$(NORMAL_UNINSTALL)
+ @list='$(bin_PROGRAMS)'; test -n "$(bindir)" || list=; \
+ files=`for p in $$list; do echo "$$p"; done | \
+ sed -e 'h;s,^.*/,,;s/$(EXEEXT)$$//;$(transform)' \
+ -e 's/$$/$(EXEEXT)/' \
+ `; \
+ test -n "$$list" || exit 0; \
+ echo " ( cd '$(DESTDIR)$(bindir)' && rm -f" $$files ")"; \
+ cd "$(DESTDIR)$(bindir)" && rm -f $$files
+
+clean-binPROGRAMS:
+ -test -z "$(bin_PROGRAMS)" || rm -f $(bin_PROGRAMS)
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES) $(EXTRA_allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(AM_V_CCLD)$(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+
+gen_insn_test$(EXEEXT): $(gen_insn_test_OBJECTS) $(gen_insn_test_DEPENDENCIES) $(EXTRA_gen_insn_test_DEPENDENCIES)
+ @rm -f gen_insn_test$(EXEEXT)
+ $(AM_V_CCLD)$(gen_insn_test_LINK) $(gen_insn_test_OBJECTS) $(gen_insn_test_LDADD) $(LIBS)
+
+insn_test_add_X0$(EXEEXT): $(insn_test_add_X0_OBJECTS) $(insn_test_add_X0_DEPENDENCIES) $(EXTRA_insn_test_add_X0_DEPENDENCIES)
+ @rm -f insn_test_add_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_add_X0_OBJECTS) $(insn_test_add_X0_LDADD) $(LIBS)
+
+insn_test_add_X1$(EXEEXT): $(insn_test_add_X1_OBJECTS) $(insn_test_add_X1_DEPENDENCIES) $(EXTRA_insn_test_add_X1_DEPENDENCIES)
+ @rm -f insn_test_add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_add_X1_OBJECTS) $(insn_test_add_X1_LDADD) $(LIBS)
+
+insn_test_add_Y0$(EXEEXT): $(insn_test_add_Y0_OBJECTS) $(insn_test_add_Y0_DEPENDENCIES) $(EXTRA_insn_test_add_Y0_DEPENDENCIES)
+ @rm -f insn_test_add_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_add_Y0_OBJECTS) $(insn_test_add_Y0_LDADD) $(LIBS)
+
+insn_test_add_Y1$(EXEEXT): $(insn_test_add_Y1_OBJECTS) $(insn_test_add_Y1_DEPENDENCIES) $(EXTRA_insn_test_add_Y1_DEPENDENCIES)
+ @rm -f insn_test_add_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_add_Y1_OBJECTS) $(insn_test_add_Y1_LDADD) $(LIBS)
+
+insn_test_addi_X0$(EXEEXT): $(insn_test_addi_X0_OBJECTS) $(insn_test_addi_X0_DEPENDENCIES) $(EXTRA_insn_test_addi_X0_DEPENDENCIES)
+ @rm -f insn_test_addi_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addi_X0_OBJECTS) $(insn_test_addi_X0_LDADD) $(LIBS)
+
+insn_test_addi_X1$(EXEEXT): $(insn_test_addi_X1_OBJECTS) $(insn_test_addi_X1_DEPENDENCIES) $(EXTRA_insn_test_addi_X1_DEPENDENCIES)
+ @rm -f insn_test_addi_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addi_X1_OBJECTS) $(insn_test_addi_X1_LDADD) $(LIBS)
+
+insn_test_addi_Y0$(EXEEXT): $(insn_test_addi_Y0_OBJECTS) $(insn_test_addi_Y0_DEPENDENCIES) $(EXTRA_insn_test_addi_Y0_DEPENDENCIES)
+ @rm -f insn_test_addi_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addi_Y0_OBJECTS) $(insn_test_addi_Y0_LDADD) $(LIBS)
+
+insn_test_addi_Y1$(EXEEXT): $(insn_test_addi_Y1_OBJECTS) $(insn_test_addi_Y1_DEPENDENCIES) $(EXTRA_insn_test_addi_Y1_DEPENDENCIES)
+ @rm -f insn_test_addi_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addi_Y1_OBJECTS) $(insn_test_addi_Y1_LDADD) $(LIBS)
+
+insn_test_addli_X0$(EXEEXT): $(insn_test_addli_X0_OBJECTS) $(insn_test_addli_X0_DEPENDENCIES) $(EXTRA_insn_test_addli_X0_DEPENDENCIES)
+ @rm -f insn_test_addli_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addli_X0_OBJECTS) $(insn_test_addli_X0_LDADD) $(LIBS)
+
+insn_test_addli_X1$(EXEEXT): $(insn_test_addli_X1_OBJECTS) $(insn_test_addli_X1_DEPENDENCIES) $(EXTRA_insn_test_addli_X1_DEPENDENCIES)
+ @rm -f insn_test_addli_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addli_X1_OBJECTS) $(insn_test_addli_X1_LDADD) $(LIBS)
+
+insn_test_addx_X0$(EXEEXT): $(insn_test_addx_X0_OBJECTS) $(insn_test_addx_X0_DEPENDENCIES) $(EXTRA_insn_test_addx_X0_DEPENDENCIES)
+ @rm -f insn_test_addx_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addx_X0_OBJECTS) $(insn_test_addx_X0_LDADD) $(LIBS)
+
+insn_test_addx_X1$(EXEEXT): $(insn_test_addx_X1_OBJECTS) $(insn_test_addx_X1_DEPENDENCIES) $(EXTRA_insn_test_addx_X1_DEPENDENCIES)
+ @rm -f insn_test_addx_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addx_X1_OBJECTS) $(insn_test_addx_X1_LDADD) $(LIBS)
+
+insn_test_addx_Y0$(EXEEXT): $(insn_test_addx_Y0_OBJECTS) $(insn_test_addx_Y0_DEPENDENCIES) $(EXTRA_insn_test_addx_Y0_DEPENDENCIES)
+ @rm -f insn_test_addx_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addx_Y0_OBJECTS) $(insn_test_addx_Y0_LDADD) $(LIBS)
+
+insn_test_addx_Y1$(EXEEXT): $(insn_test_addx_Y1_OBJECTS) $(insn_test_addx_Y1_DEPENDENCIES) $(EXTRA_insn_test_addx_Y1_DEPENDENCIES)
+ @rm -f insn_test_addx_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addx_Y1_OBJECTS) $(insn_test_addx_Y1_LDADD) $(LIBS)
+
+insn_test_addxi_X0$(EXEEXT): $(insn_test_addxi_X0_OBJECTS) $(insn_test_addxi_X0_DEPENDENCIES) $(EXTRA_insn_test_addxi_X0_DEPENDENCIES)
+ @rm -f insn_test_addxi_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addxi_X0_OBJECTS) $(insn_test_addxi_X0_LDADD) $(LIBS)
+
+insn_test_addxi_X1$(EXEEXT): $(insn_test_addxi_X1_OBJECTS) $(insn_test_addxi_X1_DEPENDENCIES) $(EXTRA_insn_test_addxi_X1_DEPENDENCIES)
+ @rm -f insn_test_addxi_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addxi_X1_OBJECTS) $(insn_test_addxi_X1_LDADD) $(LIBS)
+
+insn_test_addxi_Y0$(EXEEXT): $(insn_test_addxi_Y0_OBJECTS) $(insn_test_addxi_Y0_DEPENDENCIES) $(EXTRA_insn_test_addxi_Y0_DEPENDENCIES)
+ @rm -f insn_test_addxi_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addxi_Y0_OBJECTS) $(insn_test_addxi_Y0_LDADD) $(LIBS)
+
+insn_test_addxi_Y1$(EXEEXT): $(insn_test_addxi_Y1_OBJECTS) $(insn_test_addxi_Y1_DEPENDENCIES) $(EXTRA_insn_test_addxi_Y1_DEPENDENCIES)
+ @rm -f insn_test_addxi_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addxi_Y1_OBJECTS) $(insn_test_addxi_Y1_LDADD) $(LIBS)
+
+insn_test_addxli_X0$(EXEEXT): $(insn_test_addxli_X0_OBJECTS) $(insn_test_addxli_X0_DEPENDENCIES) $(EXTRA_insn_test_addxli_X0_DEPENDENCIES)
+ @rm -f insn_test_addxli_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addxli_X0_OBJECTS) $(insn_test_addxli_X0_LDADD) $(LIBS)
+
+insn_test_addxli_X1$(EXEEXT): $(insn_test_addxli_X1_OBJECTS) $(insn_test_addxli_X1_DEPENDENCIES) $(EXTRA_insn_test_addxli_X1_DEPENDENCIES)
+ @rm -f insn_test_addxli_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addxli_X1_OBJECTS) $(insn_test_addxli_X1_LDADD) $(LIBS)
+
+insn_test_addxsc_X0$(EXEEXT): $(insn_test_addxsc_X0_OBJECTS) $(insn_test_addxsc_X0_DEPENDENCIES) $(EXTRA_insn_test_addxsc_X0_DEPENDENCIES)
+ @rm -f insn_test_addxsc_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addxsc_X0_OBJECTS) $(insn_test_addxsc_X0_LDADD) $(LIBS)
+
+insn_test_addxsc_X1$(EXEEXT): $(insn_test_addxsc_X1_OBJECTS) $(insn_test_addxsc_X1_DEPENDENCIES) $(EXTRA_insn_test_addxsc_X1_DEPENDENCIES)
+ @rm -f insn_test_addxsc_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_addxsc_X1_OBJECTS) $(insn_test_addxsc_X1_LDADD) $(LIBS)
+
+insn_test_and_X0$(EXEEXT): $(insn_test_and_X0_OBJECTS) $(insn_test_and_X0_DEPENDENCIES) $(EXTRA_insn_test_and_X0_DEPENDENCIES)
+ @rm -f insn_test_and_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_and_X0_OBJECTS) $(insn_test_and_X0_LDADD) $(LIBS)
+
+insn_test_and_X1$(EXEEXT): $(insn_test_and_X1_OBJECTS) $(insn_test_and_X1_DEPENDENCIES) $(EXTRA_insn_test_and_X1_DEPENDENCIES)
+ @rm -f insn_test_and_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_and_X1_OBJECTS) $(insn_test_and_X1_LDADD) $(LIBS)
+
+insn_test_and_Y0$(EXEEXT): $(insn_test_and_Y0_OBJECTS) $(insn_test_and_Y0_DEPENDENCIES) $(EXTRA_insn_test_and_Y0_DEPENDENCIES)
+ @rm -f insn_test_and_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_and_Y0_OBJECTS) $(insn_test_and_Y0_LDADD) $(LIBS)
+
+insn_test_and_Y1$(EXEEXT): $(insn_test_and_Y1_OBJECTS) $(insn_test_and_Y1_DEPENDENCIES) $(EXTRA_insn_test_and_Y1_DEPENDENCIES)
+ @rm -f insn_test_and_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_and_Y1_OBJECTS) $(insn_test_and_Y1_LDADD) $(LIBS)
+
+insn_test_andi_X0$(EXEEXT): $(insn_test_andi_X0_OBJECTS) $(insn_test_andi_X0_DEPENDENCIES) $(EXTRA_insn_test_andi_X0_DEPENDENCIES)
+ @rm -f insn_test_andi_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_andi_X0_OBJECTS) $(insn_test_andi_X0_LDADD) $(LIBS)
+
+insn_test_andi_X1$(EXEEXT): $(insn_test_andi_X1_OBJECTS) $(insn_test_andi_X1_DEPENDENCIES) $(EXTRA_insn_test_andi_X1_DEPENDENCIES)
+ @rm -f insn_test_andi_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_andi_X1_OBJECTS) $(insn_test_andi_X1_LDADD) $(LIBS)
+
+insn_test_andi_Y0$(EXEEXT): $(insn_test_andi_Y0_OBJECTS) $(insn_test_andi_Y0_DEPENDENCIES) $(EXTRA_insn_test_andi_Y0_DEPENDENCIES)
+ @rm -f insn_test_andi_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_andi_Y0_OBJECTS) $(insn_test_andi_Y0_LDADD) $(LIBS)
+
+insn_test_andi_Y1$(EXEEXT): $(insn_test_andi_Y1_OBJECTS) $(insn_test_andi_Y1_DEPENDENCIES) $(EXTRA_insn_test_andi_Y1_DEPENDENCIES)
+ @rm -f insn_test_andi_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_andi_Y1_OBJECTS) $(insn_test_andi_Y1_LDADD) $(LIBS)
+
+insn_test_beqz_X1$(EXEEXT): $(insn_test_beqz_X1_OBJECTS) $(insn_test_beqz_X1_DEPENDENCIES) $(EXTRA_insn_test_beqz_X1_DEPENDENCIES)
+ @rm -f insn_test_beqz_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_beqz_X1_OBJECTS) $(insn_test_beqz_X1_LDADD) $(LIBS)
+
+insn_test_beqzt_X1$(EXEEXT): $(insn_test_beqzt_X1_OBJECTS) $(insn_test_beqzt_X1_DEPENDENCIES) $(EXTRA_insn_test_beqzt_X1_DEPENDENCIES)
+ @rm -f insn_test_beqzt_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_beqzt_X1_OBJECTS) $(insn_test_beqzt_X1_LDADD) $(LIBS)
+
+insn_test_bfexts_X0$(EXEEXT): $(insn_test_bfexts_X0_OBJECTS) $(insn_test_bfexts_X0_DEPENDENCIES) $(EXTRA_insn_test_bfexts_X0_DEPENDENCIES)
+ @rm -f insn_test_bfexts_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_bfexts_X0_OBJECTS) $(insn_test_bfexts_X0_LDADD) $(LIBS)
+
+insn_test_bfextu_X0$(EXEEXT): $(insn_test_bfextu_X0_OBJECTS) $(insn_test_bfextu_X0_DEPENDENCIES) $(EXTRA_insn_test_bfextu_X0_DEPENDENCIES)
+ @rm -f insn_test_bfextu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_bfextu_X0_OBJECTS) $(insn_test_bfextu_X0_LDADD) $(LIBS)
+
+insn_test_bfins_X0$(EXEEXT): $(insn_test_bfins_X0_OBJECTS) $(insn_test_bfins_X0_DEPENDENCIES) $(EXTRA_insn_test_bfins_X0_DEPENDENCIES)
+ @rm -f insn_test_bfins_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_bfins_X0_OBJECTS) $(insn_test_bfins_X0_LDADD) $(LIBS)
+
+insn_test_bgez_X1$(EXEEXT): $(insn_test_bgez_X1_OBJECTS) $(insn_test_bgez_X1_DEPENDENCIES) $(EXTRA_insn_test_bgez_X1_DEPENDENCIES)
+ @rm -f insn_test_bgez_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_bgez_X1_OBJECTS) $(insn_test_bgez_X1_LDADD) $(LIBS)
+
+insn_test_bgezt_X1$(EXEEXT): $(insn_test_bgezt_X1_OBJECTS) $(insn_test_bgezt_X1_DEPENDENCIES) $(EXTRA_insn_test_bgezt_X1_DEPENDENCIES)
+ @rm -f insn_test_bgezt_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_bgezt_X1_OBJECTS) $(insn_test_bgezt_X1_LDADD) $(LIBS)
+
+insn_test_bgtz_X1$(EXEEXT): $(insn_test_bgtz_X1_OBJECTS) $(insn_test_bgtz_X1_DEPENDENCIES) $(EXTRA_insn_test_bgtz_X1_DEPENDENCIES)
+ @rm -f insn_test_bgtz_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_bgtz_X1_OBJECTS) $(insn_test_bgtz_X1_LDADD) $(LIBS)
+
+insn_test_bgtzt_X1$(EXEEXT): $(insn_test_bgtzt_X1_OBJECTS) $(insn_test_bgtzt_X1_DEPENDENCIES) $(EXTRA_insn_test_bgtzt_X1_DEPENDENCIES)
+ @rm -f insn_test_bgtzt_X1$(EXEEXT)
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+
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+ @rm -f insn_test_cmulfr_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_cmulfr_X0_OBJECTS) $(insn_test_cmulfr_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_cmulh_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_cmulh_X0_OBJECTS) $(insn_test_cmulh_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_cmulhr_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_cmulhr_X0_OBJECTS) $(insn_test_cmulhr_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_crc32_32_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_crc32_32_X0_OBJECTS) $(insn_test_crc32_32_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_crc32_8_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_crc32_8_X0_OBJECTS) $(insn_test_crc32_8_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_ctz_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ctz_X0_OBJECTS) $(insn_test_ctz_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_ctz_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ctz_Y0_OBJECTS) $(insn_test_ctz_Y0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_dblalign2_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_dblalign2_X0_OBJECTS) $(insn_test_dblalign2_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_dblalign2_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_dblalign2_X1_OBJECTS) $(insn_test_dblalign2_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_dblalign4_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_dblalign4_X0_OBJECTS) $(insn_test_dblalign4_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_dblalign4_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_dblalign4_X1_OBJECTS) $(insn_test_dblalign4_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_dblalign6_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_dblalign6_X0_OBJECTS) $(insn_test_dblalign6_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_dblalign6_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_dblalign6_X1_OBJECTS) $(insn_test_dblalign6_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_dblalign_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_dblalign_X0_OBJECTS) $(insn_test_dblalign_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_dtlbpr_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_dtlbpr_X1_OBJECTS) $(insn_test_dtlbpr_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fdouble_add_flags_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fdouble_add_flags_X0_OBJECTS) $(insn_test_fdouble_add_flags_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fdouble_addsub_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fdouble_addsub_X0_OBJECTS) $(insn_test_fdouble_addsub_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fdouble_mul_flags_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fdouble_mul_flags_X0_OBJECTS) $(insn_test_fdouble_mul_flags_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fdouble_pack1_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fdouble_pack1_X0_OBJECTS) $(insn_test_fdouble_pack1_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fdouble_pack2_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fdouble_pack2_X0_OBJECTS) $(insn_test_fdouble_pack2_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fdouble_sub_flags_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fdouble_sub_flags_X0_OBJECTS) $(insn_test_fdouble_sub_flags_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fdouble_unpack_max_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fdouble_unpack_max_X0_OBJECTS) $(insn_test_fdouble_unpack_max_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fdouble_unpack_min_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fdouble_unpack_min_X0_OBJECTS) $(insn_test_fdouble_unpack_min_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_flushwb_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_flushwb_X1_OBJECTS) $(insn_test_flushwb_X1_LDADD) $(LIBS)
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+ @rm -f insn_test_fnop_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fnop_X0_OBJECTS) $(insn_test_fnop_X0_LDADD) $(LIBS)
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+ @rm -f insn_test_fnop_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fnop_X1_OBJECTS) $(insn_test_fnop_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fnop_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fnop_Y0_OBJECTS) $(insn_test_fnop_Y0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fnop_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fnop_Y1_OBJECTS) $(insn_test_fnop_Y1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fsingle_add1_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fsingle_add1_X0_OBJECTS) $(insn_test_fsingle_add1_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fsingle_addsub2_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fsingle_addsub2_X0_OBJECTS) $(insn_test_fsingle_addsub2_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fsingle_mul1_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fsingle_mul1_X0_OBJECTS) $(insn_test_fsingle_mul1_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fsingle_mul2_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fsingle_mul2_X0_OBJECTS) $(insn_test_fsingle_mul2_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fsingle_pack1_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fsingle_pack1_X0_OBJECTS) $(insn_test_fsingle_pack1_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_fsingle_pack1_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fsingle_pack1_Y0_OBJECTS) $(insn_test_fsingle_pack1_Y0_LDADD) $(LIBS)
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+ @rm -f insn_test_fsingle_pack2_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fsingle_pack2_X0_OBJECTS) $(insn_test_fsingle_pack2_X0_LDADD) $(LIBS)
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+ @rm -f insn_test_fsingle_sub1_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_fsingle_sub1_X0_OBJECTS) $(insn_test_fsingle_sub1_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_icoh_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_icoh_X1_OBJECTS) $(insn_test_icoh_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_j_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_j_X1_OBJECTS) $(insn_test_j_X1_LDADD) $(LIBS)
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+ @rm -f insn_test_jal_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_jal_X1_OBJECTS) $(insn_test_jal_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_jalr_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_jalr_X1_OBJECTS) $(insn_test_jalr_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_jalr_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_jalr_Y1_OBJECTS) $(insn_test_jalr_Y1_LDADD) $(LIBS)
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+ @rm -f insn_test_jalrp_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_jalrp_X1_OBJECTS) $(insn_test_jalrp_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_jalrp_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_jalrp_Y1_OBJECTS) $(insn_test_jalrp_Y1_LDADD) $(LIBS)
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+ @rm -f insn_test_jr_X1$(EXEEXT)
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+ @rm -f insn_test_jr_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_jr_Y1_OBJECTS) $(insn_test_jr_Y1_LDADD) $(LIBS)
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+ @rm -f insn_test_jrp_X1$(EXEEXT)
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+ @rm -f insn_test_jrp_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_jrp_Y1_OBJECTS) $(insn_test_jrp_Y1_LDADD) $(LIBS)
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+ @rm -f insn_test_ld1s_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld1s_X1_OBJECTS) $(insn_test_ld1s_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_ld1s_Y2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld1s_Y2_OBJECTS) $(insn_test_ld1s_Y2_LDADD) $(LIBS)
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+ @rm -f insn_test_ld1s_add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld1s_add_X1_OBJECTS) $(insn_test_ld1s_add_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_ld1u_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld1u_X1_OBJECTS) $(insn_test_ld1u_X1_LDADD) $(LIBS)
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+ @rm -f insn_test_ld1u_Y2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld1u_Y2_OBJECTS) $(insn_test_ld1u_Y2_LDADD) $(LIBS)
+
+insn_test_ld1u_add_X1$(EXEEXT): $(insn_test_ld1u_add_X1_OBJECTS) $(insn_test_ld1u_add_X1_DEPENDENCIES) $(EXTRA_insn_test_ld1u_add_X1_DEPENDENCIES)
+ @rm -f insn_test_ld1u_add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld1u_add_X1_OBJECTS) $(insn_test_ld1u_add_X1_LDADD) $(LIBS)
+
+insn_test_ld2s_X1$(EXEEXT): $(insn_test_ld2s_X1_OBJECTS) $(insn_test_ld2s_X1_DEPENDENCIES) $(EXTRA_insn_test_ld2s_X1_DEPENDENCIES)
+ @rm -f insn_test_ld2s_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld2s_X1_OBJECTS) $(insn_test_ld2s_X1_LDADD) $(LIBS)
+
+insn_test_ld2s_Y2$(EXEEXT): $(insn_test_ld2s_Y2_OBJECTS) $(insn_test_ld2s_Y2_DEPENDENCIES) $(EXTRA_insn_test_ld2s_Y2_DEPENDENCIES)
+ @rm -f insn_test_ld2s_Y2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld2s_Y2_OBJECTS) $(insn_test_ld2s_Y2_LDADD) $(LIBS)
+
+insn_test_ld2u_X1$(EXEEXT): $(insn_test_ld2u_X1_OBJECTS) $(insn_test_ld2u_X1_DEPENDENCIES) $(EXTRA_insn_test_ld2u_X1_DEPENDENCIES)
+ @rm -f insn_test_ld2u_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld2u_X1_OBJECTS) $(insn_test_ld2u_X1_LDADD) $(LIBS)
+
+insn_test_ld2u_Y2$(EXEEXT): $(insn_test_ld2u_Y2_OBJECTS) $(insn_test_ld2u_Y2_DEPENDENCIES) $(EXTRA_insn_test_ld2u_Y2_DEPENDENCIES)
+ @rm -f insn_test_ld2u_Y2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld2u_Y2_OBJECTS) $(insn_test_ld2u_Y2_LDADD) $(LIBS)
+
+insn_test_ld4s_X1$(EXEEXT): $(insn_test_ld4s_X1_OBJECTS) $(insn_test_ld4s_X1_DEPENDENCIES) $(EXTRA_insn_test_ld4s_X1_DEPENDENCIES)
+ @rm -f insn_test_ld4s_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld4s_X1_OBJECTS) $(insn_test_ld4s_X1_LDADD) $(LIBS)
+
+insn_test_ld4s_add_X1$(EXEEXT): $(insn_test_ld4s_add_X1_OBJECTS) $(insn_test_ld4s_add_X1_DEPENDENCIES) $(EXTRA_insn_test_ld4s_add_X1_DEPENDENCIES)
+ @rm -f insn_test_ld4s_add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld4s_add_X1_OBJECTS) $(insn_test_ld4s_add_X1_LDADD) $(LIBS)
+
+insn_test_ld4u_X1$(EXEEXT): $(insn_test_ld4u_X1_OBJECTS) $(insn_test_ld4u_X1_DEPENDENCIES) $(EXTRA_insn_test_ld4u_X1_DEPENDENCIES)
+ @rm -f insn_test_ld4u_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld4u_X1_OBJECTS) $(insn_test_ld4u_X1_LDADD) $(LIBS)
+
+insn_test_ld4u_Y2$(EXEEXT): $(insn_test_ld4u_Y2_OBJECTS) $(insn_test_ld4u_Y2_DEPENDENCIES) $(EXTRA_insn_test_ld4u_Y2_DEPENDENCIES)
+ @rm -f insn_test_ld4u_Y2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld4u_Y2_OBJECTS) $(insn_test_ld4u_Y2_LDADD) $(LIBS)
+
+insn_test_ld4u_add_X1$(EXEEXT): $(insn_test_ld4u_add_X1_OBJECTS) $(insn_test_ld4u_add_X1_DEPENDENCIES) $(EXTRA_insn_test_ld4u_add_X1_DEPENDENCIES)
+ @rm -f insn_test_ld4u_add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld4u_add_X1_OBJECTS) $(insn_test_ld4u_add_X1_LDADD) $(LIBS)
+
+insn_test_ld_X1$(EXEEXT): $(insn_test_ld_X1_OBJECTS) $(insn_test_ld_X1_DEPENDENCIES) $(EXTRA_insn_test_ld_X1_DEPENDENCIES)
+ @rm -f insn_test_ld_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld_X1_OBJECTS) $(insn_test_ld_X1_LDADD) $(LIBS)
+
+insn_test_ld_Y2$(EXEEXT): $(insn_test_ld_Y2_OBJECTS) $(insn_test_ld_Y2_DEPENDENCIES) $(EXTRA_insn_test_ld_Y2_DEPENDENCIES)
+ @rm -f insn_test_ld_Y2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld_Y2_OBJECTS) $(insn_test_ld_Y2_LDADD) $(LIBS)
+
+insn_test_ld_add_X1$(EXEEXT): $(insn_test_ld_add_X1_OBJECTS) $(insn_test_ld_add_X1_DEPENDENCIES) $(EXTRA_insn_test_ld_add_X1_DEPENDENCIES)
+ @rm -f insn_test_ld_add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ld_add_X1_OBJECTS) $(insn_test_ld_add_X1_LDADD) $(LIBS)
+
+insn_test_ldna_X1$(EXEEXT): $(insn_test_ldna_X1_OBJECTS) $(insn_test_ldna_X1_DEPENDENCIES) $(EXTRA_insn_test_ldna_X1_DEPENDENCIES)
+ @rm -f insn_test_ldna_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldna_X1_OBJECTS) $(insn_test_ldna_X1_LDADD) $(LIBS)
+
+insn_test_ldna_add_X1$(EXEEXT): $(insn_test_ldna_add_X1_OBJECTS) $(insn_test_ldna_add_X1_DEPENDENCIES) $(EXTRA_insn_test_ldna_add_X1_DEPENDENCIES)
+ @rm -f insn_test_ldna_add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldna_add_X1_OBJECTS) $(insn_test_ldna_add_X1_LDADD) $(LIBS)
+
+insn_test_ldnt1s_X1$(EXEEXT): $(insn_test_ldnt1s_X1_OBJECTS) $(insn_test_ldnt1s_X1_DEPENDENCIES) $(EXTRA_insn_test_ldnt1s_X1_DEPENDENCIES)
+ @rm -f insn_test_ldnt1s_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldnt1s_X1_OBJECTS) $(insn_test_ldnt1s_X1_LDADD) $(LIBS)
+
+insn_test_ldnt1s_add_X1$(EXEEXT): $(insn_test_ldnt1s_add_X1_OBJECTS) $(insn_test_ldnt1s_add_X1_DEPENDENCIES) $(EXTRA_insn_test_ldnt1s_add_X1_DEPENDENCIES)
+ @rm -f insn_test_ldnt1s_add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldnt1s_add_X1_OBJECTS) $(insn_test_ldnt1s_add_X1_LDADD) $(LIBS)
+
+insn_test_ldnt1u_X1$(EXEEXT): $(insn_test_ldnt1u_X1_OBJECTS) $(insn_test_ldnt1u_X1_DEPENDENCIES) $(EXTRA_insn_test_ldnt1u_X1_DEPENDENCIES)
+ @rm -f insn_test_ldnt1u_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldnt1u_X1_OBJECTS) $(insn_test_ldnt1u_X1_LDADD) $(LIBS)
+
+insn_test_ldnt1u_add_X1$(EXEEXT): $(insn_test_ldnt1u_add_X1_OBJECTS) $(insn_test_ldnt1u_add_X1_DEPENDENCIES) $(EXTRA_insn_test_ldnt1u_add_X1_DEPENDENCIES)
+ @rm -f insn_test_ldnt1u_add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldnt1u_add_X1_OBJECTS) $(insn_test_ldnt1u_add_X1_LDADD) $(LIBS)
+
+insn_test_ldnt2s_X1$(EXEEXT): $(insn_test_ldnt2s_X1_OBJECTS) $(insn_test_ldnt2s_X1_DEPENDENCIES) $(EXTRA_insn_test_ldnt2s_X1_DEPENDENCIES)
+ @rm -f insn_test_ldnt2s_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldnt2s_X1_OBJECTS) $(insn_test_ldnt2s_X1_LDADD) $(LIBS)
+
+insn_test_ldnt2s_add_X1$(EXEEXT): $(insn_test_ldnt2s_add_X1_OBJECTS) $(insn_test_ldnt2s_add_X1_DEPENDENCIES) $(EXTRA_insn_test_ldnt2s_add_X1_DEPENDENCIES)
+ @rm -f insn_test_ldnt2s_add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldnt2s_add_X1_OBJECTS) $(insn_test_ldnt2s_add_X1_LDADD) $(LIBS)
+
+insn_test_ldnt2u_add_X1$(EXEEXT): $(insn_test_ldnt2u_add_X1_OBJECTS) $(insn_test_ldnt2u_add_X1_DEPENDENCIES) $(EXTRA_insn_test_ldnt2u_add_X1_DEPENDENCIES)
+ @rm -f insn_test_ldnt2u_add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldnt2u_add_X1_OBJECTS) $(insn_test_ldnt2u_add_X1_LDADD) $(LIBS)
+
+insn_test_ldnt4s_X1$(EXEEXT): $(insn_test_ldnt4s_X1_OBJECTS) $(insn_test_ldnt4s_X1_DEPENDENCIES) $(EXTRA_insn_test_ldnt4s_X1_DEPENDENCIES)
+ @rm -f insn_test_ldnt4s_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldnt4s_X1_OBJECTS) $(insn_test_ldnt4s_X1_LDADD) $(LIBS)
+
+insn_test_ldnt4s_add_X1$(EXEEXT): $(insn_test_ldnt4s_add_X1_OBJECTS) $(insn_test_ldnt4s_add_X1_DEPENDENCIES) $(EXTRA_insn_test_ldnt4s_add_X1_DEPENDENCIES)
+ @rm -f insn_test_ldnt4s_add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldnt4s_add_X1_OBJECTS) $(insn_test_ldnt4s_add_X1_LDADD) $(LIBS)
+
+insn_test_ldnt4u_X1$(EXEEXT): $(insn_test_ldnt4u_X1_OBJECTS) $(insn_test_ldnt4u_X1_DEPENDENCIES) $(EXTRA_insn_test_ldnt4u_X1_DEPENDENCIES)
+ @rm -f insn_test_ldnt4u_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldnt4u_X1_OBJECTS) $(insn_test_ldnt4u_X1_LDADD) $(LIBS)
+
+insn_test_ldnt4u_add_X1$(EXEEXT): $(insn_test_ldnt4u_add_X1_OBJECTS) $(insn_test_ldnt4u_add_X1_DEPENDENCIES) $(EXTRA_insn_test_ldnt4u_add_X1_DEPENDENCIES)
+ @rm -f insn_test_ldnt4u_add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldnt4u_add_X1_OBJECTS) $(insn_test_ldnt4u_add_X1_LDADD) $(LIBS)
+
+insn_test_ldnt_X1$(EXEEXT): $(insn_test_ldnt_X1_OBJECTS) $(insn_test_ldnt_X1_DEPENDENCIES) $(EXTRA_insn_test_ldnt_X1_DEPENDENCIES)
+ @rm -f insn_test_ldnt_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldnt_X1_OBJECTS) $(insn_test_ldnt_X1_LDADD) $(LIBS)
+
+insn_test_ldnt_add_X1$(EXEEXT): $(insn_test_ldnt_add_X1_OBJECTS) $(insn_test_ldnt_add_X1_DEPENDENCIES) $(EXTRA_insn_test_ldnt_add_X1_DEPENDENCIES)
+ @rm -f insn_test_ldnt_add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ldnt_add_X1_OBJECTS) $(insn_test_ldnt_add_X1_LDADD) $(LIBS)
+
+insn_test_lnk_X1$(EXEEXT): $(insn_test_lnk_X1_OBJECTS) $(insn_test_lnk_X1_DEPENDENCIES) $(EXTRA_insn_test_lnk_X1_DEPENDENCIES)
+ @rm -f insn_test_lnk_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_lnk_X1_OBJECTS) $(insn_test_lnk_X1_LDADD) $(LIBS)
+
+insn_test_lnk_Y1$(EXEEXT): $(insn_test_lnk_Y1_OBJECTS) $(insn_test_lnk_Y1_DEPENDENCIES) $(EXTRA_insn_test_lnk_Y1_DEPENDENCIES)
+ @rm -f insn_test_lnk_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_lnk_Y1_OBJECTS) $(insn_test_lnk_Y1_LDADD) $(LIBS)
+
+insn_test_mf_X1$(EXEEXT): $(insn_test_mf_X1_OBJECTS) $(insn_test_mf_X1_DEPENDENCIES) $(EXTRA_insn_test_mf_X1_DEPENDENCIES)
+ @rm -f insn_test_mf_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mf_X1_OBJECTS) $(insn_test_mf_X1_LDADD) $(LIBS)
+
+insn_test_mm_X0$(EXEEXT): $(insn_test_mm_X0_OBJECTS) $(insn_test_mm_X0_DEPENDENCIES) $(EXTRA_insn_test_mm_X0_DEPENDENCIES)
+ @rm -f insn_test_mm_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mm_X0_OBJECTS) $(insn_test_mm_X0_LDADD) $(LIBS)
+
+insn_test_mnz_X0$(EXEEXT): $(insn_test_mnz_X0_OBJECTS) $(insn_test_mnz_X0_DEPENDENCIES) $(EXTRA_insn_test_mnz_X0_DEPENDENCIES)
+ @rm -f insn_test_mnz_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mnz_X0_OBJECTS) $(insn_test_mnz_X0_LDADD) $(LIBS)
+
+insn_test_mnz_X1$(EXEEXT): $(insn_test_mnz_X1_OBJECTS) $(insn_test_mnz_X1_DEPENDENCIES) $(EXTRA_insn_test_mnz_X1_DEPENDENCIES)
+ @rm -f insn_test_mnz_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mnz_X1_OBJECTS) $(insn_test_mnz_X1_LDADD) $(LIBS)
+
+insn_test_mnz_Y0$(EXEEXT): $(insn_test_mnz_Y0_OBJECTS) $(insn_test_mnz_Y0_DEPENDENCIES) $(EXTRA_insn_test_mnz_Y0_DEPENDENCIES)
+ @rm -f insn_test_mnz_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mnz_Y0_OBJECTS) $(insn_test_mnz_Y0_LDADD) $(LIBS)
+
+insn_test_mnz_Y1$(EXEEXT): $(insn_test_mnz_Y1_OBJECTS) $(insn_test_mnz_Y1_DEPENDENCIES) $(EXTRA_insn_test_mnz_Y1_DEPENDENCIES)
+ @rm -f insn_test_mnz_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mnz_Y1_OBJECTS) $(insn_test_mnz_Y1_LDADD) $(LIBS)
+
+insn_test_move_X0$(EXEEXT): $(insn_test_move_X0_OBJECTS) $(insn_test_move_X0_DEPENDENCIES) $(EXTRA_insn_test_move_X0_DEPENDENCIES)
+ @rm -f insn_test_move_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_move_X0_OBJECTS) $(insn_test_move_X0_LDADD) $(LIBS)
+
+insn_test_move_X1$(EXEEXT): $(insn_test_move_X1_OBJECTS) $(insn_test_move_X1_DEPENDENCIES) $(EXTRA_insn_test_move_X1_DEPENDENCIES)
+ @rm -f insn_test_move_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_move_X1_OBJECTS) $(insn_test_move_X1_LDADD) $(LIBS)
+
+insn_test_move_Y0$(EXEEXT): $(insn_test_move_Y0_OBJECTS) $(insn_test_move_Y0_DEPENDENCIES) $(EXTRA_insn_test_move_Y0_DEPENDENCIES)
+ @rm -f insn_test_move_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_move_Y0_OBJECTS) $(insn_test_move_Y0_LDADD) $(LIBS)
+
+insn_test_move_Y1$(EXEEXT): $(insn_test_move_Y1_OBJECTS) $(insn_test_move_Y1_DEPENDENCIES) $(EXTRA_insn_test_move_Y1_DEPENDENCIES)
+ @rm -f insn_test_move_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_move_Y1_OBJECTS) $(insn_test_move_Y1_LDADD) $(LIBS)
+
+insn_test_movei_X0$(EXEEXT): $(insn_test_movei_X0_OBJECTS) $(insn_test_movei_X0_DEPENDENCIES) $(EXTRA_insn_test_movei_X0_DEPENDENCIES)
+ @rm -f insn_test_movei_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_movei_X0_OBJECTS) $(insn_test_movei_X0_LDADD) $(LIBS)
+
+insn_test_movei_X1$(EXEEXT): $(insn_test_movei_X1_OBJECTS) $(insn_test_movei_X1_DEPENDENCIES) $(EXTRA_insn_test_movei_X1_DEPENDENCIES)
+ @rm -f insn_test_movei_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_movei_X1_OBJECTS) $(insn_test_movei_X1_LDADD) $(LIBS)
+
+insn_test_movei_Y0$(EXEEXT): $(insn_test_movei_Y0_OBJECTS) $(insn_test_movei_Y0_DEPENDENCIES) $(EXTRA_insn_test_movei_Y0_DEPENDENCIES)
+ @rm -f insn_test_movei_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_movei_Y0_OBJECTS) $(insn_test_movei_Y0_LDADD) $(LIBS)
+
+insn_test_movei_Y1$(EXEEXT): $(insn_test_movei_Y1_OBJECTS) $(insn_test_movei_Y1_DEPENDENCIES) $(EXTRA_insn_test_movei_Y1_DEPENDENCIES)
+ @rm -f insn_test_movei_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_movei_Y1_OBJECTS) $(insn_test_movei_Y1_LDADD) $(LIBS)
+
+insn_test_moveli_X0$(EXEEXT): $(insn_test_moveli_X0_OBJECTS) $(insn_test_moveli_X0_DEPENDENCIES) $(EXTRA_insn_test_moveli_X0_DEPENDENCIES)
+ @rm -f insn_test_moveli_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_moveli_X0_OBJECTS) $(insn_test_moveli_X0_LDADD) $(LIBS)
+
+insn_test_moveli_X1$(EXEEXT): $(insn_test_moveli_X1_OBJECTS) $(insn_test_moveli_X1_DEPENDENCIES) $(EXTRA_insn_test_moveli_X1_DEPENDENCIES)
+ @rm -f insn_test_moveli_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_moveli_X1_OBJECTS) $(insn_test_moveli_X1_LDADD) $(LIBS)
+
+insn_test_mul_hs_hs_X0$(EXEEXT): $(insn_test_mul_hs_hs_X0_OBJECTS) $(insn_test_mul_hs_hs_X0_DEPENDENCIES) $(EXTRA_insn_test_mul_hs_hs_X0_DEPENDENCIES)
+ @rm -f insn_test_mul_hs_hs_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mul_hs_hs_X0_OBJECTS) $(insn_test_mul_hs_hs_X0_LDADD) $(LIBS)
+
+insn_test_mul_hs_hs_Y0$(EXEEXT): $(insn_test_mul_hs_hs_Y0_OBJECTS) $(insn_test_mul_hs_hs_Y0_DEPENDENCIES) $(EXTRA_insn_test_mul_hs_hs_Y0_DEPENDENCIES)
+ @rm -f insn_test_mul_hs_hs_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mul_hs_hs_Y0_OBJECTS) $(insn_test_mul_hs_hs_Y0_LDADD) $(LIBS)
+
+insn_test_mul_hs_hu_X0$(EXEEXT): $(insn_test_mul_hs_hu_X0_OBJECTS) $(insn_test_mul_hs_hu_X0_DEPENDENCIES) $(EXTRA_insn_test_mul_hs_hu_X0_DEPENDENCIES)
+ @rm -f insn_test_mul_hs_hu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mul_hs_hu_X0_OBJECTS) $(insn_test_mul_hs_hu_X0_LDADD) $(LIBS)
+
+insn_test_mul_hs_ls_X0$(EXEEXT): $(insn_test_mul_hs_ls_X0_OBJECTS) $(insn_test_mul_hs_ls_X0_DEPENDENCIES) $(EXTRA_insn_test_mul_hs_ls_X0_DEPENDENCIES)
+ @rm -f insn_test_mul_hs_ls_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mul_hs_ls_X0_OBJECTS) $(insn_test_mul_hs_ls_X0_LDADD) $(LIBS)
+
+insn_test_mul_hs_lu_X0$(EXEEXT): $(insn_test_mul_hs_lu_X0_OBJECTS) $(insn_test_mul_hs_lu_X0_DEPENDENCIES) $(EXTRA_insn_test_mul_hs_lu_X0_DEPENDENCIES)
+ @rm -f insn_test_mul_hs_lu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mul_hs_lu_X0_OBJECTS) $(insn_test_mul_hs_lu_X0_LDADD) $(LIBS)
+
+insn_test_mul_hu_hu_X0$(EXEEXT): $(insn_test_mul_hu_hu_X0_OBJECTS) $(insn_test_mul_hu_hu_X0_DEPENDENCIES) $(EXTRA_insn_test_mul_hu_hu_X0_DEPENDENCIES)
+ @rm -f insn_test_mul_hu_hu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mul_hu_hu_X0_OBJECTS) $(insn_test_mul_hu_hu_X0_LDADD) $(LIBS)
+
+insn_test_mul_hu_hu_Y0$(EXEEXT): $(insn_test_mul_hu_hu_Y0_OBJECTS) $(insn_test_mul_hu_hu_Y0_DEPENDENCIES) $(EXTRA_insn_test_mul_hu_hu_Y0_DEPENDENCIES)
+ @rm -f insn_test_mul_hu_hu_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mul_hu_hu_Y0_OBJECTS) $(insn_test_mul_hu_hu_Y0_LDADD) $(LIBS)
+
+insn_test_mul_hu_lu_X0$(EXEEXT): $(insn_test_mul_hu_lu_X0_OBJECTS) $(insn_test_mul_hu_lu_X0_DEPENDENCIES) $(EXTRA_insn_test_mul_hu_lu_X0_DEPENDENCIES)
+ @rm -f insn_test_mul_hu_lu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mul_hu_lu_X0_OBJECTS) $(insn_test_mul_hu_lu_X0_LDADD) $(LIBS)
+
+insn_test_mul_ls_ls_X0$(EXEEXT): $(insn_test_mul_ls_ls_X0_OBJECTS) $(insn_test_mul_ls_ls_X0_DEPENDENCIES) $(EXTRA_insn_test_mul_ls_ls_X0_DEPENDENCIES)
+ @rm -f insn_test_mul_ls_ls_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mul_ls_ls_X0_OBJECTS) $(insn_test_mul_ls_ls_X0_LDADD) $(LIBS)
+
+insn_test_mul_ls_ls_Y0$(EXEEXT): $(insn_test_mul_ls_ls_Y0_OBJECTS) $(insn_test_mul_ls_ls_Y0_DEPENDENCIES) $(EXTRA_insn_test_mul_ls_ls_Y0_DEPENDENCIES)
+ @rm -f insn_test_mul_ls_ls_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mul_ls_ls_Y0_OBJECTS) $(insn_test_mul_ls_ls_Y0_LDADD) $(LIBS)
+
+insn_test_mul_ls_lu_X0$(EXEEXT): $(insn_test_mul_ls_lu_X0_OBJECTS) $(insn_test_mul_ls_lu_X0_DEPENDENCIES) $(EXTRA_insn_test_mul_ls_lu_X0_DEPENDENCIES)
+ @rm -f insn_test_mul_ls_lu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mul_ls_lu_X0_OBJECTS) $(insn_test_mul_ls_lu_X0_LDADD) $(LIBS)
+
+insn_test_mul_lu_lu_X0$(EXEEXT): $(insn_test_mul_lu_lu_X0_OBJECTS) $(insn_test_mul_lu_lu_X0_DEPENDENCIES) $(EXTRA_insn_test_mul_lu_lu_X0_DEPENDENCIES)
+ @rm -f insn_test_mul_lu_lu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mul_lu_lu_X0_OBJECTS) $(insn_test_mul_lu_lu_X0_LDADD) $(LIBS)
+
+insn_test_mul_lu_lu_Y0$(EXEEXT): $(insn_test_mul_lu_lu_Y0_OBJECTS) $(insn_test_mul_lu_lu_Y0_DEPENDENCIES) $(EXTRA_insn_test_mul_lu_lu_Y0_DEPENDENCIES)
+ @rm -f insn_test_mul_lu_lu_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mul_lu_lu_Y0_OBJECTS) $(insn_test_mul_lu_lu_Y0_LDADD) $(LIBS)
+
+insn_test_mula_hs_hs_X0$(EXEEXT): $(insn_test_mula_hs_hs_X0_OBJECTS) $(insn_test_mula_hs_hs_X0_DEPENDENCIES) $(EXTRA_insn_test_mula_hs_hs_X0_DEPENDENCIES)
+ @rm -f insn_test_mula_hs_hs_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mula_hs_hs_X0_OBJECTS) $(insn_test_mula_hs_hs_X0_LDADD) $(LIBS)
+
+insn_test_mula_hs_hs_Y0$(EXEEXT): $(insn_test_mula_hs_hs_Y0_OBJECTS) $(insn_test_mula_hs_hs_Y0_DEPENDENCIES) $(EXTRA_insn_test_mula_hs_hs_Y0_DEPENDENCIES)
+ @rm -f insn_test_mula_hs_hs_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mula_hs_hs_Y0_OBJECTS) $(insn_test_mula_hs_hs_Y0_LDADD) $(LIBS)
+
+insn_test_mula_hs_hu_X0$(EXEEXT): $(insn_test_mula_hs_hu_X0_OBJECTS) $(insn_test_mula_hs_hu_X0_DEPENDENCIES) $(EXTRA_insn_test_mula_hs_hu_X0_DEPENDENCIES)
+ @rm -f insn_test_mula_hs_hu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mula_hs_hu_X0_OBJECTS) $(insn_test_mula_hs_hu_X0_LDADD) $(LIBS)
+
+insn_test_mula_hs_ls_X0$(EXEEXT): $(insn_test_mula_hs_ls_X0_OBJECTS) $(insn_test_mula_hs_ls_X0_DEPENDENCIES) $(EXTRA_insn_test_mula_hs_ls_X0_DEPENDENCIES)
+ @rm -f insn_test_mula_hs_ls_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mula_hs_ls_X0_OBJECTS) $(insn_test_mula_hs_ls_X0_LDADD) $(LIBS)
+
+insn_test_mula_hs_lu_X0$(EXEEXT): $(insn_test_mula_hs_lu_X0_OBJECTS) $(insn_test_mula_hs_lu_X0_DEPENDENCIES) $(EXTRA_insn_test_mula_hs_lu_X0_DEPENDENCIES)
+ @rm -f insn_test_mula_hs_lu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mula_hs_lu_X0_OBJECTS) $(insn_test_mula_hs_lu_X0_LDADD) $(LIBS)
+
+insn_test_mula_hu_hu_X0$(EXEEXT): $(insn_test_mula_hu_hu_X0_OBJECTS) $(insn_test_mula_hu_hu_X0_DEPENDENCIES) $(EXTRA_insn_test_mula_hu_hu_X0_DEPENDENCIES)
+ @rm -f insn_test_mula_hu_hu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mula_hu_hu_X0_OBJECTS) $(insn_test_mula_hu_hu_X0_LDADD) $(LIBS)
+
+insn_test_mula_hu_hu_Y0$(EXEEXT): $(insn_test_mula_hu_hu_Y0_OBJECTS) $(insn_test_mula_hu_hu_Y0_DEPENDENCIES) $(EXTRA_insn_test_mula_hu_hu_Y0_DEPENDENCIES)
+ @rm -f insn_test_mula_hu_hu_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mula_hu_hu_Y0_OBJECTS) $(insn_test_mula_hu_hu_Y0_LDADD) $(LIBS)
+
+insn_test_mula_hu_ls_X0$(EXEEXT): $(insn_test_mula_hu_ls_X0_OBJECTS) $(insn_test_mula_hu_ls_X0_DEPENDENCIES) $(EXTRA_insn_test_mula_hu_ls_X0_DEPENDENCIES)
+ @rm -f insn_test_mula_hu_ls_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mula_hu_ls_X0_OBJECTS) $(insn_test_mula_hu_ls_X0_LDADD) $(LIBS)
+
+insn_test_mula_hu_lu_X0$(EXEEXT): $(insn_test_mula_hu_lu_X0_OBJECTS) $(insn_test_mula_hu_lu_X0_DEPENDENCIES) $(EXTRA_insn_test_mula_hu_lu_X0_DEPENDENCIES)
+ @rm -f insn_test_mula_hu_lu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mula_hu_lu_X0_OBJECTS) $(insn_test_mula_hu_lu_X0_LDADD) $(LIBS)
+
+insn_test_mula_ls_ls_X0$(EXEEXT): $(insn_test_mula_ls_ls_X0_OBJECTS) $(insn_test_mula_ls_ls_X0_DEPENDENCIES) $(EXTRA_insn_test_mula_ls_ls_X0_DEPENDENCIES)
+ @rm -f insn_test_mula_ls_ls_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mula_ls_ls_X0_OBJECTS) $(insn_test_mula_ls_ls_X0_LDADD) $(LIBS)
+
+insn_test_mula_ls_ls_Y0$(EXEEXT): $(insn_test_mula_ls_ls_Y0_OBJECTS) $(insn_test_mula_ls_ls_Y0_DEPENDENCIES) $(EXTRA_insn_test_mula_ls_ls_Y0_DEPENDENCIES)
+ @rm -f insn_test_mula_ls_ls_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mula_ls_ls_Y0_OBJECTS) $(insn_test_mula_ls_ls_Y0_LDADD) $(LIBS)
+
+insn_test_mula_ls_lu_X0$(EXEEXT): $(insn_test_mula_ls_lu_X0_OBJECTS) $(insn_test_mula_ls_lu_X0_DEPENDENCIES) $(EXTRA_insn_test_mula_ls_lu_X0_DEPENDENCIES)
+ @rm -f insn_test_mula_ls_lu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mula_ls_lu_X0_OBJECTS) $(insn_test_mula_ls_lu_X0_LDADD) $(LIBS)
+
+insn_test_mula_lu_lu_X0$(EXEEXT): $(insn_test_mula_lu_lu_X0_OBJECTS) $(insn_test_mula_lu_lu_X0_DEPENDENCIES) $(EXTRA_insn_test_mula_lu_lu_X0_DEPENDENCIES)
+ @rm -f insn_test_mula_lu_lu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mula_lu_lu_X0_OBJECTS) $(insn_test_mula_lu_lu_X0_LDADD) $(LIBS)
+
+insn_test_mula_lu_lu_Y0$(EXEEXT): $(insn_test_mula_lu_lu_Y0_OBJECTS) $(insn_test_mula_lu_lu_Y0_DEPENDENCIES) $(EXTRA_insn_test_mula_lu_lu_Y0_DEPENDENCIES)
+ @rm -f insn_test_mula_lu_lu_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mula_lu_lu_Y0_OBJECTS) $(insn_test_mula_lu_lu_Y0_LDADD) $(LIBS)
+
+insn_test_mulax_X0$(EXEEXT): $(insn_test_mulax_X0_OBJECTS) $(insn_test_mulax_X0_DEPENDENCIES) $(EXTRA_insn_test_mulax_X0_DEPENDENCIES)
+ @rm -f insn_test_mulax_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mulax_X0_OBJECTS) $(insn_test_mulax_X0_LDADD) $(LIBS)
+
+insn_test_mulax_Y0$(EXEEXT): $(insn_test_mulax_Y0_OBJECTS) $(insn_test_mulax_Y0_DEPENDENCIES) $(EXTRA_insn_test_mulax_Y0_DEPENDENCIES)
+ @rm -f insn_test_mulax_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mulax_Y0_OBJECTS) $(insn_test_mulax_Y0_LDADD) $(LIBS)
+
+insn_test_mulx_X0$(EXEEXT): $(insn_test_mulx_X0_OBJECTS) $(insn_test_mulx_X0_DEPENDENCIES) $(EXTRA_insn_test_mulx_X0_DEPENDENCIES)
+ @rm -f insn_test_mulx_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mulx_X0_OBJECTS) $(insn_test_mulx_X0_LDADD) $(LIBS)
+
+insn_test_mulx_Y0$(EXEEXT): $(insn_test_mulx_Y0_OBJECTS) $(insn_test_mulx_Y0_DEPENDENCIES) $(EXTRA_insn_test_mulx_Y0_DEPENDENCIES)
+ @rm -f insn_test_mulx_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mulx_Y0_OBJECTS) $(insn_test_mulx_Y0_LDADD) $(LIBS)
+
+insn_test_mz_X0$(EXEEXT): $(insn_test_mz_X0_OBJECTS) $(insn_test_mz_X0_DEPENDENCIES) $(EXTRA_insn_test_mz_X0_DEPENDENCIES)
+ @rm -f insn_test_mz_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mz_X0_OBJECTS) $(insn_test_mz_X0_LDADD) $(LIBS)
+
+insn_test_mz_X1$(EXEEXT): $(insn_test_mz_X1_OBJECTS) $(insn_test_mz_X1_DEPENDENCIES) $(EXTRA_insn_test_mz_X1_DEPENDENCIES)
+ @rm -f insn_test_mz_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mz_X1_OBJECTS) $(insn_test_mz_X1_LDADD) $(LIBS)
+
+insn_test_mz_Y0$(EXEEXT): $(insn_test_mz_Y0_OBJECTS) $(insn_test_mz_Y0_DEPENDENCIES) $(EXTRA_insn_test_mz_Y0_DEPENDENCIES)
+ @rm -f insn_test_mz_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mz_Y0_OBJECTS) $(insn_test_mz_Y0_LDADD) $(LIBS)
+
+insn_test_mz_Y1$(EXEEXT): $(insn_test_mz_Y1_OBJECTS) $(insn_test_mz_Y1_DEPENDENCIES) $(EXTRA_insn_test_mz_Y1_DEPENDENCIES)
+ @rm -f insn_test_mz_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_mz_Y1_OBJECTS) $(insn_test_mz_Y1_LDADD) $(LIBS)
+
+insn_test_nop_X0$(EXEEXT): $(insn_test_nop_X0_OBJECTS) $(insn_test_nop_X0_DEPENDENCIES) $(EXTRA_insn_test_nop_X0_DEPENDENCIES)
+ @rm -f insn_test_nop_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_nop_X0_OBJECTS) $(insn_test_nop_X0_LDADD) $(LIBS)
+
+insn_test_nop_X1$(EXEEXT): $(insn_test_nop_X1_OBJECTS) $(insn_test_nop_X1_DEPENDENCIES) $(EXTRA_insn_test_nop_X1_DEPENDENCIES)
+ @rm -f insn_test_nop_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_nop_X1_OBJECTS) $(insn_test_nop_X1_LDADD) $(LIBS)
+
+insn_test_nop_Y0$(EXEEXT): $(insn_test_nop_Y0_OBJECTS) $(insn_test_nop_Y0_DEPENDENCIES) $(EXTRA_insn_test_nop_Y0_DEPENDENCIES)
+ @rm -f insn_test_nop_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_nop_Y0_OBJECTS) $(insn_test_nop_Y0_LDADD) $(LIBS)
+
+insn_test_nop_Y1$(EXEEXT): $(insn_test_nop_Y1_OBJECTS) $(insn_test_nop_Y1_DEPENDENCIES) $(EXTRA_insn_test_nop_Y1_DEPENDENCIES)
+ @rm -f insn_test_nop_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_nop_Y1_OBJECTS) $(insn_test_nop_Y1_LDADD) $(LIBS)
+
+insn_test_nor_X0$(EXEEXT): $(insn_test_nor_X0_OBJECTS) $(insn_test_nor_X0_DEPENDENCIES) $(EXTRA_insn_test_nor_X0_DEPENDENCIES)
+ @rm -f insn_test_nor_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_nor_X0_OBJECTS) $(insn_test_nor_X0_LDADD) $(LIBS)
+
+insn_test_nor_X1$(EXEEXT): $(insn_test_nor_X1_OBJECTS) $(insn_test_nor_X1_DEPENDENCIES) $(EXTRA_insn_test_nor_X1_DEPENDENCIES)
+ @rm -f insn_test_nor_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_nor_X1_OBJECTS) $(insn_test_nor_X1_LDADD) $(LIBS)
+
+insn_test_nor_Y0$(EXEEXT): $(insn_test_nor_Y0_OBJECTS) $(insn_test_nor_Y0_DEPENDENCIES) $(EXTRA_insn_test_nor_Y0_DEPENDENCIES)
+ @rm -f insn_test_nor_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_nor_Y0_OBJECTS) $(insn_test_nor_Y0_LDADD) $(LIBS)
+
+insn_test_nor_Y1$(EXEEXT): $(insn_test_nor_Y1_OBJECTS) $(insn_test_nor_Y1_DEPENDENCIES) $(EXTRA_insn_test_nor_Y1_DEPENDENCIES)
+ @rm -f insn_test_nor_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_nor_Y1_OBJECTS) $(insn_test_nor_Y1_LDADD) $(LIBS)
+
+insn_test_or_X0$(EXEEXT): $(insn_test_or_X0_OBJECTS) $(insn_test_or_X0_DEPENDENCIES) $(EXTRA_insn_test_or_X0_DEPENDENCIES)
+ @rm -f insn_test_or_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_or_X0_OBJECTS) $(insn_test_or_X0_LDADD) $(LIBS)
+
+insn_test_or_X1$(EXEEXT): $(insn_test_or_X1_OBJECTS) $(insn_test_or_X1_DEPENDENCIES) $(EXTRA_insn_test_or_X1_DEPENDENCIES)
+ @rm -f insn_test_or_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_or_X1_OBJECTS) $(insn_test_or_X1_LDADD) $(LIBS)
+
+insn_test_or_Y0$(EXEEXT): $(insn_test_or_Y0_OBJECTS) $(insn_test_or_Y0_DEPENDENCIES) $(EXTRA_insn_test_or_Y0_DEPENDENCIES)
+ @rm -f insn_test_or_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_or_Y0_OBJECTS) $(insn_test_or_Y0_LDADD) $(LIBS)
+
+insn_test_or_Y1$(EXEEXT): $(insn_test_or_Y1_OBJECTS) $(insn_test_or_Y1_DEPENDENCIES) $(EXTRA_insn_test_or_Y1_DEPENDENCIES)
+ @rm -f insn_test_or_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_or_Y1_OBJECTS) $(insn_test_or_Y1_LDADD) $(LIBS)
+
+insn_test_ori_X0$(EXEEXT): $(insn_test_ori_X0_OBJECTS) $(insn_test_ori_X0_DEPENDENCIES) $(EXTRA_insn_test_ori_X0_DEPENDENCIES)
+ @rm -f insn_test_ori_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ori_X0_OBJECTS) $(insn_test_ori_X0_LDADD) $(LIBS)
+
+insn_test_ori_X1$(EXEEXT): $(insn_test_ori_X1_OBJECTS) $(insn_test_ori_X1_DEPENDENCIES) $(EXTRA_insn_test_ori_X1_DEPENDENCIES)
+ @rm -f insn_test_ori_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_ori_X1_OBJECTS) $(insn_test_ori_X1_LDADD) $(LIBS)
+
+insn_test_pcnt_X0$(EXEEXT): $(insn_test_pcnt_X0_OBJECTS) $(insn_test_pcnt_X0_DEPENDENCIES) $(EXTRA_insn_test_pcnt_X0_DEPENDENCIES)
+ @rm -f insn_test_pcnt_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_pcnt_X0_OBJECTS) $(insn_test_pcnt_X0_LDADD) $(LIBS)
+
+insn_test_pcnt_Y0$(EXEEXT): $(insn_test_pcnt_Y0_OBJECTS) $(insn_test_pcnt_Y0_DEPENDENCIES) $(EXTRA_insn_test_pcnt_Y0_DEPENDENCIES)
+ @rm -f insn_test_pcnt_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_pcnt_Y0_OBJECTS) $(insn_test_pcnt_Y0_LDADD) $(LIBS)
+
+insn_test_prefetch_X1$(EXEEXT): $(insn_test_prefetch_X1_OBJECTS) $(insn_test_prefetch_X1_DEPENDENCIES) $(EXTRA_insn_test_prefetch_X1_DEPENDENCIES)
+ @rm -f insn_test_prefetch_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_prefetch_X1_OBJECTS) $(insn_test_prefetch_X1_LDADD) $(LIBS)
+
+insn_test_prefetch_Y2$(EXEEXT): $(insn_test_prefetch_Y2_OBJECTS) $(insn_test_prefetch_Y2_DEPENDENCIES) $(EXTRA_insn_test_prefetch_Y2_DEPENDENCIES)
+ @rm -f insn_test_prefetch_Y2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_prefetch_Y2_OBJECTS) $(insn_test_prefetch_Y2_LDADD) $(LIBS)
+
+insn_test_prefetch_l1_X1$(EXEEXT): $(insn_test_prefetch_l1_X1_OBJECTS) $(insn_test_prefetch_l1_X1_DEPENDENCIES) $(EXTRA_insn_test_prefetch_l1_X1_DEPENDENCIES)
+ @rm -f insn_test_prefetch_l1_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_prefetch_l1_X1_OBJECTS) $(insn_test_prefetch_l1_X1_LDADD) $(LIBS)
+
+insn_test_prefetch_l1_Y2$(EXEEXT): $(insn_test_prefetch_l1_Y2_OBJECTS) $(insn_test_prefetch_l1_Y2_DEPENDENCIES) $(EXTRA_insn_test_prefetch_l1_Y2_DEPENDENCIES)
+ @rm -f insn_test_prefetch_l1_Y2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_prefetch_l1_Y2_OBJECTS) $(insn_test_prefetch_l1_Y2_LDADD) $(LIBS)
+
+insn_test_prefetch_l2_X1$(EXEEXT): $(insn_test_prefetch_l2_X1_OBJECTS) $(insn_test_prefetch_l2_X1_DEPENDENCIES) $(EXTRA_insn_test_prefetch_l2_X1_DEPENDENCIES)
+ @rm -f insn_test_prefetch_l2_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_prefetch_l2_X1_OBJECTS) $(insn_test_prefetch_l2_X1_LDADD) $(LIBS)
+
+insn_test_prefetch_l2_Y2$(EXEEXT): $(insn_test_prefetch_l2_Y2_OBJECTS) $(insn_test_prefetch_l2_Y2_DEPENDENCIES) $(EXTRA_insn_test_prefetch_l2_Y2_DEPENDENCIES)
+ @rm -f insn_test_prefetch_l2_Y2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_prefetch_l2_Y2_OBJECTS) $(insn_test_prefetch_l2_Y2_LDADD) $(LIBS)
+
+insn_test_prefetch_l3_X1$(EXEEXT): $(insn_test_prefetch_l3_X1_OBJECTS) $(insn_test_prefetch_l3_X1_DEPENDENCIES) $(EXTRA_insn_test_prefetch_l3_X1_DEPENDENCIES)
+ @rm -f insn_test_prefetch_l3_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_prefetch_l3_X1_OBJECTS) $(insn_test_prefetch_l3_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_prefetch_l3_Y2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_prefetch_l3_Y2_OBJECTS) $(insn_test_prefetch_l3_Y2_LDADD) $(LIBS)
+
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+ @rm -f insn_test_revbits_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_revbits_X0_OBJECTS) $(insn_test_revbits_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_revbits_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_revbits_Y0_OBJECTS) $(insn_test_revbits_Y0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_revbytes_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_revbytes_X0_OBJECTS) $(insn_test_revbytes_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_revbytes_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_revbytes_Y0_OBJECTS) $(insn_test_revbytes_Y0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_rotl_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_rotl_X0_OBJECTS) $(insn_test_rotl_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_rotl_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_rotl_X1_OBJECTS) $(insn_test_rotl_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_rotl_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_rotl_Y0_OBJECTS) $(insn_test_rotl_Y0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_rotl_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_rotl_Y1_OBJECTS) $(insn_test_rotl_Y1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_rotli_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_rotli_X0_OBJECTS) $(insn_test_rotli_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_rotli_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_rotli_X1_OBJECTS) $(insn_test_rotli_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_rotli_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_rotli_Y0_OBJECTS) $(insn_test_rotli_Y0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_rotli_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_rotli_Y1_OBJECTS) $(insn_test_rotli_Y1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl16insli_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl16insli_X0_OBJECTS) $(insn_test_shl16insli_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl16insli_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl16insli_X1_OBJECTS) $(insn_test_shl16insli_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl1add_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl1add_X0_OBJECTS) $(insn_test_shl1add_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl1add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl1add_X1_OBJECTS) $(insn_test_shl1add_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl1add_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl1add_Y0_OBJECTS) $(insn_test_shl1add_Y0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl1add_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl1add_Y1_OBJECTS) $(insn_test_shl1add_Y1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl1addx_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl1addx_X0_OBJECTS) $(insn_test_shl1addx_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl1addx_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl1addx_X1_OBJECTS) $(insn_test_shl1addx_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl1addx_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl1addx_Y0_OBJECTS) $(insn_test_shl1addx_Y0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl1addx_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl1addx_Y1_OBJECTS) $(insn_test_shl1addx_Y1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl2add_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl2add_X0_OBJECTS) $(insn_test_shl2add_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl2add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl2add_X1_OBJECTS) $(insn_test_shl2add_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl2add_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl2add_Y0_OBJECTS) $(insn_test_shl2add_Y0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl2add_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl2add_Y1_OBJECTS) $(insn_test_shl2add_Y1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl2addx_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl2addx_X0_OBJECTS) $(insn_test_shl2addx_X0_LDADD) $(LIBS)
+
+insn_test_shl2addx_X1$(EXEEXT): $(insn_test_shl2addx_X1_OBJECTS) $(insn_test_shl2addx_X1_DEPENDENCIES) $(EXTRA_insn_test_shl2addx_X1_DEPENDENCIES)
+ @rm -f insn_test_shl2addx_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl2addx_X1_OBJECTS) $(insn_test_shl2addx_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl2addx_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl2addx_Y0_OBJECTS) $(insn_test_shl2addx_Y0_LDADD) $(LIBS)
+
+insn_test_shl2addx_Y1$(EXEEXT): $(insn_test_shl2addx_Y1_OBJECTS) $(insn_test_shl2addx_Y1_DEPENDENCIES) $(EXTRA_insn_test_shl2addx_Y1_DEPENDENCIES)
+ @rm -f insn_test_shl2addx_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl2addx_Y1_OBJECTS) $(insn_test_shl2addx_Y1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl3add_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl3add_X0_OBJECTS) $(insn_test_shl3add_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl3add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl3add_X1_OBJECTS) $(insn_test_shl3add_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl3add_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl3add_Y0_OBJECTS) $(insn_test_shl3add_Y0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl3add_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl3add_Y1_OBJECTS) $(insn_test_shl3add_Y1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl3addx_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl3addx_X0_OBJECTS) $(insn_test_shl3addx_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl3addx_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl3addx_X1_OBJECTS) $(insn_test_shl3addx_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl3addx_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl3addx_Y0_OBJECTS) $(insn_test_shl3addx_Y0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl3addx_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl3addx_Y1_OBJECTS) $(insn_test_shl3addx_Y1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl_X0_OBJECTS) $(insn_test_shl_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl_X1_OBJECTS) $(insn_test_shl_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl_Y0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl_Y0_OBJECTS) $(insn_test_shl_Y0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shl_Y1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shl_Y1_OBJECTS) $(insn_test_shl_Y1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shli_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_shli_X0_OBJECTS) $(insn_test_shli_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_shli_X1$(EXEEXT)
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+
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+ @rm -f insn_test_shli_Y0$(EXEEXT)
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+
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+ @rm -f insn_test_shli_Y1$(EXEEXT)
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+ @rm -f insn_test_shlx_X1$(EXEEXT)
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+ @rm -f insn_test_shrs_X0$(EXEEXT)
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+ @rm -f insn_test_v1add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1add_X1_OBJECTS) $(insn_test_v1add_X1_LDADD) $(LIBS)
+
+insn_test_v1adduc_X0$(EXEEXT): $(insn_test_v1adduc_X0_OBJECTS) $(insn_test_v1adduc_X0_DEPENDENCIES) $(EXTRA_insn_test_v1adduc_X0_DEPENDENCIES)
+ @rm -f insn_test_v1adduc_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1adduc_X0_OBJECTS) $(insn_test_v1adduc_X0_LDADD) $(LIBS)
+
+insn_test_v1adduc_X1$(EXEEXT): $(insn_test_v1adduc_X1_OBJECTS) $(insn_test_v1adduc_X1_DEPENDENCIES) $(EXTRA_insn_test_v1adduc_X1_DEPENDENCIES)
+ @rm -f insn_test_v1adduc_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1adduc_X1_OBJECTS) $(insn_test_v1adduc_X1_LDADD) $(LIBS)
+
+insn_test_v1adiffu_X0$(EXEEXT): $(insn_test_v1adiffu_X0_OBJECTS) $(insn_test_v1adiffu_X0_DEPENDENCIES) $(EXTRA_insn_test_v1adiffu_X0_DEPENDENCIES)
+ @rm -f insn_test_v1adiffu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1adiffu_X0_OBJECTS) $(insn_test_v1adiffu_X0_LDADD) $(LIBS)
+
+insn_test_v1avgu_X0$(EXEEXT): $(insn_test_v1avgu_X0_OBJECTS) $(insn_test_v1avgu_X0_DEPENDENCIES) $(EXTRA_insn_test_v1avgu_X0_DEPENDENCIES)
+ @rm -f insn_test_v1avgu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1avgu_X0_OBJECTS) $(insn_test_v1avgu_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1cmpeq_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1cmpeq_X0_OBJECTS) $(insn_test_v1cmpeq_X0_LDADD) $(LIBS)
+
+insn_test_v1cmpeq_X1$(EXEEXT): $(insn_test_v1cmpeq_X1_OBJECTS) $(insn_test_v1cmpeq_X1_DEPENDENCIES) $(EXTRA_insn_test_v1cmpeq_X1_DEPENDENCIES)
+ @rm -f insn_test_v1cmpeq_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1cmpeq_X1_OBJECTS) $(insn_test_v1cmpeq_X1_LDADD) $(LIBS)
+
+insn_test_v1cmpeqi_X0$(EXEEXT): $(insn_test_v1cmpeqi_X0_OBJECTS) $(insn_test_v1cmpeqi_X0_DEPENDENCIES) $(EXTRA_insn_test_v1cmpeqi_X0_DEPENDENCIES)
+ @rm -f insn_test_v1cmpeqi_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1cmpeqi_X0_OBJECTS) $(insn_test_v1cmpeqi_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1cmpeqi_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1cmpeqi_X1_OBJECTS) $(insn_test_v1cmpeqi_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1cmples_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1cmples_X0_OBJECTS) $(insn_test_v1cmples_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1cmples_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1cmples_X1_OBJECTS) $(insn_test_v1cmples_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1cmpleu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1cmpleu_X0_OBJECTS) $(insn_test_v1cmpleu_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1cmpleu_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1cmpleu_X1_OBJECTS) $(insn_test_v1cmpleu_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1cmplts_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1cmplts_X0_OBJECTS) $(insn_test_v1cmplts_X0_LDADD) $(LIBS)
+
+insn_test_v1cmplts_X1$(EXEEXT): $(insn_test_v1cmplts_X1_OBJECTS) $(insn_test_v1cmplts_X1_DEPENDENCIES) $(EXTRA_insn_test_v1cmplts_X1_DEPENDENCIES)
+ @rm -f insn_test_v1cmplts_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1cmplts_X1_OBJECTS) $(insn_test_v1cmplts_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1cmpltu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1cmpltu_X0_OBJECTS) $(insn_test_v1cmpltu_X0_LDADD) $(LIBS)
+
+insn_test_v1cmpltu_X1$(EXEEXT): $(insn_test_v1cmpltu_X1_OBJECTS) $(insn_test_v1cmpltu_X1_DEPENDENCIES) $(EXTRA_insn_test_v1cmpltu_X1_DEPENDENCIES)
+ @rm -f insn_test_v1cmpltu_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1cmpltu_X1_OBJECTS) $(insn_test_v1cmpltu_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1cmpne_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1cmpne_X0_OBJECTS) $(insn_test_v1cmpne_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1cmpne_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1cmpne_X1_OBJECTS) $(insn_test_v1cmpne_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1ddotpu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1ddotpu_X0_OBJECTS) $(insn_test_v1ddotpu_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1ddotpua_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1ddotpua_X0_OBJECTS) $(insn_test_v1ddotpua_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1ddotpus_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1ddotpus_X0_OBJECTS) $(insn_test_v1ddotpus_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1ddotpusa_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1ddotpusa_X0_OBJECTS) $(insn_test_v1ddotpusa_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1dotp_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1dotp_X0_OBJECTS) $(insn_test_v1dotp_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1dotpa_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1dotpa_X0_OBJECTS) $(insn_test_v1dotpa_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1dotpu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1dotpu_X0_OBJECTS) $(insn_test_v1dotpu_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1dotpua_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1dotpua_X0_OBJECTS) $(insn_test_v1dotpua_X0_LDADD) $(LIBS)
+
+insn_test_v1dotpus_X0$(EXEEXT): $(insn_test_v1dotpus_X0_OBJECTS) $(insn_test_v1dotpus_X0_DEPENDENCIES) $(EXTRA_insn_test_v1dotpus_X0_DEPENDENCIES)
+ @rm -f insn_test_v1dotpus_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1dotpus_X0_OBJECTS) $(insn_test_v1dotpus_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1dotpusa_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1dotpusa_X0_OBJECTS) $(insn_test_v1dotpusa_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1int_h_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1int_h_X0_OBJECTS) $(insn_test_v1int_h_X0_LDADD) $(LIBS)
+
+insn_test_v1int_h_X1$(EXEEXT): $(insn_test_v1int_h_X1_OBJECTS) $(insn_test_v1int_h_X1_DEPENDENCIES) $(EXTRA_insn_test_v1int_h_X1_DEPENDENCIES)
+ @rm -f insn_test_v1int_h_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1int_h_X1_OBJECTS) $(insn_test_v1int_h_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1int_l_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1int_l_X0_OBJECTS) $(insn_test_v1int_l_X0_LDADD) $(LIBS)
+
+insn_test_v1int_l_X1$(EXEEXT): $(insn_test_v1int_l_X1_OBJECTS) $(insn_test_v1int_l_X1_DEPENDENCIES) $(EXTRA_insn_test_v1int_l_X1_DEPENDENCIES)
+ @rm -f insn_test_v1int_l_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1int_l_X1_OBJECTS) $(insn_test_v1int_l_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1maxu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1maxu_X0_OBJECTS) $(insn_test_v1maxu_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1maxu_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1maxu_X1_OBJECTS) $(insn_test_v1maxu_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1minu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1minu_X0_OBJECTS) $(insn_test_v1minu_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1minu_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1minu_X1_OBJECTS) $(insn_test_v1minu_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1mnz_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1mnz_X0_OBJECTS) $(insn_test_v1mnz_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1mnz_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1mnz_X1_OBJECTS) $(insn_test_v1mnz_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1multu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1multu_X0_OBJECTS) $(insn_test_v1multu_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1mulu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1mulu_X0_OBJECTS) $(insn_test_v1mulu_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1mulus_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1mulus_X0_OBJECTS) $(insn_test_v1mulus_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1mz_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1mz_X0_OBJECTS) $(insn_test_v1mz_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1mz_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1mz_X1_OBJECTS) $(insn_test_v1mz_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1sadau_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1sadau_X0_OBJECTS) $(insn_test_v1sadau_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1sadu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1sadu_X0_OBJECTS) $(insn_test_v1sadu_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1shl_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1shl_X0_OBJECTS) $(insn_test_v1shl_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1shl_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1shl_X1_OBJECTS) $(insn_test_v1shl_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1shli_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1shli_X0_OBJECTS) $(insn_test_v1shli_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1shli_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1shli_X1_OBJECTS) $(insn_test_v1shli_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1shrs_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1shrs_X0_OBJECTS) $(insn_test_v1shrs_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1shrs_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1shrs_X1_OBJECTS) $(insn_test_v1shrs_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1shrsi_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1shrsi_X0_OBJECTS) $(insn_test_v1shrsi_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1shrsi_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1shrsi_X1_OBJECTS) $(insn_test_v1shrsi_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1shru_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1shru_X0_OBJECTS) $(insn_test_v1shru_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1shru_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1shru_X1_OBJECTS) $(insn_test_v1shru_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1shrui_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1shrui_X0_OBJECTS) $(insn_test_v1shrui_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1shrui_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1shrui_X1_OBJECTS) $(insn_test_v1shrui_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1sub_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1sub_X0_OBJECTS) $(insn_test_v1sub_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1sub_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1sub_X1_OBJECTS) $(insn_test_v1sub_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1subuc_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1subuc_X0_OBJECTS) $(insn_test_v1subuc_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v1subuc_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v1subuc_X1_OBJECTS) $(insn_test_v1subuc_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2add_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2add_X0_OBJECTS) $(insn_test_v2add_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2add_X1_OBJECTS) $(insn_test_v2add_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2addsc_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2addsc_X0_OBJECTS) $(insn_test_v2addsc_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2addsc_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2addsc_X1_OBJECTS) $(insn_test_v2addsc_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2adiffs_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2adiffs_X0_OBJECTS) $(insn_test_v2adiffs_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2avgs_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2avgs_X0_OBJECTS) $(insn_test_v2avgs_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmpeq_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmpeq_X0_OBJECTS) $(insn_test_v2cmpeq_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmpeq_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmpeq_X1_OBJECTS) $(insn_test_v2cmpeq_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmpeqi_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmpeqi_X0_OBJECTS) $(insn_test_v2cmpeqi_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmpeqi_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmpeqi_X1_OBJECTS) $(insn_test_v2cmpeqi_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmples_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmples_X0_OBJECTS) $(insn_test_v2cmples_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmples_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmples_X1_OBJECTS) $(insn_test_v2cmples_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmpleu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmpleu_X0_OBJECTS) $(insn_test_v2cmpleu_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmpleu_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmpleu_X1_OBJECTS) $(insn_test_v2cmpleu_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmplts_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmplts_X0_OBJECTS) $(insn_test_v2cmplts_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmplts_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmplts_X1_OBJECTS) $(insn_test_v2cmplts_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmpltsi_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmpltsi_X0_OBJECTS) $(insn_test_v2cmpltsi_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmpltsi_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmpltsi_X1_OBJECTS) $(insn_test_v2cmpltsi_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmpltu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmpltu_X0_OBJECTS) $(insn_test_v2cmpltu_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmpltu_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmpltu_X1_OBJECTS) $(insn_test_v2cmpltu_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmpltui_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmpltui_X0_OBJECTS) $(insn_test_v2cmpltui_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmpltui_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmpltui_X1_OBJECTS) $(insn_test_v2cmpltui_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmpne_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmpne_X0_OBJECTS) $(insn_test_v2cmpne_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2cmpne_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2cmpne_X1_OBJECTS) $(insn_test_v2cmpne_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2dotp_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2dotp_X0_OBJECTS) $(insn_test_v2dotp_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2dotpa_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2dotpa_X0_OBJECTS) $(insn_test_v2dotpa_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2int_h_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2int_h_X0_OBJECTS) $(insn_test_v2int_h_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2int_h_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2int_h_X1_OBJECTS) $(insn_test_v2int_h_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2int_l_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2int_l_X0_OBJECTS) $(insn_test_v2int_l_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2int_l_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2int_l_X1_OBJECTS) $(insn_test_v2int_l_X1_LDADD) $(LIBS)
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+ @rm -f insn_test_v2maxs_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2maxs_X0_OBJECTS) $(insn_test_v2maxs_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2maxs_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2maxs_X1_OBJECTS) $(insn_test_v2maxs_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2mins_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2mins_X0_OBJECTS) $(insn_test_v2mins_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2mins_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2mins_X1_OBJECTS) $(insn_test_v2mins_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2mnz_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2mnz_X0_OBJECTS) $(insn_test_v2mnz_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2mnz_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2mnz_X1_OBJECTS) $(insn_test_v2mnz_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2mulfsc_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2mulfsc_X0_OBJECTS) $(insn_test_v2mulfsc_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2muls_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2muls_X0_OBJECTS) $(insn_test_v2muls_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2mults_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2mults_X0_OBJECTS) $(insn_test_v2mults_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2mz_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2mz_X0_OBJECTS) $(insn_test_v2mz_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2mz_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2mz_X1_OBJECTS) $(insn_test_v2mz_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2packh_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2packh_X0_OBJECTS) $(insn_test_v2packh_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2packh_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2packh_X1_OBJECTS) $(insn_test_v2packh_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2packl_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2packl_X0_OBJECTS) $(insn_test_v2packl_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2packl_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2packl_X1_OBJECTS) $(insn_test_v2packl_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2packuc_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2packuc_X0_OBJECTS) $(insn_test_v2packuc_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2packuc_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2packuc_X1_OBJECTS) $(insn_test_v2packuc_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2sadas_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2sadas_X0_OBJECTS) $(insn_test_v2sadas_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2sadau_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2sadau_X0_OBJECTS) $(insn_test_v2sadau_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2sads_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2sads_X0_OBJECTS) $(insn_test_v2sads_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2sadu_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2sadu_X0_OBJECTS) $(insn_test_v2sadu_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2shl_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2shl_X0_OBJECTS) $(insn_test_v2shl_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2shl_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2shl_X1_OBJECTS) $(insn_test_v2shl_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2shli_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2shli_X0_OBJECTS) $(insn_test_v2shli_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2shli_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2shli_X1_OBJECTS) $(insn_test_v2shli_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2shlsc_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2shlsc_X0_OBJECTS) $(insn_test_v2shlsc_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2shlsc_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2shlsc_X1_OBJECTS) $(insn_test_v2shlsc_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2shrs_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2shrs_X0_OBJECTS) $(insn_test_v2shrs_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2shrs_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2shrs_X1_OBJECTS) $(insn_test_v2shrs_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2shrsi_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2shrsi_X0_OBJECTS) $(insn_test_v2shrsi_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2shrsi_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2shrsi_X1_OBJECTS) $(insn_test_v2shrsi_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2shru_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2shru_X0_OBJECTS) $(insn_test_v2shru_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2shru_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2shru_X1_OBJECTS) $(insn_test_v2shru_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2shrui_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2shrui_X0_OBJECTS) $(insn_test_v2shrui_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2shrui_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2shrui_X1_OBJECTS) $(insn_test_v2shrui_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2sub_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2sub_X0_OBJECTS) $(insn_test_v2sub_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2sub_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2sub_X1_OBJECTS) $(insn_test_v2sub_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2subsc_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2subsc_X0_OBJECTS) $(insn_test_v2subsc_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v2subsc_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v2subsc_X1_OBJECTS) $(insn_test_v2subsc_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v4add_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v4add_X0_OBJECTS) $(insn_test_v4add_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v4add_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v4add_X1_OBJECTS) $(insn_test_v4add_X1_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v4addsc_X0$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v4addsc_X0_OBJECTS) $(insn_test_v4addsc_X0_LDADD) $(LIBS)
+
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+ @rm -f insn_test_v4addsc_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v4addsc_X1_OBJECTS) $(insn_test_v4addsc_X1_LDADD) $(LIBS)
+
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+ $(AM_V_CCLD)$(LINK) $(insn_test_v4int_h_X0_OBJECTS) $(insn_test_v4int_h_X0_LDADD) $(LIBS)
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+ @rm -f insn_test_v4int_h_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v4int_h_X1_OBJECTS) $(insn_test_v4int_h_X1_LDADD) $(LIBS)
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+ $(AM_V_CCLD)$(LINK) $(insn_test_v4int_l_X0_OBJECTS) $(insn_test_v4int_l_X0_LDADD) $(LIBS)
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+ @rm -f insn_test_v4int_l_X1$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_test_v4int_l_X1_OBJECTS) $(insn_test_v4int_l_X1_LDADD) $(LIBS)
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+ $(AM_V_CCLD)$(LINK) $(insn_test_v4shl_X0_OBJECTS) $(insn_test_v4shl_X0_LDADD) $(LIBS)
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+
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+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -MT allexec-allexec.obj -MD -MP -MF $(DEPDIR)/allexec-allexec.Tpo -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/allexec-allexec.Tpo $(DEPDIR)/allexec-allexec.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='allexec.c' object='allexec-allexec.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(allexec_CFLAGS) $(CFLAGS) -c -o allexec-allexec.obj `if test -f 'allexec.c'; then $(CYGPATH_W) 'allexec.c'; else $(CYGPATH_W) '$(srcdir)/allexec.c'; fi`
+
+gen_insn_test-gen_insn_test.o: gen_insn_test.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(gen_insn_test_CFLAGS) $(CFLAGS) -MT gen_insn_test-gen_insn_test.o -MD -MP -MF $(DEPDIR)/gen_insn_test-gen_insn_test.Tpo -c -o gen_insn_test-gen_insn_test.o `test -f 'gen_insn_test.c' || echo '$(srcdir)/'`gen_insn_test.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/gen_insn_test-gen_insn_test.Tpo $(DEPDIR)/gen_insn_test-gen_insn_test.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='gen_insn_test.c' object='gen_insn_test-gen_insn_test.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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+
+gen_insn_test-gen_insn_test.obj: gen_insn_test.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(gen_insn_test_CFLAGS) $(CFLAGS) -MT gen_insn_test-gen_insn_test.obj -MD -MP -MF $(DEPDIR)/gen_insn_test-gen_insn_test.Tpo -c -o gen_insn_test-gen_insn_test.obj `if test -f 'gen_insn_test.c'; then $(CYGPATH_W) 'gen_insn_test.c'; else $(CYGPATH_W) '$(srcdir)/gen_insn_test.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/gen_insn_test-gen_insn_test.Tpo $(DEPDIR)/gen_insn_test-gen_insn_test.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='gen_insn_test.c' object='gen_insn_test-gen_insn_test.obj' libtool=no @AMDEPBACKSLASH@
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+
+ID: $(am__tagged_files)
+ $(am__define_uniq_tagged_files); mkid -fID $$unique
+tags: tags-am
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+tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+ set x; \
+ here=`pwd`; \
+ $(am__define_uniq_tagged_files); \
+ shift; \
+ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+ test -n "$$unique" || unique=$$empty_fix; \
+ if test $$# -gt 0; then \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ "$$@" $$unique; \
+ else \
+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+ $$unique; \
+ fi; \
+ fi
+ctags: ctags-am
+
+CTAGS: ctags
+ctags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+ $(am__define_uniq_tagged_files); \
+ test -z "$(CTAGS_ARGS)$$unique" \
+ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+ $$unique
+
+GTAGS:
+ here=`$(am__cd) $(top_builddir) && pwd` \
+ && $(am__cd) $(top_srcdir) \
+ && gtags -i $(GTAGS_ARGS) "$$here"
+cscopelist: cscopelist-am
+
+cscopelist-am: $(am__tagged_files)
+ list='$(am__tagged_files)'; \
+ case "$(srcdir)" in \
+ [\\/]* | ?:[\\/]*) sdir="$(srcdir)" ;; \
+ *) sdir=$(subdir)/$(srcdir) ;; \
+ esac; \
+ for i in $$list; do \
+ if test -f "$$i"; then \
+ echo "$(subdir)/$$i"; \
+ else \
+ echo "$$sdir/$$i"; \
+ fi; \
+ done >> $(top_builddir)/cscope.files
+
+distclean-tags:
+ -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+ list='$(DISTFILES)'; \
+ dist_files=`for file in $$list; do echo $$file; done | \
+ sed -e "s|^$$srcdirstrip/||;t" \
+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+ case $$dist_files in \
+ */*) $(MKDIR_P) `echo "$$dist_files" | \
+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+ sort -u` ;; \
+ esac; \
+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(PROGRAMS) $(SCRIPTS)
+installdirs:
+ for dir in "$(DESTDIR)$(bindir)"; do \
+ test -z "$$dir" || $(MKDIR_P) "$$dir"; \
+ done
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+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ install; \
+ else \
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \
+ fi
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+dvi: dvi-am
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+dvi-am:
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+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
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+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
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+pdf: pdf-am
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+
+.PHONY: CTAGS GTAGS TAGS all all-am check check-am check-local clean \
+ clean-binPROGRAMS clean-checkPROGRAMS clean-generic \
+ clean-local cscopelist-am ctags ctags-am distclean \
+ distclean-compile distclean-generic distclean-tags distdir dvi \
+ dvi-am html html-am info info-am install install-am \
+ install-binPROGRAMS install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-html \
+ install-html-am install-info install-info-am install-man \
+ install-pdf install-pdf-am install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ maintainer-clean maintainer-clean-generic mostlyclean \
+ mostlyclean-compile mostlyclean-generic pdf pdf-am ps ps-am \
+ tags tags-am uninstall uninstall-am uninstall-binPROGRAMS
+
+.PRECIOUS: Makefile
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
+# It needs to be depended on by an 'uninstall-local' rule.
+uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
+uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+$(addsuffix .c, $(insn_tests)) : gen_insn_test
+ @$(srcdir)/gen_test.sh $@
+
+$(addsuffix .stdout.exp, $(insn_tests)) : $(insn_tests)
+ ./$(basename $(basename $@)) > $@
+
+$(addsuffix .stderr.exp, $(insn_tests)) :
+ touch $@
+
+$(addsuffix .vgtest, $(insn_tests)) :
+ echo -e "prog: $(basename $@)\nvgopts: -q" > $@
+
+check-am : $(addsuffix .stdout.exp, $(insn_tests)) $(addsuffix .stderr.exp, $(insn_tests)) $(addsuffix .vgtest, $(insn_tests))
+
+clean-am :
+ @rm -f *.stderr.exp *.stdout.exp *.vgtest $(addsuffix .c, $(insn_tests)) $(addsuffix .o, $(insn_tests)) $(insn_tests)
+ @rm -f *.o $(bin_PROGRAMS)
+
+distclean-am : clean-am
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/none/tests/tilegx/allexec.c b/none/tests/tilegx/allexec.c
deleted file mode 120000
index 6d6a9cf..0000000
--- a/none/tests/tilegx/allexec.c
+++ /dev/null
@@ -1 +0,0 @@
-../allexec.c
\ No newline at end of file
diff --git a/none/tests/allexec.c b/none/tests/tilegx/allexec.c
similarity index 100%
copy from none/tests/allexec.c
copy to none/tests/tilegx/allexec.c
diff --git a/none/tests/tilegx/insn_test_add_X0.c b/none/tests/tilegx/insn_test_add_X0.c
new file mode 100644
index 0000000..a460e2b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_add_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_add_X0.c
+//op=22
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xcbf6dda12670067, 0x15063831748c3911 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r35, -22068\n"
+ "shl16insli r35, r35, -316\n"
+ "shl16insli r35, r35, -2663\n"
+ "shl16insli r35, r35, 29773\n"
+ "moveli r25, 14446\n"
+ "shl16insli r25, r25, 26605\n"
+ "shl16insli r25, r25, 31496\n"
+ "shl16insli r25, r25, -24631\n"
+ "moveli r34, -21610\n"
+ "shl16insli r34, r34, 7292\n"
+ "shl16insli r34, r34, -8245\n"
+ "shl16insli r34, r34, 30416\n"
+ "{ add r35, r25, r34 ; fnop }\n"
+ "move %0, r35\n"
+ "move %1, r25\n"
+ "move %2, r34\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_add_X1.c b/none/tests/tilegx/insn_test_add_X1.c
new file mode 100644
index 0000000..9f2e174
--- /dev/null
+++ b/none/tests/tilegx/insn_test_add_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_add_X1.c
+//op=22
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xcbf6dda12670067, 0x15063831748c3911 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r35, -22068\n"
+ "shl16insli r35, r35, -316\n"
+ "shl16insli r35, r35, -2663\n"
+ "shl16insli r35, r35, 29773\n"
+ "moveli r25, 14446\n"
+ "shl16insli r25, r25, 26605\n"
+ "shl16insli r25, r25, 31496\n"
+ "shl16insli r25, r25, -24631\n"
+ "moveli r34, -21610\n"
+ "shl16insli r34, r34, 7292\n"
+ "shl16insli r34, r34, -8245\n"
+ "shl16insli r34, r34, 30416\n"
+ "{ fnop ; add r35, r25, r34 }\n"
+ "move %0, r35\n"
+ "move %1, r25\n"
+ "move %2, r34\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_add_Y0.c b/none/tests/tilegx/insn_test_add_Y0.c
new file mode 100644
index 0000000..cf6bca0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_add_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_add_Y0.c
+//op=22
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xcbf6dda12670067, 0x15063831748c3911 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r35, -22068\n"
+ "shl16insli r35, r35, -316\n"
+ "shl16insli r35, r35, -2663\n"
+ "shl16insli r35, r35, 29773\n"
+ "moveli r25, 14446\n"
+ "shl16insli r25, r25, 26605\n"
+ "shl16insli r25, r25, 31496\n"
+ "shl16insli r25, r25, -24631\n"
+ "moveli r34, -21610\n"
+ "shl16insli r34, r34, 7292\n"
+ "shl16insli r34, r34, -8245\n"
+ "shl16insli r34, r34, 30416\n"
+ "{ add r35, r25, r34 ; fnop ; ld r63, r54 }\n"
+ "move %0, r35\n"
+ "move %1, r25\n"
+ "move %2, r34\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_add_Y1.c b/none/tests/tilegx/insn_test_add_Y1.c
new file mode 100644
index 0000000..071c9b5
--- /dev/null
+++ b/none/tests/tilegx/insn_test_add_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_add_Y1.c
+//op=22
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xcbf6dda12670067, 0x15063831748c3911 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r35, -22068\n"
+ "shl16insli r35, r35, -316\n"
+ "shl16insli r35, r35, -2663\n"
+ "shl16insli r35, r35, 29773\n"
+ "moveli r25, 14446\n"
+ "shl16insli r25, r25, 26605\n"
+ "shl16insli r25, r25, 31496\n"
+ "shl16insli r25, r25, -24631\n"
+ "moveli r34, -21610\n"
+ "shl16insli r34, r34, 7292\n"
+ "shl16insli r34, r34, -8245\n"
+ "shl16insli r34, r34, 30416\n"
+ "{ fnop ; add r35, r25, r34 ; ld r63, r54 }\n"
+ "move %0, r35\n"
+ "move %1, r25\n"
+ "move %2, r34\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addi_X0.c b/none/tests/tilegx/insn_test_addi_X0.c
new file mode 100644
index 0000000..7393bdb
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addi_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_addi_X0.c
+//op=23
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc50a9ede838fadbb, 0xc2d6db3411b6362 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r10, -29553\n"
+ "shl16insli r10, r10, 1035\n"
+ "shl16insli r10, r10, 5152\n"
+ "shl16insli r10, r10, -10394\n"
+ "moveli r3, 16496\n"
+ "shl16insli r3, r3, 1901\n"
+ "shl16insli r3, r3, -17744\n"
+ "shl16insli r3, r3, 5578\n"
+ "{ addi r10, r3, 13 ; fnop }\n"
+ "move %0, r10\n"
+ "move %1, r3\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addi_X1.c b/none/tests/tilegx/insn_test_addi_X1.c
new file mode 100644
index 0000000..b52a8fe
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addi_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_addi_X1.c
+//op=23
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc50a9ede838fadbb, 0xc2d6db3411b6362 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r10, -29553\n"
+ "shl16insli r10, r10, 1035\n"
+ "shl16insli r10, r10, 5152\n"
+ "shl16insli r10, r10, -10394\n"
+ "moveli r3, 16496\n"
+ "shl16insli r3, r3, 1901\n"
+ "shl16insli r3, r3, -17744\n"
+ "shl16insli r3, r3, 5578\n"
+ "{ fnop ; addi r10, r3, 13 }\n"
+ "move %0, r10\n"
+ "move %1, r3\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addi_Y0.c b/none/tests/tilegx/insn_test_addi_Y0.c
new file mode 100644
index 0000000..0fbcb9b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addi_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_addi_Y0.c
+//op=23
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc50a9ede838fadbb, 0xc2d6db3411b6362 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r10, -29553\n"
+ "shl16insli r10, r10, 1035\n"
+ "shl16insli r10, r10, 5152\n"
+ "shl16insli r10, r10, -10394\n"
+ "moveli r3, 16496\n"
+ "shl16insli r3, r3, 1901\n"
+ "shl16insli r3, r3, -17744\n"
+ "shl16insli r3, r3, 5578\n"
+ "{ addi r10, r3, 13 ; fnop ; ld r63, r54 }\n"
+ "move %0, r10\n"
+ "move %1, r3\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addi_Y1.c b/none/tests/tilegx/insn_test_addi_Y1.c
new file mode 100644
index 0000000..8cb9af8
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addi_Y1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_addi_Y1.c
+//op=23
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc50a9ede838fadbb, 0xc2d6db3411b6362 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r10, -29553\n"
+ "shl16insli r10, r10, 1035\n"
+ "shl16insli r10, r10, 5152\n"
+ "shl16insli r10, r10, -10394\n"
+ "moveli r3, 16496\n"
+ "shl16insli r3, r3, 1901\n"
+ "shl16insli r3, r3, -17744\n"
+ "shl16insli r3, r3, 5578\n"
+ "{ fnop ; addi r10, r3, 13 ; ld r63, r54 }\n"
+ "move %0, r10\n"
+ "move %1, r3\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addli_X0.c b/none/tests/tilegx/insn_test_addli_X0.c
new file mode 100644
index 0000000..8521ddf
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addli_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_addli_X0.c
+//op=24
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xeebea8448496854d, 0x9fc8faed728cb8c8 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r7, -15865\n"
+ "shl16insli r7, r7, -8928\n"
+ "shl16insli r7, r7, 2151\n"
+ "shl16insli r7, r7, -8089\n"
+ "moveli r8, 18685\n"
+ "shl16insli r8, r8, 5716\n"
+ "shl16insli r8, r8, -22554\n"
+ "shl16insli r8, r8, 27127\n"
+ "{ addli r7, r8, 12693 ; fnop }\n"
+ "move %0, r7\n"
+ "move %1, r8\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addli_X1.c b/none/tests/tilegx/insn_test_addli_X1.c
new file mode 100644
index 0000000..b26007f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addli_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_addli_X1.c
+//op=24
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xeebea8448496854d, 0x9fc8faed728cb8c8 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r7, -15865\n"
+ "shl16insli r7, r7, -8928\n"
+ "shl16insli r7, r7, 2151\n"
+ "shl16insli r7, r7, -8089\n"
+ "moveli r8, 18685\n"
+ "shl16insli r8, r8, 5716\n"
+ "shl16insli r8, r8, -22554\n"
+ "shl16insli r8, r8, 27127\n"
+ "{ fnop ; addli r7, r8, 12693 }\n"
+ "move %0, r7\n"
+ "move %1, r8\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addx_X0.c b/none/tests/tilegx/insn_test_addx_X0.c
new file mode 100644
index 0000000..29a7480
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addx_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_addx_X0.c
+//op=25
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa866c1efe28f7aab, 0x422260f8cf40ffbb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, 16437\n"
+ "shl16insli r16, r16, -17949\n"
+ "shl16insli r16, r16, -5049\n"
+ "shl16insli r16, r16, 16324\n"
+ "moveli r19, 21012\n"
+ "shl16insli r19, r19, -29133\n"
+ "shl16insli r19, r19, -8710\n"
+ "shl16insli r19, r19, -16472\n"
+ "moveli r2, -10150\n"
+ "shl16insli r2, r2, -32553\n"
+ "shl16insli r2, r2, -18908\n"
+ "shl16insli r2, r2, 23364\n"
+ "{ addx r16, r19, r2 ; fnop }\n"
+ "move %0, r16\n"
+ "move %1, r19\n"
+ "move %2, r2\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addx_X1.c b/none/tests/tilegx/insn_test_addx_X1.c
new file mode 100644
index 0000000..776df63
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addx_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_addx_X1.c
+//op=25
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa866c1efe28f7aab, 0x422260f8cf40ffbb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, 16437\n"
+ "shl16insli r16, r16, -17949\n"
+ "shl16insli r16, r16, -5049\n"
+ "shl16insli r16, r16, 16324\n"
+ "moveli r19, 21012\n"
+ "shl16insli r19, r19, -29133\n"
+ "shl16insli r19, r19, -8710\n"
+ "shl16insli r19, r19, -16472\n"
+ "moveli r2, -10150\n"
+ "shl16insli r2, r2, -32553\n"
+ "shl16insli r2, r2, -18908\n"
+ "shl16insli r2, r2, 23364\n"
+ "{ fnop ; addx r16, r19, r2 }\n"
+ "move %0, r16\n"
+ "move %1, r19\n"
+ "move %2, r2\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addx_Y0.c b/none/tests/tilegx/insn_test_addx_Y0.c
new file mode 100644
index 0000000..c2e11dc
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addx_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_addx_Y0.c
+//op=25
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa866c1efe28f7aab, 0x422260f8cf40ffbb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, 16437\n"
+ "shl16insli r16, r16, -17949\n"
+ "shl16insli r16, r16, -5049\n"
+ "shl16insli r16, r16, 16324\n"
+ "moveli r19, 21012\n"
+ "shl16insli r19, r19, -29133\n"
+ "shl16insli r19, r19, -8710\n"
+ "shl16insli r19, r19, -16472\n"
+ "moveli r2, -10150\n"
+ "shl16insli r2, r2, -32553\n"
+ "shl16insli r2, r2, -18908\n"
+ "shl16insli r2, r2, 23364\n"
+ "{ addx r16, r19, r2 ; fnop ; ld r63, r54 }\n"
+ "move %0, r16\n"
+ "move %1, r19\n"
+ "move %2, r2\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addx_Y1.c b/none/tests/tilegx/insn_test_addx_Y1.c
new file mode 100644
index 0000000..cc2b370
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addx_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_addx_Y1.c
+//op=25
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa866c1efe28f7aab, 0x422260f8cf40ffbb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, 16437\n"
+ "shl16insli r16, r16, -17949\n"
+ "shl16insli r16, r16, -5049\n"
+ "shl16insli r16, r16, 16324\n"
+ "moveli r19, 21012\n"
+ "shl16insli r19, r19, -29133\n"
+ "shl16insli r19, r19, -8710\n"
+ "shl16insli r19, r19, -16472\n"
+ "moveli r2, -10150\n"
+ "shl16insli r2, r2, -32553\n"
+ "shl16insli r2, r2, -18908\n"
+ "shl16insli r2, r2, 23364\n"
+ "{ fnop ; addx r16, r19, r2 ; ld r63, r54 }\n"
+ "move %0, r16\n"
+ "move %1, r19\n"
+ "move %2, r2\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addxi_X0.c b/none/tests/tilegx/insn_test_addxi_X0.c
new file mode 100644
index 0000000..3033632
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addxi_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_addxi_X0.c
+//op=26
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x82cd9e74ccb2b602, 0xb405f09d3ac1f78c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, -28042\n"
+ "shl16insli r16, r16, 29759\n"
+ "shl16insli r16, r16, 8449\n"
+ "shl16insli r16, r16, -25778\n"
+ "moveli r19, 15873\n"
+ "shl16insli r19, r19, -26278\n"
+ "shl16insli r19, r19, -22224\n"
+ "shl16insli r19, r19, 11419\n"
+ "{ addxi r16, r19, -1 ; fnop }\n"
+ "move %0, r16\n"
+ "move %1, r19\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addxi_X1.c b/none/tests/tilegx/insn_test_addxi_X1.c
new file mode 100644
index 0000000..90ebe4d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addxi_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_addxi_X1.c
+//op=26
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x82cd9e74ccb2b602, 0xb405f09d3ac1f78c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, -28042\n"
+ "shl16insli r16, r16, 29759\n"
+ "shl16insli r16, r16, 8449\n"
+ "shl16insli r16, r16, -25778\n"
+ "moveli r19, 15873\n"
+ "shl16insli r19, r19, -26278\n"
+ "shl16insli r19, r19, -22224\n"
+ "shl16insli r19, r19, 11419\n"
+ "{ fnop ; addxi r16, r19, -1 }\n"
+ "move %0, r16\n"
+ "move %1, r19\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addxi_Y0.c b/none/tests/tilegx/insn_test_addxi_Y0.c
new file mode 100644
index 0000000..83a7a11
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addxi_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_addxi_Y0.c
+//op=26
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x82cd9e74ccb2b602, 0xb405f09d3ac1f78c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, -28042\n"
+ "shl16insli r16, r16, 29759\n"
+ "shl16insli r16, r16, 8449\n"
+ "shl16insli r16, r16, -25778\n"
+ "moveli r19, 15873\n"
+ "shl16insli r19, r19, -26278\n"
+ "shl16insli r19, r19, -22224\n"
+ "shl16insli r19, r19, 11419\n"
+ "{ addxi r16, r19, -1 ; fnop ; ld r63, r54 }\n"
+ "move %0, r16\n"
+ "move %1, r19\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addxi_Y1.c b/none/tests/tilegx/insn_test_addxi_Y1.c
new file mode 100644
index 0000000..df15bdc
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addxi_Y1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_addxi_Y1.c
+//op=26
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x82cd9e74ccb2b602, 0xb405f09d3ac1f78c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, -28042\n"
+ "shl16insli r16, r16, 29759\n"
+ "shl16insli r16, r16, 8449\n"
+ "shl16insli r16, r16, -25778\n"
+ "moveli r19, 15873\n"
+ "shl16insli r19, r19, -26278\n"
+ "shl16insli r19, r19, -22224\n"
+ "shl16insli r19, r19, 11419\n"
+ "{ fnop ; addxi r16, r19, -1 ; ld r63, r54 }\n"
+ "move %0, r16\n"
+ "move %1, r19\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addxli_X0.c b/none/tests/tilegx/insn_test_addxli_X0.c
new file mode 100644
index 0000000..21e230b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addxli_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_addxli_X0.c
+//op=27
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd5875ac284be5010, 0xfeec3c7ab59e554 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r45, -16303\n"
+ "shl16insli r45, r45, -6468\n"
+ "shl16insli r45, r45, -24288\n"
+ "shl16insli r45, r45, 22752\n"
+ "moveli r45, 5983\n"
+ "shl16insli r45, r45, 27427\n"
+ "shl16insli r45, r45, 451\n"
+ "shl16insli r45, r45, -26979\n"
+ "{ addxli r45, r45, -23808 ; fnop }\n"
+ "move %0, r45\n"
+ "move %1, r45\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addxli_X1.c b/none/tests/tilegx/insn_test_addxli_X1.c
new file mode 100644
index 0000000..2829261
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addxli_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_addxli_X1.c
+//op=27
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd5875ac284be5010, 0xfeec3c7ab59e554 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r45, -16303\n"
+ "shl16insli r45, r45, -6468\n"
+ "shl16insli r45, r45, -24288\n"
+ "shl16insli r45, r45, 22752\n"
+ "moveli r45, 5983\n"
+ "shl16insli r45, r45, 27427\n"
+ "shl16insli r45, r45, 451\n"
+ "shl16insli r45, r45, -26979\n"
+ "{ fnop ; addxli r45, r45, -23808 }\n"
+ "move %0, r45\n"
+ "move %1, r45\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addxsc_X0.c b/none/tests/tilegx/insn_test_addxsc_X0.c
new file mode 100644
index 0000000..12bfca1
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addxsc_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_addxsc_X0.c
+//op=28
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd9528fcf37ad6ac6, 0xe41f03815d99ac96 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, 27624\n"
+ "shl16insli r16, r16, 3804\n"
+ "shl16insli r16, r16, -16569\n"
+ "shl16insli r16, r16, -19918\n"
+ "moveli r12, -8205\n"
+ "shl16insli r12, r12, 24120\n"
+ "shl16insli r12, r12, 20070\n"
+ "shl16insli r12, r12, 12693\n"
+ "moveli r5, 11830\n"
+ "shl16insli r5, r5, -1700\n"
+ "shl16insli r5, r5, 8629\n"
+ "shl16insli r5, r5, -24868\n"
+ "{ addxsc r16, r12, r5 ; fnop }\n"
+ "move %0, r16\n"
+ "move %1, r12\n"
+ "move %2, r5\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_addxsc_X1.c b/none/tests/tilegx/insn_test_addxsc_X1.c
new file mode 100644
index 0000000..2d1fae4
--- /dev/null
+++ b/none/tests/tilegx/insn_test_addxsc_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_addxsc_X1.c
+//op=28
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd9528fcf37ad6ac6, 0xe41f03815d99ac96 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, 27624\n"
+ "shl16insli r16, r16, 3804\n"
+ "shl16insli r16, r16, -16569\n"
+ "shl16insli r16, r16, -19918\n"
+ "moveli r12, -8205\n"
+ "shl16insli r12, r12, 24120\n"
+ "shl16insli r12, r12, 20070\n"
+ "shl16insli r12, r12, 12693\n"
+ "moveli r5, 11830\n"
+ "shl16insli r5, r5, -1700\n"
+ "shl16insli r5, r5, 8629\n"
+ "shl16insli r5, r5, -24868\n"
+ "{ fnop ; addxsc r16, r12, r5 }\n"
+ "move %0, r16\n"
+ "move %1, r12\n"
+ "move %2, r5\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_and_X0.c b/none/tests/tilegx/insn_test_and_X0.c
new file mode 100644
index 0000000..d9ac40f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_and_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_and_X0.c
+//op=29
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6fd6d80e8b18c9bb, 0xe18dcaef23b64e7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -25962\n"
+ "shl16insli r38, r38, -29618\n"
+ "shl16insli r38, r38, 9810\n"
+ "shl16insli r38, r38, -7855\n"
+ "moveli r16, -14420\n"
+ "shl16insli r16, r16, 14085\n"
+ "shl16insli r16, r16, 14918\n"
+ "shl16insli r16, r16, 4353\n"
+ "moveli r13, -12524\n"
+ "shl16insli r13, r13, -16020\n"
+ "shl16insli r13, r13, -28698\n"
+ "shl16insli r13, r13, -10230\n"
+ "{ and r38, r16, r13 ; fnop }\n"
+ "move %0, r38\n"
+ "move %1, r16\n"
+ "move %2, r13\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_and_X1.c b/none/tests/tilegx/insn_test_and_X1.c
new file mode 100644
index 0000000..c15dfc1
--- /dev/null
+++ b/none/tests/tilegx/insn_test_and_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_and_X1.c
+//op=29
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6fd6d80e8b18c9bb, 0xe18dcaef23b64e7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -25962\n"
+ "shl16insli r38, r38, -29618\n"
+ "shl16insli r38, r38, 9810\n"
+ "shl16insli r38, r38, -7855\n"
+ "moveli r16, -14420\n"
+ "shl16insli r16, r16, 14085\n"
+ "shl16insli r16, r16, 14918\n"
+ "shl16insli r16, r16, 4353\n"
+ "moveli r13, -12524\n"
+ "shl16insli r13, r13, -16020\n"
+ "shl16insli r13, r13, -28698\n"
+ "shl16insli r13, r13, -10230\n"
+ "{ fnop ; and r38, r16, r13 }\n"
+ "move %0, r38\n"
+ "move %1, r16\n"
+ "move %2, r13\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_and_Y0.c b/none/tests/tilegx/insn_test_and_Y0.c
new file mode 100644
index 0000000..f5088a8
--- /dev/null
+++ b/none/tests/tilegx/insn_test_and_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_and_Y0.c
+//op=29
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6fd6d80e8b18c9bb, 0xe18dcaef23b64e7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -25962\n"
+ "shl16insli r38, r38, -29618\n"
+ "shl16insli r38, r38, 9810\n"
+ "shl16insli r38, r38, -7855\n"
+ "moveli r16, -14420\n"
+ "shl16insli r16, r16, 14085\n"
+ "shl16insli r16, r16, 14918\n"
+ "shl16insli r16, r16, 4353\n"
+ "moveli r13, -12524\n"
+ "shl16insli r13, r13, -16020\n"
+ "shl16insli r13, r13, -28698\n"
+ "shl16insli r13, r13, -10230\n"
+ "{ and r38, r16, r13 ; fnop ; ld r63, r54 }\n"
+ "move %0, r38\n"
+ "move %1, r16\n"
+ "move %2, r13\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_and_Y1.c b/none/tests/tilegx/insn_test_and_Y1.c
new file mode 100644
index 0000000..ad153bb
--- /dev/null
+++ b/none/tests/tilegx/insn_test_and_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_and_Y1.c
+//op=29
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6fd6d80e8b18c9bb, 0xe18dcaef23b64e7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -25962\n"
+ "shl16insli r38, r38, -29618\n"
+ "shl16insli r38, r38, 9810\n"
+ "shl16insli r38, r38, -7855\n"
+ "moveli r16, -14420\n"
+ "shl16insli r16, r16, 14085\n"
+ "shl16insli r16, r16, 14918\n"
+ "shl16insli r16, r16, 4353\n"
+ "moveli r13, -12524\n"
+ "shl16insli r13, r13, -16020\n"
+ "shl16insli r13, r13, -28698\n"
+ "shl16insli r13, r13, -10230\n"
+ "{ fnop ; and r38, r16, r13 ; ld r63, r54 }\n"
+ "move %0, r38\n"
+ "move %1, r16\n"
+ "move %2, r13\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_andi_X0.c b/none/tests/tilegx/insn_test_andi_X0.c
new file mode 100644
index 0000000..a2fdff0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_andi_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_andi_X0.c
+//op=30
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd5c03dafaeab4e7e, 0xbca200a47bf08fef };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r46, -22782\n"
+ "shl16insli r46, r46, -24188\n"
+ "shl16insli r46, r46, -5494\n"
+ "shl16insli r46, r46, 12791\n"
+ "moveli r3, -24353\n"
+ "shl16insli r3, r3, 7605\n"
+ "shl16insli r3, r3, -19417\n"
+ "shl16insli r3, r3, 15971\n"
+ "{ andi r46, r3, 96 ; fnop }\n"
+ "move %0, r46\n"
+ "move %1, r3\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_andi_X1.c b/none/tests/tilegx/insn_test_andi_X1.c
new file mode 100644
index 0000000..0248411
--- /dev/null
+++ b/none/tests/tilegx/insn_test_andi_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_andi_X1.c
+//op=30
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd5c03dafaeab4e7e, 0xbca200a47bf08fef };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r46, -22782\n"
+ "shl16insli r46, r46, -24188\n"
+ "shl16insli r46, r46, -5494\n"
+ "shl16insli r46, r46, 12791\n"
+ "moveli r3, -24353\n"
+ "shl16insli r3, r3, 7605\n"
+ "shl16insli r3, r3, -19417\n"
+ "shl16insli r3, r3, 15971\n"
+ "{ fnop ; andi r46, r3, 96 }\n"
+ "move %0, r46\n"
+ "move %1, r3\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_andi_Y0.c b/none/tests/tilegx/insn_test_andi_Y0.c
new file mode 100644
index 0000000..2e1dc50
--- /dev/null
+++ b/none/tests/tilegx/insn_test_andi_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_andi_Y0.c
+//op=30
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd5c03dafaeab4e7e, 0xbca200a47bf08fef };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r46, -22782\n"
+ "shl16insli r46, r46, -24188\n"
+ "shl16insli r46, r46, -5494\n"
+ "shl16insli r46, r46, 12791\n"
+ "moveli r3, -24353\n"
+ "shl16insli r3, r3, 7605\n"
+ "shl16insli r3, r3, -19417\n"
+ "shl16insli r3, r3, 15971\n"
+ "{ andi r46, r3, 96 ; fnop ; ld r63, r54 }\n"
+ "move %0, r46\n"
+ "move %1, r3\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_andi_Y1.c b/none/tests/tilegx/insn_test_andi_Y1.c
new file mode 100644
index 0000000..180fdac
--- /dev/null
+++ b/none/tests/tilegx/insn_test_andi_Y1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_andi_Y1.c
+//op=30
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd5c03dafaeab4e7e, 0xbca200a47bf08fef };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r46, -22782\n"
+ "shl16insli r46, r46, -24188\n"
+ "shl16insli r46, r46, -5494\n"
+ "shl16insli r46, r46, 12791\n"
+ "moveli r3, -24353\n"
+ "shl16insli r3, r3, 7605\n"
+ "shl16insli r3, r3, -19417\n"
+ "shl16insli r3, r3, 15971\n"
+ "{ fnop ; andi r46, r3, 96 ; ld r63, r54 }\n"
+ "move %0, r46\n"
+ "move %1, r3\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_beqz_X1.c b/none/tests/tilegx/insn_test_beqz_X1.c
new file mode 100644
index 0000000..0226c39
--- /dev/null
+++ b/none/tests/tilegx/insn_test_beqz_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_beqz_X1.c
+//op=31
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa3f9a29247d48ea1, 0xb0a509adc464a67c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r0, 0\n"
+ "beqz r0, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_beqzt_X1.c b/none/tests/tilegx/insn_test_beqzt_X1.c
new file mode 100644
index 0000000..4321ab8
--- /dev/null
+++ b/none/tests/tilegx/insn_test_beqzt_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_beqzt_X1.c
+//op=32
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4eb70a2cb8e0ad00, 0xae0d7beb6b9186fd };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r25, 0\n"
+ "beqzt r25, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_bfexts_X0.c b/none/tests/tilegx/insn_test_bfexts_X0.c
new file mode 100644
index 0000000..2cb8ad5
--- /dev/null
+++ b/none/tests/tilegx/insn_test_bfexts_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_bfexts_X0.c
+//op=33
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x159952beef1e2d8e, 0x344fa86966757d1d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r29, 14446\n"
+ "shl16insli r29, r29, 26605\n"
+ "shl16insli r29, r29, 31496\n"
+ "shl16insli r29, r29, -24631\n"
+ "moveli r9, -15179\n"
+ "shl16insli r9, r9, 29659\n"
+ "shl16insli r9, r9, 32207\n"
+ "shl16insli r9, r9, 7899\n"
+ "{ bfexts r29, r9, 11, 9 ; fnop }\n"
+ "move %0, r29\n"
+ "move %1, r9\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_bfextu_X0.c b/none/tests/tilegx/insn_test_bfextu_X0.c
new file mode 100644
index 0000000..7baca72
--- /dev/null
+++ b/none/tests/tilegx/insn_test_bfextu_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_bfextu_X0.c
+//op=34
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7eda32ada2f5060, 0xbcd5fb19de288be };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r15, -32243\n"
+ "shl16insli r15, r15, 5581\n"
+ "shl16insli r15, r15, 25121\n"
+ "shl16insli r15, r15, 18660\n"
+ "moveli r32, -2571\n"
+ "shl16insli r32, r32, 10073\n"
+ "shl16insli r32, r32, -8744\n"
+ "shl16insli r32, r32, 32440\n"
+ "{ bfextu r15, r32, 13, 52 ; fnop }\n"
+ "move %0, r15\n"
+ "move %1, r32\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_bfins_X0.c b/none/tests/tilegx/insn_test_bfins_X0.c
new file mode 100644
index 0000000..af34f5a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_bfins_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_bfins_X0.c
+//op=35
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6873aadf3e763127, 0x74d4eb98b256c26b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r49, 16197\n"
+ "shl16insli r49, r49, -9240\n"
+ "shl16insli r49, r49, -11331\n"
+ "shl16insli r49, r49, -8418\n"
+ "moveli r2, 17433\n"
+ "shl16insli r2, r2, 14709\n"
+ "shl16insli r2, r2, 26320\n"
+ "shl16insli r2, r2, -3232\n"
+ "{ bfins r49, r2, 21, 63 ; fnop }\n"
+ "move %0, r49\n"
+ "move %1, r2\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_bgez_X1.c b/none/tests/tilegx/insn_test_bgez_X1.c
new file mode 100644
index 0000000..b46646d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_bgez_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_bgez_X1.c
+//op=36
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x3c14fa8c76bb7fe3, 0xc8b092c42b2e6d41 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r23, 1\n"
+ "bgez r23, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_bgezt_X1.c b/none/tests/tilegx/insn_test_bgezt_X1.c
new file mode 100644
index 0000000..a61ef68
--- /dev/null
+++ b/none/tests/tilegx/insn_test_bgezt_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_bgezt_X1.c
+//op=37
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x712fa2e35cfc84ba, 0xd82bef9b16da454e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r31, 1\n"
+ "bgezt r31, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_bgtz_X1.c b/none/tests/tilegx/insn_test_bgtz_X1.c
new file mode 100644
index 0000000..2a1cd10
--- /dev/null
+++ b/none/tests/tilegx/insn_test_bgtz_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_bgtz_X1.c
+//op=38
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2220b583f77f7510, 0xb026dbf41e76db36 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r46, 0\n"
+ "bgtz r46, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_bgtzt_X1.c b/none/tests/tilegx/insn_test_bgtzt_X1.c
new file mode 100644
index 0000000..25683ea
--- /dev/null
+++ b/none/tests/tilegx/insn_test_bgtzt_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_bgtzt_X1.c
+//op=39
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7b1d4eb76be6dea6, 0x54e332914bce7010 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r24, 1\n"
+ "bgtzt r24, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_blbc_X1.c b/none/tests/tilegx/insn_test_blbc_X1.c
new file mode 100644
index 0000000..fa7bd53
--- /dev/null
+++ b/none/tests/tilegx/insn_test_blbc_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_blbc_X1.c
+//op=40
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x27ec0f0e74369816, 0x4aceb47ef3ca8ac3 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r8, 0\n"
+ "blbc r8, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_blbct_X1.c b/none/tests/tilegx/insn_test_blbct_X1.c
new file mode 100644
index 0000000..df5de61
--- /dev/null
+++ b/none/tests/tilegx/insn_test_blbct_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_blbct_X1.c
+//op=41
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xec57de1f0b8de6b3, 0xba5cc6450c5508b9 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r39, 0\n"
+ "blbct r39, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_blbs_X1.c b/none/tests/tilegx/insn_test_blbs_X1.c
new file mode 100644
index 0000000..e6f0e90
--- /dev/null
+++ b/none/tests/tilegx/insn_test_blbs_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_blbs_X1.c
+//op=42
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xce5c4dd59315697c, 0x420f71d29a23b3eb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r42, 1\n"
+ "blbs r42, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_blbst_X1.c b/none/tests/tilegx/insn_test_blbst_X1.c
new file mode 100644
index 0000000..49edd77
--- /dev/null
+++ b/none/tests/tilegx/insn_test_blbst_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_blbst_X1.c
+//op=43
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc2c31988eb4ca702, 0x400324c1f2522cf8 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r33, 0\n"
+ "blbst r33, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_blez_X1.c b/none/tests/tilegx/insn_test_blez_X1.c
new file mode 100644
index 0000000..2d23f40
--- /dev/null
+++ b/none/tests/tilegx/insn_test_blez_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_blez_X1.c
+//op=44
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa9ccfec4f599744d, 0xcbf6dda12670067 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r28, 0\n"
+ "blez r28, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_blezt_X1.c b/none/tests/tilegx/insn_test_blezt_X1.c
new file mode 100644
index 0000000..6e715da
--- /dev/null
+++ b/none/tests/tilegx/insn_test_blezt_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_blezt_X1.c
+//op=45
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x22577cfa5789437f, 0x480f8d654b2eb8b3 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r45, 1\n"
+ "blezt r45, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_bltz_X1.c b/none/tests/tilegx/insn_test_bltz_X1.c
new file mode 100644
index 0000000..3106baf
--- /dev/null
+++ b/none/tests/tilegx/insn_test_bltz_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_bltz_X1.c
+//op=46
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x8c8f040b1420d766, 0xc50a9ede838fadbb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r10, 0\n"
+ "bltz r10, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_bltzt_X1.c b/none/tests/tilegx/insn_test_bltzt_X1.c
new file mode 100644
index 0000000..a98b69b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_bltzt_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_bltzt_X1.c
+//op=47
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xfb39d803fce5e022, 0xa6f1d43f68e5d60e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r31, 0\n"
+ "bltzt r31, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_bnez_X1.c b/none/tests/tilegx/insn_test_bnez_X1.c
new file mode 100644
index 0000000..f24d670
--- /dev/null
+++ b/none/tests/tilegx/insn_test_bnez_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_bnez_X1.c
+//op=48
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc207dd200867e067, 0xeebea8448496854d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r7, 1\n"
+ "bnez r7, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_bnezt_X1.c b/none/tests/tilegx/insn_test_bnezt_X1.c
new file mode 100644
index 0000000..e24473f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_bnezt_X1.c
@@ -0,0 +1,26 @@
+//file: _insn_test_bnezt_X1.c
+//op=49
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbe6bcf910f7bc3c9, 0xcfc849bbd49048f6 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "movei r34, 0\n"
+ "bnezt r34, %0\n"
+ "jal %1\n"
+ :: "i"(func_exit), "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_clz_X0.c b/none/tests/tilegx/insn_test_clz_X0.c
new file mode 100644
index 0000000..0a71047
--- /dev/null
+++ b/none/tests/tilegx/insn_test_clz_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_clz_X0.c
+//op=50
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4035b9e3ec473fc4, 0xa866c1efe28f7aab };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -10150\n"
+ "shl16insli r3, r3, -32553\n"
+ "shl16insli r3, r3, -18908\n"
+ "shl16insli r3, r3, 23364\n"
+ "moveli r33, -27243\n"
+ "shl16insli r33, r33, 13585\n"
+ "shl16insli r33, r33, -1554\n"
+ "shl16insli r33, r33, 17682\n"
+ "{ clz r3, r33 ; fnop }\n"
+ "move %0, r3\n"
+ "move %1, r33\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_clz_Y0.c b/none/tests/tilegx/insn_test_clz_Y0.c
new file mode 100644
index 0000000..08ddb97
--- /dev/null
+++ b/none/tests/tilegx/insn_test_clz_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_clz_Y0.c
+//op=50
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4035b9e3ec473fc4, 0xa866c1efe28f7aab };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -10150\n"
+ "shl16insli r3, r3, -32553\n"
+ "shl16insli r3, r3, -18908\n"
+ "shl16insli r3, r3, 23364\n"
+ "moveli r33, -27243\n"
+ "shl16insli r33, r33, 13585\n"
+ "shl16insli r33, r33, -1554\n"
+ "shl16insli r33, r33, 17682\n"
+ "{ clz r3, r33 ; fnop ; ld r63, r54 }\n"
+ "move %0, r3\n"
+ "move %1, r33\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmoveqz_X0.c b/none/tests/tilegx/insn_test_cmoveqz_X0.c
new file mode 100644
index 0000000..dcf7904
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmoveqz_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmoveqz_X0.c
+//op=51
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x8e9efd621a0271c0, 0xe6fd0819cb489949 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r50, -2571\n"
+ "shl16insli r50, r50, 10073\n"
+ "shl16insli r50, r50, -8744\n"
+ "shl16insli r50, r50, 32440\n"
+ "moveli r28, -14135\n"
+ "shl16insli r28, r28, -9714\n"
+ "shl16insli r28, r28, -28553\n"
+ "shl16insli r28, r28, 1624\n"
+ "moveli r42, -6121\n"
+ "shl16insli r42, r42, -23936\n"
+ "shl16insli r42, r42, -6621\n"
+ "shl16insli r42, r42, -11778\n"
+ "{ cmoveqz r50, r28, r42 ; fnop }\n"
+ "move %0, r50\n"
+ "move %1, r28\n"
+ "move %2, r42\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmoveqz_Y0.c b/none/tests/tilegx/insn_test_cmoveqz_Y0.c
new file mode 100644
index 0000000..00677fb
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmoveqz_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmoveqz_Y0.c
+//op=51
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x8e9efd621a0271c0, 0xe6fd0819cb489949 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r50, -2571\n"
+ "shl16insli r50, r50, 10073\n"
+ "shl16insli r50, r50, -8744\n"
+ "shl16insli r50, r50, 32440\n"
+ "moveli r28, -14135\n"
+ "shl16insli r28, r28, -9714\n"
+ "shl16insli r28, r28, -28553\n"
+ "shl16insli r28, r28, 1624\n"
+ "moveli r42, -6121\n"
+ "shl16insli r42, r42, -23936\n"
+ "shl16insli r42, r42, -6621\n"
+ "shl16insli r42, r42, -11778\n"
+ "{ cmoveqz r50, r28, r42 ; fnop ; ld r63, r54 }\n"
+ "move %0, r50\n"
+ "move %1, r28\n"
+ "move %2, r42\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmovnez_X0.c b/none/tests/tilegx/insn_test_cmovnez_X0.c
new file mode 100644
index 0000000..b539654
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmovnez_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmovnez_X0.c
+//op=52
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9276743f21019b4e, 0x82cd9e74ccb2b602 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r8, -7642\n"
+ "shl16insli r8, r8, 2224\n"
+ "shl16insli r8, r8, 3897\n"
+ "shl16insli r8, r8, -23355\n"
+ "moveli r24, 12753\n"
+ "shl16insli r24, r24, 12718\n"
+ "shl16insli r24, r24, 27517\n"
+ "shl16insli r24, r24, -23530\n"
+ "moveli r27, -27396\n"
+ "shl16insli r27, r27, -8056\n"
+ "shl16insli r27, r27, 23879\n"
+ "shl16insli r27, r27, 14131\n"
+ "{ cmovnez r8, r24, r27 ; fnop }\n"
+ "move %0, r8\n"
+ "move %1, r24\n"
+ "move %2, r27\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmovnez_Y0.c b/none/tests/tilegx/insn_test_cmovnez_Y0.c
new file mode 100644
index 0000000..f792e11
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmovnez_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmovnez_Y0.c
+//op=52
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9276743f21019b4e, 0x82cd9e74ccb2b602 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r8, -7642\n"
+ "shl16insli r8, r8, 2224\n"
+ "shl16insli r8, r8, 3897\n"
+ "shl16insli r8, r8, -23355\n"
+ "moveli r24, 12753\n"
+ "shl16insli r24, r24, 12718\n"
+ "shl16insli r24, r24, 27517\n"
+ "shl16insli r24, r24, -23530\n"
+ "moveli r27, -27396\n"
+ "shl16insli r27, r27, -8056\n"
+ "shl16insli r27, r27, 23879\n"
+ "shl16insli r27, r27, 14131\n"
+ "{ cmovnez r8, r24, r27 ; fnop ; ld r63, r54 }\n"
+ "move %0, r8\n"
+ "move %1, r24\n"
+ "move %2, r27\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpeq_X0.c b/none/tests/tilegx/insn_test_cmpeq_X0.c
new file mode 100644
index 0000000..55d23a9
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpeq_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpeq_X0.c
+//op=53
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5fced320ec74ecd8, 0x28e0d2889b96db6d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r0, -26485\n"
+ "shl16insli r0, r0, 5854\n"
+ "shl16insli r0, r0, 20645\n"
+ "shl16insli r0, r0, 14858\n"
+ "moveli r9, 12048\n"
+ "shl16insli r9, r9, -17261\n"
+ "shl16insli r9, r9, -23773\n"
+ "shl16insli r9, r9, -13811\n"
+ "moveli r7, -30106\n"
+ "shl16insli r7, r7, 24510\n"
+ "shl16insli r7, r7, -6618\n"
+ "shl16insli r7, r7, 11033\n"
+ "{ cmpeq r0, r9, r7 ; fnop }\n"
+ "move %0, r0\n"
+ "move %1, r9\n"
+ "move %2, r7\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpeq_X1.c b/none/tests/tilegx/insn_test_cmpeq_X1.c
new file mode 100644
index 0000000..f47dc6e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpeq_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpeq_X1.c
+//op=53
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5fced320ec74ecd8, 0x28e0d2889b96db6d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r0, -26485\n"
+ "shl16insli r0, r0, 5854\n"
+ "shl16insli r0, r0, 20645\n"
+ "shl16insli r0, r0, 14858\n"
+ "moveli r9, 12048\n"
+ "shl16insli r9, r9, -17261\n"
+ "shl16insli r9, r9, -23773\n"
+ "shl16insli r9, r9, -13811\n"
+ "moveli r7, -30106\n"
+ "shl16insli r7, r7, 24510\n"
+ "shl16insli r7, r7, -6618\n"
+ "shl16insli r7, r7, 11033\n"
+ "{ fnop ; cmpeq r0, r9, r7 }\n"
+ "move %0, r0\n"
+ "move %1, r9\n"
+ "move %2, r7\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpeq_Y0.c b/none/tests/tilegx/insn_test_cmpeq_Y0.c
new file mode 100644
index 0000000..9fd2a78
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpeq_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpeq_Y0.c
+//op=53
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5fced320ec74ecd8, 0x28e0d2889b96db6d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r0, -26485\n"
+ "shl16insli r0, r0, 5854\n"
+ "shl16insli r0, r0, 20645\n"
+ "shl16insli r0, r0, 14858\n"
+ "moveli r9, 12048\n"
+ "shl16insli r9, r9, -17261\n"
+ "shl16insli r9, r9, -23773\n"
+ "shl16insli r9, r9, -13811\n"
+ "moveli r7, -30106\n"
+ "shl16insli r7, r7, 24510\n"
+ "shl16insli r7, r7, -6618\n"
+ "shl16insli r7, r7, 11033\n"
+ "{ cmpeq r0, r9, r7 ; fnop ; ld r63, r54 }\n"
+ "move %0, r0\n"
+ "move %1, r9\n"
+ "move %2, r7\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpeq_Y1.c b/none/tests/tilegx/insn_test_cmpeq_Y1.c
new file mode 100644
index 0000000..16f74c8
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpeq_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpeq_Y1.c
+//op=53
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5fced320ec74ecd8, 0x28e0d2889b96db6d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r0, -26485\n"
+ "shl16insli r0, r0, 5854\n"
+ "shl16insli r0, r0, 20645\n"
+ "shl16insli r0, r0, 14858\n"
+ "moveli r9, 12048\n"
+ "shl16insli r9, r9, -17261\n"
+ "shl16insli r9, r9, -23773\n"
+ "shl16insli r9, r9, -13811\n"
+ "moveli r7, -30106\n"
+ "shl16insli r7, r7, 24510\n"
+ "shl16insli r7, r7, -6618\n"
+ "shl16insli r7, r7, 11033\n"
+ "{ fnop ; cmpeq r0, r9, r7 ; ld r63, r54 }\n"
+ "move %0, r0\n"
+ "move %1, r9\n"
+ "move %2, r7\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpeqi_X0.c b/none/tests/tilegx/insn_test_cmpeqi_X0.c
new file mode 100644
index 0000000..015abf1
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpeqi_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_cmpeqi_X0.c
+//op=54
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc051e6bca12058e0, 0xd5875ac284be5010 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r49, -29338\n"
+ "shl16insli r49, r49, 4578\n"
+ "shl16insli r49, r49, -8168\n"
+ "shl16insli r49, r49, -29363\n"
+ "moveli r17, 8846\n"
+ "shl16insli r17, r17, -29053\n"
+ "shl16insli r17, r17, -18602\n"
+ "shl16insli r17, r17, 7817\n"
+ "{ cmpeqi r49, r17, -1 ; fnop }\n"
+ "move %0, r49\n"
+ "move %1, r17\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpeqi_X1.c b/none/tests/tilegx/insn_test_cmpeqi_X1.c
new file mode 100644
index 0000000..67a2536
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpeqi_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_cmpeqi_X1.c
+//op=54
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc051e6bca12058e0, 0xd5875ac284be5010 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r49, -29338\n"
+ "shl16insli r49, r49, 4578\n"
+ "shl16insli r49, r49, -8168\n"
+ "shl16insli r49, r49, -29363\n"
+ "moveli r17, 8846\n"
+ "shl16insli r17, r17, -29053\n"
+ "shl16insli r17, r17, -18602\n"
+ "shl16insli r17, r17, 7817\n"
+ "{ fnop ; cmpeqi r49, r17, -1 }\n"
+ "move %0, r49\n"
+ "move %1, r17\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpeqi_Y0.c b/none/tests/tilegx/insn_test_cmpeqi_Y0.c
new file mode 100644
index 0000000..0131ce1
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpeqi_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_cmpeqi_Y0.c
+//op=54
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc051e6bca12058e0, 0xd5875ac284be5010 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r49, -29338\n"
+ "shl16insli r49, r49, 4578\n"
+ "shl16insli r49, r49, -8168\n"
+ "shl16insli r49, r49, -29363\n"
+ "moveli r17, 8846\n"
+ "shl16insli r17, r17, -29053\n"
+ "shl16insli r17, r17, -18602\n"
+ "shl16insli r17, r17, 7817\n"
+ "{ cmpeqi r49, r17, -1 ; fnop ; ld r63, r54 }\n"
+ "move %0, r49\n"
+ "move %1, r17\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpeqi_Y1.c b/none/tests/tilegx/insn_test_cmpeqi_Y1.c
new file mode 100644
index 0000000..e810546
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpeqi_Y1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_cmpeqi_Y1.c
+//op=54
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc051e6bca12058e0, 0xd5875ac284be5010 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r49, -29338\n"
+ "shl16insli r49, r49, 4578\n"
+ "shl16insli r49, r49, -8168\n"
+ "shl16insli r49, r49, -29363\n"
+ "moveli r17, 8846\n"
+ "shl16insli r17, r17, -29053\n"
+ "shl16insli r17, r17, -18602\n"
+ "shl16insli r17, r17, 7817\n"
+ "{ fnop ; cmpeqi r49, r17, -1 ; ld r63, r54 }\n"
+ "move %0, r49\n"
+ "move %1, r17\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmples_X0.c b/none/tests/tilegx/insn_test_cmples_X0.c
new file mode 100644
index 0000000..462bdda
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmples_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmples_X0.c
+//op=57
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd4017cfe9fa6ebaa, 0x98d3e0700ab2b8d9 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, -26683\n"
+ "shl16insli r34, r34, 3096\n"
+ "shl16insli r34, r34, 25335\n"
+ "shl16insli r34, r34, 30983\n"
+ "moveli r26, -7486\n"
+ "shl16insli r26, r26, 24081\n"
+ "shl16insli r26, r26, 2997\n"
+ "shl16insli r26, r26, -26298\n"
+ "moveli r32, -10199\n"
+ "shl16insli r32, r32, -13638\n"
+ "shl16insli r32, r32, 17992\n"
+ "shl16insli r32, r32, -16829\n"
+ "{ cmples r34, r26, r32 ; fnop }\n"
+ "move %0, r34\n"
+ "move %1, r26\n"
+ "move %2, r32\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmples_X1.c b/none/tests/tilegx/insn_test_cmples_X1.c
new file mode 100644
index 0000000..08525d0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmples_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmples_X1.c
+//op=57
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd4017cfe9fa6ebaa, 0x98d3e0700ab2b8d9 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, -26683\n"
+ "shl16insli r34, r34, 3096\n"
+ "shl16insli r34, r34, 25335\n"
+ "shl16insli r34, r34, 30983\n"
+ "moveli r26, -7486\n"
+ "shl16insli r26, r26, 24081\n"
+ "shl16insli r26, r26, 2997\n"
+ "shl16insli r26, r26, -26298\n"
+ "moveli r32, -10199\n"
+ "shl16insli r32, r32, -13638\n"
+ "shl16insli r32, r32, 17992\n"
+ "shl16insli r32, r32, -16829\n"
+ "{ fnop ; cmples r34, r26, r32 }\n"
+ "move %0, r34\n"
+ "move %1, r26\n"
+ "move %2, r32\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmples_Y0.c b/none/tests/tilegx/insn_test_cmples_Y0.c
new file mode 100644
index 0000000..be3865e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmples_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmples_Y0.c
+//op=57
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd4017cfe9fa6ebaa, 0x98d3e0700ab2b8d9 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, -26683\n"
+ "shl16insli r34, r34, 3096\n"
+ "shl16insli r34, r34, 25335\n"
+ "shl16insli r34, r34, 30983\n"
+ "moveli r26, -7486\n"
+ "shl16insli r26, r26, 24081\n"
+ "shl16insli r26, r26, 2997\n"
+ "shl16insli r26, r26, -26298\n"
+ "moveli r32, -10199\n"
+ "shl16insli r32, r32, -13638\n"
+ "shl16insli r32, r32, 17992\n"
+ "shl16insli r32, r32, -16829\n"
+ "{ cmples r34, r26, r32 ; fnop ; ld r63, r54 }\n"
+ "move %0, r34\n"
+ "move %1, r26\n"
+ "move %2, r32\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmples_Y1.c b/none/tests/tilegx/insn_test_cmples_Y1.c
new file mode 100644
index 0000000..dba3c58
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmples_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmples_Y1.c
+//op=57
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd4017cfe9fa6ebaa, 0x98d3e0700ab2b8d9 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, -26683\n"
+ "shl16insli r34, r34, 3096\n"
+ "shl16insli r34, r34, 25335\n"
+ "shl16insli r34, r34, 30983\n"
+ "moveli r26, -7486\n"
+ "shl16insli r26, r26, 24081\n"
+ "shl16insli r26, r26, 2997\n"
+ "shl16insli r26, r26, -26298\n"
+ "moveli r32, -10199\n"
+ "shl16insli r32, r32, -13638\n"
+ "shl16insli r32, r32, 17992\n"
+ "shl16insli r32, r32, -16829\n"
+ "{ fnop ; cmples r34, r26, r32 ; ld r63, r54 }\n"
+ "move %0, r34\n"
+ "move %1, r26\n"
+ "move %2, r32\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpleu_X0.c b/none/tests/tilegx/insn_test_cmpleu_X0.c
new file mode 100644
index 0000000..0c3866f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpleu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpleu_X0.c
+//op=58
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9a968c4e2652e151, 0x6fd6d80e8b18c9bb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, -12524\n"
+ "shl16insli r16, r16, -16020\n"
+ "shl16insli r16, r16, -28698\n"
+ "shl16insli r16, r16, -10230\n"
+ "moveli r20, -25048\n"
+ "shl16insli r20, r20, -26391\n"
+ "shl16insli r20, r20, -12179\n"
+ "shl16insli r20, r20, -11222\n"
+ "moveli r10, -656\n"
+ "shl16insli r10, r10, 236\n"
+ "shl16insli r10, r10, -4273\n"
+ "shl16insli r10, r10, -1226\n"
+ "{ cmpleu r16, r20, r10 ; fnop }\n"
+ "move %0, r16\n"
+ "move %1, r20\n"
+ "move %2, r10\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpleu_X1.c b/none/tests/tilegx/insn_test_cmpleu_X1.c
new file mode 100644
index 0000000..b78705a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpleu_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpleu_X1.c
+//op=58
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9a968c4e2652e151, 0x6fd6d80e8b18c9bb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, -12524\n"
+ "shl16insli r16, r16, -16020\n"
+ "shl16insli r16, r16, -28698\n"
+ "shl16insli r16, r16, -10230\n"
+ "moveli r20, -25048\n"
+ "shl16insli r20, r20, -26391\n"
+ "shl16insli r20, r20, -12179\n"
+ "shl16insli r20, r20, -11222\n"
+ "moveli r10, -656\n"
+ "shl16insli r10, r10, 236\n"
+ "shl16insli r10, r10, -4273\n"
+ "shl16insli r10, r10, -1226\n"
+ "{ fnop ; cmpleu r16, r20, r10 }\n"
+ "move %0, r16\n"
+ "move %1, r20\n"
+ "move %2, r10\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpleu_Y0.c b/none/tests/tilegx/insn_test_cmpleu_Y0.c
new file mode 100644
index 0000000..a454205
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpleu_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpleu_Y0.c
+//op=58
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9a968c4e2652e151, 0x6fd6d80e8b18c9bb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, -12524\n"
+ "shl16insli r16, r16, -16020\n"
+ "shl16insli r16, r16, -28698\n"
+ "shl16insli r16, r16, -10230\n"
+ "moveli r20, -25048\n"
+ "shl16insli r20, r20, -26391\n"
+ "shl16insli r20, r20, -12179\n"
+ "shl16insli r20, r20, -11222\n"
+ "moveli r10, -656\n"
+ "shl16insli r10, r10, 236\n"
+ "shl16insli r10, r10, -4273\n"
+ "shl16insli r10, r10, -1226\n"
+ "{ cmpleu r16, r20, r10 ; fnop ; ld r63, r54 }\n"
+ "move %0, r16\n"
+ "move %1, r20\n"
+ "move %2, r10\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpleu_Y1.c b/none/tests/tilegx/insn_test_cmpleu_Y1.c
new file mode 100644
index 0000000..00a0fa7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpleu_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpleu_Y1.c
+//op=58
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9a968c4e2652e151, 0x6fd6d80e8b18c9bb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, -12524\n"
+ "shl16insli r16, r16, -16020\n"
+ "shl16insli r16, r16, -28698\n"
+ "shl16insli r16, r16, -10230\n"
+ "moveli r20, -25048\n"
+ "shl16insli r20, r20, -26391\n"
+ "shl16insli r20, r20, -12179\n"
+ "shl16insli r20, r20, -11222\n"
+ "moveli r10, -656\n"
+ "shl16insli r10, r10, 236\n"
+ "shl16insli r10, r10, -4273\n"
+ "shl16insli r10, r10, -1226\n"
+ "{ fnop ; cmpleu r16, r20, r10 ; ld r63, r54 }\n"
+ "move %0, r16\n"
+ "move %1, r20\n"
+ "move %2, r10\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmplts_X0.c b/none/tests/tilegx/insn_test_cmplts_X0.c
new file mode 100644
index 0000000..f7302a7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmplts_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmplts_X0.c
+//op=59
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xdfe94ab09fee22a5, 0x379c002b0119bd52 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -11368\n"
+ "shl16insli r3, r3, -9764\n"
+ "shl16insli r3, r3, -880\n"
+ "shl16insli r3, r3, -31125\n"
+ "moveli r31, -25744\n"
+ "shl16insli r31, r31, -23478\n"
+ "shl16insli r31, r31, -21167\n"
+ "shl16insli r31, r31, -9956\n"
+ "moveli r9, 19348\n"
+ "shl16insli r9, r9, 13914\n"
+ "shl16insli r9, r9, -27396\n"
+ "shl16insli r9, r9, -31879\n"
+ "{ cmplts r3, r31, r9 ; fnop }\n"
+ "move %0, r3\n"
+ "move %1, r31\n"
+ "move %2, r9\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmplts_X1.c b/none/tests/tilegx/insn_test_cmplts_X1.c
new file mode 100644
index 0000000..e4eafba
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmplts_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmplts_X1.c
+//op=59
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xdfe94ab09fee22a5, 0x379c002b0119bd52 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -11368\n"
+ "shl16insli r3, r3, -9764\n"
+ "shl16insli r3, r3, -880\n"
+ "shl16insli r3, r3, -31125\n"
+ "moveli r31, -25744\n"
+ "shl16insli r31, r31, -23478\n"
+ "shl16insli r31, r31, -21167\n"
+ "shl16insli r31, r31, -9956\n"
+ "moveli r9, 19348\n"
+ "shl16insli r9, r9, 13914\n"
+ "shl16insli r9, r9, -27396\n"
+ "shl16insli r9, r9, -31879\n"
+ "{ fnop ; cmplts r3, r31, r9 }\n"
+ "move %0, r3\n"
+ "move %1, r31\n"
+ "move %2, r9\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmplts_Y0.c b/none/tests/tilegx/insn_test_cmplts_Y0.c
new file mode 100644
index 0000000..b5d1b6b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmplts_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmplts_Y0.c
+//op=59
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xdfe94ab09fee22a5, 0x379c002b0119bd52 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -11368\n"
+ "shl16insli r3, r3, -9764\n"
+ "shl16insli r3, r3, -880\n"
+ "shl16insli r3, r3, -31125\n"
+ "moveli r31, -25744\n"
+ "shl16insli r31, r31, -23478\n"
+ "shl16insli r31, r31, -21167\n"
+ "shl16insli r31, r31, -9956\n"
+ "moveli r9, 19348\n"
+ "shl16insli r9, r9, 13914\n"
+ "shl16insli r9, r9, -27396\n"
+ "shl16insli r9, r9, -31879\n"
+ "{ cmplts r3, r31, r9 ; fnop ; ld r63, r54 }\n"
+ "move %0, r3\n"
+ "move %1, r31\n"
+ "move %2, r9\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmplts_Y1.c b/none/tests/tilegx/insn_test_cmplts_Y1.c
new file mode 100644
index 0000000..341c09d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmplts_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmplts_Y1.c
+//op=59
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xdfe94ab09fee22a5, 0x379c002b0119bd52 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -11368\n"
+ "shl16insli r3, r3, -9764\n"
+ "shl16insli r3, r3, -880\n"
+ "shl16insli r3, r3, -31125\n"
+ "moveli r31, -25744\n"
+ "shl16insli r31, r31, -23478\n"
+ "shl16insli r31, r31, -21167\n"
+ "shl16insli r31, r31, -9956\n"
+ "moveli r9, 19348\n"
+ "shl16insli r9, r9, 13914\n"
+ "shl16insli r9, r9, -27396\n"
+ "shl16insli r9, r9, -31879\n"
+ "{ fnop ; cmplts r3, r31, r9 ; ld r63, r54 }\n"
+ "move %0, r3\n"
+ "move %1, r31\n"
+ "move %2, r9\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpltsi_X0.c b/none/tests/tilegx/insn_test_cmpltsi_X0.c
new file mode 100644
index 0000000..69b6836
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpltsi_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_cmpltsi_X0.c
+//op=60
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa702a184ea8a31f7, 0xd5c03dafaeab4e7e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r4, -686\n"
+ "shl16insli r4, r4, -26042\n"
+ "shl16insli r4, r4, 8081\n"
+ "shl16insli r4, r4, -25541\n"
+ "moveli r24, -12028\n"
+ "shl16insli r24, r24, -6402\n"
+ "shl16insli r24, r24, -9261\n"
+ "shl16insli r24, r24, 9978\n"
+ "{ cmpltsi r4, r24, -23 ; fnop }\n"
+ "move %0, r4\n"
+ "move %1, r24\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpltsi_X1.c b/none/tests/tilegx/insn_test_cmpltsi_X1.c
new file mode 100644
index 0000000..37de364
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpltsi_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_cmpltsi_X1.c
+//op=60
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa702a184ea8a31f7, 0xd5c03dafaeab4e7e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r4, -686\n"
+ "shl16insli r4, r4, -26042\n"
+ "shl16insli r4, r4, 8081\n"
+ "shl16insli r4, r4, -25541\n"
+ "moveli r24, -12028\n"
+ "shl16insli r24, r24, -6402\n"
+ "shl16insli r24, r24, -9261\n"
+ "shl16insli r24, r24, 9978\n"
+ "{ fnop ; cmpltsi r4, r24, -23 }\n"
+ "move %0, r4\n"
+ "move %1, r24\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpltsi_Y0.c b/none/tests/tilegx/insn_test_cmpltsi_Y0.c
new file mode 100644
index 0000000..74e9a2e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpltsi_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_cmpltsi_Y0.c
+//op=60
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa702a184ea8a31f7, 0xd5c03dafaeab4e7e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r4, -686\n"
+ "shl16insli r4, r4, -26042\n"
+ "shl16insli r4, r4, 8081\n"
+ "shl16insli r4, r4, -25541\n"
+ "moveli r24, -12028\n"
+ "shl16insli r24, r24, -6402\n"
+ "shl16insli r24, r24, -9261\n"
+ "shl16insli r24, r24, 9978\n"
+ "{ cmpltsi r4, r24, -23 ; fnop ; ld r63, r54 }\n"
+ "move %0, r4\n"
+ "move %1, r24\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpltsi_Y1.c b/none/tests/tilegx/insn_test_cmpltsi_Y1.c
new file mode 100644
index 0000000..a1e3d03
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpltsi_Y1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_cmpltsi_Y1.c
+//op=60
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa702a184ea8a31f7, 0xd5c03dafaeab4e7e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r4, -686\n"
+ "shl16insli r4, r4, -26042\n"
+ "shl16insli r4, r4, 8081\n"
+ "shl16insli r4, r4, -25541\n"
+ "moveli r24, -12028\n"
+ "shl16insli r24, r24, -6402\n"
+ "shl16insli r24, r24, -9261\n"
+ "shl16insli r24, r24, 9978\n"
+ "{ fnop ; cmpltsi r4, r24, -23 ; ld r63, r54 }\n"
+ "move %0, r4\n"
+ "move %1, r24\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpltu_X0.c b/none/tests/tilegx/insn_test_cmpltu_X0.c
new file mode 100644
index 0000000..e680a68
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpltu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpltu_X0.c
+//op=61
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x26836d784e440ab7, 0xef3b92483b066295 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, -20987\n"
+ "shl16insli r13, r13, 15474\n"
+ "shl16insli r13, r13, 14956\n"
+ "shl16insli r13, r13, -29129\n"
+ "moveli r6, 6095\n"
+ "shl16insli r6, r6, -319\n"
+ "shl16insli r6, r6, -21787\n"
+ "shl16insli r6, r6, -21356\n"
+ "moveli r35, 8260\n"
+ "shl16insli r35, r35, -7206\n"
+ "shl16insli r35, r35, -24567\n"
+ "shl16insli r35, r35, -8840\n"
+ "{ cmpltu r13, r6, r35 ; fnop }\n"
+ "move %0, r13\n"
+ "move %1, r6\n"
+ "move %2, r35\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpltu_X1.c b/none/tests/tilegx/insn_test_cmpltu_X1.c
new file mode 100644
index 0000000..355764d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpltu_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpltu_X1.c
+//op=61
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x26836d784e440ab7, 0xef3b92483b066295 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, -20987\n"
+ "shl16insli r13, r13, 15474\n"
+ "shl16insli r13, r13, 14956\n"
+ "shl16insli r13, r13, -29129\n"
+ "moveli r6, 6095\n"
+ "shl16insli r6, r6, -319\n"
+ "shl16insli r6, r6, -21787\n"
+ "shl16insli r6, r6, -21356\n"
+ "moveli r35, 8260\n"
+ "shl16insli r35, r35, -7206\n"
+ "shl16insli r35, r35, -24567\n"
+ "shl16insli r35, r35, -8840\n"
+ "{ fnop ; cmpltu r13, r6, r35 }\n"
+ "move %0, r13\n"
+ "move %1, r6\n"
+ "move %2, r35\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpltu_Y0.c b/none/tests/tilegx/insn_test_cmpltu_Y0.c
new file mode 100644
index 0000000..79a73d9
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpltu_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpltu_Y0.c
+//op=61
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x26836d784e440ab7, 0xef3b92483b066295 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, -20987\n"
+ "shl16insli r13, r13, 15474\n"
+ "shl16insli r13, r13, 14956\n"
+ "shl16insli r13, r13, -29129\n"
+ "moveli r6, 6095\n"
+ "shl16insli r6, r6, -319\n"
+ "shl16insli r6, r6, -21787\n"
+ "shl16insli r6, r6, -21356\n"
+ "moveli r35, 8260\n"
+ "shl16insli r35, r35, -7206\n"
+ "shl16insli r35, r35, -24567\n"
+ "shl16insli r35, r35, -8840\n"
+ "{ cmpltu r13, r6, r35 ; fnop ; ld r63, r54 }\n"
+ "move %0, r13\n"
+ "move %1, r6\n"
+ "move %2, r35\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpltu_Y1.c b/none/tests/tilegx/insn_test_cmpltu_Y1.c
new file mode 100644
index 0000000..4169565
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpltu_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpltu_Y1.c
+//op=61
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x26836d784e440ab7, 0xef3b92483b066295 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, -20987\n"
+ "shl16insli r13, r13, 15474\n"
+ "shl16insli r13, r13, 14956\n"
+ "shl16insli r13, r13, -29129\n"
+ "moveli r6, 6095\n"
+ "shl16insli r6, r6, -319\n"
+ "shl16insli r6, r6, -21787\n"
+ "shl16insli r6, r6, -21356\n"
+ "moveli r35, 8260\n"
+ "shl16insli r35, r35, -7206\n"
+ "shl16insli r35, r35, -24567\n"
+ "shl16insli r35, r35, -8840\n"
+ "{ fnop ; cmpltu r13, r6, r35 ; ld r63, r54 }\n"
+ "move %0, r13\n"
+ "move %1, r6\n"
+ "move %2, r35\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpltui_X0.c b/none/tests/tilegx/insn_test_cmpltui_X0.c
new file mode 100644
index 0000000..0639bea
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpltui_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_cmpltui_X0.c
+//op=62
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6a0cb98ab56a8e60, 0xa3f9a29247d48ea1 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r30, 27938\n"
+ "shl16insli r30, r30, -31883\n"
+ "shl16insli r30, r30, -15298\n"
+ "shl16insli r30, r30, 10238\n"
+ "moveli r29, -25838\n"
+ "shl16insli r29, r29, 23398\n"
+ "shl16insli r29, r29, 16827\n"
+ "shl16insli r29, r29, -24775\n"
+ "{ cmpltui r30, r29, 114 ; fnop }\n"
+ "move %0, r30\n"
+ "move %1, r29\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpltui_X1.c b/none/tests/tilegx/insn_test_cmpltui_X1.c
new file mode 100644
index 0000000..24e4151
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpltui_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_cmpltui_X1.c
+//op=62
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6a0cb98ab56a8e60, 0xa3f9a29247d48ea1 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r30, 27938\n"
+ "shl16insli r30, r30, -31883\n"
+ "shl16insli r30, r30, -15298\n"
+ "shl16insli r30, r30, 10238\n"
+ "moveli r29, -25838\n"
+ "shl16insli r29, r29, 23398\n"
+ "shl16insli r29, r29, 16827\n"
+ "shl16insli r29, r29, -24775\n"
+ "{ fnop ; cmpltui r30, r29, 114 }\n"
+ "move %0, r30\n"
+ "move %1, r29\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpne_X0.c b/none/tests/tilegx/insn_test_cmpne_X0.c
new file mode 100644
index 0000000..79f08c1
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpne_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpne_X0.c
+//op=63
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x11b59d6276787136, 0x78c2286b07e86b55 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r45, -19189\n"
+ "shl16insli r45, r45, 6578\n"
+ "shl16insli r45, r45, 17580\n"
+ "shl16insli r45, r45, 32436\n"
+ "moveli r36, -31697\n"
+ "shl16insli r36, r36, 8179\n"
+ "shl16insli r36, r36, -19147\n"
+ "shl16insli r36, r36, -16129\n"
+ "moveli r19, -12252\n"
+ "shl16insli r19, r19, 5860\n"
+ "shl16insli r19, r19, 15129\n"
+ "shl16insli r19, r19, -15375\n"
+ "{ cmpne r45, r36, r19 ; fnop }\n"
+ "move %0, r45\n"
+ "move %1, r36\n"
+ "move %2, r19\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpne_X1.c b/none/tests/tilegx/insn_test_cmpne_X1.c
new file mode 100644
index 0000000..469a95d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpne_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpne_X1.c
+//op=63
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x11b59d6276787136, 0x78c2286b07e86b55 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r45, -19189\n"
+ "shl16insli r45, r45, 6578\n"
+ "shl16insli r45, r45, 17580\n"
+ "shl16insli r45, r45, 32436\n"
+ "moveli r36, -31697\n"
+ "shl16insli r36, r36, 8179\n"
+ "shl16insli r36, r36, -19147\n"
+ "shl16insli r36, r36, -16129\n"
+ "moveli r19, -12252\n"
+ "shl16insli r19, r19, 5860\n"
+ "shl16insli r19, r19, 15129\n"
+ "shl16insli r19, r19, -15375\n"
+ "{ fnop ; cmpne r45, r36, r19 }\n"
+ "move %0, r45\n"
+ "move %1, r36\n"
+ "move %2, r19\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpne_Y0.c b/none/tests/tilegx/insn_test_cmpne_Y0.c
new file mode 100644
index 0000000..731941b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpne_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpne_Y0.c
+//op=63
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x11b59d6276787136, 0x78c2286b07e86b55 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r45, -19189\n"
+ "shl16insli r45, r45, 6578\n"
+ "shl16insli r45, r45, 17580\n"
+ "shl16insli r45, r45, 32436\n"
+ "moveli r36, -31697\n"
+ "shl16insli r36, r36, 8179\n"
+ "shl16insli r36, r36, -19147\n"
+ "shl16insli r36, r36, -16129\n"
+ "moveli r19, -12252\n"
+ "shl16insli r19, r19, 5860\n"
+ "shl16insli r19, r19, 15129\n"
+ "shl16insli r19, r19, -15375\n"
+ "{ cmpne r45, r36, r19 ; fnop ; ld r63, r54 }\n"
+ "move %0, r45\n"
+ "move %1, r36\n"
+ "move %2, r19\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmpne_Y1.c b/none/tests/tilegx/insn_test_cmpne_Y1.c
new file mode 100644
index 0000000..70a3ced
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmpne_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmpne_Y1.c
+//op=63
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x11b59d6276787136, 0x78c2286b07e86b55 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r45, -19189\n"
+ "shl16insli r45, r45, 6578\n"
+ "shl16insli r45, r45, 17580\n"
+ "shl16insli r45, r45, 32436\n"
+ "moveli r36, -31697\n"
+ "shl16insli r36, r36, 8179\n"
+ "shl16insli r36, r36, -19147\n"
+ "shl16insli r36, r36, -16129\n"
+ "moveli r19, -12252\n"
+ "shl16insli r19, r19, 5860\n"
+ "shl16insli r19, r19, 15129\n"
+ "shl16insli r19, r19, -15375\n"
+ "{ fnop ; cmpne r45, r36, r19 ; ld r63, r54 }\n"
+ "move %0, r45\n"
+ "move %1, r36\n"
+ "move %2, r19\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmul_X0.c b/none/tests/tilegx/insn_test_cmul_X0.c
new file mode 100644
index 0000000..e2deb0c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmul_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmul_X0.c
+//op=64
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x411d3fc3fc916064, 0x4eb70a2cb8e0ad00 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r35, -12554\n"
+ "shl16insli r35, r35, 3660\n"
+ "shl16insli r35, r35, -31312\n"
+ "shl16insli r35, r35, 5700\n"
+ "moveli r21, 31847\n"
+ "shl16insli r21, r21, 16845\n"
+ "shl16insli r21, r21, -32108\n"
+ "shl16insli r21, r21, -3821\n"
+ "moveli r42, -5570\n"
+ "shl16insli r42, r42, -29385\n"
+ "shl16insli r42, r42, -18769\n"
+ "shl16insli r42, r42, -2309\n"
+ "{ cmul r35, r21, r42 ; fnop }\n"
+ "move %0, r35\n"
+ "move %1, r21\n"
+ "move %2, r42\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmula_X0.c b/none/tests/tilegx/insn_test_cmula_X0.c
new file mode 100644
index 0000000..aed073f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmula_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmula_X0.c
+//op=65
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x553c16d3559d1cee, 0xe53c5e867b2c2d0e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r35, -20478\n"
+ "shl16insli r35, r35, -22564\n"
+ "shl16insli r35, r35, 7251\n"
+ "shl16insli r35, r35, -29417\n"
+ "moveli r35, 23890\n"
+ "shl16insli r35, r35, 28671\n"
+ "shl16insli r35, r35, -167\n"
+ "shl16insli r35, r35, 16603\n"
+ "moveli r5, 20445\n"
+ "shl16insli r5, r5, -17976\n"
+ "shl16insli r5, r5, -29438\n"
+ "shl16insli r5, r5, -12912\n"
+ "{ cmula r35, r35, r5 ; fnop }\n"
+ "move %0, r35\n"
+ "move %1, r35\n"
+ "move %2, r5\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmulaf_X0.c b/none/tests/tilegx/insn_test_cmulaf_X0.c
new file mode 100644
index 0000000..611fc6d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmulaf_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmulaf_X0.c
+//op=66
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x386e67ed7b089fc9, 0x159952beef1e2d8e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r17, 12406\n"
+ "shl16insli r17, r17, -7608\n"
+ "shl16insli r17, r17, -24144\n"
+ "shl16insli r17, r17, 13065\n"
+ "moveli r20, 14943\n"
+ "shl16insli r20, r20, -18119\n"
+ "shl16insli r20, r20, -10933\n"
+ "shl16insli r20, r20, 517\n"
+ "moveli r30, 26677\n"
+ "shl16insli r30, r30, 32003\n"
+ "shl16insli r30, r30, 16745\n"
+ "shl16insli r30, r30, -29543\n"
+ "{ cmulaf r17, r20, r30 ; fnop }\n"
+ "move %0, r17\n"
+ "move %1, r20\n"
+ "move %2, r30\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmulf_X0.c b/none/tests/tilegx/insn_test_cmulf_X0.c
new file mode 100644
index 0000000..ff0a7fa
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmulf_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmulf_X0.c
+//op=67
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x20a35a283e09bcf3, 0xf918ceb605460b8e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r47, 12090\n"
+ "shl16insli r47, r47, -15392\n"
+ "shl16insli r47, r47, 393\n"
+ "shl16insli r47, r47, 9111\n"
+ "moveli r2, 22012\n"
+ "shl16insli r2, r2, 18909\n"
+ "shl16insli r2, r2, 17994\n"
+ "shl16insli r2, r2, -10137\n"
+ "moveli r46, 30081\n"
+ "shl16insli r46, r46, 2888\n"
+ "shl16insli r46, r46, 17535\n"
+ "shl16insli r46, r46, -29480\n"
+ "{ cmulf r47, r2, r46 ; fnop }\n"
+ "move %0, r47\n"
+ "move %1, r2\n"
+ "move %2, r46\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmulfr_X0.c b/none/tests/tilegx/insn_test_cmulfr_X0.c
new file mode 100644
index 0000000..12c83f7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmulfr_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmulfr_X0.c
+//op=68
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x820d15cd622148e4, 0x7eda32ada2f5060 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r39, 9587\n"
+ "shl16insli r39, r39, 15755\n"
+ "shl16insli r39, r39, 24004\n"
+ "shl16insli r39, r39, 30644\n"
+ "moveli r16, -6121\n"
+ "shl16insli r16, r16, -23936\n"
+ "shl16insli r16, r16, -6621\n"
+ "shl16insli r16, r16, -11778\n"
+ "moveli r25, 25551\n"
+ "shl16insli r25, r25, 28722\n"
+ "shl16insli r25, r25, -26847\n"
+ "shl16insli r25, r25, 5345\n"
+ "{ cmulfr r39, r16, r25 ; fnop }\n"
+ "move %0, r39\n"
+ "move %1, r16\n"
+ "move %2, r25\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmulh_X0.c b/none/tests/tilegx/insn_test_cmulh_X0.c
new file mode 100644
index 0000000..941cc33
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmulh_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmulh_X0.c
+//op=69
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4070076dbab015ca, 0x741405116e136ce3 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r26, 30607\n"
+ "shl16insli r26, r26, 12143\n"
+ "shl16insli r26, r26, 6105\n"
+ "shl16insli r26, r26, 59\n"
+ "moveli r3, -10033\n"
+ "shl16insli r3, r3, 14176\n"
+ "shl16insli r3, r3, -28670\n"
+ "shl16insli r3, r3, 13765\n"
+ "moveli r10, 8165\n"
+ "shl16insli r10, r10, 18793\n"
+ "shl16insli r10, r10, -22214\n"
+ "shl16insli r10, r10, 5498\n"
+ "{ cmulh r26, r3, r10 ; fnop }\n"
+ "move %0, r26\n"
+ "move %1, r3\n"
+ "move %2, r10\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_cmulhr_X0.c b/none/tests/tilegx/insn_test_cmulhr_X0.c
new file mode 100644
index 0000000..2cbfe0c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_cmulhr_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_cmulhr_X0.c
+//op=70
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x3f45dbe8d3bddf1e, 0x6873aadf3e763127 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r49, 17759\n"
+ "shl16insli r49, r49, -31178\n"
+ "shl16insli r49, r49, -28954\n"
+ "shl16insli r49, r49, -24129\n"
+ "moveli r30, 15980\n"
+ "shl16insli r30, r30, 6185\n"
+ "shl16insli r30, r30, -3610\n"
+ "shl16insli r30, r30, -10263\n"
+ "moveli r31, 26063\n"
+ "shl16insli r31, r31, 27563\n"
+ "shl16insli r31, r31, 24059\n"
+ "shl16insli r31, r31, -1753\n"
+ "{ cmulhr r49, r30, r31 ; fnop }\n"
+ "move %0, r49\n"
+ "move %1, r30\n"
+ "move %2, r31\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_crc32_32_X0.c b/none/tests/tilegx/insn_test_crc32_32_X0.c
new file mode 100644
index 0000000..a3a9a78
--- /dev/null
+++ b/none/tests/tilegx/insn_test_crc32_32_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_crc32_32_X0.c
+//op=71
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5797c115d06a021e, 0xcec6c9aa9564502a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r21, -22875\n"
+ "shl16insli r21, r21, -32077\n"
+ "shl16insli r21, r21, -9073\n"
+ "shl16insli r21, r21, 28291\n"
+ "moveli r18, -19329\n"
+ "shl16insli r18, r18, -4231\n"
+ "shl16insli r18, r18, 22518\n"
+ "shl16insli r18, r18, 1958\n"
+ "moveli r23, -31981\n"
+ "shl16insli r23, r23, -84\n"
+ "shl16insli r23, r23, 2678\n"
+ "shl16insli r23, r23, 4570\n"
+ "{ crc32_32 r21, r18, r23 ; fnop }\n"
+ "move %0, r21\n"
+ "move %1, r18\n"
+ "move %2, r23\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_crc32_8_X0.c b/none/tests/tilegx/insn_test_crc32_8_X0.c
new file mode 100644
index 0000000..f1f3596
--- /dev/null
+++ b/none/tests/tilegx/insn_test_crc32_8_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_crc32_8_X0.c
+//op=72
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x48fd1654a7e669f7, 0x3c14fa8c76bb7fe3 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, -1456\n"
+ "shl16insli r34, r34, -8976\n"
+ "shl16insli r34, r34, -20412\n"
+ "shl16insli r34, r34, -10854\n"
+ "moveli r38, -32379\n"
+ "shl16insli r38, r38, -17242\n"
+ "shl16insli r38, r38, -8818\n"
+ "shl16insli r38, r38, 7579\n"
+ "moveli r45, 26010\n"
+ "shl16insli r45, r45, -10170\n"
+ "shl16insli r45, r45, -10239\n"
+ "shl16insli r45, r45, -24168\n"
+ "{ crc32_8 r34, r38, r45 ; fnop }\n"
+ "move %0, r34\n"
+ "move %1, r38\n"
+ "move %2, r45\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ctz_X0.c b/none/tests/tilegx/insn_test_ctz_X0.c
new file mode 100644
index 0000000..1c100f1
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ctz_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_ctz_X0.c
+//op=73
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xea70c8b3ffd336c3, 0x4dcbb13e69f7210c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r20, 21188\n"
+ "shl16insli r20, r20, -26615\n"
+ "shl16insli r20, r20, -6842\n"
+ "shl16insli r20, r20, 23302\n"
+ "moveli r15, -28043\n"
+ "shl16insli r15, r15, -17799\n"
+ "shl16insli r15, r15, -27340\n"
+ "shl16insli r15, r15, -22535\n"
+ "{ ctz r20, r15 ; fnop }\n"
+ "move %0, r20\n"
+ "move %1, r15\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ctz_Y0.c b/none/tests/tilegx/insn_test_ctz_Y0.c
new file mode 100644
index 0000000..9c0fbf9
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ctz_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_ctz_Y0.c
+//op=73
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xea70c8b3ffd336c3, 0x4dcbb13e69f7210c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r20, 21188\n"
+ "shl16insli r20, r20, -26615\n"
+ "shl16insli r20, r20, -6842\n"
+ "shl16insli r20, r20, 23302\n"
+ "moveli r15, -28043\n"
+ "shl16insli r15, r15, -17799\n"
+ "shl16insli r15, r15, -27340\n"
+ "shl16insli r15, r15, -22535\n"
+ "{ ctz r20, r15 ; fnop ; ld r63, r54 }\n"
+ "move %0, r20\n"
+ "move %1, r15\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_dblalign2_X0.c b/none/tests/tilegx/insn_test_dblalign2_X0.c
new file mode 100644
index 0000000..819891d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_dblalign2_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_dblalign2_X0.c
+//op=75
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x52148e33ddfabfa8, 0xc6860cbdb069dbcf };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r39, -27243\n"
+ "shl16insli r39, r39, 13585\n"
+ "shl16insli r39, r39, -1554\n"
+ "shl16insli r39, r39, 17682\n"
+ "moveli r19, -3548\n"
+ "shl16insli r19, r19, -18819\n"
+ "shl16insli r19, r19, -5126\n"
+ "shl16insli r19, r19, -7819\n"
+ "moveli r48, 10648\n"
+ "shl16insli r48, r48, -21072\n"
+ "shl16insli r48, r48, -30644\n"
+ "shl16insli r48, r48, -24292\n"
+ "{ dblalign2 r39, r19, r48 ; fnop }\n"
+ "move %0, r39\n"
+ "move %1, r19\n"
+ "move %2, r48\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_dblalign2_X1.c b/none/tests/tilegx/insn_test_dblalign2_X1.c
new file mode 100644
index 0000000..e3b7a13
--- /dev/null
+++ b/none/tests/tilegx/insn_test_dblalign2_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_dblalign2_X1.c
+//op=75
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x52148e33ddfabfa8, 0xc6860cbdb069dbcf };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r39, -27243\n"
+ "shl16insli r39, r39, 13585\n"
+ "shl16insli r39, r39, -1554\n"
+ "shl16insli r39, r39, 17682\n"
+ "moveli r19, -3548\n"
+ "shl16insli r19, r19, -18819\n"
+ "shl16insli r19, r19, -5126\n"
+ "shl16insli r19, r19, -7819\n"
+ "moveli r48, 10648\n"
+ "shl16insli r48, r48, -21072\n"
+ "shl16insli r48, r48, -30644\n"
+ "shl16insli r48, r48, -24292\n"
+ "{ fnop ; dblalign2 r39, r19, r48 }\n"
+ "move %0, r39\n"
+ "move %1, r19\n"
+ "move %2, r48\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_dblalign4_X0.c b/none/tests/tilegx/insn_test_dblalign4_X0.c
new file mode 100644
index 0000000..101d3c8
--- /dev/null
+++ b/none/tests/tilegx/insn_test_dblalign4_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_dblalign4_X0.c
+//op=76
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb17341a0d542c8a8, 0x2220b583f77f7510 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r41, -25189\n"
+ "shl16insli r41, r41, 30892\n"
+ "shl16insli r41, r41, 12292\n"
+ "shl16insli r41, r41, 9859\n"
+ "moveli r10, -10199\n"
+ "shl16insli r10, r10, -13638\n"
+ "shl16insli r10, r10, 17992\n"
+ "shl16insli r10, r10, -16829\n"
+ "moveli r16, -8310\n"
+ "shl16insli r16, r16, -28931\n"
+ "shl16insli r16, r16, 16317\n"
+ "shl16insli r16, r16, -2081\n"
+ "{ dblalign4 r41, r10, r16 ; fnop }\n"
+ "move %0, r41\n"
+ "move %1, r10\n"
+ "move %2, r16\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_dblalign4_X1.c b/none/tests/tilegx/insn_test_dblalign4_X1.c
new file mode 100644
index 0000000..a5a587d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_dblalign4_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_dblalign4_X1.c
+//op=76
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb17341a0d542c8a8, 0x2220b583f77f7510 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r41, -25189\n"
+ "shl16insli r41, r41, 30892\n"
+ "shl16insli r41, r41, 12292\n"
+ "shl16insli r41, r41, 9859\n"
+ "moveli r10, -10199\n"
+ "shl16insli r10, r10, -13638\n"
+ "shl16insli r10, r10, 17992\n"
+ "shl16insli r10, r10, -16829\n"
+ "moveli r16, -8310\n"
+ "shl16insli r16, r16, -28931\n"
+ "shl16insli r16, r16, 16317\n"
+ "shl16insli r16, r16, -2081\n"
+ "{ fnop ; dblalign4 r41, r10, r16 }\n"
+ "move %0, r41\n"
+ "move %1, r10\n"
+ "move %2, r16\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_dblalign6_X0.c b/none/tests/tilegx/insn_test_dblalign6_X0.c
new file mode 100644
index 0000000..29f370b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_dblalign6_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_dblalign6_X0.c
+//op=77
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x32e0ae3536cebe67, 0x8917ce8584615586 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r45, 30164\n"
+ "shl16insli r45, r45, 21219\n"
+ "shl16insli r45, r45, -24252\n"
+ "shl16insli r45, r45, -4168\n"
+ "moveli r35, 27921\n"
+ "shl16insli r35, r35, 15394\n"
+ "shl16insli r35, r35, -22195\n"
+ "shl16insli r35, r35, 26084\n"
+ "moveli r2, 25320\n"
+ "shl16insli r2, r2, 3164\n"
+ "shl16insli r2, r2, 17326\n"
+ "shl16insli r2, r2, 5238\n"
+ "{ dblalign6 r45, r35, r2 ; fnop }\n"
+ "move %0, r45\n"
+ "move %1, r35\n"
+ "move %2, r2\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_dblalign6_X1.c b/none/tests/tilegx/insn_test_dblalign6_X1.c
new file mode 100644
index 0000000..0a23aaa
--- /dev/null
+++ b/none/tests/tilegx/insn_test_dblalign6_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_dblalign6_X1.c
+//op=77
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x32e0ae3536cebe67, 0x8917ce8584615586 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r45, 30164\n"
+ "shl16insli r45, r45, 21219\n"
+ "shl16insli r45, r45, -24252\n"
+ "shl16insli r45, r45, -4168\n"
+ "moveli r35, 27921\n"
+ "shl16insli r35, r35, 15394\n"
+ "shl16insli r35, r35, -22195\n"
+ "shl16insli r35, r35, 26084\n"
+ "moveli r2, 25320\n"
+ "shl16insli r2, r2, 3164\n"
+ "shl16insli r2, r2, 17326\n"
+ "shl16insli r2, r2, 5238\n"
+ "{ fnop ; dblalign6 r45, r35, r2 }\n"
+ "move %0, r45\n"
+ "move %1, r35\n"
+ "move %2, r2\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_dblalign_X0.c b/none/tests/tilegx/insn_test_dblalign_X0.c
new file mode 100644
index 0000000..f258c21
--- /dev/null
+++ b/none/tests/tilegx/insn_test_dblalign_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_dblalign_X0.c
+//op=74
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x68fb6e92c7467995, 0x712fa2e35cfc84ba };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r14, -10628\n"
+ "shl16insli r14, r14, 21331\n"
+ "shl16insli r14, r14, -19208\n"
+ "shl16insli r14, r14, 14673\n"
+ "moveli r28, -30755\n"
+ "shl16insli r28, r28, 5835\n"
+ "shl16insli r28, r28, -24471\n"
+ "shl16insli r28, r28, -4179\n"
+ "moveli r29, -10637\n"
+ "shl16insli r29, r29, -13587\n"
+ "shl16insli r29, r29, 6072\n"
+ "shl16insli r29, r29, -2381\n"
+ "{ dblalign r14, r28, r29 ; fnop }\n"
+ "move %0, r14\n"
+ "move %1, r28\n"
+ "move %2, r29\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_dtlbpr_X1.c b/none/tests/tilegx/insn_test_dtlbpr_X1.c
new file mode 100644
index 0000000..1c528a6
--- /dev/null
+++ b/none/tests/tilegx/insn_test_dtlbpr_X1.c
@@ -0,0 +1,30 @@
+//file: _insn_test_dtlbpr_X1.c
+//op=79
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x910a2955c6e71b1, 0x884eacaf96426585 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r6, 6476\n"
+ "shl16insli r6, r6, -30926\n"
+ "shl16insli r6, r6, 24920\n"
+ "shl16insli r6, r6, 10073\n"
+ "{ fnop ; dtlbpr r6 }\n"
+ "move %0, r6\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fdouble_add_flags_X0.c b/none/tests/tilegx/insn_test_fdouble_add_flags_X0.c
new file mode 100644
index 0000000..bbe3c7a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fdouble_add_flags_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_fdouble_add_flags_X0.c
+//op=82
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5ff5d41ce72b342e, 0xec57de1f0b8de6b3 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r40, -10411\n"
+ "shl16insli r40, r40, 28866\n"
+ "shl16insli r40, r40, 30647\n"
+ "shl16insli r40, r40, 15107\n"
+ "moveli r21, 13116\n"
+ "shl16insli r21, r21, 11172\n"
+ "shl16insli r21, r21, -2564\n"
+ "shl16insli r21, r21, 1912\n"
+ "moveli r44, 10847\n"
+ "shl16insli r44, r44, -21273\n"
+ "shl16insli r44, r44, -26560\n"
+ "shl16insli r44, r44, -2137\n"
+ "{ fdouble_add_flags r40, r21, r44 ; fnop }\n"
+ "move %0, r40\n"
+ "move %1, r21\n"
+ "move %2, r44\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fdouble_addsub_X0.c b/none/tests/tilegx/insn_test_fdouble_addsub_X0.c
new file mode 100644
index 0000000..f1a2970
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fdouble_addsub_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_fdouble_addsub_X0.c
+//op=83
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x57b488292bdd9c2b, 0xfd7e2c78d6f58fbd };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r50, 9884\n"
+ "shl16insli r50, r50, -18142\n"
+ "shl16insli r50, r50, -24129\n"
+ "shl16insli r50, r50, 11296\n"
+ "moveli r9, -26512\n"
+ "shl16insli r9, r9, -8064\n"
+ "shl16insli r9, r9, 9043\n"
+ "shl16insli r9, r9, 18472\n"
+ "moveli r20, 4246\n"
+ "shl16insli r20, r20, 6079\n"
+ "shl16insli r20, r20, 8698\n"
+ "shl16insli r20, r20, -2697\n"
+ "{ fdouble_addsub r50, r9, r20 ; fnop }\n"
+ "move %0, r50\n"
+ "move %1, r9\n"
+ "move %2, r20\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fdouble_mul_flags_X0.c b/none/tests/tilegx/insn_test_fdouble_mul_flags_X0.c
new file mode 100644
index 0000000..c939561
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fdouble_mul_flags_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_fdouble_mul_flags_X0.c
+//op=84
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xdff35e384e663195, 0xce5c4dd59315697c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r23, -2482\n"
+ "shl16insli r23, r23, 1883\n"
+ "shl16insli r23, r23, 757\n"
+ "shl16insli r23, r23, 5578\n"
+ "moveli r32, -12252\n"
+ "shl16insli r32, r32, 5860\n"
+ "shl16insli r32, r32, 15129\n"
+ "shl16insli r32, r32, -15375\n"
+ "moveli r3, -4690\n"
+ "shl16insli r3, r3, 18437\n"
+ "shl16insli r3, r3, 14549\n"
+ "shl16insli r3, r3, -22291\n"
+ "{ fdouble_mul_flags r23, r32, r3 ; fnop }\n"
+ "move %0, r23\n"
+ "move %1, r32\n"
+ "move %2, r3\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fdouble_pack1_X0.c b/none/tests/tilegx/insn_test_fdouble_pack1_X0.c
new file mode 100644
index 0000000..74e5a6f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fdouble_pack1_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_fdouble_pack1_X0.c
+//op=85
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x8a6bdf08a51f10d3, 0xbb06a702206f99b2 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r28, 31787\n"
+ "shl16insli r28, r28, 188\n"
+ "shl16insli r28, r28, -30112\n"
+ "shl16insli r28, r28, -13987\n"
+ "moveli r28, -217\n"
+ "shl16insli r28, r28, -31069\n"
+ "shl16insli r28, r28, 14592\n"
+ "shl16insli r28, r28, 26557\n"
+ "moveli r26, -8315\n"
+ "shl16insli r26, r26, 5404\n"
+ "shl16insli r26, r26, 15177\n"
+ "shl16insli r26, r26, -6931\n"
+ "{ fdouble_pack1 r28, r28, r26 ; fnop }\n"
+ "move %0, r28\n"
+ "move %1, r28\n"
+ "move %2, r26\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fdouble_pack2_X0.c b/none/tests/tilegx/insn_test_fdouble_pack2_X0.c
new file mode 100644
index 0000000..0cc8f9b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fdouble_pack2_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_fdouble_pack2_X0.c
+//op=86
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x38646a3eaf613478, 0xc2c31988eb4ca702 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r9, 18459\n"
+ "shl16insli r9, r9, -11831\n"
+ "shl16insli r9, r9, -23522\n"
+ "shl16insli r9, r9, -17142\n"
+ "moveli r9, 9504\n"
+ "shl16insli r9, r9, 15930\n"
+ "shl16insli r9, r9, -27963\n"
+ "shl16insli r9, r9, -6534\n"
+ "moveli r12, -19781\n"
+ "shl16insli r12, r12, 4441\n"
+ "shl16insli r12, r12, -25151\n"
+ "shl16insli r12, r12, -1099\n"
+ "{ fdouble_pack2 r9, r9, r12 ; fnop }\n"
+ "move %0, r9\n"
+ "move %1, r9\n"
+ "move %2, r12\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fdouble_sub_flags_X0.c b/none/tests/tilegx/insn_test_fdouble_sub_flags_X0.c
new file mode 100644
index 0000000..750d218
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fdouble_sub_flags_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_fdouble_sub_flags_X0.c
+//op=87
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc7ac37053a461101, 0xf55855739bded624 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r1, -25048\n"
+ "shl16insli r1, r1, -26391\n"
+ "shl16insli r1, r1, -12179\n"
+ "shl16insli r1, r1, -11222\n"
+ "moveli r17, -6657\n"
+ "shl16insli r17, r17, -8617\n"
+ "shl16insli r17, r17, 10307\n"
+ "shl16insli r17, r17, 8268\n"
+ "moveli r42, -11842\n"
+ "shl16insli r42, r42, 25434\n"
+ "shl16insli r42, r42, -11416\n"
+ "shl16insli r42, r42, -1334\n"
+ "{ fdouble_sub_flags r1, r17, r42 ; fnop }\n"
+ "move %0, r1\n"
+ "move %1, r17\n"
+ "move %2, r42\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fdouble_unpack_max_X0.c b/none/tests/tilegx/insn_test_fdouble_unpack_max_X0.c
new file mode 100644
index 0000000..8272651
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fdouble_unpack_max_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_fdouble_unpack_max_X0.c
+//op=88
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xab961c7cdfcb76d0, 0xa9ccfec4f599744d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r45, -7064\n"
+ "shl16insli r45, r45, -20382\n"
+ "shl16insli r45, r45, -30133\n"
+ "shl16insli r45, r45, 11394\n"
+ "moveli r5, 26677\n"
+ "shl16insli r5, r5, 32003\n"
+ "shl16insli r5, r5, 16745\n"
+ "shl16insli r5, r5, -29543\n"
+ "moveli r48, -17450\n"
+ "shl16insli r48, r48, 24652\n"
+ "shl16insli r48, r48, 22143\n"
+ "shl16insli r48, r48, -2590\n"
+ "{ fdouble_unpack_max r45, r5, r48 ; fnop }\n"
+ "move %0, r45\n"
+ "move %1, r5\n"
+ "move %2, r48\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fdouble_unpack_min_X0.c b/none/tests/tilegx/insn_test_fdouble_unpack_min_X0.c
new file mode 100644
index 0000000..921e604
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fdouble_unpack_min_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_fdouble_unpack_min_X0.c
+//op=89
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc7396f52c760a9d3, 0x4bf0ef1260a5545f };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, -29325\n"
+ "shl16insli r34, r34, 23863\n"
+ "shl16insli r34, r34, -25021\n"
+ "shl16insli r34, r34, -17019\n"
+ "moveli r35, 6975\n"
+ "shl16insli r35, r35, -3872\n"
+ "shl16insli r35, r35, 17466\n"
+ "shl16insli r35, r35, 15329\n"
+ "moveli r3, -10923\n"
+ "shl16insli r3, r3, 19053\n"
+ "shl16insli r3, r3, 1173\n"
+ "shl16insli r3, r3, -17395\n"
+ "{ fdouble_unpack_min r34, r35, r3 ; fnop }\n"
+ "move %0, r34\n"
+ "move %1, r35\n"
+ "move %2, r3\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_flushwb_X1.c b/none/tests/tilegx/insn_test_flushwb_X1.c
new file mode 100644
index 0000000..89dd33b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_flushwb_X1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_flushwb_X1.c
+//op=100
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd85a80d7b6245b44, 0x4035b9e3ec473fc4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "{ fnop ; flushwb }\n"
+ );
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fnop_X0.c b/none/tests/tilegx/insn_test_fnop_X0.c
new file mode 100644
index 0000000..7935cbc
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fnop_X0.c
@@ -0,0 +1,24 @@
+//file: _insn_test_fnop_X0.c
+//op=101
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x1b58c82cfa9e7805, 0xeb546e8d18f5ab4c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "{ fnop ; fnop }\n"
+ );
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fnop_X1.c b/none/tests/tilegx/insn_test_fnop_X1.c
new file mode 100644
index 0000000..21ac123
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fnop_X1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_fnop_X1.c
+//op=101
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x1b58c82cfa9e7805, 0xeb546e8d18f5ab4c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "{ fnop ; fnop }\n"
+ );
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fnop_Y0.c b/none/tests/tilegx/insn_test_fnop_Y0.c
new file mode 100644
index 0000000..5c13e5b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fnop_Y0.c
@@ -0,0 +1,24 @@
+//file: _insn_test_fnop_Y0.c
+//op=101
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x1b58c82cfa9e7805, 0xeb546e8d18f5ab4c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "{ fnop ; fnop ; ld r63, r54 }\n"
+ );
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fnop_Y1.c b/none/tests/tilegx/insn_test_fnop_Y1.c
new file mode 100644
index 0000000..b9df4b5
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fnop_Y1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_fnop_Y1.c
+//op=101
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x1b58c82cfa9e7805, 0xeb546e8d18f5ab4c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "{ fnop ; fnop ; ld r63, r54 }\n"
+ );
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fsingle_add1_X0.c b/none/tests/tilegx/insn_test_fsingle_add1_X0.c
new file mode 100644
index 0000000..9d933e7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fsingle_add1_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_fsingle_add1_X0.c
+//op=102
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf5f52759ddd87eb8, 0x8e9efd621a0271c0 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r21, -6121\n"
+ "shl16insli r21, r21, -23936\n"
+ "shl16insli r21, r21, -6621\n"
+ "shl16insli r21, r21, -11778\n"
+ "moveli r22, 24848\n"
+ "shl16insli r22, r22, -12444\n"
+ "shl16insli r22, r22, -9823\n"
+ "shl16insli r22, r22, -18157\n"
+ "moveli r3, -29477\n"
+ "shl16insli r3, r3, 10834\n"
+ "shl16insli r3, r3, -26605\n"
+ "shl16insli r3, r3, 14005\n"
+ "{ fsingle_add1 r21, r22, r3 ; fnop }\n"
+ "move %0, r21\n"
+ "move %1, r22\n"
+ "move %2, r3\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fsingle_addsub2_X0.c b/none/tests/tilegx/insn_test_fsingle_addsub2_X0.c
new file mode 100644
index 0000000..24ba0d2
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fsingle_addsub2_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_fsingle_addsub2_X0.c
+//op=103
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2c24dd020e9fa33f, 0xc279be840ee86dea };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, -8392\n"
+ "shl16insli r16, r16, -23005\n"
+ "shl16insli r16, r16, -28857\n"
+ "shl16insli r16, r16, -4517\n"
+ "moveli r18, -23753\n"
+ "shl16insli r18, r18, -24851\n"
+ "shl16insli r18, r18, 4221\n"
+ "shl16insli r18, r18, 16539\n"
+ "moveli r13, -2884\n"
+ "shl16insli r13, r13, 28785\n"
+ "shl16insli r13, r13, 7136\n"
+ "shl16insli r13, r13, 32281\n"
+ "{ fsingle_addsub2 r16, r18, r13 ; fnop }\n"
+ "move %0, r16\n"
+ "move %1, r18\n"
+ "move %2, r13\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fsingle_mul1_X0.c b/none/tests/tilegx/insn_test_fsingle_mul1_X0.c
new file mode 100644
index 0000000..2f7b6aa
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fsingle_mul1_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_fsingle_mul1_X0.c
+//op=104
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe22608b00f39a4c5, 0x9276743f21019b4e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r32, -27396\n"
+ "shl16insli r32, r32, -8056\n"
+ "shl16insli r32, r32, 23879\n"
+ "shl16insli r32, r32, 14131\n"
+ "moveli r4, 4550\n"
+ "shl16insli r4, r4, 29355\n"
+ "shl16insli r4, r4, 30941\n"
+ "shl16insli r4, r4, 29755\n"
+ "moveli r38, -21466\n"
+ "shl16insli r38, r38, 11354\n"
+ "shl16insli r38, r38, -10374\n"
+ "shl16insli r38, r38, 87\n"
+ "{ fsingle_mul1 r32, r4, r38 ; fnop }\n"
+ "move %0, r32\n"
+ "move %1, r4\n"
+ "move %2, r38\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fsingle_mul2_X0.c b/none/tests/tilegx/insn_test_fsingle_mul2_X0.c
new file mode 100644
index 0000000..72aa38d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fsingle_mul2_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_fsingle_mul2_X0.c
+//op=105
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4419397566d0f360, 0xebc915599850d350 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r36, 15980\n"
+ "shl16insli r36, r36, 6185\n"
+ "shl16insli r36, r36, -3610\n"
+ "shl16insli r36, r36, -10263\n"
+ "moveli r48, 11819\n"
+ "shl16insli r48, r48, -3940\n"
+ "shl16insli r48, r48, 25912\n"
+ "shl16insli r48, r48, 22355\n"
+ "moveli r9, -832\n"
+ "shl16insli r9, r9, -16346\n"
+ "shl16insli r9, r9, -24487\n"
+ "shl16insli r9, r9, 31724\n"
+ "{ fsingle_mul2 r36, r48, r9 ; fnop }\n"
+ "move %0, r36\n"
+ "move %1, r48\n"
+ "move %2, r9\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fsingle_pack1_X0.c b/none/tests/tilegx/insn_test_fsingle_pack1_X0.c
new file mode 100644
index 0000000..59272f9
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fsingle_pack1_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_fsingle_pack1_X0.c
+//op=106
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x988b16de50a53a0a, 0x5fced320ec74ecd8 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r46, -30106\n"
+ "shl16insli r46, r46, 24510\n"
+ "shl16insli r46, r46, -6618\n"
+ "shl16insli r46, r46, 11033\n"
+ "moveli r26, -11405\n"
+ "shl16insli r26, r26, -6947\n"
+ "shl16insli r26, r26, 19133\n"
+ "shl16insli r26, r26, -19900\n"
+ "{ fsingle_pack1 r46, r26 ; fnop }\n"
+ "move %0, r46\n"
+ "move %1, r26\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fsingle_pack1_Y0.c b/none/tests/tilegx/insn_test_fsingle_pack1_Y0.c
new file mode 100644
index 0000000..d85d6c6
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fsingle_pack1_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_fsingle_pack1_Y0.c
+//op=106
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x988b16de50a53a0a, 0x5fced320ec74ecd8 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r46, -30106\n"
+ "shl16insli r46, r46, 24510\n"
+ "shl16insli r46, r46, -6618\n"
+ "shl16insli r46, r46, 11033\n"
+ "moveli r26, -11405\n"
+ "shl16insli r26, r26, -6947\n"
+ "shl16insli r26, r26, 19133\n"
+ "shl16insli r26, r26, -19900\n"
+ "{ fsingle_pack1 r46, r26 ; fnop ; ld r63, r54 }\n"
+ "move %0, r46\n"
+ "move %1, r26\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fsingle_pack2_X0.c b/none/tests/tilegx/insn_test_fsingle_pack2_X0.c
new file mode 100644
index 0000000..6d2b3a4
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fsingle_pack2_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_fsingle_pack2_X0.c
+//op=107
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4463a2383032e2f2, 0x4a32a55c75498ba7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r25, 27454\n"
+ "shl16insli r25, r25, -25613\n"
+ "shl16insli r25, r25, -25678\n"
+ "shl16insli r25, r25, -280\n"
+ "moveli r33, -5991\n"
+ "shl16insli r33, r33, 9025\n"
+ "shl16insli r33, r33, -5431\n"
+ "shl16insli r33, r33, 19958\n"
+ "moveli r28, 10868\n"
+ "shl16insli r28, r28, 28978\n"
+ "shl16insli r28, r28, -7157\n"
+ "shl16insli r28, r28, 19796\n"
+ "{ fsingle_pack2 r25, r33, r28 ; fnop }\n"
+ "move %0, r25\n"
+ "move %1, r33\n"
+ "move %2, r28\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_fsingle_sub1_X0.c b/none/tests/tilegx/insn_test_fsingle_sub1_X0.c
new file mode 100644
index 0000000..75823d8
--- /dev/null
+++ b/none/tests/tilegx/insn_test_fsingle_sub1_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_fsingle_sub1_X0.c
+//op=108
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x8d6611e2e0188d4d, 0xc051e6bca12058e0 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r18, -32379\n"
+ "shl16insli r18, r18, -17242\n"
+ "shl16insli r18, r18, -8818\n"
+ "shl16insli r18, r18, 7579\n"
+ "moveli r22, 9145\n"
+ "shl16insli r22, r22, 16129\n"
+ "shl16insli r22, r22, -28988\n"
+ "shl16insli r22, r22, -28265\n"
+ "moveli r4, 23316\n"
+ "shl16insli r4, r4, 27509\n"
+ "shl16insli r4, r4, 21179\n"
+ "shl16insli r4, r4, 13422\n"
+ "{ fsingle_sub1 r18, r22, r4 ; fnop }\n"
+ "move %0, r18\n"
+ "move %1, r22\n"
+ "move %2, r4\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_icoh_X1.c b/none/tests/tilegx/insn_test_icoh_X1.c
new file mode 100644
index 0000000..2275236
--- /dev/null
+++ b/none/tests/tilegx/insn_test_icoh_X1.c
@@ -0,0 +1,30 @@
+//file: _insn_test_icoh_X1.c
+//op=109
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x1fe3ff849620d963, 0x911b4b9f0928dd1b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r31, 15613\n"
+ "shl16insli r31, r31, -26390\n"
+ "shl16insli r31, r31, -13320\n"
+ "shl16insli r31, r31, 11345\n"
+ "{ fnop ; icoh r31 }\n"
+ "move %0, r31\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_j_X1.c b/none/tests/tilegx/insn_test_j_X1.c
new file mode 100644
index 0000000..285ac1f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_j_X1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_j_X1.c
+//op=113
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x721ddf3c2c82992f, 0xdc2f92eb642eb1d1 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "j %0\n"
+ :: "i"(func_exit));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_jal_X1.c b/none/tests/tilegx/insn_test_jal_X1.c
new file mode 100644
index 0000000..0a6ce83
--- /dev/null
+++ b/none/tests/tilegx/insn_test_jal_X1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_jal_X1.c
+//op=114
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x97c50c1862f77907, 0xd4017cfe9fa6ebaa };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "jal %0\n"
+ :: "i"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_jalr_X1.c b/none/tests/tilegx/insn_test_jalr_X1.c
new file mode 100644
index 0000000..fdde6c4
--- /dev/null
+++ b/none/tests/tilegx/insn_test_jalr_X1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_jalr_X1.c
+//op=115
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4826371b074e6849, 0xf512a65b934c3280 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "jalr %0\n"
+ :: "r"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_jalr_Y1.c b/none/tests/tilegx/insn_test_jalr_Y1.c
new file mode 100644
index 0000000..c6a66a3
--- /dev/null
+++ b/none/tests/tilegx/insn_test_jalr_Y1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_jalr_Y1.c
+//op=115
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4826371b074e6849, 0xf512a65b934c3280 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "jalr %0\n"
+ :: "r"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_jalrp_X1.c b/none/tests/tilegx/insn_test_jalrp_X1.c
new file mode 100644
index 0000000..d53cbfb
--- /dev/null
+++ b/none/tests/tilegx/insn_test_jalrp_X1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_jalrp_X1.c
+//op=116
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xcf14c16c8fe6d80a, 0x9a968c4e2652e151 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "jalrp %0\n"
+ :: "r"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_jalrp_Y1.c b/none/tests/tilegx/insn_test_jalrp_Y1.c
new file mode 100644
index 0000000..8ae4c84
--- /dev/null
+++ b/none/tests/tilegx/insn_test_jalrp_Y1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_jalrp_Y1.c
+//op=116
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xcf14c16c8fe6d80a, 0x9a968c4e2652e151 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "jalrp %0\n"
+ :: "r"(func_call));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_jr_X1.c b/none/tests/tilegx/insn_test_jr_X1.c
new file mode 100644
index 0000000..ecba26f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_jr_X1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_jr_X1.c
+//op=117
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5468060e74455729, 0x796b977f2174befa };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "jr %0\n"
+ :: "r"(func_exit));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_jr_Y1.c b/none/tests/tilegx/insn_test_jr_Y1.c
new file mode 100644
index 0000000..aace76b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_jr_Y1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_jr_Y1.c
+//op=117
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5468060e74455729, 0x796b977f2174befa };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "jr %0\n"
+ :: "r"(func_exit));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_jrp_X1.c b/none/tests/tilegx/insn_test_jrp_X1.c
new file mode 100644
index 0000000..38d4b9f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_jrp_X1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_jrp_X1.c
+//op=118
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd398d9dcfc90866b, 0xdfe94ab09fee22a5 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "jrp %0\n"
+ :: "r"(func_exit));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_jrp_Y1.c b/none/tests/tilegx/insn_test_jrp_Y1.c
new file mode 100644
index 0000000..f9af56d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_jrp_Y1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_jrp_Y1.c
+//op=118
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd398d9dcfc90866b, 0xdfe94ab09fee22a5 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "jrp %0\n"
+ :: "r"(func_exit));
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld1s_X1.c b/none/tests/tilegx/insn_test_ld1s_X1.c
new file mode 100644
index 0000000..8c60563
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld1s_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld1s_X1.c
+//op=120
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xfd529a461f919c3b, 0xa702a184ea8a31f7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -25406\n"
+ "shl16insli r38, r38, 4116\n"
+ "shl16insli r38, r38, 26061\n"
+ "shl16insli r38, r38, -21556\n"
+ "moveli r25, 9517\n"
+ "shl16insli r25, r25, -14743\n"
+ "shl16insli r25, r25, 28886\n"
+ "shl16insli r25, r25, 23646\n"
+ "move r25, %2\n"
+ "{ fnop ; ld1s r38, r25 }\n"
+ "move %0, r38\n"
+ "move %1, r25\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld1s_Y2.c b/none/tests/tilegx/insn_test_ld1s_Y2.c
new file mode 100644
index 0000000..3cb93b0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld1s_Y2.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld1s_Y2.c
+//op=120
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xfd529a461f919c3b, 0xa702a184ea8a31f7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, -25406\n"
+ "shl16insli r11, r11, 4116\n"
+ "shl16insli r11, r11, 26061\n"
+ "shl16insli r11, r11, -21556\n"
+ "moveli r20, 9517\n"
+ "shl16insli r20, r20, -14743\n"
+ "shl16insli r20, r20, 28886\n"
+ "shl16insli r20, r20, 23646\n"
+ "move r20, %2\n"
+ "{ fnop ; fnop ; ld1s r11, r20 }\n"
+ "move %0, r11\n"
+ "move %1, r20\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld1s_add_X1.c b/none/tests/tilegx/insn_test_ld1s_add_X1.c
new file mode 100644
index 0000000..1a07d59
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld1s_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld1s_add_X1.c
+//op=121
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbf944e471ed68a09, 0xc750773165e75c2a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, 2389\n"
+ "shl16insli r11, r11, -8821\n"
+ "shl16insli r11, r11, -19715\n"
+ "shl16insli r11, r11, 21029\n"
+ "moveli r19, 8794\n"
+ "shl16insli r19, r19, -28834\n"
+ "shl16insli r19, r19, 6092\n"
+ "shl16insli r19, r19, 15960\n"
+ "move r19, %2\n"
+ "{ fnop ; ld1s_add r11, r19, -82 }\n"
+ "move %0, r11\n"
+ "move %1, r19\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld1u_X1.c b/none/tests/tilegx/insn_test_ld1u_X1.c
new file mode 100644
index 0000000..457af2e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld1u_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld1u_X1.c
+//op=122
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xae053c723a6c8e37, 0x26836d784e440ab7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r19, 8260\n"
+ "shl16insli r19, r19, -7206\n"
+ "shl16insli r19, r19, -24567\n"
+ "shl16insli r19, r19, -8840\n"
+ "moveli r23, -18757\n"
+ "shl16insli r23, r23, 26178\n"
+ "shl16insli r23, r23, 32618\n"
+ "shl16insli r23, r23, 22067\n"
+ "move r23, %2\n"
+ "{ fnop ; ld1u r19, r23 }\n"
+ "move %0, r19\n"
+ "move %1, r23\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld1u_Y2.c b/none/tests/tilegx/insn_test_ld1u_Y2.c
new file mode 100644
index 0000000..9159214
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld1u_Y2.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld1u_Y2.c
+//op=122
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xae053c723a6c8e37, 0x26836d784e440ab7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r35, 8260\n"
+ "shl16insli r35, r35, -7206\n"
+ "shl16insli r35, r35, -24567\n"
+ "shl16insli r35, r35, -8840\n"
+ "moveli r9, -18757\n"
+ "shl16insli r9, r9, 26178\n"
+ "shl16insli r9, r9, 32618\n"
+ "shl16insli r9, r9, 22067\n"
+ "move r9, %2\n"
+ "{ fnop ; fnop ; ld1u r35, r9 }\n"
+ "move %0, r35\n"
+ "move %1, r9\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld1u_add_X1.c b/none/tests/tilegx/insn_test_ld1u_add_X1.c
new file mode 100644
index 0000000..e8f754a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld1u_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld1u_add_X1.c
+//op=123
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x71782df005cc3618, 0x98e72847e6d80b39 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r33, 13116\n"
+ "shl16insli r33, r33, 11172\n"
+ "shl16insli r33, r33, -2564\n"
+ "shl16insli r33, r33, 1912\n"
+ "moveli r32, 28219\n"
+ "shl16insli r32, r32, -17492\n"
+ "shl16insli r32, r32, -19727\n"
+ "shl16insli r32, r32, 7684\n"
+ "move r32, %2\n"
+ "{ fnop ; ld1u_add r33, r32, -75 }\n"
+ "move %0, r33\n"
+ "move %1, r32\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld2s_X1.c b/none/tests/tilegx/insn_test_ld2s_X1.c
new file mode 100644
index 0000000..4f19ed7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld2s_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld2s_X1.c
+//op=124
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6d228375c43e27fe, 0x6a0cb98ab56a8e60 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r18, -2019\n"
+ "shl16insli r18, r18, 30837\n"
+ "shl16insli r18, r18, -1194\n"
+ "shl16insli r18, r18, -12623\n"
+ "moveli r46, -17868\n"
+ "shl16insli r46, r46, -15637\n"
+ "shl16insli r46, r46, -21854\n"
+ "shl16insli r46, r46, 31769\n"
+ "move r46, %2\n"
+ "{ fnop ; ld2s r18, r46 }\n"
+ "move %0, r18\n"
+ "move %1, r46\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld2s_Y2.c b/none/tests/tilegx/insn_test_ld2s_Y2.c
new file mode 100644
index 0000000..0759176
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld2s_Y2.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld2s_Y2.c
+//op=124
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6d228375c43e27fe, 0x6a0cb98ab56a8e60 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r43, -2019\n"
+ "shl16insli r43, r43, 30837\n"
+ "shl16insli r43, r43, -1194\n"
+ "shl16insli r43, r43, -12623\n"
+ "moveli r41, -17868\n"
+ "shl16insli r41, r41, -15637\n"
+ "shl16insli r41, r41, -21854\n"
+ "shl16insli r41, r41, 31769\n"
+ "move r41, %2\n"
+ "{ fnop ; fnop ; ld2s r43, r41 }\n"
+ "move %0, r43\n"
+ "move %1, r41\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld2u_X1.c b/none/tests/tilegx/insn_test_ld2u_X1.c
new file mode 100644
index 0000000..9983db1
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld2u_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld2u_X1.c
+//op=126
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb50b19b244ac7eb4, 0x11b59d6276787136 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r12, -12252\n"
+ "shl16insli r12, r12, 5860\n"
+ "shl16insli r12, r12, 15129\n"
+ "shl16insli r12, r12, -15375\n"
+ "moveli r47, -11895\n"
+ "shl16insli r47, r47, 21718\n"
+ "shl16insli r47, r47, -14088\n"
+ "shl16insli r47, r47, -5322\n"
+ "move r47, %2\n"
+ "{ fnop ; ld2u r12, r47 }\n"
+ "move %0, r12\n"
+ "move %1, r47\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld2u_Y2.c b/none/tests/tilegx/insn_test_ld2u_Y2.c
new file mode 100644
index 0000000..9396a0d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld2u_Y2.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld2u_Y2.c
+//op=126
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb50b19b244ac7eb4, 0x11b59d6276787136 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r42, -12252\n"
+ "shl16insli r42, r42, 5860\n"
+ "shl16insli r42, r42, 15129\n"
+ "shl16insli r42, r42, -15375\n"
+ "moveli r4, -11895\n"
+ "shl16insli r4, r4, 21718\n"
+ "shl16insli r4, r4, -14088\n"
+ "shl16insli r4, r4, -5322\n"
+ "move r4, %2\n"
+ "{ fnop ; fnop ; ld2u r42, r4 }\n"
+ "move %0, r42\n"
+ "move %1, r4\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld4s_X1.c b/none/tests/tilegx/insn_test_ld4s_X1.c
new file mode 100644
index 0000000..36d7f9e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld4s_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld4s_X1.c
+//op=128
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xcef60e4c85b01644, 0x411d3fc3fc916064 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r15, -5570\n"
+ "shl16insli r15, r15, -29385\n"
+ "shl16insli r15, r15, -18769\n"
+ "shl16insli r15, r15, -2309\n"
+ "moveli r48, -28670\n"
+ "shl16insli r48, r48, -6265\n"
+ "shl16insli r48, r48, 15425\n"
+ "shl16insli r48, r48, 17326\n"
+ "move r48, %2\n"
+ "{ fnop ; ld4s r15, r48 }\n"
+ "move %0, r15\n"
+ "move %1, r48\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld4s_add_X1.c b/none/tests/tilegx/insn_test_ld4s_add_X1.c
new file mode 100644
index 0000000..7c05420
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld4s_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld4s_add_X1.c
+//op=129
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x3ab13aa81a1f8e6, 0xa0f4db3555dcd53 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r7, 9504\n"
+ "shl16insli r7, r7, 15930\n"
+ "shl16insli r7, r7, -27963\n"
+ "shl16insli r7, r7, -6534\n"
+ "moveli r33, 7720\n"
+ "shl16insli r33, r33, -13533\n"
+ "shl16insli r33, r33, 10333\n"
+ "shl16insli r33, r33, -5169\n"
+ "move r33, %2\n"
+ "{ fnop ; ld4s_add r7, r33, 106 }\n"
+ "move %0, r7\n"
+ "move %1, r33\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld4u_X1.c b/none/tests/tilegx/insn_test_ld4u_X1.c
new file mode 100644
index 0000000..2f60d93
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld4u_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld4u_X1.c
+//op=130
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb002a7dc1c538d17, 0x553c16d3559d1cee };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r46, 20445\n"
+ "shl16insli r46, r46, -17976\n"
+ "shl16insli r46, r46, -29438\n"
+ "shl16insli r46, r46, -12912\n"
+ "moveli r2, 6570\n"
+ "shl16insli r2, r2, -30096\n"
+ "shl16insli r2, r2, -3418\n"
+ "shl16insli r2, r2, 9405\n"
+ "move r2, %2\n"
+ "{ fnop ; ld4u r46, r2 }\n"
+ "move %0, r46\n"
+ "move %1, r2\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld4u_Y2.c b/none/tests/tilegx/insn_test_ld4u_Y2.c
new file mode 100644
index 0000000..847bf1d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld4u_Y2.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld4u_Y2.c
+//op=130
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb002a7dc1c538d17, 0x553c16d3559d1cee };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r42, 20445\n"
+ "shl16insli r42, r42, -17976\n"
+ "shl16insli r42, r42, -29438\n"
+ "shl16insli r42, r42, -12912\n"
+ "moveli r15, 6570\n"
+ "shl16insli r15, r15, -30096\n"
+ "shl16insli r15, r15, -3418\n"
+ "shl16insli r15, r15, 9405\n"
+ "move r15, %2\n"
+ "{ fnop ; fnop ; ld4u r42, r15 }\n"
+ "move %0, r42\n"
+ "move %1, r15\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld4u_add_X1.c b/none/tests/tilegx/insn_test_ld4u_add_X1.c
new file mode 100644
index 0000000..d4fabf7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld4u_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld4u_add_X1.c
+//op=131
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7f88e5945a40e9ee, 0xe76171c85a64faf7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r31, -14377\n"
+ "shl16insli r31, r31, -7231\n"
+ "shl16insli r31, r31, -29806\n"
+ "shl16insli r31, r31, 3514\n"
+ "moveli r50, 16073\n"
+ "shl16insli r50, r50, -20366\n"
+ "shl16insli r50, r50, -10414\n"
+ "shl16insli r50, r50, 4096\n"
+ "move r50, %2\n"
+ "{ fnop ; ld4u_add r31, r50, -16 }\n"
+ "move %0, r31\n"
+ "move %1, r50\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld_X1.c b/none/tests/tilegx/insn_test_ld_X1.c
new file mode 100644
index 0000000..830f1fa
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld_X1.c
+//op=119
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xdd853a2377c4c1cd, 0x7f7658d7010e1ce1 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r42, -17282\n"
+ "shl16insli r42, r42, 6317\n"
+ "shl16insli r42, r42, -15116\n"
+ "shl16insli r42, r42, -17196\n"
+ "moveli r26, -9435\n"
+ "shl16insli r26, r26, 12124\n"
+ "shl16insli r26, r26, -6695\n"
+ "shl16insli r26, r26, 1712\n"
+ "move r26, %2\n"
+ "{ fnop ; ld r42, r26 }\n"
+ "move %0, r42\n"
+ "move %1, r26\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld_Y2.c b/none/tests/tilegx/insn_test_ld_Y2.c
new file mode 100644
index 0000000..e127f07
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld_Y2.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld_Y2.c
+//op=119
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xdd853a2377c4c1cd, 0x7f7658d7010e1ce1 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r19, -17282\n"
+ "shl16insli r19, r19, 6317\n"
+ "shl16insli r19, r19, -15116\n"
+ "shl16insli r19, r19, -17196\n"
+ "moveli r34, -9435\n"
+ "shl16insli r34, r34, 12124\n"
+ "shl16insli r34, r34, -6695\n"
+ "shl16insli r34, r34, 1712\n"
+ "move r34, %2\n"
+ "{ fnop ; fnop ; ld r19, r34 }\n"
+ "move %0, r19\n"
+ "move %1, r34\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ld_add_X1.c b/none/tests/tilegx/insn_test_ld_add_X1.c
new file mode 100644
index 0000000..1d32c97
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ld_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ld_add_X1.c
+//op=132
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x3076e248a1b03309, 0x386e67ed7b089fc9 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r27, 26677\n"
+ "shl16insli r27, r27, 32003\n"
+ "shl16insli r27, r27, 16745\n"
+ "shl16insli r27, r27, -29543\n"
+ "moveli r39, 27432\n"
+ "shl16insli r39, r39, -22439\n"
+ "shl16insli r39, r39, 15226\n"
+ "shl16insli r39, r39, -19568\n"
+ "move r39, %2\n"
+ "{ fnop ; ld_add r27, r39, 118 }\n"
+ "move %0, r27\n"
+ "move %1, r39\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldna_X1.c b/none/tests/tilegx/insn_test_ldna_X1.c
new file mode 100644
index 0000000..8be9693
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldna_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldna_X1.c
+//op=133
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe99ff6bbb270ebf, 0xc708d15463e8c0ec };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r32, -30640\n"
+ "shl16insli r32, r32, 31848\n"
+ "shl16insli r32, r32, 11423\n"
+ "shl16insli r32, r32, -20012\n"
+ "moveli r16, -24423\n"
+ "shl16insli r16, r16, -14237\n"
+ "shl16insli r16, r16, 18232\n"
+ "shl16insli r16, r16, -32601\n"
+ "move r16, %2\n"
+ "{ fnop ; ldna r32, r16 }\n"
+ "move %0, r32\n"
+ "move %1, r16\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldna_add_X1.c b/none/tests/tilegx/insn_test_ldna_add_X1.c
new file mode 100644
index 0000000..e7741f2
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldna_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldna_add_X1.c
+//op=134
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2f3ac3e001892397, 0x20a35a283e09bcf3 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r23, 30081\n"
+ "shl16insli r23, r23, 2888\n"
+ "shl16insli r23, r23, 17535\n"
+ "shl16insli r23, r23, -29480\n"
+ "moveli r20, -32745\n"
+ "shl16insli r20, r20, -15929\n"
+ "shl16insli r20, r20, -787\n"
+ "shl16insli r20, r20, 26982\n"
+ "move r20, %2\n"
+ "{ fnop ; ldna_add r23, r20, 11 }\n"
+ "move %0, r23\n"
+ "move %1, r20\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldnt1s_X1.c b/none/tests/tilegx/insn_test_ldnt1s_X1.c
new file mode 100644
index 0000000..99d7d3c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldnt1s_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldnt1s_X1.c
+//op=136
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x25733d8b5dc477b4, 0x820d15cd622148e4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r49, 25551\n"
+ "shl16insli r49, r49, 28722\n"
+ "shl16insli r49, r49, -26847\n"
+ "shl16insli r49, r49, 5345\n"
+ "moveli r33, -29477\n"
+ "shl16insli r33, r33, 10834\n"
+ "shl16insli r33, r33, -26605\n"
+ "shl16insli r33, r33, 14005\n"
+ "move r33, %2\n"
+ "{ fnop ; ldnt1s r49, r33 }\n"
+ "move %0, r49\n"
+ "move %1, r33\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldnt1s_add_X1.c b/none/tests/tilegx/insn_test_ldnt1s_add_X1.c
new file mode 100644
index 0000000..fbd9b49
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldnt1s_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldnt1s_add_X1.c
+//op=137
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe11d6a52db1557dd, 0x601a65b89d0791ab };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r46, -25023\n"
+ "shl16insli r46, r46, 14244\n"
+ "shl16insli r46, r46, -1027\n"
+ "shl16insli r46, r46, 6652\n"
+ "moveli r19, -22946\n"
+ "shl16insli r19, r19, -5784\n"
+ "shl16insli r19, r19, 19718\n"
+ "shl16insli r19, r19, -7802\n"
+ "move r19, %2\n"
+ "{ fnop ; ldnt1s_add r46, r19, -111 }\n"
+ "move %0, r46\n"
+ "move %1, r19\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldnt1u_X1.c b/none/tests/tilegx/insn_test_ldnt1u_X1.c
new file mode 100644
index 0000000..688ceb8
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldnt1u_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldnt1u_X1.c
+//op=138
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x778f2f6f17d9003b, 0x4070076dbab015ca };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r1, 8165\n"
+ "shl16insli r1, r1, 18793\n"
+ "shl16insli r1, r1, -22214\n"
+ "shl16insli r1, r1, 5498\n"
+ "moveli r10, 31115\n"
+ "shl16insli r10, r10, -26645\n"
+ "shl16insli r10, r10, -28059\n"
+ "shl16insli r10, r10, -26401\n"
+ "move r10, %2\n"
+ "{ fnop ; ldnt1u r1, r10 }\n"
+ "move %0, r1\n"
+ "move %1, r10\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldnt1u_add_X1.c b/none/tests/tilegx/insn_test_ldnt1u_add_X1.c
new file mode 100644
index 0000000..30d4d72
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldnt1u_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldnt1u_add_X1.c
+//op=139
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xab1fe60bd5f86c0d, 0xd3191cdcf9681de6 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r32, -30537\n"
+ "shl16insli r32, r32, 27764\n"
+ "shl16insli r32, r32, 16739\n"
+ "shl16insli r32, r32, 8330\n"
+ "moveli r3, -26924\n"
+ "shl16insli r3, r3, -3594\n"
+ "shl16insli r3, r3, -24949\n"
+ "shl16insli r3, r3, 31134\n"
+ "move r3, %2\n"
+ "{ fnop ; ldnt1u_add r32, r3, 90 }\n"
+ "move %0, r32\n"
+ "move %1, r3\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldnt2s_X1.c b/none/tests/tilegx/insn_test_ldnt2s_X1.c
new file mode 100644
index 0000000..e7b7597
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldnt2s_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldnt2s_X1.c
+//op=140
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x455f86368ee6a1bf, 0x3f45dbe8d3bddf1e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r32, 26063\n"
+ "shl16insli r32, r32, 27563\n"
+ "shl16insli r32, r32, 24059\n"
+ "shl16insli r32, r32, -1753\n"
+ "moveli r8, -832\n"
+ "shl16insli r8, r8, -16346\n"
+ "shl16insli r8, r8, -24487\n"
+ "shl16insli r8, r8, 31724\n"
+ "move r8, %2\n"
+ "{ fnop ; ldnt2s r32, r8 }\n"
+ "move %0, r32\n"
+ "move %1, r8\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldnt2s_add_X1.c b/none/tests/tilegx/insn_test_ldnt2s_add_X1.c
new file mode 100644
index 0000000..ee07ed4
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldnt2s_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldnt2s_add_X1.c
+//op=141
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x818b8dda9648095a, 0xa1c9172b9a0d1dac };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r6, 29106\n"
+ "shl16insli r6, r6, 15753\n"
+ "shl16insli r6, r6, -26093\n"
+ "shl16insli r6, r6, -30730\n"
+ "moveli r14, -23898\n"
+ "shl16insli r14, r14, 12060\n"
+ "shl16insli r14, r14, 9181\n"
+ "shl16insli r14, r14, 3478\n"
+ "move r14, %2\n"
+ "{ fnop ; ldnt2s_add r6, r14, 107 }\n"
+ "move %0, r6\n"
+ "move %1, r14\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldnt2u_add_X1.c b/none/tests/tilegx/insn_test_ldnt2u_add_X1.c
new file mode 100644
index 0000000..a67b144
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldnt2u_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldnt2u_add_X1.c
+//op=143
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x59fad680489ec628, 0xc20f490a26161c01 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r30, 16120\n"
+ "shl16insli r30, r30, -22959\n"
+ "shl16insli r30, r30, 22252\n"
+ "shl16insli r30, r30, 172\n"
+ "moveli r2, -28491\n"
+ "shl16insli r2, r2, 5201\n"
+ "shl16insli r2, r2, 4373\n"
+ "shl16insli r2, r2, 26208\n"
+ "move r2, %2\n"
+ "{ fnop ; ldnt2u_add r30, r2, -25 }\n"
+ "move %0, r30\n"
+ "move %1, r2\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldnt4s_X1.c b/none/tests/tilegx/insn_test_ldnt4s_X1.c
new file mode 100644
index 0000000..9e8723c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldnt4s_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldnt4s_X1.c
+//op=144
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xfa50dcf0b044d59a, 0x48fd1654a7e669f7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r41, 26010\n"
+ "shl16insli r41, r41, -10170\n"
+ "shl16insli r41, r41, -10239\n"
+ "shl16insli r41, r41, -24168\n"
+ "moveli r30, 23316\n"
+ "shl16insli r30, r30, 27509\n"
+ "shl16insli r30, r30, 21179\n"
+ "shl16insli r30, r30, 13422\n"
+ "move r30, %2\n"
+ "{ fnop ; ldnt4s r41, r30 }\n"
+ "move %0, r41\n"
+ "move %1, r30\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldnt4s_add_X1.c b/none/tests/tilegx/insn_test_ldnt4s_add_X1.c
new file mode 100644
index 0000000..4ee1a41
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldnt4s_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldnt4s_add_X1.c
+//op=145
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd6233f383d6fcac4, 0xa3f745ffc94270b2 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r17, 20154\n"
+ "shl16insli r17, r17, -1171\n"
+ "shl16insli r17, r17, 18338\n"
+ "shl16insli r17, r17, -23205\n"
+ "moveli r32, -21605\n"
+ "shl16insli r32, r32, -21137\n"
+ "shl16insli r32, r32, 22949\n"
+ "shl16insli r32, r32, -13067\n"
+ "move r32, %2\n"
+ "{ fnop ; ldnt4s_add r17, r32, 77 }\n"
+ "move %0, r17\n"
+ "move %1, r32\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldnt4u_X1.c b/none/tests/tilegx/insn_test_ldnt4u_X1.c
new file mode 100644
index 0000000..9c2fc26
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldnt4u_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldnt4u_X1.c
+//op=146
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x52c49809e5465b06, 0xea70c8b3ffd336c3 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r14, 27619\n"
+ "shl16insli r14, r14, 17289\n"
+ "shl16insli r14, r14, 12105\n"
+ "shl16insli r14, r14, -30968\n"
+ "moveli r34, -1549\n"
+ "shl16insli r34, r34, 17842\n"
+ "shl16insli r34, r34, 24501\n"
+ "shl16insli r34, r34, -29822\n"
+ "move r34, %2\n"
+ "{ fnop ; ldnt4u r14, r34 }\n"
+ "move %0, r14\n"
+ "move %1, r34\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldnt4u_add_X1.c b/none/tests/tilegx/insn_test_ldnt4u_add_X1.c
new file mode 100644
index 0000000..72e70cd
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldnt4u_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldnt4u_add_X1.c
+//op=147
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5d9ea0967d2b4507, 0x65938abe343c4eed };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r19, -26655\n"
+ "shl16insli r19, r19, 14881\n"
+ "shl16insli r19, r19, 22810\n"
+ "shl16insli r19, r19, 12324\n"
+ "moveli r9, 10449\n"
+ "shl16insli r9, r9, -23499\n"
+ "shl16insli r9, r9, -25395\n"
+ "shl16insli r9, r9, 17474\n"
+ "move r9, %2\n"
+ "{ fnop ; ldnt4u_add r19, r9, -95 }\n"
+ "move %0, r19\n"
+ "move %1, r9\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldnt_X1.c b/none/tests/tilegx/insn_test_ldnt_X1.c
new file mode 100644
index 0000000..d8ca7c9
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldnt_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldnt_X1.c
+//op=135
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x8f37eee6381b10aa, 0xa536cafeb2fbe757 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r18, -5987\n"
+ "shl16insli r18, r18, -16935\n"
+ "shl16insli r18, r18, 638\n"
+ "shl16insli r18, r18, 32300\n"
+ "moveli r2, -15250\n"
+ "shl16insli r2, r2, 18129\n"
+ "shl16insli r2, r2, -22479\n"
+ "shl16insli r2, r2, 7405\n"
+ "move r2, %2\n"
+ "{ fnop ; ldnt r18, r2 }\n"
+ "move %0, r18\n"
+ "move %1, r2\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ldnt_add_X1.c b/none/tests/tilegx/insn_test_ldnt_add_X1.c
new file mode 100644
index 0000000..2638a7c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ldnt_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_ldnt_add_X1.c
+//op=148
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd67c5353b4f83951, 0x68fb6e92c7467995 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, -10637\n"
+ "shl16insli r34, r34, -13587\n"
+ "shl16insli r34, r34, 6072\n"
+ "shl16insli r34, r34, -2381\n"
+ "moveli r42, -31836\n"
+ "shl16insli r42, r42, -15605\n"
+ "shl16insli r42, r42, -32767\n"
+ "shl16insli r42, r42, -3062\n"
+ "move r42, %2\n"
+ "{ fnop ; ldnt_add r34, r42, 11 }\n"
+ "move %0, r34\n"
+ "move %1, r42\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_lnk_X1.c b/none/tests/tilegx/insn_test_lnk_X1.c
new file mode 100644
index 0000000..e93fca6
--- /dev/null
+++ b/none/tests/tilegx/insn_test_lnk_X1.c
@@ -0,0 +1,30 @@
+//file: _insn_test_lnk_X1.c
+//op=149
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x74d04934d1d15274, 0xd270fbfbde298322 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r26, -23588\n"
+ "shl16insli r26, r26, 9244\n"
+ "shl16insli r26, r26, 32109\n"
+ "shl16insli r26, r26, -30144\n"
+ "{ fnop ; lnk r26 }\n"
+ "move %0, r26\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_lnk_Y1.c b/none/tests/tilegx/insn_test_lnk_Y1.c
new file mode 100644
index 0000000..fe34ffd
--- /dev/null
+++ b/none/tests/tilegx/insn_test_lnk_Y1.c
@@ -0,0 +1,30 @@
+//file: _insn_test_lnk_Y1.c
+//op=149
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x74d04934d1d15274, 0xd270fbfbde298322 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r26, -23588\n"
+ "shl16insli r26, r26, 9244\n"
+ "shl16insli r26, r26, 32109\n"
+ "shl16insli r26, r26, -30144\n"
+ "{ fnop ; lnk r26 ; ld r63, r54 }\n"
+ "move %0, r26\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mf_X1.c b/none/tests/tilegx/insn_test_mf_X1.c
new file mode 100644
index 0000000..ccf9c8b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mf_X1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_mf_X1.c
+//op=150
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x95953511f9ee4512, 0x52148e33ddfabfa8 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "{ fnop ; mf }\n"
+ );
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mm_X0.c b/none/tests/tilegx/insn_test_mm_X0.c
new file mode 100644
index 0000000..1500c60
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mm_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_mm_X0.c
+//op=152
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9d9b78ac30042683, 0xb17341a0d542c8a8 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r24, -8310\n"
+ "shl16insli r24, r24, -28931\n"
+ "shl16insli r24, r24, 16317\n"
+ "shl16insli r24, r24, -2081\n"
+ "moveli r31, -8094\n"
+ "shl16insli r31, r31, -3077\n"
+ "shl16insli r31, r31, 14718\n"
+ "shl16insli r31, r31, -8598\n"
+ "{ mm r24, r31, 34, 41 ; fnop }\n"
+ "move %0, r24\n"
+ "move %1, r31\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mnz_X0.c b/none/tests/tilegx/insn_test_mnz_X0.c
new file mode 100644
index 0000000..07ff1c6
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mnz_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mnz_X0.c
+//op=153
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc8c9da0e90770658, 0x3dce75e113642c2b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, 24848\n"
+ "shl16insli r11, r11, -12444\n"
+ "shl16insli r11, r11, -9823\n"
+ "shl16insli r11, r11, -18157\n"
+ "moveli r30, 11291\n"
+ "shl16insli r30, r30, -29222\n"
+ "shl16insli r30, r30, 27249\n"
+ "shl16insli r30, r30, -15038\n"
+ "moveli r22, 31329\n"
+ "shl16insli r22, r22, 2611\n"
+ "shl16insli r22, r22, -21984\n"
+ "shl16insli r22, r22, -27173\n"
+ "{ mnz r11, r30, r22 ; fnop }\n"
+ "move %0, r11\n"
+ "move %1, r30\n"
+ "move %2, r22\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mnz_X1.c b/none/tests/tilegx/insn_test_mnz_X1.c
new file mode 100644
index 0000000..a061ada
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mnz_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mnz_X1.c
+//op=153
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc8c9da0e90770658, 0x3dce75e113642c2b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, 24848\n"
+ "shl16insli r11, r11, -12444\n"
+ "shl16insli r11, r11, -9823\n"
+ "shl16insli r11, r11, -18157\n"
+ "moveli r30, 11291\n"
+ "shl16insli r30, r30, -29222\n"
+ "shl16insli r30, r30, 27249\n"
+ "shl16insli r30, r30, -15038\n"
+ "moveli r22, 31329\n"
+ "shl16insli r22, r22, 2611\n"
+ "shl16insli r22, r22, -21984\n"
+ "shl16insli r22, r22, -27173\n"
+ "{ fnop ; mnz r11, r30, r22 }\n"
+ "move %0, r11\n"
+ "move %1, r30\n"
+ "move %2, r22\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mnz_Y0.c b/none/tests/tilegx/insn_test_mnz_Y0.c
new file mode 100644
index 0000000..858a94a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mnz_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mnz_Y0.c
+//op=153
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc8c9da0e90770658, 0x3dce75e113642c2b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, 24848\n"
+ "shl16insli r11, r11, -12444\n"
+ "shl16insli r11, r11, -9823\n"
+ "shl16insli r11, r11, -18157\n"
+ "moveli r30, 11291\n"
+ "shl16insli r30, r30, -29222\n"
+ "shl16insli r30, r30, 27249\n"
+ "shl16insli r30, r30, -15038\n"
+ "moveli r22, 31329\n"
+ "shl16insli r22, r22, 2611\n"
+ "shl16insli r22, r22, -21984\n"
+ "shl16insli r22, r22, -27173\n"
+ "{ mnz r11, r30, r22 ; fnop ; ld r63, r54 }\n"
+ "move %0, r11\n"
+ "move %1, r30\n"
+ "move %2, r22\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mnz_Y1.c b/none/tests/tilegx/insn_test_mnz_Y1.c
new file mode 100644
index 0000000..36b8cc5
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mnz_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mnz_Y1.c
+//op=153
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc8c9da0e90770658, 0x3dce75e113642c2b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, 24848\n"
+ "shl16insli r11, r11, -12444\n"
+ "shl16insli r11, r11, -9823\n"
+ "shl16insli r11, r11, -18157\n"
+ "moveli r30, 11291\n"
+ "shl16insli r30, r30, -29222\n"
+ "shl16insli r30, r30, 27249\n"
+ "shl16insli r30, r30, -15038\n"
+ "moveli r22, 31329\n"
+ "shl16insli r22, r22, 2611\n"
+ "shl16insli r22, r22, -21984\n"
+ "shl16insli r22, r22, -27173\n"
+ "{ fnop ; mnz r11, r30, r22 ; ld r63, r54 }\n"
+ "move %0, r11\n"
+ "move %1, r30\n"
+ "move %2, r22\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_move_X0.c b/none/tests/tilegx/insn_test_move_X0.c
new file mode 100644
index 0000000..d7a3b41
--- /dev/null
+++ b/none/tests/tilegx/insn_test_move_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_move_X0.c
+//op=5
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbccc64192e474b2d, 0xae4a1eebcf0aa6f1 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, -6666\n"
+ "shl16insli r22, r22, 9055\n"
+ "shl16insli r22, r22, 10215\n"
+ "shl16insli r22, r22, -15289\n"
+ "moveli r35, -17246\n"
+ "shl16insli r35, r35, 164\n"
+ "shl16insli r35, r35, 31728\n"
+ "shl16insli r35, r35, -28689\n"
+ "{ move r22, r35 ; fnop }\n"
+ "move %0, r22\n"
+ "move %1, r35\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_move_X1.c b/none/tests/tilegx/insn_test_move_X1.c
new file mode 100644
index 0000000..10bffd9
--- /dev/null
+++ b/none/tests/tilegx/insn_test_move_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_move_X1.c
+//op=5
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbccc64192e474b2d, 0xae4a1eebcf0aa6f1 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, -6666\n"
+ "shl16insli r22, r22, 9055\n"
+ "shl16insli r22, r22, 10215\n"
+ "shl16insli r22, r22, -15289\n"
+ "moveli r35, -17246\n"
+ "shl16insli r35, r35, 164\n"
+ "shl16insli r35, r35, 31728\n"
+ "shl16insli r35, r35, -28689\n"
+ "{ fnop ; move r22, r35 }\n"
+ "move %0, r22\n"
+ "move %1, r35\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_move_Y0.c b/none/tests/tilegx/insn_test_move_Y0.c
new file mode 100644
index 0000000..c9e3682
--- /dev/null
+++ b/none/tests/tilegx/insn_test_move_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_move_Y0.c
+//op=5
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbccc64192e474b2d, 0xae4a1eebcf0aa6f1 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, -6666\n"
+ "shl16insli r22, r22, 9055\n"
+ "shl16insli r22, r22, 10215\n"
+ "shl16insli r22, r22, -15289\n"
+ "moveli r35, -17246\n"
+ "shl16insli r35, r35, 164\n"
+ "shl16insli r35, r35, 31728\n"
+ "shl16insli r35, r35, -28689\n"
+ "{ move r22, r35 ; fnop ; ld r63, r54 }\n"
+ "move %0, r22\n"
+ "move %1, r35\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_move_Y1.c b/none/tests/tilegx/insn_test_move_Y1.c
new file mode 100644
index 0000000..30a6ca7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_move_Y1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_move_Y1.c
+//op=5
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbccc64192e474b2d, 0xae4a1eebcf0aa6f1 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, -6666\n"
+ "shl16insli r22, r22, 9055\n"
+ "shl16insli r22, r22, 10215\n"
+ "shl16insli r22, r22, -15289\n"
+ "moveli r35, -17246\n"
+ "shl16insli r35, r35, 164\n"
+ "shl16insli r35, r35, 31728\n"
+ "shl16insli r35, r35, -28689\n"
+ "{ fnop ; move r22, r35 ; ld r63, r54 }\n"
+ "move %0, r22\n"
+ "move %1, r35\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_movei_X0.c b/none/tests/tilegx/insn_test_movei_X0.c
new file mode 100644
index 0000000..bbef693
--- /dev/null
+++ b/none/tests/tilegx/insn_test_movei_X0.c
@@ -0,0 +1,30 @@
+//file: _insn_test_movei_X0.c
+//op=6
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd65eb4d9fa5bdd9a, 0x1c0a7303af5ad0fd };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -24632\n"
+ "shl16insli r38, r38, -1299\n"
+ "shl16insli r38, r38, 29324\n"
+ "shl16insli r38, r38, -18232\n"
+ "{ movei r38, -17 ; fnop }\n"
+ "move %0, r38\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_movei_X1.c b/none/tests/tilegx/insn_test_movei_X1.c
new file mode 100644
index 0000000..65878b7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_movei_X1.c
@@ -0,0 +1,30 @@
+//file: _insn_test_movei_X1.c
+//op=6
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd65eb4d9fa5bdd9a, 0x1c0a7303af5ad0fd };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -24632\n"
+ "shl16insli r38, r38, -1299\n"
+ "shl16insli r38, r38, 29324\n"
+ "shl16insli r38, r38, -18232\n"
+ "{ fnop ; movei r38, -17 }\n"
+ "move %0, r38\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_movei_Y0.c b/none/tests/tilegx/insn_test_movei_Y0.c
new file mode 100644
index 0000000..7455ae6
--- /dev/null
+++ b/none/tests/tilegx/insn_test_movei_Y0.c
@@ -0,0 +1,30 @@
+//file: _insn_test_movei_Y0.c
+//op=6
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd65eb4d9fa5bdd9a, 0x1c0a7303af5ad0fd };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -24632\n"
+ "shl16insli r38, r38, -1299\n"
+ "shl16insli r38, r38, 29324\n"
+ "shl16insli r38, r38, -18232\n"
+ "{ movei r38, -17 ; fnop ; ld r63, r54 }\n"
+ "move %0, r38\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_movei_Y1.c b/none/tests/tilegx/insn_test_movei_Y1.c
new file mode 100644
index 0000000..ecdd4c0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_movei_Y1.c
@@ -0,0 +1,30 @@
+//file: _insn_test_movei_Y1.c
+//op=6
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd65eb4d9fa5bdd9a, 0x1c0a7303af5ad0fd };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -24632\n"
+ "shl16insli r38, r38, -1299\n"
+ "shl16insli r38, r38, 29324\n"
+ "shl16insli r38, r38, -18232\n"
+ "{ fnop ; movei r38, -17 ; ld r63, r54 }\n"
+ "move %0, r38\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_moveli_X0.c b/none/tests/tilegx/insn_test_moveli_X0.c
new file mode 100644
index 0000000..7d4fabf
--- /dev/null
+++ b/none/tests/tilegx/insn_test_moveli_X0.c
@@ -0,0 +1,30 @@
+//file: _insn_test_moveli_X0.c
+//op=7
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4448037363c51f9a, 0xd2e5cb4994058d63 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r45, -7137\n"
+ "shl16insli r45, r45, 897\n"
+ "shl16insli r45, r45, 23961\n"
+ "shl16insli r45, r45, -21354\n"
+ "{ moveli r45, -15765 ; fnop }\n"
+ "move %0, r45\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_moveli_X1.c b/none/tests/tilegx/insn_test_moveli_X1.c
new file mode 100644
index 0000000..6114841
--- /dev/null
+++ b/none/tests/tilegx/insn_test_moveli_X1.c
@@ -0,0 +1,30 @@
+//file: _insn_test_moveli_X1.c
+//op=7
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4448037363c51f9a, 0xd2e5cb4994058d63 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r45, -7137\n"
+ "shl16insli r45, r45, 897\n"
+ "shl16insli r45, r45, 23961\n"
+ "shl16insli r45, r45, -21354\n"
+ "{ fnop ; moveli r45, -15765 }\n"
+ "move %0, r45\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mul_hs_hs_X0.c b/none/tests/tilegx/insn_test_mul_hs_hs_X0.c
new file mode 100644
index 0000000..62e1afd
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mul_hs_hs_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mul_hs_hs_X0.c
+//op=155
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc707c0e7f8704eba, 0x1518d5b56d04d8a5 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r39, 2892\n"
+ "shl16insli r39, r39, -15734\n"
+ "shl16insli r39, r39, -18162\n"
+ "shl16insli r39, r39, -30153\n"
+ "moveli r32, 31894\n"
+ "shl16insli r32, r32, -18512\n"
+ "shl16insli r32, r32, 13763\n"
+ "shl16insli r32, r32, -9785\n"
+ "moveli r18, 14299\n"
+ "shl16insli r18, r18, -16601\n"
+ "shl16insli r18, r18, -30080\n"
+ "shl16insli r18, r18, 10179\n"
+ "{ mul_hs_hs r39, r32, r18 ; fnop }\n"
+ "move %0, r39\n"
+ "move %1, r32\n"
+ "move %2, r18\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mul_hs_hs_Y0.c b/none/tests/tilegx/insn_test_mul_hs_hs_Y0.c
new file mode 100644
index 0000000..8d4f536
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mul_hs_hs_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mul_hs_hs_Y0.c
+//op=155
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc707c0e7f8704eba, 0x1518d5b56d04d8a5 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r39, 2892\n"
+ "shl16insli r39, r39, -15734\n"
+ "shl16insli r39, r39, -18162\n"
+ "shl16insli r39, r39, -30153\n"
+ "moveli r32, 31894\n"
+ "shl16insli r32, r32, -18512\n"
+ "shl16insli r32, r32, 13763\n"
+ "shl16insli r32, r32, -9785\n"
+ "moveli r18, 14299\n"
+ "shl16insli r18, r18, -16601\n"
+ "shl16insli r18, r18, -30080\n"
+ "shl16insli r18, r18, 10179\n"
+ "{ mul_hs_hs r39, r32, r18 ; fnop ; ld r63, r54 }\n"
+ "move %0, r39\n"
+ "move %1, r32\n"
+ "move %2, r18\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mul_hs_hu_X0.c b/none/tests/tilegx/insn_test_mul_hs_hu_X0.c
new file mode 100644
index 0000000..19ae691
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mul_hs_hu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mul_hs_hu_X0.c
+//op=156
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x31d131ae6b7da416, 0x3e01995aa9302c9b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r35, 4550\n"
+ "shl16insli r35, r35, 29355\n"
+ "shl16insli r35, r35, 30941\n"
+ "shl16insli r35, r35, 29755\n"
+ "moveli r7, -18630\n"
+ "shl16insli r7, r7, -31252\n"
+ "shl16insli r7, r7, -15964\n"
+ "shl16insli r7, r7, 8400\n"
+ "moveli r22, 29514\n"
+ "shl16insli r22, r22, 14828\n"
+ "shl16insli r22, r22, 1013\n"
+ "shl16insli r22, r22, 14302\n"
+ "{ mul_hs_hu r35, r7, r22 ; fnop }\n"
+ "move %0, r35\n"
+ "move %1, r7\n"
+ "move %2, r22\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mul_hs_ls_X0.c b/none/tests/tilegx/insn_test_mul_hs_ls_X0.c
new file mode 100644
index 0000000..a8a31c4
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mul_hs_ls_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mul_hs_ls_X0.c
+//op=157
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc2cac20f9054ab64, 0xc57bfb2ed874d267 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, 30145\n"
+ "shl16insli r22, r22, 20983\n"
+ "shl16insli r22, r22, 7997\n"
+ "shl16insli r22, r22, -21347\n"
+ "moveli r0, 3083\n"
+ "shl16insli r0, r0, -6125\n"
+ "shl16insli r0, r0, -10642\n"
+ "shl16insli r0, r0, 872\n"
+ "moveli r19, -14850\n"
+ "shl16insli r19, r19, -32360\n"
+ "shl16insli r19, r19, 12889\n"
+ "shl16insli r19, r19, 3288\n"
+ "{ mul_hs_ls r22, r0, r19 ; fnop }\n"
+ "move %0, r22\n"
+ "move %1, r0\n"
+ "move %2, r19\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mul_hs_lu_X0.c b/none/tests/tilegx/insn_test_mul_hs_lu_X0.c
new file mode 100644
index 0000000..69eb7f3
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mul_hs_lu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mul_hs_lu_X0.c
+//op=158
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x194c873261582759, 0x910a2955c6e71b1 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r6, 31890\n"
+ "shl16insli r6, r6, 22503\n"
+ "shl16insli r6, r6, 26461\n"
+ "shl16insli r6, r6, -16338\n"
+ "moveli r25, 31333\n"
+ "shl16insli r25, r25, 15554\n"
+ "shl16insli r25, r25, 16035\n"
+ "shl16insli r25, r25, -6284\n"
+ "moveli r17, -19874\n"
+ "shl16insli r17, r17, -32652\n"
+ "shl16insli r17, r17, -27551\n"
+ "shl16insli r17, r17, 14010\n"
+ "{ mul_hs_lu r6, r25, r17 ; fnop }\n"
+ "move %0, r6\n"
+ "move %1, r25\n"
+ "move %2, r17\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mul_hu_hu_X0.c b/none/tests/tilegx/insn_test_mul_hu_hu_X0.c
new file mode 100644
index 0000000..5bf53bd
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mul_hu_hu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mul_hu_hu_X0.c
+//op=159
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2f10bc93a323ca0d, 0x9be2dc4ee83ae1ea };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r18, -11405\n"
+ "shl16insli r18, r18, -6947\n"
+ "shl16insli r18, r18, 19133\n"
+ "shl16insli r18, r18, -19900\n"
+ "moveli r27, 31983\n"
+ "shl16insli r27, r27, 16872\n"
+ "shl16insli r27, r27, 25578\n"
+ "shl16insli r27, r27, 12902\n"
+ "moveli r10, 20609\n"
+ "shl16insli r10, r10, -28665\n"
+ "shl16insli r10, r10, -5637\n"
+ "shl16insli r10, r10, -7979\n"
+ "{ mul_hu_hu r18, r27, r10 ; fnop }\n"
+ "move %0, r18\n"
+ "move %1, r27\n"
+ "move %2, r10\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mul_hu_hu_Y0.c b/none/tests/tilegx/insn_test_mul_hu_hu_Y0.c
new file mode 100644
index 0000000..ede94dd
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mul_hu_hu_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mul_hu_hu_Y0.c
+//op=159
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2f10bc93a323ca0d, 0x9be2dc4ee83ae1ea };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r18, -11405\n"
+ "shl16insli r18, r18, -6947\n"
+ "shl16insli r18, r18, 19133\n"
+ "shl16insli r18, r18, -19900\n"
+ "moveli r27, 31983\n"
+ "shl16insli r27, r27, 16872\n"
+ "shl16insli r27, r27, 25578\n"
+ "shl16insli r27, r27, 12902\n"
+ "moveli r10, 20609\n"
+ "shl16insli r10, r10, -28665\n"
+ "shl16insli r10, r10, -5637\n"
+ "shl16insli r10, r10, -7979\n"
+ "{ mul_hu_hu r18, r27, r10 ; fnop ; ld r63, r54 }\n"
+ "move %0, r18\n"
+ "move %1, r27\n"
+ "move %2, r10\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mul_hu_lu_X0.c b/none/tests/tilegx/insn_test_mul_hu_lu_X0.c
new file mode 100644
index 0000000..cae7ebd
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mul_hu_lu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mul_hu_lu_X0.c
+//op=161
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4639d63ca03e5e4e, 0x5e51bd49489c060d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r10, -11099\n"
+ "shl16insli r10, r10, 22725\n"
+ "shl16insli r10, r10, -18659\n"
+ "shl16insli r10, r10, 28990\n"
+ "moveli r19, -7114\n"
+ "shl16insli r19, r19, -4623\n"
+ "shl16insli r19, r19, 4807\n"
+ "shl16insli r19, r19, -17110\n"
+ "moveli r31, 5393\n"
+ "shl16insli r31, r31, -22253\n"
+ "shl16insli r31, r31, 25749\n"
+ "shl16insli r31, r31, -7203\n"
+ "{ mul_hu_lu r10, r19, r31 ; fnop }\n"
+ "move %0, r10\n"
+ "move %1, r19\n"
+ "move %2, r31\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mul_ls_ls_X0.c b/none/tests/tilegx/insn_test_mul_ls_ls_X0.c
new file mode 100644
index 0000000..b9f0bf0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mul_ls_ls_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mul_ls_ls_X0.c
+//op=162
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x228e8e83b7561e89, 0x175f6b2301c3969d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r33, 9145\n"
+ "shl16insli r33, r33, 16129\n"
+ "shl16insli r33, r33, -28988\n"
+ "shl16insli r33, r33, -28265\n"
+ "moveli r47, -17072\n"
+ "shl16insli r47, r47, 26742\n"
+ "shl16insli r47, r47, -10023\n"
+ "shl16insli r47, r47, -32380\n"
+ "moveli r19, 7549\n"
+ "shl16insli r19, r19, -19041\n"
+ "shl16insli r19, r19, -30505\n"
+ "shl16insli r19, r19, -15011\n"
+ "{ mul_ls_ls r33, r47, r19 ; fnop }\n"
+ "move %0, r33\n"
+ "move %1, r47\n"
+ "move %2, r19\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mul_ls_ls_Y0.c b/none/tests/tilegx/insn_test_mul_ls_ls_Y0.c
new file mode 100644
index 0000000..84ad175
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mul_ls_ls_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mul_ls_ls_Y0.c
+//op=162
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x228e8e83b7561e89, 0x175f6b2301c3969d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r33, 9145\n"
+ "shl16insli r33, r33, 16129\n"
+ "shl16insli r33, r33, -28988\n"
+ "shl16insli r33, r33, -28265\n"
+ "moveli r47, -17072\n"
+ "shl16insli r47, r47, 26742\n"
+ "shl16insli r47, r47, -10023\n"
+ "shl16insli r47, r47, -32380\n"
+ "moveli r19, 7549\n"
+ "shl16insli r19, r19, -19041\n"
+ "shl16insli r19, r19, -30505\n"
+ "shl16insli r19, r19, -15011\n"
+ "{ mul_ls_ls r33, r47, r19 ; fnop ; ld r63, r54 }\n"
+ "move %0, r33\n"
+ "move %1, r47\n"
+ "move %2, r19\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mul_ls_lu_X0.c b/none/tests/tilegx/insn_test_mul_ls_lu_X0.c
new file mode 100644
index 0000000..2808862
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mul_ls_lu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mul_ls_lu_X0.c
+//op=163
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xcdce8cd30da8f45b, 0x85932185df148d8d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r2, -19516\n"
+ "shl16insli r2, r2, -21805\n"
+ "shl16insli r2, r2, -31810\n"
+ "shl16insli r2, r2, 31088\n"
+ "moveli r32, 3846\n"
+ "shl16insli r32, r32, -1507\n"
+ "shl16insli r32, r32, -17183\n"
+ "shl16insli r32, r32, -527\n"
+ "moveli r4, 25062\n"
+ "shl16insli r4, r4, -3688\n"
+ "shl16insli r4, r4, 15670\n"
+ "shl16insli r4, r4, 15480\n"
+ "{ mul_ls_lu r2, r32, r4 ; fnop }\n"
+ "move %0, r2\n"
+ "move %1, r32\n"
+ "move %2, r4\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mul_lu_lu_X0.c b/none/tests/tilegx/insn_test_mul_lu_lu_X0.c
new file mode 100644
index 0000000..89ed777
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mul_lu_lu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mul_lu_lu_X0.c
+//op=164
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd75570c277b73b03, 0x5ff5d41ce72b342e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r24, 10847\n"
+ "shl16insli r24, r24, -21273\n"
+ "shl16insli r24, r24, -26560\n"
+ "shl16insli r24, r24, -2137\n"
+ "moveli r22, -4257\n"
+ "shl16insli r22, r22, 16637\n"
+ "shl16insli r22, r22, -13862\n"
+ "shl16insli r22, r22, 2993\n"
+ "moveli r2, 2928\n"
+ "shl16insli r2, r2, -22351\n"
+ "shl16insli r2, r2, 15965\n"
+ "shl16insli r2, r2, -15676\n"
+ "{ mul_lu_lu r24, r22, r2 ; fnop }\n"
+ "move %0, r24\n"
+ "move %1, r22\n"
+ "move %2, r2\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mul_lu_lu_Y0.c b/none/tests/tilegx/insn_test_mul_lu_lu_Y0.c
new file mode 100644
index 0000000..9119189
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mul_lu_lu_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mul_lu_lu_Y0.c
+//op=164
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd75570c277b73b03, 0x5ff5d41ce72b342e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r24, 10847\n"
+ "shl16insli r24, r24, -21273\n"
+ "shl16insli r24, r24, -26560\n"
+ "shl16insli r24, r24, -2137\n"
+ "moveli r22, -4257\n"
+ "shl16insli r22, r22, 16637\n"
+ "shl16insli r22, r22, -13862\n"
+ "shl16insli r22, r22, 2993\n"
+ "moveli r2, 2928\n"
+ "shl16insli r2, r2, -22351\n"
+ "shl16insli r2, r2, 15965\n"
+ "shl16insli r2, r2, -15676\n"
+ "{ mul_lu_lu r24, r22, r2 ; fnop ; ld r63, r54 }\n"
+ "move %0, r24\n"
+ "move %1, r22\n"
+ "move %2, r2\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mula_hs_hs_X0.c b/none/tests/tilegx/insn_test_mula_hs_hs_X0.c
new file mode 100644
index 0000000..ba063d6
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mula_hs_hs_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mula_hs_hs_X0.c
+//op=165
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xec7e102d827fb085, 0x2fbb511bf652c89f };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r42, -23610\n"
+ "shl16insli r42, r42, -23703\n"
+ "shl16insli r42, r42, 2719\n"
+ "shl16insli r42, r42, -32635\n"
+ "moveli r11, 21737\n"
+ "shl16insli r11, r11, 21508\n"
+ "shl16insli r11, r11, 4642\n"
+ "shl16insli r11, r11, -1298\n"
+ "moveli r45, 16489\n"
+ "shl16insli r45, r45, 1852\n"
+ "shl16insli r45, r45, -22328\n"
+ "shl16insli r45, r45, -20016\n"
+ "{ mula_hs_hs r42, r11, r45 ; fnop }\n"
+ "move %0, r42\n"
+ "move %1, r11\n"
+ "move %2, r45\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mula_hs_hs_Y0.c b/none/tests/tilegx/insn_test_mula_hs_hs_Y0.c
new file mode 100644
index 0000000..c932dcc
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mula_hs_hs_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mula_hs_hs_Y0.c
+//op=165
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xec7e102d827fb085, 0x2fbb511bf652c89f };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r42, -23610\n"
+ "shl16insli r42, r42, -23703\n"
+ "shl16insli r42, r42, 2719\n"
+ "shl16insli r42, r42, -32635\n"
+ "moveli r11, 21737\n"
+ "shl16insli r11, r11, 21508\n"
+ "shl16insli r11, r11, 4642\n"
+ "shl16insli r11, r11, -1298\n"
+ "moveli r45, 16489\n"
+ "shl16insli r45, r45, 1852\n"
+ "shl16insli r45, r45, -22328\n"
+ "shl16insli r45, r45, -20016\n"
+ "{ mula_hs_hs r42, r11, r45 ; fnop ; ld r63, r54 }\n"
+ "move %0, r42\n"
+ "move %1, r11\n"
+ "move %2, r45\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mula_hs_hu_X0.c b/none/tests/tilegx/insn_test_mula_hs_hu_X0.c
new file mode 100644
index 0000000..173128b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mula_hs_hu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mula_hs_hu_X0.c
+//op=166
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x269cb922a1bf2c20, 0x57b488292bdd9c2b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r30, 4246\n"
+ "shl16insli r30, r30, 6079\n"
+ "shl16insli r30, r30, 8698\n"
+ "shl16insli r30, r30, -2697\n"
+ "moveli r29, 27899\n"
+ "shl16insli r29, r29, -1363\n"
+ "shl16insli r29, r29, 695\n"
+ "shl16insli r29, r29, -3150\n"
+ "moveli r29, -29126\n"
+ "shl16insli r29, r29, -20326\n"
+ "shl16insli r29, r29, 27689\n"
+ "shl16insli r29, r29, 15548\n"
+ "{ mula_hs_hu r30, r29, r29 ; fnop }\n"
+ "move %0, r30\n"
+ "move %1, r29\n"
+ "move %2, r29\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mula_hs_ls_X0.c b/none/tests/tilegx/insn_test_mula_hs_ls_X0.c
new file mode 100644
index 0000000..3b0f9ed
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mula_hs_ls_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mula_hs_ls_X0.c
+//op=167
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x334d1321b4c11950, 0x4406ad0fa9c44e77 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r37, 47\n"
+ "shl16insli r37, r37, 27756\n"
+ "shl16insli r37, r37, -285\n"
+ "shl16insli r37, r37, 5847\n"
+ "moveli r14, -22393\n"
+ "shl16insli r14, r14, -5429\n"
+ "shl16insli r14, r14, -14300\n"
+ "shl16insli r14, r14, 11616\n"
+ "moveli r1, 31370\n"
+ "shl16insli r1, r1, -7442\n"
+ "shl16insli r1, r1, 26409\n"
+ "shl16insli r1, r1, 25903\n"
+ "{ mula_hs_ls r37, r14, r1 ; fnop }\n"
+ "move %0, r37\n"
+ "move %1, r14\n"
+ "move %2, r1\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mula_hs_lu_X0.c b/none/tests/tilegx/insn_test_mula_hs_lu_X0.c
new file mode 100644
index 0000000..8279c24
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mula_hs_lu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mula_hs_lu_X0.c
+//op=168
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf64e075b02f515ca, 0xdff35e384e663195 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r45, -4690\n"
+ "shl16insli r45, r45, 18437\n"
+ "shl16insli r45, r45, 14549\n"
+ "shl16insli r45, r45, -22291\n"
+ "moveli r7, 15584\n"
+ "shl16insli r7, r7, -16025\n"
+ "shl16insli r7, r7, 24621\n"
+ "shl16insli r7, r7, -25450\n"
+ "moveli r2, -16204\n"
+ "shl16insli r2, r2, -989\n"
+ "shl16insli r2, r2, -29843\n"
+ "shl16insli r2, r2, -32026\n"
+ "{ mula_hs_lu r45, r7, r2 ; fnop }\n"
+ "move %0, r45\n"
+ "move %1, r7\n"
+ "move %2, r2\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mula_hu_hu_X0.c b/none/tests/tilegx/insn_test_mula_hu_hu_X0.c
new file mode 100644
index 0000000..52429d7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mula_hu_hu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mula_hu_hu_X0.c
+//op=169
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa479dc4ef3600b13, 0x286401a31761e02a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r0, -9560\n"
+ "shl16insli r0, r0, 27577\n"
+ "shl16insli r0, r0, -8798\n"
+ "shl16insli r0, r0, 25385\n"
+ "moveli r47, -17024\n"
+ "shl16insli r47, r47, -8491\n"
+ "shl16insli r47, r47, 31461\n"
+ "shl16insli r47, r47, -10531\n"
+ "moveli r35, 13663\n"
+ "shl16insli r35, r35, 11635\n"
+ "shl16insli r35, r35, -24944\n"
+ "shl16insli r35, r35, -3616\n"
+ "{ mula_hu_hu r0, r47, r35 ; fnop }\n"
+ "move %0, r0\n"
+ "move %1, r47\n"
+ "move %2, r35\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mula_hu_hu_Y0.c b/none/tests/tilegx/insn_test_mula_hu_hu_Y0.c
new file mode 100644
index 0000000..54d848c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mula_hu_hu_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mula_hu_hu_Y0.c
+//op=169
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa479dc4ef3600b13, 0x286401a31761e02a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r0, -9560\n"
+ "shl16insli r0, r0, 27577\n"
+ "shl16insli r0, r0, -8798\n"
+ "shl16insli r0, r0, 25385\n"
+ "moveli r47, -17024\n"
+ "shl16insli r47, r47, -8491\n"
+ "shl16insli r47, r47, 31461\n"
+ "shl16insli r47, r47, -10531\n"
+ "moveli r35, 13663\n"
+ "shl16insli r35, r35, 11635\n"
+ "shl16insli r35, r35, -24944\n"
+ "shl16insli r35, r35, -3616\n"
+ "{ mula_hu_hu r0, r47, r35 ; fnop ; ld r63, r54 }\n"
+ "move %0, r0\n"
+ "move %1, r47\n"
+ "move %2, r35\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mula_hu_ls_X0.c b/none/tests/tilegx/insn_test_mula_hu_ls_X0.c
new file mode 100644
index 0000000..db45f92
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mula_hu_ls_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mula_hu_ls_X0.c
+//op=170
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7c2b00bc8a60c95d, 0x8a6bdf08a51f10d3 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, -8315\n"
+ "shl16insli r22, r22, 5404\n"
+ "shl16insli r22, r22, 15177\n"
+ "shl16insli r22, r22, -6931\n"
+ "moveli r12, -20178\n"
+ "shl16insli r12, r12, 16109\n"
+ "shl16insli r12, r12, -17955\n"
+ "shl16insli r12, r12, 766\n"
+ "moveli r43, -29874\n"
+ "shl16insli r43, r43, -7795\n"
+ "shl16insli r43, r43, -2712\n"
+ "shl16insli r43, r43, 26506\n"
+ "{ mula_hu_ls r22, r12, r43 ; fnop }\n"
+ "move %0, r22\n"
+ "move %1, r12\n"
+ "move %2, r43\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mula_hu_lu_X0.c b/none/tests/tilegx/insn_test_mula_hu_lu_X0.c
new file mode 100644
index 0000000..d411a28
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mula_hu_lu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mula_hu_lu_X0.c
+//op=171
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe2c25e110bb59946, 0xd06357c8b3903323 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r36, -11276\n"
+ "shl16insli r36, r36, -71\n"
+ "shl16insli r36, r36, -26089\n"
+ "shl16insli r36, r36, 30233\n"
+ "moveli r22, 9301\n"
+ "shl16insli r22, r22, -32656\n"
+ "shl16insli r22, r22, -4555\n"
+ "shl16insli r22, r22, 17657\n"
+ "moveli r24, 17032\n"
+ "shl16insli r24, r24, 29889\n"
+ "shl16insli r24, r24, 32576\n"
+ "shl16insli r24, r24, 8242\n"
+ "{ mula_hu_lu r36, r22, r24 ; fnop }\n"
+ "move %0, r36\n"
+ "move %1, r22\n"
+ "move %2, r24\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mula_ls_ls_X0.c b/none/tests/tilegx/insn_test_mula_ls_ls_X0.c
new file mode 100644
index 0000000..baaa378
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mula_ls_ls_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mula_ls_ls_X0.c
+//op=172
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x481bd1c9a41ebd0a, 0x38646a3eaf613478 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r17, -19781\n"
+ "shl16insli r17, r17, 4441\n"
+ "shl16insli r17, r17, -25151\n"
+ "shl16insli r17, r17, -1099\n"
+ "moveli r30, 16040\n"
+ "shl16insli r30, r30, 13539\n"
+ "shl16insli r30, r30, -10611\n"
+ "shl16insli r30, r30, 18456\n"
+ "moveli r43, 9010\n"
+ "shl16insli r43, r43, -28846\n"
+ "shl16insli r43, r43, 3819\n"
+ "shl16insli r43, r43, -25218\n"
+ "{ mula_ls_ls r17, r30, r43 ; fnop }\n"
+ "move %0, r17\n"
+ "move %1, r30\n"
+ "move %2, r43\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mula_ls_ls_Y0.c b/none/tests/tilegx/insn_test_mula_ls_ls_Y0.c
new file mode 100644
index 0000000..80c88ed
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mula_ls_ls_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mula_ls_ls_Y0.c
+//op=172
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x481bd1c9a41ebd0a, 0x38646a3eaf613478 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r17, -19781\n"
+ "shl16insli r17, r17, 4441\n"
+ "shl16insli r17, r17, -25151\n"
+ "shl16insli r17, r17, -1099\n"
+ "moveli r30, 16040\n"
+ "shl16insli r30, r30, 13539\n"
+ "shl16insli r30, r30, -10611\n"
+ "shl16insli r30, r30, 18456\n"
+ "moveli r43, 9010\n"
+ "shl16insli r43, r43, -28846\n"
+ "shl16insli r43, r43, 3819\n"
+ "shl16insli r43, r43, -25218\n"
+ "{ mula_ls_ls r17, r30, r43 ; fnop ; ld r63, r54 }\n"
+ "move %0, r17\n"
+ "move %1, r30\n"
+ "move %2, r43\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mula_ls_lu_X0.c b/none/tests/tilegx/insn_test_mula_ls_lu_X0.c
new file mode 100644
index 0000000..ecfbbfb
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mula_ls_lu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mula_ls_lu_X0.c
+//op=173
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4a40d1e28d4a3d4a, 0x308f52b9c1ed029f };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, 14076\n"
+ "shl16insli r3, r3, -13318\n"
+ "shl16insli r3, r3, -31064\n"
+ "shl16insli r3, r3, 24882\n"
+ "moveli r2, 1130\n"
+ "shl16insli r2, r2, 19735\n"
+ "shl16insli r2, r2, 18026\n"
+ "shl16insli r2, r2, 2783\n"
+ "moveli r34, 22540\n"
+ "shl16insli r34, r34, -22507\n"
+ "shl16insli r34, r34, 24248\n"
+ "shl16insli r34, r34, 23620\n"
+ "{ mula_ls_lu r3, r2, r34 ; fnop }\n"
+ "move %0, r3\n"
+ "move %1, r2\n"
+ "move %2, r34\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mula_lu_lu_X0.c b/none/tests/tilegx/insn_test_mula_lu_lu_X0.c
new file mode 100644
index 0000000..38ef23f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mula_lu_lu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mula_lu_lu_X0.c
+//op=174
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9e2898e9d06dd42a, 0xc7ac37053a461101 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r39, -11842\n"
+ "shl16insli r39, r39, 25434\n"
+ "shl16insli r39, r39, -11416\n"
+ "shl16insli r39, r39, -1334\n"
+ "moveli r38, -8159\n"
+ "shl16insli r38, r38, -19405\n"
+ "shl16insli r38, r38, -6882\n"
+ "shl16insli r38, r38, 24332\n"
+ "moveli r36, 11583\n"
+ "shl16insli r36, r36, -32720\n"
+ "shl16insli r36, r36, 17409\n"
+ "shl16insli r36, r36, -25838\n"
+ "{ mula_lu_lu r39, r38, r36 ; fnop }\n"
+ "move %0, r39\n"
+ "move %1, r38\n"
+ "move %2, r36\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mula_lu_lu_Y0.c b/none/tests/tilegx/insn_test_mula_lu_lu_Y0.c
new file mode 100644
index 0000000..59f9712
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mula_lu_lu_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mula_lu_lu_Y0.c
+//op=174
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9e2898e9d06dd42a, 0xc7ac37053a461101 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r39, -11842\n"
+ "shl16insli r39, r39, 25434\n"
+ "shl16insli r39, r39, -11416\n"
+ "shl16insli r39, r39, -1334\n"
+ "moveli r38, -8159\n"
+ "shl16insli r38, r38, -19405\n"
+ "shl16insli r38, r38, -6882\n"
+ "shl16insli r38, r38, 24332\n"
+ "moveli r36, 11583\n"
+ "shl16insli r36, r36, -32720\n"
+ "shl16insli r36, r36, 17409\n"
+ "shl16insli r36, r36, -25838\n"
+ "{ mula_lu_lu r39, r38, r36 ; fnop ; ld r63, r54 }\n"
+ "move %0, r39\n"
+ "move %1, r38\n"
+ "move %2, r36\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mulax_X0.c b/none/tests/tilegx/insn_test_mulax_X0.c
new file mode 100644
index 0000000..ce091a9
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mulax_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mulax_X0.c
+//op=175
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf2b0303a92767195, 0x8dd298793721b4a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r48, -15789\n"
+ "shl16insli r48, r48, 590\n"
+ "shl16insli r48, r48, -26270\n"
+ "shl16insli r48, r48, -21766\n"
+ "moveli r44, 23264\n"
+ "shl16insli r44, r44, -28907\n"
+ "shl16insli r44, r44, -1813\n"
+ "shl16insli r44, r44, -17554\n"
+ "moveli r46, -2982\n"
+ "shl16insli r46, r46, -29749\n"
+ "shl16insli r46, r46, 881\n"
+ "shl16insli r46, r46, 9838\n"
+ "{ mulax r48, r44, r46 ; fnop }\n"
+ "move %0, r48\n"
+ "move %1, r44\n"
+ "move %2, r46\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mulax_Y0.c b/none/tests/tilegx/insn_test_mulax_Y0.c
new file mode 100644
index 0000000..8c2153f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mulax_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mulax_Y0.c
+//op=175
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf2b0303a92767195, 0x8dd298793721b4a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r48, -15789\n"
+ "shl16insli r48, r48, 590\n"
+ "shl16insli r48, r48, -26270\n"
+ "shl16insli r48, r48, -21766\n"
+ "moveli r44, 23264\n"
+ "shl16insli r44, r44, -28907\n"
+ "shl16insli r44, r44, -1813\n"
+ "shl16insli r44, r44, -17554\n"
+ "moveli r46, -2982\n"
+ "shl16insli r46, r46, -29749\n"
+ "shl16insli r46, r46, 881\n"
+ "shl16insli r46, r46, 9838\n"
+ "{ mulax r48, r44, r46 ; fnop ; ld r63, r54 }\n"
+ "move %0, r48\n"
+ "move %1, r44\n"
+ "move %2, r46\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mulx_X0.c b/none/tests/tilegx/insn_test_mulx_X0.c
new file mode 100644
index 0000000..d37f2a3
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mulx_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mulx_X0.c
+//op=176
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe468b0628a4b2c82, 0xab961c7cdfcb76d0 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, -17450\n"
+ "shl16insli r34, r34, 24652\n"
+ "shl16insli r34, r34, 22143\n"
+ "shl16insli r34, r34, -2590\n"
+ "moveli r20, 3184\n"
+ "shl16insli r20, r20, 7750\n"
+ "shl16insli r20, r20, -24327\n"
+ "shl16insli r20, r20, 22846\n"
+ "moveli r43, -31998\n"
+ "shl16insli r43, r43, 23863\n"
+ "shl16insli r43, r43, -12992\n"
+ "shl16insli r43, r43, -15691\n"
+ "{ mulx r34, r20, r43 ; fnop }\n"
+ "move %0, r34\n"
+ "move %1, r20\n"
+ "move %2, r43\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mulx_Y0.c b/none/tests/tilegx/insn_test_mulx_Y0.c
new file mode 100644
index 0000000..2ce09b6
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mulx_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mulx_Y0.c
+//op=176
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe468b0628a4b2c82, 0xab961c7cdfcb76d0 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, -17450\n"
+ "shl16insli r34, r34, 24652\n"
+ "shl16insli r34, r34, 22143\n"
+ "shl16insli r34, r34, -2590\n"
+ "moveli r20, 3184\n"
+ "shl16insli r20, r20, 7750\n"
+ "shl16insli r20, r20, -24327\n"
+ "shl16insli r20, r20, 22846\n"
+ "moveli r43, -31998\n"
+ "shl16insli r43, r43, 23863\n"
+ "shl16insli r43, r43, -12992\n"
+ "shl16insli r43, r43, -15691\n"
+ "{ mulx r34, r20, r43 ; fnop ; ld r63, r54 }\n"
+ "move %0, r34\n"
+ "move %1, r20\n"
+ "move %2, r43\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mz_X0.c b/none/tests/tilegx/insn_test_mz_X0.c
new file mode 100644
index 0000000..89d802c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mz_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mz_X0.c
+//op=177
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9b70a44aad51d91c, 0x67d733d090a0e0ad };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r47, -6674\n"
+ "shl16insli r47, r47, -26653\n"
+ "shl16insli r47, r47, -16240\n"
+ "shl16insli r47, r47, 300\n"
+ "moveli r39, -14350\n"
+ "shl16insli r39, r39, -13718\n"
+ "shl16insli r39, r39, -10168\n"
+ "shl16insli r39, r39, -15190\n"
+ "moveli r40, 208\n"
+ "shl16insli r40, r40, 20913\n"
+ "shl16insli r40, r40, 19131\n"
+ "shl16insli r40, r40, -17081\n"
+ "{ mz r47, r39, r40 ; fnop }\n"
+ "move %0, r47\n"
+ "move %1, r39\n"
+ "move %2, r40\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mz_X1.c b/none/tests/tilegx/insn_test_mz_X1.c
new file mode 100644
index 0000000..f4b0421
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mz_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mz_X1.c
+//op=177
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9b70a44aad51d91c, 0x67d733d090a0e0ad };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r47, -6674\n"
+ "shl16insli r47, r47, -26653\n"
+ "shl16insli r47, r47, -16240\n"
+ "shl16insli r47, r47, 300\n"
+ "moveli r39, -14350\n"
+ "shl16insli r39, r39, -13718\n"
+ "shl16insli r39, r39, -10168\n"
+ "shl16insli r39, r39, -15190\n"
+ "moveli r40, 208\n"
+ "shl16insli r40, r40, 20913\n"
+ "shl16insli r40, r40, 19131\n"
+ "shl16insli r40, r40, -17081\n"
+ "{ fnop ; mz r47, r39, r40 }\n"
+ "move %0, r47\n"
+ "move %1, r39\n"
+ "move %2, r40\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mz_Y0.c b/none/tests/tilegx/insn_test_mz_Y0.c
new file mode 100644
index 0000000..c538f06
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mz_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mz_Y0.c
+//op=177
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9b70a44aad51d91c, 0x67d733d090a0e0ad };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r47, -6674\n"
+ "shl16insli r47, r47, -26653\n"
+ "shl16insli r47, r47, -16240\n"
+ "shl16insli r47, r47, 300\n"
+ "moveli r39, -14350\n"
+ "shl16insli r39, r39, -13718\n"
+ "shl16insli r39, r39, -10168\n"
+ "shl16insli r39, r39, -15190\n"
+ "moveli r40, 208\n"
+ "shl16insli r40, r40, 20913\n"
+ "shl16insli r40, r40, 19131\n"
+ "shl16insli r40, r40, -17081\n"
+ "{ mz r47, r39, r40 ; fnop ; ld r63, r54 }\n"
+ "move %0, r47\n"
+ "move %1, r39\n"
+ "move %2, r40\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_mz_Y1.c b/none/tests/tilegx/insn_test_mz_Y1.c
new file mode 100644
index 0000000..1046e3a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_mz_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_mz_Y1.c
+//op=177
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9b70a44aad51d91c, 0x67d733d090a0e0ad };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r47, -6674\n"
+ "shl16insli r47, r47, -26653\n"
+ "shl16insli r47, r47, -16240\n"
+ "shl16insli r47, r47, 300\n"
+ "moveli r39, -14350\n"
+ "shl16insli r39, r39, -13718\n"
+ "shl16insli r39, r39, -10168\n"
+ "shl16insli r39, r39, -15190\n"
+ "moveli r40, 208\n"
+ "shl16insli r40, r40, 20913\n"
+ "shl16insli r40, r40, 19131\n"
+ "shl16insli r40, r40, -17081\n"
+ "{ fnop ; mz r47, r39, r40 ; ld r63, r54 }\n"
+ "move %0, r47\n"
+ "move %1, r39\n"
+ "move %2, r40\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_nop_X0.c b/none/tests/tilegx/insn_test_nop_X0.c
new file mode 100644
index 0000000..7d13191
--- /dev/null
+++ b/none/tests/tilegx/insn_test_nop_X0.c
@@ -0,0 +1,24 @@
+//file: _insn_test_nop_X0.c
+//op=179
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x592fbed956a8fd1f, 0xb149341116c1d072 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "{ nop ; fnop }\n"
+ );
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_nop_X1.c b/none/tests/tilegx/insn_test_nop_X1.c
new file mode 100644
index 0000000..3bd4c91
--- /dev/null
+++ b/none/tests/tilegx/insn_test_nop_X1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_nop_X1.c
+//op=179
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x592fbed956a8fd1f, 0xb149341116c1d072 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "{ fnop ; nop }\n"
+ );
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_nop_Y0.c b/none/tests/tilegx/insn_test_nop_Y0.c
new file mode 100644
index 0000000..c525921
--- /dev/null
+++ b/none/tests/tilegx/insn_test_nop_Y0.c
@@ -0,0 +1,24 @@
+//file: _insn_test_nop_Y0.c
+//op=179
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x592fbed956a8fd1f, 0xb149341116c1d072 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "{ nop ; fnop ; ld r63, r54 }\n"
+ );
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_nop_Y1.c b/none/tests/tilegx/insn_test_nop_Y1.c
new file mode 100644
index 0000000..3a06aba
--- /dev/null
+++ b/none/tests/tilegx/insn_test_nop_Y1.c
@@ -0,0 +1,24 @@
+//file: _insn_test_nop_Y1.c
+//op=179
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x592fbed956a8fd1f, 0xb149341116c1d072 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "{ fnop ; nop ; ld r63, r54 }\n"
+ );
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_nor_X0.c b/none/tests/tilegx/insn_test_nor_X0.c
new file mode 100644
index 0000000..a86a1fb
--- /dev/null
+++ b/none/tests/tilegx/insn_test_nor_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_nor_X0.c
+//op=180
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd104e6fedbd326fa, 0xa0df1db5b4273e63 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, 9517\n"
+ "shl16insli r22, r22, -14743\n"
+ "shl16insli r22, r22, 28886\n"
+ "shl16insli r22, r22, 23646\n"
+ "moveli r8, 31287\n"
+ "shl16insli r8, r8, -16865\n"
+ "shl16insli r8, r8, 32203\n"
+ "shl16insli r8, r8, 26808\n"
+ "moveli r7, -18162\n"
+ "shl16insli r7, r7, 4413\n"
+ "shl16insli r7, r7, 14247\n"
+ "shl16insli r7, r7, 14892\n"
+ "{ nor r22, r8, r7 ; fnop }\n"
+ "move %0, r22\n"
+ "move %1, r8\n"
+ "move %2, r7\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_nor_X1.c b/none/tests/tilegx/insn_test_nor_X1.c
new file mode 100644
index 0000000..8b2ed2f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_nor_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_nor_X1.c
+//op=180
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd104e6fedbd326fa, 0xa0df1db5b4273e63 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, 9517\n"
+ "shl16insli r22, r22, -14743\n"
+ "shl16insli r22, r22, 28886\n"
+ "shl16insli r22, r22, 23646\n"
+ "moveli r8, 31287\n"
+ "shl16insli r8, r8, -16865\n"
+ "shl16insli r8, r8, 32203\n"
+ "shl16insli r8, r8, 26808\n"
+ "moveli r7, -18162\n"
+ "shl16insli r7, r7, 4413\n"
+ "shl16insli r7, r7, 14247\n"
+ "shl16insli r7, r7, 14892\n"
+ "{ fnop ; nor r22, r8, r7 }\n"
+ "move %0, r22\n"
+ "move %1, r8\n"
+ "move %2, r7\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_nor_Y0.c b/none/tests/tilegx/insn_test_nor_Y0.c
new file mode 100644
index 0000000..558eb7f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_nor_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_nor_Y0.c
+//op=180
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd104e6fedbd326fa, 0xa0df1db5b4273e63 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, 9517\n"
+ "shl16insli r22, r22, -14743\n"
+ "shl16insli r22, r22, 28886\n"
+ "shl16insli r22, r22, 23646\n"
+ "moveli r8, 31287\n"
+ "shl16insli r8, r8, -16865\n"
+ "shl16insli r8, r8, 32203\n"
+ "shl16insli r8, r8, 26808\n"
+ "moveli r7, -18162\n"
+ "shl16insli r7, r7, 4413\n"
+ "shl16insli r7, r7, 14247\n"
+ "shl16insli r7, r7, 14892\n"
+ "{ nor r22, r8, r7 ; fnop ; ld r63, r54 }\n"
+ "move %0, r22\n"
+ "move %1, r8\n"
+ "move %2, r7\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_nor_Y1.c b/none/tests/tilegx/insn_test_nor_Y1.c
new file mode 100644
index 0000000..8faa86b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_nor_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_nor_Y1.c
+//op=180
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd104e6fedbd326fa, 0xa0df1db5b4273e63 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, 9517\n"
+ "shl16insli r22, r22, -14743\n"
+ "shl16insli r22, r22, 28886\n"
+ "shl16insli r22, r22, 23646\n"
+ "moveli r8, 31287\n"
+ "shl16insli r8, r8, -16865\n"
+ "shl16insli r8, r8, 32203\n"
+ "shl16insli r8, r8, 26808\n"
+ "moveli r7, -18162\n"
+ "shl16insli r7, r7, 4413\n"
+ "shl16insli r7, r7, 14247\n"
+ "shl16insli r7, r7, 14892\n"
+ "{ fnop ; nor r22, r8, r7 ; ld r63, r54 }\n"
+ "move %0, r22\n"
+ "move %1, r8\n"
+ "move %2, r7\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_or_X0.c b/none/tests/tilegx/insn_test_or_X0.c
new file mode 100644
index 0000000..a2deee9
--- /dev/null
+++ b/none/tests/tilegx/insn_test_or_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_or_X0.c
+//op=181
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbda18e421a932d37, 0xe49de7021c00d425 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, 4269\n"
+ "shl16insli r13, r13, 12585\n"
+ "shl16insli r13, r13, 23528\n"
+ "shl16insli r13, r13, -28113\n"
+ "moveli r36, 3720\n"
+ "shl16insli r36, r36, 21467\n"
+ "shl16insli r36, r36, 16503\n"
+ "shl16insli r36, r36, -15551\n"
+ "moveli r7, -17228\n"
+ "shl16insli r7, r7, -9907\n"
+ "shl16insli r7, r7, 11604\n"
+ "shl16insli r7, r7, -13348\n"
+ "{ or r13, r36, r7 ; fnop }\n"
+ "move %0, r13\n"
+ "move %1, r36\n"
+ "move %2, r7\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_or_X1.c b/none/tests/tilegx/insn_test_or_X1.c
new file mode 100644
index 0000000..91d51e1
--- /dev/null
+++ b/none/tests/tilegx/insn_test_or_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_or_X1.c
+//op=181
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbda18e421a932d37, 0xe49de7021c00d425 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, 4269\n"
+ "shl16insli r13, r13, 12585\n"
+ "shl16insli r13, r13, 23528\n"
+ "shl16insli r13, r13, -28113\n"
+ "moveli r36, 3720\n"
+ "shl16insli r36, r36, 21467\n"
+ "shl16insli r36, r36, 16503\n"
+ "shl16insli r36, r36, -15551\n"
+ "moveli r7, -17228\n"
+ "shl16insli r7, r7, -9907\n"
+ "shl16insli r7, r7, 11604\n"
+ "shl16insli r7, r7, -13348\n"
+ "{ fnop ; or r13, r36, r7 }\n"
+ "move %0, r13\n"
+ "move %1, r36\n"
+ "move %2, r7\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_or_Y0.c b/none/tests/tilegx/insn_test_or_Y0.c
new file mode 100644
index 0000000..e8576ea
--- /dev/null
+++ b/none/tests/tilegx/insn_test_or_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_or_Y0.c
+//op=181
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbda18e421a932d37, 0xe49de7021c00d425 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, 4269\n"
+ "shl16insli r13, r13, 12585\n"
+ "shl16insli r13, r13, 23528\n"
+ "shl16insli r13, r13, -28113\n"
+ "moveli r36, 3720\n"
+ "shl16insli r36, r36, 21467\n"
+ "shl16insli r36, r36, 16503\n"
+ "shl16insli r36, r36, -15551\n"
+ "moveli r7, -17228\n"
+ "shl16insli r7, r7, -9907\n"
+ "shl16insli r7, r7, 11604\n"
+ "shl16insli r7, r7, -13348\n"
+ "{ or r13, r36, r7 ; fnop ; ld r63, r54 }\n"
+ "move %0, r13\n"
+ "move %1, r36\n"
+ "move %2, r7\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_or_Y1.c b/none/tests/tilegx/insn_test_or_Y1.c
new file mode 100644
index 0000000..43d1f2a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_or_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_or_Y1.c
+//op=181
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbda18e421a932d37, 0xe49de7021c00d425 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, 4269\n"
+ "shl16insli r13, r13, 12585\n"
+ "shl16insli r13, r13, 23528\n"
+ "shl16insli r13, r13, -28113\n"
+ "moveli r36, 3720\n"
+ "shl16insli r36, r36, 21467\n"
+ "shl16insli r36, r36, 16503\n"
+ "shl16insli r36, r36, -15551\n"
+ "moveli r7, -17228\n"
+ "shl16insli r7, r7, -9907\n"
+ "shl16insli r7, r7, 11604\n"
+ "shl16insli r7, r7, -13348\n"
+ "{ fnop ; or r13, r36, r7 ; ld r63, r54 }\n"
+ "move %0, r13\n"
+ "move %1, r36\n"
+ "move %2, r7\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ori_X0.c b/none/tests/tilegx/insn_test_ori_X0.c
new file mode 100644
index 0000000..b4e22d9
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ori_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_ori_X0.c
+//op=182
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xfefebc9ad18eac85, 0x6bf7e8d962dcb3ff };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r40, 29084\n"
+ "shl16insli r40, r40, 17620\n"
+ "shl16insli r40, r40, -5765\n"
+ "shl16insli r40, r40, 17748\n"
+ "moveli r36, -12155\n"
+ "shl16insli r36, r36, -29090\n"
+ "shl16insli r36, r36, 11972\n"
+ "shl16insli r36, r36, -26553\n"
+ "{ ori r40, r36, 29 ; fnop }\n"
+ "move %0, r40\n"
+ "move %1, r36\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_ori_X1.c b/none/tests/tilegx/insn_test_ori_X1.c
new file mode 100644
index 0000000..8d524cc
--- /dev/null
+++ b/none/tests/tilegx/insn_test_ori_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_ori_X1.c
+//op=182
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xfefebc9ad18eac85, 0x6bf7e8d962dcb3ff };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r40, 29084\n"
+ "shl16insli r40, r40, 17620\n"
+ "shl16insli r40, r40, -5765\n"
+ "shl16insli r40, r40, 17748\n"
+ "moveli r36, -12155\n"
+ "shl16insli r36, r36, -29090\n"
+ "shl16insli r36, r36, 11972\n"
+ "shl16insli r36, r36, -26553\n"
+ "{ fnop ; ori r40, r36, 29 }\n"
+ "move %0, r40\n"
+ "move %1, r36\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_pcnt_X0.c b/none/tests/tilegx/insn_test_pcnt_X0.c
new file mode 100644
index 0000000..f2818c0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_pcnt_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_pcnt_X0.c
+//op=183
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x17cffec1aae5ac94, 0xc7c07a1c34655bf8 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r21, -18757\n"
+ "shl16insli r21, r21, 26178\n"
+ "shl16insli r21, r21, 32618\n"
+ "shl16insli r21, r21, 22067\n"
+ "moveli r31, -1083\n"
+ "shl16insli r31, r31, 30832\n"
+ "shl16insli r31, r31, 25967\n"
+ "shl16insli r31, r31, 4463\n"
+ "{ pcnt r21, r31 ; fnop }\n"
+ "move %0, r21\n"
+ "move %1, r31\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_pcnt_Y0.c b/none/tests/tilegx/insn_test_pcnt_Y0.c
new file mode 100644
index 0000000..db18321
--- /dev/null
+++ b/none/tests/tilegx/insn_test_pcnt_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_pcnt_Y0.c
+//op=183
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x17cffec1aae5ac94, 0xc7c07a1c34655bf8 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r21, -18757\n"
+ "shl16insli r21, r21, 26178\n"
+ "shl16insli r21, r21, 32618\n"
+ "shl16insli r21, r21, 22067\n"
+ "moveli r31, -1083\n"
+ "shl16insli r31, r31, 30832\n"
+ "shl16insli r31, r31, 25967\n"
+ "shl16insli r31, r31, 4463\n"
+ "{ pcnt r21, r31 ; fnop ; ld r63, r54 }\n"
+ "move %0, r21\n"
+ "move %1, r31\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_prefetch_X1.c b/none/tests/tilegx/insn_test_prefetch_X1.c
new file mode 100644
index 0000000..639d501
--- /dev/null
+++ b/none/tests/tilegx/insn_test_prefetch_X1.c
@@ -0,0 +1,30 @@
+//file: _insn_test_prefetch_X1.c
+//op=8
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd941c90b89d1197b, 0x9f2fd3736342eb2e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r5, -20979\n"
+ "shl16insli r5, r5, 31723\n"
+ "shl16insli r5, r5, 27537\n"
+ "shl16insli r5, r5, -30979\n"
+ "{ fnop ; prefetch r5 }\n"
+ "move %0, r5\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_prefetch_Y2.c b/none/tests/tilegx/insn_test_prefetch_Y2.c
new file mode 100644
index 0000000..5226cbb
--- /dev/null
+++ b/none/tests/tilegx/insn_test_prefetch_Y2.c
@@ -0,0 +1,30 @@
+//file: _insn_test_prefetch_Y2.c
+//op=8
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd941c90b89d1197b, 0x9f2fd3736342eb2e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r5, -20979\n"
+ "shl16insli r5, r5, 31723\n"
+ "shl16insli r5, r5, 27537\n"
+ "shl16insli r5, r5, -30979\n"
+ "{ fnop ; fnop ; prefetch r5 }\n"
+ "move %0, r5\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_prefetch_l1_X1.c b/none/tests/tilegx/insn_test_prefetch_l1_X1.c
new file mode 100644
index 0000000..6b71a3c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_prefetch_l1_X1.c
@@ -0,0 +1,30 @@
+//file: _insn_test_prefetch_l1_X1.c
+//op=15
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbca200a47bf08fef, 0xcc8e27fe3fbcf86c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r48, -10816\n"
+ "shl16insli r48, r48, 15791\n"
+ "shl16insli r48, r48, -20821\n"
+ "shl16insli r48, r48, 20094\n"
+ "{ fnop ; prefetch r48 }\n"
+ "move %0, r48\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_prefetch_l1_Y2.c b/none/tests/tilegx/insn_test_prefetch_l1_Y2.c
new file mode 100644
index 0000000..1b66ad0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_prefetch_l1_Y2.c
@@ -0,0 +1,30 @@
+//file: _insn_test_prefetch_l1_Y2.c
+//op=15
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbca200a47bf08fef, 0xcc8e27fe3fbcf86c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r48, -10816\n"
+ "shl16insli r48, r48, 15791\n"
+ "shl16insli r48, r48, -20821\n"
+ "shl16insli r48, r48, 20094\n"
+ "{ fnop ; fnop ; prefetch r48 }\n"
+ "move %0, r48\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_prefetch_l2_X1.c b/none/tests/tilegx/insn_test_prefetch_l2_X1.c
new file mode 100644
index 0000000..eca64a0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_prefetch_l2_X1.c
@@ -0,0 +1,30 @@
+//file: _insn_test_prefetch_l2_X1.c
+//op=17
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbcd5fb19de288be, 0x10f22adff1ed0182 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r48, 2029\n"
+ "shl16insli r48, r48, -23766\n"
+ "shl16insli r48, r48, -9681\n"
+ "shl16insli r48, r48, 20576\n"
+ "{ fnop ; prefetch_l2 r48 }\n"
+ "move %0, r48\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_prefetch_l2_Y2.c b/none/tests/tilegx/insn_test_prefetch_l2_Y2.c
new file mode 100644
index 0000000..142a648
--- /dev/null
+++ b/none/tests/tilegx/insn_test_prefetch_l2_Y2.c
@@ -0,0 +1,30 @@
+//file: _insn_test_prefetch_l2_Y2.c
+//op=17
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbcd5fb19de288be, 0x10f22adff1ed0182 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r48, 2029\n"
+ "shl16insli r48, r48, -23766\n"
+ "shl16insli r48, r48, -9681\n"
+ "shl16insli r48, r48, 20576\n"
+ "{ fnop ; fnop ; prefetch_l2 r48 }\n"
+ "move %0, r48\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_prefetch_l3_X1.c b/none/tests/tilegx/insn_test_prefetch_l3_X1.c
new file mode 100644
index 0000000..0ffb076
--- /dev/null
+++ b/none/tests/tilegx/insn_test_prefetch_l3_X1.c
@@ -0,0 +1,30 @@
+//file: _insn_test_prefetch_l3_X1.c
+//op=19
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb026dbf41e76db36, 0x3030888d84db4c82 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, 8736\n"
+ "shl16insli r13, r13, -19069\n"
+ "shl16insli r13, r13, -2177\n"
+ "shl16insli r13, r13, 29968\n"
+ "{ fnop ; prefetch_l3 r13 }\n"
+ "move %0, r13\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_prefetch_l3_Y2.c b/none/tests/tilegx/insn_test_prefetch_l3_Y2.c
new file mode 100644
index 0000000..5af7d41
--- /dev/null
+++ b/none/tests/tilegx/insn_test_prefetch_l3_Y2.c
@@ -0,0 +1,30 @@
+//file: _insn_test_prefetch_l3_Y2.c
+//op=19
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb026dbf41e76db36, 0x3030888d84db4c82 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, 8736\n"
+ "shl16insli r13, r13, -19069\n"
+ "shl16insli r13, r13, -2177\n"
+ "shl16insli r13, r13, 29968\n"
+ "{ fnop ; fnop ; prefetch_l3 r13 }\n"
+ "move %0, r13\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_revbits_X0.c b/none/tests/tilegx/insn_test_revbits_X0.c
new file mode 100644
index 0000000..3711ac7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_revbits_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_revbits_X0.c
+//op=184
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x683c0bdf5b51687b, 0x82d752d6d5c34590 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r43, -27981\n"
+ "shl16insli r43, r43, -3839\n"
+ "shl16insli r43, r43, -10726\n"
+ "shl16insli r43, r43, 16403\n"
+ "moveli r48, 21888\n"
+ "shl16insli r48, r48, -8663\n"
+ "shl16insli r48, r48, -14905\n"
+ "shl16insli r48, r48, -14362\n"
+ "{ revbits r43, r48 ; fnop }\n"
+ "move %0, r43\n"
+ "move %1, r48\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_revbits_Y0.c b/none/tests/tilegx/insn_test_revbits_Y0.c
new file mode 100644
index 0000000..3898146
--- /dev/null
+++ b/none/tests/tilegx/insn_test_revbits_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_revbits_Y0.c
+//op=184
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x683c0bdf5b51687b, 0x82d752d6d5c34590 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r43, -27981\n"
+ "shl16insli r43, r43, -3839\n"
+ "shl16insli r43, r43, -10726\n"
+ "shl16insli r43, r43, 16403\n"
+ "moveli r48, 21888\n"
+ "shl16insli r48, r48, -8663\n"
+ "shl16insli r48, r48, -14905\n"
+ "shl16insli r48, r48, -14362\n"
+ "{ revbits r43, r48 ; fnop ; ld r63, r54 }\n"
+ "move %0, r43\n"
+ "move %1, r48\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_revbytes_X0.c b/none/tests/tilegx/insn_test_revbytes_X0.c
new file mode 100644
index 0000000..8f58aa0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_revbytes_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_revbytes_X0.c
+//op=185
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x8855e8634340c3dd, 0x83fe56474a5b5a36 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, 2393\n"
+ "shl16insli r38, r38, 12415\n"
+ "shl16insli r38, r38, -29425\n"
+ "shl16insli r38, r38, -12730\n"
+ "moveli r41, -12869\n"
+ "shl16insli r41, r41, -19528\n"
+ "shl16insli r41, r41, 27018\n"
+ "shl16insli r41, r41, -20432\n"
+ "{ revbytes r38, r41 ; fnop }\n"
+ "move %0, r38\n"
+ "move %1, r41\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_revbytes_Y0.c b/none/tests/tilegx/insn_test_revbytes_Y0.c
new file mode 100644
index 0000000..d9ad9ad
--- /dev/null
+++ b/none/tests/tilegx/insn_test_revbytes_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_revbytes_Y0.c
+//op=185
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x8855e8634340c3dd, 0x83fe56474a5b5a36 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, 2393\n"
+ "shl16insli r38, r38, 12415\n"
+ "shl16insli r38, r38, -29425\n"
+ "shl16insli r38, r38, -12730\n"
+ "moveli r41, -12869\n"
+ "shl16insli r41, r41, -19528\n"
+ "shl16insli r41, r41, 27018\n"
+ "shl16insli r41, r41, -20432\n"
+ "{ revbytes r38, r41 ; fnop ; ld r63, r54 }\n"
+ "move %0, r38\n"
+ "move %1, r41\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_rotl_X0.c b/none/tests/tilegx/insn_test_rotl_X0.c
new file mode 100644
index 0000000..b57885b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_rotl_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_rotl_X0.c
+//op=186
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9b125b6641bb9f39, 0x90ce422b64edc869 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r43, -17868\n"
+ "shl16insli r43, r43, -15637\n"
+ "shl16insli r43, r43, -21854\n"
+ "shl16insli r43, r43, 31769\n"
+ "moveli r22, -19055\n"
+ "shl16insli r22, r22, -26082\n"
+ "shl16insli r22, r22, -18335\n"
+ "shl16insli r22, r22, -26425\n"
+ "moveli r43, -28917\n"
+ "shl16insli r43, r43, -6384\n"
+ "shl16insli r43, r43, -11771\n"
+ "shl16insli r43, r43, -16008\n"
+ "{ rotl r43, r22, r43 ; fnop }\n"
+ "move %0, r43\n"
+ "move %1, r22\n"
+ "move %2, r43\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_rotl_X1.c b/none/tests/tilegx/insn_test_rotl_X1.c
new file mode 100644
index 0000000..96bfcb4
--- /dev/null
+++ b/none/tests/tilegx/insn_test_rotl_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_rotl_X1.c
+//op=186
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9b125b6641bb9f39, 0x90ce422b64edc869 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r43, -17868\n"
+ "shl16insli r43, r43, -15637\n"
+ "shl16insli r43, r43, -21854\n"
+ "shl16insli r43, r43, 31769\n"
+ "moveli r22, -19055\n"
+ "shl16insli r22, r22, -26082\n"
+ "shl16insli r22, r22, -18335\n"
+ "shl16insli r22, r22, -26425\n"
+ "moveli r43, -28917\n"
+ "shl16insli r43, r43, -6384\n"
+ "shl16insli r43, r43, -11771\n"
+ "shl16insli r43, r43, -16008\n"
+ "{ fnop ; rotl r43, r22, r43 }\n"
+ "move %0, r43\n"
+ "move %1, r22\n"
+ "move %2, r43\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_rotl_Y0.c b/none/tests/tilegx/insn_test_rotl_Y0.c
new file mode 100644
index 0000000..4f097fb
--- /dev/null
+++ b/none/tests/tilegx/insn_test_rotl_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_rotl_Y0.c
+//op=186
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9b125b6641bb9f39, 0x90ce422b64edc869 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r43, -17868\n"
+ "shl16insli r43, r43, -15637\n"
+ "shl16insli r43, r43, -21854\n"
+ "shl16insli r43, r43, 31769\n"
+ "moveli r22, -19055\n"
+ "shl16insli r22, r22, -26082\n"
+ "shl16insli r22, r22, -18335\n"
+ "shl16insli r22, r22, -26425\n"
+ "moveli r43, -28917\n"
+ "shl16insli r43, r43, -6384\n"
+ "shl16insli r43, r43, -11771\n"
+ "shl16insli r43, r43, -16008\n"
+ "{ rotl r43, r22, r43 ; fnop ; ld r63, r54 }\n"
+ "move %0, r43\n"
+ "move %1, r22\n"
+ "move %2, r43\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_rotl_Y1.c b/none/tests/tilegx/insn_test_rotl_Y1.c
new file mode 100644
index 0000000..e414352
--- /dev/null
+++ b/none/tests/tilegx/insn_test_rotl_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_rotl_Y1.c
+//op=186
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9b125b6641bb9f39, 0x90ce422b64edc869 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r43, -17868\n"
+ "shl16insli r43, r43, -15637\n"
+ "shl16insli r43, r43, -21854\n"
+ "shl16insli r43, r43, 31769\n"
+ "moveli r22, -19055\n"
+ "shl16insli r22, r22, -26082\n"
+ "shl16insli r22, r22, -18335\n"
+ "shl16insli r22, r22, -26425\n"
+ "moveli r43, -28917\n"
+ "shl16insli r43, r43, -6384\n"
+ "shl16insli r43, r43, -11771\n"
+ "shl16insli r43, r43, -16008\n"
+ "{ fnop ; rotl r43, r22, r43 ; ld r63, r54 }\n"
+ "move %0, r43\n"
+ "move %1, r22\n"
+ "move %2, r43\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_rotli_X0.c b/none/tests/tilegx/insn_test_rotli_X0.c
new file mode 100644
index 0000000..ac473a1
--- /dev/null
+++ b/none/tests/tilegx/insn_test_rotli_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_rotli_X0.c
+//op=187
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7703657413b27076, 0x1bee8662fa44392b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, 16585\n"
+ "shl16insli r38, r38, 19462\n"
+ "shl16insli r38, r38, 29122\n"
+ "shl16insli r38, r38, -30058\n"
+ "moveli r7, 3682\n"
+ "shl16insli r7, r7, 7348\n"
+ "shl16insli r7, r7, -12127\n"
+ "shl16insli r7, r7, 24558\n"
+ "{ rotli r38, r7, 53 ; fnop }\n"
+ "move %0, r38\n"
+ "move %1, r7\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_rotli_X1.c b/none/tests/tilegx/insn_test_rotli_X1.c
new file mode 100644
index 0000000..1552082
--- /dev/null
+++ b/none/tests/tilegx/insn_test_rotli_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_rotli_X1.c
+//op=187
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7703657413b27076, 0x1bee8662fa44392b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, 16585\n"
+ "shl16insli r38, r38, 19462\n"
+ "shl16insli r38, r38, 29122\n"
+ "shl16insli r38, r38, -30058\n"
+ "moveli r7, 3682\n"
+ "shl16insli r7, r7, 7348\n"
+ "shl16insli r7, r7, -12127\n"
+ "shl16insli r7, r7, 24558\n"
+ "{ fnop ; rotli r38, r7, 53 }\n"
+ "move %0, r38\n"
+ "move %1, r7\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_rotli_Y0.c b/none/tests/tilegx/insn_test_rotli_Y0.c
new file mode 100644
index 0000000..bb5188f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_rotli_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_rotli_Y0.c
+//op=187
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7703657413b27076, 0x1bee8662fa44392b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, 16585\n"
+ "shl16insli r38, r38, 19462\n"
+ "shl16insli r38, r38, 29122\n"
+ "shl16insli r38, r38, -30058\n"
+ "moveli r7, 3682\n"
+ "shl16insli r7, r7, 7348\n"
+ "shl16insli r7, r7, -12127\n"
+ "shl16insli r7, r7, 24558\n"
+ "{ rotli r38, r7, 53 ; fnop ; ld r63, r54 }\n"
+ "move %0, r38\n"
+ "move %1, r7\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_rotli_Y1.c b/none/tests/tilegx/insn_test_rotli_Y1.c
new file mode 100644
index 0000000..695a3fe
--- /dev/null
+++ b/none/tests/tilegx/insn_test_rotli_Y1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_rotli_Y1.c
+//op=187
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7703657413b27076, 0x1bee8662fa44392b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, 16585\n"
+ "shl16insli r38, r38, 19462\n"
+ "shl16insli r38, r38, 29122\n"
+ "shl16insli r38, r38, -30058\n"
+ "moveli r7, 3682\n"
+ "shl16insli r7, r7, 7348\n"
+ "shl16insli r7, r7, -12127\n"
+ "shl16insli r7, r7, 24558\n"
+ "{ fnop ; rotli r38, r7, 53 ; ld r63, r54 }\n"
+ "move %0, r38\n"
+ "move %1, r7\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl16insli_X0.c b/none/tests/tilegx/insn_test_shl16insli_X0.c
new file mode 100644
index 0000000..4d3addd
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl16insli_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shl16insli_X0.c
+//op=189
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x842f1ff3b535c0ff, 0xb4e168d3b1d1a300 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r29, -11895\n"
+ "shl16insli r29, r29, 21718\n"
+ "shl16insli r29, r29, -14088\n"
+ "shl16insli r29, r29, -5322\n"
+ "moveli r27, -18517\n"
+ "shl16insli r27, r27, 12387\n"
+ "shl16insli r27, r27, 27111\n"
+ "shl16insli r27, r27, 15808\n"
+ "{ shl16insli r29, r27, -27202 ; fnop }\n"
+ "move %0, r29\n"
+ "move %1, r27\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl16insli_X1.c b/none/tests/tilegx/insn_test_shl16insli_X1.c
new file mode 100644
index 0000000..4b30057
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl16insli_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shl16insli_X1.c
+//op=189
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x842f1ff3b535c0ff, 0xb4e168d3b1d1a300 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r29, -11895\n"
+ "shl16insli r29, r29, 21718\n"
+ "shl16insli r29, r29, -14088\n"
+ "shl16insli r29, r29, -5322\n"
+ "moveli r27, -18517\n"
+ "shl16insli r27, r27, 12387\n"
+ "shl16insli r27, r27, 27111\n"
+ "shl16insli r27, r27, 15808\n"
+ "{ fnop ; shl16insli r29, r27, -27202 }\n"
+ "move %0, r29\n"
+ "move %1, r27\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl1add_X0.c b/none/tests/tilegx/insn_test_shl1add_X0.c
new file mode 100644
index 0000000..1468ac4
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl1add_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl1add_X0.c
+//op=190
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x811d401994a9cbd4, 0xc39a04b8ff503c88 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r36, 30711\n"
+ "shl16insli r36, r36, -23959\n"
+ "shl16insli r36, r36, 22299\n"
+ "shl16insli r36, r36, 25192\n"
+ "moveli r33, 24574\n"
+ "shl16insli r33, r33, -7860\n"
+ "shl16insli r33, r33, 22844\n"
+ "shl16insli r33, r33, -25856\n"
+ "moveli r3, -8773\n"
+ "shl16insli r3, r3, 2664\n"
+ "shl16insli r3, r3, -12396\n"
+ "shl16insli r3, r3, -20538\n"
+ "{ shl1add r36, r33, r3 ; fnop }\n"
+ "move %0, r36\n"
+ "move %1, r33\n"
+ "move %2, r3\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl1add_X1.c b/none/tests/tilegx/insn_test_shl1add_X1.c
new file mode 100644
index 0000000..ca4566a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl1add_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl1add_X1.c
+//op=190
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x811d401994a9cbd4, 0xc39a04b8ff503c88 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r36, 30711\n"
+ "shl16insli r36, r36, -23959\n"
+ "shl16insli r36, r36, 22299\n"
+ "shl16insli r36, r36, 25192\n"
+ "moveli r33, 24574\n"
+ "shl16insli r33, r33, -7860\n"
+ "shl16insli r33, r33, 22844\n"
+ "shl16insli r33, r33, -25856\n"
+ "moveli r3, -8773\n"
+ "shl16insli r3, r3, 2664\n"
+ "shl16insli r3, r3, -12396\n"
+ "shl16insli r3, r3, -20538\n"
+ "{ fnop ; shl1add r36, r33, r3 }\n"
+ "move %0, r36\n"
+ "move %1, r33\n"
+ "move %2, r3\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl1add_Y0.c b/none/tests/tilegx/insn_test_shl1add_Y0.c
new file mode 100644
index 0000000..2f78c35
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl1add_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl1add_Y0.c
+//op=190
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x811d401994a9cbd4, 0xc39a04b8ff503c88 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r36, 30711\n"
+ "shl16insli r36, r36, -23959\n"
+ "shl16insli r36, r36, 22299\n"
+ "shl16insli r36, r36, 25192\n"
+ "moveli r33, 24574\n"
+ "shl16insli r33, r33, -7860\n"
+ "shl16insli r33, r33, 22844\n"
+ "shl16insli r33, r33, -25856\n"
+ "moveli r3, -8773\n"
+ "shl16insli r3, r3, 2664\n"
+ "shl16insli r3, r3, -12396\n"
+ "shl16insli r3, r3, -20538\n"
+ "{ shl1add r36, r33, r3 ; fnop ; ld r63, r54 }\n"
+ "move %0, r36\n"
+ "move %1, r33\n"
+ "move %2, r3\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl1add_Y1.c b/none/tests/tilegx/insn_test_shl1add_Y1.c
new file mode 100644
index 0000000..8e9a4a7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl1add_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl1add_Y1.c
+//op=190
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x811d401994a9cbd4, 0xc39a04b8ff503c88 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r36, 30711\n"
+ "shl16insli r36, r36, -23959\n"
+ "shl16insli r36, r36, 22299\n"
+ "shl16insli r36, r36, 25192\n"
+ "moveli r33, 24574\n"
+ "shl16insli r33, r33, -7860\n"
+ "shl16insli r33, r33, 22844\n"
+ "shl16insli r33, r33, -25856\n"
+ "moveli r3, -8773\n"
+ "shl16insli r3, r3, 2664\n"
+ "shl16insli r3, r3, -12396\n"
+ "shl16insli r3, r3, -20538\n"
+ "{ fnop ; shl1add r36, r33, r3 ; ld r63, r54 }\n"
+ "move %0, r36\n"
+ "move %1, r33\n"
+ "move %2, r3\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl1addx_X0.c b/none/tests/tilegx/insn_test_shl1addx_X0.c
new file mode 100644
index 0000000..e25f8a3
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl1addx_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl1addx_X0.c
+//op=191
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf057c60d59f89641, 0xa3975d48e8f324d7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r46, -17307\n"
+ "shl16insli r46, r46, 5811\n"
+ "shl16insli r46, r46, -14070\n"
+ "shl16insli r46, r46, 1938\n"
+ "moveli r24, 31602\n"
+ "shl16insli r24, r24, 20410\n"
+ "shl16insli r24, r24, 32651\n"
+ "shl16insli r24, r24, -17296\n"
+ "moveli r33, 1206\n"
+ "shl16insli r33, r33, 4007\n"
+ "shl16insli r33, r33, -27712\n"
+ "shl16insli r33, r33, 3824\n"
+ "{ shl1addx r46, r24, r33 ; fnop }\n"
+ "move %0, r46\n"
+ "move %1, r24\n"
+ "move %2, r33\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl1addx_X1.c b/none/tests/tilegx/insn_test_shl1addx_X1.c
new file mode 100644
index 0000000..dff1075
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl1addx_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl1addx_X1.c
+//op=191
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf057c60d59f89641, 0xa3975d48e8f324d7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r46, -17307\n"
+ "shl16insli r46, r46, 5811\n"
+ "shl16insli r46, r46, -14070\n"
+ "shl16insli r46, r46, 1938\n"
+ "moveli r24, 31602\n"
+ "shl16insli r24, r24, 20410\n"
+ "shl16insli r24, r24, 32651\n"
+ "shl16insli r24, r24, -17296\n"
+ "moveli r33, 1206\n"
+ "shl16insli r33, r33, 4007\n"
+ "shl16insli r33, r33, -27712\n"
+ "shl16insli r33, r33, 3824\n"
+ "{ fnop ; shl1addx r46, r24, r33 }\n"
+ "move %0, r46\n"
+ "move %1, r24\n"
+ "move %2, r33\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl1addx_Y0.c b/none/tests/tilegx/insn_test_shl1addx_Y0.c
new file mode 100644
index 0000000..6a5aa88
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl1addx_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl1addx_Y0.c
+//op=191
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf057c60d59f89641, 0xa3975d48e8f324d7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r46, -17307\n"
+ "shl16insli r46, r46, 5811\n"
+ "shl16insli r46, r46, -14070\n"
+ "shl16insli r46, r46, 1938\n"
+ "moveli r24, 31602\n"
+ "shl16insli r24, r24, 20410\n"
+ "shl16insli r24, r24, 32651\n"
+ "shl16insli r24, r24, -17296\n"
+ "moveli r33, 1206\n"
+ "shl16insli r33, r33, 4007\n"
+ "shl16insli r33, r33, -27712\n"
+ "shl16insli r33, r33, 3824\n"
+ "{ shl1addx r46, r24, r33 ; fnop ; ld r63, r54 }\n"
+ "move %0, r46\n"
+ "move %1, r24\n"
+ "move %2, r33\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl1addx_Y1.c b/none/tests/tilegx/insn_test_shl1addx_Y1.c
new file mode 100644
index 0000000..31ee968
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl1addx_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl1addx_Y1.c
+//op=191
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf057c60d59f89641, 0xa3975d48e8f324d7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r46, -17307\n"
+ "shl16insli r46, r46, 5811\n"
+ "shl16insli r46, r46, -14070\n"
+ "shl16insli r46, r46, 1938\n"
+ "moveli r24, 31602\n"
+ "shl16insli r24, r24, 20410\n"
+ "shl16insli r24, r24, 32651\n"
+ "shl16insli r24, r24, -17296\n"
+ "moveli r33, 1206\n"
+ "shl16insli r33, r33, 4007\n"
+ "shl16insli r33, r33, -27712\n"
+ "shl16insli r33, r33, 3824\n"
+ "{ fnop ; shl1addx r46, r24, r33 ; ld r63, r54 }\n"
+ "move %0, r46\n"
+ "move %1, r24\n"
+ "move %2, r33\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl2add_X0.c b/none/tests/tilegx/insn_test_shl2add_X0.c
new file mode 100644
index 0000000..7085cf9
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl2add_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl2add_X0.c
+//op=192
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7c6741cd8294f113, 0x7df20b112210ce2f };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r0, -28670\n"
+ "shl16insli r0, r0, -6265\n"
+ "shl16insli r0, r0, 15425\n"
+ "shl16insli r0, r0, 17326\n"
+ "moveli r19, 7596\n"
+ "shl16insli r19, r19, -10648\n"
+ "shl16insli r19, r19, 15573\n"
+ "shl16insli r19, r19, -25790\n"
+ "moveli r43, -7218\n"
+ "shl16insli r43, r43, 7896\n"
+ "shl16insli r43, r43, -22888\n"
+ "shl16insli r43, r43, -25968\n"
+ "{ shl2add r0, r19, r43 ; fnop }\n"
+ "move %0, r0\n"
+ "move %1, r19\n"
+ "move %2, r43\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl2add_X1.c b/none/tests/tilegx/insn_test_shl2add_X1.c
new file mode 100644
index 0000000..7edbdb1
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl2add_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl2add_X1.c
+//op=192
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7c6741cd8294f113, 0x7df20b112210ce2f };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r0, -28670\n"
+ "shl16insli r0, r0, -6265\n"
+ "shl16insli r0, r0, 15425\n"
+ "shl16insli r0, r0, 17326\n"
+ "moveli r19, 7596\n"
+ "shl16insli r19, r19, -10648\n"
+ "shl16insli r19, r19, 15573\n"
+ "shl16insli r19, r19, -25790\n"
+ "moveli r43, -7218\n"
+ "shl16insli r43, r43, 7896\n"
+ "shl16insli r43, r43, -22888\n"
+ "shl16insli r43, r43, -25968\n"
+ "{ fnop ; shl2add r0, r19, r43 }\n"
+ "move %0, r0\n"
+ "move %1, r19\n"
+ "move %2, r43\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl2add_Y0.c b/none/tests/tilegx/insn_test_shl2add_Y0.c
new file mode 100644
index 0000000..0820039
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl2add_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl2add_Y0.c
+//op=192
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7c6741cd8294f113, 0x7df20b112210ce2f };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r0, -28670\n"
+ "shl16insli r0, r0, -6265\n"
+ "shl16insli r0, r0, 15425\n"
+ "shl16insli r0, r0, 17326\n"
+ "moveli r19, 7596\n"
+ "shl16insli r19, r19, -10648\n"
+ "shl16insli r19, r19, 15573\n"
+ "shl16insli r19, r19, -25790\n"
+ "moveli r43, -7218\n"
+ "shl16insli r43, r43, 7896\n"
+ "shl16insli r43, r43, -22888\n"
+ "shl16insli r43, r43, -25968\n"
+ "{ shl2add r0, r19, r43 ; fnop ; ld r63, r54 }\n"
+ "move %0, r0\n"
+ "move %1, r19\n"
+ "move %2, r43\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl2add_Y1.c b/none/tests/tilegx/insn_test_shl2add_Y1.c
new file mode 100644
index 0000000..e24a20e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl2add_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl2add_Y1.c
+//op=192
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7c6741cd8294f113, 0x7df20b112210ce2f };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r0, -28670\n"
+ "shl16insli r0, r0, -6265\n"
+ "shl16insli r0, r0, 15425\n"
+ "shl16insli r0, r0, 17326\n"
+ "moveli r19, 7596\n"
+ "shl16insli r19, r19, -10648\n"
+ "shl16insli r19, r19, 15573\n"
+ "shl16insli r19, r19, -25790\n"
+ "moveli r43, -7218\n"
+ "shl16insli r43, r43, 7896\n"
+ "shl16insli r43, r43, -22888\n"
+ "shl16insli r43, r43, -25968\n"
+ "{ fnop ; shl2add r0, r19, r43 ; ld r63, r54 }\n"
+ "move %0, r0\n"
+ "move %1, r19\n"
+ "move %2, r43\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl2addx_X0.c b/none/tests/tilegx/insn_test_shl2addx_X0.c
new file mode 100644
index 0000000..611c8ae
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl2addx_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl2addx_X0.c
+//op=193
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x853e551b961eaa4c, 0x7867e09f71095915 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r50, -28023\n"
+ "shl16insli r50, r50, -28331\n"
+ "shl16insli r50, r50, 32085\n"
+ "shl16insli r50, r50, -17473\n"
+ "moveli r49, -5833\n"
+ "shl16insli r49, r49, -31753\n"
+ "shl16insli r49, r49, -27071\n"
+ "shl16insli r49, r49, -23683\n"
+ "moveli r21, 6443\n"
+ "shl16insli r21, r21, 17296\n"
+ "shl16insli r21, r21, 8461\n"
+ "shl16insli r21, r21, -6245\n"
+ "{ shl2addx r50, r49, r21 ; fnop }\n"
+ "move %0, r50\n"
+ "move %1, r49\n"
+ "move %2, r21\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl2addx_X1.c b/none/tests/tilegx/insn_test_shl2addx_X1.c
new file mode 100644
index 0000000..f0164f6
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl2addx_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl2addx_X1.c
+//op=193
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x853e551b961eaa4c, 0x7867e09f71095915 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r50, -28023\n"
+ "shl16insli r50, r50, -28331\n"
+ "shl16insli r50, r50, 32085\n"
+ "shl16insli r50, r50, -17473\n"
+ "moveli r49, -5833\n"
+ "shl16insli r49, r49, -31753\n"
+ "shl16insli r49, r49, -27071\n"
+ "shl16insli r49, r49, -23683\n"
+ "moveli r21, 6443\n"
+ "shl16insli r21, r21, 17296\n"
+ "shl16insli r21, r21, 8461\n"
+ "shl16insli r21, r21, -6245\n"
+ "{ fnop ; shl2addx r50, r49, r21 }\n"
+ "move %0, r50\n"
+ "move %1, r49\n"
+ "move %2, r21\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl2addx_Y0.c b/none/tests/tilegx/insn_test_shl2addx_Y0.c
new file mode 100644
index 0000000..d4b7586
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl2addx_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl2addx_Y0.c
+//op=193
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x853e551b961eaa4c, 0x7867e09f71095915 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r50, -28023\n"
+ "shl16insli r50, r50, -28331\n"
+ "shl16insli r50, r50, 32085\n"
+ "shl16insli r50, r50, -17473\n"
+ "moveli r49, -5833\n"
+ "shl16insli r49, r49, -31753\n"
+ "shl16insli r49, r49, -27071\n"
+ "shl16insli r49, r49, -23683\n"
+ "moveli r21, 6443\n"
+ "shl16insli r21, r21, 17296\n"
+ "shl16insli r21, r21, 8461\n"
+ "shl16insli r21, r21, -6245\n"
+ "{ shl2addx r50, r49, r21 ; fnop ; ld r63, r54 }\n"
+ "move %0, r50\n"
+ "move %1, r49\n"
+ "move %2, r21\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl2addx_Y1.c b/none/tests/tilegx/insn_test_shl2addx_Y1.c
new file mode 100644
index 0000000..e191e2e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl2addx_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl2addx_Y1.c
+//op=193
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x853e551b961eaa4c, 0x7867e09f71095915 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r50, -28023\n"
+ "shl16insli r50, r50, -28331\n"
+ "shl16insli r50, r50, 32085\n"
+ "shl16insli r50, r50, -17473\n"
+ "moveli r49, -5833\n"
+ "shl16insli r49, r49, -31753\n"
+ "shl16insli r49, r49, -27071\n"
+ "shl16insli r49, r49, -23683\n"
+ "moveli r21, 6443\n"
+ "shl16insli r21, r21, 17296\n"
+ "shl16insli r21, r21, 8461\n"
+ "shl16insli r21, r21, -6245\n"
+ "{ fnop ; shl2addx r50, r49, r21 ; ld r63, r54 }\n"
+ "move %0, r50\n"
+ "move %1, r49\n"
+ "move %2, r21\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl3add_X0.c b/none/tests/tilegx/insn_test_shl3add_X0.c
new file mode 100644
index 0000000..ea72911
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl3add_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl3add_X0.c
+//op=194
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc8704900d8de98e2, 0xdeb2133cfb2c5342 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r9, 9269\n"
+ "shl16insli r9, r9, 23416\n"
+ "shl16insli r9, r9, -14988\n"
+ "shl16insli r9, r9, 22168\n"
+ "moveli r44, -12324\n"
+ "shl16insli r44, r44, -28627\n"
+ "shl16insli r44, r44, 16604\n"
+ "shl16insli r44, r44, -17536\n"
+ "moveli r1, 7448\n"
+ "shl16insli r1, r1, 10894\n"
+ "shl16insli r1, r1, 29909\n"
+ "shl16insli r1, r1, 28991\n"
+ "{ shl3add r9, r44, r1 ; fnop }\n"
+ "move %0, r9\n"
+ "move %1, r44\n"
+ "move %2, r1\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl3add_X1.c b/none/tests/tilegx/insn_test_shl3add_X1.c
new file mode 100644
index 0000000..702ba90
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl3add_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl3add_X1.c
+//op=194
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc8704900d8de98e2, 0xdeb2133cfb2c5342 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r9, 9269\n"
+ "shl16insli r9, r9, 23416\n"
+ "shl16insli r9, r9, -14988\n"
+ "shl16insli r9, r9, 22168\n"
+ "moveli r44, -12324\n"
+ "shl16insli r44, r44, -28627\n"
+ "shl16insli r44, r44, 16604\n"
+ "shl16insli r44, r44, -17536\n"
+ "moveli r1, 7448\n"
+ "shl16insli r1, r1, 10894\n"
+ "shl16insli r1, r1, 29909\n"
+ "shl16insli r1, r1, 28991\n"
+ "{ fnop ; shl3add r9, r44, r1 }\n"
+ "move %0, r9\n"
+ "move %1, r44\n"
+ "move %2, r1\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl3add_Y0.c b/none/tests/tilegx/insn_test_shl3add_Y0.c
new file mode 100644
index 0000000..91d353a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl3add_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl3add_Y0.c
+//op=194
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc8704900d8de98e2, 0xdeb2133cfb2c5342 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r9, 9269\n"
+ "shl16insli r9, r9, 23416\n"
+ "shl16insli r9, r9, -14988\n"
+ "shl16insli r9, r9, 22168\n"
+ "moveli r44, -12324\n"
+ "shl16insli r44, r44, -28627\n"
+ "shl16insli r44, r44, 16604\n"
+ "shl16insli r44, r44, -17536\n"
+ "moveli r1, 7448\n"
+ "shl16insli r1, r1, 10894\n"
+ "shl16insli r1, r1, 29909\n"
+ "shl16insli r1, r1, 28991\n"
+ "{ shl3add r9, r44, r1 ; fnop ; ld r63, r54 }\n"
+ "move %0, r9\n"
+ "move %1, r44\n"
+ "move %2, r1\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl3add_Y1.c b/none/tests/tilegx/insn_test_shl3add_Y1.c
new file mode 100644
index 0000000..de28d4f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl3add_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl3add_Y1.c
+//op=194
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc8704900d8de98e2, 0xdeb2133cfb2c5342 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r9, 9269\n"
+ "shl16insli r9, r9, 23416\n"
+ "shl16insli r9, r9, -14988\n"
+ "shl16insli r9, r9, 22168\n"
+ "moveli r44, -12324\n"
+ "shl16insli r44, r44, -28627\n"
+ "shl16insli r44, r44, 16604\n"
+ "shl16insli r44, r44, -17536\n"
+ "moveli r1, 7448\n"
+ "shl16insli r1, r1, 10894\n"
+ "shl16insli r1, r1, 29909\n"
+ "shl16insli r1, r1, 28991\n"
+ "{ fnop ; shl3add r9, r44, r1 ; ld r63, r54 }\n"
+ "move %0, r9\n"
+ "move %1, r44\n"
+ "move %2, r1\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl3addx_X0.c b/none/tests/tilegx/insn_test_shl3addx_X0.c
new file mode 100644
index 0000000..754ee78
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl3addx_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl3addx_X0.c
+//op=195
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5d526fffff5940db, 0x85ff61d332ccdd58 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r2, 6570\n"
+ "shl16insli r2, r2, -30096\n"
+ "shl16insli r2, r2, -3418\n"
+ "shl16insli r2, r2, 9405\n"
+ "moveli r11, -1170\n"
+ "shl16insli r11, r11, -1505\n"
+ "shl16insli r11, r11, -1810\n"
+ "shl16insli r11, r11, 12649\n"
+ "moveli r17, -7548\n"
+ "shl16insli r17, r17, -12942\n"
+ "shl16insli r17, r17, -2876\n"
+ "shl16insli r17, r17, 29349\n"
+ "{ shl3addx r2, r11, r17 ; fnop }\n"
+ "move %0, r2\n"
+ "move %1, r11\n"
+ "move %2, r17\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl3addx_X1.c b/none/tests/tilegx/insn_test_shl3addx_X1.c
new file mode 100644
index 0000000..9296c71
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl3addx_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl3addx_X1.c
+//op=195
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5d526fffff5940db, 0x85ff61d332ccdd58 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r2, 6570\n"
+ "shl16insli r2, r2, -30096\n"
+ "shl16insli r2, r2, -3418\n"
+ "shl16insli r2, r2, 9405\n"
+ "moveli r11, -1170\n"
+ "shl16insli r11, r11, -1505\n"
+ "shl16insli r11, r11, -1810\n"
+ "shl16insli r11, r11, 12649\n"
+ "moveli r17, -7548\n"
+ "shl16insli r17, r17, -12942\n"
+ "shl16insli r17, r17, -2876\n"
+ "shl16insli r17, r17, 29349\n"
+ "{ fnop ; shl3addx r2, r11, r17 }\n"
+ "move %0, r2\n"
+ "move %1, r11\n"
+ "move %2, r17\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl3addx_Y0.c b/none/tests/tilegx/insn_test_shl3addx_Y0.c
new file mode 100644
index 0000000..e38b9f9
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl3addx_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl3addx_Y0.c
+//op=195
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5d526fffff5940db, 0x85ff61d332ccdd58 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r2, 6570\n"
+ "shl16insli r2, r2, -30096\n"
+ "shl16insli r2, r2, -3418\n"
+ "shl16insli r2, r2, 9405\n"
+ "moveli r11, -1170\n"
+ "shl16insli r11, r11, -1505\n"
+ "shl16insli r11, r11, -1810\n"
+ "shl16insli r11, r11, 12649\n"
+ "moveli r17, -7548\n"
+ "shl16insli r17, r17, -12942\n"
+ "shl16insli r17, r17, -2876\n"
+ "shl16insli r17, r17, 29349\n"
+ "{ shl3addx r2, r11, r17 ; fnop ; ld r63, r54 }\n"
+ "move %0, r2\n"
+ "move %1, r11\n"
+ "move %2, r17\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl3addx_Y1.c b/none/tests/tilegx/insn_test_shl3addx_Y1.c
new file mode 100644
index 0000000..43923be
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl3addx_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl3addx_Y1.c
+//op=195
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5d526fffff5940db, 0x85ff61d332ccdd58 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r2, 6570\n"
+ "shl16insli r2, r2, -30096\n"
+ "shl16insli r2, r2, -3418\n"
+ "shl16insli r2, r2, 9405\n"
+ "moveli r11, -1170\n"
+ "shl16insli r11, r11, -1505\n"
+ "shl16insli r11, r11, -1810\n"
+ "shl16insli r11, r11, 12649\n"
+ "moveli r17, -7548\n"
+ "shl16insli r17, r17, -12942\n"
+ "shl16insli r17, r17, -2876\n"
+ "shl16insli r17, r17, 29349\n"
+ "{ fnop ; shl3addx r2, r11, r17 ; ld r63, r54 }\n"
+ "move %0, r2\n"
+ "move %1, r11\n"
+ "move %2, r17\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl_X0.c b/none/tests/tilegx/insn_test_shl_X0.c
new file mode 100644
index 0000000..cb48a17
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl_X0.c
+//op=188
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x53094f44a07b725d, 0xe61730d0d9026b62 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r23, -28145\n"
+ "shl16insli r23, r23, -7915\n"
+ "shl16insli r23, r23, 2786\n"
+ "shl16insli r23, r23, 4140\n"
+ "moveli r19, -17474\n"
+ "shl16insli r19, r19, 5541\n"
+ "shl16insli r19, r19, 25238\n"
+ "shl16insli r19, r19, 6803\n"
+ "moveli r48, -9071\n"
+ "shl16insli r48, r48, -18527\n"
+ "shl16insli r48, r48, -17369\n"
+ "shl16insli r48, r48, 13142\n"
+ "{ shl r23, r19, r48 ; fnop }\n"
+ "move %0, r23\n"
+ "move %1, r19\n"
+ "move %2, r48\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl_X1.c b/none/tests/tilegx/insn_test_shl_X1.c
new file mode 100644
index 0000000..aae8993
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl_X1.c
+//op=188
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x53094f44a07b725d, 0xe61730d0d9026b62 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r23, -28145\n"
+ "shl16insli r23, r23, -7915\n"
+ "shl16insli r23, r23, 2786\n"
+ "shl16insli r23, r23, 4140\n"
+ "moveli r19, -17474\n"
+ "shl16insli r19, r19, 5541\n"
+ "shl16insli r19, r19, 25238\n"
+ "shl16insli r19, r19, 6803\n"
+ "moveli r48, -9071\n"
+ "shl16insli r48, r48, -18527\n"
+ "shl16insli r48, r48, -17369\n"
+ "shl16insli r48, r48, 13142\n"
+ "{ fnop ; shl r23, r19, r48 }\n"
+ "move %0, r23\n"
+ "move %1, r19\n"
+ "move %2, r48\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl_Y0.c b/none/tests/tilegx/insn_test_shl_Y0.c
new file mode 100644
index 0000000..bdb4360
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl_Y0.c
+//op=188
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x53094f44a07b725d, 0xe61730d0d9026b62 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r23, -28145\n"
+ "shl16insli r23, r23, -7915\n"
+ "shl16insli r23, r23, 2786\n"
+ "shl16insli r23, r23, 4140\n"
+ "moveli r19, -17474\n"
+ "shl16insli r19, r19, 5541\n"
+ "shl16insli r19, r19, 25238\n"
+ "shl16insli r19, r19, 6803\n"
+ "moveli r48, -9071\n"
+ "shl16insli r48, r48, -18527\n"
+ "shl16insli r48, r48, -17369\n"
+ "shl16insli r48, r48, 13142\n"
+ "{ shl r23, r19, r48 ; fnop ; ld r63, r54 }\n"
+ "move %0, r23\n"
+ "move %1, r19\n"
+ "move %2, r48\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shl_Y1.c b/none/tests/tilegx/insn_test_shl_Y1.c
new file mode 100644
index 0000000..cae39e7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shl_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shl_Y1.c
+//op=188
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x53094f44a07b725d, 0xe61730d0d9026b62 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r23, -28145\n"
+ "shl16insli r23, r23, -7915\n"
+ "shl16insli r23, r23, 2786\n"
+ "shl16insli r23, r23, 4140\n"
+ "moveli r19, -17474\n"
+ "shl16insli r19, r19, 5541\n"
+ "shl16insli r19, r19, 25238\n"
+ "shl16insli r19, r19, 6803\n"
+ "moveli r48, -9071\n"
+ "shl16insli r48, r48, -18527\n"
+ "shl16insli r48, r48, -17369\n"
+ "shl16insli r48, r48, 13142\n"
+ "{ fnop ; shl r23, r19, r48 ; ld r63, r54 }\n"
+ "move %0, r23\n"
+ "move %1, r19\n"
+ "move %2, r48\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shli_X0.c b/none/tests/tilegx/insn_test_shli_X0.c
new file mode 100644
index 0000000..3c0b7c7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shli_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shli_X0.c
+//op=196
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x555a73f8e7686b53, 0xca681c3c17f1785e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -17698\n"
+ "shl16insli r3, r3, -1407\n"
+ "shl16insli r3, r3, 3238\n"
+ "shl16insli r3, r3, 14331\n"
+ "moveli r38, -19915\n"
+ "shl16insli r38, r38, -2852\n"
+ "shl16insli r38, r38, 32613\n"
+ "shl16insli r38, r38, 14940\n"
+ "{ shli r3, r38, 16 ; fnop }\n"
+ "move %0, r3\n"
+ "move %1, r38\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shli_X1.c b/none/tests/tilegx/insn_test_shli_X1.c
new file mode 100644
index 0000000..82f5787
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shli_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shli_X1.c
+//op=196
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x555a73f8e7686b53, 0xca681c3c17f1785e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -17698\n"
+ "shl16insli r3, r3, -1407\n"
+ "shl16insli r3, r3, 3238\n"
+ "shl16insli r3, r3, 14331\n"
+ "moveli r38, -19915\n"
+ "shl16insli r38, r38, -2852\n"
+ "shl16insli r38, r38, 32613\n"
+ "shl16insli r38, r38, 14940\n"
+ "{ fnop ; shli r3, r38, 16 }\n"
+ "move %0, r3\n"
+ "move %1, r38\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shli_Y0.c b/none/tests/tilegx/insn_test_shli_Y0.c
new file mode 100644
index 0000000..8154cfc
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shli_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shli_Y0.c
+//op=196
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x555a73f8e7686b53, 0xca681c3c17f1785e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -17698\n"
+ "shl16insli r3, r3, -1407\n"
+ "shl16insli r3, r3, 3238\n"
+ "shl16insli r3, r3, 14331\n"
+ "moveli r38, -19915\n"
+ "shl16insli r38, r38, -2852\n"
+ "shl16insli r38, r38, 32613\n"
+ "shl16insli r38, r38, 14940\n"
+ "{ shli r3, r38, 16 ; fnop ; ld r63, r54 }\n"
+ "move %0, r3\n"
+ "move %1, r38\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shli_Y1.c b/none/tests/tilegx/insn_test_shli_Y1.c
new file mode 100644
index 0000000..a96f1b9
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shli_Y1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shli_Y1.c
+//op=196
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x555a73f8e7686b53, 0xca681c3c17f1785e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -17698\n"
+ "shl16insli r3, r3, -1407\n"
+ "shl16insli r3, r3, 3238\n"
+ "shl16insli r3, r3, 14331\n"
+ "moveli r38, -19915\n"
+ "shl16insli r38, r38, -2852\n"
+ "shl16insli r38, r38, 32613\n"
+ "shl16insli r38, r38, 14940\n"
+ "{ fnop ; shli r3, r38, 16 ; ld r63, r54 }\n"
+ "move %0, r3\n"
+ "move %1, r38\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shlx_X0.c b/none/tests/tilegx/insn_test_shlx_X0.c
new file mode 100644
index 0000000..c908daa
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shlx_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shlx_X0.c
+//op=197
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc50a1fac55b8148e, 0x7a42921bfe898fb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r4, -11574\n"
+ "shl16insli r4, r4, 5546\n"
+ "shl16insli r4, r4, -19680\n"
+ "shl16insli r4, r4, -25733\n"
+ "moveli r4, -7090\n"
+ "shl16insli r4, r4, -11125\n"
+ "shl16insli r4, r4, -23773\n"
+ "shl16insli r4, r4, 7384\n"
+ "moveli r42, -25884\n"
+ "shl16insli r42, r42, -16117\n"
+ "shl16insli r42, r42, 21894\n"
+ "shl16insli r42, r42, -22287\n"
+ "{ shlx r4, r4, r42 ; fnop }\n"
+ "move %0, r4\n"
+ "move %1, r4\n"
+ "move %2, r42\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shlx_X1.c b/none/tests/tilegx/insn_test_shlx_X1.c
new file mode 100644
index 0000000..b37a90a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shlx_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shlx_X1.c
+//op=197
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc50a1fac55b8148e, 0x7a42921bfe898fb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r4, -11574\n"
+ "shl16insli r4, r4, 5546\n"
+ "shl16insli r4, r4, -19680\n"
+ "shl16insli r4, r4, -25733\n"
+ "moveli r4, -7090\n"
+ "shl16insli r4, r4, -11125\n"
+ "shl16insli r4, r4, -23773\n"
+ "shl16insli r4, r4, 7384\n"
+ "moveli r42, -25884\n"
+ "shl16insli r42, r42, -16117\n"
+ "shl16insli r42, r42, 21894\n"
+ "shl16insli r42, r42, -22287\n"
+ "{ fnop ; shlx r4, r4, r42 }\n"
+ "move %0, r4\n"
+ "move %1, r4\n"
+ "move %2, r42\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shlxi_X0.c b/none/tests/tilegx/insn_test_shlxi_X0.c
new file mode 100644
index 0000000..8a9a03c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shlxi_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shlxi_X0.c
+//op=198
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x3a5fb939d54b0205, 0xc4b573db7dcf1edb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r28, 27432\n"
+ "shl16insli r28, r28, -22439\n"
+ "shl16insli r28, r28, 15226\n"
+ "shl16insli r28, r28, -19568\n"
+ "moveli r27, -20710\n"
+ "shl16insli r27, r27, 2588\n"
+ "shl16insli r27, r27, -32310\n"
+ "shl16insli r27, r27, 10817\n"
+ "{ shlxi r28, r27, 58 ; fnop }\n"
+ "move %0, r28\n"
+ "move %1, r27\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shlxi_X1.c b/none/tests/tilegx/insn_test_shlxi_X1.c
new file mode 100644
index 0000000..06bf4f8
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shlxi_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shlxi_X1.c
+//op=198
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x3a5fb939d54b0205, 0xc4b573db7dcf1edb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r28, 27432\n"
+ "shl16insli r28, r28, -22439\n"
+ "shl16insli r28, r28, 15226\n"
+ "shl16insli r28, r28, -19568\n"
+ "moveli r27, -20710\n"
+ "shl16insli r27, r27, 2588\n"
+ "shl16insli r27, r27, -32310\n"
+ "shl16insli r27, r27, 10817\n"
+ "{ fnop ; shlxi r28, r27, 58 }\n"
+ "move %0, r28\n"
+ "move %1, r27\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shrs_X0.c b/none/tests/tilegx/insn_test_shrs_X0.c
new file mode 100644
index 0000000..c2fc5fd
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shrs_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shrs_X0.c
+//op=199
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x744ac897b12768c8, 0x643ae14995d28745 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r32, -3067\n"
+ "shl16insli r32, r32, -406\n"
+ "shl16insli r32, r32, 4305\n"
+ "shl16insli r32, r32, -13947\n"
+ "moveli r26, -23554\n"
+ "shl16insli r26, r26, 503\n"
+ "shl16insli r26, r26, -18013\n"
+ "shl16insli r26, r26, 27535\n"
+ "moveli r26, -13851\n"
+ "shl16insli r26, r26, 4596\n"
+ "shl16insli r26, r26, -18309\n"
+ "shl16insli r26, r26, -24130\n"
+ "{ shrs r32, r26, r26 ; fnop }\n"
+ "move %0, r32\n"
+ "move %1, r26\n"
+ "move %2, r26\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shrs_X1.c b/none/tests/tilegx/insn_test_shrs_X1.c
new file mode 100644
index 0000000..6d86101
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shrs_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shrs_X1.c
+//op=199
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x744ac897b12768c8, 0x643ae14995d28745 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r32, -3067\n"
+ "shl16insli r32, r32, -406\n"
+ "shl16insli r32, r32, 4305\n"
+ "shl16insli r32, r32, -13947\n"
+ "moveli r26, -23554\n"
+ "shl16insli r26, r26, 503\n"
+ "shl16insli r26, r26, -18013\n"
+ "shl16insli r26, r26, 27535\n"
+ "moveli r26, -13851\n"
+ "shl16insli r26, r26, 4596\n"
+ "shl16insli r26, r26, -18309\n"
+ "shl16insli r26, r26, -24130\n"
+ "{ fnop ; shrs r32, r26, r26 }\n"
+ "move %0, r32\n"
+ "move %1, r26\n"
+ "move %2, r26\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shrs_Y0.c b/none/tests/tilegx/insn_test_shrs_Y0.c
new file mode 100644
index 0000000..ffaac0a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shrs_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shrs_Y0.c
+//op=199
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x744ac897b12768c8, 0x643ae14995d28745 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r32, -3067\n"
+ "shl16insli r32, r32, -406\n"
+ "shl16insli r32, r32, 4305\n"
+ "shl16insli r32, r32, -13947\n"
+ "moveli r26, -23554\n"
+ "shl16insli r26, r26, 503\n"
+ "shl16insli r26, r26, -18013\n"
+ "shl16insli r26, r26, 27535\n"
+ "moveli r26, -13851\n"
+ "shl16insli r26, r26, 4596\n"
+ "shl16insli r26, r26, -18309\n"
+ "shl16insli r26, r26, -24130\n"
+ "{ shrs r32, r26, r26 ; fnop ; ld r63, r54 }\n"
+ "move %0, r32\n"
+ "move %1, r26\n"
+ "move %2, r26\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shrs_Y1.c b/none/tests/tilegx/insn_test_shrs_Y1.c
new file mode 100644
index 0000000..7dfada3
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shrs_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shrs_Y1.c
+//op=199
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x744ac897b12768c8, 0x643ae14995d28745 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r32, -3067\n"
+ "shl16insli r32, r32, -406\n"
+ "shl16insli r32, r32, 4305\n"
+ "shl16insli r32, r32, -13947\n"
+ "moveli r26, -23554\n"
+ "shl16insli r26, r26, 503\n"
+ "shl16insli r26, r26, -18013\n"
+ "shl16insli r26, r26, 27535\n"
+ "moveli r26, -13851\n"
+ "shl16insli r26, r26, 4596\n"
+ "shl16insli r26, r26, -18309\n"
+ "shl16insli r26, r26, -24130\n"
+ "{ fnop ; shrs r32, r26, r26 ; ld r63, r54 }\n"
+ "move %0, r32\n"
+ "move %1, r26\n"
+ "move %2, r26\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shrsi_X0.c b/none/tests/tilegx/insn_test_shrsi_X0.c
new file mode 100644
index 0000000..f265855
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shrsi_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shrsi_X0.c
+//op=200
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf248472b636bec53, 0xd85a80d7b6245b44 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r25, -26255\n"
+ "shl16insli r25, r25, -13898\n"
+ "shl16insli r25, r25, 12833\n"
+ "shl16insli r25, r25, 32008\n"
+ "moveli r35, -25986\n"
+ "shl16insli r35, r35, -11739\n"
+ "shl16insli r35, r35, 13313\n"
+ "shl16insli r35, r35, -12374\n"
+ "{ shrsi r25, r35, 46 ; fnop }\n"
+ "move %0, r25\n"
+ "move %1, r35\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shrsi_X1.c b/none/tests/tilegx/insn_test_shrsi_X1.c
new file mode 100644
index 0000000..83c4efe
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shrsi_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shrsi_X1.c
+//op=200
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf248472b636bec53, 0xd85a80d7b6245b44 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r25, -26255\n"
+ "shl16insli r25, r25, -13898\n"
+ "shl16insli r25, r25, 12833\n"
+ "shl16insli r25, r25, 32008\n"
+ "moveli r35, -25986\n"
+ "shl16insli r35, r35, -11739\n"
+ "shl16insli r35, r35, 13313\n"
+ "shl16insli r35, r35, -12374\n"
+ "{ fnop ; shrsi r25, r35, 46 }\n"
+ "move %0, r25\n"
+ "move %1, r35\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shrsi_Y0.c b/none/tests/tilegx/insn_test_shrsi_Y0.c
new file mode 100644
index 0000000..5d06453
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shrsi_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shrsi_Y0.c
+//op=200
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf248472b636bec53, 0xd85a80d7b6245b44 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r25, -26255\n"
+ "shl16insli r25, r25, -13898\n"
+ "shl16insli r25, r25, 12833\n"
+ "shl16insli r25, r25, 32008\n"
+ "moveli r35, -25986\n"
+ "shl16insli r35, r35, -11739\n"
+ "shl16insli r35, r35, 13313\n"
+ "shl16insli r35, r35, -12374\n"
+ "{ shrsi r25, r35, 46 ; fnop ; ld r63, r54 }\n"
+ "move %0, r25\n"
+ "move %1, r35\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shrsi_Y1.c b/none/tests/tilegx/insn_test_shrsi_Y1.c
new file mode 100644
index 0000000..a8eb62c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shrsi_Y1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shrsi_Y1.c
+//op=200
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf248472b636bec53, 0xd85a80d7b6245b44 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r25, -26255\n"
+ "shl16insli r25, r25, -13898\n"
+ "shl16insli r25, r25, 12833\n"
+ "shl16insli r25, r25, 32008\n"
+ "moveli r35, -25986\n"
+ "shl16insli r35, r35, -11739\n"
+ "shl16insli r35, r35, 13313\n"
+ "shl16insli r35, r35, -12374\n"
+ "{ fnop ; shrsi r25, r35, 46 ; ld r63, r54 }\n"
+ "move %0, r25\n"
+ "move %1, r35\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shru_X0.c b/none/tests/tilegx/insn_test_shru_X0.c
new file mode 100644
index 0000000..5b92a8d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shru_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shru_X0.c
+//op=201
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x55fc49dd464ad867, 0xa2f896884ed05e90 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -32745\n"
+ "shl16insli r38, r38, -15929\n"
+ "shl16insli r38, r38, -787\n"
+ "shl16insli r38, r38, 26982\n"
+ "moveli r21, 11986\n"
+ "shl16insli r21, r21, 6051\n"
+ "shl16insli r21, r21, 28164\n"
+ "shl16insli r21, r21, -14685\n"
+ "moveli r41, -32304\n"
+ "shl16insli r41, r41, 5880\n"
+ "shl16insli r41, r41, 26751\n"
+ "shl16insli r41, r41, 15077\n"
+ "{ shru r38, r21, r41 ; fnop }\n"
+ "move %0, r38\n"
+ "move %1, r21\n"
+ "move %2, r41\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shru_X1.c b/none/tests/tilegx/insn_test_shru_X1.c
new file mode 100644
index 0000000..274cbcd
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shru_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shru_X1.c
+//op=201
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x55fc49dd464ad867, 0xa2f896884ed05e90 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -32745\n"
+ "shl16insli r38, r38, -15929\n"
+ "shl16insli r38, r38, -787\n"
+ "shl16insli r38, r38, 26982\n"
+ "moveli r21, 11986\n"
+ "shl16insli r21, r21, 6051\n"
+ "shl16insli r21, r21, 28164\n"
+ "shl16insli r21, r21, -14685\n"
+ "moveli r41, -32304\n"
+ "shl16insli r41, r41, 5880\n"
+ "shl16insli r41, r41, 26751\n"
+ "shl16insli r41, r41, 15077\n"
+ "{ fnop ; shru r38, r21, r41 }\n"
+ "move %0, r38\n"
+ "move %1, r21\n"
+ "move %2, r41\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shru_Y0.c b/none/tests/tilegx/insn_test_shru_Y0.c
new file mode 100644
index 0000000..3d57d5e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shru_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shru_Y0.c
+//op=201
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x55fc49dd464ad867, 0xa2f896884ed05e90 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -32745\n"
+ "shl16insli r38, r38, -15929\n"
+ "shl16insli r38, r38, -787\n"
+ "shl16insli r38, r38, 26982\n"
+ "moveli r21, 11986\n"
+ "shl16insli r21, r21, 6051\n"
+ "shl16insli r21, r21, 28164\n"
+ "shl16insli r21, r21, -14685\n"
+ "moveli r41, -32304\n"
+ "shl16insli r41, r41, 5880\n"
+ "shl16insli r41, r41, 26751\n"
+ "shl16insli r41, r41, 15077\n"
+ "{ shru r38, r21, r41 ; fnop ; ld r63, r54 }\n"
+ "move %0, r38\n"
+ "move %1, r21\n"
+ "move %2, r41\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shru_Y1.c b/none/tests/tilegx/insn_test_shru_Y1.c
new file mode 100644
index 0000000..243bd0c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shru_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shru_Y1.c
+//op=201
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x55fc49dd464ad867, 0xa2f896884ed05e90 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -32745\n"
+ "shl16insli r38, r38, -15929\n"
+ "shl16insli r38, r38, -787\n"
+ "shl16insli r38, r38, 26982\n"
+ "moveli r21, 11986\n"
+ "shl16insli r21, r21, 6051\n"
+ "shl16insli r21, r21, 28164\n"
+ "shl16insli r21, r21, -14685\n"
+ "moveli r41, -32304\n"
+ "shl16insli r41, r41, 5880\n"
+ "shl16insli r41, r41, 26751\n"
+ "shl16insli r41, r41, 15077\n"
+ "{ fnop ; shru r38, r21, r41 ; ld r63, r54 }\n"
+ "move %0, r38\n"
+ "move %1, r21\n"
+ "move %2, r41\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shrui_X0.c b/none/tests/tilegx/insn_test_shrui_X0.c
new file mode 100644
index 0000000..1d379ff
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shrui_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shrui_X0.c
+//op=202
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf903c34a732ec74d, 0x1b58c82cfa9e7805 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r44, 22940\n"
+ "shl16insli r44, r44, -25012\n"
+ "shl16insli r44, r44, 1293\n"
+ "shl16insli r44, r44, 20844\n"
+ "moveli r5, 4497\n"
+ "shl16insli r5, r5, 8011\n"
+ "shl16insli r5, r5, -29488\n"
+ "shl16insli r5, r5, -23563\n"
+ "{ shrui r44, r5, 30 ; fnop }\n"
+ "move %0, r44\n"
+ "move %1, r5\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shrui_X1.c b/none/tests/tilegx/insn_test_shrui_X1.c
new file mode 100644
index 0000000..0d9621f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shrui_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shrui_X1.c
+//op=202
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf903c34a732ec74d, 0x1b58c82cfa9e7805 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r44, 22940\n"
+ "shl16insli r44, r44, -25012\n"
+ "shl16insli r44, r44, 1293\n"
+ "shl16insli r44, r44, 20844\n"
+ "moveli r5, 4497\n"
+ "shl16insli r5, r5, 8011\n"
+ "shl16insli r5, r5, -29488\n"
+ "shl16insli r5, r5, -23563\n"
+ "{ fnop ; shrui r44, r5, 30 }\n"
+ "move %0, r44\n"
+ "move %1, r5\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shrui_Y0.c b/none/tests/tilegx/insn_test_shrui_Y0.c
new file mode 100644
index 0000000..da2014a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shrui_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shrui_Y0.c
+//op=202
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf903c34a732ec74d, 0x1b58c82cfa9e7805 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r44, 22940\n"
+ "shl16insli r44, r44, -25012\n"
+ "shl16insli r44, r44, 1293\n"
+ "shl16insli r44, r44, 20844\n"
+ "moveli r5, 4497\n"
+ "shl16insli r5, r5, 8011\n"
+ "shl16insli r5, r5, -29488\n"
+ "shl16insli r5, r5, -23563\n"
+ "{ shrui r44, r5, 30 ; fnop ; ld r63, r54 }\n"
+ "move %0, r44\n"
+ "move %1, r5\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shrui_Y1.c b/none/tests/tilegx/insn_test_shrui_Y1.c
new file mode 100644
index 0000000..e19c40c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shrui_Y1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_shrui_Y1.c
+//op=202
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf903c34a732ec74d, 0x1b58c82cfa9e7805 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r44, 22940\n"
+ "shl16insli r44, r44, -25012\n"
+ "shl16insli r44, r44, 1293\n"
+ "shl16insli r44, r44, 20844\n"
+ "moveli r5, 4497\n"
+ "shl16insli r5, r5, 8011\n"
+ "shl16insli r5, r5, -29488\n"
+ "shl16insli r5, r5, -23563\n"
+ "{ fnop ; shrui r44, r5, 30 ; ld r63, r54 }\n"
+ "move %0, r44\n"
+ "move %1, r5\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shrux_X0.c b/none/tests/tilegx/insn_test_shrux_X0.c
new file mode 100644
index 0000000..17e34f4
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shrux_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shrux_X0.c
+//op=203
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc37f982bb51ed5f2, 0xeb5eb16625bf3fb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r42, -7121\n"
+ "shl16insli r42, r42, -30624\n"
+ "shl16insli r42, r42, -1997\n"
+ "shl16insli r42, r42, 26909\n"
+ "moveli r49, -18112\n"
+ "shl16insli r49, r49, -30675\n"
+ "shl16insli r49, r49, -20511\n"
+ "shl16insli r49, r49, 26134\n"
+ "moveli r35, 5545\n"
+ "shl16insli r35, r35, 27154\n"
+ "shl16insli r35, r35, -18159\n"
+ "shl16insli r35, r35, 26569\n"
+ "{ shrux r42, r49, r35 ; fnop }\n"
+ "move %0, r42\n"
+ "move %1, r49\n"
+ "move %2, r35\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shrux_X1.c b/none/tests/tilegx/insn_test_shrux_X1.c
new file mode 100644
index 0000000..fd4960e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shrux_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shrux_X1.c
+//op=203
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc37f982bb51ed5f2, 0xeb5eb16625bf3fb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r42, -7121\n"
+ "shl16insli r42, r42, -30624\n"
+ "shl16insli r42, r42, -1997\n"
+ "shl16insli r42, r42, 26909\n"
+ "moveli r49, -18112\n"
+ "shl16insli r49, r49, -30675\n"
+ "shl16insli r49, r49, -20511\n"
+ "shl16insli r49, r49, 26134\n"
+ "moveli r35, 5545\n"
+ "shl16insli r35, r35, 27154\n"
+ "shl16insli r35, r35, -18159\n"
+ "shl16insli r35, r35, 26569\n"
+ "{ fnop ; shrux r42, r49, r35 }\n"
+ "move %0, r42\n"
+ "move %1, r49\n"
+ "move %2, r35\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_shufflebytes_X0.c b/none/tests/tilegx/insn_test_shufflebytes_X0.c
new file mode 100644
index 0000000..7c2dffc
--- /dev/null
+++ b/none/tests/tilegx/insn_test_shufflebytes_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_shufflebytes_X0.c
+//op=205
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa6483705cd54508, 0x21d4110911f94e5 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r32, -22776\n"
+ "shl16insli r32, r32, 13201\n"
+ "shl16insli r32, r32, 12503\n"
+ "shl16insli r32, r32, -18616\n"
+ "moveli r31, -22828\n"
+ "shl16insli r31, r31, -15690\n"
+ "shl16insli r31, r31, 1274\n"
+ "shl16insli r31, r31, 1723\n"
+ "moveli r45, -14449\n"
+ "shl16insli r45, r45, -2545\n"
+ "shl16insli r45, r45, -8339\n"
+ "shl16insli r45, r45, 221\n"
+ "{ shufflebytes r32, r31, r45 ; fnop }\n"
+ "move %0, r32\n"
+ "move %1, r31\n"
+ "move %2, r45\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_st1_X1.c b/none/tests/tilegx/insn_test_st1_X1.c
new file mode 100644
index 0000000..3de74d5
--- /dev/null
+++ b/none/tests/tilegx/insn_test_st1_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_st1_X1.c
+//op=207
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd8cf3760900235c5, 0x4e5b0c323c359e88 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r17, 31115\n"
+ "shl16insli r17, r17, -26645\n"
+ "shl16insli r17, r17, -28059\n"
+ "shl16insli r17, r17, -26401\n"
+ "moveli r40, -23165\n"
+ "shl16insli r40, r40, 1139\n"
+ "shl16insli r40, r40, -11511\n"
+ "shl16insli r40, r40, -24395\n"
+ "move r17, %2\n"
+ "{ fnop ; st1 r17, r40 }\n"
+ "move %0, r17\n"
+ "move %1, r40\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_st1_Y2.c b/none/tests/tilegx/insn_test_st1_Y2.c
new file mode 100644
index 0000000..9173a07
--- /dev/null
+++ b/none/tests/tilegx/insn_test_st1_Y2.c
@@ -0,0 +1,38 @@
+//file: _insn_test_st1_Y2.c
+//op=207
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd8cf3760900235c5, 0x4e5b0c323c359e88 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r32, 31115\n"
+ "shl16insli r32, r32, -26645\n"
+ "shl16insli r32, r32, -28059\n"
+ "shl16insli r32, r32, -26401\n"
+ "moveli r51, -23165\n"
+ "shl16insli r51, r51, 1139\n"
+ "shl16insli r51, r51, -11511\n"
+ "shl16insli r51, r51, -24395\n"
+ "move r32, %2\n"
+ "{ fnop ; fnop ; st1 r32, r51 }\n"
+ "move %0, r32\n"
+ "move %1, r51\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_st1_add_X1.c b/none/tests/tilegx/insn_test_st1_add_X1.c
new file mode 100644
index 0000000..86f751b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_st1_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_st1_add_X1.c
+//op=208
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x94fce0885d473733, 0xe22608b00f39a4c5 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r47, -21466\n"
+ "shl16insli r47, r47, 11354\n"
+ "shl16insli r47, r47, -10374\n"
+ "shl16insli r47, r47, 87\n"
+ "moveli r29, 29514\n"
+ "shl16insli r29, r29, 14828\n"
+ "shl16insli r29, r29, 1013\n"
+ "shl16insli r29, r29, 14302\n"
+ "move r47, %2\n"
+ "{ fnop ; st1_add r47, r29, -39 }\n"
+ "move %0, r47\n"
+ "move %1, r29\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_st2_X1.c b/none/tests/tilegx/insn_test_st2_X1.c
new file mode 100644
index 0000000..c85395e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_st2_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_st2_X1.c
+//op=209
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd28f375e560f9e91, 0x155a9a746b0baf };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r29, 31479\n"
+ "shl16insli r29, r29, 14417\n"
+ "shl16insli r29, r29, -15390\n"
+ "shl16insli r29, r29, -30051\n"
+ "moveli r11, -26026\n"
+ "shl16insli r11, r11, 10353\n"
+ "shl16insli r11, r11, 13698\n"
+ "shl16insli r11, r11, 29702\n"
+ "move r29, %2\n"
+ "{ fnop ; st2 r29, r11 }\n"
+ "move %0, r29\n"
+ "move %1, r11\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_st2_Y2.c b/none/tests/tilegx/insn_test_st2_Y2.c
new file mode 100644
index 0000000..2927bff
--- /dev/null
+++ b/none/tests/tilegx/insn_test_st2_Y2.c
@@ -0,0 +1,38 @@
+//file: _insn_test_st2_Y2.c
+//op=209
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd28f375e560f9e91, 0x155a9a746b0baf };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r27, 31479\n"
+ "shl16insli r27, r27, 14417\n"
+ "shl16insli r27, r27, -15390\n"
+ "shl16insli r27, r27, -30051\n"
+ "moveli r21, -26026\n"
+ "shl16insli r21, r21, 10353\n"
+ "shl16insli r21, r21, 13698\n"
+ "shl16insli r21, r21, 29702\n"
+ "move r27, %2\n"
+ "{ fnop ; fnop ; st2 r27, r21 }\n"
+ "move %0, r27\n"
+ "move %1, r21\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_st2_add_X1.c b/none/tests/tilegx/insn_test_st2_add_X1.c
new file mode 100644
index 0000000..7f6f844
--- /dev/null
+++ b/none/tests/tilegx/insn_test_st2_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_st2_add_X1.c
+//op=210
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x3e6c1829f1e6d7e9, 0x4419397566d0f360 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r47, -832\n"
+ "shl16insli r47, r47, -16346\n"
+ "shl16insli r47, r47, -24487\n"
+ "shl16insli r47, r47, 31724\n"
+ "moveli r34, -11697\n"
+ "shl16insli r34, r34, 28366\n"
+ "shl16insli r34, r34, -10445\n"
+ "shl16insli r34, r34, -26110\n"
+ "move r47, %2\n"
+ "{ fnop ; st2_add r47, r34, 123 }\n"
+ "move %0, r47\n"
+ "move %1, r34\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_st4_X1.c b/none/tests/tilegx/insn_test_st4_X1.c
new file mode 100644
index 0000000..64df1bd
--- /dev/null
+++ b/none/tests/tilegx/insn_test_st4_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_st4_X1.c
+//op=211
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x559c13b7886a9188, 0xe3421eb8576951b8 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r20, -22718\n"
+ "shl16insli r20, r20, 15821\n"
+ "shl16insli r20, r20, -14581\n"
+ "shl16insli r20, r20, -14875\n"
+ "moveli r12, -13950\n"
+ "shl16insli r12, r12, 11169\n"
+ "shl16insli r12, r12, -18391\n"
+ "shl16insli r12, r12, -19133\n"
+ "move r20, %2\n"
+ "{ fnop ; st4 r20, r12 }\n"
+ "move %0, r20\n"
+ "move %1, r12\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_st4_Y2.c b/none/tests/tilegx/insn_test_st4_Y2.c
new file mode 100644
index 0000000..43b287b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_st4_Y2.c
@@ -0,0 +1,38 @@
+//file: _insn_test_st4_Y2.c
+//op=211
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x559c13b7886a9188, 0xe3421eb8576951b8 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r29, -22718\n"
+ "shl16insli r29, r29, 15821\n"
+ "shl16insli r29, r29, -14581\n"
+ "shl16insli r29, r29, -14875\n"
+ "moveli r38, -13950\n"
+ "shl16insli r38, r38, 11169\n"
+ "shl16insli r38, r38, -18391\n"
+ "shl16insli r38, r38, -19133\n"
+ "move r29, %2\n"
+ "{ fnop ; fnop ; st4 r29, r38 }\n"
+ "move %0, r29\n"
+ "move %1, r38\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_st4_add_X1.c b/none/tests/tilegx/insn_test_st4_add_X1.c
new file mode 100644
index 0000000..1fa7538
--- /dev/null
+++ b/none/tests/tilegx/insn_test_st4_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_st4_add_X1.c
+//op=212
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x8a665fbee6262b19, 0x988b16de50a53a0a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r9, -5920\n"
+ "shl16insli r9, r9, 6097\n"
+ "shl16insli r9, r9, -2456\n"
+ "shl16insli r9, r9, 10572\n"
+ "moveli r45, 20609\n"
+ "shl16insli r45, r45, -28665\n"
+ "shl16insli r45, r45, -5637\n"
+ "shl16insli r45, r45, -7979\n"
+ "move r9, %2\n"
+ "{ fnop ; st4_add r9, r45, -34 }\n"
+ "move %0, r9\n"
+ "move %1, r45\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_st_X1.c b/none/tests/tilegx/insn_test_st_X1.c
new file mode 100644
index 0000000..c13e1f6
--- /dev/null
+++ b/none/tests/tilegx/insn_test_st_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_st_X1.c
+//op=206
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xdf38a6238f47ee5b, 0x2c24dd020e9fa33f };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r4, -2884\n"
+ "shl16insli r4, r4, 28785\n"
+ "shl16insli r4, r4, 7136\n"
+ "shl16insli r4, r4, 32281\n"
+ "moveli r7, -14930\n"
+ "shl16insli r7, r7, -27555\n"
+ "shl16insli r7, r7, -15233\n"
+ "shl16insli r7, r7, -7776\n"
+ "move r4, %2\n"
+ "{ fnop ; st r4, r7 }\n"
+ "move %0, r4\n"
+ "move %1, r7\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_st_Y2.c b/none/tests/tilegx/insn_test_st_Y2.c
new file mode 100644
index 0000000..599304f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_st_Y2.c
@@ -0,0 +1,38 @@
+//file: _insn_test_st_Y2.c
+//op=206
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xdf38a6238f47ee5b, 0x2c24dd020e9fa33f };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r29, -2884\n"
+ "shl16insli r29, r29, 28785\n"
+ "shl16insli r29, r29, 7136\n"
+ "shl16insli r29, r29, 32281\n"
+ "moveli r6, -14930\n"
+ "shl16insli r6, r6, -27555\n"
+ "shl16insli r6, r6, -15233\n"
+ "shl16insli r6, r6, -7776\n"
+ "move r29, %2\n"
+ "{ fnop ; fnop ; st r29, r6 }\n"
+ "move %0, r29\n"
+ "move %1, r6\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_st_add_X1.c b/none/tests/tilegx/insn_test_st_add_X1.c
new file mode 100644
index 0000000..7c6202f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_st_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_st_add_X1.c
+//op=213
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb47fef7957f607a6, 0x8f11359b0d4a2989 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r29, -13060\n"
+ "shl16insli r29, r29, 30193\n"
+ "shl16insli r29, r29, -17572\n"
+ "shl16insli r29, r29, -9789\n"
+ "moveli r42, 27632\n"
+ "shl16insli r42, r42, 12264\n"
+ "shl16insli r42, r42, 18107\n"
+ "shl16insli r42, r42, 1639\n"
+ "move r29, %2\n"
+ "{ fnop ; st_add r29, r42, 41 }\n"
+ "move %0, r29\n"
+ "move %1, r42\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_stnt1_X1.c b/none/tests/tilegx/insn_test_stnt1_X1.c
new file mode 100644
index 0000000..2a222d8
--- /dev/null
+++ b/none/tests/tilegx/insn_test_stnt1_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_stnt1_X1.c
+//op=215
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x40001b1a5c71f305, 0x9355b6a95b9dd621 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r33, -20990\n"
+ "shl16insli r33, r33, -3887\n"
+ "shl16insli r33, r33, 1674\n"
+ "shl16insli r33, r33, 11807\n"
+ "moveli r21, 13070\n"
+ "shl16insli r21, r21, 14309\n"
+ "shl16insli r21, r21, -28472\n"
+ "shl16insli r21, r21, 23329\n"
+ "move r33, %2\n"
+ "{ fnop ; stnt1 r33, r21 }\n"
+ "move %0, r33\n"
+ "move %1, r21\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_stnt2_X1.c b/none/tests/tilegx/insn_test_stnt2_X1.c
new file mode 100644
index 0000000..82e5027
--- /dev/null
+++ b/none/tests/tilegx/insn_test_stnt2_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_stnt2_X1.c
+//op=217
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4264771eb976f72, 0x85fc92ac292ed02e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r8, 5764\n"
+ "shl16insli r8, r8, 30540\n"
+ "shl16insli r8, r8, 17158\n"
+ "shl16insli r8, r8, -20975\n"
+ "moveli r18, 25827\n"
+ "shl16insli r18, r18, 7973\n"
+ "shl16insli r18, r18, 5233\n"
+ "shl16insli r18, r18, 29962\n"
+ "move r8, %2\n"
+ "{ fnop ; stnt2 r8, r18 }\n"
+ "move %0, r8\n"
+ "move %1, r18\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_stnt2_add_X1.c b/none/tests/tilegx/insn_test_stnt2_add_X1.c
new file mode 100644
index 0000000..09b5dad
--- /dev/null
+++ b/none/tests/tilegx/insn_test_stnt2_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_stnt2_add_X1.c
+//op=218
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x3cfd98eacbf82c51, 0x1fe3ff849620d963 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r32, 31983\n"
+ "shl16insli r32, r32, -22770\n"
+ "shl16insli r32, r32, 20146\n"
+ "shl16insli r32, r32, -3298\n"
+ "moveli r49, -616\n"
+ "shl16insli r49, r49, -17536\n"
+ "shl16insli r49, r49, -4093\n"
+ "shl16insli r49, r49, -4473\n"
+ "move r32, %2\n"
+ "{ fnop ; stnt2_add r32, r49, 102 }\n"
+ "move %0, r32\n"
+ "move %1, r49\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_stnt4_X1.c b/none/tests/tilegx/insn_test_stnt4_X1.c
new file mode 100644
index 0000000..124b872
--- /dev/null
+++ b/none/tests/tilegx/insn_test_stnt4_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_stnt4_X1.c
+//op=219
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9275ba799534a7f9, 0x6745e72a91ff67c2 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r40, -1549\n"
+ "shl16insli r40, r40, 17842\n"
+ "shl16insli r40, r40, 24501\n"
+ "shl16insli r40, r40, -29822\n"
+ "moveli r41, 17684\n"
+ "shl16insli r41, r41, 2987\n"
+ "shl16insli r41, r41, 15358\n"
+ "shl16insli r41, r41, 2277\n"
+ "move r40, %2\n"
+ "{ fnop ; stnt4 r40, r41 }\n"
+ "move %0, r40\n"
+ "move %1, r41\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_stnt4_add_X1.c b/none/tests/tilegx/insn_test_stnt4_add_X1.c
new file mode 100644
index 0000000..964e28e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_stnt4_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_stnt4_add_X1.c
+//op=220
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6f255d688978bfb5, 0x6b650d3d95fb5164 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r39, -25531\n"
+ "shl16insli r39, r39, -23858\n"
+ "shl16insli r39, r39, 24910\n"
+ "shl16insli r39, r39, -31706\n"
+ "moveli r1, 16489\n"
+ "shl16insli r1, r1, 1852\n"
+ "shl16insli r1, r1, -22328\n"
+ "shl16insli r1, r1, -20016\n"
+ "move r39, %2\n"
+ "{ fnop ; stnt4_add r39, r1, 104 }\n"
+ "move %0, r39\n"
+ "move %1, r1\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_stnt_X1.c b/none/tests/tilegx/insn_test_stnt_X1.c
new file mode 100644
index 0000000..b917f7f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_stnt_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_stnt_X1.c
+//op=214
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6b3e9bf39bb2fee8, 0x4463a2383032e2f2 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r19, 10868\n"
+ "shl16insli r19, r19, 28978\n"
+ "shl16insli r19, r19, -7157\n"
+ "shl16insli r19, r19, 19796\n"
+ "moveli r24, -15907\n"
+ "shl16insli r24, r24, -20157\n"
+ "shl16insli r24, r24, 22361\n"
+ "shl16insli r24, r24, -24834\n"
+ "move r19, %2\n"
+ "{ fnop ; stnt r19, r24 }\n"
+ "move %0, r19\n"
+ "move %1, r24\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_stnt_add_X1.c b/none/tests/tilegx/insn_test_stnt_add_X1.c
new file mode 100644
index 0000000..3431f66
--- /dev/null
+++ b/none/tests/tilegx/insn_test_stnt_add_X1.c
@@ -0,0 +1,38 @@
+//file: _insn_test_stnt_add_X1.c
+//op=221
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x8886d34e2ec2c46, 0x31537bc8fa0b780a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, 27578\n"
+ "shl16insli r13, r13, -12921\n"
+ "shl16insli r13, r13, 10612\n"
+ "shl16insli r13, r13, -6350\n"
+ "moveli r38, -29644\n"
+ "shl16insli r38, r38, -25434\n"
+ "shl16insli r38, r38, -11296\n"
+ "shl16insli r38, r38, -14614\n"
+ "move r13, %2\n"
+ "{ fnop ; stnt_add r13, r38, -75 }\n"
+ "move %0, r13\n"
+ "move %1, r38\n"
+ :"=r"(a[0]),"=r"(a[1]) : "r"(mem));
+ printf("%016lx %016lx\n", mem[0], mem[1]);
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_sub_X0.c b/none/tests/tilegx/insn_test_sub_X0.c
new file mode 100644
index 0000000..eb94de0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_sub_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_sub_X0.c
+//op=222
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x87dd16cba069efad, 0x63c2bab813708efb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r31, -31836\n"
+ "shl16insli r31, r31, -15605\n"
+ "shl16insli r31, r31, -32767\n"
+ "shl16insli r31, r31, -3062\n"
+ "moveli r49, 15126\n"
+ "shl16insli r49, r49, -17631\n"
+ "shl16insli r49, r49, 31423\n"
+ "shl16insli r49, r49, 10557\n"
+ "moveli r28, -7514\n"
+ "shl16insli r28, r28, -32499\n"
+ "shl16insli r28, r28, -9013\n"
+ "shl16insli r28, r28, -11291\n"
+ "{ sub r31, r49, r28 ; fnop }\n"
+ "move %0, r31\n"
+ "move %1, r49\n"
+ "move %2, r28\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_sub_X1.c b/none/tests/tilegx/insn_test_sub_X1.c
new file mode 100644
index 0000000..8ab3dc0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_sub_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_sub_X1.c
+//op=222
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x87dd16cba069efad, 0x63c2bab813708efb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r31, -31836\n"
+ "shl16insli r31, r31, -15605\n"
+ "shl16insli r31, r31, -32767\n"
+ "shl16insli r31, r31, -3062\n"
+ "moveli r49, 15126\n"
+ "shl16insli r49, r49, -17631\n"
+ "shl16insli r49, r49, 31423\n"
+ "shl16insli r49, r49, 10557\n"
+ "moveli r28, -7514\n"
+ "shl16insli r28, r28, -32499\n"
+ "shl16insli r28, r28, -9013\n"
+ "shl16insli r28, r28, -11291\n"
+ "{ fnop ; sub r31, r49, r28 }\n"
+ "move %0, r31\n"
+ "move %1, r49\n"
+ "move %2, r28\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_sub_Y0.c b/none/tests/tilegx/insn_test_sub_Y0.c
new file mode 100644
index 0000000..323df5b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_sub_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_sub_Y0.c
+//op=222
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x87dd16cba069efad, 0x63c2bab813708efb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r31, -31836\n"
+ "shl16insli r31, r31, -15605\n"
+ "shl16insli r31, r31, -32767\n"
+ "shl16insli r31, r31, -3062\n"
+ "moveli r49, 15126\n"
+ "shl16insli r49, r49, -17631\n"
+ "shl16insli r49, r49, 31423\n"
+ "shl16insli r49, r49, 10557\n"
+ "moveli r28, -7514\n"
+ "shl16insli r28, r28, -32499\n"
+ "shl16insli r28, r28, -9013\n"
+ "shl16insli r28, r28, -11291\n"
+ "{ sub r31, r49, r28 ; fnop ; ld r63, r54 }\n"
+ "move %0, r31\n"
+ "move %1, r49\n"
+ "move %2, r28\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_sub_Y1.c b/none/tests/tilegx/insn_test_sub_Y1.c
new file mode 100644
index 0000000..b328149
--- /dev/null
+++ b/none/tests/tilegx/insn_test_sub_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_sub_Y1.c
+//op=222
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x87dd16cba069efad, 0x63c2bab813708efb };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r31, -31836\n"
+ "shl16insli r31, r31, -15605\n"
+ "shl16insli r31, r31, -32767\n"
+ "shl16insli r31, r31, -3062\n"
+ "moveli r49, 15126\n"
+ "shl16insli r49, r49, -17631\n"
+ "shl16insli r49, r49, 31423\n"
+ "shl16insli r49, r49, 10557\n"
+ "moveli r28, -7514\n"
+ "shl16insli r28, r28, -32499\n"
+ "shl16insli r28, r28, -9013\n"
+ "shl16insli r28, r28, -11291\n"
+ "{ fnop ; sub r31, r49, r28 ; ld r63, r54 }\n"
+ "move %0, r31\n"
+ "move %1, r49\n"
+ "move %2, r28\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_subx_X0.c b/none/tests/tilegx/insn_test_subx_X0.c
new file mode 100644
index 0000000..362691a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_subx_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_subx_X0.c
+//op=223
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb80daced7a10c38f, 0x7b03f62381712f55 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, -11286\n"
+ "shl16insli r11, r11, 24130\n"
+ "shl16insli r11, r11, -21471\n"
+ "shl16insli r11, r11, -29764\n"
+ "moveli r6, -5788\n"
+ "shl16insli r6, r6, -20401\n"
+ "shl16insli r6, r6, 13325\n"
+ "shl16insli r6, r6, -17582\n"
+ "moveli r31, 1590\n"
+ "shl16insli r31, r31, 2484\n"
+ "shl16insli r31, r31, 10483\n"
+ "shl16insli r31, r31, -30014\n"
+ "{ subx r11, r6, r31 ; fnop }\n"
+ "move %0, r11\n"
+ "move %1, r6\n"
+ "move %2, r31\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_subx_X1.c b/none/tests/tilegx/insn_test_subx_X1.c
new file mode 100644
index 0000000..b3a7273
--- /dev/null
+++ b/none/tests/tilegx/insn_test_subx_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_subx_X1.c
+//op=223
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb80daced7a10c38f, 0x7b03f62381712f55 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, -11286\n"
+ "shl16insli r11, r11, 24130\n"
+ "shl16insli r11, r11, -21471\n"
+ "shl16insli r11, r11, -29764\n"
+ "moveli r6, -5788\n"
+ "shl16insli r6, r6, -20401\n"
+ "shl16insli r6, r6, 13325\n"
+ "shl16insli r6, r6, -17582\n"
+ "moveli r31, 1590\n"
+ "shl16insli r31, r31, 2484\n"
+ "shl16insli r31, r31, 10483\n"
+ "shl16insli r31, r31, -30014\n"
+ "{ fnop ; subx r11, r6, r31 }\n"
+ "move %0, r11\n"
+ "move %1, r6\n"
+ "move %2, r31\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_subx_Y0.c b/none/tests/tilegx/insn_test_subx_Y0.c
new file mode 100644
index 0000000..7e76300
--- /dev/null
+++ b/none/tests/tilegx/insn_test_subx_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_subx_Y0.c
+//op=223
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb80daced7a10c38f, 0x7b03f62381712f55 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, -11286\n"
+ "shl16insli r11, r11, 24130\n"
+ "shl16insli r11, r11, -21471\n"
+ "shl16insli r11, r11, -29764\n"
+ "moveli r6, -5788\n"
+ "shl16insli r6, r6, -20401\n"
+ "shl16insli r6, r6, 13325\n"
+ "shl16insli r6, r6, -17582\n"
+ "moveli r31, 1590\n"
+ "shl16insli r31, r31, 2484\n"
+ "shl16insli r31, r31, 10483\n"
+ "shl16insli r31, r31, -30014\n"
+ "{ subx r11, r6, r31 ; fnop ; ld r63, r54 }\n"
+ "move %0, r11\n"
+ "move %1, r6\n"
+ "move %2, r31\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_subx_Y1.c b/none/tests/tilegx/insn_test_subx_Y1.c
new file mode 100644
index 0000000..857470a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_subx_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_subx_Y1.c
+//op=223
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb80daced7a10c38f, 0x7b03f62381712f55 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, -11286\n"
+ "shl16insli r11, r11, 24130\n"
+ "shl16insli r11, r11, -21471\n"
+ "shl16insli r11, r11, -29764\n"
+ "moveli r6, -5788\n"
+ "shl16insli r6, r6, -20401\n"
+ "shl16insli r6, r6, 13325\n"
+ "shl16insli r6, r6, -17582\n"
+ "moveli r31, 1590\n"
+ "shl16insli r31, r31, 2484\n"
+ "shl16insli r31, r31, 10483\n"
+ "shl16insli r31, r31, -30014\n"
+ "{ fnop ; subx r11, r6, r31 ; ld r63, r54 }\n"
+ "move %0, r11\n"
+ "move %1, r6\n"
+ "move %2, r31\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_tblidxb0_X0.c b/none/tests/tilegx/insn_test_tblidxb0_X0.c
new file mode 100644
index 0000000..04237ad
--- /dev/null
+++ b/none/tests/tilegx/insn_test_tblidxb0_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_tblidxb0_X0.c
+//op=229
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x31b68d06344a9475, 0xebc9dd79c7a87a22 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r5, -1618\n"
+ "shl16insli r5, r5, -6082\n"
+ "shl16insli r5, r5, 16233\n"
+ "shl16insli r5, r5, -1212\n"
+ "moveli r13, -29258\n"
+ "shl16insli r13, r13, -8488\n"
+ "shl16insli r13, r13, -31577\n"
+ "shl16insli r13, r13, 27843\n"
+ "{ tblidxb0 r5, r13 ; fnop }\n"
+ "move %0, r5\n"
+ "move %1, r13\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_tblidxb0_Y0.c b/none/tests/tilegx/insn_test_tblidxb0_Y0.c
new file mode 100644
index 0000000..375f323
--- /dev/null
+++ b/none/tests/tilegx/insn_test_tblidxb0_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_tblidxb0_Y0.c
+//op=229
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x31b68d06344a9475, 0xebc9dd79c7a87a22 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r5, -1618\n"
+ "shl16insli r5, r5, -6082\n"
+ "shl16insli r5, r5, 16233\n"
+ "shl16insli r5, r5, -1212\n"
+ "moveli r13, -29258\n"
+ "shl16insli r13, r13, -8488\n"
+ "shl16insli r13, r13, -31577\n"
+ "shl16insli r13, r13, 27843\n"
+ "{ tblidxb0 r5, r13 ; fnop ; ld r63, r54 }\n"
+ "move %0, r5\n"
+ "move %1, r13\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_tblidxb1_X0.c b/none/tests/tilegx/insn_test_tblidxb1_X0.c
new file mode 100644
index 0000000..317e110
--- /dev/null
+++ b/none/tests/tilegx/insn_test_tblidxb1_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_tblidxb1_X0.c
+//op=230
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5c5f60b8899f2703, 0x4826371b074e6849 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r10, 27846\n"
+ "shl16insli r10, r10, 314\n"
+ "shl16insli r10, r10, -26424\n"
+ "shl16insli r10, r10, 10908\n"
+ "moveli r2, -32180\n"
+ "shl16insli r2, r2, 27477\n"
+ "shl16insli r2, r2, 9680\n"
+ "shl16insli r2, r2, 16927\n"
+ "{ tblidxb1 r10, r2 ; fnop }\n"
+ "move %0, r10\n"
+ "move %1, r2\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_tblidxb1_Y0.c b/none/tests/tilegx/insn_test_tblidxb1_Y0.c
new file mode 100644
index 0000000..9921515
--- /dev/null
+++ b/none/tests/tilegx/insn_test_tblidxb1_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_tblidxb1_Y0.c
+//op=230
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5c5f60b8899f2703, 0x4826371b074e6849 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r10, 27846\n"
+ "shl16insli r10, r10, 314\n"
+ "shl16insli r10, r10, -26424\n"
+ "shl16insli r10, r10, 10908\n"
+ "moveli r2, -32180\n"
+ "shl16insli r2, r2, 27477\n"
+ "shl16insli r2, r2, 9680\n"
+ "shl16insli r2, r2, 16927\n"
+ "{ tblidxb1 r10, r2 ; fnop ; ld r63, r54 }\n"
+ "move %0, r10\n"
+ "move %1, r2\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_tblidxb2_X0.c b/none/tests/tilegx/insn_test_tblidxb2_X0.c
new file mode 100644
index 0000000..83c49c0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_tblidxb2_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_tblidxb2_X0.c
+//op=231
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6d113c22a94d65e4, 0x400c09fcfb9b518b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r48, -831\n"
+ "shl16insli r48, r48, -21707\n"
+ "shl16insli r48, r48, 21243\n"
+ "shl16insli r48, r48, 32630\n"
+ "moveli r45, 5379\n"
+ "shl16insli r45, r45, 17793\n"
+ "shl16insli r45, r45, 30101\n"
+ "shl16insli r45, r45, 16122\n"
+ "{ tblidxb2 r48, r45 ; fnop }\n"
+ "move %0, r48\n"
+ "move %1, r45\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_tblidxb2_Y0.c b/none/tests/tilegx/insn_test_tblidxb2_Y0.c
new file mode 100644
index 0000000..e4d1fc4
--- /dev/null
+++ b/none/tests/tilegx/insn_test_tblidxb2_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_tblidxb2_Y0.c
+//op=231
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6d113c22a94d65e4, 0x400c09fcfb9b518b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r48, -831\n"
+ "shl16insli r48, r48, -21707\n"
+ "shl16insli r48, r48, 21243\n"
+ "shl16insli r48, r48, 32630\n"
+ "moveli r45, 5379\n"
+ "shl16insli r45, r45, 17793\n"
+ "shl16insli r45, r45, 30101\n"
+ "shl16insli r45, r45, 16122\n"
+ "{ tblidxb2 r48, r45 ; fnop ; ld r63, r54 }\n"
+ "move %0, r48\n"
+ "move %1, r45\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_tblidxb3_X0.c b/none/tests/tilegx/insn_test_tblidxb3_X0.c
new file mode 100644
index 0000000..d8cfb75
--- /dev/null
+++ b/none/tests/tilegx/insn_test_tblidxb3_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_tblidxb3_X0.c
+//op=232
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xfd7000ecef4ffb36, 0xcf14c16c8fe6d80a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r29, 21338\n"
+ "shl16insli r29, r29, -8055\n"
+ "shl16insli r29, r29, -7131\n"
+ "shl16insli r29, r29, 21377\n"
+ "moveli r28, 11583\n"
+ "shl16insli r28, r28, -32720\n"
+ "shl16insli r28, r28, 17409\n"
+ "shl16insli r28, r28, -25838\n"
+ "{ tblidxb3 r29, r28 ; fnop }\n"
+ "move %0, r29\n"
+ "move %1, r28\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_tblidxb3_Y0.c b/none/tests/tilegx/insn_test_tblidxb3_Y0.c
new file mode 100644
index 0000000..4f90f5d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_tblidxb3_Y0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_tblidxb3_Y0.c
+//op=232
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xfd7000ecef4ffb36, 0xcf14c16c8fe6d80a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r29, 21338\n"
+ "shl16insli r29, r29, -8055\n"
+ "shl16insli r29, r29, -7131\n"
+ "shl16insli r29, r29, 21377\n"
+ "moveli r28, 11583\n"
+ "shl16insli r28, r28, -32720\n"
+ "shl16insli r28, r28, 17409\n"
+ "shl16insli r28, r28, -25838\n"
+ "{ tblidxb3 r29, r28 ; fnop ; ld r63, r54 }\n"
+ "move %0, r29\n"
+ "move %1, r28\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1add_X0.c b/none/tests/tilegx/insn_test_v1add_X0.c
new file mode 100644
index 0000000..3d3208d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1add_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1add_X0.c
+//op=233
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb6f11f94786226c8, 0xef169cd1658e9a9b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r20, 27682\n"
+ "shl16insli r20, r20, 13107\n"
+ "shl16insli r20, r20, 1100\n"
+ "shl16insli r20, r20, -12585\n"
+ "moveli r21, 32493\n"
+ "shl16insli r21, r21, 14979\n"
+ "shl16insli r21, r21, 26024\n"
+ "shl16insli r21, r21, 32141\n"
+ "moveli r17, -26698\n"
+ "shl16insli r17, r17, 18738\n"
+ "shl16insli r17, r17, -23994\n"
+ "shl16insli r17, r17, -32450\n"
+ "{ v1add r20, r21, r17 ; fnop }\n"
+ "move %0, r20\n"
+ "move %1, r21\n"
+ "move %2, r17\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1add_X1.c b/none/tests/tilegx/insn_test_v1add_X1.c
new file mode 100644
index 0000000..606818f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1add_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1add_X1.c
+//op=233
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb6f11f94786226c8, 0xef169cd1658e9a9b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r20, 27682\n"
+ "shl16insli r20, r20, 13107\n"
+ "shl16insli r20, r20, 1100\n"
+ "shl16insli r20, r20, -12585\n"
+ "moveli r21, 32493\n"
+ "shl16insli r21, r21, 14979\n"
+ "shl16insli r21, r21, 26024\n"
+ "shl16insli r21, r21, 32141\n"
+ "moveli r17, -26698\n"
+ "shl16insli r17, r17, 18738\n"
+ "shl16insli r17, r17, -23994\n"
+ "shl16insli r17, r17, -32450\n"
+ "{ fnop ; v1add r20, r21, r17 }\n"
+ "move %0, r20\n"
+ "move %1, r21\n"
+ "move %2, r17\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1adduc_X0.c b/none/tests/tilegx/insn_test_v1adduc_X0.c
new file mode 100644
index 0000000..78936dd
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1adduc_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1adduc_X0.c
+//op=235
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x22ce703cb6ffeac4, 0x80948177d07e88f4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r14, -13316\n"
+ "shl16insli r14, r14, -18141\n"
+ "shl16insli r14, r14, -11937\n"
+ "shl16insli r14, r14, -15394\n"
+ "moveli r19, -22708\n"
+ "shl16insli r19, r19, -32336\n"
+ "shl16insli r19, r19, -14907\n"
+ "shl16insli r19, r19, -32360\n"
+ "moveli r50, -3633\n"
+ "shl16insli r50, r50, -22778\n"
+ "shl16insli r50, r50, -18593\n"
+ "shl16insli r50, r50, -30611\n"
+ "{ v1adduc r14, r19, r50 ; fnop }\n"
+ "move %0, r14\n"
+ "move %1, r19\n"
+ "move %2, r50\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1adduc_X1.c b/none/tests/tilegx/insn_test_v1adduc_X1.c
new file mode 100644
index 0000000..051e024
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1adduc_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1adduc_X1.c
+//op=235
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x22ce703cb6ffeac4, 0x80948177d07e88f4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r14, -13316\n"
+ "shl16insli r14, r14, -18141\n"
+ "shl16insli r14, r14, -11937\n"
+ "shl16insli r14, r14, -15394\n"
+ "moveli r19, -22708\n"
+ "shl16insli r19, r19, -32336\n"
+ "shl16insli r19, r19, -14907\n"
+ "shl16insli r19, r19, -32360\n"
+ "moveli r50, -3633\n"
+ "shl16insli r50, r50, -22778\n"
+ "shl16insli r50, r50, -18593\n"
+ "shl16insli r50, r50, -30611\n"
+ "{ fnop ; v1adduc r14, r19, r50 }\n"
+ "move %0, r14\n"
+ "move %1, r19\n"
+ "move %2, r50\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1adiffu_X0.c b/none/tests/tilegx/insn_test_v1adiffu_X0.c
new file mode 100644
index 0000000..c8d0973
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1adiffu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1adiffu_X0.c
+//op=236
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4b94365a94fc8379, 0xd398d9dcfc90866b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r2, 21980\n"
+ "shl16insli r2, r2, 6619\n"
+ "shl16insli r2, r2, -5633\n"
+ "shl16insli r2, r2, 14172\n"
+ "moveli r35, 208\n"
+ "shl16insli r35, r35, 20913\n"
+ "shl16insli r35, r35, 19131\n"
+ "shl16insli r35, r35, -17081\n"
+ "moveli r33, 25300\n"
+ "shl16insli r33, r33, 18828\n"
+ "shl16insli r33, r33, 835\n"
+ "shl16insli r33, r33, 10241\n"
+ "{ v1adiffu r2, r35, r33 ; fnop }\n"
+ "move %0, r2\n"
+ "move %1, r35\n"
+ "move %2, r33\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1avgu_X0.c b/none/tests/tilegx/insn_test_v1avgu_X0.c
new file mode 100644
index 0000000..c77f514
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1avgu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1avgu_X0.c
+//op=237
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xeaf60994f1256f, 0x96d7d7579295561d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r43, 31333\n"
+ "shl16insli r43, r43, 15554\n"
+ "shl16insli r43, r43, 16035\n"
+ "shl16insli r43, r43, -6284\n"
+ "moveli r15, -6999\n"
+ "shl16insli r15, r15, -24670\n"
+ "shl16insli r15, r15, -31990\n"
+ "shl16insli r15, r15, -6084\n"
+ "moveli r9, -29195\n"
+ "shl16insli r9, r9, -14971\n"
+ "shl16insli r9, r9, 21267\n"
+ "shl16insli r9, r9, -6933\n"
+ "{ v1avgu r43, r15, r9 ; fnop }\n"
+ "move %0, r43\n"
+ "move %1, r15\n"
+ "move %2, r9\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1cmpeq_X0.c b/none/tests/tilegx/insn_test_v1cmpeq_X0.c
new file mode 100644
index 0000000..26c2436
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1cmpeq_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1cmpeq_X0.c
+//op=238
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbc7e18adc4f4bcd4, 0xdd853a2377c4c1cd };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -28260\n"
+ "shl16insli r3, r3, -3800\n"
+ "shl16insli r3, r3, 26206\n"
+ "shl16insli r3, r3, 20590\n"
+ "moveli r43, -7555\n"
+ "shl16insli r43, r43, -10473\n"
+ "shl16insli r43, r43, 1769\n"
+ "shl16insli r43, r43, 20859\n"
+ "moveli r22, 31720\n"
+ "shl16insli r22, r22, -26184\n"
+ "shl16insli r22, r22, -29280\n"
+ "shl16insli r22, r22, 21783\n"
+ "{ v1cmpeq r3, r43, r22 ; fnop }\n"
+ "move %0, r3\n"
+ "move %1, r43\n"
+ "move %2, r22\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1cmpeq_X1.c b/none/tests/tilegx/insn_test_v1cmpeq_X1.c
new file mode 100644
index 0000000..d453b03
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1cmpeq_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1cmpeq_X1.c
+//op=238
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbc7e18adc4f4bcd4, 0xdd853a2377c4c1cd };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -28260\n"
+ "shl16insli r3, r3, -3800\n"
+ "shl16insli r3, r3, 26206\n"
+ "shl16insli r3, r3, 20590\n"
+ "moveli r43, -7555\n"
+ "shl16insli r43, r43, -10473\n"
+ "shl16insli r43, r43, 1769\n"
+ "shl16insli r43, r43, 20859\n"
+ "moveli r22, 31720\n"
+ "shl16insli r22, r22, -26184\n"
+ "shl16insli r22, r22, -29280\n"
+ "shl16insli r22, r22, 21783\n"
+ "{ fnop ; v1cmpeq r3, r43, r22 }\n"
+ "move %0, r3\n"
+ "move %1, r43\n"
+ "move %2, r22\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1cmpeqi_X0.c b/none/tests/tilegx/insn_test_v1cmpeqi_X0.c
new file mode 100644
index 0000000..b5300a6
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1cmpeqi_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v1cmpeqi_X0.c
+//op=239
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x645d1ce0b9aa791f, 0xdd076487e2dc381a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r33, 6146\n"
+ "shl16insli r33, r33, -18709\n"
+ "shl16insli r33, r33, -4572\n"
+ "shl16insli r33, r33, -2632\n"
+ "moveli r27, 18247\n"
+ "shl16insli r27, r27, 6533\n"
+ "shl16insli r27, r27, 16990\n"
+ "shl16insli r27, r27, 10640\n"
+ "{ v1cmpeqi r33, r27, 110 ; fnop }\n"
+ "move %0, r33\n"
+ "move %1, r27\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1cmpeqi_X1.c b/none/tests/tilegx/insn_test_v1cmpeqi_X1.c
new file mode 100644
index 0000000..e93dda4
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1cmpeqi_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v1cmpeqi_X1.c
+//op=239
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x645d1ce0b9aa791f, 0xdd076487e2dc381a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r33, 6146\n"
+ "shl16insli r33, r33, -18709\n"
+ "shl16insli r33, r33, -4572\n"
+ "shl16insli r33, r33, -2632\n"
+ "moveli r27, 18247\n"
+ "shl16insli r27, r27, 6533\n"
+ "shl16insli r27, r27, 16990\n"
+ "shl16insli r27, r27, 10640\n"
+ "{ fnop ; v1cmpeqi r33, r27, 110 }\n"
+ "move %0, r33\n"
+ "move %1, r27\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1cmples_X0.c b/none/tests/tilegx/insn_test_v1cmples_X0.c
new file mode 100644
index 0000000..136d35b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1cmples_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1cmples_X0.c
+//op=240
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9cc2101465cdabcc, 0xfd529a461f919c3b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r30, -398\n"
+ "shl16insli r30, r30, 9724\n"
+ "shl16insli r30, r30, -28764\n"
+ "shl16insli r30, r30, 25983\n"
+ "moveli r39, -18162\n"
+ "shl16insli r39, r39, 4413\n"
+ "shl16insli r39, r39, 14247\n"
+ "shl16insli r39, r39, 14892\n"
+ "moveli r9, 10415\n"
+ "shl16insli r9, r9, -24373\n"
+ "shl16insli r9, r9, 23725\n"
+ "shl16insli r9, r9, -29919\n"
+ "{ v1cmples r30, r39, r9 ; fnop }\n"
+ "move %0, r30\n"
+ "move %1, r39\n"
+ "move %2, r9\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1cmples_X1.c b/none/tests/tilegx/insn_test_v1cmples_X1.c
new file mode 100644
index 0000000..37bc683
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1cmples_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1cmples_X1.c
+//op=240
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9cc2101465cdabcc, 0xfd529a461f919c3b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r30, -398\n"
+ "shl16insli r30, r30, 9724\n"
+ "shl16insli r30, r30, -28764\n"
+ "shl16insli r30, r30, 25983\n"
+ "moveli r39, -18162\n"
+ "shl16insli r39, r39, 4413\n"
+ "shl16insli r39, r39, 14247\n"
+ "shl16insli r39, r39, 14892\n"
+ "moveli r9, 10415\n"
+ "shl16insli r9, r9, -24373\n"
+ "shl16insli r9, r9, 23725\n"
+ "shl16insli r9, r9, -29919\n"
+ "{ fnop ; v1cmples r30, r39, r9 }\n"
+ "move %0, r30\n"
+ "move %1, r39\n"
+ "move %2, r9\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1cmpleu_X0.c b/none/tests/tilegx/insn_test_v1cmpleu_X0.c
new file mode 100644
index 0000000..21d676d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1cmpleu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1cmpleu_X0.c
+//op=241
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf650c1dfb5e7ad42, 0x58b08e812190ba77 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -2057\n"
+ "shl16insli r3, r3, 27159\n"
+ "shl16insli r3, r3, -22172\n"
+ "shl16insli r3, r3, 8048\n"
+ "moveli r8, -12225\n"
+ "shl16insli r8, r8, -10603\n"
+ "shl16insli r8, r8, 1383\n"
+ "shl16insli r8, r8, -9619\n"
+ "moveli r14, -24673\n"
+ "shl16insli r14, r14, 32616\n"
+ "shl16insli r14, r14, 28197\n"
+ "shl16insli r14, r14, -4516\n"
+ "{ v1cmpleu r3, r8, r14 ; fnop }\n"
+ "move %0, r3\n"
+ "move %1, r8\n"
+ "move %2, r14\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1cmpleu_X1.c b/none/tests/tilegx/insn_test_v1cmpleu_X1.c
new file mode 100644
index 0000000..9d80d16
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1cmpleu_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1cmpleu_X1.c
+//op=241
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf650c1dfb5e7ad42, 0x58b08e812190ba77 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -2057\n"
+ "shl16insli r3, r3, 27159\n"
+ "shl16insli r3, r3, -22172\n"
+ "shl16insli r3, r3, 8048\n"
+ "moveli r8, -12225\n"
+ "shl16insli r8, r8, -10603\n"
+ "shl16insli r8, r8, 1383\n"
+ "shl16insli r8, r8, -9619\n"
+ "moveli r14, -24673\n"
+ "shl16insli r14, r14, 32616\n"
+ "shl16insli r14, r14, 28197\n"
+ "shl16insli r14, r14, -4516\n"
+ "{ fnop ; v1cmpleu r3, r8, r14 }\n"
+ "move %0, r3\n"
+ "move %1, r8\n"
+ "move %2, r14\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1cmplts_X0.c b/none/tests/tilegx/insn_test_v1cmplts_X0.c
new file mode 100644
index 0000000..ff6420f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1cmplts_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1cmplts_X0.c
+//op=242
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x955dd8bb2fd5225, 0xbf944e471ed68a09 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r24, -6390\n"
+ "shl16insli r24, r24, 7138\n"
+ "shl16insli r24, r24, -13688\n"
+ "shl16insli r24, r24, 18787\n"
+ "moveli r40, 19035\n"
+ "shl16insli r40, r40, -3036\n"
+ "shl16insli r40, r40, -31964\n"
+ "shl16insli r40, r40, -9865\n"
+ "moveli r0, -31939\n"
+ "shl16insli r0, r0, 30972\n"
+ "shl16insli r0, r0, 13500\n"
+ "shl16insli r0, r0, 23688\n"
+ "{ v1cmplts r24, r40, r0 ; fnop }\n"
+ "move %0, r24\n"
+ "move %1, r40\n"
+ "move %2, r0\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1cmplts_X1.c b/none/tests/tilegx/insn_test_v1cmplts_X1.c
new file mode 100644
index 0000000..be39062
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1cmplts_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1cmplts_X1.c
+//op=242
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x955dd8bb2fd5225, 0xbf944e471ed68a09 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r24, -6390\n"
+ "shl16insli r24, r24, 7138\n"
+ "shl16insli r24, r24, -13688\n"
+ "shl16insli r24, r24, 18787\n"
+ "moveli r40, 19035\n"
+ "shl16insli r40, r40, -3036\n"
+ "shl16insli r40, r40, -31964\n"
+ "shl16insli r40, r40, -9865\n"
+ "moveli r0, -31939\n"
+ "shl16insli r0, r0, 30972\n"
+ "shl16insli r0, r0, 13500\n"
+ "shl16insli r0, r0, 23688\n"
+ "{ fnop ; v1cmplts r24, r40, r0 }\n"
+ "move %0, r24\n"
+ "move %1, r40\n"
+ "move %2, r0\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1cmpltu_X0.c b/none/tests/tilegx/insn_test_v1cmpltu_X0.c
new file mode 100644
index 0000000..af45358
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1cmpltu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1cmpltu_X0.c
+//op=244
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2044e3daa009dd78, 0xae053c723a6c8e37 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r40, 25454\n"
+ "shl16insli r40, r40, 27378\n"
+ "shl16insli r40, r40, 27144\n"
+ "shl16insli r40, r40, -1050\n"
+ "moveli r29, -3584\n"
+ "shl16insli r29, r29, -12139\n"
+ "shl16insli r29, r29, 27236\n"
+ "shl16insli r29, r29, -11299\n"
+ "moveli r36, -23497\n"
+ "shl16insli r36, r36, 11245\n"
+ "shl16insli r36, r36, 19779\n"
+ "shl16insli r36, r36, 27653\n"
+ "{ v1cmpltu r40, r29, r36 ; fnop }\n"
+ "move %0, r40\n"
+ "move %1, r29\n"
+ "move %2, r36\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1cmpltu_X1.c b/none/tests/tilegx/insn_test_v1cmpltu_X1.c
new file mode 100644
index 0000000..05f8403
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1cmpltu_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1cmpltu_X1.c
+//op=244
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2044e3daa009dd78, 0xae053c723a6c8e37 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r40, 25454\n"
+ "shl16insli r40, r40, 27378\n"
+ "shl16insli r40, r40, 27144\n"
+ "shl16insli r40, r40, -1050\n"
+ "moveli r29, -3584\n"
+ "shl16insli r29, r29, -12139\n"
+ "shl16insli r29, r29, 27236\n"
+ "shl16insli r29, r29, -11299\n"
+ "moveli r36, -23497\n"
+ "shl16insli r36, r36, 11245\n"
+ "shl16insli r36, r36, 19779\n"
+ "shl16insli r36, r36, 27653\n"
+ "{ fnop ; v1cmpltu r40, r29, r36 }\n"
+ "move %0, r40\n"
+ "move %1, r29\n"
+ "move %2, r36\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1cmpne_X0.c b/none/tests/tilegx/insn_test_v1cmpne_X0.c
new file mode 100644
index 0000000..e666e77
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1cmpne_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1cmpne_X0.c
+//op=246
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x333c2ba4f5fc0778, 0x71782df005cc3618 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r12, -4257\n"
+ "shl16insli r12, r12, 16637\n"
+ "shl16insli r12, r12, -13862\n"
+ "shl16insli r12, r12, 2993\n"
+ "moveli r28, 19170\n"
+ "shl16insli r28, r28, -5999\n"
+ "shl16insli r28, r28, 20031\n"
+ "shl16insli r28, r28, -9404\n"
+ "moveli r13, 24886\n"
+ "shl16insli r13, r13, 6119\n"
+ "shl16insli r13, r13, -23856\n"
+ "shl16insli r13, r13, -8685\n"
+ "{ v1cmpne r12, r28, r13 ; fnop }\n"
+ "move %0, r12\n"
+ "move %1, r28\n"
+ "move %2, r13\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1cmpne_X1.c b/none/tests/tilegx/insn_test_v1cmpne_X1.c
new file mode 100644
index 0000000..7ab2489
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1cmpne_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1cmpne_X1.c
+//op=246
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x333c2ba4f5fc0778, 0x71782df005cc3618 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r12, -4257\n"
+ "shl16insli r12, r12, 16637\n"
+ "shl16insli r12, r12, -13862\n"
+ "shl16insli r12, r12, 2993\n"
+ "moveli r28, 19170\n"
+ "shl16insli r28, r28, -5999\n"
+ "shl16insli r28, r28, 20031\n"
+ "shl16insli r28, r28, -9404\n"
+ "moveli r13, 24886\n"
+ "shl16insli r13, r13, 6119\n"
+ "shl16insli r13, r13, -23856\n"
+ "shl16insli r13, r13, -8685\n"
+ "{ fnop ; v1cmpne r12, r28, r13 }\n"
+ "move %0, r12\n"
+ "move %1, r28\n"
+ "move %2, r13\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1ddotpu_X0.c b/none/tests/tilegx/insn_test_v1ddotpu_X0.c
new file mode 100644
index 0000000..4508259
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1ddotpu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1ddotpu_X0.c
+//op=247
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc5185c9ad40a6c8e, 0x38d738cd6b643ded };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -30305\n"
+ "shl16insli r38, r38, -15724\n"
+ "shl16insli r38, r38, 16680\n"
+ "shl16insli r38, r38, -25985\n"
+ "moveli r11, -14413\n"
+ "shl16insli r11, r11, -6278\n"
+ "shl16insli r11, r11, -14697\n"
+ "shl16insli r11, r11, -23431\n"
+ "moveli r4, 122\n"
+ "shl16insli r4, r4, 8399\n"
+ "shl16insli r4, r4, -22661\n"
+ "shl16insli r4, r4, -9174\n"
+ "{ v1ddotpu r38, r11, r4 ; fnop }\n"
+ "move %0, r38\n"
+ "move %1, r11\n"
+ "move %2, r4\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1ddotpua_X0.c b/none/tests/tilegx/insn_test_v1ddotpua_X0.c
new file mode 100644
index 0000000..002537e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1ddotpua_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1ddotpua_X0.c
+//op=248
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf81d7875fb56ceb1, 0x6d228375c43e27fe };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r26, 5758\n"
+ "shl16insli r26, r26, -26380\n"
+ "shl16insli r26, r26, 10010\n"
+ "shl16insli r26, r26, 27850\n"
+ "moveli r35, -28917\n"
+ "shl16insli r35, r35, -6384\n"
+ "shl16insli r35, r35, -11771\n"
+ "shl16insli r35, r35, -16008\n"
+ "moveli r48, -8573\n"
+ "shl16insli r48, r48, 9318\n"
+ "shl16insli r48, r48, -9607\n"
+ "shl16insli r48, r48, 22154\n"
+ "{ v1ddotpua r26, r35, r48 ; fnop }\n"
+ "move %0, r26\n"
+ "move %1, r35\n"
+ "move %2, r48\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1ddotpus_X0.c b/none/tests/tilegx/insn_test_v1ddotpus_X0.c
new file mode 100644
index 0000000..99e822a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1ddotpus_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1ddotpus_X0.c
+//op=249
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9870e08023534828, 0x669e8333dc6e20a4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r35, 27899\n"
+ "shl16insli r35, r35, -1363\n"
+ "shl16insli r35, r35, 695\n"
+ "shl16insli r35, r35, -3150\n"
+ "moveli r47, -31722\n"
+ "shl16insli r47, r47, 28986\n"
+ "shl16insli r47, r47, -27906\n"
+ "shl16insli r47, r47, -13798\n"
+ "moveli r39, 32546\n"
+ "shl16insli r39, r39, -25949\n"
+ "shl16insli r39, r39, -2759\n"
+ "shl16insli r39, r39, -21019\n"
+ "{ v1ddotpus r35, r47, r39 ; fnop }\n"
+ "move %0, r35\n"
+ "move %1, r47\n"
+ "move %2, r39\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1ddotpusa_X0.c b/none/tests/tilegx/insn_test_v1ddotpusa_X0.c
new file mode 100644
index 0000000..ce1e557
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1ddotpusa_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1ddotpusa_X0.c
+//op=250
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x3ae24f779a8d3dc, 0x6bfa391c07b5ae93 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r29, 11405\n"
+ "shl16insli r29, r29, 16621\n"
+ "shl16insli r29, r29, -29926\n"
+ "shl16insli r29, r29, -21425\n"
+ "moveli r22, 29339\n"
+ "shl16insli r22, r22, -30280\n"
+ "shl16insli r22, r22, 6890\n"
+ "shl16insli r22, r22, 27358\n"
+ "moveli r1, 30556\n"
+ "shl16insli r1, r1, -25484\n"
+ "shl16insli r1, r1, 28103\n"
+ "shl16insli r1, r1, 12543\n"
+ "{ v1ddotpusa r29, r22, r1 ; fnop }\n"
+ "move %0, r29\n"
+ "move %1, r22\n"
+ "move %2, r1\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1dotp_X0.c b/none/tests/tilegx/insn_test_v1dotp_X0.c
new file mode 100644
index 0000000..b23f637
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1dotp_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1dotp_X0.c
+//op=251
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7b812106b9ba177f, 0xa91bb9da3e399735 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r3, -2452\n"
+ "shl16insli r3, r3, -32096\n"
+ "shl16insli r3, r3, -11540\n"
+ "shl16insli r3, r3, 18694\n"
+ "moveli r42, -335\n"
+ "shl16insli r42, r42, -26011\n"
+ "shl16insli r42, r42, -23631\n"
+ "shl16insli r42, r42, -1594\n"
+ "moveli r44, -16908\n"
+ "shl16insli r44, r44, -28320\n"
+ "shl16insli r44, r44, 5956\n"
+ "shl16insli r44, r44, 28904\n"
+ "{ v1dotp r3, r42, r44 ; fnop }\n"
+ "move %0, r3\n"
+ "move %1, r42\n"
+ "move %2, r44\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1dotpa_X0.c b/none/tests/tilegx/insn_test_v1dotpa_X0.c
new file mode 100644
index 0000000..8914add
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1dotpa_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1dotpa_X0.c
+//op=252
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd02416e43b19c3f1, 0xb50b19b244ac7eb4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r4, 15584\n"
+ "shl16insli r4, r4, -16025\n"
+ "shl16insli r4, r4, 24621\n"
+ "shl16insli r4, r4, -25450\n"
+ "moveli r7, 14194\n"
+ "shl16insli r7, r7, 6886\n"
+ "shl16insli r7, r7, -25858\n"
+ "shl16insli r7, r7, -24609\n"
+ "moveli r0, 12923\n"
+ "shl16insli r0, r0, -8055\n"
+ "shl16insli r0, r0, -31361\n"
+ "shl16insli r0, r0, -7893\n"
+ "{ v1dotpa r4, r7, r0 ; fnop }\n"
+ "move %0, r4\n"
+ "move %1, r7\n"
+ "move %2, r0\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1dotpu_X0.c b/none/tests/tilegx/insn_test_v1dotpu_X0.c
new file mode 100644
index 0000000..21d304f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1dotpu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1dotpu_X0.c
+//op=253
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb9d12319fbf02182, 0x42d3871d0b55e0e5 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r20, 7058\n"
+ "shl16insli r20, r20, -10273\n"
+ "shl16insli r20, r20, -27400\n"
+ "shl16insli r20, r20, 410\n"
+ "moveli r27, -1572\n"
+ "shl16insli r27, r27, 7162\n"
+ "shl16insli r27, r27, -2477\n"
+ "shl16insli r27, r27, -2756\n"
+ "moveli r46, -23264\n"
+ "shl16insli r46, r46, 16614\n"
+ "shl16insli r46, r46, 28637\n"
+ "shl16insli r46, r46, 17411\n"
+ "{ v1dotpu r20, r27, r46 ; fnop }\n"
+ "move %0, r20\n"
+ "move %1, r27\n"
+ "move %2, r46\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1dotpua_X0.c b/none/tests/tilegx/insn_test_v1dotpua_X0.c
new file mode 100644
index 0000000..420c372
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1dotpua_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1dotpua_X0.c
+//op=254
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xba522198b7685638, 0x5038bdaa45b53cd3 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r20, -30432\n"
+ "shl16insli r20, r20, -21685\n"
+ "shl16insli r20, r20, -14635\n"
+ "shl16insli r20, r20, 15094\n"
+ "moveli r49, 3435\n"
+ "shl16insli r49, r49, 5337\n"
+ "shl16insli r49, r49, 12729\n"
+ "shl16insli r49, r49, -31162\n"
+ "moveli r38, -23611\n"
+ "shl16insli r38, r38, 9907\n"
+ "shl16insli r38, r38, 19129\n"
+ "shl16insli r38, r38, 30763\n"
+ "{ v1dotpua r20, r49, r38 ; fnop }\n"
+ "move %0, r20\n"
+ "move %1, r49\n"
+ "move %2, r38\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1dotpus_X0.c b/none/tests/tilegx/insn_test_v1dotpus_X0.c
new file mode 100644
index 0000000..4663f44
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1dotpus_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1dotpus_X0.c
+//op=255
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xff2786a3390067bd, 0x12d0fd16d91f87d7 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r30, -20178\n"
+ "shl16insli r30, r30, 16109\n"
+ "shl16insli r30, r30, -17955\n"
+ "shl16insli r30, r30, 766\n"
+ "moveli r30, -16791\n"
+ "shl16insli r30, r30, -775\n"
+ "shl16insli r30, r30, 8064\n"
+ "shl16insli r30, r30, 31392\n"
+ "moveli r48, 2300\n"
+ "shl16insli r48, r48, 6845\n"
+ "shl16insli r48, r48, -2405\n"
+ "shl16insli r48, r48, 31247\n"
+ "{ v1dotpus r30, r30, r48 ; fnop }\n"
+ "move %0, r30\n"
+ "move %1, r30\n"
+ "move %2, r48\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1dotpusa_X0.c b/none/tests/tilegx/insn_test_v1dotpusa_X0.c
new file mode 100644
index 0000000..64fa1fe
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1dotpusa_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1dotpusa_X0.c
+//op=256
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xea3e8d37b6aff6fb, 0xcef60e4c85b01644 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, 26537\n"
+ "shl16insli r11, r11, -7716\n"
+ "shl16insli r11, r11, 24513\n"
+ "shl16insli r11, r11, 8687\n"
+ "moveli r35, -7218\n"
+ "shl16insli r35, r35, 7896\n"
+ "shl16insli r35, r35, -22888\n"
+ "shl16insli r35, r35, -25968\n"
+ "moveli r39, -6406\n"
+ "shl16insli r39, r39, -8101\n"
+ "shl16insli r39, r39, 21933\n"
+ "shl16insli r39, r39, 5916\n"
+ "{ v1dotpusa r11, r35, r39 ; fnop }\n"
+ "move %0, r11\n"
+ "move %1, r35\n"
+ "move %2, r39\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1int_h_X0.c b/none/tests/tilegx/insn_test_v1int_h_X0.c
new file mode 100644
index 0000000..935bc44
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1int_h_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1int_h_X0.c
+//op=257
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe9a8302931b95203, 0x70bdff1ab2dd150d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r21, 8325\n"
+ "shl16insli r21, r21, -18852\n"
+ "shl16insli r21, r21, 5136\n"
+ "shl16insli r21, r21, 25114\n"
+ "moveli r14, -28465\n"
+ "shl16insli r14, r14, -20971\n"
+ "shl16insli r14, r14, 28669\n"
+ "shl16insli r14, r14, 5613\n"
+ "moveli r17, -533\n"
+ "shl16insli r17, r17, -12789\n"
+ "shl16insli r17, r17, -10981\n"
+ "shl16insli r17, r17, -30754\n"
+ "{ v1int_h r21, r14, r17 ; fnop }\n"
+ "move %0, r21\n"
+ "move %1, r14\n"
+ "move %2, r17\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1int_h_X1.c b/none/tests/tilegx/insn_test_v1int_h_X1.c
new file mode 100644
index 0000000..982962c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1int_h_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1int_h_X1.c
+//op=257
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe9a8302931b95203, 0x70bdff1ab2dd150d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r21, 8325\n"
+ "shl16insli r21, r21, -18852\n"
+ "shl16insli r21, r21, 5136\n"
+ "shl16insli r21, r21, 25114\n"
+ "moveli r14, -28465\n"
+ "shl16insli r14, r14, -20971\n"
+ "shl16insli r14, r14, 28669\n"
+ "shl16insli r14, r14, 5613\n"
+ "moveli r17, -533\n"
+ "shl16insli r17, r17, -12789\n"
+ "shl16insli r17, r17, -10981\n"
+ "shl16insli r17, r17, -30754\n"
+ "{ fnop ; v1int_h r21, r14, r17 }\n"
+ "move %0, r21\n"
+ "move %1, r14\n"
+ "move %2, r17\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1int_l_X0.c b/none/tests/tilegx/insn_test_v1int_l_X0.c
new file mode 100644
index 0000000..4bac650
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1int_l_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1int_l_X0.c
+//op=258
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x25203e3a92c5e67a, 0x3ab13aa81a1f8e6 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, 16040\n"
+ "shl16insli r16, r16, 13539\n"
+ "shl16insli r16, r16, -10611\n"
+ "shl16insli r16, r16, 18456\n"
+ "moveli r1, -8860\n"
+ "shl16insli r1, r1, 10696\n"
+ "shl16insli r1, r1, -32518\n"
+ "shl16insli r1, r1, 20582\n"
+ "moveli r32, 25660\n"
+ "shl16insli r32, r32, -31058\n"
+ "shl16insli r32, r32, 3321\n"
+ "shl16insli r32, r32, 742\n"
+ "{ v1int_l r16, r1, r32 ; fnop }\n"
+ "move %0, r16\n"
+ "move %1, r1\n"
+ "move %2, r32\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1int_l_X1.c b/none/tests/tilegx/insn_test_v1int_l_X1.c
new file mode 100644
index 0000000..a610b85
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1int_l_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1int_l_X1.c
+//op=258
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x25203e3a92c5e67a, 0x3ab13aa81a1f8e6 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, 16040\n"
+ "shl16insli r16, r16, 13539\n"
+ "shl16insli r16, r16, -10611\n"
+ "shl16insli r16, r16, 18456\n"
+ "moveli r1, -8860\n"
+ "shl16insli r1, r1, 10696\n"
+ "shl16insli r1, r1, -32518\n"
+ "shl16insli r1, r1, 20582\n"
+ "moveli r32, 25660\n"
+ "shl16insli r32, r32, -31058\n"
+ "shl16insli r32, r32, 3321\n"
+ "shl16insli r32, r32, 742\n"
+ "{ fnop ; v1int_l r16, r1, r32 }\n"
+ "move %0, r16\n"
+ "move %1, r1\n"
+ "move %2, r32\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1maxu_X0.c b/none/tests/tilegx/insn_test_v1maxu_X0.c
new file mode 100644
index 0000000..4098831
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1maxu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1maxu_X0.c
+//op=259
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5555b89e33103d34, 0x72ce0e1d1ecdfc7b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r7, 31643\n"
+ "shl16insli r7, r7, -418\n"
+ "shl16insli r7, r7, -25830\n"
+ "shl16insli r7, r7, 267\n"
+ "moveli r17, 21415\n"
+ "shl16insli r17, r17, 28561\n"
+ "shl16insli r17, r17, 26253\n"
+ "shl16insli r17, r17, -24335\n"
+ "moveli r5, -8528\n"
+ "shl16insli r5, r5, 8536\n"
+ "shl16insli r5, r5, -30783\n"
+ "shl16insli r5, r5, 721\n"
+ "{ v1maxu r7, r17, r5 ; fnop }\n"
+ "move %0, r7\n"
+ "move %1, r17\n"
+ "move %2, r5\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1maxu_X1.c b/none/tests/tilegx/insn_test_v1maxu_X1.c
new file mode 100644
index 0000000..baaa366
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1maxu_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1maxu_X1.c
+//op=259
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5555b89e33103d34, 0x72ce0e1d1ecdfc7b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r7, 31643\n"
+ "shl16insli r7, r7, -418\n"
+ "shl16insli r7, r7, -25830\n"
+ "shl16insli r7, r7, 267\n"
+ "moveli r17, 21415\n"
+ "shl16insli r17, r17, 28561\n"
+ "shl16insli r17, r17, 26253\n"
+ "shl16insli r17, r17, -24335\n"
+ "moveli r5, -8528\n"
+ "shl16insli r5, r5, 8536\n"
+ "shl16insli r5, r5, -30783\n"
+ "shl16insli r5, r5, 721\n"
+ "{ fnop ; v1maxu r7, r17, r5 }\n"
+ "move %0, r7\n"
+ "move %1, r17\n"
+ "move %2, r5\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1minu_X0.c b/none/tests/tilegx/insn_test_v1minu_X0.c
new file mode 100644
index 0000000..a29cd79
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1minu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1minu_X0.c
+//op=261
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe5ffde572843204c, 0xf80a73ea5b48cd2e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r48, -8159\n"
+ "shl16insli r48, r48, -19405\n"
+ "shl16insli r48, r48, -6882\n"
+ "shl16insli r48, r48, 24332\n"
+ "moveli r5, 588\n"
+ "shl16insli r5, r5, 25418\n"
+ "shl16insli r5, r5, -27674\n"
+ "shl16insli r5, r5, 2111\n"
+ "moveli r23, -19496\n"
+ "shl16insli r23, r23, -22831\n"
+ "shl16insli r23, r23, -22278\n"
+ "shl16insli r23, r23, 2692\n"
+ "{ v1minu r48, r5, r23 ; fnop }\n"
+ "move %0, r48\n"
+ "move %1, r5\n"
+ "move %2, r23\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1minu_X1.c b/none/tests/tilegx/insn_test_v1minu_X1.c
new file mode 100644
index 0000000..5ed1440
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1minu_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1minu_X1.c
+//op=261
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe5ffde572843204c, 0xf80a73ea5b48cd2e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r48, -8159\n"
+ "shl16insli r48, r48, -19405\n"
+ "shl16insli r48, r48, -6882\n"
+ "shl16insli r48, r48, 24332\n"
+ "moveli r5, 588\n"
+ "shl16insli r5, r5, 25418\n"
+ "shl16insli r5, r5, -27674\n"
+ "shl16insli r5, r5, 2111\n"
+ "moveli r23, -19496\n"
+ "shl16insli r23, r23, -22831\n"
+ "shl16insli r23, r23, -22278\n"
+ "shl16insli r23, r23, 2692\n"
+ "{ fnop ; v1minu r48, r5, r23 }\n"
+ "move %0, r48\n"
+ "move %1, r5\n"
+ "move %2, r23\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1mnz_X0.c b/none/tests/tilegx/insn_test_v1mnz_X0.c
new file mode 100644
index 0000000..b5b2d8f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1mnz_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1mnz_X0.c
+//op=263
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x3713ce4eed37fdb1, 0xb8fb1c28cc3fba32 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r37, -32459\n"
+ "shl16insli r37, r37, 16523\n"
+ "shl16insli r37, r37, 2092\n"
+ "shl16insli r37, r37, -8699\n"
+ "moveli r5, 8954\n"
+ "shl16insli r5, r5, 9384\n"
+ "shl16insli r5, r5, 3635\n"
+ "shl16insli r5, r5, -28024\n"
+ "moveli r22, 7513\n"
+ "shl16insli r22, r22, -1317\n"
+ "shl16insli r22, r22, 32450\n"
+ "shl16insli r22, r22, -11880\n"
+ "{ v1mnz r37, r5, r22 ; fnop }\n"
+ "move %0, r37\n"
+ "move %1, r5\n"
+ "move %2, r22\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1mnz_X1.c b/none/tests/tilegx/insn_test_v1mnz_X1.c
new file mode 100644
index 0000000..1dd3d93
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1mnz_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1mnz_X1.c
+//op=263
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x3713ce4eed37fdb1, 0xb8fb1c28cc3fba32 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r37, -32459\n"
+ "shl16insli r37, r37, 16523\n"
+ "shl16insli r37, r37, 2092\n"
+ "shl16insli r37, r37, -8699\n"
+ "moveli r5, 8954\n"
+ "shl16insli r5, r5, 9384\n"
+ "shl16insli r5, r5, 3635\n"
+ "shl16insli r5, r5, -28024\n"
+ "moveli r22, 7513\n"
+ "shl16insli r22, r22, -1317\n"
+ "shl16insli r22, r22, 32450\n"
+ "shl16insli r22, r22, -11880\n"
+ "{ fnop ; v1mnz r37, r5, r22 }\n"
+ "move %0, r37\n"
+ "move %1, r5\n"
+ "move %2, r22\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1multu_X0.c b/none/tests/tilegx/insn_test_v1multu_X0.c
new file mode 100644
index 0000000..b83e49f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1multu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1multu_X0.c
+//op=264
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x68357d0341698c99, 0x3076e248a1b03309 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r41, 3184\n"
+ "shl16insli r41, r41, 7750\n"
+ "shl16insli r41, r41, -24327\n"
+ "shl16insli r41, r41, 22846\n"
+ "moveli r20, -22618\n"
+ "shl16insli r20, r20, 24630\n"
+ "shl16insli r20, r20, -15349\n"
+ "shl16insli r20, r20, 29173\n"
+ "moveli r44, 21939\n"
+ "shl16insli r44, r44, 20800\n"
+ "shl16insli r44, r44, 15363\n"
+ "shl16insli r44, r44, -32405\n"
+ "{ v1multu r41, r20, r44 ; fnop }\n"
+ "move %0, r41\n"
+ "move %1, r20\n"
+ "move %2, r44\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1mulu_X0.c b/none/tests/tilegx/insn_test_v1mulu_X0.c
new file mode 100644
index 0000000..5103f66
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1mulu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1mulu_X0.c
+//op=265
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xc6ae3df2f165e603, 0x4124d3b9cd881478 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r27, -8005\n"
+ "shl16insli r27, r27, 29496\n"
+ "shl16insli r27, r27, 24596\n"
+ "shl16insli r27, r27, 10312\n"
+ "moveli r8, -21695\n"
+ "shl16insli r8, r8, 9862\n"
+ "shl16insli r8, r8, -14356\n"
+ "shl16insli r8, r8, -32187\n"
+ "moveli r13, -16854\n"
+ "shl16insli r13, r13, 30079\n"
+ "shl16insli r13, r13, -7543\n"
+ "shl16insli r13, r13, 13209\n"
+ "{ v1mulu r27, r8, r13 ; fnop }\n"
+ "move %0, r27\n"
+ "move %1, r8\n"
+ "move %2, r13\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1mulus_X0.c b/none/tests/tilegx/insn_test_v1mulus_X0.c
new file mode 100644
index 0000000..1494618
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1mulus_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1mulus_X0.c
+//op=266
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x88507c682c9fb1d4, 0xe99ff6bbb270ebf };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r14, -18039\n"
+ "shl16insli r14, r14, 4267\n"
+ "shl16insli r14, r14, 12150\n"
+ "shl16insli r14, r14, 11106\n"
+ "moveli r3, 24521\n"
+ "shl16insli r3, r3, -15738\n"
+ "shl16insli r3, r3, -31870\n"
+ "shl16insli r3, r3, -24660\n"
+ "moveli r15, -31630\n"
+ "shl16insli r15, r15, -11693\n"
+ "shl16insli r15, r15, 19273\n"
+ "shl16insli r15, r15, 31577\n"
+ "{ v1mulus r14, r3, r15 ; fnop }\n"
+ "move %0, r14\n"
+ "move %1, r3\n"
+ "move %2, r15\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1mz_X0.c b/none/tests/tilegx/insn_test_v1mz_X0.c
new file mode 100644
index 0000000..a152275
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1mz_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1mz_X0.c
+//op=267
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x1b3ff0e0443a3be1, 0x220687ea6e937cd5 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, 4964\n"
+ "shl16insli r38, r38, -27298\n"
+ "shl16insli r38, r38, 27287\n"
+ "shl16insli r38, r38, 25242\n"
+ "moveli r45, 12630\n"
+ "shl16insli r45, r45, 24867\n"
+ "shl16insli r45, r45, -32060\n"
+ "shl16insli r45, r45, 29383\n"
+ "moveli r38, -6355\n"
+ "shl16insli r38, r38, -29829\n"
+ "shl16insli r38, r38, 8624\n"
+ "shl16insli r38, r38, -6732\n"
+ "{ v1mz r38, r45, r38 ; fnop }\n"
+ "move %0, r38\n"
+ "move %1, r45\n"
+ "move %2, r38\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1mz_X1.c b/none/tests/tilegx/insn_test_v1mz_X1.c
new file mode 100644
index 0000000..d7c8755
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1mz_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1mz_X1.c
+//op=267
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x1b3ff0e0443a3be1, 0x220687ea6e937cd5 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, 4964\n"
+ "shl16insli r38, r38, -27298\n"
+ "shl16insli r38, r38, 27287\n"
+ "shl16insli r38, r38, 25242\n"
+ "moveli r45, 12630\n"
+ "shl16insli r45, r45, 24867\n"
+ "shl16insli r45, r45, -32060\n"
+ "shl16insli r45, r45, 29383\n"
+ "moveli r38, -6355\n"
+ "shl16insli r38, r38, -29829\n"
+ "shl16insli r38, r38, 8624\n"
+ "shl16insli r38, r38, -6732\n"
+ "{ fnop ; v1mz r38, r45, r38 }\n"
+ "move %0, r38\n"
+ "move %1, r45\n"
+ "move %2, r38\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1sadau_X0.c b/none/tests/tilegx/insn_test_v1sadau_X0.c
new file mode 100644
index 0000000..155f814
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1sadau_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1sadau_X0.c
+//op=268
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x75810b48447f8cd8, 0x2f3ac3e001892397 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r15, 16969\n"
+ "shl16insli r15, r15, 21355\n"
+ "shl16insli r15, r15, -13594\n"
+ "shl16insli r15, r15, 31543\n"
+ "moveli r46, -32304\n"
+ "shl16insli r46, r46, 5880\n"
+ "shl16insli r46, r46, 26751\n"
+ "shl16insli r46, r46, 15077\n"
+ "moveli r45, -22749\n"
+ "shl16insli r45, r45, -6105\n"
+ "shl16insli r45, r45, 23283\n"
+ "shl16insli r45, r45, 28386\n"
+ "{ v1sadau r15, r46, r45 ; fnop }\n"
+ "move %0, r15\n"
+ "move %1, r46\n"
+ "move %2, r45\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1sadu_X0.c b/none/tests/tilegx/insn_test_v1sadu_X0.c
new file mode 100644
index 0000000..99b77bf
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1sadu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1sadu_X0.c
+//op=269
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xdb49fd06b08ce7b9, 0xa5181ef50e01b108 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r23, 21116\n"
+ "shl16insli r23, r23, 9443\n"
+ "shl16insli r23, r23, -5433\n"
+ "shl16insli r23, r23, -6455\n"
+ "moveli r15, 21546\n"
+ "shl16insli r15, r15, -20814\n"
+ "shl16insli r15, r15, -29149\n"
+ "shl16insli r15, r15, 28694\n"
+ "moveli r5, 9956\n"
+ "shl16insli r5, r5, -29770\n"
+ "shl16insli r5, r5, 32138\n"
+ "shl16insli r5, r5, 24785\n"
+ "{ v1sadu r23, r15, r5 ; fnop }\n"
+ "move %0, r23\n"
+ "move %1, r15\n"
+ "move %2, r5\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1shl_X0.c b/none/tests/tilegx/insn_test_v1shl_X0.c
new file mode 100644
index 0000000..3fd853d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1shl_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1shl_X0.c
+//op=270
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe89dbdd9027e7e2c, 0x8f37eee6381b10aa };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r47, 31287\n"
+ "shl16insli r47, r47, -16865\n"
+ "shl16insli r47, r47, 32203\n"
+ "shl16insli r47, r47, 26808\n"
+ "moveli r20, -31597\n"
+ "shl16insli r20, r20, -25798\n"
+ "shl16insli r20, r20, 24137\n"
+ "shl16insli r20, r20, -18758\n"
+ "moveli r18, 29925\n"
+ "shl16insli r18, r18, -28562\n"
+ "shl16insli r18, r18, 19610\n"
+ "shl16insli r18, r18, 28019\n"
+ "{ v1shl r47, r20, r18 ; fnop }\n"
+ "move %0, r47\n"
+ "move %1, r20\n"
+ "move %2, r18\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1shl_X1.c b/none/tests/tilegx/insn_test_v1shl_X1.c
new file mode 100644
index 0000000..c183230
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1shl_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1shl_X1.c
+//op=270
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe89dbdd9027e7e2c, 0x8f37eee6381b10aa };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r47, 31287\n"
+ "shl16insli r47, r47, -16865\n"
+ "shl16insli r47, r47, 32203\n"
+ "shl16insli r47, r47, 26808\n"
+ "moveli r20, -31597\n"
+ "shl16insli r20, r20, -25798\n"
+ "shl16insli r20, r20, 24137\n"
+ "shl16insli r20, r20, -18758\n"
+ "moveli r18, 29925\n"
+ "shl16insli r18, r18, -28562\n"
+ "shl16insli r18, r18, 19610\n"
+ "shl16insli r18, r18, 28019\n"
+ "{ fnop ; v1shl r47, r20, r18 }\n"
+ "move %0, r47\n"
+ "move %1, r20\n"
+ "move %2, r18\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1shli_X0.c b/none/tests/tilegx/insn_test_v1shli_X0.c
new file mode 100644
index 0000000..981c25e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1shli_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v1shli_X0.c
+//op=271
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x83de1f8744af2d85, 0x6f2ecad32a189723 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, -23389\n"
+ "shl16insli r16, r16, 14250\n"
+ "shl16insli r16, r16, -12431\n"
+ "shl16insli r16, r16, 3789\n"
+ "moveli r46, 12068\n"
+ "shl16insli r46, r46, 8339\n"
+ "shl16insli r46, r46, 11978\n"
+ "shl16insli r46, r46, 15868\n"
+ "{ v1shli r16, r46, 47 ; fnop }\n"
+ "move %0, r16\n"
+ "move %1, r46\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1shli_X1.c b/none/tests/tilegx/insn_test_v1shli_X1.c
new file mode 100644
index 0000000..9515057
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1shli_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v1shli_X1.c
+//op=271
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x83de1f8744af2d85, 0x6f2ecad32a189723 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r16, -23389\n"
+ "shl16insli r16, r16, 14250\n"
+ "shl16insli r16, r16, -12431\n"
+ "shl16insli r16, r16, 3789\n"
+ "moveli r46, 12068\n"
+ "shl16insli r46, r46, 8339\n"
+ "shl16insli r46, r46, 11978\n"
+ "shl16insli r46, r46, 15868\n"
+ "{ fnop ; v1shli r16, r46, 47 }\n"
+ "move %0, r16\n"
+ "move %1, r46\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1shrs_X0.c b/none/tests/tilegx/insn_test_v1shrs_X0.c
new file mode 100644
index 0000000..ac5bfdf
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1shrs_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1shrs_X0.c
+//op=272
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x63cf7032972114e1, 0x25733d8b5dc477b4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, -18049\n"
+ "shl16insli r22, r22, 22607\n"
+ "shl16insli r22, r22, -26435\n"
+ "shl16insli r22, r22, 16640\n"
+ "moveli r0, -23960\n"
+ "shl16insli r0, r0, 21412\n"
+ "shl16insli r0, r0, 5756\n"
+ "shl16insli r0, r0, -23361\n"
+ "moveli r30, -27381\n"
+ "shl16insli r30, r30, -5985\n"
+ "shl16insli r30, r30, 29874\n"
+ "shl16insli r30, r30, 15106\n"
+ "{ v1shrs r22, r0, r30 ; fnop }\n"
+ "move %0, r22\n"
+ "move %1, r0\n"
+ "move %2, r30\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1shrs_X1.c b/none/tests/tilegx/insn_test_v1shrs_X1.c
new file mode 100644
index 0000000..c5c27ae
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1shrs_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1shrs_X1.c
+//op=272
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x63cf7032972114e1, 0x25733d8b5dc477b4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, -18049\n"
+ "shl16insli r22, r22, 22607\n"
+ "shl16insli r22, r22, -26435\n"
+ "shl16insli r22, r22, 16640\n"
+ "moveli r0, -23960\n"
+ "shl16insli r0, r0, 21412\n"
+ "shl16insli r0, r0, 5756\n"
+ "shl16insli r0, r0, -23361\n"
+ "moveli r30, -27381\n"
+ "shl16insli r30, r30, -5985\n"
+ "shl16insli r30, r30, 29874\n"
+ "shl16insli r30, r30, 15106\n"
+ "{ fnop ; v1shrs r22, r0, r30 }\n"
+ "move %0, r22\n"
+ "move %1, r0\n"
+ "move %2, r30\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1shrsi_X0.c b/none/tests/tilegx/insn_test_v1shrsi_X0.c
new file mode 100644
index 0000000..c416ab7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1shrsi_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v1shrsi_X0.c
+//op=273
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x99db15856c0b4de, 0x7721cf058b98c6d4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r5, -12155\n"
+ "shl16insli r5, r5, -29090\n"
+ "shl16insli r5, r5, 11972\n"
+ "shl16insli r5, r5, -26553\n"
+ "moveli r17, 13958\n"
+ "shl16insli r17, r17, -23061\n"
+ "shl16insli r17, r17, -20\n"
+ "shl16insli r17, r17, 9148\n"
+ "{ v1shrsi r5, r17, 58 ; fnop }\n"
+ "move %0, r5\n"
+ "move %1, r17\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1shrsi_X1.c b/none/tests/tilegx/insn_test_v1shrsi_X1.c
new file mode 100644
index 0000000..9227f28
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1shrsi_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v1shrsi_X1.c
+//op=273
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x99db15856c0b4de, 0x7721cf058b98c6d4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r5, -12155\n"
+ "shl16insli r5, r5, -29090\n"
+ "shl16insli r5, r5, 11972\n"
+ "shl16insli r5, r5, -26553\n"
+ "moveli r17, 13958\n"
+ "shl16insli r17, r17, -23061\n"
+ "shl16insli r17, r17, -20\n"
+ "shl16insli r17, r17, 9148\n"
+ "{ fnop ; v1shrsi r5, r17, 58 }\n"
+ "move %0, r5\n"
+ "move %1, r17\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1shru_X0.c b/none/tests/tilegx/insn_test_v1shru_X0.c
new file mode 100644
index 0000000..70da6ba
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1shru_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1shru_X0.c
+//op=274
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9e4137a4fbfd19fc, 0xe11d6a52db1557dd };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r19, -27667\n"
+ "shl16insli r19, r19, -7882\n"
+ "shl16insli r19, r19, 17186\n"
+ "shl16insli r19, r19, 17173\n"
+ "moveli r1, 31681\n"
+ "shl16insli r1, r1, 6366\n"
+ "shl16insli r1, r1, -2389\n"
+ "shl16insli r1, r1, 19110\n"
+ "moveli r25, 16926\n"
+ "shl16insli r25, r25, -28231\n"
+ "shl16insli r25, r25, -13659\n"
+ "shl16insli r25, r25, 19027\n"
+ "{ v1shru r19, r1, r25 ; fnop }\n"
+ "move %0, r19\n"
+ "move %1, r1\n"
+ "move %2, r25\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1shru_X1.c b/none/tests/tilegx/insn_test_v1shru_X1.c
new file mode 100644
index 0000000..f28a8c0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1shru_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1shru_X1.c
+//op=274
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9e4137a4fbfd19fc, 0xe11d6a52db1557dd };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r19, -27667\n"
+ "shl16insli r19, r19, -7882\n"
+ "shl16insli r19, r19, 17186\n"
+ "shl16insli r19, r19, 17173\n"
+ "moveli r1, 31681\n"
+ "shl16insli r1, r1, 6366\n"
+ "shl16insli r1, r1, -2389\n"
+ "shl16insli r1, r1, 19110\n"
+ "moveli r25, 16926\n"
+ "shl16insli r25, r25, -28231\n"
+ "shl16insli r25, r25, -13659\n"
+ "shl16insli r25, r25, 19027\n"
+ "{ fnop ; v1shru r19, r1, r25 }\n"
+ "move %0, r19\n"
+ "move %1, r1\n"
+ "move %2, r25\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1shrui_X0.c b/none/tests/tilegx/insn_test_v1shrui_X0.c
new file mode 100644
index 0000000..081c275
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1shrui_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v1shrui_X0.c
+//op=275
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x420e29019dd4c946, 0x562bb4e51ed838f4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, -14185\n"
+ "shl16insli r11, r11, 11751\n"
+ "shl16insli r11, r11, 25109\n"
+ "shl16insli r11, r11, 30569\n"
+ "moveli r18, 3022\n"
+ "shl16insli r18, r18, -17758\n"
+ "shl16insli r18, r18, 25795\n"
+ "shl16insli r18, r18, 7417\n"
+ "{ v1shrui r11, r18, 41 ; fnop }\n"
+ "move %0, r11\n"
+ "move %1, r18\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1shrui_X1.c b/none/tests/tilegx/insn_test_v1shrui_X1.c
new file mode 100644
index 0000000..792afcb
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1shrui_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v1shrui_X1.c
+//op=275
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x420e29019dd4c946, 0x562bb4e51ed838f4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, -14185\n"
+ "shl16insli r11, r11, 11751\n"
+ "shl16insli r11, r11, 25109\n"
+ "shl16insli r11, r11, 30569\n"
+ "moveli r18, 3022\n"
+ "shl16insli r18, r18, -17758\n"
+ "shl16insli r18, r18, 25795\n"
+ "shl16insli r18, r18, 7417\n"
+ "{ fnop ; v1shrui r11, r18, 41 }\n"
+ "move %0, r11\n"
+ "move %1, r18\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1sub_X0.c b/none/tests/tilegx/insn_test_v1sub_X0.c
new file mode 100644
index 0000000..d32340f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1sub_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1sub_X0.c
+//op=276
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x1fe54969a93a157a, 0x778f2f6f17d9003b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r44, 21888\n"
+ "shl16insli r44, r44, -8663\n"
+ "shl16insli r44, r44, -14905\n"
+ "shl16insli r44, r44, -14362\n"
+ "moveli r26, -18766\n"
+ "shl16insli r26, r26, 19438\n"
+ "shl16insli r26, r26, 15394\n"
+ "shl16insli r26, r26, -6172\n"
+ "moveli r24, 28503\n"
+ "shl16insli r24, r24, 24946\n"
+ "shl16insli r24, r24, 28527\n"
+ "shl16insli r24, r24, 6539\n"
+ "{ v1sub r44, r26, r24 ; fnop }\n"
+ "move %0, r44\n"
+ "move %1, r26\n"
+ "move %2, r24\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1sub_X1.c b/none/tests/tilegx/insn_test_v1sub_X1.c
new file mode 100644
index 0000000..4c97b9d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1sub_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1sub_X1.c
+//op=276
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x1fe54969a93a157a, 0x778f2f6f17d9003b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r44, 21888\n"
+ "shl16insli r44, r44, -8663\n"
+ "shl16insli r44, r44, -14905\n"
+ "shl16insli r44, r44, -14362\n"
+ "moveli r26, -18766\n"
+ "shl16insli r26, r26, 19438\n"
+ "shl16insli r26, r26, 15394\n"
+ "shl16insli r26, r26, -6172\n"
+ "moveli r24, 28503\n"
+ "shl16insli r24, r24, 24946\n"
+ "shl16insli r24, r24, 28527\n"
+ "shl16insli r24, r24, 6539\n"
+ "{ fnop ; v1sub r44, r26, r24 }\n"
+ "move %0, r44\n"
+ "move %1, r26\n"
+ "move %2, r24\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1subuc_X0.c b/none/tests/tilegx/insn_test_v1subuc_X0.c
new file mode 100644
index 0000000..a7911d3
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1subuc_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1subuc_X0.c
+//op=277
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xaec371f1597db508, 0x70a50c305e0116b3 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r1, -32522\n"
+ "shl16insli r1, r1, -12465\n"
+ "shl16insli r1, r1, 13861\n"
+ "shl16insli r1, r1, 7011\n"
+ "moveli r13, 25648\n"
+ "shl16insli r13, r13, 19640\n"
+ "shl16insli r13, r13, -32625\n"
+ "shl16insli r13, r13, -6642\n"
+ "moveli r6, 4519\n"
+ "shl16insli r6, r6, 25115\n"
+ "shl16insli r6, r6, 25290\n"
+ "shl16insli r6, r6, -28916\n"
+ "{ v1subuc r1, r13, r6 ; fnop }\n"
+ "move %0, r1\n"
+ "move %1, r13\n"
+ "move %2, r6\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v1subuc_X1.c b/none/tests/tilegx/insn_test_v1subuc_X1.c
new file mode 100644
index 0000000..aa0abe0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v1subuc_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v1subuc_X1.c
+//op=277
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xaec371f1597db508, 0x70a50c305e0116b3 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r1, -32522\n"
+ "shl16insli r1, r1, -12465\n"
+ "shl16insli r1, r1, 13861\n"
+ "shl16insli r1, r1, 7011\n"
+ "moveli r13, 25648\n"
+ "shl16insli r13, r13, 19640\n"
+ "shl16insli r13, r13, -32625\n"
+ "shl16insli r13, r13, -6642\n"
+ "moveli r6, 4519\n"
+ "shl16insli r6, r6, 25115\n"
+ "shl16insli r6, r6, 25290\n"
+ "shl16insli r6, r6, -28916\n"
+ "{ fnop ; v1subuc r1, r13, r6 }\n"
+ "move %0, r1\n"
+ "move %1, r13\n"
+ "move %2, r6\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2add_X0.c b/none/tests/tilegx/insn_test_v2add_X0.c
new file mode 100644
index 0000000..edff8f6
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2add_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2add_X0.c
+//op=278
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x88b76c744163208a, 0xab1fe60bd5f86c0d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r48, -20701\n"
+ "shl16insli r48, r48, 19319\n"
+ "shl16insli r48, r48, -14144\n"
+ "shl16insli r48, r48, -17797\n"
+ "moveli r42, -26180\n"
+ "shl16insli r42, r42, -32480\n"
+ "shl16insli r42, r42, -16635\n"
+ "shl16insli r42, r42, -11404\n"
+ "moveli r12, 15399\n"
+ "shl16insli r12, r12, 19647\n"
+ "shl16insli r12, r12, -13624\n"
+ "shl16insli r12, r12, 29718\n"
+ "{ v2add r48, r42, r12 ; fnop }\n"
+ "move %0, r48\n"
+ "move %1, r42\n"
+ "move %2, r12\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2add_X1.c b/none/tests/tilegx/insn_test_v2add_X1.c
new file mode 100644
index 0000000..9cbed50
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2add_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2add_X1.c
+//op=278
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x88b76c744163208a, 0xab1fe60bd5f86c0d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r48, -20701\n"
+ "shl16insli r48, r48, 19319\n"
+ "shl16insli r48, r48, -14144\n"
+ "shl16insli r48, r48, -17797\n"
+ "moveli r42, -26180\n"
+ "shl16insli r42, r42, -32480\n"
+ "shl16insli r42, r42, -16635\n"
+ "shl16insli r42, r42, -11404\n"
+ "moveli r12, 15399\n"
+ "shl16insli r12, r12, 19647\n"
+ "shl16insli r12, r12, -13624\n"
+ "shl16insli r12, r12, 29718\n"
+ "{ fnop ; v2add r48, r42, r12 }\n"
+ "move %0, r48\n"
+ "move %1, r42\n"
+ "move %2, r12\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2addsc_X0.c b/none/tests/tilegx/insn_test_v2addsc_X0.c
new file mode 100644
index 0000000..5caf009
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2addsc_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2addsc_X0.c
+//op=280
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x65cf6bab5dfbf927, 0x455f86368ee6a1bf };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r7, 9473\n"
+ "shl16insli r7, r7, -14156\n"
+ "shl16insli r7, r7, 12314\n"
+ "shl16insli r7, r7, -12172\n"
+ "moveli r22, 28628\n"
+ "shl16insli r22, r22, -15724\n"
+ "shl16insli r22, r22, 22937\n"
+ "shl16insli r22, r22, -21350\n"
+ "moveli r23, -4550\n"
+ "shl16insli r23, r23, 10548\n"
+ "shl16insli r23, r23, -3563\n"
+ "shl16insli r23, r23, -26830\n"
+ "{ v2addsc r7, r22, r23 ; fnop }\n"
+ "move %0, r7\n"
+ "move %1, r22\n"
+ "move %2, r23\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2addsc_X1.c b/none/tests/tilegx/insn_test_v2addsc_X1.c
new file mode 100644
index 0000000..3e08b25
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2addsc_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2addsc_X1.c
+//op=280
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x65cf6bab5dfbf927, 0x455f86368ee6a1bf };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r7, 9473\n"
+ "shl16insli r7, r7, -14156\n"
+ "shl16insli r7, r7, 12314\n"
+ "shl16insli r7, r7, -12172\n"
+ "moveli r22, 28628\n"
+ "shl16insli r22, r22, -15724\n"
+ "shl16insli r22, r22, 22937\n"
+ "shl16insli r22, r22, -21350\n"
+ "moveli r23, -4550\n"
+ "shl16insli r23, r23, 10548\n"
+ "shl16insli r23, r23, -3563\n"
+ "shl16insli r23, r23, -26830\n"
+ "{ fnop ; v2addsc r7, r22, r23 }\n"
+ "move %0, r7\n"
+ "move %1, r22\n"
+ "move %2, r23\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2adiffs_X0.c b/none/tests/tilegx/insn_test_v2adiffs_X0.c
new file mode 100644
index 0000000..0eefc9e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2adiffs_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2adiffs_X0.c
+//op=281
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6f21f4f815dfb72, 0x5b4570159a31813a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r10, -15907\n"
+ "shl16insli r10, r10, 8951\n"
+ "shl16insli r10, r10, -9037\n"
+ "shl16insli r10, r10, 10333\n"
+ "moveli r5, -798\n"
+ "shl16insli r5, r5, -2293\n"
+ "shl16insli r5, r5, -26610\n"
+ "shl16insli r5, r5, -17\n"
+ "moveli r39, -3845\n"
+ "shl16insli r39, r39, -15318\n"
+ "shl16insli r39, r39, 29335\n"
+ "shl16insli r39, r39, 30594\n"
+ "{ v2adiffs r10, r5, r39 ; fnop }\n"
+ "move %0, r10\n"
+ "move %1, r5\n"
+ "move %2, r39\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2avgs_X0.c b/none/tests/tilegx/insn_test_v2avgs_X0.c
new file mode 100644
index 0000000..11ca6e9
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2avgs_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2avgs_X0.c
+//op=282
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x71b23d899a1387f6, 0x818b8dda9648095a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r6, -17474\n"
+ "shl16insli r6, r6, 5541\n"
+ "shl16insli r6, r6, 25238\n"
+ "shl16insli r6, r6, 6803\n"
+ "moveli r50, -5690\n"
+ "shl16insli r50, r50, 12649\n"
+ "shl16insli r50, r50, 15657\n"
+ "shl16insli r50, r50, -29970\n"
+ "moveli r50, 29145\n"
+ "shl16insli r50, r50, 12637\n"
+ "shl16insli r50, r50, -13093\n"
+ "shl16insli r50, r50, 10273\n"
+ "{ v2avgs r6, r50, r50 ; fnop }\n"
+ "move %0, r6\n"
+ "move %1, r50\n"
+ "move %2, r50\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmpeq_X0.c b/none/tests/tilegx/insn_test_v2cmpeq_X0.c
new file mode 100644
index 0000000..53577af
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmpeq_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2cmpeq_X0.c
+//op=283
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x81ebfd4038066c1, 0x27d94b818c24b012 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r28, 18704\n"
+ "shl16insli r28, r28, -13143\n"
+ "shl16insli r28, r28, 20980\n"
+ "shl16insli r28, r28, -16967\n"
+ "moveli r38, 2058\n"
+ "shl16insli r38, r38, -13098\n"
+ "shl16insli r38, r38, 23303\n"
+ "shl16insli r38, r38, -31712\n"
+ "moveli r16, 6420\n"
+ "shl16insli r16, r16, 31924\n"
+ "shl16insli r16, r16, -30519\n"
+ "shl16insli r16, r16, 32754\n"
+ "{ v2cmpeq r28, r38, r16 ; fnop }\n"
+ "move %0, r28\n"
+ "move %1, r38\n"
+ "move %2, r16\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmpeq_X1.c b/none/tests/tilegx/insn_test_v2cmpeq_X1.c
new file mode 100644
index 0000000..f37f536
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmpeq_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2cmpeq_X1.c
+//op=283
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x81ebfd4038066c1, 0x27d94b818c24b012 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r28, 18704\n"
+ "shl16insli r28, r28, -13143\n"
+ "shl16insli r28, r28, 20980\n"
+ "shl16insli r28, r28, -16967\n"
+ "moveli r38, 2058\n"
+ "shl16insli r38, r38, -13098\n"
+ "shl16insli r38, r38, 23303\n"
+ "shl16insli r38, r38, -31712\n"
+ "moveli r16, 6420\n"
+ "shl16insli r16, r16, 31924\n"
+ "shl16insli r16, r16, -30519\n"
+ "shl16insli r16, r16, 32754\n"
+ "{ fnop ; v2cmpeq r28, r38, r16 }\n"
+ "move %0, r28\n"
+ "move %1, r38\n"
+ "move %2, r16\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmpeqi_X0.c b/none/tests/tilegx/insn_test_v2cmpeqi_X0.c
new file mode 100644
index 0000000..49733d8
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmpeqi_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v2cmpeqi_X0.c
+//op=284
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x8313ffac0a7611da, 0xa6a582b3dc8f6e83 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r26, -30297\n"
+ "shl16insli r26, r26, -30363\n"
+ "shl16insli r26, r26, -30605\n"
+ "shl16insli r26, r26, 3831\n"
+ "moveli r35, 7782\n"
+ "shl16insli r35, r35, 2739\n"
+ "shl16insli r35, r35, -10491\n"
+ "shl16insli r35, r35, -19368\n"
+ "{ v2cmpeqi r26, r35, 63 ; fnop }\n"
+ "move %0, r26\n"
+ "move %1, r35\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmpeqi_X1.c b/none/tests/tilegx/insn_test_v2cmpeqi_X1.c
new file mode 100644
index 0000000..2d8cfea
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmpeqi_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v2cmpeqi_X1.c
+//op=284
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x8313ffac0a7611da, 0xa6a582b3dc8f6e83 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r26, -30297\n"
+ "shl16insli r26, r26, -30363\n"
+ "shl16insli r26, r26, -30605\n"
+ "shl16insli r26, r26, 3831\n"
+ "moveli r35, 7782\n"
+ "shl16insli r35, r35, 2739\n"
+ "shl16insli r35, r35, -10491\n"
+ "shl16insli r35, r35, -19368\n"
+ "{ fnop ; v2cmpeqi r26, r35, 63 }\n"
+ "move %0, r26\n"
+ "move %1, r35\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmples_X0.c b/none/tests/tilegx/insn_test_v2cmples_X0.c
new file mode 100644
index 0000000..3eee3ae
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmples_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2cmples_X0.c
+//op=285
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6bc7185f1c32c400, 0x77be6930d1ff0375 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, 24574\n"
+ "shl16insli r22, r22, -7860\n"
+ "shl16insli r22, r22, 22844\n"
+ "shl16insli r22, r22, -25856\n"
+ "moveli r9, 30705\n"
+ "shl16insli r9, r9, -3754\n"
+ "shl16insli r9, r9, 28337\n"
+ "shl16insli r9, r9, -16712\n"
+ "moveli r50, -1269\n"
+ "shl16insli r50, r50, -3807\n"
+ "shl16insli r50, r50, -5572\n"
+ "shl16insli r50, r50, -28620\n"
+ "{ v2cmples r22, r9, r50 ; fnop }\n"
+ "move %0, r22\n"
+ "move %1, r9\n"
+ "move %2, r50\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmples_X1.c b/none/tests/tilegx/insn_test_v2cmples_X1.c
new file mode 100644
index 0000000..5ed4e02
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmples_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2cmples_X1.c
+//op=285
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6bc7185f1c32c400, 0x77be6930d1ff0375 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, 24574\n"
+ "shl16insli r22, r22, -7860\n"
+ "shl16insli r22, r22, 22844\n"
+ "shl16insli r22, r22, -25856\n"
+ "moveli r9, 30705\n"
+ "shl16insli r9, r9, -3754\n"
+ "shl16insli r9, r9, 28337\n"
+ "shl16insli r9, r9, -16712\n"
+ "moveli r50, -1269\n"
+ "shl16insli r50, r50, -3807\n"
+ "shl16insli r50, r50, -5572\n"
+ "shl16insli r50, r50, -28620\n"
+ "{ fnop ; v2cmples r22, r9, r50 }\n"
+ "move %0, r22\n"
+ "move %1, r9\n"
+ "move %2, r50\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmpleu_X0.c b/none/tests/tilegx/insn_test_v2cmpleu_X0.c
new file mode 100644
index 0000000..1c06e62
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmpleu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2cmpleu_X0.c
+//op=286
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x3ef8a65156ec00ac, 0x59fad680489ec628 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r50, 27539\n"
+ "shl16insli r50, r50, -29737\n"
+ "shl16insli r50, r50, 27831\n"
+ "shl16insli r50, r50, -25163\n"
+ "moveli r13, 694\n"
+ "shl16insli r13, r13, -3893\n"
+ "shl16insli r13, r13, 5047\n"
+ "shl16insli r13, r13, -7475\n"
+ "moveli r2, -31766\n"
+ "shl16insli r2, r2, 20217\n"
+ "shl16insli r2, r2, -13682\n"
+ "shl16insli r2, r2, -10053\n"
+ "{ v2cmpleu r50, r13, r2 ; fnop }\n"
+ "move %0, r50\n"
+ "move %1, r13\n"
+ "move %2, r2\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmpleu_X1.c b/none/tests/tilegx/insn_test_v2cmpleu_X1.c
new file mode 100644
index 0000000..fc201ad
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmpleu_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2cmpleu_X1.c
+//op=286
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x3ef8a65156ec00ac, 0x59fad680489ec628 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r50, 27539\n"
+ "shl16insli r50, r50, -29737\n"
+ "shl16insli r50, r50, 27831\n"
+ "shl16insli r50, r50, -25163\n"
+ "moveli r13, 694\n"
+ "shl16insli r13, r13, -3893\n"
+ "shl16insli r13, r13, 5047\n"
+ "shl16insli r13, r13, -7475\n"
+ "moveli r2, -31766\n"
+ "shl16insli r2, r2, 20217\n"
+ "shl16insli r2, r2, -13682\n"
+ "shl16insli r2, r2, -10053\n"
+ "{ fnop ; v2cmpleu r50, r13, r2 }\n"
+ "move %0, r50\n"
+ "move %1, r13\n"
+ "move %2, r2\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmplts_X0.c b/none/tests/tilegx/insn_test_v2cmplts_X0.c
new file mode 100644
index 0000000..7280ebe
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmplts_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2cmplts_X0.c
+//op=287
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xee16007d198e11f0, 0x1aa7041318ab41dd };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r36, 31237\n"
+ "shl16insli r36, r36, -13233\n"
+ "shl16insli r36, r36, -23176\n"
+ "shl16insli r36, r36, 582\n"
+ "moveli r45, 10053\n"
+ "shl16insli r45, r45, 8734\n"
+ "shl16insli r45, r45, 386\n"
+ "shl16insli r45, r45, -2790\n"
+ "moveli r20, 27000\n"
+ "shl16insli r20, r20, -5959\n"
+ "shl16insli r20, r20, 7411\n"
+ "shl16insli r20, r20, 17645\n"
+ "{ v2cmplts r36, r45, r20 ; fnop }\n"
+ "move %0, r36\n"
+ "move %1, r45\n"
+ "move %2, r20\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmplts_X1.c b/none/tests/tilegx/insn_test_v2cmplts_X1.c
new file mode 100644
index 0000000..18a0cbf
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmplts_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2cmplts_X1.c
+//op=287
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xee16007d198e11f0, 0x1aa7041318ab41dd };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r36, 31237\n"
+ "shl16insli r36, r36, -13233\n"
+ "shl16insli r36, r36, -23176\n"
+ "shl16insli r36, r36, 582\n"
+ "moveli r45, 10053\n"
+ "shl16insli r45, r45, 8734\n"
+ "shl16insli r45, r45, 386\n"
+ "shl16insli r45, r45, -2790\n"
+ "moveli r20, 27000\n"
+ "shl16insli r20, r20, -5959\n"
+ "shl16insli r20, r20, 7411\n"
+ "shl16insli r20, r20, 17645\n"
+ "{ fnop ; v2cmplts r36, r45, r20 }\n"
+ "move %0, r36\n"
+ "move %1, r45\n"
+ "move %2, r20\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmpltsi_X0.c b/none/tests/tilegx/insn_test_v2cmpltsi_X0.c
new file mode 100644
index 0000000..7e9e929
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmpltsi_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v2cmpltsi_X0.c
+//op=288
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x659ad846d801a198, 0xfa50dcf0b044d59a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r1, 7596\n"
+ "shl16insli r1, r1, -10648\n"
+ "shl16insli r1, r1, 15573\n"
+ "shl16insli r1, r1, -25790\n"
+ "moveli r40, -27339\n"
+ "shl16insli r40, r40, -13420\n"
+ "shl16insli r40, r40, 19273\n"
+ "shl16insli r40, r40, -27678\n"
+ "{ v2cmpltsi r1, r40, 43 ; fnop }\n"
+ "move %0, r1\n"
+ "move %1, r40\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmpltsi_X1.c b/none/tests/tilegx/insn_test_v2cmpltsi_X1.c
new file mode 100644
index 0000000..e13063e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmpltsi_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v2cmpltsi_X1.c
+//op=288
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x659ad846d801a198, 0xfa50dcf0b044d59a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r1, 7596\n"
+ "shl16insli r1, r1, -10648\n"
+ "shl16insli r1, r1, 15573\n"
+ "shl16insli r1, r1, -25790\n"
+ "moveli r40, -27339\n"
+ "shl16insli r40, r40, -13420\n"
+ "shl16insli r40, r40, 19273\n"
+ "shl16insli r40, r40, -27678\n"
+ "{ fnop ; v2cmpltsi r1, r40, 43 }\n"
+ "move %0, r1\n"
+ "move %1, r40\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmpltu_X0.c b/none/tests/tilegx/insn_test_v2cmpltu_X0.c
new file mode 100644
index 0000000..40887f3
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmpltu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2cmpltu_X0.c
+//op=289
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5bebf9affeed58c5, 0x5f48984c90970726 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r17, -4172\n"
+ "shl16insli r17, r17, 3357\n"
+ "shl16insli r17, r17, 24413\n"
+ "shl16insli r17, r17, -20526\n"
+ "moveli r27, 301\n"
+ "shl16insli r27, r27, -10739\n"
+ "shl16insli r27, r27, -13582\n"
+ "shl16insli r27, r27, 11244\n"
+ "moveli r10, 9533\n"
+ "shl16insli r10, r10, -1340\n"
+ "shl16insli r10, r10, -4688\n"
+ "shl16insli r10, r10, 849\n"
+ "{ v2cmpltu r17, r27, r10 ; fnop }\n"
+ "move %0, r17\n"
+ "move %1, r27\n"
+ "move %2, r10\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmpltu_X1.c b/none/tests/tilegx/insn_test_v2cmpltu_X1.c
new file mode 100644
index 0000000..d076173
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmpltu_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2cmpltu_X1.c
+//op=289
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x5bebf9affeed58c5, 0x5f48984c90970726 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r17, -4172\n"
+ "shl16insli r17, r17, 3357\n"
+ "shl16insli r17, r17, 24413\n"
+ "shl16insli r17, r17, -20526\n"
+ "moveli r27, 301\n"
+ "shl16insli r27, r27, -10739\n"
+ "shl16insli r27, r27, -13582\n"
+ "shl16insli r27, r27, 11244\n"
+ "moveli r10, 9533\n"
+ "shl16insli r10, r10, -1340\n"
+ "shl16insli r10, r10, -4688\n"
+ "shl16insli r10, r10, 849\n"
+ "{ fnop ; v2cmpltu r17, r27, r10 }\n"
+ "move %0, r17\n"
+ "move %1, r27\n"
+ "move %2, r10\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmpltui_X0.c b/none/tests/tilegx/insn_test_v2cmpltui_X0.c
new file mode 100644
index 0000000..4c30390
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmpltui_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v2cmpltui_X0.c
+//op=290
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4ebafb6d47a2a55b, 0xd6233f383d6fcac4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -25706\n"
+ "shl16insli r38, r38, -25275\n"
+ "shl16insli r38, r38, 17720\n"
+ "shl16insli r38, r38, 16967\n"
+ "moveli r24, -18642\n"
+ "shl16insli r24, r24, -25898\n"
+ "shl16insli r24, r24, -7881\n"
+ "shl16insli r24, r24, 8833\n"
+ "{ v2cmpltui r38, r24, -54 ; fnop }\n"
+ "move %0, r38\n"
+ "move %1, r24\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmpltui_X1.c b/none/tests/tilegx/insn_test_v2cmpltui_X1.c
new file mode 100644
index 0000000..2707b53
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmpltui_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v2cmpltui_X1.c
+//op=290
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4ebafb6d47a2a55b, 0xd6233f383d6fcac4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r38, -25706\n"
+ "shl16insli r38, r38, -25275\n"
+ "shl16insli r38, r38, 17720\n"
+ "shl16insli r38, r38, 16967\n"
+ "moveli r24, -18642\n"
+ "shl16insli r24, r24, -25898\n"
+ "shl16insli r24, r24, -7881\n"
+ "shl16insli r24, r24, 8833\n"
+ "{ fnop ; v2cmpltui r38, r24, -54 }\n"
+ "move %0, r38\n"
+ "move %1, r24\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmpne_X0.c b/none/tests/tilegx/insn_test_v2cmpne_X0.c
new file mode 100644
index 0000000..5c049d0
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmpne_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2cmpne_X0.c
+//op=291
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x73bf93bc04d834da, 0x76a2823539bdf579 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, -12324\n"
+ "shl16insli r22, r22, -28627\n"
+ "shl16insli r22, r22, 16604\n"
+ "shl16insli r22, r22, -17536\n"
+ "moveli r4, -7766\n"
+ "shl16insli r4, r4, 5697\n"
+ "shl16insli r4, r4, 28357\n"
+ "shl16insli r4, r4, -6412\n"
+ "moveli r17, 864\n"
+ "shl16insli r17, r17, 29519\n"
+ "shl16insli r17, r17, 2450\n"
+ "shl16insli r17, r17, -17857\n"
+ "{ v2cmpne r22, r4, r17 ; fnop }\n"
+ "move %0, r22\n"
+ "move %1, r4\n"
+ "move %2, r17\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2cmpne_X1.c b/none/tests/tilegx/insn_test_v2cmpne_X1.c
new file mode 100644
index 0000000..35031b2
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2cmpne_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2cmpne_X1.c
+//op=291
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x73bf93bc04d834da, 0x76a2823539bdf579 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, -12324\n"
+ "shl16insli r22, r22, -28627\n"
+ "shl16insli r22, r22, 16604\n"
+ "shl16insli r22, r22, -17536\n"
+ "moveli r4, -7766\n"
+ "shl16insli r4, r4, 5697\n"
+ "shl16insli r4, r4, 28357\n"
+ "shl16insli r4, r4, -6412\n"
+ "moveli r17, 864\n"
+ "shl16insli r17, r17, 29519\n"
+ "shl16insli r17, r17, 2450\n"
+ "shl16insli r17, r17, -17857\n"
+ "{ fnop ; v2cmpne r22, r4, r17 }\n"
+ "move %0, r22\n"
+ "move %1, r4\n"
+ "move %2, r17\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2dotp_X0.c b/none/tests/tilegx/insn_test_v2dotp_X0.c
new file mode 100644
index 0000000..f81bb0a
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2dotp_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2dotp_X0.c
+//op=292
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6be343892f498708, 0x52c49809e5465b06 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r9, 25552\n"
+ "shl16insli r9, r9, -32365\n"
+ "shl16insli r9, r9, 7253\n"
+ "shl16insli r9, r9, 12258\n"
+ "moveli r16, 31670\n"
+ "shl16insli r16, r16, 10120\n"
+ "shl16insli r16, r16, -14289\n"
+ "shl16insli r16, r16, -12244\n"
+ "moveli r25, 2217\n"
+ "shl16insli r25, r25, 23167\n"
+ "shl16insli r25, r25, 4870\n"
+ "shl16insli r25, r25, 31812\n"
+ "{ v2dotp r9, r16, r25 ; fnop }\n"
+ "move %0, r9\n"
+ "move %1, r16\n"
+ "move %2, r25\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2dotpa_X0.c b/none/tests/tilegx/insn_test_v2dotpa_X0.c
new file mode 100644
index 0000000..be29012
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2dotpa_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2dotpa_X0.c
+//op=293
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf3a626370b91d897, 0xecbff88d5bcc8c90 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r17, 6194\n"
+ "shl16insli r17, r17, 2413\n"
+ "shl16insli r17, r17, 21362\n"
+ "shl16insli r17, r17, 21211\n"
+ "moveli r8, 14829\n"
+ "shl16insli r8, r8, 23848\n"
+ "shl16insli r8, r8, 17951\n"
+ "shl16insli r8, r8, -953\n"
+ "moveli r25, 21203\n"
+ "shl16insli r25, r25, -13101\n"
+ "shl16insli r25, r25, 14734\n"
+ "shl16insli r25, r25, -27100\n"
+ "{ v2dotpa r17, r8, r25 ; fnop }\n"
+ "move %0, r17\n"
+ "move %1, r8\n"
+ "move %2, r25\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2int_h_X0.c b/none/tests/tilegx/insn_test_v2int_h_X0.c
new file mode 100644
index 0000000..5c11542
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2int_h_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2int_h_X0.c
+//op=294
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x97e13a21591a3024, 0x5d9ea0967d2b4507 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r43, -19915\n"
+ "shl16insli r43, r43, -2852\n"
+ "shl16insli r43, r43, 32613\n"
+ "shl16insli r43, r43, 14940\n"
+ "moveli r42, -8260\n"
+ "shl16insli r42, r42, -23578\n"
+ "shl16insli r42, r42, -18362\n"
+ "shl16insli r42, r42, 19495\n"
+ "moveli r21, -29446\n"
+ "shl16insli r21, r21, -10554\n"
+ "shl16insli r21, r21, 9903\n"
+ "shl16insli r21, r21, -20470\n"
+ "{ v2int_h r43, r42, r21 ; fnop }\n"
+ "move %0, r43\n"
+ "move %1, r42\n"
+ "move %2, r21\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2int_h_X1.c b/none/tests/tilegx/insn_test_v2int_h_X1.c
new file mode 100644
index 0000000..f43e7bd
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2int_h_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2int_h_X1.c
+//op=294
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x97e13a21591a3024, 0x5d9ea0967d2b4507 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r43, -19915\n"
+ "shl16insli r43, r43, -2852\n"
+ "shl16insli r43, r43, 32613\n"
+ "shl16insli r43, r43, 14940\n"
+ "moveli r42, -8260\n"
+ "shl16insli r42, r42, -23578\n"
+ "shl16insli r42, r42, -18362\n"
+ "shl16insli r42, r42, 19495\n"
+ "moveli r21, -29446\n"
+ "shl16insli r21, r21, -10554\n"
+ "shl16insli r21, r21, 9903\n"
+ "shl16insli r21, r21, -20470\n"
+ "{ fnop ; v2int_h r43, r42, r21 }\n"
+ "move %0, r43\n"
+ "move %1, r42\n"
+ "move %2, r21\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2int_l_X0.c b/none/tests/tilegx/insn_test_v2int_l_X0.c
new file mode 100644
index 0000000..a6aa8a3
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2int_l_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2int_l_X0.c
+//op=295
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xcfb4af8744c008a6, 0x7da224c9da343236 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r39, -7263\n"
+ "shl16insli r39, r39, -2165\n"
+ "shl16insli r39, r39, 15401\n"
+ "shl16insli r39, r39, 3495\n"
+ "moveli r50, -16001\n"
+ "shl16insli r50, r50, 28334\n"
+ "shl16insli r50, r50, 10964\n"
+ "shl16insli r50, r50, -18458\n"
+ "moveli r49, -15860\n"
+ "shl16insli r49, r49, -32482\n"
+ "shl16insli r49, r49, 31946\n"
+ "shl16insli r49, r49, -29777\n"
+ "{ v2int_l r39, r50, r49 ; fnop }\n"
+ "move %0, r39\n"
+ "move %1, r50\n"
+ "move %2, r49\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2int_l_X1.c b/none/tests/tilegx/insn_test_v2int_l_X1.c
new file mode 100644
index 0000000..5a1bddb
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2int_l_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2int_l_X1.c
+//op=295
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xcfb4af8744c008a6, 0x7da224c9da343236 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r39, -7263\n"
+ "shl16insli r39, r39, -2165\n"
+ "shl16insli r39, r39, 15401\n"
+ "shl16insli r39, r39, 3495\n"
+ "moveli r50, -16001\n"
+ "shl16insli r50, r50, 28334\n"
+ "shl16insli r50, r50, 10964\n"
+ "shl16insli r50, r50, -18458\n"
+ "moveli r49, -15860\n"
+ "shl16insli r49, r49, -32482\n"
+ "shl16insli r49, r49, 31946\n"
+ "shl16insli r49, r49, -29777\n"
+ "{ fnop ; v2int_l r39, r50, r49 }\n"
+ "move %0, r39\n"
+ "move %1, r50\n"
+ "move %2, r49\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2maxs_X0.c b/none/tests/tilegx/insn_test_v2maxs_X0.c
new file mode 100644
index 0000000..a466202
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2maxs_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2maxs_X0.c
+//op=296
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd673caed17b8f6b3, 0xd67c5353b4f83951 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r17, -9565\n"
+ "shl16insli r17, r17, -2221\n"
+ "shl16insli r17, r17, 28285\n"
+ "shl16insli r17, r17, -15121\n"
+ "moveli r49, -7514\n"
+ "shl16insli r49, r49, -32499\n"
+ "shl16insli r49, r49, -9013\n"
+ "shl16insli r49, r49, -11291\n"
+ "moveli r38, -30570\n"
+ "shl16insli r38, r38, 23912\n"
+ "shl16insli r38, r38, -22856\n"
+ "shl16insli r38, r38, 8963\n"
+ "{ v2maxs r17, r49, r38 ; fnop }\n"
+ "move %0, r17\n"
+ "move %1, r49\n"
+ "move %2, r38\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2maxs_X1.c b/none/tests/tilegx/insn_test_v2maxs_X1.c
new file mode 100644
index 0000000..7f2ec99
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2maxs_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2maxs_X1.c
+//op=296
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd673caed17b8f6b3, 0xd67c5353b4f83951 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r17, -9565\n"
+ "shl16insli r17, r17, -2221\n"
+ "shl16insli r17, r17, 28285\n"
+ "shl16insli r17, r17, -15121\n"
+ "moveli r49, -7514\n"
+ "shl16insli r49, r49, -32499\n"
+ "shl16insli r49, r49, -9013\n"
+ "shl16insli r49, r49, -11291\n"
+ "moveli r38, -30570\n"
+ "shl16insli r38, r38, 23912\n"
+ "shl16insli r38, r38, -22856\n"
+ "shl16insli r38, r38, 8963\n"
+ "{ fnop ; v2maxs r17, r49, r38 }\n"
+ "move %0, r17\n"
+ "move %1, r49\n"
+ "move %2, r38\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2mins_X0.c b/none/tests/tilegx/insn_test_v2mins_X0.c
new file mode 100644
index 0000000..608b217
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2mins_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2mins_X0.c
+//op=298
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa3dc241c7d6d8a40, 0x74d04934d1d15274 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, -6438\n"
+ "shl16insli r11, r11, 23407\n"
+ "shl16insli r11, r11, -8776\n"
+ "shl16insli r11, r11, -3925\n"
+ "moveli r49, -16630\n"
+ "shl16insli r49, r49, 3480\n"
+ "shl16insli r49, r49, -23548\n"
+ "shl16insli r49, r49, -31140\n"
+ "moveli r31, 15345\n"
+ "shl16insli r31, r31, 9943\n"
+ "shl16insli r31, r31, 20819\n"
+ "shl16insli r31, r31, 16223\n"
+ "{ v2mins r11, r49, r31 ; fnop }\n"
+ "move %0, r11\n"
+ "move %1, r49\n"
+ "move %2, r31\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2mins_X1.c b/none/tests/tilegx/insn_test_v2mins_X1.c
new file mode 100644
index 0000000..57c7f7b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2mins_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2mins_X1.c
+//op=298
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa3dc241c7d6d8a40, 0x74d04934d1d15274 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, -6438\n"
+ "shl16insli r11, r11, 23407\n"
+ "shl16insli r11, r11, -8776\n"
+ "shl16insli r11, r11, -3925\n"
+ "moveli r49, -16630\n"
+ "shl16insli r49, r49, 3480\n"
+ "shl16insli r49, r49, -23548\n"
+ "shl16insli r49, r49, -31140\n"
+ "moveli r31, 15345\n"
+ "shl16insli r31, r31, 9943\n"
+ "shl16insli r31, r31, 20819\n"
+ "shl16insli r31, r31, 16223\n"
+ "{ fnop ; v2mins r11, r49, r31 }\n"
+ "move %0, r11\n"
+ "move %1, r49\n"
+ "move %2, r31\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2mnz_X0.c b/none/tests/tilegx/insn_test_v2mnz_X0.c
new file mode 100644
index 0000000..7df50e1
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2mnz_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2mnz_X0.c
+//op=300
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2998adb0884ca11c, 0x95953511f9ee4512 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r8, -25986\n"
+ "shl16insli r8, r8, -11739\n"
+ "shl16insli r8, r8, 13313\n"
+ "shl16insli r8, r8, -12374\n"
+ "moveli r5, 8557\n"
+ "shl16insli r5, r5, 20208\n"
+ "shl16insli r5, r5, -26295\n"
+ "shl16insli r5, r5, -27540\n"
+ "moveli r49, 24429\n"
+ "shl16insli r49, r49, 18925\n"
+ "shl16insli r49, r49, 30717\n"
+ "shl16insli r49, r49, -32703\n"
+ "{ v2mnz r8, r5, r49 ; fnop }\n"
+ "move %0, r8\n"
+ "move %1, r5\n"
+ "move %2, r49\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2mnz_X1.c b/none/tests/tilegx/insn_test_v2mnz_X1.c
new file mode 100644
index 0000000..81e8b76
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2mnz_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2mnz_X1.c
+//op=300
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2998adb0884ca11c, 0x95953511f9ee4512 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r8, -25986\n"
+ "shl16insli r8, r8, -11739\n"
+ "shl16insli r8, r8, 13313\n"
+ "shl16insli r8, r8, -12374\n"
+ "moveli r5, 8557\n"
+ "shl16insli r5, r5, 20208\n"
+ "shl16insli r5, r5, -26295\n"
+ "shl16insli r5, r5, -27540\n"
+ "moveli r49, 24429\n"
+ "shl16insli r49, r49, 18925\n"
+ "shl16insli r49, r49, 30717\n"
+ "shl16insli r49, r49, -32703\n"
+ "{ fnop ; v2mnz r8, r5, r49 }\n"
+ "move %0, r8\n"
+ "move %1, r5\n"
+ "move %2, r49\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2mulfsc_X0.c b/none/tests/tilegx/insn_test_v2mulfsc_X0.c
new file mode 100644
index 0000000..236df3b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2mulfsc_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2mulfsc_X0.c
+//op=301
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xfc4c1139fffb1c60, 0xb25a859df5ae736 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r42, -31119\n"
+ "shl16insli r42, r42, -1080\n"
+ "shl16insli r42, r42, 6437\n"
+ "shl16insli r42, r42, 1017\n"
+ "moveli r19, 18489\n"
+ "shl16insli r19, r19, -6115\n"
+ "shl16insli r19, r19, -11917\n"
+ "shl16insli r19, r19, -887\n"
+ "moveli r6, -7581\n"
+ "shl16insli r6, r6, -24479\n"
+ "shl16insli r6, r6, 27035\n"
+ "shl16insli r6, r6, -19583\n"
+ "{ v2mulfsc r42, r19, r6 ; fnop }\n"
+ "move %0, r42\n"
+ "move %1, r19\n"
+ "move %2, r6\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2muls_X0.c b/none/tests/tilegx/insn_test_v2muls_X0.c
new file mode 100644
index 0000000..f47e89e
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2muls_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2muls_X0.c
+//op=302
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x16cf0b15dab31447, 0x4f71ee192e8cc1e4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r35, 14213\n"
+ "shl16insli r35, r35, -12906\n"
+ "shl16insli r35, r35, -10898\n"
+ "shl16insli r35, r35, 21664\n"
+ "moveli r33, -3303\n"
+ "shl16insli r33, r33, -18198\n"
+ "shl16insli r33, r33, 17267\n"
+ "shl16insli r33, r33, -25748\n"
+ "moveli r48, -32118\n"
+ "shl16insli r48, r48, -21438\n"
+ "shl16insli r48, r48, -21975\n"
+ "shl16insli r48, r48, -17458\n"
+ "{ v2muls r35, r33, r48 ; fnop }\n"
+ "move %0, r35\n"
+ "move %1, r33\n"
+ "move %2, r48\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2mults_X0.c b/none/tests/tilegx/insn_test_v2mults_X0.c
new file mode 100644
index 0000000..6815340
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2mults_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2mults_X0.c
+//op=303
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x10a358c86acccf50, 0xdf11630124acb01a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r9, 4497\n"
+ "shl16insli r9, r9, 8011\n"
+ "shl16insli r9, r9, -29488\n"
+ "shl16insli r9, r9, -23563\n"
+ "moveli r39, -24360\n"
+ "shl16insli r39, r39, 26052\n"
+ "shl16insli r39, r39, -30688\n"
+ "shl16insli r39, r39, -6964\n"
+ "moveli r46, 14490\n"
+ "shl16insli r46, r46, 13586\n"
+ "shl16insli r46, r46, -31514\n"
+ "shl16insli r46, r46, -17044\n"
+ "{ v2mults r9, r39, r46 ; fnop }\n"
+ "move %0, r9\n"
+ "move %1, r39\n"
+ "move %2, r46\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2mz_X0.c b/none/tests/tilegx/insn_test_v2mz_X0.c
new file mode 100644
index 0000000..c7db681
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2mz_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2mz_X0.c
+//op=304
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xdf8a8efd3fbdf7df, 0x9d9b78ac30042683 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r1, -1899\n"
+ "shl16insli r1, r1, -8825\n"
+ "shl16insli r1, r1, -7773\n"
+ "shl16insli r1, r1, -2647\n"
+ "moveli r26, -32534\n"
+ "shl16insli r26, r26, -13813\n"
+ "shl16insli r26, r26, -14272\n"
+ "shl16insli r26, r26, -25134\n"
+ "moveli r32, -5907\n"
+ "shl16insli r32, r32, 24588\n"
+ "shl16insli r32, r32, -15094\n"
+ "shl16insli r32, r32, 11658\n"
+ "{ v2mz r1, r26, r32 ; fnop }\n"
+ "move %0, r1\n"
+ "move %1, r26\n"
+ "move %2, r32\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2mz_X1.c b/none/tests/tilegx/insn_test_v2mz_X1.c
new file mode 100644
index 0000000..0953ec8
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2mz_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2mz_X1.c
+//op=304
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xdf8a8efd3fbdf7df, 0x9d9b78ac30042683 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r1, -1899\n"
+ "shl16insli r1, r1, -8825\n"
+ "shl16insli r1, r1, -7773\n"
+ "shl16insli r1, r1, -2647\n"
+ "moveli r26, -32534\n"
+ "shl16insli r26, r26, -13813\n"
+ "shl16insli r26, r26, -14272\n"
+ "shl16insli r26, r26, -25134\n"
+ "moveli r32, -5907\n"
+ "shl16insli r32, r32, 24588\n"
+ "shl16insli r32, r32, -15094\n"
+ "shl16insli r32, r32, 11658\n"
+ "{ fnop ; v2mz r1, r26, r32 }\n"
+ "move %0, r1\n"
+ "move %1, r26\n"
+ "move %2, r32\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2packh_X0.c b/none/tests/tilegx/insn_test_v2packh_X0.c
new file mode 100644
index 0000000..9991c1d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2packh_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2packh_X0.c
+//op=305
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbe377398fe6841d2, 0xdc57bd79a15b537d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r31, 4830\n"
+ "shl16insli r31, r31, 30571\n"
+ "shl16insli r31, r31, -14162\n"
+ "shl16insli r31, r31, 16427\n"
+ "moveli r48, 26721\n"
+ "shl16insli r48, r48, 13661\n"
+ "shl16insli r48, r48, 14804\n"
+ "shl16insli r48, r48, 23341\n"
+ "moveli r24, -18421\n"
+ "shl16insli r24, r24, -1115\n"
+ "shl16insli r24, r24, 24581\n"
+ "shl16insli r24, r24, 17697\n"
+ "{ v2packh r31, r48, r24 ; fnop }\n"
+ "move %0, r31\n"
+ "move %1, r48\n"
+ "move %2, r24\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2packh_X1.c b/none/tests/tilegx/insn_test_v2packh_X1.c
new file mode 100644
index 0000000..fa93ab2
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2packh_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2packh_X1.c
+//op=305
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xbe377398fe6841d2, 0xdc57bd79a15b537d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r31, 4830\n"
+ "shl16insli r31, r31, 30571\n"
+ "shl16insli r31, r31, -14162\n"
+ "shl16insli r31, r31, 16427\n"
+ "moveli r48, 26721\n"
+ "shl16insli r48, r48, 13661\n"
+ "shl16insli r48, r48, 14804\n"
+ "shl16insli r48, r48, 23341\n"
+ "moveli r24, -18421\n"
+ "shl16insli r24, r24, -1115\n"
+ "shl16insli r24, r24, 24581\n"
+ "shl16insli r24, r24, 17697\n"
+ "{ fnop ; v2packh r31, r48, r24 }\n"
+ "move %0, r31\n"
+ "move %1, r48\n"
+ "move %2, r24\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2packl_X0.c b/none/tests/tilegx/insn_test_v2packl_X0.c
new file mode 100644
index 0000000..d699781
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2packl_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2packl_X0.c
+//op=306
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6110cf64d9a1b913, 0xc8c9da0e90770658 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r45, 31329\n"
+ "shl16insli r45, r45, 2611\n"
+ "shl16insli r45, r45, -21984\n"
+ "shl16insli r45, r45, -27173\n"
+ "moveli r13, 29208\n"
+ "shl16insli r13, r13, -3828\n"
+ "shl16insli r13, r13, 13042\n"
+ "shl16insli r13, r13, 9981\n"
+ "moveli r40, 2094\n"
+ "shl16insli r40, r40, 8442\n"
+ "shl16insli r40, r40, -10144\n"
+ "shl16insli r40, r40, -21625\n"
+ "{ v2packl r45, r13, r40 ; fnop }\n"
+ "move %0, r45\n"
+ "move %1, r13\n"
+ "move %2, r40\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2packl_X1.c b/none/tests/tilegx/insn_test_v2packl_X1.c
new file mode 100644
index 0000000..b54834c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2packl_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2packl_X1.c
+//op=306
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x6110cf64d9a1b913, 0xc8c9da0e90770658 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r45, 31329\n"
+ "shl16insli r45, r45, 2611\n"
+ "shl16insli r45, r45, -21984\n"
+ "shl16insli r45, r45, -27173\n"
+ "moveli r13, 29208\n"
+ "shl16insli r13, r13, -3828\n"
+ "shl16insli r13, r13, 13042\n"
+ "shl16insli r13, r13, 9981\n"
+ "moveli r40, 2094\n"
+ "shl16insli r40, r40, 8442\n"
+ "shl16insli r40, r40, -10144\n"
+ "shl16insli r40, r40, -21625\n"
+ "{ fnop ; v2packl r45, r13, r40 }\n"
+ "move %0, r45\n"
+ "move %1, r13\n"
+ "move %2, r40\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2packuc_X0.c b/none/tests/tilegx/insn_test_v2packuc_X0.c
new file mode 100644
index 0000000..26df79f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2packuc_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2packuc_X0.c
+//op=307
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe14980afe3a8dcf2, 0x14a9d2cae102f39d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r48, -14873\n"
+ "shl16insli r48, r48, 20437\n"
+ "shl16insli r48, r48, 1647\n"
+ "shl16insli r48, r48, -19288\n"
+ "moveli r2, 30869\n"
+ "shl16insli r2, r2, -5643\n"
+ "shl16insli r2, r2, 25290\n"
+ "shl16insli r2, r2, -10746\n"
+ "moveli r10, -14292\n"
+ "shl16insli r10, r10, -10131\n"
+ "shl16insli r10, r10, -22412\n"
+ "shl16insli r10, r10, -22005\n"
+ "{ v2packuc r48, r2, r10 ; fnop }\n"
+ "move %0, r48\n"
+ "move %1, r2\n"
+ "move %2, r10\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2packuc_X1.c b/none/tests/tilegx/insn_test_v2packuc_X1.c
new file mode 100644
index 0000000..7c23086
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2packuc_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2packuc_X1.c
+//op=307
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe14980afe3a8dcf2, 0x14a9d2cae102f39d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r48, -14873\n"
+ "shl16insli r48, r48, 20437\n"
+ "shl16insli r48, r48, 1647\n"
+ "shl16insli r48, r48, -19288\n"
+ "moveli r2, 30869\n"
+ "shl16insli r2, r2, -5643\n"
+ "shl16insli r2, r2, 25290\n"
+ "shl16insli r2, r2, -10746\n"
+ "moveli r10, -14292\n"
+ "shl16insli r10, r10, -10131\n"
+ "shl16insli r10, r10, -22412\n"
+ "shl16insli r10, r10, -22005\n"
+ "{ fnop ; v2packuc r48, r2, r10 }\n"
+ "move %0, r48\n"
+ "move %1, r2\n"
+ "move %2, r10\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2sadas_X0.c b/none/tests/tilegx/insn_test_v2sadas_X0.c
new file mode 100644
index 0000000..1bab24d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2sadas_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2sadas_X0.c
+//op=308
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x62e80c5c43ae1476, 0x75d452e3a144efb8 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r23, 241\n"
+ "shl16insli r23, r23, -14815\n"
+ "shl16insli r23, r23, -21901\n"
+ "shl16insli r23, r23, -3061\n"
+ "moveli r7, -22129\n"
+ "shl16insli r7, r7, -14930\n"
+ "shl16insli r7, r7, -14368\n"
+ "shl16insli r7, r7, -8560\n"
+ "moveli r29, -18028\n"
+ "shl16insli r29, r29, -11276\n"
+ "shl16insli r29, r29, 30167\n"
+ "shl16insli r29, r29, -30797\n"
+ "{ v2sadas r23, r7, r29 ; fnop }\n"
+ "move %0, r23\n"
+ "move %1, r7\n"
+ "move %2, r29\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2sadau_X0.c b/none/tests/tilegx/insn_test_v2sadau_X0.c
new file mode 100644
index 0000000..792c5ef
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2sadau_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2sadau_X0.c
+//op=309
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa3379eed107d409b, 0xb774c986061d211c };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r47, -14930\n"
+ "shl16insli r47, r47, -27555\n"
+ "shl16insli r47, r47, -15233\n"
+ "shl16insli r47, r47, -7776\n"
+ "moveli r46, 28855\n"
+ "shl16insli r46, r46, 12220\n"
+ "shl16insli r46, r46, -21108\n"
+ "shl16insli r46, r46, 22056\n"
+ "moveli r28, -20567\n"
+ "shl16insli r28, r28, -30793\n"
+ "shl16insli r28, r28, -6577\n"
+ "shl16insli r28, r28, -29356\n"
+ "{ v2sadau r47, r46, r28 ; fnop }\n"
+ "move %0, r47\n"
+ "move %1, r46\n"
+ "move %2, r28\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2sads_X0.c b/none/tests/tilegx/insn_test_v2sads_X0.c
new file mode 100644
index 0000000..5a4b7c4
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2sads_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2sads_X0.c
+//op=310
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb4cc28ab90e8a37, 0xc707c0e7f8704eba };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r22, 14299\n"
+ "shl16insli r22, r22, -16601\n"
+ "shl16insli r22, r22, -30080\n"
+ "shl16insli r22, r22, 10179\n"
+ "moveli r10, -32760\n"
+ "shl16insli r10, r10, 21279\n"
+ "shl16insli r10, r10, 9681\n"
+ "shl16insli r10, r10, 15414\n"
+ "moveli r21, 29123\n"
+ "shl16insli r21, r21, -20065\n"
+ "shl16insli r21, r21, 10672\n"
+ "shl16insli r21, r21, -17765\n"
+ "{ v2sads r22, r10, r21 ; fnop }\n"
+ "move %0, r22\n"
+ "move %1, r10\n"
+ "move %2, r21\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2sadu_X0.c b/none/tests/tilegx/insn_test_v2sadu_X0.c
new file mode 100644
index 0000000..acc1206
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2sadu_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2sadu_X0.c
+//op=311
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x16b1b65c0b6644ef, 0x11cdf52de566595 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r9, 31657\n"
+ "shl16insli r9, r9, -25836\n"
+ "shl16insli r9, r9, 8322\n"
+ "shl16insli r9, r9, -9300\n"
+ "moveli r34, -25603\n"
+ "shl16insli r34, r34, -29751\n"
+ "shl16insli r34, r34, 11341\n"
+ "shl16insli r34, r34, 7895\n"
+ "moveli r1, 15964\n"
+ "shl16insli r1, r1, 23061\n"
+ "shl16insli r1, r1, -7003\n"
+ "shl16insli r1, r1, 27153\n"
+ "{ v2sadu r9, r34, r1 ; fnop }\n"
+ "move %0, r9\n"
+ "move %1, r34\n"
+ "move %2, r1\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2shl_X0.c b/none/tests/tilegx/insn_test_v2shl_X0.c
new file mode 100644
index 0000000..bac9889
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2shl_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2shl_X0.c
+//op=312
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x11c672ab78dd743b, 0x31d131ae6b7da416 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, 29514\n"
+ "shl16insli r34, r34, 14828\n"
+ "shl16insli r34, r34, 1013\n"
+ "shl16insli r34, r34, 14302\n"
+ "moveli r19, -22322\n"
+ "shl16insli r19, r19, -9600\n"
+ "shl16insli r19, r19, 31146\n"
+ "shl16insli r19, r19, -10762\n"
+ "moveli r19, 1482\n"
+ "shl16insli r19, r19, 23578\n"
+ "shl16insli r19, r19, 5382\n"
+ "shl16insli r19, r19, 26331\n"
+ "{ v2shl r34, r19, r19 ; fnop }\n"
+ "move %0, r34\n"
+ "move %1, r19\n"
+ "move %2, r19\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2shl_X1.c b/none/tests/tilegx/insn_test_v2shl_X1.c
new file mode 100644
index 0000000..b3af644
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2shl_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2shl_X1.c
+//op=312
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x11c672ab78dd743b, 0x31d131ae6b7da416 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, 29514\n"
+ "shl16insli r34, r34, 14828\n"
+ "shl16insli r34, r34, 1013\n"
+ "shl16insli r34, r34, 14302\n"
+ "moveli r19, -22322\n"
+ "shl16insli r19, r19, -9600\n"
+ "shl16insli r19, r19, 31146\n"
+ "shl16insli r19, r19, -10762\n"
+ "moveli r19, 1482\n"
+ "shl16insli r19, r19, 23578\n"
+ "shl16insli r19, r19, 5382\n"
+ "shl16insli r19, r19, 26331\n"
+ "{ fnop ; v2shl r34, r19, r19 }\n"
+ "move %0, r34\n"
+ "move %1, r19\n"
+ "move %2, r19\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2shli_X0.c b/none/tests/tilegx/insn_test_v2shli_X0.c
new file mode 100644
index 0000000..b1edc20
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2shli_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v2shli_X0.c
+//op=313
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x499ada215a6ab283, 0x5c0e0858161567af };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, -21610\n"
+ "shl16insli r34, r34, -29358\n"
+ "shl16insli r34, r34, -13412\n"
+ "shl16insli r34, r34, 28660\n"
+ "moveli r48, 16361\n"
+ "shl16insli r48, r48, 2055\n"
+ "shl16insli r48, r48, 4220\n"
+ "shl16insli r48, r48, 9151\n"
+ "{ v2shli r34, r48, 2 ; fnop }\n"
+ "move %0, r34\n"
+ "move %1, r48\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2shli_X1.c b/none/tests/tilegx/insn_test_v2shli_X1.c
new file mode 100644
index 0000000..4802022
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2shli_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v2shli_X1.c
+//op=313
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x499ada215a6ab283, 0x5c0e0858161567af };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, -21610\n"
+ "shl16insli r34, r34, -29358\n"
+ "shl16insli r34, r34, -13412\n"
+ "shl16insli r34, r34, 28660\n"
+ "moveli r48, 16361\n"
+ "shl16insli r48, r48, 2055\n"
+ "shl16insli r48, r48, 4220\n"
+ "shl16insli r48, r48, 9151\n"
+ "{ fnop ; v2shli r34, r48, 2 }\n"
+ "move %0, r34\n"
+ "move %1, r48\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2shlsc_X0.c b/none/tests/tilegx/insn_test_v2shlsc_X0.c
new file mode 100644
index 0000000..a769286
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2shlsc_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2shlsc_X0.c
+//op=314
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x75c151f71f3dac9d, 0xc2cac20f9054ab64 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r42, -14850\n"
+ "shl16insli r42, r42, -32360\n"
+ "shl16insli r42, r42, 12889\n"
+ "shl16insli r42, r42, 3288\n"
+ "moveli r27, -3965\n"
+ "shl16insli r27, r27, -6372\n"
+ "shl16insli r27, r27, 21671\n"
+ "shl16insli r27, r27, 553\n"
+ "moveli r24, -19347\n"
+ "shl16insli r24, r24, 16492\n"
+ "shl16insli r24, r24, 10067\n"
+ "shl16insli r24, r24, 7567\n"
+ "{ v2shlsc r42, r27, r24 ; fnop }\n"
+ "move %0, r42\n"
+ "move %1, r27\n"
+ "move %2, r24\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2shlsc_X1.c b/none/tests/tilegx/insn_test_v2shlsc_X1.c
new file mode 100644
index 0000000..88a5b76
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2shlsc_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2shlsc_X1.c
+//op=314
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x75c151f71f3dac9d, 0xc2cac20f9054ab64 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r42, -14850\n"
+ "shl16insli r42, r42, -32360\n"
+ "shl16insli r42, r42, 12889\n"
+ "shl16insli r42, r42, 3288\n"
+ "moveli r27, -3965\n"
+ "shl16insli r27, r27, -6372\n"
+ "shl16insli r27, r27, 21671\n"
+ "shl16insli r27, r27, 553\n"
+ "moveli r24, -19347\n"
+ "shl16insli r24, r24, 16492\n"
+ "shl16insli r24, r24, 10067\n"
+ "shl16insli r24, r24, 7567\n"
+ "{ fnop ; v2shlsc r42, r27, r24 }\n"
+ "move %0, r42\n"
+ "move %1, r27\n"
+ "move %2, r24\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2shrs_X0.c b/none/tests/tilegx/insn_test_v2shrs_X0.c
new file mode 100644
index 0000000..8bb9af6
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2shrs_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2shrs_X0.c
+//op=315
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2e2bf09c65385753, 0xebdd0a243fdaeac0 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r27, -11697\n"
+ "shl16insli r27, r27, 28366\n"
+ "shl16insli r27, r27, -10445\n"
+ "shl16insli r27, r27, -26110\n"
+ "moveli r43, 19765\n"
+ "shl16insli r43, r43, 31767\n"
+ "shl16insli r43, r43, 18729\n"
+ "shl16insli r43, r43, 27881\n"
+ "moveli r4, -18306\n"
+ "shl16insli r4, r4, 19057\n"
+ "shl16insli r4, r4, 16125\n"
+ "shl16insli r4, r4, -18666\n"
+ "{ v2shrs r27, r43, r4 ; fnop }\n"
+ "move %0, r27\n"
+ "move %1, r43\n"
+ "move %2, r4\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2shrs_X1.c b/none/tests/tilegx/insn_test_v2shrs_X1.c
new file mode 100644
index 0000000..f55532f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2shrs_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2shrs_X1.c
+//op=315
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2e2bf09c65385753, 0xebdd0a243fdaeac0 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r27, -11697\n"
+ "shl16insli r27, r27, 28366\n"
+ "shl16insli r27, r27, -10445\n"
+ "shl16insli r27, r27, -26110\n"
+ "moveli r43, 19765\n"
+ "shl16insli r43, r43, 31767\n"
+ "shl16insli r43, r43, 18729\n"
+ "shl16insli r43, r43, 27881\n"
+ "moveli r4, -18306\n"
+ "shl16insli r4, r4, 19057\n"
+ "shl16insli r4, r4, 16125\n"
+ "shl16insli r4, r4, -18666\n"
+ "{ fnop ; v2shrs r27, r43, r4 }\n"
+ "move %0, r27\n"
+ "move %1, r43\n"
+ "move %2, r4\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2shrsi_X0.c b/none/tests/tilegx/insn_test_v2shrsi_X0.c
new file mode 100644
index 0000000..09c6987
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2shrsi_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v2shrsi_X0.c
+//op=316
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7c9257e7675dc02e, 0x194c873261582759 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r29, -19874\n"
+ "shl16insli r29, r29, -32652\n"
+ "shl16insli r29, r29, -27551\n"
+ "shl16insli r29, r29, 14010\n"
+ "moveli r39, -29195\n"
+ "shl16insli r39, r39, -14971\n"
+ "shl16insli r39, r39, 21267\n"
+ "shl16insli r39, r39, -6933\n"
+ "{ v2shrsi r29, r39, 29 ; fnop }\n"
+ "move %0, r29\n"
+ "move %1, r39\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2shrsi_X1.c b/none/tests/tilegx/insn_test_v2shrsi_X1.c
new file mode 100644
index 0000000..c6b5c86
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2shrsi_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v2shrsi_X1.c
+//op=316
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x7c9257e7675dc02e, 0x194c873261582759 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r29, -19874\n"
+ "shl16insli r29, r29, -32652\n"
+ "shl16insli r29, r29, -27551\n"
+ "shl16insli r29, r29, 14010\n"
+ "moveli r39, -29195\n"
+ "shl16insli r39, r39, -14971\n"
+ "shl16insli r39, r39, 21267\n"
+ "shl16insli r39, r39, -6933\n"
+ "{ fnop ; v2shrsi r29, r39, 29 }\n"
+ "move %0, r29\n"
+ "move %1, r39\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2shru_X0.c b/none/tests/tilegx/insn_test_v2shru_X0.c
new file mode 100644
index 0000000..71b6179
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2shru_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2shru_X0.c
+//op=317
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x57bcf4c2092d9b7c, 0xf0b9de77e27316a4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r50, 5090\n"
+ "shl16insli r50, r50, -3949\n"
+ "shl16insli r50, r50, -32171\n"
+ "shl16insli r50, r50, -2954\n"
+ "moveli r25, -17595\n"
+ "shl16insli r25, r25, 2853\n"
+ "shl16insli r25, r25, -2027\n"
+ "shl16insli r25, r25, 1813\n"
+ "moveli r0, 31428\n"
+ "shl16insli r0, r0, -7946\n"
+ "shl16insli r0, r0, -26525\n"
+ "shl16insli r0, r0, -15747\n"
+ "{ v2shru r50, r25, r0 ; fnop }\n"
+ "move %0, r50\n"
+ "move %1, r25\n"
+ "move %2, r0\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2shru_X1.c b/none/tests/tilegx/insn_test_v2shru_X1.c
new file mode 100644
index 0000000..dd2b369
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2shru_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2shru_X1.c
+//op=317
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x57bcf4c2092d9b7c, 0xf0b9de77e27316a4 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r50, 5090\n"
+ "shl16insli r50, r50, -3949\n"
+ "shl16insli r50, r50, -32171\n"
+ "shl16insli r50, r50, -2954\n"
+ "moveli r25, -17595\n"
+ "shl16insli r25, r25, 2853\n"
+ "shl16insli r25, r25, -2027\n"
+ "shl16insli r25, r25, 1813\n"
+ "moveli r0, 31428\n"
+ "shl16insli r0, r0, -7946\n"
+ "shl16insli r0, r0, -26525\n"
+ "shl16insli r0, r0, -15747\n"
+ "{ fnop ; v2shru r50, r25, r0 }\n"
+ "move %0, r50\n"
+ "move %1, r25\n"
+ "move %2, r0\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2shrui_X0.c b/none/tests/tilegx/insn_test_v2shrui_X0.c
new file mode 100644
index 0000000..990a05b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2shrui_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v2shrui_X0.c
+//op=318
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd373e4dd4abdb244, 0x2f10bc93a323ca0d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r23, 20609\n"
+ "shl16insli r23, r23, -28665\n"
+ "shl16insli r23, r23, -5637\n"
+ "shl16insli r23, r23, -7979\n"
+ "moveli r22, -6693\n"
+ "shl16insli r22, r22, 32122\n"
+ "shl16insli r22, r22, 32283\n"
+ "shl16insli r22, r22, -22128\n"
+ "{ v2shrui r23, r22, 62 ; fnop }\n"
+ "move %0, r23\n"
+ "move %1, r22\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2shrui_X1.c b/none/tests/tilegx/insn_test_v2shrui_X1.c
new file mode 100644
index 0000000..91bdb88
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2shrui_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_v2shrui_X1.c
+//op=318
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd373e4dd4abdb244, 0x2f10bc93a323ca0d };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r23, 20609\n"
+ "shl16insli r23, r23, -28665\n"
+ "shl16insli r23, r23, -5637\n"
+ "shl16insli r23, r23, -7979\n"
+ "moveli r22, -6693\n"
+ "shl16insli r22, r22, 32122\n"
+ "shl16insli r22, r22, 32283\n"
+ "shl16insli r22, r22, -22128\n"
+ "{ fnop ; v2shrui r23, r22, 62 }\n"
+ "move %0, r23\n"
+ "move %1, r22\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2sub_X0.c b/none/tests/tilegx/insn_test_v2sub_X0.c
new file mode 100644
index 0000000..62db68f
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2sub_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2sub_X0.c
+//op=319
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x61c13e55406befc0, 0xe69a8a5b32e86179 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r39, -19019\n"
+ "shl16insli r39, r39, 19818\n"
+ "shl16insli r39, r39, 30879\n"
+ "shl16insli r39, r39, -27712\n"
+ "moveli r20, 15911\n"
+ "shl16insli r20, r20, 26398\n"
+ "shl16insli r20, r20, -12667\n"
+ "shl16insli r20, r20, 29760\n"
+ "moveli r38, -21567\n"
+ "shl16insli r38, r38, -21338\n"
+ "shl16insli r38, r38, -1807\n"
+ "shl16insli r38, r38, -13303\n"
+ "{ v2sub r39, r20, r38 ; fnop }\n"
+ "move %0, r39\n"
+ "move %1, r20\n"
+ "move %2, r38\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2sub_X1.c b/none/tests/tilegx/insn_test_v2sub_X1.c
new file mode 100644
index 0000000..f69f4eb
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2sub_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2sub_X1.c
+//op=319
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x61c13e55406befc0, 0xe69a8a5b32e86179 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r39, -19019\n"
+ "shl16insli r39, r39, 19818\n"
+ "shl16insli r39, r39, 30879\n"
+ "shl16insli r39, r39, -27712\n"
+ "moveli r20, 15911\n"
+ "shl16insli r20, r20, 26398\n"
+ "shl16insli r20, r20, -12667\n"
+ "shl16insli r20, r20, 29760\n"
+ "moveli r38, -21567\n"
+ "shl16insli r38, r38, -21338\n"
+ "shl16insli r38, r38, -1807\n"
+ "shl16insli r38, r38, -13303\n"
+ "{ fnop ; v2sub r39, r20, r38 }\n"
+ "move %0, r39\n"
+ "move %1, r20\n"
+ "move %2, r38\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2subsc_X0.c b/none/tests/tilegx/insn_test_v2subsc_X0.c
new file mode 100644
index 0000000..2fde659
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2subsc_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2subsc_X0.c
+//op=320
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd8c6caab057cf371, 0x86109da9991e057a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r19, 13645\n"
+ "shl16insli r19, r19, 12702\n"
+ "shl16insli r19, r19, -22722\n"
+ "shl16insli r19, r19, 25020\n"
+ "moveli r19, 10415\n"
+ "shl16insli r19, r19, -24373\n"
+ "shl16insli r19, r19, 23725\n"
+ "shl16insli r19, r19, -29919\n"
+ "moveli r37, 12018\n"
+ "shl16insli r37, r37, -2612\n"
+ "shl16insli r37, r37, 2644\n"
+ "shl16insli r37, r37, -1447\n"
+ "{ v2subsc r19, r19, r37 ; fnop }\n"
+ "move %0, r19\n"
+ "move %1, r19\n"
+ "move %2, r37\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v2subsc_X1.c b/none/tests/tilegx/insn_test_v2subsc_X1.c
new file mode 100644
index 0000000..cd42c16
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v2subsc_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v2subsc_X1.c
+//op=320
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd8c6caab057cf371, 0x86109da9991e057a };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r19, 13645\n"
+ "shl16insli r19, r19, 12702\n"
+ "shl16insli r19, r19, -22722\n"
+ "shl16insli r19, r19, 25020\n"
+ "moveli r19, 10415\n"
+ "shl16insli r19, r19, -24373\n"
+ "shl16insli r19, r19, 23725\n"
+ "shl16insli r19, r19, -29919\n"
+ "moveli r37, 12018\n"
+ "shl16insli r37, r37, -2612\n"
+ "shl16insli r37, r37, 2644\n"
+ "shl16insli r37, r37, -1447\n"
+ "{ fnop ; v2subsc r19, r19, r37 }\n"
+ "move %0, r19\n"
+ "move %1, r19\n"
+ "move %2, r37\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4add_X0.c b/none/tests/tilegx/insn_test_v4add_X0.c
new file mode 100644
index 0000000..37ffc31
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4add_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4add_X0.c
+//op=321
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe8992341eac94df6, 0x65cc09dafded6d76 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r37, -15907\n"
+ "shl16insli r37, r37, -20157\n"
+ "shl16insli r37, r37, 22361\n"
+ "shl16insli r37, r37, -24834\n"
+ "moveli r23, 11074\n"
+ "shl16insli r23, r23, 24074\n"
+ "shl16insli r23, r23, 17669\n"
+ "shl16insli r23, r23, 8301\n"
+ "moveli r15, -19606\n"
+ "shl16insli r15, r15, 31855\n"
+ "shl16insli r15, r15, -1361\n"
+ "shl16insli r15, r15, -31541\n"
+ "{ v4add r37, r23, r15 ; fnop }\n"
+ "move %0, r37\n"
+ "move %1, r23\n"
+ "move %2, r15\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4add_X1.c b/none/tests/tilegx/insn_test_v4add_X1.c
new file mode 100644
index 0000000..010316c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4add_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4add_X1.c
+//op=321
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xe8992341eac94df6, 0x65cc09dafded6d76 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r37, -15907\n"
+ "shl16insli r37, r37, -20157\n"
+ "shl16insli r37, r37, 22361\n"
+ "shl16insli r37, r37, -24834\n"
+ "moveli r23, 11074\n"
+ "shl16insli r23, r23, 24074\n"
+ "shl16insli r23, r23, 17669\n"
+ "shl16insli r23, r23, 8301\n"
+ "moveli r15, -19606\n"
+ "shl16insli r15, r15, 31855\n"
+ "shl16insli r15, r15, -1361\n"
+ "shl16insli r15, r15, -31541\n"
+ "{ fnop ; v4add r37, r23, r15 }\n"
+ "move %0, r37\n"
+ "move %1, r23\n"
+ "move %2, r15\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4addsc_X0.c b/none/tests/tilegx/insn_test_v4addsc_X0.c
new file mode 100644
index 0000000..5852801
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4addsc_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4addsc_X0.c
+//op=322
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd4a558c5b71d713e, 0x4639d63ca03e5e4e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r35, 5393\n"
+ "shl16insli r35, r35, -22253\n"
+ "shl16insli r35, r35, 25749\n"
+ "shl16insli r35, r35, -7203\n"
+ "moveli r9, 21658\n"
+ "shl16insli r9, r9, 7462\n"
+ "shl16insli r9, r9, -214\n"
+ "shl16insli r9, r9, -426\n"
+ "moveli r15, -17213\n"
+ "shl16insli r15, r15, 15408\n"
+ "shl16insli r15, r15, -28656\n"
+ "shl16insli r15, r15, 10623\n"
+ "{ v4addsc r35, r9, r15 ; fnop }\n"
+ "move %0, r35\n"
+ "move %1, r9\n"
+ "move %2, r15\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4addsc_X1.c b/none/tests/tilegx/insn_test_v4addsc_X1.c
new file mode 100644
index 0000000..09923dc
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4addsc_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4addsc_X1.c
+//op=322
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xd4a558c5b71d713e, 0x4639d63ca03e5e4e };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r35, 5393\n"
+ "shl16insli r35, r35, -22253\n"
+ "shl16insli r35, r35, 25749\n"
+ "shl16insli r35, r35, -7203\n"
+ "moveli r9, 21658\n"
+ "shl16insli r9, r9, 7462\n"
+ "shl16insli r9, r9, -214\n"
+ "shl16insli r9, r9, -426\n"
+ "moveli r15, -17213\n"
+ "shl16insli r15, r15, 15408\n"
+ "shl16insli r15, r15, -28656\n"
+ "shl16insli r15, r15, 10623\n"
+ "{ fnop ; v4addsc r35, r9, r15 }\n"
+ "move %0, r35\n"
+ "move %1, r9\n"
+ "move %2, r15\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4int_h_X0.c b/none/tests/tilegx/insn_test_v4int_h_X0.c
new file mode 100644
index 0000000..bcecbee
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4int_h_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4int_h_X0.c
+//op=323
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x41bcf962c564feb9, 0xdaeccac706283a05 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, -28418\n"
+ "shl16insli r13, r13, 24424\n"
+ "shl16insli r13, r13, 6148\n"
+ "shl16insli r13, r13, -14231\n"
+ "moveli r43, -26849\n"
+ "shl16insli r43, r43, 4171\n"
+ "shl16insli r43, r43, -14537\n"
+ "shl16insli r43, r43, -11074\n"
+ "moveli r45, 356\n"
+ "shl16insli r45, r45, 21071\n"
+ "shl16insli r45, r45, -4609\n"
+ "shl16insli r45, r45, 18199\n"
+ "{ v4int_h r13, r43, r45 ; fnop }\n"
+ "move %0, r13\n"
+ "move %1, r43\n"
+ "move %2, r45\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4int_h_X1.c b/none/tests/tilegx/insn_test_v4int_h_X1.c
new file mode 100644
index 0000000..b1ba5c4
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4int_h_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4int_h_X1.c
+//op=323
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x41bcf962c564feb9, 0xdaeccac706283a05 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, -28418\n"
+ "shl16insli r13, r13, 24424\n"
+ "shl16insli r13, r13, 6148\n"
+ "shl16insli r13, r13, -14231\n"
+ "moveli r43, -26849\n"
+ "shl16insli r43, r43, 4171\n"
+ "shl16insli r43, r43, -14537\n"
+ "shl16insli r43, r43, -11074\n"
+ "moveli r45, 356\n"
+ "shl16insli r45, r45, 21071\n"
+ "shl16insli r45, r45, -4609\n"
+ "shl16insli r45, r45, 18199\n"
+ "{ fnop ; v4int_h r13, r43, r45 }\n"
+ "move %0, r13\n"
+ "move %1, r43\n"
+ "move %2, r45\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4int_l_X0.c b/none/tests/tilegx/insn_test_v4int_l_X0.c
new file mode 100644
index 0000000..cfa1062
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4int_l_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4int_l_X0.c
+//op=324
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x23b93f018ec49197, 0x228e8e83b7561e89 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r12, 7549\n"
+ "shl16insli r12, r12, -19041\n"
+ "shl16insli r12, r12, -30505\n"
+ "shl16insli r12, r12, -15011\n"
+ "moveli r7, 13064\n"
+ "shl16insli r7, r7, -5615\n"
+ "shl16insli r7, r7, -31470\n"
+ "shl16insli r7, r7, -17239\n"
+ "moveli r23, -24056\n"
+ "shl16insli r23, r23, -14095\n"
+ "shl16insli r23, r23, 1863\n"
+ "shl16insli r23, r23, -26485\n"
+ "{ v4int_l r12, r7, r23 ; fnop }\n"
+ "move %0, r12\n"
+ "move %1, r7\n"
+ "move %2, r23\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4int_l_X1.c b/none/tests/tilegx/insn_test_v4int_l_X1.c
new file mode 100644
index 0000000..0b52233
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4int_l_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4int_l_X1.c
+//op=324
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x23b93f018ec49197, 0x228e8e83b7561e89 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r12, 7549\n"
+ "shl16insli r12, r12, -19041\n"
+ "shl16insli r12, r12, -30505\n"
+ "shl16insli r12, r12, -15011\n"
+ "moveli r7, 13064\n"
+ "shl16insli r7, r7, -5615\n"
+ "shl16insli r7, r7, -31470\n"
+ "shl16insli r7, r7, -17239\n"
+ "moveli r23, -24056\n"
+ "shl16insli r23, r23, -14095\n"
+ "shl16insli r23, r23, 1863\n"
+ "shl16insli r23, r23, -26485\n"
+ "{ fnop ; v4int_l r12, r7, r23 }\n"
+ "move %0, r12\n"
+ "move %1, r7\n"
+ "move %2, r23\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4packsc_X0.c b/none/tests/tilegx/insn_test_v4packsc_X0.c
new file mode 100644
index 0000000..817edc9
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4packsc_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4packsc_X0.c
+//op=325
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9662ab02d3651bd3, 0x7d173ebe8d71845 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, 8404\n"
+ "shl16insli r11, r11, -13138\n"
+ "shl16insli r11, r11, -8174\n"
+ "shl16insli r11, r11, 18247\n"
+ "moveli r42, 26140\n"
+ "shl16insli r42, r42, 28081\n"
+ "shl16insli r42, r42, -4734\n"
+ "shl16insli r42, r42, -2567\n"
+ "moveli r34, 1665\n"
+ "shl16insli r34, r34, -24287\n"
+ "shl16insli r34, r34, 25276\n"
+ "shl16insli r34, r34, 26188\n"
+ "{ v4packsc r11, r42, r34 ; fnop }\n"
+ "move %0, r11\n"
+ "move %1, r42\n"
+ "move %2, r34\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4packsc_X1.c b/none/tests/tilegx/insn_test_v4packsc_X1.c
new file mode 100644
index 0000000..7f7189d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4packsc_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4packsc_X1.c
+//op=325
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x9662ab02d3651bd3, 0x7d173ebe8d71845 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, 8404\n"
+ "shl16insli r11, r11, -13138\n"
+ "shl16insli r11, r11, -8174\n"
+ "shl16insli r11, r11, 18247\n"
+ "moveli r42, 26140\n"
+ "shl16insli r42, r42, 28081\n"
+ "shl16insli r42, r42, -4734\n"
+ "shl16insli r42, r42, -2567\n"
+ "moveli r34, 1665\n"
+ "shl16insli r34, r34, -24287\n"
+ "shl16insli r34, r34, 25276\n"
+ "shl16insli r34, r34, 26188\n"
+ "{ fnop ; v4packsc r11, r42, r34 }\n"
+ "move %0, r11\n"
+ "move %1, r42\n"
+ "move %2, r34\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4shl_X0.c b/none/tests/tilegx/insn_test_v4shl_X0.c
new file mode 100644
index 0000000..da693dd
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4shl_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4shl_X0.c
+//op=326
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb3c4aad383be7970, 0xcdce8cd30da8f45b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, 25062\n"
+ "shl16insli r34, r34, -3688\n"
+ "shl16insli r34, r34, 15670\n"
+ "shl16insli r34, r34, 15480\n"
+ "moveli r41, 6763\n"
+ "shl16insli r41, r41, -31823\n"
+ "shl16insli r41, r41, 3289\n"
+ "shl16insli r41, r41, 2018\n"
+ "moveli r35, -12490\n"
+ "shl16insli r35, r35, 25114\n"
+ "shl16insli r35, r35, -6270\n"
+ "shl16insli r35, r35, -17183\n"
+ "{ v4shl r34, r41, r35 ; fnop }\n"
+ "move %0, r34\n"
+ "move %1, r41\n"
+ "move %2, r35\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4shl_X1.c b/none/tests/tilegx/insn_test_v4shl_X1.c
new file mode 100644
index 0000000..2c34587
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4shl_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4shl_X1.c
+//op=326
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xb3c4aad383be7970, 0xcdce8cd30da8f45b };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, 25062\n"
+ "shl16insli r34, r34, -3688\n"
+ "shl16insli r34, r34, 15670\n"
+ "shl16insli r34, r34, 15480\n"
+ "moveli r41, 6763\n"
+ "shl16insli r41, r41, -31823\n"
+ "shl16insli r41, r41, 3289\n"
+ "shl16insli r41, r41, 2018\n"
+ "moveli r35, -12490\n"
+ "shl16insli r35, r35, 25114\n"
+ "shl16insli r35, r35, -6270\n"
+ "shl16insli r35, r35, -17183\n"
+ "{ fnop ; v4shl r34, r41, r35 }\n"
+ "move %0, r34\n"
+ "move %1, r41\n"
+ "move %2, r35\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4shlsc_X0.c b/none/tests/tilegx/insn_test_v4shlsc_X0.c
new file mode 100644
index 0000000..d8dd118
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4shlsc_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4shlsc_X0.c
+//op=327
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2568a113544174a0, 0xd019893a69c430df };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, -616\n"
+ "shl16insli r13, r13, -17536\n"
+ "shl16insli r13, r13, -4093\n"
+ "shl16insli r13, r13, -4473\n"
+ "moveli r27, 28804\n"
+ "shl16insli r27, r27, -24345\n"
+ "shl16insli r27, r27, 3201\n"
+ "shl16insli r27, r27, -21187\n"
+ "moveli r33, 2083\n"
+ "shl16insli r33, r33, -15312\n"
+ "shl16insli r33, r33, -6918\n"
+ "shl16insli r33, r33, -23024\n"
+ "{ v4shlsc r13, r27, r33 ; fnop }\n"
+ "move %0, r13\n"
+ "move %1, r27\n"
+ "move %2, r33\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4shlsc_X1.c b/none/tests/tilegx/insn_test_v4shlsc_X1.c
new file mode 100644
index 0000000..a6ef69d
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4shlsc_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4shlsc_X1.c
+//op=327
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2568a113544174a0, 0xd019893a69c430df };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r13, -616\n"
+ "shl16insli r13, r13, -17536\n"
+ "shl16insli r13, r13, -4093\n"
+ "shl16insli r13, r13, -4473\n"
+ "moveli r27, 28804\n"
+ "shl16insli r27, r27, -24345\n"
+ "shl16insli r27, r27, 3201\n"
+ "shl16insli r27, r27, -21187\n"
+ "moveli r33, 2083\n"
+ "shl16insli r33, r33, -15312\n"
+ "shl16insli r33, r33, -6918\n"
+ "shl16insli r33, r33, -23024\n"
+ "{ fnop ; v4shlsc r13, r27, r33 }\n"
+ "move %0, r13\n"
+ "move %1, r27\n"
+ "move %2, r33\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4shrs_X0.c b/none/tests/tilegx/insn_test_v4shrs_X0.c
new file mode 100644
index 0000000..9bf37e2
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4shrs_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4shrs_X0.c
+//op=328
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2a5face79840f7a7, 0xd75570c277b73b03 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, 2928\n"
+ "shl16insli r34, r34, -22351\n"
+ "shl16insli r34, r34, 15965\n"
+ "shl16insli r34, r34, -15676\n"
+ "moveli r34, 24886\n"
+ "shl16insli r34, r34, 6119\n"
+ "shl16insli r34, r34, -23856\n"
+ "shl16insli r34, r34, -8685\n"
+ "moveli r45, 1295\n"
+ "shl16insli r45, r45, -12278\n"
+ "shl16insli r45, r45, -23875\n"
+ "shl16insli r45, r45, 20883\n"
+ "{ v4shrs r34, r34, r45 ; fnop }\n"
+ "move %0, r34\n"
+ "move %1, r34\n"
+ "move %2, r45\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4shrs_X1.c b/none/tests/tilegx/insn_test_v4shrs_X1.c
new file mode 100644
index 0000000..1fb011b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4shrs_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4shrs_X1.c
+//op=328
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2a5face79840f7a7, 0xd75570c277b73b03 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r34, 2928\n"
+ "shl16insli r34, r34, -22351\n"
+ "shl16insli r34, r34, 15965\n"
+ "shl16insli r34, r34, -15676\n"
+ "moveli r34, 24886\n"
+ "shl16insli r34, r34, 6119\n"
+ "shl16insli r34, r34, -23856\n"
+ "shl16insli r34, r34, -8685\n"
+ "moveli r45, 1295\n"
+ "shl16insli r45, r45, -12278\n"
+ "shl16insli r45, r45, -23875\n"
+ "shl16insli r45, r45, 20883\n"
+ "{ fnop ; v4shrs r34, r34, r45 }\n"
+ "move %0, r34\n"
+ "move %1, r34\n"
+ "move %2, r45\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4shru_X0.c b/none/tests/tilegx/insn_test_v4shru_X0.c
new file mode 100644
index 0000000..f5d8d2b
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4shru_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4shru_X0.c
+//op=329
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf942b109f0cbea25, 0x66bb2ebdeb23deb0 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r32, -17067\n"
+ "shl16insli r32, r32, 30779\n"
+ "shl16insli r32, r32, -22230\n"
+ "shl16insli r32, r32, -5615\n"
+ "moveli r50, -4121\n"
+ "shl16insli r50, r50, 16135\n"
+ "shl16insli r50, r50, -13858\n"
+ "shl16insli r50, r50, 4952\n"
+ "moveli r32, 12419\n"
+ "shl16insli r32, r32, -25174\n"
+ "shl16insli r32, r32, -23501\n"
+ "shl16insli r32, r32, 7961\n"
+ "{ v4shru r32, r50, r32 ; fnop }\n"
+ "move %0, r32\n"
+ "move %1, r50\n"
+ "move %2, r32\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4shru_X1.c b/none/tests/tilegx/insn_test_v4shru_X1.c
new file mode 100644
index 0000000..c77d354
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4shru_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4shru_X1.c
+//op=329
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xf942b109f0cbea25, 0x66bb2ebdeb23deb0 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r32, -17067\n"
+ "shl16insli r32, r32, 30779\n"
+ "shl16insli r32, r32, -22230\n"
+ "shl16insli r32, r32, -5615\n"
+ "moveli r50, -4121\n"
+ "shl16insli r50, r50, 16135\n"
+ "shl16insli r50, r50, -13858\n"
+ "shl16insli r50, r50, 4952\n"
+ "moveli r32, 12419\n"
+ "shl16insli r32, r32, -25174\n"
+ "shl16insli r32, r32, -23501\n"
+ "shl16insli r32, r32, 7961\n"
+ "{ fnop ; v4shru r32, r50, r32 }\n"
+ "move %0, r32\n"
+ "move %1, r50\n"
+ "move %2, r32\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4sub_X0.c b/none/tests/tilegx/insn_test_v4sub_X0.c
new file mode 100644
index 0000000..b2d9500
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4sub_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4sub_X0.c
+//op=330
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa3c6a3690a9f8085, 0xec7e102d827fb085 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r27, 16489\n"
+ "shl16insli r27, r27, 1852\n"
+ "shl16insli r27, r27, -22328\n"
+ "shl16insli r27, r27, -20016\n"
+ "moveli r15, -8129\n"
+ "shl16insli r15, r15, -16265\n"
+ "shl16insli r15, r15, -27946\n"
+ "shl16insli r15, r15, 22744\n"
+ "moveli r28, 12168\n"
+ "shl16insli r28, r28, 24071\n"
+ "shl16insli r28, r28, 5574\n"
+ "shl16insli r28, r28, 21456\n"
+ "{ v4sub r27, r15, r28 ; fnop }\n"
+ "move %0, r27\n"
+ "move %1, r15\n"
+ "move %2, r28\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4sub_X1.c b/none/tests/tilegx/insn_test_v4sub_X1.c
new file mode 100644
index 0000000..481bb20
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4sub_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4sub_X1.c
+//op=330
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0xa3c6a3690a9f8085, 0xec7e102d827fb085 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r27, 16489\n"
+ "shl16insli r27, r27, 1852\n"
+ "shl16insli r27, r27, -22328\n"
+ "shl16insli r27, r27, -20016\n"
+ "moveli r15, -8129\n"
+ "shl16insli r15, r15, -16265\n"
+ "shl16insli r15, r15, -27946\n"
+ "shl16insli r15, r15, 22744\n"
+ "moveli r28, 12168\n"
+ "shl16insli r28, r28, 24071\n"
+ "shl16insli r28, r28, 5574\n"
+ "shl16insli r28, r28, 21456\n"
+ "{ fnop ; v4sub r27, r15, r28 }\n"
+ "move %0, r27\n"
+ "move %1, r15\n"
+ "move %2, r28\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4subsc_X0.c b/none/tests/tilegx/insn_test_v4subsc_X0.c
new file mode 100644
index 0000000..f74f7c1
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4subsc_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4subsc_X0.c
+//op=331
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x92adb447873201ff, 0xd36a8d07bde44b83 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r42, 30010\n"
+ "shl16insli r42, r42, 8476\n"
+ "shl16insli r42, r42, 20122\n"
+ "shl16insli r42, r42, -20634\n"
+ "moveli r44, 26115\n"
+ "shl16insli r44, r44, 9284\n"
+ "shl16insli r44, r44, 29287\n"
+ "shl16insli r44, r44, 8638\n"
+ "moveli r29, 19275\n"
+ "shl16insli r29, r29, -29979\n"
+ "shl16insli r29, r29, 31395\n"
+ "shl16insli r29, r29, -21694\n"
+ "{ v4subsc r42, r44, r29 ; fnop }\n"
+ "move %0, r42\n"
+ "move %1, r44\n"
+ "move %2, r29\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_v4subsc_X1.c b/none/tests/tilegx/insn_test_v4subsc_X1.c
new file mode 100644
index 0000000..df250e7
--- /dev/null
+++ b/none/tests/tilegx/insn_test_v4subsc_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_v4subsc_X1.c
+//op=331
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x92adb447873201ff, 0xd36a8d07bde44b83 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r42, 30010\n"
+ "shl16insli r42, r42, 8476\n"
+ "shl16insli r42, r42, 20122\n"
+ "shl16insli r42, r42, -20634\n"
+ "moveli r44, 26115\n"
+ "shl16insli r44, r44, 9284\n"
+ "shl16insli r44, r44, 29287\n"
+ "shl16insli r44, r44, 8638\n"
+ "moveli r29, 19275\n"
+ "shl16insli r29, r29, -29979\n"
+ "shl16insli r29, r29, 31395\n"
+ "shl16insli r29, r29, -21694\n"
+ "{ fnop ; v4subsc r42, r44, r29 }\n"
+ "move %0, r42\n"
+ "move %1, r44\n"
+ "move %2, r29\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_wh64_X1.c b/none/tests/tilegx/insn_test_wh64_X1.c
new file mode 100644
index 0000000..827d7e3
--- /dev/null
+++ b/none/tests/tilegx/insn_test_wh64_X1.c
@@ -0,0 +1,30 @@
+//file: _insn_test_wh64_X1.c
+//op=332
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x109617bf21faf577, 0x269cb922a1bf2c20 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r11, -29126\n"
+ "shl16insli r11, r11, -20326\n"
+ "shl16insli r11, r11, 27689\n"
+ "shl16insli r11, r11, 15548\n"
+ "{ fnop ; wh64 r11 }\n"
+ "move %0, r11\n"
+ :"=r"(a[0]));
+ printf("%016lx\n", a[0]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_xor_X0.c b/none/tests/tilegx/insn_test_xor_X0.c
new file mode 100644
index 0000000..f1ee19c
--- /dev/null
+++ b/none/tests/tilegx/insn_test_xor_X0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_xor_X0.c
+//op=333
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4f4d9c00e64f18fd, 0x1894984f8a4b9b67 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r23, 15126\n"
+ "shl16insli r23, r23, -17631\n"
+ "shl16insli r23, r23, 31423\n"
+ "shl16insli r23, r23, 10557\n"
+ "moveli r20, -9320\n"
+ "shl16insli r20, r20, -29957\n"
+ "shl16insli r20, r20, 7281\n"
+ "shl16insli r20, r20, 3173\n"
+ "moveli r33, 2487\n"
+ "shl16insli r33, r33, 6184\n"
+ "shl16insli r33, r33, 10965\n"
+ "shl16insli r33, r33, -25198\n"
+ "{ xor r23, r20, r33 ; fnop }\n"
+ "move %0, r23\n"
+ "move %1, r20\n"
+ "move %2, r33\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_xor_X1.c b/none/tests/tilegx/insn_test_xor_X1.c
new file mode 100644
index 0000000..dd4af38
--- /dev/null
+++ b/none/tests/tilegx/insn_test_xor_X1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_xor_X1.c
+//op=333
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4f4d9c00e64f18fd, 0x1894984f8a4b9b67 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r23, 15126\n"
+ "shl16insli r23, r23, -17631\n"
+ "shl16insli r23, r23, 31423\n"
+ "shl16insli r23, r23, 10557\n"
+ "moveli r20, -9320\n"
+ "shl16insli r20, r20, -29957\n"
+ "shl16insli r20, r20, 7281\n"
+ "shl16insli r20, r20, 3173\n"
+ "moveli r33, 2487\n"
+ "shl16insli r33, r33, 6184\n"
+ "shl16insli r33, r33, 10965\n"
+ "shl16insli r33, r33, -25198\n"
+ "{ fnop ; xor r23, r20, r33 }\n"
+ "move %0, r23\n"
+ "move %1, r20\n"
+ "move %2, r33\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_xor_Y0.c b/none/tests/tilegx/insn_test_xor_Y0.c
new file mode 100644
index 0000000..bd345d2
--- /dev/null
+++ b/none/tests/tilegx/insn_test_xor_Y0.c
@@ -0,0 +1,42 @@
+//file: _insn_test_xor_Y0.c
+//op=333
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4f4d9c00e64f18fd, 0x1894984f8a4b9b67 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r23, 15126\n"
+ "shl16insli r23, r23, -17631\n"
+ "shl16insli r23, r23, 31423\n"
+ "shl16insli r23, r23, 10557\n"
+ "moveli r20, -9320\n"
+ "shl16insli r20, r20, -29957\n"
+ "shl16insli r20, r20, 7281\n"
+ "shl16insli r20, r20, 3173\n"
+ "moveli r33, 2487\n"
+ "shl16insli r33, r33, 6184\n"
+ "shl16insli r33, r33, 10965\n"
+ "shl16insli r33, r33, -25198\n"
+ "{ xor r23, r20, r33 ; fnop ; ld r63, r54 }\n"
+ "move %0, r23\n"
+ "move %1, r20\n"
+ "move %2, r33\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_xor_Y1.c b/none/tests/tilegx/insn_test_xor_Y1.c
new file mode 100644
index 0000000..c756d99
--- /dev/null
+++ b/none/tests/tilegx/insn_test_xor_Y1.c
@@ -0,0 +1,42 @@
+//file: _insn_test_xor_Y1.c
+//op=333
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x4f4d9c00e64f18fd, 0x1894984f8a4b9b67 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r23, 15126\n"
+ "shl16insli r23, r23, -17631\n"
+ "shl16insli r23, r23, 31423\n"
+ "shl16insli r23, r23, 10557\n"
+ "moveli r20, -9320\n"
+ "shl16insli r20, r20, -29957\n"
+ "shl16insli r20, r20, 7281\n"
+ "shl16insli r20, r20, 3173\n"
+ "moveli r33, 2487\n"
+ "shl16insli r33, r33, 6184\n"
+ "shl16insli r33, r33, 10965\n"
+ "shl16insli r33, r33, -25198\n"
+ "{ fnop ; xor r23, r20, r33 ; ld r63, r54 }\n"
+ "move %0, r23\n"
+ "move %1, r20\n"
+ "move %2, r33\n"
+ :"=r"(a[0]),"=r"(a[1]),"=r"(a[2]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ printf("%016lx\n", a[2]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_xori_X0.c b/none/tests/tilegx/insn_test_xori_X0.c
new file mode 100644
index 0000000..d966409
--- /dev/null
+++ b/none/tests/tilegx/insn_test_xori_X0.c
@@ -0,0 +1,36 @@
+//file: _insn_test_xori_X0.c
+//op=334
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2f6c6cfee316d7, 0x334d1321b4c11950 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r46, 31370\n"
+ "shl16insli r46, r46, -7442\n"
+ "shl16insli r46, r46, 26409\n"
+ "shl16insli r46, r46, 25903\n"
+ "moveli r40, 2219\n"
+ "shl16insli r40, r40, -14686\n"
+ "shl16insli r40, r40, 5250\n"
+ "shl16insli r40, r40, 16891\n"
+ "{ xori r46, r40, 75 ; fnop }\n"
+ "move %0, r46\n"
+ "move %1, r40\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/tilegx/insn_test_xori_X1.c b/none/tests/tilegx/insn_test_xori_X1.c
new file mode 100644
index 0000000..f061be5
--- /dev/null
+++ b/none/tests/tilegx/insn_test_xori_X1.c
@@ -0,0 +1,36 @@
+//file: _insn_test_xori_X1.c
+//op=334
+#include <stdio.h>
+#include <stdlib.h>
+
+void func_exit(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+void func_call(void) {
+ printf("%s\n", __func__);
+ exit(0);
+}
+
+unsigned long mem[2] = { 0x2f6c6cfee316d7, 0x334d1321b4c11950 };
+
+int main(void) {
+ unsigned long a[4] = { 0, 0 };
+ asm __volatile__ (
+ "moveli r46, 31370\n"
+ "shl16insli r46, r46, -7442\n"
+ "shl16insli r46, r46, 26409\n"
+ "shl16insli r46, r46, 25903\n"
+ "moveli r40, 2219\n"
+ "shl16insli r40, r40, -14686\n"
+ "shl16insli r40, r40, 5250\n"
+ "shl16insli r40, r40, 16891\n"
+ "{ fnop ; xori r46, r40, 75 }\n"
+ "move %0, r46\n"
+ "move %1, r40\n"
+ :"=r"(a[0]),"=r"(a[1]));
+ printf("%016lx\n", a[0]);
+ printf("%016lx\n", a[1]);
+ return 0;
+}
diff --git a/none/tests/x86-darwin/Makefile.in b/none/tests/x86-darwin/Makefile.in
new file mode 100644
index 0000000..76e67d9
--- /dev/null
+++ b/none/tests/x86-darwin/Makefile.in
@@ -0,0 +1,934 @@
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+# @configure_input@
+
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+
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+
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+
+
+# Make sure that all test programs have threaded errno.
+# Disable largefile support as there are test cases explictly enabling it.
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
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+
+AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
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+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
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+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
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+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
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+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+ -mmacosx-version-min=10.6 -fno-stack-protector
+
+AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
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+AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900
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+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@
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+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
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+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
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+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
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+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
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+
+# Baseline link flags for making vgpreload shared objects.
+#
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+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
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+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
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+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ @FLAG_M32@ $(FLAG_MMMX) $(FLAG_MSSE)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) @FLAG_M32@ \
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+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = \
+ filter_stderr
+
+EXTRA_DIST = \
+ bug341419.vgtest bug341419.stderr.exp \
+ bug350062.vgtest bug350062.stderr.exp
+
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .c .o .obj
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+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
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+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/x86-darwin/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/x86-darwin/Makefile
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+ @case '$?' in \
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+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
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+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
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+ $(AM_V_CCLD)$(LINK) $(bug350062_OBJECTS) $(bug350062_LDADD) $(LIBS)
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+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug341419.Po@am__quote@
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+ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
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+ctags: ctags-am
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+GTAGS:
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+ && gtags -i $(GTAGS_ARGS) "$$here"
+cscopelist: cscopelist-am
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+cscopelist-am: $(am__tagged_files)
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+ echo "$(subdir)/$$i"; \
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+ echo "$$sdir/$$i"; \
+ fi; \
+ done >> $(top_builddir)/cscope.files
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+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
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+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
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+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
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+ fi
+mostlyclean-generic:
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+clean-generic:
+
+distclean-generic:
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+dvi: dvi-am
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+html: html-am
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+.PRECIOUS: Makefile
+
+
+# This used to be required when Vex had a handwritten Makefile. It
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+
+#----------------------------------------------------------------------------
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+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
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+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
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+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
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+
+AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
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+ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8
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+AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \
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+
+AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \
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+AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
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+AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@
+AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
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+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
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+# Flags for the primary target. These must be used to build the
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+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
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+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
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+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
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+
+# Nb: Tools need to augment these flags with an arch-selection option, such
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+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
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+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
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+dist_noinst_SCRIPTS = \
+ filter_stderr
+
+EXTRA_DIST = \
+ bug345887.stderr.exp bug345887.vgtest \
+ hang.stderr.exp hang.vgtest \
+ seg_override.stderr.exp seg_override.stdout.exp seg_override.vgtest \
+ sigcontext.stdout.exp sigcontext.stderr.exp sigcontext.vgtest
+
+all: all-am
+
+.SUFFIXES:
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+ @for dep in $?; do \
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+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
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+ $(AUTOMAKE) --foreign none/tests/x86-linux/Makefile
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+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
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+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
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+ $(AM_V_CCLD)$(LINK) $(bug345887_OBJECTS) $(bug345887_LDADD) $(LIBS)
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+ echo "$(subdir)/$$i"; \
+ else \
+ echo "$$sdir/$$i"; \
+ fi; \
+ done >> $(top_builddir)/cscope.files
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+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
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+.PRECIOUS: Makefile
+
+
+# This used to be required when Vex had a handwritten Makefile. It
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+
+#----------------------------------------------------------------------------
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+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
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+# hook so that every time "make check" is run, we subsequently invoke
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+# newer than their corresponding .dSYM directory.
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+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
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+ dsymutil $$f; \
+ fi; \
+ done
+
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+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
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+# Flags for the primary target. These must be used to build the
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+ coredump_single_thread_mdb \
+ coredump_single_thread_sse_mdb \
+ filter_stderr
+
+EXTRA_DIST = \
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+ coredump_single_thread.stdout.exp coredump_single_thread.vgtest \
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+
+
+# This used to be required when Vex had a handwritten Makefile. It
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+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
+# It needs to be depended on by an 'uninstall-local' rule.
+uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
+uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/none/tests/x86-solaris/coredump_single_thread.post.exp b/none/tests/x86-solaris/coredump_single_thread.post.exp
index 407f7ac..446a029 100644
--- a/none/tests/x86-solaris/coredump_single_thread.post.exp
+++ b/none/tests/x86-solaris/coredump_single_thread.post.exp
@@ -1,7 +1,6 @@
---Status---
debugging core file of coredump_single (32-bit) from ...
initial argv: ./coredump_single_thread
-threading model: native threads
status: process terminated by SIGSEGV (Segmentation Fault), addr=........
---Registers---
@@ -12,7 +11,7 @@
%fs = 0x........ %esi = 0x00000105
%gs = 0x........ %edi = 0x00000106
- %eip = 0x........ coredump_single_thread`inner+0x........
+ %eip = 0x........ inner+0x........
%kesp = 0x00000000
@@ -21,7 +20,7 @@
%err = 0x0
---Stack trace---
-coredump_single_thread`inner
-coredump_single_thread`outer
-coredump_single_thread`main
-coredump_single_thread`_start
+inner
+outer
+main
+_start
diff --git a/none/tests/x86-solaris/coredump_single_thread_mdb b/none/tests/x86-solaris/coredump_single_thread_mdb
index c500478..b0053c6 100755
--- a/none/tests/x86-solaris/coredump_single_thread_mdb
+++ b/none/tests/x86-solaris/coredump_single_thread_mdb
@@ -7,6 +7,7 @@
echo "::status" | /usr/bin/mdb vgcore.* | \
perl -p -e 's/from \S*$/from .../' | \
perl -0 -p -e 's/^file: .+?^(initial argv:)/$1/ms' | \
+sed '/^threading model:/ d' | \
perl -p -e 's/addr=[0-9A-Fa-f]+/addr=......../g'
echo "\n---Registers---"
diff --git a/none/tests/x86-solaris/coredump_single_thread_sse.post.exp b/none/tests/x86-solaris/coredump_single_thread_sse.post.exp
index d42da8a..97d8781 100644
--- a/none/tests/x86-solaris/coredump_single_thread_sse.post.exp
+++ b/none/tests/x86-solaris/coredump_single_thread_sse.post.exp
@@ -1,7 +1,6 @@
---Status---
debugging core file of coredump_single (32-bit) from ...
initial argv: ./coredump_single_thread_sse
-threading model: native threads
status: process terminated by SIGSEGV (Segmentation Fault), addr=........
---SSE Registers---
diff --git a/none/tests/x86-solaris/coredump_single_thread_sse_mdb b/none/tests/x86-solaris/coredump_single_thread_sse_mdb
index 3cc5413..8d8f550 100755
--- a/none/tests/x86-solaris/coredump_single_thread_sse_mdb
+++ b/none/tests/x86-solaris/coredump_single_thread_sse_mdb
@@ -7,6 +7,7 @@
echo "::status" | /usr/bin/mdb vgcore.* | \
perl -p -e 's/from \S*$/from .../' | \
perl -0 -p -e 's/^file: .+?^(initial argv:)/$1/ms' | \
+sed '/^threading model:/ d' | \
perl -p -e 's/addr=[0-9A-Fa-f]+/addr=......../g'
echo "\n---SSE Registers---"
diff --git a/none/tests/x86/Makefile.in b/none/tests/x86/Makefile.in
new file mode 100644
index 0000000..fa4f777
--- /dev/null
+++ b/none/tests/x86/Makefile.in
@@ -0,0 +1,1517 @@
+# Makefile.in generated by automake 1.15 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994-2014 Free Software Foundation, Inc.
+
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs. And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+am__is_gnu_make = { \
+ if test -z '$(MAKELEVEL)'; then \
+ false; \
+ elif test -n '$(MAKE_HOST)'; then \
+ true; \
+ elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \
+ true; \
+ else \
+ false; \
+ fi; \
+}
+am__make_running_with_option = \
+ case $${target_option-} in \
+ ?) ;; \
+ *) echo "am__make_running_with_option: internal error: invalid" \
+ "target option '$${target_option-}' specified" >&2; \
+ exit 1;; \
+ esac; \
+ has_opt=no; \
+ sane_makeflags=$$MAKEFLAGS; \
+ if $(am__is_gnu_make); then \
+ sane_makeflags=$$MFLAGS; \
+ else \
+ case $$MAKEFLAGS in \
+ *\\[\ \ ]*) \
+ bs=\\; \
+ sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
+ | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \
+ esac; \
+ fi; \
+ skip_next=no; \
+ strip_trailopt () \
+ { \
+ flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
+ }; \
+ for flg in $$sane_makeflags; do \
+ test $$skip_next = yes && { skip_next=no; continue; }; \
+ case $$flg in \
+ *=*|--*) continue;; \
+ -*I) strip_trailopt 'I'; skip_next=yes;; \
+ -*I?*) strip_trailopt 'I';; \
+ -*O) strip_trailopt 'O'; skip_next=yes;; \
+ -*O?*) strip_trailopt 'O';; \
+ -*l) strip_trailopt 'l'; skip_next=yes;; \
+ -*l?*) strip_trailopt 'l';; \
+ -[dEDm]) skip_next=yes;; \
+ -[JT]) skip_next=yes;; \
+ esac; \
+ case $$flg in \
+ *$$target_option*) has_opt=yes; break;; \
+ esac; \
+ done; \
+ test $$has_opt = yes
+am__make_dryrun = (target_option=n; $(am__make_running_with_option))
+am__make_keepgoing = (target_option=k; $(am__make_running_with_option))
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+@COMPILER_IS_CLANG_TRUE@am__append_1 = -Wno-cast-align -Wno-self-assign \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-compare
+
+@SOLARIS_XPG_SYMBOLS_PRESENT_TRUE@am__append_2 = -Wl,-M,$(top_srcdir)/solaris/vgpreload-solaris.mapfile
+
+# The Android toolchain includes all kinds of stdlib helpers present in
+# bionic which is bad because we are not linking with it and the Android
+# linker will panic.
+@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_3 = -nostdlib
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+
+# Make sure that all test programs have threaded errno.
+# Disable largefile support as there are test cases explictly enabling it.
+@VGCONF_OS_IS_SOLARIS_TRUE@am__append_5 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@
+@COMPILER_IS_CLANG_TRUE@am__append_6 = -Wno-format-extra-args \
+@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \
+@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-constant-out-of-range-compare \
+@COMPILER_IS_CLANG_TRUE@ -Wno-self-assign -Wno-string-plus-int \
+@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \
+@COMPILER_IS_CLANG_TRUE@ clang 3.0.0
+@COMPILER_IS_CLANG_TRUE@am__append_7 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp
+@COMPILER_IS_CLANG_FALSE@am__append_8 = insn_sse insn_sse2
+@BUILD_SSSE3_TESTS_TRUE@@COMPILER_IS_CLANG_FALSE@am__append_9 = insn_ssse3
+# Sun Studio assembler fails to build some tests (illegal mnemonic).
+@BUILD_SSE3_TESTS_TRUE@@COMPILER_IS_CLANG_FALSE@@SOLARIS_SUN_STUDIO_AS_FALSE@am__append_10 = insn_sse3
+
+# Sun Studio assembler fails to build some tests (illegal mnemonic).
+@SOLARIS_SUN_STUDIO_AS_FALSE@am__append_11 = insn_fpu
+check_PROGRAMS = aad_aam$(EXEEXT) allexec$(EXEEXT) badseg$(EXEEXT) \
+ bt_everything$(EXEEXT) bt_literal$(EXEEXT) \
+ bug125959-x86$(EXEEXT) bug126147-x86$(EXEEXT) \
+ bug132813-x86$(EXEEXT) bug135421-x86$(EXEEXT) \
+ bug137714-x86$(EXEEXT) bug152818-x86$(EXEEXT) \
+ cmpxchg8b$(EXEEXT) cpuid$(EXEEXT) cse_fail$(EXEEXT) \
+ fcmovnu$(EXEEXT) fpu_lazy_eflags$(EXEEXT) fxtract$(EXEEXT) \
+ getseg$(EXEEXT) incdec_alt$(EXEEXT) $(am__EXEEXT_5) \
+ int$(EXEEXT) jcxz$(EXEEXT) lahf$(EXEEXT) looper$(EXEEXT) \
+ movx$(EXEEXT) sbbmisc$(EXEEXT) shift_ndep$(EXEEXT) \
+ smc1$(EXEEXT) x86locked$(EXEEXT) x87trigOOR$(EXEEXT) \
+ yield$(EXEEXT) xadd$(EXEEXT) $(am__EXEEXT_6) $(am__EXEEXT_7) \
+ $(am__EXEEXT_8) $(am__EXEEXT_9) $(am__EXEEXT_10)
+@BUILD_SSSE3_TESTS_TRUE@am__append_12 = ssse3_misaligned
+@BUILD_LZCNT_TESTS_TRUE@am__append_13 = lzcnt32
+@BUILD_MOVBE_TESTS_TRUE@am__append_14 = movbe
+# Sun Studio assembler fails to assemble the bound instruction
+# clang errors out complaining that %eax as the 1st operand in the bound
+# insn is an invalid operand.
+@COMPILER_IS_CLANG_FALSE@@SOLARIS_SUN_STUDIO_AS_FALSE@@VGCONF_OS_IS_DARWIN_FALSE@am__append_15 = faultstatus
+# Sun Studio assembler fails to assemble pushw %fs, popw %fs
+@SOLARIS_SUN_STUDIO_AS_FALSE@am__append_16 = pushpopseg
+
+# Some of the tests (bug125959_x86, bug152818_x86, insn_*) need
+# -mdynamic-no-pic. I tried setting *_CFLAGS separately for all of them,
+# but it caused problems with the generation of insn_*.c. So just use this
+# crude approach of setting -mdynamic-no-pic for all tests in this
+# directory.
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_17 = -mdynamic-no-pic
+subdir = none/tests/x86
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.ac
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+ $(ACLOCAL_M4)
+DIST_COMMON = $(srcdir)/Makefile.am $(dist_noinst_SCRIPTS) \
+ $(am__DIST_COMMON)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+@COMPILER_IS_CLANG_FALSE@am__EXEEXT_1 = insn_sse$(EXEEXT) \
+@COMPILER_IS_CLANG_FALSE@ insn_sse2$(EXEEXT)
+@BUILD_SSSE3_TESTS_TRUE@@COMPILER_IS_CLANG_FALSE@am__EXEEXT_2 = insn_ssse3$(EXEEXT)
+@BUILD_SSE3_TESTS_TRUE@@COMPILER_IS_CLANG_FALSE@@SOLARIS_SUN_STUDIO_AS_FALSE@am__EXEEXT_3 = insn_sse3$(EXEEXT)
+@SOLARIS_SUN_STUDIO_AS_FALSE@am__EXEEXT_4 = insn_fpu$(EXEEXT)
+am__EXEEXT_5 = insn_basic$(EXEEXT) insn_cmov$(EXEEXT) \
+ insn_mmx$(EXEEXT) insn_mmxext$(EXEEXT) $(am__EXEEXT_1) \
+ $(am__EXEEXT_2) $(am__EXEEXT_3) $(am__EXEEXT_4)
+@BUILD_SSSE3_TESTS_TRUE@am__EXEEXT_6 = ssse3_misaligned$(EXEEXT)
+@BUILD_LZCNT_TESTS_TRUE@am__EXEEXT_7 = lzcnt32$(EXEEXT)
+@BUILD_MOVBE_TESTS_TRUE@am__EXEEXT_8 = movbe$(EXEEXT)
+@COMPILER_IS_CLANG_FALSE@@SOLARIS_SUN_STUDIO_AS_FALSE@@VGCONF_OS_IS_DARWIN_FALSE@am__EXEEXT_9 = faultstatus$(EXEEXT)
+@SOLARIS_SUN_STUDIO_AS_FALSE@am__EXEEXT_10 = pushpopseg$(EXEEXT)
+aad_aam_SOURCES = aad_aam.c
+aad_aam_OBJECTS = aad_aam.$(OBJEXT)
+aad_aam_LDADD = $(LDADD)
+allexec_SOURCES = allexec.c
+allexec_OBJECTS = allexec-allexec.$(OBJEXT)
+allexec_LDADD = $(LDADD)
+allexec_LINK = $(CCLD) $(allexec_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+badseg_SOURCES = badseg.c
+badseg_OBJECTS = badseg.$(OBJEXT)
+badseg_LDADD = $(LDADD)
+bt_everything_SOURCES = bt_everything.c
+bt_everything_OBJECTS = bt_everything.$(OBJEXT)
+bt_everything_LDADD = $(LDADD)
+bt_literal_SOURCES = bt_literal.c
+bt_literal_OBJECTS = bt_literal.$(OBJEXT)
+bt_literal_LDADD = $(LDADD)
+bug125959_x86_SOURCES = bug125959-x86.c
+bug125959_x86_OBJECTS = bug125959-x86.$(OBJEXT)
+bug125959_x86_LDADD = $(LDADD)
+bug126147_x86_SOURCES = bug126147-x86.c
+bug126147_x86_OBJECTS = bug126147-x86.$(OBJEXT)
+bug126147_x86_LDADD = $(LDADD)
+bug132813_x86_SOURCES = bug132813-x86.c
+bug132813_x86_OBJECTS = bug132813-x86.$(OBJEXT)
+bug132813_x86_LDADD = $(LDADD)
+bug135421_x86_SOURCES = bug135421-x86.c
+bug135421_x86_OBJECTS = bug135421-x86.$(OBJEXT)
+bug135421_x86_LDADD = $(LDADD)
+bug137714_x86_SOURCES = bug137714-x86.c
+bug137714_x86_OBJECTS = bug137714-x86.$(OBJEXT)
+bug137714_x86_LDADD = $(LDADD)
+bug152818_x86_SOURCES = bug152818-x86.c
+bug152818_x86_OBJECTS = bug152818-x86.$(OBJEXT)
+bug152818_x86_LDADD = $(LDADD)
+cmpxchg8b_SOURCES = cmpxchg8b.c
+cmpxchg8b_OBJECTS = cmpxchg8b.$(OBJEXT)
+cmpxchg8b_LDADD = $(LDADD)
+am_cpuid_OBJECTS = cpuid_c.$(OBJEXT) cpuid_s.$(OBJEXT)
+cpuid_OBJECTS = $(am_cpuid_OBJECTS)
+cpuid_LDADD = $(LDADD)
+cse_fail_SOURCES = cse_fail.c
+cse_fail_OBJECTS = cse_fail.$(OBJEXT)
+cse_fail_LDADD = $(LDADD)
+faultstatus_SOURCES = faultstatus.c
+faultstatus_OBJECTS = faultstatus.$(OBJEXT)
+faultstatus_LDADD = $(LDADD)
+fcmovnu_SOURCES = fcmovnu.c
+fcmovnu_OBJECTS = fcmovnu.$(OBJEXT)
+fcmovnu_LDADD = $(LDADD)
+fpu_lazy_eflags_SOURCES = fpu_lazy_eflags.c
+fpu_lazy_eflags_OBJECTS = fpu_lazy_eflags-fpu_lazy_eflags.$(OBJEXT)
+fpu_lazy_eflags_LDADD = $(LDADD)
+fpu_lazy_eflags_LINK = $(CCLD) $(fpu_lazy_eflags_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
+fxtract_SOURCES = fxtract.c
+fxtract_OBJECTS = fxtract-fxtract.$(OBJEXT)
+fxtract_DEPENDENCIES =
+fxtract_LINK = $(CCLD) $(fxtract_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+ $(LDFLAGS) -o $@
+getseg_SOURCES = getseg.c
+getseg_OBJECTS = getseg.$(OBJEXT)
+getseg_LDADD = $(LDADD)
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+incdec_alt_OBJECTS = incdec_alt.$(OBJEXT)
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+am_insn_basic_OBJECTS = insn_basic.$(OBJEXT)
+insn_basic_OBJECTS = $(am_insn_basic_OBJECTS)
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+am_insn_cmov_OBJECTS = insn_cmov.$(OBJEXT)
+insn_cmov_OBJECTS = $(am_insn_cmov_OBJECTS)
+insn_cmov_DEPENDENCIES =
+am_insn_fpu_OBJECTS = insn_fpu.$(OBJEXT)
+insn_fpu_OBJECTS = $(am_insn_fpu_OBJECTS)
+insn_fpu_DEPENDENCIES =
+am_insn_mmx_OBJECTS = insn_mmx.$(OBJEXT)
+insn_mmx_OBJECTS = $(am_insn_mmx_OBJECTS)
+insn_mmx_DEPENDENCIES =
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+insn_mmxext_OBJECTS = $(am_insn_mmxext_OBJECTS)
+insn_mmxext_DEPENDENCIES =
+am_insn_sse_OBJECTS = insn_sse.$(OBJEXT)
+insn_sse_OBJECTS = $(am_insn_sse_OBJECTS)
+insn_sse_DEPENDENCIES =
+am_insn_sse2_OBJECTS = insn_sse2.$(OBJEXT)
+insn_sse2_OBJECTS = $(am_insn_sse2_OBJECTS)
+insn_sse2_DEPENDENCIES =
+am_insn_sse3_OBJECTS = insn_sse3.$(OBJEXT)
+insn_sse3_OBJECTS = $(am_insn_sse3_OBJECTS)
+insn_sse3_DEPENDENCIES =
+am_insn_ssse3_OBJECTS = insn_ssse3.$(OBJEXT)
+insn_ssse3_OBJECTS = $(am_insn_ssse3_OBJECTS)
+insn_ssse3_DEPENDENCIES =
+int_SOURCES = int.c
+int_OBJECTS = int.$(OBJEXT)
+int_LDADD = $(LDADD)
+jcxz_SOURCES = jcxz.c
+jcxz_OBJECTS = jcxz.$(OBJEXT)
+jcxz_LDADD = $(LDADD)
+lahf_SOURCES = lahf.c
+lahf_OBJECTS = lahf.$(OBJEXT)
+lahf_LDADD = $(LDADD)
+looper_SOURCES = looper.c
+looper_OBJECTS = looper.$(OBJEXT)
+looper_LDADD = $(LDADD)
+lzcnt32_SOURCES = lzcnt32.c
+lzcnt32_OBJECTS = lzcnt32.$(OBJEXT)
+lzcnt32_LDADD = $(LDADD)
+movbe_SOURCES = movbe.c
+movbe_OBJECTS = movbe.$(OBJEXT)
+movbe_LDADD = $(LDADD)
+movx_SOURCES = movx.c
+movx_OBJECTS = movx.$(OBJEXT)
+movx_LDADD = $(LDADD)
+pushpopseg_SOURCES = pushpopseg.c
+pushpopseg_OBJECTS = pushpopseg.$(OBJEXT)
+pushpopseg_LDADD = $(LDADD)
+sbbmisc_SOURCES = sbbmisc.c
+sbbmisc_OBJECTS = sbbmisc.$(OBJEXT)
+sbbmisc_LDADD = $(LDADD)
+shift_ndep_SOURCES = shift_ndep.c
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+#----------------------------------------------------------------------------
+# Flags
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+# Baseline flags for all compilations. Aim here is to maximise
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+
+
+# These flags are used for building the preload shared objects (PSOs).
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+
+# Flags for specific targets.
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+ $(AM_CFLAGS_PSO_BASE)
+
+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
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+ $(AM_CFLAGS_BASE) -fomit-frame-pointer \
+ @SOLARIS_UNDEF_LARGESOURCE@
+
+AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM
+AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@
+AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \
+ $(AM_CFLAGS_BASE) -fomit-frame-pointer
+
+AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM
+
+# Flags for the primary target. These must be used to build the
+# regtests and performance tests. In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC =
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_3)
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \
+ -Wl,-z,interpose,-z,initfirst $(am__append_2)
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
+ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \
+ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \
+ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \
+ $(am__append_4)
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_5) $(am__append_6) \
+ @FLAG_M32@ $(FLAG_MMMX) $(FLAG_MSSE) $(am__append_17)
+AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \
+ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_7) @FLAG_M32@ \
+ $(FLAG_MMMX) $(FLAG_MSSE)
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake; see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = filter_cpuid filter_inf_nan filter_stderr gen_insn_test.pl
+CLEANFILES = $(addsuffix .c,$(INSN_TESTS))
+INSN_TESTS = insn_basic insn_cmov insn_mmx insn_mmxext $(am__append_8) \
+ $(am__append_9) $(am__append_10) $(am__append_11)
+
+# Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS,
+# to avoid packaging screwups if 'make dist' is run on a machine
+# which failed the BUILD_SSE3_TESTS test in configure.in.
+EXTRA_DIST = \
+ aad_aam.stdout.exp aad_aam.stderr.exp aad_aam.vgtest \
+ badseg.stderr.exp badseg.stdout.exp badseg.stdout.exp-solaris \
+ badseg.vgtest \
+ bt_everything.stderr.exp bt_everything.stdout.exp bt_everything.vgtest \
+ bt_literal.stderr.exp bt_literal.stdout.exp bt_literal.vgtest \
+ bug125959-x86.stderr.exp bug125959-x86.stdout.exp bug125959-x86.vgtest \
+ bug126147-x86.stderr.exp bug126147-x86.stdout.exp bug126147-x86.vgtest \
+ bug132813-x86.stderr.exp bug132813-x86.stdout.exp bug132813-x86.vgtest \
+ bug135421-x86.stderr.exp bug135421-x86.stdout.exp bug135421-x86.vgtest \
+ bug137714-x86.stderr.exp bug137714-x86.stdout.exp bug137714-x86.vgtest \
+ bug152818-x86.stderr.exp bug152818-x86.stdout.exp bug152818-x86.vgtest \
+ cmpxchg8b.stderr.exp cmpxchg8b.stdout.exp cmpxchg8b.vgtest \
+ cpuid.stderr.exp cpuid.stdout.exp cpuid.vgtest \
+ cse_fail.stderr.exp cse_fail.stdout.exp cse_fail.vgtest \
+ faultstatus.disabled faultstatus.stderr.exp \
+ fcmovnu.vgtest fcmovnu.stderr.exp fcmovnu.stdout.exp \
+ fpu_lazy_eflags.stderr.exp fpu_lazy_eflags.stdout.exp \
+ fpu_lazy_eflags.vgtest \
+ fxtract.stdout.exp fxtract.stderr.exp fxtract.vgtest \
+ fxtract.stdout.exp-older-glibc \
+ getseg.stdout.exp getseg.stderr.exp getseg.vgtest \
+ incdec_alt.stdout.exp incdec_alt.stderr.exp incdec_alt.vgtest \
+ int.stderr.exp int.stdout.exp int.disabled \
+ $(addsuffix .stderr.exp,$(INSN_TESTS)) \
+ $(addsuffix .stdout.exp,$(INSN_TESTS)) \
+ $(addsuffix .vgtest,$(INSN_TESTS)) \
+ insn_fpu.stdout.exp insn_fpu.stderr.exp insn_fpu.vgtest \
+ insn_sse.stdout.exp insn_sse.stderr.exp insn_sse.vgtest \
+ insn_sse2.stdout.exp insn_sse2.stderr.exp insn_sse2.vgtest \
+ insn_sse3.stdout.exp insn_sse3.stderr.exp insn_sse3.vgtest \
+ insn_ssse3.stdout.exp insn_ssse3.stderr.exp insn_ssse3.vgtest \
+ jcxz.stdout.exp jcxz.stderr.exp jcxz.vgtest \
+ lahf.stdout.exp lahf.stderr.exp lahf.vgtest \
+ looper.stderr.exp looper.stdout.exp looper.vgtest \
+ lzcnt32.stderr.exp lzcnt32.stdout.exp lzcnt32.vgtest \
+ movx.stderr.exp movx.stdout.exp movx.vgtest \
+ movbe.stderr.exp movbe.stdout.exp movbe.vgtest \
+ pushpopseg.stderr.exp pushpopseg.stdout.exp pushpopseg.vgtest \
+ sbbmisc.stderr.exp sbbmisc.stdout.exp sbbmisc.vgtest \
+ shift_ndep.stderr.exp shift_ndep.stdout.exp shift_ndep.vgtest \
+ smc1.stderr.exp smc1.stdout.exp smc1.vgtest \
+ ssse3_misaligned.stderr.exp ssse3_misaligned.stdout.exp \
+ ssse3_misaligned.vgtest ssse3_misaligned.c \
+ x86locked.vgtest x86locked.stdout.exp x86locked.stderr.exp \
+ x87trigOOR.vgtest x87trigOOR.stdout.exp x87trigOOR.stderr.exp \
+ yield.stderr.exp yield.stdout.exp yield.disabled \
+ xadd.stdout.exp xadd.stderr.exp xadd.vgtest
+
+allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
+cpuid_SOURCES = cpuid_c.c cpuid_s.S
+# fpu_lazy_eflags must use these flags -- the bug only occurred with them.
+fpu_lazy_eflags_CFLAGS = $(AM_CFLAGS) -O2 -march=pentiumpro
+fxtract_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_OVERFLOW@
+fxtract_LDADD = -lm
+insn_basic_SOURCES = insn_basic.def
+insn_basic_LDADD = -lm
+insn_fpu_SOURCES = insn_fpu.def
+insn_fpu_LDADD = -lm
+insn_cmov_SOURCES = insn_cmov.def
+insn_cmov_LDADD = -lm
+insn_mmx_SOURCES = insn_mmx.def
+insn_mmx_LDADD = -lm
+insn_mmxext_SOURCES = insn_mmxext.def
+insn_mmxext_LDADD = -lm
+insn_sse_SOURCES = insn_sse.def
+insn_sse_LDADD = -lm
+insn_sse2_SOURCES = insn_sse2.def
+insn_sse2_LDADD = -lm
+insn_sse3_SOURCES = insn_sse3.def
+insn_sse3_LDADD = -lm
+insn_ssse3_SOURCES = insn_ssse3.def
+insn_ssse3_LDADD = -lm
+x86locked_CFLAGS = $(AM_CFLAGS) -O
+yield_LDADD = -lpthread
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .S .c .def .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+ @for dep in $?; do \
+ case '$(am__configure_deps)' in \
+ *$$dep*) \
+ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+ && { if test -f $@; then exit 0; else break; fi; }; \
+ exit 1;; \
+ esac; \
+ done; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/x86/Makefile'; \
+ $(am__cd) $(top_srcdir) && \
+ $(AUTOMAKE) --foreign none/tests/x86/Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+ @case '$?' in \
+ *config.status*) \
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+ *) \
+ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+ esac;
+$(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__empty):
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+ -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+
+aad_aam$(EXEEXT): $(aad_aam_OBJECTS) $(aad_aam_DEPENDENCIES) $(EXTRA_aad_aam_DEPENDENCIES)
+ @rm -f aad_aam$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(aad_aam_OBJECTS) $(aad_aam_LDADD) $(LIBS)
+
+allexec$(EXEEXT): $(allexec_OBJECTS) $(allexec_DEPENDENCIES) $(EXTRA_allexec_DEPENDENCIES)
+ @rm -f allexec$(EXEEXT)
+ $(AM_V_CCLD)$(allexec_LINK) $(allexec_OBJECTS) $(allexec_LDADD) $(LIBS)
+
+badseg$(EXEEXT): $(badseg_OBJECTS) $(badseg_DEPENDENCIES) $(EXTRA_badseg_DEPENDENCIES)
+ @rm -f badseg$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(badseg_OBJECTS) $(badseg_LDADD) $(LIBS)
+
+bt_everything$(EXEEXT): $(bt_everything_OBJECTS) $(bt_everything_DEPENDENCIES) $(EXTRA_bt_everything_DEPENDENCIES)
+ @rm -f bt_everything$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bt_everything_OBJECTS) $(bt_everything_LDADD) $(LIBS)
+
+bt_literal$(EXEEXT): $(bt_literal_OBJECTS) $(bt_literal_DEPENDENCIES) $(EXTRA_bt_literal_DEPENDENCIES)
+ @rm -f bt_literal$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bt_literal_OBJECTS) $(bt_literal_LDADD) $(LIBS)
+
+bug125959-x86$(EXEEXT): $(bug125959_x86_OBJECTS) $(bug125959_x86_DEPENDENCIES) $(EXTRA_bug125959_x86_DEPENDENCIES)
+ @rm -f bug125959-x86$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug125959_x86_OBJECTS) $(bug125959_x86_LDADD) $(LIBS)
+
+bug126147-x86$(EXEEXT): $(bug126147_x86_OBJECTS) $(bug126147_x86_DEPENDENCIES) $(EXTRA_bug126147_x86_DEPENDENCIES)
+ @rm -f bug126147-x86$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug126147_x86_OBJECTS) $(bug126147_x86_LDADD) $(LIBS)
+
+bug132813-x86$(EXEEXT): $(bug132813_x86_OBJECTS) $(bug132813_x86_DEPENDENCIES) $(EXTRA_bug132813_x86_DEPENDENCIES)
+ @rm -f bug132813-x86$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug132813_x86_OBJECTS) $(bug132813_x86_LDADD) $(LIBS)
+
+bug135421-x86$(EXEEXT): $(bug135421_x86_OBJECTS) $(bug135421_x86_DEPENDENCIES) $(EXTRA_bug135421_x86_DEPENDENCIES)
+ @rm -f bug135421-x86$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug135421_x86_OBJECTS) $(bug135421_x86_LDADD) $(LIBS)
+
+bug137714-x86$(EXEEXT): $(bug137714_x86_OBJECTS) $(bug137714_x86_DEPENDENCIES) $(EXTRA_bug137714_x86_DEPENDENCIES)
+ @rm -f bug137714-x86$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug137714_x86_OBJECTS) $(bug137714_x86_LDADD) $(LIBS)
+
+bug152818-x86$(EXEEXT): $(bug152818_x86_OBJECTS) $(bug152818_x86_DEPENDENCIES) $(EXTRA_bug152818_x86_DEPENDENCIES)
+ @rm -f bug152818-x86$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(bug152818_x86_OBJECTS) $(bug152818_x86_LDADD) $(LIBS)
+
+cmpxchg8b$(EXEEXT): $(cmpxchg8b_OBJECTS) $(cmpxchg8b_DEPENDENCIES) $(EXTRA_cmpxchg8b_DEPENDENCIES)
+ @rm -f cmpxchg8b$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(cmpxchg8b_OBJECTS) $(cmpxchg8b_LDADD) $(LIBS)
+
+cpuid$(EXEEXT): $(cpuid_OBJECTS) $(cpuid_DEPENDENCIES) $(EXTRA_cpuid_DEPENDENCIES)
+ @rm -f cpuid$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(cpuid_OBJECTS) $(cpuid_LDADD) $(LIBS)
+
+cse_fail$(EXEEXT): $(cse_fail_OBJECTS) $(cse_fail_DEPENDENCIES) $(EXTRA_cse_fail_DEPENDENCIES)
+ @rm -f cse_fail$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(cse_fail_OBJECTS) $(cse_fail_LDADD) $(LIBS)
+
+faultstatus$(EXEEXT): $(faultstatus_OBJECTS) $(faultstatus_DEPENDENCIES) $(EXTRA_faultstatus_DEPENDENCIES)
+ @rm -f faultstatus$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(faultstatus_OBJECTS) $(faultstatus_LDADD) $(LIBS)
+
+fcmovnu$(EXEEXT): $(fcmovnu_OBJECTS) $(fcmovnu_DEPENDENCIES) $(EXTRA_fcmovnu_DEPENDENCIES)
+ @rm -f fcmovnu$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(fcmovnu_OBJECTS) $(fcmovnu_LDADD) $(LIBS)
+
+fpu_lazy_eflags$(EXEEXT): $(fpu_lazy_eflags_OBJECTS) $(fpu_lazy_eflags_DEPENDENCIES) $(EXTRA_fpu_lazy_eflags_DEPENDENCIES)
+ @rm -f fpu_lazy_eflags$(EXEEXT)
+ $(AM_V_CCLD)$(fpu_lazy_eflags_LINK) $(fpu_lazy_eflags_OBJECTS) $(fpu_lazy_eflags_LDADD) $(LIBS)
+
+fxtract$(EXEEXT): $(fxtract_OBJECTS) $(fxtract_DEPENDENCIES) $(EXTRA_fxtract_DEPENDENCIES)
+ @rm -f fxtract$(EXEEXT)
+ $(AM_V_CCLD)$(fxtract_LINK) $(fxtract_OBJECTS) $(fxtract_LDADD) $(LIBS)
+
+getseg$(EXEEXT): $(getseg_OBJECTS) $(getseg_DEPENDENCIES) $(EXTRA_getseg_DEPENDENCIES)
+ @rm -f getseg$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(getseg_OBJECTS) $(getseg_LDADD) $(LIBS)
+
+incdec_alt$(EXEEXT): $(incdec_alt_OBJECTS) $(incdec_alt_DEPENDENCIES) $(EXTRA_incdec_alt_DEPENDENCIES)
+ @rm -f incdec_alt$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(incdec_alt_OBJECTS) $(incdec_alt_LDADD) $(LIBS)
+
+insn_basic$(EXEEXT): $(insn_basic_OBJECTS) $(insn_basic_DEPENDENCIES) $(EXTRA_insn_basic_DEPENDENCIES)
+ @rm -f insn_basic$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_basic_OBJECTS) $(insn_basic_LDADD) $(LIBS)
+
+insn_cmov$(EXEEXT): $(insn_cmov_OBJECTS) $(insn_cmov_DEPENDENCIES) $(EXTRA_insn_cmov_DEPENDENCIES)
+ @rm -f insn_cmov$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_cmov_OBJECTS) $(insn_cmov_LDADD) $(LIBS)
+
+insn_fpu$(EXEEXT): $(insn_fpu_OBJECTS) $(insn_fpu_DEPENDENCIES) $(EXTRA_insn_fpu_DEPENDENCIES)
+ @rm -f insn_fpu$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_fpu_OBJECTS) $(insn_fpu_LDADD) $(LIBS)
+
+insn_mmx$(EXEEXT): $(insn_mmx_OBJECTS) $(insn_mmx_DEPENDENCIES) $(EXTRA_insn_mmx_DEPENDENCIES)
+ @rm -f insn_mmx$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_mmx_OBJECTS) $(insn_mmx_LDADD) $(LIBS)
+
+insn_mmxext$(EXEEXT): $(insn_mmxext_OBJECTS) $(insn_mmxext_DEPENDENCIES) $(EXTRA_insn_mmxext_DEPENDENCIES)
+ @rm -f insn_mmxext$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_mmxext_OBJECTS) $(insn_mmxext_LDADD) $(LIBS)
+
+insn_sse$(EXEEXT): $(insn_sse_OBJECTS) $(insn_sse_DEPENDENCIES) $(EXTRA_insn_sse_DEPENDENCIES)
+ @rm -f insn_sse$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_sse_OBJECTS) $(insn_sse_LDADD) $(LIBS)
+
+insn_sse2$(EXEEXT): $(insn_sse2_OBJECTS) $(insn_sse2_DEPENDENCIES) $(EXTRA_insn_sse2_DEPENDENCIES)
+ @rm -f insn_sse2$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_sse2_OBJECTS) $(insn_sse2_LDADD) $(LIBS)
+
+insn_sse3$(EXEEXT): $(insn_sse3_OBJECTS) $(insn_sse3_DEPENDENCIES) $(EXTRA_insn_sse3_DEPENDENCIES)
+ @rm -f insn_sse3$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_sse3_OBJECTS) $(insn_sse3_LDADD) $(LIBS)
+
+insn_ssse3$(EXEEXT): $(insn_ssse3_OBJECTS) $(insn_ssse3_DEPENDENCIES) $(EXTRA_insn_ssse3_DEPENDENCIES)
+ @rm -f insn_ssse3$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(insn_ssse3_OBJECTS) $(insn_ssse3_LDADD) $(LIBS)
+
+int$(EXEEXT): $(int_OBJECTS) $(int_DEPENDENCIES) $(EXTRA_int_DEPENDENCIES)
+ @rm -f int$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(int_OBJECTS) $(int_LDADD) $(LIBS)
+
+jcxz$(EXEEXT): $(jcxz_OBJECTS) $(jcxz_DEPENDENCIES) $(EXTRA_jcxz_DEPENDENCIES)
+ @rm -f jcxz$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(jcxz_OBJECTS) $(jcxz_LDADD) $(LIBS)
+
+lahf$(EXEEXT): $(lahf_OBJECTS) $(lahf_DEPENDENCIES) $(EXTRA_lahf_DEPENDENCIES)
+ @rm -f lahf$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(lahf_OBJECTS) $(lahf_LDADD) $(LIBS)
+
+looper$(EXEEXT): $(looper_OBJECTS) $(looper_DEPENDENCIES) $(EXTRA_looper_DEPENDENCIES)
+ @rm -f looper$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(looper_OBJECTS) $(looper_LDADD) $(LIBS)
+
+lzcnt32$(EXEEXT): $(lzcnt32_OBJECTS) $(lzcnt32_DEPENDENCIES) $(EXTRA_lzcnt32_DEPENDENCIES)
+ @rm -f lzcnt32$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(lzcnt32_OBJECTS) $(lzcnt32_LDADD) $(LIBS)
+
+movbe$(EXEEXT): $(movbe_OBJECTS) $(movbe_DEPENDENCIES) $(EXTRA_movbe_DEPENDENCIES)
+ @rm -f movbe$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(movbe_OBJECTS) $(movbe_LDADD) $(LIBS)
+
+movx$(EXEEXT): $(movx_OBJECTS) $(movx_DEPENDENCIES) $(EXTRA_movx_DEPENDENCIES)
+ @rm -f movx$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(movx_OBJECTS) $(movx_LDADD) $(LIBS)
+
+pushpopseg$(EXEEXT): $(pushpopseg_OBJECTS) $(pushpopseg_DEPENDENCIES) $(EXTRA_pushpopseg_DEPENDENCIES)
+ @rm -f pushpopseg$(EXEEXT)
+ $(AM_V_CCLD)$(LINK) $(pushpopseg_OBJECTS) $(pushpopseg_LDADD) $(LIBS)
+
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+ for file in $$dist_files; do \
+ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+ if test -d $$d/$$file; then \
+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+ if test -d "$(distdir)/$$file"; then \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+ fi; \
+ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+ else \
+ test -f "$(distdir)/$$file" \
+ || cp -p $$d/$$file "$(distdir)/$$file" \
+ || exit 1; \
+ fi; \
+ done
+check-am: all-am
+ $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+ $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+ @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+ if test -z '$(STRIP)'; then \
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ install; \
+ else \
+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+ "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \
+ fi
+mostlyclean-generic:
+
+clean-generic:
+ -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)
+
+distclean-generic:
+ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+ @echo "This command is intended for maintainers to use"
+ @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+ distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+ -rm -rf ./$(DEPDIR)
+ -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS TAGS all all-am check check-am check-local clean \
+ clean-checkPROGRAMS clean-generic clean-local cscopelist-am \
+ ctags ctags-am distclean distclean-compile distclean-generic \
+ distclean-tags distdir dvi dvi-am html html-am info info-am \
+ install install-am install-data install-data-am install-dvi \
+ install-dvi-am install-exec install-exec-am install-html \
+ install-html-am install-info install-info-am install-man \
+ install-pdf install-pdf-am install-ps install-ps-am \
+ install-strip installcheck installcheck-am installdirs \
+ maintainer-clean maintainer-clean-generic mostlyclean \
+ mostlyclean-compile mostlyclean-generic pdf pdf-am ps ps-am \
+ tags tags-am uninstall uninstall-am
+
+.PRECIOUS: Makefile
+
+
+# This used to be required when Vex had a handwritten Makefile. It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'. This must be generated after the executable is
+# created, with 'dsymutil p'. We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain. Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+ for f in $(noinst_DSYMS); do \
+ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \
+ echo "dsymutil $$f"; \
+ dsymutil $$f; \
+ fi; \
+ done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_PROGRAMS) ; do \
+ rm -f $(inplacedir)/$$f; \
+ ln -f -s ../$(subdir)/$$f $(inplacedir); \
+ done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+ mkdir -p $(inplacedir); \
+ for f in $(noinst_DSYMS); do \
+ rm -f $(inplacedir)/$$f.dSYM; \
+ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install". It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_PROGRAMS); do \
+ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+ done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/.
+# It needs to be depended on by an 'uninstall-local' rule.
+uninstall-noinst_PROGRAMS:
+ for f in $(noinst_PROGRAMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \
+ done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories. XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+ $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+ for f in $(noinst_DSYMS); do \
+ cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+ done
+
+# Similar to uninstall-noinst_PROGRAMS.
+uninstall-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \
+ done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+ for f in $(noinst_DSYMS); do \
+ rm -rf $$f.dSYM; \
+ done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+.def.c: $(srcdir)/gen_insn_test.pl
+ $(PERL) $(srcdir)/gen_insn_test.pl < $< > $@
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
diff --git a/none/tests/x86/allexec.c b/none/tests/x86/allexec.c
deleted file mode 120000
index 6d6a9cf..0000000
--- a/none/tests/x86/allexec.c
+++ /dev/null
@@ -1 +0,0 @@
-../allexec.c
\ No newline at end of file
diff --git a/none/tests/allexec.c b/none/tests/x86/allexec.c
similarity index 100%
copy from none/tests/allexec.c
copy to none/tests/x86/allexec.c
diff --git a/none/tests/x86/insn_fpu.def b/none/tests/x86/insn_fpu.def
index c99815e..590f584 100644
--- a/none/tests/x86/insn_fpu.def
+++ b/none/tests/x86/insn_fpu.def
@@ -58,6 +58,18 @@
fiaddl st0.pd[-1234567.7654321] : m32.sd[87654321] => st0.pd[86419753.2345679]
fiaddl st0.pd[1234567.7654321] : m32.sd[-87654321] => st0.pd[-86419753.2345679]
fiaddl st0.pd[-1234567.7654321] : m32.sd[-87654321] => st0.pd[-88888888.7654321]
+fcoms st0.ps[1234.5678] : m32.ps[1234.5676] => st0.ps[1234.5678] fpusw[0x4700,0x0000]
+fcoms st0.ps[1234.5678] : m32.ps[1234.5679] => st0.ps[1234.5678] fpusw[0x4700,0x0100]
+fcoms st0.ps[1234.5678] : m32.ps[1234.5678] => st0.ps[1234.5678] fpusw[0x4700,0x4000]
+fcoml st0.pd[1234567.7654321] : m64.pd[1234567.7654320] => st0.pd[1234567.7654321] fpusw[0x4700,0x0000]
+fcoml st0.pd[1234567.7654321] : m64.pd[1234567.7654322] => st0.pd[1234567.7654321] fpusw[0x4700,0x0100]
+fcoml st0.pd[1234567.7654321] : m64.pd[1234567.7654321] => st0.pd[1234567.7654321] fpusw[0x4700,0x4000]
+fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5676] => st0.ps[8765.4321] fpusw[0x4700,0x0000]
+fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5679] => st0.ps[8765.4321] fpusw[0x4700,0x0100]
+fcomps st1.ps[8765.4321] st0.ps[1234.5678] : m32.ps[1234.5678] => st0.ps[8765.4321] fpusw[0x4700,0x4000]
+fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654320] => st0.pd[7654321.1234567] fpusw[0x4700,0x0000]
+fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654322] => st0.pd[7654321.1234567] fpusw[0x4700,0x0100]
+fcompl st1.pd[7654321.1234567] st0.pd[1234567.7654321] : m64.pd[1234567.7654321] => st0.pd[7654321.1234567] fpusw[0x4700,0x4000]
fcomi st2.ps[1234.5678] st0.ps[1234.5679] => st0.ps[1234.5678] st2.ps[1234.5679] eflags[0x45,0x00]
fcomi st2.ps[1234.5678] st0.ps[1234.5676] => st0.ps[1234.5678] st2.ps[1234.5676] eflags[0x45,0x01]
fcomi st2.ps[1234.5678] st0.ps[1234.5678] => st0.ps[1234.5678] st2.ps[1234.5678] eflags[0x45,0x40]
diff --git a/none/tests/x86/insn_fpu.stdout.exp b/none/tests/x86/insn_fpu.stdout.exp
index 2dbaa07..67128c1 100644
--- a/none/tests/x86/insn_fpu.stdout.exp
+++ b/none/tests/x86/insn_fpu.stdout.exp
@@ -58,6 +58,18 @@
fiaddl_6 ... ok
fiaddl_7 ... ok
fiaddl_8 ... ok
+fcoms_1 ... ok
+fcoms_2 ... ok
+fcoms_3 ... ok
+fcoml_1 ... ok
+fcoml_2 ... ok
+fcoml_3 ... ok
+fcomps_1 ... ok
+fcomps_2 ... ok
+fcomps_3 ... ok
+fcompl_1 ... ok
+fcompl_2 ... ok
+fcompl_3 ... ok
fcomi_1 ... ok
fcomi_2 ... ok
fcomi_3 ... ok