| ###aaa eflags[0x11,0x01] al.ub[0x1] ah.ub[0x0] : => al.ub[0x1] ah.ub[0x00] eflags[0x11,0x00] |
| ###aaa eflags[0x11,0x01] al.ub[0x9] ah.ub[0x0] : => al.ub[0x9] ah.ub[0x00] eflags[0x11,0x00] |
| ###aaa eflags[0x11,0x00] al.ub[0xa] ah.ub[0x0] : => al.ub[0x0] ah.ub[0x01] eflags[0x11,0x11] |
| ###aaa eflags[0x11,0x00] al.ub[0xf] ah.ub[0x0] : => al.ub[0x5] ah.ub[0x01] eflags[0x11,0x11] |
| ###aaa eflags[0x11,0x10] al.ub[0x1] ah.ub[0x0] : => al.ub[0x7] ah.ub[0x01] eflags[0x11,0x11] |
| ###aaa eflags[0x11,0x10] al.ub[0x9] ah.ub[0x0] : => al.ub[0xf] ah.ub[0x01] eflags[0x11,0x11] |
| ###aaa eflags[0x11,0x10] al.ub[0xa] ah.ub[0x0] : => al.ub[0x0] ah.ub[0x01] eflags[0x11,0x11] |
| ###aaa eflags[0x11,0x10] al.ub[0xf] ah.ub[0x0] : => al.ub[0x5] ah.ub[0x01] eflags[0x11,0x11] |
| ###aad al.ub[37] ah.ub[2] : => al.ub[57] ah.ub[0] |
| ###aad al.ub[73] ah.ub[2] : => al.ub[93] ah.ub[0] |
| ###aam al.ub[37] ah.ub[0] : => al.ub[7] ah.ub[3] |
| ###aam al.ub[73] ah.ub[0] : => al.ub[3] ah.ub[7] |
| ###aas eflags[0x11,0x01] al.ub[0x1] ah.ub[0x2] : => al.ub[0x1] ah.ub[0x02] eflags[0x11,0x00] |
| ###aas eflags[0x11,0x01] al.ub[0x9] ah.ub[0x2] : => al.ub[0x9] ah.ub[0x02] eflags[0x11,0x00] |
| ###aas eflags[0x11,0x00] al.ub[0xa] ah.ub[0x2] : => al.ub[0x4] ah.ub[0x01] eflags[0x11,0x11] |
| ###aas eflags[0x11,0x00] al.ub[0xf] ah.ub[0x2] : => al.ub[0x9] ah.ub[0x01] eflags[0x11,0x11] |
| ###aas eflags[0x11,0x10] al.ub[0x1] ah.ub[0x2] : => al.ub[0xb] ah.ub[0x00] eflags[0x11,0x11] |
| ###aas eflags[0x11,0x10] al.ub[0x9] ah.ub[0x2] : => al.ub[0x3] ah.ub[0x01] eflags[0x11,0x11] |
| ###aas eflags[0x11,0x10] al.ub[0xa] ah.ub[0x2] : => al.ub[0x4] ah.ub[0x01] eflags[0x11,0x11] |
| ###aas eflags[0x11,0x10] al.ub[0xf] ah.ub[0x2] : => al.ub[0x9] ah.ub[0x01] eflags[0x11,0x11] |
| ###adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46] |
| ###adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47] |
| adcb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46] |
| adcb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47] |
| adcb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46] |
| adcb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47] |
| adcb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[46] |
| adcb eflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[47] |
| adcb eflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[46] |
| adcb eflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[47] |
| ###adcb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[46] |
| ###adcb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[47] |
| adcw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468] |
| adcw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469] |
| ###adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912] |
| ###adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913] |
| adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912] |
| adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913] |
| adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912] |
| adcw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913] |
| adcw eflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[6912] |
| adcw eflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[6913] |
| adcw eflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[6912] |
| adcw eflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[6913] |
| adcw eflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[6912] |
| adcw eflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[6913] |
| adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333] |
| adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334] |
| ###adcl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999] |
| ###adcl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000] |
| adcl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[99999999] |
| adcl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[100000000] |
| adcl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999] |
| adcl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[100000000] |
| adcl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999] |
| adcl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[100000000] |
| adcl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999] |
| adcl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000] |
| adcl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999] |
| adcl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000] |
| addb imm8[12] al.ub[34] => 1.ub[46] |
| addb imm8[12] bl.ub[34] => 1.ub[46] |
| addb imm8[12] m8.ub[34] => 1.ub[46] |
| addb r8.ub[12] r8.ub[34] => 1.ub[46] |
| addb r8.ub[12] m8.ub[34] => 1.ub[46] |
| addb m8.ub[12] r8.ub[34] => 1.ub[46] |
| addw imm8[12] r16.uw[3456] => 1.uw[3468] |
| addw imm16[1234] ax.uw[5678] => 1.uw[6912] |
| addw imm16[1234] bx.uw[5678] => 1.uw[6912] |
| addw imm16[1234] m16.uw[5678] => 1.uw[6912] |
| addw r16.uw[1234] r16.uw[5678] => 1.uw[6912] |
| addw r16.uw[1234] m16.uw[5678] => 1.uw[6912] |
| addw m16.uw[1234] r16.uw[5678] => 1.uw[6912] |
| addl imm8[12] r32.ud[87654321] => 1.ud[87654333] |
| addl imm32[12345678] eax.ud[87654321] => 1.ud[99999999] |
| addl imm32[12345678] ebx.ud[87654321] => 1.ud[99999999] |
| addl imm32[12345678] m32.ud[87654321] => 1.ud[99999999] |
| addl r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999] |
| addl r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999] |
| addl m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999] |
| andb imm8[0x34] al.ub[0x56] => 1.ub[0x14] |
| andb imm8[0x34] bl.ub[0x56] => 1.ub[0x14] |
| andb imm8[0x34] m8.ub[0x56] => 1.ub[0x14] |
| andb r8.ub[0x34] r8.ub[0x56] => 1.ub[0x14] |
| andb r8.ub[0x34] m8.ub[0x56] => 1.ub[0x14] |
| andb m8.ub[0x34] r8.ub[0x56] => 1.ub[0x14] |
| andw imm8[0x31] r16.uw[0x1234] => 1.uw[0x0030] |
| andw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x0230] |
| andw imm16[0x4231] bx.uw[0x1234] => 1.uw[0x0230] |
| andw imm16[0x4231] m16.uw[0x1234] => 1.uw[0x0230] |
| andw r16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x0230] |
| andw r16.uw[0x4231] m16.uw[0x1234] => 1.uw[0x0230] |
| andw m16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x0230] |
| andl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x00000030] |
| andl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x02005430] |
| andl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x02005430] |
| andl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x02005430] |
| andl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x02005430] |
| andl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x02005430] |
| andl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x02005430] |
| bsfw r16.uw[0x2468] r16.uw[0] => 1.uw[3] |
| bsfw m16.uw[0x8642] r16.uw[0] => 1.uw[1] |
| bsfl r32.ud[0x13572468] r32.ud[0] => 1.ud[3] |
| bsfl m32.ud[0x75318642] r32.ud[0] => 1.ud[1] |
| bsrw r16.uw[0x2468] r16.uw[0] => 1.uw[13] |
| bsrw m16.uw[0x8642] r16.uw[0] => 1.uw[15] |
| bsrl r32.ud[0x13572468] r32.ud[0] => 1.ud[28] |
| bsrl m32.ud[0x75318642] r32.ud[0] => 1.ud[30] |
| bswapl r32.ud[0x12345678] => 0.ud[0x78563412] |
| ###btw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] |
| ###btw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] |
| ###btw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] |
| ###btw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] |
| btw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] |
| btw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] |
| btw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] |
| btw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] |
| ###btl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] |
| ###btl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] |
| ###btl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] |
| ###btl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] |
| btl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] |
| btl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] |
| btl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] |
| btl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] |
| ###btcw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] |
| ###btcw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] |
| ###btcw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] |
| ###btcw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] |
| btcw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] |
| btcw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] |
| btcw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] |
| btcw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] |
| ###btcl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] |
| ###btcl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] |
| ###btcl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] |
| ###btcl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] |
| btcl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] |
| btcl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] |
| btcl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] |
| btcl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] |
| ###btrw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] |
| ###btrw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] |
| ###btrw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] |
| ###btrw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] |
| btrw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] |
| btrw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] |
| btrw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001] |
| btrw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000] |
| ###btrl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] |
| ###btrl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] |
| ###btrl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] |
| ###btrl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] |
| btrl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] |
| btrl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] |
| btrl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001] |
| btrl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000] |
| ###btsw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] |
| ###btsw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] |
| ###btsw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] |
| ###btsw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] |
| btsw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] |
| btsw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] |
| btsw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001] |
| btsw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000] |
| ###btsl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] |
| ###btsl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] |
| ###btsl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] |
| ###btsl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] |
| btsl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] |
| btsl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] |
| btsl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001] |
| btsl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000] |
| cbw al.sb[123] : => ax.sw[123] |
| cbw al.sb[-123] : => ax.sw[-123] |
| cdq eax.ud[0x12345678] : => edx.ud[0x00000000] eax.ud[0x12345678] |
| cdq eax.ud[0xfedcba98] : => edx.ud[0xffffffff] eax.ud[0xfedcba98] |
| ###clc eflags[0x001,0x000] : => eflags[0x001,0x000] |
| ###clc eflags[0x001,0x001] : => eflags[0x001,0x000] |
| cld eflags[0x400,0x000] : => eflags[0x400,0x000] |
| cld eflags[0x400,0x400] : => eflags[0x400,0x000] |
| ###cmc eflags[0x001,0x000] : => eflags[0x001,0x001] |
| ###cmc eflags[0x001,0x001] : => eflags[0x001,0x000] |
| cmpb imm8[3] al.ub[2] => eflags[0x010,0x010] |
| cmpb imm8[2] al.ub[3] => eflags[0x010,0x000] |
| cmpb imm8[12] al.ub[12] => eflags[0x044,0x044] |
| cmpb imm8[12] al.ub[34] => eflags[0x044,0x000] |
| cmpb imm8[34] al.ub[12] => eflags[0x081,0x081] |
| cmpb imm8[12] al.ub[34] => eflags[0x081,0x000] |
| cmpb imm8[100] al.sb[-100] => eflags[0x800,0x800] |
| cmpb imm8[50] al.sb[-50] => eflags[0x800,0x000] |
| cmpb imm8[-50] al.sb[50] => eflags[0x800,0x000] |
| cmpb imm8[-100] al.sb[100] => eflags[0x800,0x800] |
| cmpb imm8[3] r8.ub[2] => eflags[0x010,0x010] |
| cmpb imm8[2] r8.ub[3] => eflags[0x010,0x000] |
| cmpb imm8[12] r8.ub[12] => eflags[0x044,0x044] |
| cmpb imm8[12] r8.ub[34] => eflags[0x044,0x000] |
| cmpb imm8[34] r8.ub[12] => eflags[0x081,0x081] |
| cmpb imm8[12] r8.ub[34] => eflags[0x081,0x000] |
| cmpb imm8[100] r8.sb[-100] => eflags[0x800,0x800] |
| cmpb imm8[50] r8.sb[-50] => eflags[0x800,0x000] |
| cmpb imm8[-50] r8.sb[50] => eflags[0x800,0x000] |
| cmpb imm8[-100] r8.sb[100] => eflags[0x800,0x800] |
| cmpb imm8[3] m8.ub[2] => eflags[0x010,0x010] |
| cmpb imm8[2] m8.ub[3] => eflags[0x010,0x000] |
| cmpb imm8[12] m8.ub[12] => eflags[0x044,0x044] |
| cmpb imm8[12] m8.ub[34] => eflags[0x044,0x000] |
| cmpb imm8[34] m8.ub[12] => eflags[0x081,0x081] |
| cmpb imm8[12] m8.ub[34] => eflags[0x081,0x000] |
| cmpb imm8[100] m8.sb[-100] => eflags[0x800,0x800] |
| cmpb imm8[50] m8.sb[-50] => eflags[0x800,0x000] |
| cmpb imm8[-50] m8.sb[50] => eflags[0x800,0x000] |
| cmpb imm8[-100] m8.sb[100] => eflags[0x800,0x800] |
| cmpb r8.ub[3] r8.ub[2] => eflags[0x010,0x010] |
| cmpb r8.ub[2] r8.ub[3] => eflags[0x010,0x000] |
| cmpb r8.ub[12] r8.ub[12] => eflags[0x044,0x044] |
| cmpb r8.ub[12] r8.ub[34] => eflags[0x044,0x000] |
| cmpb r8.ub[34] r8.ub[12] => eflags[0x081,0x081] |
| cmpb r8.ub[12] r8.ub[34] => eflags[0x081,0x000] |
| cmpb r8.ub[100] r8.sb[-100] => eflags[0x800,0x800] |
| cmpb r8.ub[50] r8.sb[-50] => eflags[0x800,0x000] |
| cmpb r8.sb[-50] r8.sb[50] => eflags[0x800,0x000] |
| cmpb r8.sb[-100] r8.sb[100] => eflags[0x800,0x800] |
| cmpb r8.ub[3] m8.ub[2] => eflags[0x010,0x010] |
| cmpb r8.ub[2] m8.ub[3] => eflags[0x010,0x000] |
| cmpb r8.ub[12] m8.ub[12] => eflags[0x044,0x044] |
| cmpb r8.ub[12] m8.ub[34] => eflags[0x044,0x000] |
| cmpb r8.ub[34] m8.ub[12] => eflags[0x081,0x081] |
| cmpb r8.ub[12] m8.ub[34] => eflags[0x081,0x000] |
| cmpb r8.ub[100] m8.sb[-100] => eflags[0x800,0x800] |
| cmpb r8.ub[50] m8.sb[-50] => eflags[0x800,0x000] |
| cmpb r8.sb[-50] m8.sb[50] => eflags[0x800,0x000] |
| cmpb r8.sb[-100] m8.sb[100] => eflags[0x800,0x800] |
| cmpb m8.ub[3] r8.ub[2] => eflags[0x010,0x010] |
| cmpb m8.ub[2] r8.ub[3] => eflags[0x010,0x000] |
| cmpb m8.ub[12] r8.ub[12] => eflags[0x044,0x044] |
| cmpb m8.ub[12] r8.ub[34] => eflags[0x044,0x000] |
| cmpb m8.ub[34] r8.ub[12] => eflags[0x081,0x081] |
| cmpb m8.ub[12] r8.ub[34] => eflags[0x081,0x000] |
| cmpb m8.ub[100] r8.sb[-100] => eflags[0x800,0x800] |
| cmpb m8.ub[50] r8.sb[-50] => eflags[0x800,0x000] |
| cmpb m8.sb[-50] r8.sb[50] => eflags[0x800,0x000] |
| cmpb m8.sb[-100] r8.sb[100] => eflags[0x800,0x800] |
| cmpw imm8[3] r16.uw[2] => eflags[0x010,0x010] |
| cmpw imm8[2] r16.uw[3] => eflags[0x010,0x000] |
| cmpw imm8[12] r16.uw[12] => eflags[0x044,0x044] |
| cmpw imm8[12] r16.uw[34] => eflags[0x044,0x000] |
| cmpw imm8[34] r16.uw[12] => eflags[0x081,0x081] |
| cmpw imm8[12] r16.uw[34] => eflags[0x081,0x000] |
| cmpw imm8[100] r16.sw[-32700] => eflags[0x800,0x800] |
| cmpw imm8[50] r16.sw[-50] => eflags[0x800,0x000] |
| cmpw imm8[-50] r16.sw[50] => eflags[0x800,0x000] |
| cmpw imm8[-100] r16.sw[32700] => eflags[0x800,0x800] |
| cmpw imm8[3] m16.uw[2] => eflags[0x010,0x010] |
| cmpw imm8[2] m16.uw[3] => eflags[0x010,0x000] |
| cmpw imm8[12] m16.uw[12] => eflags[0x044,0x044] |
| cmpw imm8[12] m16.uw[34] => eflags[0x044,0x000] |
| cmpw imm8[34] m16.uw[12] => eflags[0x081,0x081] |
| cmpw imm8[12] m16.uw[34] => eflags[0x081,0x000] |
| cmpw imm8[100] m16.sw[-32700] => eflags[0x800,0x800] |
| cmpw imm8[50] m16.sw[-50] => eflags[0x800,0x000] |
| cmpw imm8[-50] m16.sw[50] => eflags[0x800,0x000] |
| cmpw imm8[-100] m16.sw[32700] => eflags[0x800,0x800] |
| cmpw imm16[3] ax.uw[2] => eflags[0x010,0x010] |
| cmpw imm16[2] ax.uw[3] => eflags[0x010,0x000] |
| cmpw imm16[12] ax.uw[12] => eflags[0x044,0x044] |
| cmpw imm16[12] ax.uw[34] => eflags[0x044,0x000] |
| cmpw imm16[34] ax.uw[12] => eflags[0x081,0x081] |
| cmpw imm16[12] ax.uw[34] => eflags[0x081,0x000] |
| cmpw imm16[100] ax.sw[-32700] => eflags[0x800,0x800] |
| cmpw imm16[50] ax.sw[-50] => eflags[0x800,0x000] |
| cmpw imm16[-50] ax.sw[50] => eflags[0x800,0x000] |
| cmpw imm16[-100] ax.sw[32700] => eflags[0x800,0x800] |
| cmpw imm16[3] r16.uw[2] => eflags[0x010,0x010] |
| cmpw imm16[2] r16.uw[3] => eflags[0x010,0x000] |
| cmpw imm16[12] r16.uw[12] => eflags[0x044,0x044] |
| cmpw imm16[12] r16.uw[34] => eflags[0x044,0x000] |
| cmpw imm16[34] r16.uw[12] => eflags[0x081,0x081] |
| cmpw imm16[12] r16.uw[34] => eflags[0x081,0x000] |
| cmpw imm16[100] r16.sw[-32700] => eflags[0x800,0x800] |
| cmpw imm16[50] r16.sw[-50] => eflags[0x800,0x000] |
| cmpw imm16[-50] r16.sw[50] => eflags[0x800,0x000] |
| cmpw imm16[-100] r16.sw[32700] => eflags[0x800,0x800] |
| cmpw imm16[3] m16.uw[2] => eflags[0x010,0x010] |
| cmpw imm16[2] m16.uw[3] => eflags[0x010,0x000] |
| cmpw imm16[12] m16.uw[12] => eflags[0x044,0x044] |
| cmpw imm16[12] m16.uw[34] => eflags[0x044,0x000] |
| cmpw imm16[34] m16.uw[12] => eflags[0x081,0x081] |
| cmpw imm16[12] m16.uw[34] => eflags[0x081,0x000] |
| cmpw imm16[100] m16.sw[-32700] => eflags[0x800,0x800] |
| cmpw imm16[50] m16.sw[-50] => eflags[0x800,0x000] |
| cmpw imm16[-50] m16.sw[50] => eflags[0x800,0x000] |
| cmpw imm16[-100] m16.sw[32700] => eflags[0x800,0x800] |
| cmpw r16.uw[3] r16.uw[2] => eflags[0x010,0x010] |
| cmpw r16.uw[2] r16.uw[3] => eflags[0x010,0x000] |
| cmpw r16.uw[12] r16.uw[12] => eflags[0x044,0x044] |
| cmpw r16.uw[12] r16.uw[34] => eflags[0x044,0x000] |
| cmpw r16.uw[34] r16.uw[12] => eflags[0x081,0x081] |
| cmpw r16.uw[12] r16.uw[34] => eflags[0x081,0x000] |
| cmpw r16.uw[100] r16.sw[-32700] => eflags[0x800,0x800] |
| cmpw r16.uw[50] r16.sw[-50] => eflags[0x800,0x000] |
| cmpw r16.sw[-50] r16.sw[50] => eflags[0x800,0x000] |
| cmpw r16.sw[-100] r16.sw[32700] => eflags[0x800,0x800] |
| cmpw r16.uw[3] m16.uw[2] => eflags[0x010,0x010] |
| cmpw r16.uw[2] m16.uw[3] => eflags[0x010,0x000] |
| cmpw r16.uw[12] m16.uw[12] => eflags[0x044,0x044] |
| cmpw r16.uw[12] m16.uw[34] => eflags[0x044,0x000] |
| cmpw r16.uw[34] m16.uw[12] => eflags[0x081,0x081] |
| cmpw r16.uw[12] m16.uw[34] => eflags[0x081,0x000] |
| cmpw r16.uw[100] m16.sw[-32700] => eflags[0x800,0x800] |
| cmpw r16.uw[50] m16.sw[-50] => eflags[0x800,0x000] |
| cmpw r16.sw[-50] m16.sw[50] => eflags[0x800,0x000] |
| cmpw r16.sw[-100] m16.sw[32700] => eflags[0x800,0x800] |
| cmpw m16.uw[3] r16.uw[2] => eflags[0x010,0x010] |
| cmpw m16.uw[2] r16.uw[3] => eflags[0x010,0x000] |
| cmpw m16.uw[12] r16.uw[12] => eflags[0x044,0x044] |
| cmpw m16.uw[12] r16.uw[34] => eflags[0x044,0x000] |
| cmpw m16.uw[34] r16.uw[12] => eflags[0x081,0x081] |
| cmpw m16.uw[12] r16.uw[34] => eflags[0x081,0x000] |
| cmpw m16.uw[100] r16.sw[-32700] => eflags[0x800,0x800] |
| cmpw m16.uw[50] r16.sw[-50] => eflags[0x800,0x000] |
| cmpw m16.sw[-50] r16.sw[50] => eflags[0x800,0x000] |
| cmpw m16.sw[-100] r16.sw[32700] => eflags[0x800,0x800] |
| cmpl imm8[3] r32.ud[2] => eflags[0x010,0x010] |
| cmpl imm8[2] r32.ud[3] => eflags[0x010,0x000] |
| cmpl imm8[12] r32.ud[12] => eflags[0x044,0x044] |
| cmpl imm8[12] r32.ud[34] => eflags[0x044,0x000] |
| cmpl imm8[34] r32.ud[12] => eflags[0x081,0x081] |
| cmpl imm8[12] r32.ud[34] => eflags[0x081,0x000] |
| cmpl imm8[100] r32.sd[-2147483600] => eflags[0x800,0x800] |
| cmpl imm8[50] r32.sd[-50] => eflags[0x800,0x000] |
| cmpl imm8[-50] r32.sd[50] => eflags[0x800,0x000] |
| cmpl imm8[-100] r32.sd[2147483600] => eflags[0x800,0x800] |
| cmpl imm8[3] m32.ud[2] => eflags[0x010,0x010] |
| cmpl imm8[2] m32.ud[3] => eflags[0x010,0x000] |
| cmpl imm8[12] m32.ud[12] => eflags[0x044,0x044] |
| cmpl imm8[12] m32.ud[34] => eflags[0x044,0x000] |
| cmpl imm8[34] m32.ud[12] => eflags[0x081,0x081] |
| cmpl imm8[12] m32.ud[34] => eflags[0x081,0x000] |
| cmpl imm8[100] m32.sd[-2147483600] => eflags[0x800,0x800] |
| cmpl imm8[50] m32.sd[-50] => eflags[0x800,0x000] |
| cmpl imm8[-50] m32.sd[50] => eflags[0x800,0x000] |
| cmpl imm8[-100] m32.sd[2147483600] => eflags[0x800,0x800] |
| cmpl imm32[3] eax.ud[2] => eflags[0x010,0x010] |
| cmpl imm32[2] eax.ud[3] => eflags[0x010,0x000] |
| cmpl imm32[12] eax.ud[12] => eflags[0x044,0x044] |
| cmpl imm32[12] eax.ud[34] => eflags[0x044,0x000] |
| cmpl imm32[34] eax.ud[12] => eflags[0x081,0x081] |
| cmpl imm32[12] eax.ud[34] => eflags[0x081,0x000] |
| cmpl imm32[100] eax.sd[-2147483600] => eflags[0x800,0x800] |
| cmpl imm32[50] eax.sd[-50] => eflags[0x800,0x000] |
| cmpl imm32[-50] eax.sd[50] => eflags[0x800,0x000] |
| cmpl imm32[-100] eax.sd[2147483600] => eflags[0x800,0x800] |
| cmpl imm32[3] r32.ud[2] => eflags[0x010,0x010] |
| cmpl imm32[2] r32.ud[3] => eflags[0x010,0x000] |
| cmpl imm32[12] r32.ud[12] => eflags[0x044,0x044] |
| cmpl imm32[12] r32.ud[34] => eflags[0x044,0x000] |
| cmpl imm32[34] r32.ud[12] => eflags[0x081,0x081] |
| cmpl imm32[12] r32.ud[34] => eflags[0x081,0x000] |
| cmpl imm32[100] r32.sd[-2147483600] => eflags[0x800,0x800] |
| cmpl imm32[50] r32.sd[-50] => eflags[0x800,0x000] |
| cmpl imm32[-50] r32.sd[50] => eflags[0x800,0x000] |
| cmpl imm32[-100] r32.sd[2147483600] => eflags[0x800,0x800] |
| cmpl imm32[3] m32.ud[2] => eflags[0x010,0x010] |
| cmpl imm32[2] m32.ud[3] => eflags[0x010,0x000] |
| cmpl imm32[12] m32.ud[12] => eflags[0x044,0x044] |
| cmpl imm32[12] m32.ud[34] => eflags[0x044,0x000] |
| cmpl imm32[34] m32.ud[12] => eflags[0x081,0x081] |
| cmpl imm32[12] m32.ud[34] => eflags[0x081,0x000] |
| cmpl imm32[100] m32.sd[-2147483600] => eflags[0x800,0x800] |
| cmpl imm32[50] m32.sd[-50] => eflags[0x800,0x000] |
| cmpl imm32[-50] m32.sd[50] => eflags[0x800,0x000] |
| cmpl imm32[-100] m32.sd[2147483600] => eflags[0x800,0x800] |
| cmpl r32.ud[3] r32.ud[2] => eflags[0x010,0x010] |
| cmpl r32.ud[2] r32.ud[3] => eflags[0x010,0x000] |
| cmpl r32.ud[12] r32.ud[12] => eflags[0x044,0x044] |
| cmpl r32.ud[12] r32.ud[34] => eflags[0x044,0x000] |
| cmpl r32.ud[34] r32.ud[12] => eflags[0x081,0x081] |
| cmpl r32.ud[12] r32.ud[34] => eflags[0x081,0x000] |
| cmpl r32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800] |
| cmpl r32.ud[50] r32.sd[-50] => eflags[0x800,0x000] |
| cmpl r32.sd[-50] r32.sd[50] => eflags[0x800,0x000] |
| cmpl r32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800] |
| cmpl r32.ud[3] m32.ud[2] => eflags[0x010,0x010] |
| cmpl r32.ud[2] m32.ud[3] => eflags[0x010,0x000] |
| cmpl r32.ud[12] m32.ud[12] => eflags[0x044,0x044] |
| cmpl r32.ud[12] m32.ud[34] => eflags[0x044,0x000] |
| cmpl r32.ud[34] m32.ud[12] => eflags[0x081,0x081] |
| cmpl r32.ud[12] m32.ud[34] => eflags[0x081,0x000] |
| cmpl r32.ud[100] m32.sd[-2147483600] => eflags[0x800,0x800] |
| cmpl r32.ud[50] m32.sd[-50] => eflags[0x800,0x000] |
| cmpl r32.sd[-50] m32.sd[50] => eflags[0x800,0x000] |
| cmpl r32.sd[-100] m32.sd[2147483600] => eflags[0x800,0x800] |
| cmpl m32.ud[3] r32.ud[2] => eflags[0x010,0x010] |
| cmpl m32.ud[2] r32.ud[3] => eflags[0x010,0x000] |
| cmpl m32.ud[12] r32.ud[12] => eflags[0x044,0x044] |
| cmpl m32.ud[12] r32.ud[34] => eflags[0x044,0x000] |
| cmpl m32.ud[34] r32.ud[12] => eflags[0x081,0x081] |
| cmpl m32.ud[12] r32.ud[34] => eflags[0x081,0x000] |
| cmpl m32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800] |
| cmpl m32.ud[50] r32.sd[-50] => eflags[0x800,0x000] |
| cmpl m32.sd[-50] r32.sd[50] => eflags[0x800,0x000] |
| cmpl m32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800] |
| cmpxchgb eflags[0x40,0x00] ax.uw[12] : r8.ub[56] r8.ub[12] => eflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56] |
| cmpxchgb eflags[0x40,0x40] al.ub[12] : r8.ub[56] r8.ub[34] => eflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34] |
| cmpxchgb eflags[0x40,0x00] al.ub[12] : r8.ub[56] m8.ub[12] => eflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56] |
| cmpxchgb eflags[0x40,0x40] al.ub[12] : r8.ub[56] m8.ub[34] => eflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34] |
| cmpxchgw eflags[0x40,0x00] ax.uw[123] : r16.uw[567] r16.uw[123] => eflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567] |
| cmpxchgw eflags[0x40,0x40] ax.uw[123] : r16.uw[567] r16.uw[345] => eflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345] |
| cmpxchgw eflags[0x40,0x00] ax.uw[123] : r16.uw[567] m16.uw[123] => eflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567] |
| cmpxchgw eflags[0x40,0x40] ax.uw[123] : r16.uw[567] m16.uw[345] => eflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345] |
| cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] r32.ud[1234] => eflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678] |
| cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] r32.ud[3456] => eflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456] |
| cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] m32.ud[1234] => eflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678] |
| cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] m32.ud[3456] => eflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456] |
| cwd ax.uw[0x1234] : => dx.uw[0x0000] ax.uw[0x1234] |
| cwd ax.uw[0xfedc] : => dx.uw[0xffff] ax.uw[0xfedc] |
| cwde ax.sw[12345] : => eax.sd[12345] |
| cwde ax.sw[-12345] : => eax.sd[-12345] |
| ###daa eflags[0x8d5,0x880] al.ub[0xae] : => al.ub[0x14] eflags[0xd5,0x15] |
| ###daa eflags[0x8d5,0x880] al.ub[0x2e] : => al.ub[0x34] eflags[0xd5,0x10] |
| ###das eflags[0x8d5,0x895] al.ub[0xee] : => al.ub[0x88] eflags[0xd5,0x95] |
| decb r8.ub[123] => 0.ub[122] |
| decb m8.ub[123] => 0.ub[122] |
| decw r16.uw[12345] => 0.uw[12344] |
| decw m16.uw[12345] => 0.uw[12344] |
| decl r32.ud[12345678] => 0.ud[12345677] |
| decl m32.ud[12345678] => 0.ud[12345677] |
| divb ax.uw[30276] : r8.ub[123] => al.ub[246] ah.ub[18] |
| divb ax.uw[30276] : m8.ub[123] => al.ub[246] ah.ub[18] |
| divw dx.uw[464] ax.uw[58794] : r16.uw[12345] => ax.uw[2468] dx.uw[38] |
| divw dx.uw[464] ax.uw[58794] : m16.uw[12345] => ax.uw[2468] dx.uw[38] |
| divl edx.ud[251958] eax.ud[673192206] : r32.ud[87654321] => eax.ud[12345678] edx.ud[20783136] |
| divl edx.ud[251958] eax.ud[673192206] : m32.ud[87654321] => eax.ud[12345678] edx.ud[20783136] |
| idivb ax.sw[-15157] : r8.sb[123] => al.sb[-123] ah.sb[-28] |
| idivb ax.sw[15157] : m8.sb[-123] => al.sb[-123] ah.sb[28] |
| idivw dx.sw[-464] ax.sw[-23456] : r16.sw[12345] => ax.sw[-2459] dx.sw[-10269] |
| idivw dx.sw[464] ax.sw[23456] : m16.sw[-12345] => ax.sw[-2465] dx.sw[1735] |
| idivl edx.sd[-251959] eax.sd[-673192206] : r32.sd[87654321] => eax.sd[-12345678] edx.sd[-20783136] |
| idivl edx.sd[251958] eax.sd[673192206] : m32.sd[-87654321] => eax.sd[-12345678] edx.sd[20783136] |
| imulb al.sb[123] : r8.sb[-123] => ax.sw[-15129] |
| imulb al.sb[-123] : m8.sb[123] => ax.sw[-15129] |
| imulw ax.sw[-12345] : r16.sw[12345] => dx.sw[-2326] ax.sw[-27825] |
| imulw ax.sw[12345] : m16.sw[-12345] => dx.sw[-2326] ax.sw[-27825] |
| imull eax.sd[-12345678] : r32.sd[12345678] => edx.sd[-35488] eax.sd[-260846532] |
| imull eax.sd[12345678] : m32.sd[-12345678] => edx.sd[-35488] eax.sd[-260846532] |
| imulw imm8[123] r16.uw[456] => 1.uw[56088] |
| imulw imm8[123] r16.uw[456] r16.uw[0] => 2.uw[56088] |
| imulw imm8[123] m16.uw[456] r16.uw[0] => 2.uw[56088] |
| imulw imm16[123] r16.uw[456] => 1.uw[56088] |
| imulw imm16[123] r16.uw[456] r16.uw[0] => 2.uw[56088] |
| imulw imm16[123] m16.uw[456] r16.uw[0] => 2.uw[56088] |
| imulw r16.uw[123] r16.uw[456] => 1.uw[56088] |
| imulw m16.uw[123] r16.uw[456] => 1.uw[56088] |
| imull imm8[123] r32.ud[67890] => 1.ud[8350470] |
| imull imm8[123] r32.ud[67890] r32.ud[0] => 2.ud[8350470] |
| imull imm8[123] m32.ud[67890] r32.ud[0] => 2.ud[8350470] |
| imull imm32[12345] r32.ud[67890] => 1.ud[838102050] |
| imull imm32[12345] r32.ud[67890] r32.ud[0] => 2.ud[838102050] |
| imull imm32[12345] m32.ud[67890] r32.ud[0] => 2.ud[838102050] |
| imull r32.ud[12345] r32.ud[67890] => 1.ud[838102050] |
| imull m32.ud[12345] r32.ud[67890] => 1.ud[838102050] |
| incb r8.ub[123] => 0.ub[124] |
| incb m8.ub[123] => 0.ub[124] |
| incw r16.uw[12345] => 0.uw[12346] |
| incw m16.uw[12345] => 0.uw[12346] |
| incl r32.ud[12345678] => 0.ud[12345679] |
| incl m32.ud[12345678] => 0.ud[12345679] |
| ###lahf eflags[0xff,0xfd] ah.ub[0x28] : => ah.ub[0xd7] |
| ###lahf eflags[0xff,0x28] ah.ub[0xfd] : => ah.ub[0x02] |
| movb imm8[123] r8.ub[0] => 1.ub[123] |
| movb imm8[123] m8.ub[0] => 1.ub[123] |
| movb r8.ub[123] r8.ub[0] => 1.ub[123] |
| movb r8.ub[123] m8.ub[0] => 1.ub[123] |
| movb m8.ub[123] r8.ub[0] => 1.ub[123] |
| movw imm16[12345] r16.uw[0] => 1.uw[12345] |
| movw imm16[12345] m16.uw[0] => 1.uw[12345] |
| movw r16.uw[12345] r16.uw[0] => 1.uw[12345] |
| movw r16.uw[12345] m16.uw[0] => 1.uw[12345] |
| movw m16.uw[12345] r16.uw[0] => 1.uw[12345] |
| movl imm32[12345678] r32.ud[0] => 1.ud[12345678] |
| movl imm32[12345678] m32.ud[0] => 1.ud[12345678] |
| movl r32.ud[12345678] r32.ud[0] => 1.ud[12345678] |
| movl r32.ud[12345678] m32.ud[0] => 1.ud[12345678] |
| movl m32.ud[12345678] r32.ud[0] => 1.ud[12345678] |
| movsbw r8.sb[123] r16.sw[0] => 1.sw[123] |
| movsbw m8.sb[-123] r16.sw[0] => 1.sw[-123] |
| movsbl r8.sb[123] r32.sd[0] => 1.sd[123] |
| movsbl m8.sb[-123] r32.sd[0] => 1.sd[-123] |
| movswl r16.sw[12345] r32.sd[0] => 1.sd[12345] |
| movswl m16.sw[-12345] r32.sd[0] => 1.sd[-12345] |
| movzbw r8.ub[123] r16.uw[0] => 1.uw[123] |
| movzbw m8.ub[246] r16.uw[0] => 1.uw[246] |
| movzbl r8.ub[123] r32.ud[0] => 1.ud[123] |
| movzbl m8.ub[246] r32.ud[0] => 1.ud[246] |
| movzwl r16.uw[12345] r32.ud[0] => 1.ud[12345] |
| movzwl m16.uw[49380] r32.ud[0] => 1.ud[49380] |
| mulb al.ub[123] : r8.ub[123] => ax.uw[15129] |
| mulb al.ub[123] : m8.ub[123] => ax.uw[15129] |
| mulw ax.uw[12345] : r16.uw[12345] => dx.uw[2325] ax.uw[27825] |
| mulw ax.uw[12345] : m16.uw[12345] => dx.uw[2325] ax.uw[27825] |
| mull eax.ud[12345678] : r32.ud[12345678] => edx.ud[35487] eax.ud[260846532] |
| mull eax.ud[12345678] : m32.ud[12345678] => edx.ud[35487] eax.ud[260846532] |
| negb r8.sb[123] => 0.sb[-123] |
| negb m8.sb[-123] => 0.sb[123] |
| negw r16.sw[12345] => 0.sw[-12345] |
| negw m16.sw[-12345] => 0.sw[12345] |
| negl r32.sd[12345678] => 0.sd[-12345678] |
| negl m32.sd[-12345678] => 0.sd[12345678] |
| notb r8.ub[0xca] => 0.ub[0x35] |
| notb m8.ub[0xca] => 0.ub[0x35] |
| notw r16.uw[0xf0ca] => 0.uw[0x0f35] |
| notw m16.uw[0xf0ca] => 0.uw[0x0f35] |
| notl r32.ud[0xff00f0ca] => 0.ud[0x00ff0f35] |
| notl m32.ud[0xff00f0ca] => 0.ud[0x00ff0f35] |
| orb imm8[0x34] al.ub[0x56] => 1.ub[0x76] |
| orb imm8[0x34] bl.ub[0x56] => 1.ub[0x76] |
| orb imm8[0x34] m8.ub[0x56] => 1.ub[0x76] |
| orb r8.ub[0x34] r8.ub[0x56] => 1.ub[0x76] |
| orb r8.ub[0x34] m8.ub[0x56] => 1.ub[0x76] |
| orb m8.ub[0x34] r8.ub[0x56] => 1.ub[0x76] |
| orw imm8[0x31] r16.uw[0x1234] => 1.uw[0x1235] |
| orw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x5235] |
| orw imm16[0x4231] bx.uw[0x1234] => 1.uw[0x5235] |
| orw imm16[0x4231] m16.uw[0x1234] => 1.uw[0x5235] |
| orw r16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x5235] |
| orw r16.uw[0x4231] m16.uw[0x1234] => 1.uw[0x5235] |
| orw m16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x5235] |
| orl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x12345679] |
| orl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x96767779] |
| orl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x96767779] |
| orl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x96767779] |
| orl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x96767779] |
| orl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x96767779] |
| orl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x96767779] |
| ###rclb eflags[0x1,0x0] : r8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1] |
| ###rclb eflags[0x1,0x0] : m8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1] |
| ###rclb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] |
| ###rclb eflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] |
| ###rclb eflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] |
| ###rclb eflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1] |
| ###rclw eflags[0x1,0x0] : r16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1] |
| ###rclw eflags[0x1,0x0] : m16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1] |
| ###rclw eflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] |
| ###rclw eflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] |
| ###rclw eflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] |
| ###rclw eflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1] |
| ###rcll eflags[0x1,0x0] : r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1] |
| ###rcll eflags[0x1,0x0] : m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1] |
| ###rcll eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] |
| ###rcll eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] |
| ###rcll eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] |
| ###rcll eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1] |
| rcrb eflags[0x1,0x1] : r8.ub[0xca] => 0.ub[0xe5] eflags[0x1,0x0] |
| rcrb eflags[0x1,0x1] : m8.ub[0xca] => 0.ub[0xe5] eflags[0x1,0x0] |
| rcrb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1] |
| rcrb eflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1] |
| rcrb eflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1] |
| rcrb eflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1] |
| rcrw eflags[0x1,0x1] : r16.uw[0xf0ca] => 0.uw[0xf865] eflags[0x1,0x0] |
| rcrw eflags[0x1,0x1] : m16.uw[0xf0ca] => 0.uw[0xf865] eflags[0x1,0x0] |
| rcrw eflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1] |
| rcrw eflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1] |
| rcrw eflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1] |
| rcrw eflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1] |
| rcrl eflags[0x1,0x1] : r32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0] |
| rcrl eflags[0x1,0x1] : m32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0] |
| rcrl eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1] |
| rcrl eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1] |
| rcrl eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1] |
| rcrl eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1] |
| rolb r8.ub[0xca] => 0.ub[0x95] |
| rolb m8.ub[0xca] => 0.ub[0x95] |
| rolb imm8[2] r8.ub[0xca] => 1.ub[0x2b] |
| rolb imm8[2] m8.ub[0xca] => 1.ub[0x2b] |
| rolb cl.ub[2] r8.ub[0xca] => 1.ub[0x2b] |
| rolb cl.ub[2] m8.ub[0xca] => 1.ub[0x2b] |
| rolw r16.uw[0xf0ca] => 0.uw[0xe195] |
| rolw m16.uw[0xf0ca] => 0.uw[0xe195] |
| rolw imm8[4] r16.uw[0xf0ca] => 1.uw[0x0caf] |
| rolw imm8[4] m16.uw[0xf0ca] => 1.uw[0x0caf] |
| rolw cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0caf] |
| rolw cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0caf] |
| roll r32.ud[0xff00f0ca] => 0.ud[0xfe01e195] |
| roll m32.ud[0xff00f0ca] => 0.ud[0xfe01e195] |
| roll imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0caff] |
| roll imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0caff] |
| roll cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0caff] |
| roll cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0caff] |
| rorb r8.ub[0xca] => 0.ub[0x65] |
| rorb m8.ub[0xca] => 0.ub[0x65] |
| rorb imm8[2] r8.ub[0xca] => 1.ub[0xb2] |
| rorb imm8[2] m8.ub[0xca] => 1.ub[0xb2] |
| rorb cl.ub[2] r8.ub[0xca] => 1.ub[0xb2] |
| rorb cl.ub[2] m8.ub[0xca] => 1.ub[0xb2] |
| rorw r16.uw[0xf0ca] => 0.uw[0x7865] |
| rorw m16.uw[0xf0ca] => 0.uw[0x7865] |
| rorw imm8[4] r16.uw[0xf0ca] => 1.uw[0xaf0c] |
| rorw imm8[4] m16.uw[0xf0ca] => 1.uw[0xaf0c] |
| rorw cl.ub[4] r16.uw[0xf0ca] => 1.uw[0xaf0c] |
| rorw cl.ub[4] m16.uw[0xf0ca] => 1.uw[0xaf0c] |
| rorl r32.ud[0xff00f0ca] => 0.ud[0x7f807865] |
| rorl m32.ud[0xff00f0ca] => 0.ud[0x7f807865] |
| rorl imm8[8] r32.ud[0xff00f0ca] => 1.ud[0xcaff00f0] |
| rorl imm8[8] m32.ud[0xff00f0ca] => 1.ud[0xcaff00f0] |
| rorl cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0xcaff00f0] |
| rorl cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0xcaff00f0] |
| sahf eflags[0xff,0x28] ah.ub[0xfd] : => eflags[0xfd,0xd5] |
| sahf eflags[0xff,0xfd] ah.ub[0x28] : => eflags[0xfd,0x00] |
| salb r8.ub[0xca] => 0.ub[0x94] |
| salb m8.ub[0xca] => 0.ub[0x94] |
| salb imm8[2] r8.ub[0xca] => 1.ub[0x28] |
| salb imm8[2] m8.ub[0xca] => 1.ub[0x28] |
| salb cl.ub[2] r8.ub[0xca] => 1.ub[0x28] |
| salb cl.ub[2] m8.ub[0xca] => 1.ub[0x28] |
| salw r16.uw[0xf0ca] => 0.uw[0xe194] |
| salw m16.uw[0xf0ca] => 0.uw[0xe194] |
| salw imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca0] |
| salw imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca0] |
| salw cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca0] |
| salw cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca0] |
| sall r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] |
| sall m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] |
| sall imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00] |
| sall imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00] |
| sall cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00] |
| sall cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00] |
| sarb r8.ub[0xca] => 0.ub[0xe5] |
| sarb m8.ub[0xca] => 0.ub[0xe5] |
| sarb imm8[2] r8.ub[0xca] => 1.ub[0xf2] |
| sarb imm8[2] m8.ub[0xca] => 1.ub[0xf2] |
| sarb cl.ub[2] r8.ub[0xca] => 1.ub[0xf2] |
| sarb cl.ub[2] m8.ub[0xca] => 1.ub[0xf2] |
| sarw r16.uw[0xf0ca] => 0.uw[0xf865] |
| sarw m16.uw[0xf0ca] => 0.uw[0xf865] |
| sarw imm8[4] r16.uw[0xf0ca] => 1.uw[0xff0c] |
| sarw imm8[4] m16.uw[0xf0ca] => 1.uw[0xff0c] |
| sarw cl.ub[4] r16.uw[0xf0ca] => 1.uw[0xff0c] |
| sarw cl.ub[4] m16.uw[0xf0ca] => 1.uw[0xff0c] |
| sarl r32.ud[0xff00f0ca] => 0.ud[0xff807865] |
| sarl m32.ud[0xff00f0ca] => 0.ud[0xff807865] |
| sarl imm8[8] r32.ud[0xff00f0ca] => 1.ud[0xffff00f0] |
| sarl imm8[8] m32.ud[0xff00f0ca] => 1.ud[0xffff00f0] |
| sarl cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0xffff00f0] |
| sarl cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0xffff00f0] |
| ###sbbb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[22] |
| ###sbbb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[21] |
| sbbb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[22] |
| sbbb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[21] |
| sbbb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[22] |
| sbbb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[21] |
| sbbb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[22] |
| sbbb eflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[21] |
| sbbb eflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[22] |
| sbbb eflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[21] |
| ###sbbb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[22] |
| ###sbbb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[21] |
| sbbw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3444] |
| sbbw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3443] |
| ###sbbw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[4444] |
| ###sbbw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[4443] |
| sbbw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[4444] |
| sbbw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[4443] |
| sbbw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[4444] |
| sbbw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[4443] |
| sbbw eflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[4444] |
| sbbw eflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[4443] |
| sbbw eflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[4444] |
| sbbw eflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[4443] |
| sbbw eflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[4444] |
| sbbw eflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[4443] |
| sbbl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654309] |
| sbbl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654308] |
| ###sbbl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643] |
| ###sbbl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642] |
| sbbl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308643] |
| sbbl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308642] |
| sbbl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643] |
| sbbl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[75308642] |
| sbbl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643] |
| sbbl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308642] |
| sbbl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643] |
| sbbl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308642] |
| sbbl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643] |
| sbbl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308642] |
| seta eflags[0x041,0x000] : r8.ub[123] => 0.ub[1] |
| seta eflags[0x041,0x001] : r8.ub[123] => 0.ub[0] |
| seta eflags[0x041,0x040] : r8.ub[123] => 0.ub[0] |
| seta eflags[0x041,0x041] : r8.ub[123] => 0.ub[0] |
| seta eflags[0x041,0x000] : m8.ub[123] => 0.ub[1] |
| seta eflags[0x041,0x001] : m8.ub[123] => 0.ub[0] |
| seta eflags[0x041,0x040] : m8.ub[123] => 0.ub[0] |
| seta eflags[0x041,0x041] : m8.ub[123] => 0.ub[0] |
| setae eflags[0x001,0x000] : r8.ub[123] => 0.ub[1] |
| setae eflags[0x001,0x001] : r8.ub[123] => 0.ub[0] |
| setae eflags[0x001,0x000] : m8.ub[123] => 0.ub[1] |
| setae eflags[0x001,0x001] : m8.ub[123] => 0.ub[0] |
| setb eflags[0x001,0x000] : r8.ub[123] => 0.ub[0] |
| setb eflags[0x001,0x001] : r8.ub[123] => 0.ub[1] |
| setb eflags[0x001,0x000] : m8.ub[123] => 0.ub[0] |
| setb eflags[0x001,0x001] : m8.ub[123] => 0.ub[1] |
| setbe eflags[0x041,0x000] : r8.ub[123] => 0.ub[0] |
| setbe eflags[0x041,0x001] : r8.ub[123] => 0.ub[1] |
| setbe eflags[0x041,0x040] : r8.ub[123] => 0.ub[1] |
| setbe eflags[0x041,0x041] : r8.ub[123] => 0.ub[1] |
| setbe eflags[0x041,0x000] : m8.ub[123] => 0.ub[0] |
| setbe eflags[0x041,0x001] : m8.ub[123] => 0.ub[1] |
| setbe eflags[0x041,0x040] : m8.ub[123] => 0.ub[1] |
| setbe eflags[0x041,0x041] : m8.ub[123] => 0.ub[1] |
| setc eflags[0x001,0x000] : r8.ub[123] => 0.ub[0] |
| setc eflags[0x001,0x001] : r8.ub[123] => 0.ub[1] |
| setc eflags[0x001,0x000] : m8.ub[123] => 0.ub[0] |
| setc eflags[0x001,0x001] : m8.ub[123] => 0.ub[1] |
| sete eflags[0x040,0x000] : r8.ub[123] => 0.ub[0] |
| sete eflags[0x040,0x040] : r8.ub[123] => 0.ub[1] |
| sete eflags[0x040,0x000] : m8.ub[123] => 0.ub[0] |
| sete eflags[0x040,0x040] : m8.ub[123] => 0.ub[1] |
| setg eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] |
| setg eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0] |
| setg eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] |
| setg eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0] |
| setg eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] |
| setg eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0] |
| setg eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] |
| setg eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0] |
| setg eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] |
| setg eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0] |
| setg eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] |
| setg eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0] |
| setg eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] |
| setg eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0] |
| setg eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] |
| setg eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0] |
| setge eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] |
| setge eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] |
| setge eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] |
| setge eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] |
| setge eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] |
| setge eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] |
| setge eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] |
| setge eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] |
| setl eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] |
| setl eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] |
| setl eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] |
| setl eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] |
| setl eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] |
| setl eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] |
| setl eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] |
| setl eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] |
| setle eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] |
| setle eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1] |
| setle eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] |
| setle eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1] |
| setle eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] |
| setle eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1] |
| setle eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] |
| setle eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1] |
| setle eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] |
| setle eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1] |
| setle eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] |
| setle eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1] |
| setle eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] |
| setle eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1] |
| setle eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] |
| setle eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1] |
| setna eflags[0x041,0x000] : r8.ub[123] => 0.ub[0] |
| setna eflags[0x041,0x001] : r8.ub[123] => 0.ub[1] |
| setna eflags[0x041,0x040] : r8.ub[123] => 0.ub[1] |
| setna eflags[0x041,0x041] : r8.ub[123] => 0.ub[1] |
| setna eflags[0x041,0x000] : m8.ub[123] => 0.ub[0] |
| setna eflags[0x041,0x001] : m8.ub[123] => 0.ub[1] |
| setna eflags[0x041,0x040] : m8.ub[123] => 0.ub[1] |
| setna eflags[0x041,0x041] : m8.ub[123] => 0.ub[1] |
| setnae eflags[0x001,0x000] : r8.ub[123] => 0.ub[0] |
| setnae eflags[0x001,0x001] : r8.ub[123] => 0.ub[1] |
| setnae eflags[0x001,0x000] : m8.ub[123] => 0.ub[0] |
| setnae eflags[0x001,0x001] : m8.ub[123] => 0.ub[1] |
| setnb eflags[0x001,0x000] : r8.ub[123] => 0.ub[1] |
| setnb eflags[0x001,0x001] : r8.ub[123] => 0.ub[0] |
| setnb eflags[0x001,0x000] : m8.ub[123] => 0.ub[1] |
| setnb eflags[0x001,0x001] : m8.ub[123] => 0.ub[0] |
| setnbe eflags[0x041,0x000] : r8.ub[123] => 0.ub[1] |
| setnbe eflags[0x041,0x001] : r8.ub[123] => 0.ub[0] |
| setnbe eflags[0x041,0x040] : r8.ub[123] => 0.ub[0] |
| setnbe eflags[0x041,0x041] : r8.ub[123] => 0.ub[0] |
| setnbe eflags[0x041,0x000] : m8.ub[123] => 0.ub[1] |
| setnbe eflags[0x041,0x001] : m8.ub[123] => 0.ub[0] |
| setnbe eflags[0x041,0x040] : m8.ub[123] => 0.ub[0] |
| setnbe eflags[0x041,0x041] : m8.ub[123] => 0.ub[0] |
| setnc eflags[0x001,0x000] : r8.ub[123] => 0.ub[1] |
| setnc eflags[0x001,0x001] : r8.ub[123] => 0.ub[0] |
| setnc eflags[0x001,0x000] : m8.ub[123] => 0.ub[1] |
| setnc eflags[0x001,0x001] : m8.ub[123] => 0.ub[0] |
| setne eflags[0x040,0x000] : r8.ub[123] => 0.ub[1] |
| setne eflags[0x040,0x040] : r8.ub[123] => 0.ub[0] |
| setne eflags[0x040,0x000] : m8.ub[123] => 0.ub[1] |
| setne eflags[0x040,0x040] : m8.ub[123] => 0.ub[0] |
| setng eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] |
| setng eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1] |
| setng eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] |
| setng eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1] |
| setng eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] |
| setng eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1] |
| setng eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] |
| setng eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1] |
| setng eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] |
| setng eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1] |
| setng eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] |
| setng eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1] |
| setng eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] |
| setng eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1] |
| setng eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] |
| setng eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1] |
| setnge eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0] |
| setnge eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1] |
| setnge eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1] |
| setnge eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0] |
| setnge eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0] |
| setnge eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1] |
| setnge eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1] |
| setnge eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0] |
| setnl eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] |
| setnl eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] |
| setnl eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] |
| setnl eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] |
| setnl eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] |
| setnl eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] |
| setnl eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] |
| setnl eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] |
| setnle eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1] |
| setnle eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0] |
| setnle eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0] |
| setnle eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0] |
| setnle eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0] |
| setnle eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0] |
| setnle eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1] |
| setnle eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0] |
| setnle eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1] |
| setnle eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0] |
| setnle eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0] |
| setnle eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0] |
| setnle eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0] |
| setnle eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0] |
| setnle eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1] |
| setnle eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0] |
| setno eflags[0x800,0x000] : r8.ub[123] => 0.ub[1] |
| setno eflags[0x800,0x800] : r8.ub[123] => 0.ub[0] |
| setno eflags[0x800,0x000] : m8.ub[123] => 0.ub[1] |
| setno eflags[0x800,0x800] : m8.ub[123] => 0.ub[0] |
| setnp eflags[0x004,0x000] : r8.ub[123] => 0.ub[1] |
| setnp eflags[0x004,0x004] : r8.ub[123] => 0.ub[0] |
| setnp eflags[0x004,0x000] : m8.ub[123] => 0.ub[1] |
| setnp eflags[0x004,0x004] : m8.ub[123] => 0.ub[0] |
| setns eflags[0x080,0x000] : r8.ub[123] => 0.ub[1] |
| setns eflags[0x080,0x080] : r8.ub[123] => 0.ub[0] |
| setns eflags[0x080,0x000] : m8.ub[123] => 0.ub[1] |
| setns eflags[0x080,0x080] : m8.ub[123] => 0.ub[0] |
| setnz eflags[0x040,0x000] : r8.ub[123] => 0.ub[1] |
| setnz eflags[0x040,0x040] : r8.ub[123] => 0.ub[0] |
| setnz eflags[0x040,0x000] : m8.ub[123] => 0.ub[1] |
| setnz eflags[0x040,0x040] : m8.ub[123] => 0.ub[0] |
| seto eflags[0x800,0x000] : r8.ub[123] => 0.ub[0] |
| seto eflags[0x800,0x800] : r8.ub[123] => 0.ub[1] |
| seto eflags[0x800,0x000] : m8.ub[123] => 0.ub[0] |
| seto eflags[0x800,0x800] : m8.ub[123] => 0.ub[1] |
| setp eflags[0x004,0x000] : r8.ub[123] => 0.ub[0] |
| setp eflags[0x004,0x004] : r8.ub[123] => 0.ub[1] |
| setp eflags[0x004,0x000] : m8.ub[123] => 0.ub[0] |
| setp eflags[0x004,0x004] : m8.ub[123] => 0.ub[1] |
| sets eflags[0x080,0x000] : r8.ub[123] => 0.ub[0] |
| sets eflags[0x080,0x080] : r8.ub[123] => 0.ub[1] |
| sets eflags[0x080,0x000] : m8.ub[123] => 0.ub[0] |
| sets eflags[0x080,0x080] : m8.ub[123] => 0.ub[1] |
| setz eflags[0x040,0x000] : r8.ub[123] => 0.ub[0] |
| setz eflags[0x040,0x040] : r8.ub[123] => 0.ub[1] |
| setz eflags[0x040,0x000] : m8.ub[123] => 0.ub[0] |
| setz eflags[0x040,0x040] : m8.ub[123] => 0.ub[1] |
| shlb r8.ub[0xca] => 0.ub[0x94] |
| shlb m8.ub[0xca] => 0.ub[0x94] |
| shlb imm8[2] r8.ub[0xca] => 1.ub[0x28] |
| shlb imm8[2] m8.ub[0xca] => 1.ub[0x28] |
| shlb cl.ub[2] r8.ub[0xca] => 1.ub[0x28] |
| shlb cl.ub[2] m8.ub[0xca] => 1.ub[0x28] |
| shlw r16.uw[0xf0ca] => 0.uw[0xe194] |
| shlw m16.uw[0xf0ca] => 0.uw[0xe194] |
| shlw imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca0] |
| shlw imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca0] |
| shlw cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca0] |
| shlw cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca0] |
| shll r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] |
| shll m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] |
| shll imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00] |
| shll imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00] |
| shll cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00] |
| shll cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00] |
| shrb r8.ub[0xca] => 0.ub[0x65] |
| shrb m8.ub[0xca] => 0.ub[0x65] |
| shrb imm8[2] r8.ub[0xca] => 1.ub[0x32] |
| shrb imm8[2] m8.ub[0xca] => 1.ub[0x32] |
| shrb cl.ub[2] r8.ub[0xca] => 1.ub[0x32] |
| shrb cl.ub[2] m8.ub[0xca] => 1.ub[0x32] |
| shrw r16.uw[0xf0ca] => 0.uw[0x7865] |
| shrw m16.uw[0xf0ca] => 0.uw[0x7865] |
| shrw imm8[4] r16.uw[0xf0ca] => 1.uw[0x0f0c] |
| shrw imm8[4] m16.uw[0xf0ca] => 1.uw[0x0f0c] |
| shrw cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0f0c] |
| shrw cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0f0c] |
| shrl r32.ud[0xff00f0ca] => 0.ud[0x7f807865] |
| shrl m32.ud[0xff00f0ca] => 0.ud[0x7f807865] |
| shrl imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00ff00f0] |
| shrl imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00ff00f0] |
| shrl cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00ff00f0] |
| shrl cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00ff00f0] |
| shldw imm8[1] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0xe195] |
| shldw imm8[1] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0xe195] |
| shldw imm8[4] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0x0caf] |
| shldw imm8[4] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0x0caf] |
| shldw cl.ub[1] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0xe195] |
| shldw cl.ub[1] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0xe195] |
| shldw cl.ub[4] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0x0caf] |
| shldw cl.ub[4] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0x0caf] |
| shldl imm8[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xfe01e195] |
| shldl imm8[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xfe01e195] |
| shldl imm8[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x00f0caff] |
| shldl imm8[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x00f0caff] |
| shldl cl.ub[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xfe01e195] |
| shldl cl.ub[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xfe01e195] |
| shldl cl.ub[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x00f0caff] |
| shldl cl.ub[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x00f0caff] |
| shrdw imm8[1] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0x7865] |
| shrdw imm8[1] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0x7865] |
| shrdw imm8[4] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0xaf0c] |
| shrdw imm8[4] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0xaf0c] |
| shrdw cl.ub[1] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0x7865] |
| shrdw cl.ub[1] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0x7865] |
| shrdw cl.ub[4] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0xaf0c] |
| shrdw cl.ub[4] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0xaf0c] |
| shrdl imm8[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x7f807865] |
| shrdl imm8[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x7f807865] |
| shrdl imm8[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xcaff00f0] |
| shrdl imm8[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xcaff00f0] |
| shrdl cl.ub[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x7f807865] |
| shrdl cl.ub[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x7f807865] |
| shrdl cl.ub[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xcaff00f0] |
| shrdl cl.ub[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xcaff00f0] |
| ###stc eflags[0x001,0x000] : => eflags[0x001,0x001] |
| ###stc eflags[0x001,0x001] : => eflags[0x001,0x001] |
| std eflags[0x400,0x000] : => eflags[0x400,0x400] |
| std eflags[0x400,0x400] : => eflags[0x400,0x400] |
| subb imm8[12] al.ub[34] => 1.ub[22] |
| subb imm8[12] bl.ub[34] => 1.ub[22] |
| subb imm8[12] m8.ub[34] => 1.ub[22] |
| subb r8.ub[12] r8.ub[34] => 1.ub[22] |
| subb r8.ub[12] m8.ub[34] => 1.ub[22] |
| subb m8.ub[12] r8.ub[34] => 1.ub[22] |
| subw imm8[12] r16.uw[3456] => 1.uw[3444] |
| subw imm16[1234] ax.uw[5678] => 1.uw[4444] |
| subw imm16[1234] bx.uw[5678] => 1.uw[4444] |
| subw imm16[1234] m16.uw[5678] => 1.uw[4444] |
| subw r16.uw[1234] r16.uw[5678] => 1.uw[4444] |
| subw r16.uw[1234] m16.uw[5678] => 1.uw[4444] |
| subw m16.uw[1234] r16.uw[5678] => 1.uw[4444] |
| subl imm8[12] r32.ud[87654321] => 1.ud[87654309] |
| subl imm32[12345678] r32.ud[87654321] => 1.ud[75308643] |
| subl imm32[12345678] eax.ud[87654321] => 1.ud[75308643] |
| subl imm32[12345678] ebx.ud[87654321] => 1.ud[75308643] |
| subl r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643] |
| subl r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643] |
| subl m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643] |
| testb imm8[0x1a] al.ub[0x1a] => eflags[0x8c5,0x000] |
| testb imm8[0x5a] al.ub[0x5a] => eflags[0x8c5,0x004] |
| testb imm8[0x1a] al.ub[0xa1] => eflags[0x8c5,0x044] |
| testb imm8[0xa1] al.ub[0xa1] => eflags[0x8c5,0x080] |
| testb imm8[0xa5] al.ub[0xa5] => eflags[0x8c5,0x084] |
| testb imm8[0x1a] bl.ub[0x1a] => eflags[0x8c5,0x000] |
| testb imm8[0x5a] bl.ub[0x5a] => eflags[0x8c5,0x004] |
| testb imm8[0x1a] bl.ub[0xa1] => eflags[0x8c5,0x044] |
| testb imm8[0xa1] bl.ub[0xa1] => eflags[0x8c5,0x080] |
| testb imm8[0xa5] bl.ub[0xa5] => eflags[0x8c5,0x084] |
| testb imm8[0x1a] m8.ub[0x1a] => eflags[0x8c5,0x000] |
| testb imm8[0x5a] m8.ub[0x5a] => eflags[0x8c5,0x004] |
| testb imm8[0x1a] m8.ub[0xa1] => eflags[0x8c5,0x044] |
| testb imm8[0xa1] m8.ub[0xa1] => eflags[0x8c5,0x080] |
| testb imm8[0xa5] m8.ub[0xa5] => eflags[0x8c5,0x084] |
| testb r8.ub[0x1a] r8.ub[0x1a] => eflags[0x8c5,0x000] |
| testb r8.ub[0x5a] r8.ub[0x5a] => eflags[0x8c5,0x004] |
| testb r8.ub[0x1a] r8.ub[0xa1] => eflags[0x8c5,0x044] |
| testb r8.ub[0xa1] r8.ub[0xa1] => eflags[0x8c5,0x080] |
| testb r8.ub[0xa5] r8.ub[0xa5] => eflags[0x8c5,0x084] |
| testb r8.ub[0x1a] m8.ub[0x1a] => eflags[0x8c5,0x000] |
| testb r8.ub[0x5a] m8.ub[0x5a] => eflags[0x8c5,0x004] |
| testb r8.ub[0x1a] m8.ub[0xa1] => eflags[0x8c5,0x044] |
| testb r8.ub[0xa1] m8.ub[0xa1] => eflags[0x8c5,0x080] |
| testb r8.ub[0xa5] m8.ub[0xa5] => eflags[0x8c5,0x084] |
| testw imm16[0x1a1a] ax.uw[0x1a1a] => eflags[0x8c5,0x000] |
| testw imm16[0x5a5a] ax.uw[0x5a5a] => eflags[0x8c5,0x004] |
| testw imm16[0x1a1a] ax.uw[0xa1a1] => eflags[0x8c5,0x044] |
| testw imm16[0xa1a1] ax.uw[0xa1a1] => eflags[0x8c5,0x080] |
| testw imm16[0xa5a5] ax.uw[0xa5a5] => eflags[0x8c5,0x084] |
| testw imm16[0x1a1a] bx.uw[0x1a1a] => eflags[0x8c5,0x000] |
| testw imm16[0x5a5a] bx.uw[0x5a5a] => eflags[0x8c5,0x004] |
| testw imm16[0x1a1a] bx.uw[0xa1a1] => eflags[0x8c5,0x044] |
| testw imm16[0xa1a1] bx.uw[0xa1a1] => eflags[0x8c5,0x080] |
| testw imm16[0xa5a5] bx.uw[0xa5a5] => eflags[0x8c5,0x084] |
| testw imm16[0x1a1a] m16.uw[0x1a1a] => eflags[0x8c5,0x000] |
| testw imm16[0x5a5a] m16.uw[0x5a5a] => eflags[0x8c5,0x004] |
| testw imm16[0x1a1a] m16.uw[0xa1a1] => eflags[0x8c5,0x044] |
| testw imm16[0xa1a1] m16.uw[0xa1a1] => eflags[0x8c5,0x080] |
| testw imm16[0xa5a5] m16.uw[0xa5a5] => eflags[0x8c5,0x084] |
| testw r16.uw[0x1a1a] r16.uw[0x1a1a] => eflags[0x8c5,0x000] |
| testw r16.uw[0x5a5a] r16.uw[0x5a5a] => eflags[0x8c5,0x004] |
| testw r16.uw[0x1a1a] r16.uw[0xa1a1] => eflags[0x8c5,0x044] |
| testw r16.uw[0xa1a1] r16.uw[0xa1a1] => eflags[0x8c5,0x080] |
| testw r16.uw[0xa5a5] r16.uw[0xa5a5] => eflags[0x8c5,0x084] |
| testw r16.uw[0x1a1a] m16.uw[0x1a1a] => eflags[0x8c5,0x000] |
| testw r16.uw[0x5a5a] m16.uw[0x5a5a] => eflags[0x8c5,0x004] |
| testw r16.uw[0x1a1a] m16.uw[0xa1a1] => eflags[0x8c5,0x044] |
| testw r16.uw[0xa1a1] m16.uw[0xa1a1] => eflags[0x8c5,0x080] |
| testw r16.uw[0xa5a5] m16.uw[0xa5a5] => eflags[0x8c5,0x084] |
| testl imm32[0x1a1a1a1a] eax.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] |
| testl imm32[0x5a5a5a5a] eax.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] |
| testl imm32[0x1a1a1a1a] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] |
| testl imm32[0xa1a1a1a1] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] |
| testl imm32[0xa5a5a5a5] eax.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] |
| testl imm32[0x1a1a1a1a] ebx.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] |
| testl imm32[0x5a5a5a5a] ebx.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] |
| testl imm32[0x1a1a1a1a] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] |
| testl imm32[0xa1a1a1a1] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] |
| testl imm32[0xa5a5a5a5] ebx.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] |
| testl imm32[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] |
| testl imm32[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] |
| testl imm32[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] |
| testl imm32[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] |
| testl imm32[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] |
| testl r32.ud[0x1a1a1a1a] r32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] |
| testl r32.ud[0x5a5a5a5a] r32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] |
| testl r32.ud[0x1a1a1a1a] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] |
| testl r32.ud[0xa1a1a1a1] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] |
| testl r32.ud[0xa5a5a5a5] r32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] |
| testl r32.ud[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000] |
| testl r32.ud[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004] |
| testl r32.ud[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044] |
| testl r32.ud[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080] |
| testl r32.ud[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084] |
| ###xaddb r8.ub[12] r8.ub[34] => 0.ub[34] 1.ub[46] |
| ###xaddb r8.ub[12] m8.ub[34] => 0.ub[34] 1.ub[46] |
| ###xaddw r16.uw[1234] r16.uw[5678] => 0.uw[5678] 1.uw[6912] |
| xaddw r16.uw[1234] m16.uw[5678] => 0.uw[5678] 1.uw[6912] |
| ###xaddl r32.ud[12345678] r32.ud[87654321] => 0.ud[87654321] 1.ud[99999999] |
| xaddl r32.ud[12345678] m32.ud[87654321] => 0.ud[87654321] 1.ud[99999999] |
| xchgb r8.ub[12] r8.ub[34] => 0.ub[34] 1.ub[12] |
| xchgb r8.ub[12] m8.ub[34] => 0.ub[34] 1.ub[12] |
| xchgb m8.ub[12] r8.ub[34] => 0.ub[34] 1.ub[12] |
| xchgw ax.uw[1234] bx.uw[5678] => 0.uw[5678] 1.uw[1234] |
| xchgw bx.uw[1234] ax.uw[5678] => 0.uw[5678] 1.uw[1234] |
| xchgw ax.uw[1234] cx.uw[5678] => 0.uw[5678] 1.uw[1234] |
| xchgw r16.uw[1234] m16.uw[5678] => 0.uw[5678] 1.uw[1234] |
| xchgw m16.uw[1234] r16.uw[5678] => 0.uw[5678] 1.uw[1234] |
| xchgl eax.ud[12345678] ebx.ud[87654321] => 0.ud[87654321] 1.ud[12345678] |
| xchgl ebx.ud[12345678] eax.ud[87654321] => 0.ud[87654321] 1.ud[12345678] |
| xchgl ebx.ud[12345678] ecx.ud[87654321] => 0.ud[87654321] 1.ud[12345678] |
| xchgl r32.ud[12345678] m32.ud[87654321] => 0.ud[87654321] 1.ud[12345678] |
| xchgl m32.ud[12345678] r32.ud[87654321] => 0.ud[87654321] 1.ud[12345678] |
| xorb imm8[0x34] al.ub[0x56] => 1.ub[0x62] |
| xorb imm8[0x34] bl.ub[0x56] => 1.ub[0x62] |
| xorb imm8[0x34] m8.ub[0x56] => 1.ub[0x62] |
| xorb r8.ub[0x34] r8.ub[0x56] => 1.ub[0x62] |
| xorb r8.ub[0x34] m8.ub[0x56] => 1.ub[0x62] |
| xorb m8.ub[0x34] r8.ub[0x56] => 1.ub[0x62] |
| xorw imm8[0x31] r16.uw[0x1234] => 1.uw[0x1205] |
| xorw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x5005] |
| xorw imm16[0x4231] bx.uw[0x1234] => 1.uw[0x5005] |
| xorw imm16[0x4231] m16.uw[0x1234] => 1.uw[0x5005] |
| xorw r16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x5005] |
| xorw r16.uw[0x4231] m16.uw[0x1234] => 1.uw[0x5005] |
| xorw m16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x5005] |
| xorl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x12345649] |
| xorl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x94762349] |
| xorl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x94762349] |
| xorl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x94762349] |
| xorl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x94762349] |
| xorl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x94762349] |
| xorl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x94762349] |