Update Valgrind and TSan.
Rebased local changes on:
http://valgrind-variant.googlecode.com/svn/trunk@125
http://data-race-test.googlecode.com/svn/trunk@3717
Change-Id: I4d7a227ad72fb8e9998015a5fe26e00496ec1da3
diff --git a/main/VEX/priv/host_arm_defs.h b/main/VEX/priv/host_arm_defs.h
index 1901e80..0dea3f5 100644
--- a/main/VEX/priv/host_arm_defs.h
+++ b/main/VEX/priv/host_arm_defs.h
@@ -1,4 +1,3 @@
-
/*---------------------------------------------------------------*/
/*--- begin host_arm_defs.h ---*/
/*---------------------------------------------------------------*/
@@ -7,7 +6,7 @@
This file is part of Valgrind, a dynamic binary instrumentation
framework.
- Copyright (C) 2004-2010 OpenWorks LLP
+ Copyright (C) 2004-2011 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
@@ -587,6 +586,7 @@
ARMin_VCvtID,
ARMin_FPSCR,
ARMin_MFence,
+ ARMin_CLREX,
/* Neon */
ARMin_NLdStQ,
ARMin_NLdStD,
@@ -709,18 +709,21 @@
struct {
ARMMulOp op;
} Mul;
- /* LDREX{,H,B} r0, [r1]
+ /* LDREX{,H,B} r2, [r4] and
+ LDREXD r2, r3, [r4] (on LE hosts, transferred value is r3:r2)
Again, hardwired registers since this is not performance
critical, and there are possibly constraints on the
registers that we can't express in the register allocator.*/
struct {
- Int szB; /* currently only 4 is allowed */
+ Int szB; /* 1, 2, 4 or 8 */
} LdrEX;
- /* STREX{,H,B} r0, r1, [r2]
- r0 = SC( [r2] = r1 )
+ /* STREX{,H,B} r0, r2, [r4] and
+ STREXD r0, r2, r3, [r4] (on LE hosts, transferred value is r3:r2)
+ r0 = SC( [r4] = r2 ) (8, 16, 32 bit transfers)
+ r0 = SC( [r4] = r3:r2) (64 bit transfers)
Ditto comment re fixed registers. */
struct {
- Int szB; /* currently only 4 is allowed */
+ Int szB; /* 1, 2, 4 or 8 */
} StrEX;
/* VFP INSTRUCTIONS */
/* 64-bit Fp load/store */
@@ -824,6 +827,9 @@
*/
struct {
} MFence;
+ /* A CLREX instruction. */
+ struct {
+ } CLREX;
/* Neon data processing instruction: 3 registers of the same
length */
struct {
@@ -937,10 +943,11 @@
HReg dst, HReg src );
extern ARMInstr* ARMInstr_FPSCR ( Bool toFPSCR, HReg iReg );
extern ARMInstr* ARMInstr_MFence ( void );
+extern ARMInstr* ARMInstr_CLREX ( void );
extern ARMInstr* ARMInstr_NLdStQ ( Bool isLoad, HReg, ARMAModeN* );
extern ARMInstr* ARMInstr_NLdStD ( Bool isLoad, HReg, ARMAModeN* );
extern ARMInstr* ARMInstr_NUnary ( ARMNeonUnOp, HReg, HReg, UInt, Bool );
-extern ARMInstr* ARMInstr_NUnaryS ( ARMNeonUnOp, ARMNRS*, ARMNRS*,
+extern ARMInstr* ARMInstr_NUnaryS ( ARMNeonUnOpS, ARMNRS*, ARMNRS*,
UInt, Bool );
extern ARMInstr* ARMInstr_NDual ( ARMNeonDualOp, HReg, HReg, UInt, Bool );
extern ARMInstr* ARMInstr_NBinary ( ARMNeonBinOp, HReg, HReg, HReg,
@@ -960,7 +967,9 @@
extern void mapRegs_ARMInstr ( HRegRemap*, ARMInstr*, Bool );
extern Bool isMove_ARMInstr ( ARMInstr*, HReg*, HReg* );
extern Int emit_ARMInstr ( UChar* buf, Int nbuf, ARMInstr*,
- Bool, void* dispatch );
+ Bool,
+ void* dispatch_unassisted,
+ void* dispatch_assisted );
extern void genSpill_ARM ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
HReg rreg, Int offset, Bool );