sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
| 3 | /*--- ---*/ |
| 4 | /*--- This file (host-generic/reg_alloc2.c) is ---*/ |
sewardj | dbcfae7 | 2005-08-02 11:14:04 +0000 | [diff] [blame] | 5 | /*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 6 | /*--- ---*/ |
| 7 | /*---------------------------------------------------------------*/ |
| 8 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | /* |
| 10 | This file is part of LibVEX, a library for dynamic binary |
| 11 | instrumentation and translation. |
| 12 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 13 | Copyright (C) 2004-2005 OpenWorks LLP. All rights reserved. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 14 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 15 | This library is made available under a dual licensing scheme. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 16 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 17 | If you link LibVEX against other code all of which is itself |
| 18 | licensed under the GNU General Public License, version 2 dated June |
| 19 | 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL |
| 20 | v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL |
| 21 | is missing, you can obtain a copy of the GPL v2 from the Free |
| 22 | Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 23 | 02110-1301, USA. |
| 24 | |
| 25 | For any other uses of LibVEX, you must first obtain a commercial |
| 26 | license from OpenWorks LLP. Please contact info@open-works.co.uk |
| 27 | for information about commercial licensing. |
| 28 | |
| 29 | This software is provided by OpenWorks LLP "as is" and any express |
| 30 | or implied warranties, including, but not limited to, the implied |
| 31 | warranties of merchantability and fitness for a particular purpose |
| 32 | are disclaimed. In no event shall OpenWorks LLP be liable for any |
| 33 | direct, indirect, incidental, special, exemplary, or consequential |
| 34 | damages (including, but not limited to, procurement of substitute |
| 35 | goods or services; loss of use, data, or profits; or business |
| 36 | interruption) however caused and on any theory of liability, |
| 37 | whether in contract, strict liability, or tort (including |
| 38 | negligence or otherwise) arising in any way out of the use of this |
| 39 | software, even if advised of the possibility of such damage. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 40 | |
| 41 | Neither the names of the U.S. Department of Energy nor the |
| 42 | University of California nor the names of its contributors may be |
| 43 | used to endorse or promote products derived from this software |
| 44 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 45 | */ |
| 46 | |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 47 | #include "libvex_basictypes.h" |
| 48 | #include "libvex.h" |
| 49 | |
| 50 | #include "main/vex_util.h" |
| 51 | #include "host-generic/h_generic_regs.h" |
| 52 | |
| 53 | /* Set to 1 for lots of debugging output. */ |
| 54 | #define DEBUG_REGALLOC 0 |
| 55 | |
| 56 | |
| 57 | /* TODO 27 Oct 04: |
| 58 | |
| 59 | (Critical): Need a way to statically establish the vreg classes, |
| 60 | else we can't allocate spill slots properly. |
| 61 | |
| 62 | Better consistency checking from what isMove tells us. |
| 63 | |
| 64 | We can possibly do V-V coalescing even when the src is spilled, |
| 65 | providing we can arrange for the dst to have the same spill slot. |
| 66 | |
| 67 | Note that state[].hreg is the same as the available real regs. |
| 68 | |
| 69 | Check whether rreg preferencing has any beneficial effect. |
| 70 | |
| 71 | Remove preferencing fields in VRegInfo, if not used. |
| 72 | |
| 73 | Generally rationalise data structures. */ |
| 74 | |
| 75 | |
| 76 | /* Records information on virtual register live ranges. Computed once |
| 77 | and remains unchanged after that. */ |
| 78 | typedef |
| 79 | struct { |
| 80 | /* Becomes live for the first time after this insn ... */ |
| 81 | Short live_after; |
| 82 | /* Becomes dead for the last time before this insn ... */ |
| 83 | Short dead_before; |
| 84 | /* The "home" spill slot, if needed. Never changes. */ |
| 85 | Short spill_offset; |
| 86 | Short spill_size; |
| 87 | /* What kind of register this is. */ |
| 88 | HRegClass reg_class; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 89 | } |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 90 | VRegLR; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 91 | |
| 92 | |
| 93 | /* Records information on real-register live ranges. Computed once |
| 94 | and remains unchanged after that. */ |
| 95 | typedef |
| 96 | struct { |
| 97 | HReg rreg; |
| 98 | /* Becomes live after this insn ... */ |
| 99 | Short live_after; |
| 100 | /* Becomes dead before this insn ... */ |
| 101 | Short dead_before; |
| 102 | } |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 103 | RRegLR; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 104 | |
| 105 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 106 | /* An array of the following structs (rreg_state) comprises the |
| 107 | running state of the allocator. It indicates what the current |
| 108 | disposition of each allocatable real register is. The array gets |
| 109 | updated as the allocator processes instructions. */ |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 110 | typedef |
| 111 | struct { |
| 112 | /* FIELDS WHICH DO NOT CHANGE */ |
| 113 | /* Which rreg is this for? */ |
| 114 | HReg rreg; |
| 115 | /* Is this involved in any HLRs? (only an optimisation hint) */ |
| 116 | Bool has_hlrs; |
| 117 | /* FIELDS WHICH DO CHANGE */ |
| 118 | /* What's it's current disposition? */ |
| 119 | enum { Free, /* available for use */ |
| 120 | Unavail, /* in a real-reg live range */ |
| 121 | Bound /* in use (holding value of some vreg) */ |
| 122 | } |
| 123 | disp; |
| 124 | /* If RRegBound, what vreg is it bound to? */ |
| 125 | HReg vreg; |
| 126 | /* Used when .disp == Bound and we are looking for vregs to |
| 127 | spill. */ |
| 128 | Bool is_spill_cand; |
| 129 | } |
| 130 | RRegState; |
| 131 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 132 | /* The allocator also maintains a redundant array of indexes |
| 133 | (vreg_state) from vreg numbers back to entries in rreg_state. It |
| 134 | is redundant because iff vreg_state[i] == j then |
| 135 | hregNumber(rreg_state[j].vreg) == i -- that is, the two entries |
| 136 | point at each other. The purpose of this is to speed up activities |
| 137 | which involve looking for a particular vreg: there is no need to |
| 138 | scan the rreg_state looking for it, just index directly into |
| 139 | vreg_state. The FAQ "does this vreg already have an associated |
| 140 | rreg" is the main beneficiary. |
| 141 | |
| 142 | To indicate, in vreg_state[i], that a given vreg is not currently |
| 143 | associated with any rreg, that entry can be set to INVALID_RREG_NO. |
| 144 | |
| 145 | Because the vreg_state entries are signed Shorts, the max number |
| 146 | of vregs that can be handed by regalloc is 32767. |
| 147 | */ |
| 148 | |
| 149 | #define INVALID_RREG_NO ((Short)(-1)) |
| 150 | |
| 151 | #define IS_VALID_VREGNO(_zz) ((_zz) >= 0 && (_zz) < n_vregs) |
| 152 | #define IS_VALID_RREGNO(_zz) ((_zz) >= 0 && (_zz) < n_rregs) |
| 153 | |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 154 | |
| 155 | |
| 156 | /* Does this instruction mention a particular reg? */ |
| 157 | static Bool instrMentionsReg ( |
| 158 | void (*getRegUsage) (HRegUsage*, HInstr*), |
| 159 | HInstr* instr, |
| 160 | HReg r |
| 161 | ) |
| 162 | { |
| 163 | Int i; |
| 164 | HRegUsage reg_usage; |
| 165 | (*getRegUsage)(®_usage, instr); |
| 166 | for (i = 0; i < reg_usage.n_used; i++) |
| 167 | if (reg_usage.hreg[i] == r) |
| 168 | return True; |
| 169 | return False; |
| 170 | } |
| 171 | |
| 172 | |
| 173 | /* Search forward from some given point in the incoming instruction |
| 174 | sequence. Point is to select a virtual register to spill, by |
| 175 | finding the vreg which is mentioned as far ahead as possible, in |
| 176 | the hope that this will minimise the number of consequent reloads. |
| 177 | |
| 178 | Only do the search for vregs which are Bound in the running state, |
| 179 | and for which the .is_spill_cand field is set. This allows the |
| 180 | caller to arbitrarily restrict the set of spill candidates to be |
| 181 | considered. |
| 182 | |
| 183 | Returns an index into the state array indicating the (v,r) pair to |
| 184 | spill, or -1 if none was found. */ |
| 185 | static |
| 186 | Int findMostDistantlyMentionedVReg ( |
| 187 | void (*getRegUsage) (HRegUsage*, HInstr*), |
| 188 | HInstrArray* instrs_in, |
| 189 | Int search_from_instr, |
| 190 | RRegState* state, |
| 191 | Int n_state |
| 192 | ) |
| 193 | { |
| 194 | Int k, m; |
| 195 | Int furthest_k = -1; |
| 196 | Int furthest = -1; |
| 197 | vassert(search_from_instr >= 0); |
| 198 | for (k = 0; k < n_state; k++) { |
| 199 | if (!state[k].is_spill_cand) |
| 200 | continue; |
| 201 | vassert(state[k].disp == Bound); |
| 202 | for (m = search_from_instr; m < instrs_in->arr_used; m++) { |
| 203 | if (instrMentionsReg(getRegUsage, |
| 204 | instrs_in->arr[m], state[k].vreg)) |
| 205 | break; |
| 206 | } |
| 207 | if (m > furthest) { |
| 208 | furthest = m; |
| 209 | furthest_k = k; |
| 210 | } |
| 211 | } |
| 212 | return furthest_k; |
| 213 | } |
| 214 | |
| 215 | |
| 216 | |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 217 | /* Double the size of the real-reg live-range array, if needed. */ |
| 218 | static void ensureRRLRspace ( RRegLR** info, Int* size, Int used ) |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 219 | { |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 220 | Int k; |
| 221 | RRegLR* arr2; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 222 | if (used < *size) return; |
| 223 | if (0) |
| 224 | vex_printf("ensureRRISpace: %d -> %d\n", *size, 2 * *size); |
| 225 | vassert(used == *size); |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 226 | arr2 = LibVEX_Alloc(2 * *size * sizeof(RRegLR)); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 227 | for (k = 0; k < *size; k++) |
| 228 | arr2[k] = (*info)[k]; |
| 229 | *size *= 2; |
| 230 | *info = arr2; |
| 231 | } |
| 232 | |
| 233 | |
sewardj | 17bbc21 | 2004-12-30 00:14:54 +0000 | [diff] [blame] | 234 | /* A target-independent register allocator. Requires various |
| 235 | functions which it uses to deal abstractly with instructions and |
| 236 | registers, since it cannot have any target-specific knowledge. |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 237 | |
| 238 | Returns a new list of instructions, which, as a result of the |
| 239 | behaviour of mapRegs, will be in-place modifications of the |
| 240 | original instructions. |
| 241 | |
| 242 | Requires that the incoming code has been generated using |
| 243 | vreg numbers 0, 1 .. n_vregs-1. Appearance of a vreg outside |
| 244 | that range is a checked run-time error. |
| 245 | |
| 246 | Takes an expandable array of pointers to unallocated insns. |
| 247 | Returns an expandable array of pointers to allocated insns. |
| 248 | */ |
| 249 | HInstrArray* doRegisterAllocation ( |
| 250 | |
| 251 | /* Incoming virtual-registerised code. */ |
| 252 | HInstrArray* instrs_in, |
| 253 | |
| 254 | /* An array listing all the real registers the allocator may use, |
| 255 | in no particular order. */ |
| 256 | HReg* available_real_regs, |
| 257 | Int n_available_real_regs, |
| 258 | |
| 259 | /* Return True iff the given insn is a reg-reg move, in which |
| 260 | case also return the src and dst regs. */ |
| 261 | Bool (*isMove) (HInstr*, HReg*, HReg*), |
| 262 | |
| 263 | /* Get info about register usage in this insn. */ |
| 264 | void (*getRegUsage) (HRegUsage*, HInstr*), |
| 265 | |
| 266 | /* Apply a reg-reg mapping to an insn. */ |
| 267 | void (*mapRegs) (HRegRemap*, HInstr*), |
| 268 | |
| 269 | /* Return an insn to spill/restore a real reg to a spill slot |
| 270 | byte offset. */ |
| 271 | HInstr* (*genSpill) ( HReg, Int ), |
| 272 | HInstr* (*genReload) ( HReg, Int ), |
| 273 | Int guest_sizeB, |
| 274 | |
| 275 | /* For debug printing only. */ |
| 276 | void (*ppInstr) ( HInstr* ), |
| 277 | void (*ppReg) ( HReg ) |
| 278 | ) |
| 279 | { |
| 280 | # define N_SPILL64S (LibVEX_N_SPILL_BYTES / 8) |
| 281 | |
| 282 | /* Iterators and temporaries. */ |
| 283 | Int ii, j, k, m, spillee, k_suboptimal; |
| 284 | HReg rreg, vreg, vregS, vregD; |
| 285 | HRegUsage reg_usage; |
| 286 | |
| 287 | /* Info on vregs and rregs. Computed once and remains |
| 288 | unchanged. */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 289 | Int n_vregs; |
| 290 | VRegLR* vreg_lrs; /* [0 .. n_vregs-1] */ |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 291 | |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 292 | RRegLR* rreg_lrs; |
| 293 | Int rreg_lrs_size; |
| 294 | Int rreg_lrs_used; |
| 295 | |
| 296 | /* Used when constructing vreg_lrs (for allocating stack |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 297 | slots). */ |
| 298 | Int ss_busy_until_before[N_SPILL64S]; |
| 299 | |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 300 | /* Used when constructing rreg_lrs. */ |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 301 | Int* rreg_live_after; |
| 302 | Int* rreg_dead_before; |
| 303 | |
| 304 | /* Running state of the core allocation algorithm. */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 305 | RRegState* rreg_state; /* [0 .. n_rregs-1] */ |
| 306 | Int n_rregs; |
| 307 | |
| 308 | /* .. and the redundant backward map */ |
| 309 | /* Each value is 0 .. n_rregs-1 or is INVALID_RREG_NO. |
| 310 | This inplies n_rregs must be <= 32768. */ |
| 311 | Short* vreg_state; /* [0 .. n_vregs-1] */ |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 312 | |
| 313 | /* The vreg -> rreg map constructed and then applied to each |
| 314 | instr. */ |
| 315 | HRegRemap remap; |
| 316 | |
| 317 | /* The output array of instructions. */ |
| 318 | HInstrArray* instrs_out; |
| 319 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 320 | /* Sanity checks are expensive. They are only done periodically, |
| 321 | not at each insn processed. */ |
| 322 | Bool do_sanity_check; |
| 323 | |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 324 | vassert(0 == LibVEX_N_SPILL_BYTES % 16); |
| 325 | vassert(0 == guest_sizeB % 8); |
| 326 | |
| 327 | /* The live range numbers are signed shorts, and so limiting the |
| 328 | number of insns to 10000 comfortably guards against them |
| 329 | overflowing 32k. */ |
| 330 | vassert(instrs_in->arr_used <= 10000); |
| 331 | |
| 332 | # define INVALID_INSTRNO (-2) |
| 333 | |
| 334 | # define EMIT_INSTR(_instr) \ |
| 335 | do { \ |
| 336 | HInstr* _tmp = (_instr); \ |
| 337 | if (DEBUG_REGALLOC) { \ |
| 338 | vex_printf("** "); \ |
| 339 | (*ppInstr)(_tmp); \ |
| 340 | vex_printf("\n\n"); \ |
| 341 | } \ |
| 342 | addHInstr ( instrs_out, _tmp ); \ |
| 343 | } while (0) |
| 344 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 345 | # define PRINT_STATE \ |
| 346 | do { \ |
| 347 | Int z, q; \ |
| 348 | for (z = 0; z < n_rregs; z++) { \ |
| 349 | vex_printf(" rreg_state[%2d] = ", z); \ |
| 350 | (*ppReg)(rreg_state[z].rreg); \ |
| 351 | vex_printf(" \t"); \ |
| 352 | switch (rreg_state[z].disp) { \ |
| 353 | case Free: vex_printf("Free\n"); break; \ |
| 354 | case Unavail: vex_printf("Unavail\n"); break; \ |
| 355 | case Bound: vex_printf("BoundTo "); \ |
| 356 | (*ppReg)(rreg_state[z].vreg); \ |
| 357 | vex_printf("\n"); break; \ |
| 358 | } \ |
| 359 | } \ |
| 360 | vex_printf("\n vreg_state[0 .. %d]:\n ", n_vregs-1); \ |
| 361 | q = 0; \ |
| 362 | for (z = 0; z < n_vregs; z++) { \ |
| 363 | if (vreg_state[z] == INVALID_RREG_NO) \ |
| 364 | continue; \ |
| 365 | vex_printf("[%d] -> %d ", z, vreg_state[z]); \ |
| 366 | q++; \ |
| 367 | if (q > 0 && (q % 6) == 0) \ |
| 368 | vex_printf("\n "); \ |
| 369 | } \ |
| 370 | vex_printf("\n"); \ |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 371 | } while (0) |
| 372 | |
| 373 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 374 | /* --------- Stage 0: set up output array --------- */ |
| 375 | /* --------- and allocate/initialise running state. --------- */ |
| 376 | |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 377 | instrs_out = newHInstrArray(); |
| 378 | |
| 379 | /* ... and initialise running state. */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 380 | /* n_rregs is no more than a short name for n_available_real_regs. */ |
| 381 | n_rregs = n_available_real_regs; |
| 382 | n_vregs = instrs_in->n_vregs; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 383 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 384 | /* If this is not so, vreg_state entries will overflow. */ |
| 385 | vassert(n_vregs < 32767); |
| 386 | |
| 387 | rreg_state = LibVEX_Alloc(n_rregs * sizeof(RRegState)); |
| 388 | vreg_state = LibVEX_Alloc(n_vregs * sizeof(Short)); |
| 389 | |
| 390 | for (j = 0; j < n_rregs; j++) { |
| 391 | rreg_state[j].rreg = available_real_regs[j]; |
| 392 | rreg_state[j].has_hlrs = False; |
| 393 | rreg_state[j].disp = Free; |
| 394 | rreg_state[j].vreg = INVALID_HREG; |
| 395 | rreg_state[j].is_spill_cand = False; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 396 | } |
| 397 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 398 | for (j = 0; j < n_vregs; j++) |
| 399 | vreg_state[j] = INVALID_RREG_NO; |
| 400 | |
| 401 | |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 402 | /* --------- Stage 1: compute vreg live ranges. --------- */ |
| 403 | /* --------- Stage 2: compute rreg live ranges. --------- */ |
| 404 | |
| 405 | /* ------ start of SET UP TO COMPUTE VREG LIVE RANGES ------ */ |
| 406 | |
| 407 | /* This is relatively simple, because (1) we only seek the complete |
| 408 | end-to-end live range of each vreg, and are not interested in |
| 409 | any holes in it, and (2) the vregs are conveniently numbered 0 |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 410 | .. n_vregs-1, so we can just dump the results in a |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 411 | pre-allocated array. */ |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 412 | |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 413 | vreg_lrs = NULL; |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 414 | if (n_vregs > 0) |
| 415 | vreg_lrs = LibVEX_Alloc(sizeof(VRegLR) * n_vregs); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 416 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 417 | for (j = 0; j < n_vregs; j++) { |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 418 | vreg_lrs[j].live_after = INVALID_INSTRNO; |
| 419 | vreg_lrs[j].dead_before = INVALID_INSTRNO; |
| 420 | vreg_lrs[j].spill_offset = 0; |
| 421 | vreg_lrs[j].spill_size = 0; |
| 422 | vreg_lrs[j].reg_class = HRcINVALID; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 423 | } |
| 424 | |
| 425 | /* ------ end of SET UP TO COMPUTE VREG LIVE RANGES ------ */ |
| 426 | |
| 427 | /* ------ start of SET UP TO COMPUTE RREG LIVE RANGES ------ */ |
| 428 | |
| 429 | /* This is more complex than Stage 1, because we need to compute |
| 430 | exactly all the live ranges of all the allocatable real regs, |
| 431 | and we don't know in advance how many there will be. */ |
| 432 | |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 433 | rreg_lrs_used = 0; |
| 434 | rreg_lrs_size = 4; |
| 435 | rreg_lrs = LibVEX_Alloc(rreg_lrs_size * sizeof(RRegLR)); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 436 | |
| 437 | /* We'll need to track live range start/end points seperately for |
| 438 | each rreg. Sigh. */ |
| 439 | vassert(n_available_real_regs > 0); |
| 440 | rreg_live_after = LibVEX_Alloc(n_available_real_regs * sizeof(Int)); |
| 441 | rreg_dead_before = LibVEX_Alloc(n_available_real_regs * sizeof(Int)); |
| 442 | |
| 443 | for (j = 0; j < n_available_real_regs; j++) { |
| 444 | rreg_live_after[j] = |
| 445 | rreg_dead_before[j] = INVALID_INSTRNO; |
| 446 | } |
| 447 | |
| 448 | /* ------ end of SET UP TO COMPUTE RREG LIVE RANGES ------ */ |
| 449 | |
| 450 | /* ------ start of ITERATE OVER INSNS ------ */ |
| 451 | |
| 452 | for (ii = 0; ii < instrs_in->arr_used; ii++) { |
| 453 | |
| 454 | (*getRegUsage)( ®_usage, instrs_in->arr[ii] ); |
| 455 | |
| 456 | # if 0 |
| 457 | vex_printf("\n%d stage1: ", ii); |
| 458 | (*ppInstr)(instrs_in->arr[ii]); |
| 459 | vex_printf("\n"); |
| 460 | ppHRegUsage(®_usage); |
| 461 | # endif |
| 462 | |
| 463 | /* ------ start of DEAL WITH VREG LIVE RANGES ------ */ |
| 464 | |
| 465 | /* for each reg mentioned in the insn ... */ |
| 466 | for (j = 0; j < reg_usage.n_used; j++) { |
| 467 | |
| 468 | vreg = reg_usage.hreg[j]; |
| 469 | /* only interested in virtual registers right now. */ |
| 470 | if (!hregIsVirtual(vreg)) |
| 471 | continue; |
| 472 | k = hregNumber(vreg); |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 473 | if (k < 0 || k >= n_vregs) { |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 474 | vex_printf("\n"); |
| 475 | (*ppInstr)(instrs_in->arr[ii]); |
| 476 | vex_printf("\n"); |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 477 | vex_printf("vreg %d, n_vregs %d\n", k, n_vregs); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 478 | vpanic("doRegisterAllocation: out-of-range vreg"); |
| 479 | } |
| 480 | |
| 481 | /* Take the opportunity to note its regclass. We'll need |
| 482 | that when allocating spill slots. */ |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 483 | if (vreg_lrs[k].reg_class == HRcINVALID) { |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 484 | /* First mention of this vreg. */ |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 485 | vreg_lrs[k].reg_class = hregClass(vreg); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 486 | } else { |
| 487 | /* Seen it before, so check for consistency. */ |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 488 | vassert(vreg_lrs[k].reg_class == hregClass(vreg)); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 489 | } |
| 490 | |
| 491 | /* Now consider live ranges. */ |
| 492 | switch (reg_usage.mode[j]) { |
| 493 | case HRmRead: |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 494 | if (vreg_lrs[k].live_after == INVALID_INSTRNO) { |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 495 | vex_printf("\n\nOFFENDING VREG = %d\n", k); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 496 | vpanic("doRegisterAllocation: " |
| 497 | "first event for vreg is Read"); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 498 | } |
sewardj | 40e144d | 2005-03-28 00:46:27 +0000 | [diff] [blame] | 499 | vreg_lrs[k].dead_before = toShort(ii + 1); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 500 | break; |
| 501 | case HRmWrite: |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 502 | if (vreg_lrs[k].live_after == INVALID_INSTRNO) |
sewardj | 40e144d | 2005-03-28 00:46:27 +0000 | [diff] [blame] | 503 | vreg_lrs[k].live_after = toShort(ii); |
| 504 | vreg_lrs[k].dead_before = toShort(ii + 1); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 505 | break; |
| 506 | case HRmModify: |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 507 | if (vreg_lrs[k].live_after == INVALID_INSTRNO) { |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 508 | vex_printf("\n\nOFFENDING VREG = %d\n", k); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 509 | vpanic("doRegisterAllocation: " |
| 510 | "first event for vreg is Modify"); |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 511 | } |
sewardj | 40e144d | 2005-03-28 00:46:27 +0000 | [diff] [blame] | 512 | vreg_lrs[k].dead_before = toShort(ii + 1); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 513 | break; |
| 514 | default: |
| 515 | vpanic("doRegisterAllocation(1)"); |
| 516 | } /* switch */ |
| 517 | |
| 518 | } /* iterate over registers */ |
| 519 | |
| 520 | /* ------ end of DEAL WITH VREG LIVE RANGES ------ */ |
| 521 | |
| 522 | /* ------ start of DEAL WITH RREG LIVE RANGES ------ */ |
| 523 | |
| 524 | /* for each reg mentioned in the insn ... */ |
| 525 | for (j = 0; j < reg_usage.n_used; j++) { |
| 526 | |
| 527 | /* Dummy initialisations of flush_la and flush_db to avoid |
| 528 | possible bogus uninit-var warnings from gcc. */ |
| 529 | Int flush_la = INVALID_INSTRNO, flush_db = INVALID_INSTRNO; |
| 530 | Bool flush; |
| 531 | |
| 532 | rreg = reg_usage.hreg[j]; |
| 533 | |
| 534 | /* only interested in real registers right now. */ |
| 535 | if (hregIsVirtual(rreg)) |
| 536 | continue; |
| 537 | |
| 538 | /* Furthermore, we're not interested in this rreg unless it's |
| 539 | one of the allocatable ones. For example, it could be a |
| 540 | stack pointer register, or some other register beyond our |
| 541 | control, in which case we should just ignore it. */ |
| 542 | for (k = 0; k < n_available_real_regs; k++) |
| 543 | if (available_real_regs[k] == rreg) |
| 544 | break; |
| 545 | if (k == n_available_real_regs) |
| 546 | continue; /* not found -- ignore. */ |
| 547 | flush = False; |
| 548 | switch (reg_usage.mode[j]) { |
| 549 | case HRmWrite: |
| 550 | flush_la = rreg_live_after[k]; |
| 551 | flush_db = rreg_dead_before[k]; |
| 552 | if (flush_la != INVALID_INSTRNO |
| 553 | && flush_db != INVALID_INSTRNO) |
| 554 | flush = True; |
| 555 | rreg_live_after[k] = ii; |
| 556 | rreg_dead_before[k] = ii+1; |
| 557 | break; |
| 558 | case HRmRead: |
sewardj | 6447157 | 2005-02-09 19:13:29 +0000 | [diff] [blame] | 559 | if (rreg_live_after[k] == INVALID_INSTRNO) { |
| 560 | vex_printf("\nOFFENDING RREG = "); |
| 561 | (*ppReg)(available_real_regs[k]); |
| 562 | vex_printf("\n"); |
| 563 | vex_printf("\nOFFENDING instr = "); |
| 564 | (*ppInstr)(instrs_in->arr[ii]); |
| 565 | vex_printf("\n"); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 566 | vpanic("doRegisterAllocation: " |
| 567 | "first event for rreg is Read"); |
sewardj | 6447157 | 2005-02-09 19:13:29 +0000 | [diff] [blame] | 568 | } |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 569 | rreg_dead_before[k] = ii+1; |
| 570 | break; |
| 571 | case HRmModify: |
sewardj | 6447157 | 2005-02-09 19:13:29 +0000 | [diff] [blame] | 572 | if (rreg_live_after[k] == INVALID_INSTRNO) { |
| 573 | vex_printf("\nOFFENDING RREG = "); |
| 574 | (*ppReg)(available_real_regs[k]); |
| 575 | vex_printf("\n"); |
| 576 | vex_printf("\nOFFENDING instr = "); |
| 577 | (*ppInstr)(instrs_in->arr[ii]); |
| 578 | vex_printf("\n"); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 579 | vpanic("doRegisterAllocation: " |
| 580 | "first event for rreg is Modify"); |
sewardj | 6447157 | 2005-02-09 19:13:29 +0000 | [diff] [blame] | 581 | } |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 582 | rreg_dead_before[k] = ii+1; |
| 583 | break; |
| 584 | default: |
| 585 | vpanic("doRegisterAllocation(2)"); |
| 586 | } |
| 587 | |
| 588 | if (flush) { |
| 589 | vassert(flush_la != INVALID_INSTRNO); |
| 590 | vassert(flush_db != INVALID_INSTRNO); |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 591 | ensureRRLRspace(&rreg_lrs, &rreg_lrs_size, rreg_lrs_used); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 592 | if (0) |
| 593 | vex_printf("FLUSH 1 (%d,%d)\n", flush_la, flush_db); |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 594 | rreg_lrs[rreg_lrs_used].rreg = rreg; |
sewardj | 40e144d | 2005-03-28 00:46:27 +0000 | [diff] [blame] | 595 | rreg_lrs[rreg_lrs_used].live_after = toShort(flush_la); |
| 596 | rreg_lrs[rreg_lrs_used].dead_before = toShort(flush_db); |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 597 | rreg_lrs_used++; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 598 | } |
| 599 | |
| 600 | } /* iterate over regs in the instr */ |
| 601 | |
| 602 | /* ------ end of DEAL WITH RREG LIVE RANGES ------ */ |
| 603 | |
| 604 | } /* iterate over insns */ |
| 605 | |
| 606 | /* ------ end of ITERATE OVER INSNS ------ */ |
| 607 | |
| 608 | /* ------ start of FINALISE RREG LIVE RANGES ------ */ |
| 609 | |
| 610 | /* Now finish up any live ranges left over. */ |
| 611 | for (j = 0; j < n_available_real_regs; j++) { |
| 612 | |
| 613 | # if 0 |
| 614 | vex_printf("residual %d: %d %d\n", j, rreg_live_after[j], |
| 615 | rreg_dead_before[j]); |
| 616 | # endif |
| 617 | vassert( (rreg_live_after[j] == INVALID_INSTRNO |
| 618 | && rreg_dead_before[j] == INVALID_INSTRNO) |
| 619 | || |
| 620 | (rreg_live_after[j] != INVALID_INSTRNO |
| 621 | && rreg_dead_before[j] != INVALID_INSTRNO) |
| 622 | ); |
| 623 | |
| 624 | if (rreg_live_after[j] == INVALID_INSTRNO) |
| 625 | continue; |
| 626 | |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 627 | ensureRRLRspace(&rreg_lrs, &rreg_lrs_size, rreg_lrs_used); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 628 | if (0) |
| 629 | vex_printf("FLUSH 2 (%d,%d)\n", |
| 630 | rreg_live_after[j], rreg_dead_before[j]); |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 631 | rreg_lrs[rreg_lrs_used].rreg = available_real_regs[j]; |
sewardj | 40e144d | 2005-03-28 00:46:27 +0000 | [diff] [blame] | 632 | rreg_lrs[rreg_lrs_used].live_after = toShort(rreg_live_after[j]); |
| 633 | rreg_lrs[rreg_lrs_used].dead_before = toShort(rreg_dead_before[j]); |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 634 | rreg_lrs_used++; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 635 | } |
| 636 | |
| 637 | /* Compute summary hints for choosing real regs. If a real reg is |
| 638 | involved in a hard live range, record that fact in the fixed |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 639 | part of the running rreg_state. Later, when offered a choice between |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 640 | rregs, it's better to choose one which is not marked as having |
| 641 | any HLRs, since ones with HLRs may need to be spilled around |
| 642 | their HLRs. Correctness of final assignment is unaffected by |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 643 | this mechanism -- it is only an optimisation. */ |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 644 | |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 645 | for (j = 0; j < rreg_lrs_used; j++) { |
| 646 | rreg = rreg_lrs[j].rreg; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 647 | vassert(!hregIsVirtual(rreg)); |
| 648 | /* rreg is involved in a HLR. Record this info in the array, if |
| 649 | there is space. */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 650 | for (k = 0; k < n_rregs; k++) |
| 651 | if (rreg_state[k].rreg == rreg) |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 652 | break; |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 653 | vassert(k < n_rregs); /* else rreg was not found in rreg_state?! */ |
| 654 | rreg_state[k].has_hlrs = True; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 655 | } |
| 656 | if (0) { |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 657 | for (j = 0; j < n_rregs; j++) { |
| 658 | if (!rreg_state[j].has_hlrs) |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 659 | continue; |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 660 | ppReg(rreg_state[j].rreg); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 661 | vex_printf(" hinted\n"); |
| 662 | } |
| 663 | } |
| 664 | |
| 665 | /* ------ end of FINALISE RREG LIVE RANGES ------ */ |
| 666 | |
| 667 | # if DEBUG_REGALLOC |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 668 | for (j = 0; j < n_vregs; j++) { |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 669 | vex_printf("vreg %d: la = %d, db = %d\n", |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 670 | j, vreg_lrs[j].live_after, vreg_lrs[j].dead_before ); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 671 | } |
| 672 | # endif |
| 673 | |
| 674 | # if DEBUG_REGALLOC |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 675 | for (j = 0; j < rreg_lrs_used; j++) { |
| 676 | (*ppReg)(rreg_lrs[j].rreg); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 677 | vex_printf(" la = %d, db = %d\n", |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 678 | rreg_lrs[j].live_after, rreg_lrs[j].dead_before ); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 679 | } |
| 680 | # endif |
| 681 | |
| 682 | /* --------- Stage 3: allocate spill slots. --------- */ |
| 683 | |
| 684 | /* Each spill slot is 8 bytes long. For 128-bit vregs |
sewardj | 18fca0f | 2005-03-26 12:57:39 +0000 | [diff] [blame] | 685 | we have to allocate two spill slots. |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 686 | |
| 687 | Do a rank-based allocation of vregs to spill slot numbers. We |
| 688 | put as few values as possible in spill slows, but nevertheless |
| 689 | need to have a spill slot available for all vregs, just in case. |
| 690 | */ |
| 691 | /* max_ss_no = -1; */ |
| 692 | |
| 693 | for (j = 0; j < N_SPILL64S; j++) |
| 694 | ss_busy_until_before[j] = 0; |
| 695 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 696 | for (j = 0; j < n_vregs; j++) { |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 697 | |
| 698 | /* True iff this vreg is unused. In which case we also expect |
| 699 | that the reg_class field for it has not been set. */ |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 700 | if (vreg_lrs[j].live_after == INVALID_INSTRNO) { |
| 701 | vassert(vreg_lrs[j].reg_class == HRcINVALID); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 702 | continue; |
| 703 | } |
| 704 | |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 705 | /* The spill slots are 64 bits in size. That means, to spill a |
| 706 | Vec128-class vreg, we'll need to find two adjacent spill |
sewardj | 18fca0f | 2005-03-26 12:57:39 +0000 | [diff] [blame] | 707 | slots to use. Note, this special-casing needs to happen for |
| 708 | all 128-bit sized register classes. Currently though |
| 709 | HRcVector is the only such class. */ |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 710 | |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 711 | if (vreg_lrs[j].reg_class != HRcVec128) { |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 712 | |
| 713 | /* The ordinary case -- just find a single spill slot. */ |
| 714 | |
| 715 | /* Find the lowest-numbered spill slot which is available at |
| 716 | the start point of this interval, and assign the interval |
| 717 | to it. */ |
| 718 | for (k = 0; k < N_SPILL64S; k++) |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 719 | if (ss_busy_until_before[k] <= vreg_lrs[j].live_after) |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 720 | break; |
| 721 | if (k == N_SPILL64S) { |
| 722 | vpanic("LibVEX_N_SPILL_BYTES is too low. " |
| 723 | "Increase and recompile."); |
| 724 | } |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 725 | ss_busy_until_before[k] = vreg_lrs[j].dead_before; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 726 | |
| 727 | } else { |
| 728 | |
| 729 | /* Find two adjacent free slots in which to spill a 128-bit |
| 730 | vreg. */ |
| 731 | |
| 732 | for (k = 0; k < N_SPILL64S-1; k++) |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 733 | if (ss_busy_until_before[k] <= vreg_lrs[j].live_after |
| 734 | && ss_busy_until_before[k+1] <= vreg_lrs[j].live_after) |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 735 | break; |
| 736 | if (k == N_SPILL64S-1) { |
| 737 | vpanic("LibVEX_N_SPILL_BYTES is too low. " |
| 738 | "Increase and recompile."); |
| 739 | } |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 740 | ss_busy_until_before[k+0] = vreg_lrs[j].dead_before; |
| 741 | ss_busy_until_before[k+1] = vreg_lrs[j].dead_before; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 742 | |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 743 | } |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 744 | |
| 745 | /* This reflects LibVEX's hard-wired knowledge of the baseBlock |
| 746 | layout: the guest state, then an equal sized area following |
| 747 | it for shadow state, and then the spill area. */ |
sewardj | 40e144d | 2005-03-28 00:46:27 +0000 | [diff] [blame] | 748 | vreg_lrs[j].spill_offset = toShort(guest_sizeB * 2 + k * 8); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 749 | |
| 750 | /* if (j > max_ss_no) */ |
| 751 | /* max_ss_no = j; */ |
| 752 | } |
| 753 | |
| 754 | # if 0 |
| 755 | vex_printf("\n\n"); |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 756 | for (j = 0; j < n_vregs; j++) |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 757 | vex_printf("vreg %d --> spill offset %d\n", |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 758 | j, vreg_lrs[j].spill_offset); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 759 | # endif |
| 760 | |
| 761 | /* --------- Stage 4: establish rreg preferences --------- */ |
| 762 | |
| 763 | /* It may be advantageous to allocating certain vregs to specific |
| 764 | rregs, as a way of avoiding reg-reg moves later. Here we |
| 765 | establish which, if any, rreg each vreg would prefer to be in. |
| 766 | Note that this constrains the allocator -- ideally we end up |
sewardj | 2fa60a3 | 2004-10-30 22:23:53 +0000 | [diff] [blame] | 767 | with as few as possible vregs expressing a preference. |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 768 | |
sewardj | 2fa60a3 | 2004-10-30 22:23:53 +0000 | [diff] [blame] | 769 | This is an optimisation: if the .preferred_rreg field is never |
| 770 | set to anything different from INVALID_HREG, the allocator still |
| 771 | works. */ |
sewardj | 17bbc21 | 2004-12-30 00:14:54 +0000 | [diff] [blame] | 772 | |
| 773 | /* 30 Dec 04: removed this mechanism as it does not seem to |
| 774 | help. */ |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 775 | |
| 776 | /* --------- Stage 5: process instructions --------- */ |
| 777 | |
| 778 | /* This is the main loop of the allocator. First, we need to |
| 779 | correctly set up our running state, which tracks the status of |
| 780 | each real register. */ |
| 781 | |
| 782 | /* ------ BEGIN: Process each insn in turn. ------ */ |
| 783 | |
| 784 | for (ii = 0; ii < instrs_in->arr_used; ii++) { |
| 785 | |
| 786 | # if DEBUG_REGALLOC |
| 787 | vex_printf("\n====----====---- Insn %d ----====----====\n", ii); |
| 788 | vex_printf("---- "); |
| 789 | (*ppInstr)(instrs_in->arr[ii]); |
| 790 | vex_printf("\n\nInitial state:\n"); |
| 791 | PRINT_STATE; |
| 792 | vex_printf("\n"); |
| 793 | # endif |
| 794 | |
| 795 | /* ------------ Sanity checks ------------ */ |
| 796 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 797 | /* Sanity checks are expensive. So they are done only once |
| 798 | every 7 instructions, and just before the last |
| 799 | instruction. */ |
| 800 | do_sanity_check |
| 801 | = toBool( |
| 802 | False /* Set to True for sanity checking of all insns. */ |
| 803 | || ii == instrs_in->arr_used-1 |
| 804 | || (ii > 0 && (ii % 7) == 0) |
| 805 | ); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 806 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 807 | if (do_sanity_check) { |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 808 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 809 | /* Sanity check 1: all rregs with a hard live range crossing |
| 810 | this insn must be marked as unavailable in the running |
| 811 | state. */ |
| 812 | for (j = 0; j < rreg_lrs_used; j++) { |
| 813 | if (rreg_lrs[j].live_after < ii |
| 814 | && ii < rreg_lrs[j].dead_before) { |
| 815 | /* ii is the middle of a hard live range for some real |
| 816 | reg. Check it's marked as such in the running |
| 817 | state. */ |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 818 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 819 | # if 0 |
| 820 | vex_printf("considering la %d .. db %d reg = ", |
| 821 | rreg_lrs[j].live_after, |
| 822 | rreg_lrs[j].dead_before); |
| 823 | (*ppReg)(rreg_lrs[j].rreg); |
| 824 | vex_printf("\n"); |
| 825 | # endif |
| 826 | |
| 827 | /* find the state entry for this rreg */ |
| 828 | for (k = 0; k < n_rregs; k++) |
| 829 | if (rreg_state[k].rreg == rreg_lrs[j].rreg) |
| 830 | break; |
| 831 | |
| 832 | /* and assert that this rreg is marked as unavailable */ |
| 833 | vassert(rreg_state[k].disp == Unavail); |
| 834 | } |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 835 | } |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 836 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 837 | /* Sanity check 2: conversely, all rregs marked as |
| 838 | unavailable in the running rreg_state must have a |
| 839 | corresponding hard live range entry in the rreg_lrs |
| 840 | array. */ |
| 841 | for (j = 0; j < n_available_real_regs; j++) { |
| 842 | vassert(rreg_state[j].disp == Bound |
| 843 | || rreg_state[j].disp == Free |
| 844 | || rreg_state[j].disp == Unavail); |
| 845 | if (rreg_state[j].disp != Unavail) |
| 846 | continue; |
| 847 | for (k = 0; k < rreg_lrs_used; k++) |
| 848 | if (rreg_lrs[k].rreg == rreg_state[j].rreg |
| 849 | && rreg_lrs[k].live_after < ii |
| 850 | && ii < rreg_lrs[k].dead_before) |
| 851 | break; |
| 852 | /* If this vassertion fails, we couldn't find a |
| 853 | corresponding HLR. */ |
| 854 | vassert(k < rreg_lrs_used); |
| 855 | } |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 856 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 857 | /* Sanity check 3: all vreg-rreg bindings must bind registers |
| 858 | of the same class. */ |
| 859 | for (j = 0; j < n_rregs; j++) { |
| 860 | if (rreg_state[j].disp != Bound) |
| 861 | continue; |
| 862 | vassert(hregClass(rreg_state[j].rreg) |
| 863 | == hregClass(rreg_state[j].vreg)); |
| 864 | vassert( hregIsVirtual(rreg_state[j].vreg)); |
| 865 | vassert(!hregIsVirtual(rreg_state[j].rreg)); |
| 866 | } |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 867 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 868 | /* Sanity check 4: the vreg_state and rreg_state |
| 869 | mutually-redundant mappings are consistent. If |
| 870 | rreg_state[j].vreg points at some vreg_state entry then |
| 871 | that vreg_state entry should point back at |
| 872 | rreg_state[j]. */ |
| 873 | for (j = 0; j < n_rregs; j++) { |
| 874 | if (rreg_state[j].disp != Bound) |
| 875 | continue; |
| 876 | k = hregNumber(rreg_state[j].vreg); |
| 877 | vassert(IS_VALID_VREGNO(k)); |
| 878 | vassert(vreg_state[k] == j); |
| 879 | } |
| 880 | for (j = 0; j < n_vregs; j++) { |
| 881 | k = vreg_state[j]; |
| 882 | if (k == INVALID_RREG_NO) |
| 883 | continue; |
| 884 | vassert(IS_VALID_RREGNO(k)); |
| 885 | vassert(rreg_state[k].disp == Bound); |
| 886 | vassert(hregNumber(rreg_state[k].vreg) == j); |
| 887 | } |
| 888 | |
| 889 | } /* if (do_sanity_check) */ |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 890 | |
| 891 | /* ------------ end of Sanity checks ------------ */ |
| 892 | |
| 893 | /* Do various optimisations pertaining to register coalescing |
| 894 | and preferencing: |
| 895 | MOV v <-> v coalescing (done here). |
| 896 | MOV v <-> r coalescing (not yet, if ever) |
| 897 | */ |
| 898 | /* If doing a reg-reg move between two vregs, and the src's live |
| 899 | range ends here and the dst's live range starts here, bind |
| 900 | the dst to the src's rreg, and that's all. */ |
| 901 | if ( (*isMove)( instrs_in->arr[ii], &vregS, &vregD ) ) { |
| 902 | if (!hregIsVirtual(vregS)) goto cannot_coalesce; |
| 903 | if (!hregIsVirtual(vregD)) goto cannot_coalesce; |
| 904 | /* Check that *isMove is not telling us a bunch of lies ... */ |
| 905 | vassert(hregClass(vregS) == hregClass(vregD)); |
| 906 | k = hregNumber(vregS); |
| 907 | m = hregNumber(vregD); |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 908 | vassert(IS_VALID_VREGNO(k)); |
| 909 | vassert(IS_VALID_VREGNO(m)); |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 910 | if (vreg_lrs[k].dead_before != ii + 1) goto cannot_coalesce; |
| 911 | if (vreg_lrs[m].live_after != ii) goto cannot_coalesce; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 912 | # if DEBUG_REGALLOC |
| 913 | vex_printf("COALESCE "); |
| 914 | (*ppReg)(vregS); |
| 915 | vex_printf(" -> "); |
| 916 | (*ppReg)(vregD); |
| 917 | vex_printf("\n\n"); |
| 918 | # endif |
| 919 | /* Find the state entry for vregS. */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 920 | for (m = 0; m < n_rregs; m++) |
| 921 | if (rreg_state[m].disp == Bound && rreg_state[m].vreg == vregS) |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 922 | break; |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 923 | if (m == n_rregs) |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 924 | /* We failed to find a binding for vregS, which means it's |
| 925 | currently not in a register. So we can't do the |
| 926 | coalescing. Give up. */ |
| 927 | goto cannot_coalesce; |
| 928 | |
| 929 | /* Finally, we can do the coalescing. It's trivial -- merely |
| 930 | claim vregS's register for vregD. */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 931 | rreg_state[m].vreg = vregD; |
| 932 | vassert(IS_VALID_VREGNO(hregNumber(vregD))); |
| 933 | vassert(IS_VALID_VREGNO(hregNumber(vregS))); |
sewardj | d4d3dd6 | 2005-07-04 10:08:24 +0000 | [diff] [blame] | 934 | vreg_state[hregNumber(vregD)] = toShort(m); |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 935 | vreg_state[hregNumber(vregS)] = INVALID_RREG_NO; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 936 | |
| 937 | /* Move on to the next insn. We skip the post-insn stuff for |
| 938 | fixed registers, since this move should not interact with |
| 939 | them in any way. */ |
| 940 | continue; |
| 941 | } |
| 942 | cannot_coalesce: |
| 943 | |
| 944 | /* ------ Free up rregs bound to dead vregs ------ */ |
| 945 | |
| 946 | /* Look for vregs whose live range has just ended, and |
| 947 | mark the associated rreg as free. */ |
| 948 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 949 | for (j = 0; j < n_rregs; j++) { |
| 950 | if (rreg_state[j].disp != Bound) |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 951 | continue; |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 952 | vreg = hregNumber(rreg_state[j].vreg); |
| 953 | vassert(IS_VALID_VREGNO(vreg)); |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 954 | if (vreg_lrs[vreg].dead_before <= ii) { |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 955 | rreg_state[j].disp = Free; |
| 956 | m = hregNumber(rreg_state[j].vreg); |
| 957 | vassert(IS_VALID_VREGNO(m)); |
| 958 | vreg_state[m] = INVALID_RREG_NO; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 959 | if (DEBUG_REGALLOC) { |
| 960 | vex_printf("free up "); |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 961 | (*ppReg)(rreg_state[j].rreg); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 962 | vex_printf("\n"); |
| 963 | } |
| 964 | } |
| 965 | } |
| 966 | |
| 967 | /* ------ Pre-instruction actions for fixed rreg uses ------ */ |
| 968 | |
| 969 | /* Now we have to deal with rregs which are about to be made |
| 970 | live by this instruction -- in other words, are entering into |
| 971 | one of their live ranges. If any such rreg holds a vreg, we |
| 972 | will have to free up the rreg. The simplest solution which |
| 973 | is correct is to spill the rreg. |
| 974 | |
| 975 | Note we could do better: |
| 976 | * Could move it into some other free rreg, if one is available |
| 977 | |
| 978 | Simplest way to do this is to iterate over the collection |
| 979 | of rreg live ranges. |
| 980 | */ |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 981 | for (j = 0; j < rreg_lrs_used; j++) { |
| 982 | if (rreg_lrs[j].live_after == ii) { |
| 983 | /* rreg_lrs[j].rreg needs to be freed up. Find |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 984 | the associated rreg_state entry. */ |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 985 | /* Note, re rreg_lrs[j].live_after == ii. Real register |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 986 | live ranges are guaranteed to be well-formed in that |
| 987 | they start with a write to the register -- Stage 2 |
| 988 | rejects any code not satisfying this. So the correct |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 989 | question to ask is whether rreg_lrs[j].live_after == |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 990 | ii, that is, whether the reg becomes live after this |
| 991 | insn -- rather than before it. */ |
| 992 | # if DEBUG_REGALLOC |
| 993 | vex_printf("need to free up rreg: "); |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 994 | (*ppReg)(rreg_lrs[j].rreg); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 995 | vex_printf("\n\n"); |
| 996 | # endif |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 997 | for (k = 0; k < n_rregs; k++) |
| 998 | if (rreg_state[k].rreg == rreg_lrs[j].rreg) |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 999 | break; |
| 1000 | /* If this fails, we don't have an entry for this rreg. |
| 1001 | Which we should. */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1002 | vassert(IS_VALID_RREGNO(k)); |
| 1003 | m = hregNumber(rreg_state[k].vreg); |
| 1004 | if (rreg_state[k].disp == Bound) { |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1005 | /* Yes, there is an associated vreg. Spill it if it's |
| 1006 | still live. */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1007 | vassert(IS_VALID_VREGNO(m)); |
| 1008 | vreg_state[m] = INVALID_RREG_NO; |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 1009 | if (vreg_lrs[m].dead_before > ii) { |
| 1010 | vassert(vreg_lrs[m].reg_class != HRcINVALID); |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1011 | EMIT_INSTR( (*genSpill)( rreg_state[k].rreg, |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 1012 | vreg_lrs[m].spill_offset ) ); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1013 | } |
| 1014 | } |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1015 | rreg_state[k].disp = Unavail; |
| 1016 | rreg_state[k].vreg = INVALID_HREG; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1017 | } |
| 1018 | } |
| 1019 | |
| 1020 | # if DEBUG_REGALLOC |
| 1021 | vex_printf("After pre-insn actions for fixed regs:\n"); |
| 1022 | PRINT_STATE; |
| 1023 | vex_printf("\n"); |
| 1024 | # endif |
| 1025 | |
| 1026 | |
| 1027 | /* ------ Deal with the current instruction. ------ */ |
| 1028 | |
| 1029 | /* Finally we can begin the processing of this instruction |
| 1030 | itself. The aim is to free up enough rregs for this insn. |
| 1031 | This may generate spill stores since we may have to evict |
| 1032 | some vregs currently in rregs. Also generates spill loads. |
| 1033 | We also build up the final vreg->rreg mapping to be applied |
| 1034 | to the insn. */ |
| 1035 | |
| 1036 | (*getRegUsage)( ®_usage, instrs_in->arr[ii] ); |
| 1037 | |
| 1038 | initHRegRemap(&remap); |
| 1039 | |
| 1040 | /* for each reg mentioned in the insn ... */ |
| 1041 | for (j = 0; j < reg_usage.n_used; j++) { |
| 1042 | |
| 1043 | vreg = reg_usage.hreg[j]; |
| 1044 | |
| 1045 | /* only interested in virtual registers right now. */ |
| 1046 | if (!hregIsVirtual(vreg)) |
| 1047 | continue; |
| 1048 | |
| 1049 | # if 0 |
| 1050 | vex_printf("considering "); (*ppReg)(vreg); vex_printf("\n"); |
| 1051 | # endif |
| 1052 | |
| 1053 | /* Now we're trying to find a rreg for "vreg". First of all, |
| 1054 | if it already has an rreg assigned, we don't need to do |
| 1055 | anything more. Search the current state to find out. */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1056 | m = hregNumber(vreg); |
| 1057 | vassert(IS_VALID_VREGNO(m)); |
| 1058 | k = vreg_state[m]; |
| 1059 | if (IS_VALID_RREGNO(k)) { |
| 1060 | vassert(rreg_state[k].disp == Bound); |
| 1061 | addToHRegRemap(&remap, vreg, rreg_state[k].rreg); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1062 | continue; |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1063 | } else { |
| 1064 | vassert(k == INVALID_RREG_NO); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1065 | } |
| 1066 | |
| 1067 | /* No luck. The next thing to do is see if there is a |
| 1068 | currently free rreg available, of the correct class. If |
| 1069 | so, bag it. NOTE, we could improve this by selecting an |
| 1070 | rreg for which the next live-range event is as far ahead |
| 1071 | as possible. */ |
| 1072 | k_suboptimal = -1; |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1073 | for (k = 0; k < n_rregs; k++) { |
| 1074 | if (rreg_state[k].disp != Free |
| 1075 | || hregClass(rreg_state[k].rreg) != hregClass(vreg)) |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1076 | continue; |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1077 | if (rreg_state[k].has_hlrs) { |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1078 | /* Well, at least we can use k_suboptimal if we really |
| 1079 | have to. Keep on looking for a better candidate. */ |
| 1080 | k_suboptimal = k; |
| 1081 | } else { |
| 1082 | /* Found a preferable reg. Use it. */ |
| 1083 | k_suboptimal = -1; |
| 1084 | break; |
| 1085 | } |
| 1086 | } |
| 1087 | if (k_suboptimal >= 0) |
| 1088 | k = k_suboptimal; |
| 1089 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1090 | if (k < n_rregs) { |
| 1091 | rreg_state[k].disp = Bound; |
| 1092 | rreg_state[k].vreg = vreg; |
| 1093 | m = hregNumber(vreg); |
| 1094 | vassert(IS_VALID_VREGNO(m)); |
sewardj | d4d3dd6 | 2005-07-04 10:08:24 +0000 | [diff] [blame] | 1095 | vreg_state[m] = toShort(k); |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1096 | addToHRegRemap(&remap, vreg, rreg_state[k].rreg); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1097 | /* Generate a reload if needed. */ |
| 1098 | if (reg_usage.mode[j] != HRmWrite) { |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 1099 | vassert(vreg_lrs[m].reg_class != HRcINVALID); |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1100 | EMIT_INSTR( (*genReload)( rreg_state[k].rreg, |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 1101 | vreg_lrs[m].spill_offset ) ); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1102 | } |
| 1103 | continue; |
| 1104 | } |
| 1105 | |
| 1106 | /* Well, now we have no option but to spill a vreg. It's |
| 1107 | important to make a good choice of vreg to spill, and of |
| 1108 | course we need to be careful not to spill a vreg which is |
| 1109 | needed by this insn. */ |
| 1110 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1111 | /* First, mark in the rreg_state, those rregs which are not spill |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1112 | candidates, due to holding a vreg mentioned by this |
| 1113 | instruction. Or being of the wrong class. */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1114 | for (k = 0; k < n_rregs; k++) { |
| 1115 | rreg_state[k].is_spill_cand = False; |
| 1116 | if (rreg_state[k].disp != Bound) |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1117 | continue; |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1118 | if (hregClass(rreg_state[k].rreg) != hregClass(vreg)) |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1119 | continue; |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1120 | rreg_state[k].is_spill_cand = True; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1121 | for (m = 0; m < reg_usage.n_used; m++) { |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1122 | if (rreg_state[k].vreg == reg_usage.hreg[m]) { |
| 1123 | rreg_state[k].is_spill_cand = False; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1124 | break; |
| 1125 | } |
| 1126 | } |
| 1127 | } |
| 1128 | |
| 1129 | /* We can choose to spill any rreg satisfying |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1130 | rreg_state[r].is_spill_cand (so to speak). Choose r so that |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1131 | the next use of its associated vreg is as far ahead as |
| 1132 | possible, in the hope that this will minimise the number |
| 1133 | of consequent reloads required. */ |
| 1134 | spillee |
| 1135 | = findMostDistantlyMentionedVReg ( |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1136 | getRegUsage, instrs_in, ii+1, rreg_state, n_rregs ); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1137 | |
| 1138 | if (spillee == -1) { |
| 1139 | /* Hmmmmm. There don't appear to be any spill candidates. |
| 1140 | We're hosed. */ |
| 1141 | vex_printf("reg_alloc: can't find a register in class: "); |
| 1142 | ppHRegClass(hregClass(vreg)); |
| 1143 | vex_printf("\n"); |
| 1144 | vpanic("reg_alloc: can't create a free register."); |
| 1145 | } |
| 1146 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1147 | /* Right. So we're going to spill rreg_state[spillee]. */ |
| 1148 | vassert(IS_VALID_RREGNO(spillee)); |
| 1149 | vassert(rreg_state[spillee].disp == Bound); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1150 | /* check it's the right class */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1151 | vassert(hregClass(rreg_state[spillee].rreg) == hregClass(vreg)); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1152 | /* check we're not ejecting the vreg for which we are trying |
| 1153 | to free up a register. */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1154 | vassert(rreg_state[spillee].vreg != vreg); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1155 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1156 | m = hregNumber(rreg_state[spillee].vreg); |
| 1157 | vassert(IS_VALID_VREGNO(m)); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1158 | |
| 1159 | /* So here's the spill store. Assert that we're spilling a |
| 1160 | live vreg. */ |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 1161 | vassert(vreg_lrs[m].dead_before > ii); |
| 1162 | vassert(vreg_lrs[m].reg_class != HRcINVALID); |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1163 | EMIT_INSTR( (*genSpill)( rreg_state[spillee].rreg, |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 1164 | vreg_lrs[m].spill_offset ) ); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1165 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1166 | /* Update the rreg_state to reflect the new assignment for this |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1167 | rreg. */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1168 | rreg_state[spillee].vreg = vreg; |
| 1169 | vreg_state[m] = INVALID_RREG_NO; |
| 1170 | |
| 1171 | m = hregNumber(vreg); |
| 1172 | vassert(IS_VALID_VREGNO(m)); |
sewardj | d4d3dd6 | 2005-07-04 10:08:24 +0000 | [diff] [blame] | 1173 | vreg_state[m] = toShort(spillee); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1174 | |
| 1175 | /* Now, if this vreg is being read or modified (as opposed to |
| 1176 | written), we have to generate a reload for it. */ |
| 1177 | if (reg_usage.mode[j] != HRmWrite) { |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 1178 | vassert(vreg_lrs[m].reg_class != HRcINVALID); |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1179 | EMIT_INSTR( (*genReload)( rreg_state[spillee].rreg, |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 1180 | vreg_lrs[m].spill_offset ) ); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1181 | } |
| 1182 | |
| 1183 | /* So after much twisting and turning, we have vreg mapped to |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1184 | rreg_state[furthest_k].rreg. Note that in the map. */ |
| 1185 | addToHRegRemap(&remap, vreg, rreg_state[spillee].rreg); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1186 | |
| 1187 | } /* iterate over registers in this instruction. */ |
| 1188 | |
| 1189 | /* We've finished clowning around with registers in this instruction. |
| 1190 | Three results: |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1191 | - the running rreg_state[] has been updated |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1192 | - a suitable vreg->rreg mapping for this instruction has been |
| 1193 | constructed |
| 1194 | - spill and reload instructions may have been emitted. |
| 1195 | |
| 1196 | The final step is to apply the mapping to the instruction, |
| 1197 | and emit that. |
| 1198 | */ |
| 1199 | |
| 1200 | /* NOTE, DESTRUCTIVELY MODIFIES instrs_in->arr[ii]. */ |
| 1201 | (*mapRegs)( &remap, instrs_in->arr[ii] ); |
| 1202 | EMIT_INSTR( instrs_in->arr[ii] ); |
| 1203 | |
| 1204 | # if DEBUG_REGALLOC |
| 1205 | vex_printf("After dealing with current insn:\n"); |
| 1206 | PRINT_STATE; |
| 1207 | vex_printf("\n"); |
| 1208 | # endif |
| 1209 | |
| 1210 | /* ------ Post-instruction actions for fixed rreg uses ------ */ |
| 1211 | |
| 1212 | /* Now we need to check for rregs exiting fixed live ranges |
| 1213 | after this instruction, and if so mark them as free. */ |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 1214 | for (j = 0; j < rreg_lrs_used; j++) { |
| 1215 | if (rreg_lrs[j].dead_before == ii+1) { |
| 1216 | /* rreg_lrs[j].rreg is exiting a hard live range. Mark |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1217 | it as such in the main rreg_state array. */ |
| 1218 | for (k = 0; k < n_rregs; k++) |
| 1219 | if (rreg_state[k].rreg == rreg_lrs[j].rreg) |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1220 | break; |
| 1221 | /* If this vassertion fails, we don't have an entry for |
| 1222 | this rreg. Which we should. */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1223 | vassert(k < n_rregs); |
| 1224 | vassert(rreg_state[k].disp == Unavail); |
| 1225 | rreg_state[k].disp = Free; |
| 1226 | rreg_state[k].vreg = INVALID_HREG; |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1227 | } |
| 1228 | } |
| 1229 | |
| 1230 | # if DEBUG_REGALLOC |
| 1231 | vex_printf("After post-insn actions for fixed regs:\n"); |
| 1232 | PRINT_STATE; |
| 1233 | vex_printf("\n"); |
| 1234 | # endif |
| 1235 | |
| 1236 | } /* iterate over insns */ |
| 1237 | |
| 1238 | /* ------ END: Process each insn in turn. ------ */ |
| 1239 | |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1240 | /* free(rreg_state); */ |
sewardj | ad572dd | 2004-12-30 01:44:51 +0000 | [diff] [blame] | 1241 | /* free(rreg_lrs); */ |
| 1242 | /* if (vreg_lrs) free(vreg_lrs); */ |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1243 | |
| 1244 | /* Paranoia */ |
sewardj | ee7d228 | 2005-07-04 09:38:58 +0000 | [diff] [blame] | 1245 | for (j = 0; j < n_rregs; j++) |
| 1246 | vassert(rreg_state[j].rreg == available_real_regs[j]); |
sewardj | 432b1c9 | 2004-10-30 13:00:55 +0000 | [diff] [blame] | 1247 | |
| 1248 | return instrs_out; |
| 1249 | |
| 1250 | # undef INVALID_INSTRNO |
| 1251 | # undef EMIT_INSTR |
| 1252 | # undef PRINT_STATE |
| 1253 | } |
| 1254 | |
| 1255 | |
| 1256 | |
| 1257 | /*---------------------------------------------------------------*/ |
| 1258 | /*--- host-generic/reg_alloc2.c ---*/ |
| 1259 | /*---------------------------------------------------------------*/ |