njn | c953984 | 2002-10-02 13:26:35 +0000 | [diff] [blame] | 1 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2 | /*--------------------------------------------------------------------*/ |
njn | c953984 | 2002-10-02 13:26:35 +0000 | [diff] [blame] | 3 | /*--- MemCheck: Maintain bitmaps of memory, tracking the ---*/ |
| 4 | /*--- accessibility (A) and validity (V) status of each byte. ---*/ |
njn25 | cac76cb | 2002-09-23 11:21:57 +0000 | [diff] [blame] | 5 | /*--- mc_main.c ---*/ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 6 | /*--------------------------------------------------------------------*/ |
| 7 | |
| 8 | /* |
nethercote | 137bc55 | 2003-11-14 17:47:54 +0000 | [diff] [blame] | 9 | This file is part of MemCheck, a heavyweight Valgrind tool for |
njn | c953984 | 2002-10-02 13:26:35 +0000 | [diff] [blame] | 10 | detecting memory errors. |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 11 | |
nethercote | bb1c991 | 2004-01-04 16:43:23 +0000 | [diff] [blame] | 12 | Copyright (C) 2000-2004 Julian Seward |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 13 | jseward@acm.org |
| 14 | |
| 15 | This program is free software; you can redistribute it and/or |
| 16 | modify it under the terms of the GNU General Public License as |
| 17 | published by the Free Software Foundation; either version 2 of the |
| 18 | License, or (at your option) any later version. |
| 19 | |
| 20 | This program is distributed in the hope that it will be useful, but |
| 21 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 23 | General Public License for more details. |
| 24 | |
| 25 | You should have received a copy of the GNU General Public License |
| 26 | along with this program; if not, write to the Free Software |
| 27 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 28 | 02111-1307, USA. |
| 29 | |
| 30 | The GNU General Public License is contained in the file COPYING. |
| 31 | */ |
| 32 | |
njn25 | cac76cb | 2002-09-23 11:21:57 +0000 | [diff] [blame] | 33 | #include "mc_include.h" |
| 34 | #include "memcheck.h" /* for client requests */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 35 | //#include "vg_profile.c" |
| 36 | |
| 37 | /* Define to debug the mem audit system. */ |
| 38 | /* #define VG_DEBUG_MEMORY */ |
| 39 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 40 | #define DEBUG(fmt, args...) //VG_(printf)(fmt, ## args) |
| 41 | |
| 42 | /*------------------------------------------------------------*/ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 43 | /*--- Low-level support for memory checking. ---*/ |
| 44 | /*------------------------------------------------------------*/ |
| 45 | |
| 46 | /* All reads and writes are checked against a memory map, which |
| 47 | records the state of all memory in the process. The memory map is |
| 48 | organised like this: |
| 49 | |
| 50 | The top 16 bits of an address are used to index into a top-level |
| 51 | map table, containing 65536 entries. Each entry is a pointer to a |
| 52 | second-level map, which records the accesibililty and validity |
| 53 | permissions for the 65536 bytes indexed by the lower 16 bits of the |
| 54 | address. Each byte is represented by nine bits, one indicating |
| 55 | accessibility, the other eight validity. So each second-level map |
| 56 | contains 73728 bytes. This two-level arrangement conveniently |
| 57 | divides the 4G address space into 64k lumps, each size 64k bytes. |
| 58 | |
| 59 | All entries in the primary (top-level) map must point to a valid |
| 60 | secondary (second-level) map. Since most of the 4G of address |
| 61 | space will not be in use -- ie, not mapped at all -- there is a |
| 62 | distinguished secondary map, which indicates `not addressible and |
| 63 | not valid' writeable for all bytes. Entries in the primary map for |
| 64 | which the entire 64k is not in use at all point at this |
| 65 | distinguished map. |
| 66 | |
| 67 | [...] lots of stuff deleted due to out of date-ness |
| 68 | |
| 69 | As a final optimisation, the alignment and address checks for |
| 70 | 4-byte loads and stores are combined in a neat way. The primary |
| 71 | map is extended to have 262144 entries (2^18), rather than 2^16. |
| 72 | The top 3/4 of these entries are permanently set to the |
| 73 | distinguished secondary map. For a 4-byte load/store, the |
| 74 | top-level map is indexed not with (addr >> 16) but instead f(addr), |
| 75 | where |
| 76 | |
| 77 | f( XXXX XXXX XXXX XXXX ____ ____ ____ __YZ ) |
| 78 | = ____ ____ ____ __YZ XXXX XXXX XXXX XXXX or |
| 79 | = ____ ____ ____ __ZY XXXX XXXX XXXX XXXX |
| 80 | |
| 81 | ie the lowest two bits are placed above the 16 high address bits. |
| 82 | If either of these two bits are nonzero, the address is misaligned; |
| 83 | this will select a secondary map from the upper 3/4 of the primary |
| 84 | map. Because this is always the distinguished secondary map, a |
| 85 | (bogus) address check failure will result. The failure handling |
| 86 | code can then figure out whether this is a genuine addr check |
| 87 | failure or whether it is a possibly-legitimate access at a |
| 88 | misaligned address. |
| 89 | */ |
| 90 | |
| 91 | |
| 92 | /*------------------------------------------------------------*/ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 93 | /*--- Function declarations. ---*/ |
| 94 | /*------------------------------------------------------------*/ |
| 95 | |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 96 | static UInt mc_rd_V4_SLOWLY ( Addr a ); |
| 97 | static UInt mc_rd_V2_SLOWLY ( Addr a ); |
| 98 | static UInt mc_rd_V1_SLOWLY ( Addr a ); |
| 99 | static void mc_wr_V4_SLOWLY ( Addr a, UInt vbytes ); |
| 100 | static void mc_wr_V2_SLOWLY ( Addr a, UInt vbytes ); |
| 101 | static void mc_wr_V1_SLOWLY ( Addr a, UInt vbytes ); |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 102 | static void mc_fpu_read_check_SLOWLY ( Addr addr, SizeT size ); |
| 103 | static void mc_fpu_write_check_SLOWLY ( Addr addr, SizeT size ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 104 | |
| 105 | /*------------------------------------------------------------*/ |
| 106 | /*--- Data defns. ---*/ |
| 107 | /*------------------------------------------------------------*/ |
| 108 | |
| 109 | typedef |
| 110 | struct { |
| 111 | UChar abits[8192]; |
| 112 | UChar vbyte[65536]; |
| 113 | } |
| 114 | SecMap; |
| 115 | |
| 116 | static SecMap* primary_map[ /*65536*/ 262144 ]; |
| 117 | static SecMap distinguished_secondary_map; |
| 118 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 119 | static void init_shadow_memory ( void ) |
| 120 | { |
| 121 | Int i; |
| 122 | |
| 123 | for (i = 0; i < 8192; i++) /* Invalid address */ |
| 124 | distinguished_secondary_map.abits[i] = VGM_BYTE_INVALID; |
| 125 | for (i = 0; i < 65536; i++) /* Invalid Value */ |
| 126 | distinguished_secondary_map.vbyte[i] = VGM_BYTE_INVALID; |
| 127 | |
| 128 | /* These entries gradually get overwritten as the used address |
| 129 | space expands. */ |
| 130 | for (i = 0; i < 65536; i++) |
| 131 | primary_map[i] = &distinguished_secondary_map; |
| 132 | |
| 133 | /* These ones should never change; it's a bug in Valgrind if they do. */ |
| 134 | for (i = 65536; i < 262144; i++) |
| 135 | primary_map[i] = &distinguished_secondary_map; |
| 136 | } |
| 137 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 138 | /*------------------------------------------------------------*/ |
| 139 | /*--- Basic bitmap management, reading and writing. ---*/ |
| 140 | /*------------------------------------------------------------*/ |
| 141 | |
| 142 | /* Allocate and initialise a secondary map. */ |
| 143 | |
| 144 | static SecMap* alloc_secondary_map ( __attribute__ ((unused)) |
| 145 | Char* caller ) |
| 146 | { |
| 147 | SecMap* map; |
| 148 | UInt i; |
| 149 | PROF_EVENT(10); |
| 150 | |
| 151 | /* Mark all bytes as invalid access and invalid value. */ |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 152 | map = (SecMap *)VG_(shadow_alloc)(sizeof(SecMap)); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 153 | |
| 154 | for (i = 0; i < 8192; i++) |
| 155 | map->abits[i] = VGM_BYTE_INVALID; /* Invalid address */ |
| 156 | for (i = 0; i < 65536; i++) |
| 157 | map->vbyte[i] = VGM_BYTE_INVALID; /* Invalid Value */ |
| 158 | |
| 159 | /* VG_(printf)("ALLOC_2MAP(%s)\n", caller ); */ |
| 160 | return map; |
| 161 | } |
| 162 | |
| 163 | |
| 164 | /* Basic reading/writing of the bitmaps, for byte-sized accesses. */ |
| 165 | |
| 166 | static __inline__ UChar get_abit ( Addr a ) |
| 167 | { |
| 168 | SecMap* sm = primary_map[a >> 16]; |
| 169 | UInt sm_off = a & 0xFFFF; |
| 170 | PROF_EVENT(20); |
| 171 | # if 0 |
| 172 | if (IS_DISTINGUISHED_SM(sm)) |
| 173 | VG_(message)(Vg_DebugMsg, |
| 174 | "accessed distinguished 2ndary (A)map! 0x%x\n", a); |
| 175 | # endif |
| 176 | return BITARR_TEST(sm->abits, sm_off) |
| 177 | ? VGM_BIT_INVALID : VGM_BIT_VALID; |
| 178 | } |
| 179 | |
| 180 | static __inline__ UChar get_vbyte ( Addr a ) |
| 181 | { |
| 182 | SecMap* sm = primary_map[a >> 16]; |
| 183 | UInt sm_off = a & 0xFFFF; |
| 184 | PROF_EVENT(21); |
| 185 | # if 0 |
| 186 | if (IS_DISTINGUISHED_SM(sm)) |
| 187 | VG_(message)(Vg_DebugMsg, |
| 188 | "accessed distinguished 2ndary (V)map! 0x%x\n", a); |
| 189 | # endif |
| 190 | return sm->vbyte[sm_off]; |
| 191 | } |
| 192 | |
sewardj | 5686735 | 2003-10-12 10:27:06 +0000 | [diff] [blame] | 193 | static /* __inline__ */ void set_abit ( Addr a, UChar abit ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 194 | { |
| 195 | SecMap* sm; |
| 196 | UInt sm_off; |
| 197 | PROF_EVENT(22); |
| 198 | ENSURE_MAPPABLE(a, "set_abit"); |
| 199 | sm = primary_map[a >> 16]; |
| 200 | sm_off = a & 0xFFFF; |
| 201 | if (abit) |
| 202 | BITARR_SET(sm->abits, sm_off); |
| 203 | else |
| 204 | BITARR_CLEAR(sm->abits, sm_off); |
| 205 | } |
| 206 | |
| 207 | static __inline__ void set_vbyte ( Addr a, UChar vbyte ) |
| 208 | { |
| 209 | SecMap* sm; |
| 210 | UInt sm_off; |
| 211 | PROF_EVENT(23); |
| 212 | ENSURE_MAPPABLE(a, "set_vbyte"); |
| 213 | sm = primary_map[a >> 16]; |
| 214 | sm_off = a & 0xFFFF; |
| 215 | sm->vbyte[sm_off] = vbyte; |
| 216 | } |
| 217 | |
| 218 | |
| 219 | /* Reading/writing of the bitmaps, for aligned word-sized accesses. */ |
| 220 | |
| 221 | static __inline__ UChar get_abits4_ALIGNED ( Addr a ) |
| 222 | { |
| 223 | SecMap* sm; |
| 224 | UInt sm_off; |
| 225 | UChar abits8; |
| 226 | PROF_EVENT(24); |
| 227 | # ifdef VG_DEBUG_MEMORY |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 228 | tl_assert(IS_ALIGNED4_ADDR(a)); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 229 | # endif |
| 230 | sm = primary_map[a >> 16]; |
| 231 | sm_off = a & 0xFFFF; |
| 232 | abits8 = sm->abits[sm_off >> 3]; |
| 233 | abits8 >>= (a & 4 /* 100b */); /* a & 4 is either 0 or 4 */ |
| 234 | abits8 &= 0x0F; |
| 235 | return abits8; |
| 236 | } |
| 237 | |
| 238 | static UInt __inline__ get_vbytes4_ALIGNED ( Addr a ) |
| 239 | { |
| 240 | SecMap* sm = primary_map[a >> 16]; |
| 241 | UInt sm_off = a & 0xFFFF; |
| 242 | PROF_EVENT(25); |
| 243 | # ifdef VG_DEBUG_MEMORY |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 244 | tl_assert(IS_ALIGNED4_ADDR(a)); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 245 | # endif |
| 246 | return ((UInt*)(sm->vbyte))[sm_off >> 2]; |
| 247 | } |
| 248 | |
| 249 | |
sewardj | ee07084 | 2003-07-05 17:53:55 +0000 | [diff] [blame] | 250 | static void __inline__ set_vbytes4_ALIGNED ( Addr a, UInt vbytes ) |
| 251 | { |
| 252 | SecMap* sm; |
| 253 | UInt sm_off; |
| 254 | ENSURE_MAPPABLE(a, "set_vbytes4_ALIGNED"); |
| 255 | sm = primary_map[a >> 16]; |
| 256 | sm_off = a & 0xFFFF; |
| 257 | PROF_EVENT(23); |
| 258 | # ifdef VG_DEBUG_MEMORY |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 259 | tl_assert(IS_ALIGNED4_ADDR(a)); |
sewardj | ee07084 | 2003-07-05 17:53:55 +0000 | [diff] [blame] | 260 | # endif |
| 261 | ((UInt*)(sm->vbyte))[sm_off >> 2] = vbytes; |
| 262 | } |
| 263 | |
| 264 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 265 | /*------------------------------------------------------------*/ |
| 266 | /*--- Setting permissions over address ranges. ---*/ |
| 267 | /*------------------------------------------------------------*/ |
| 268 | |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 269 | static void set_address_range_perms ( Addr a, SizeT len, |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 270 | UInt example_a_bit, |
| 271 | UInt example_v_bit ) |
| 272 | { |
| 273 | UChar vbyte, abyte8; |
| 274 | UInt vword4, sm_off; |
| 275 | SecMap* sm; |
| 276 | |
| 277 | PROF_EVENT(30); |
| 278 | |
| 279 | if (len == 0) |
| 280 | return; |
| 281 | |
nethercote | a66033c | 2004-03-08 15:37:58 +0000 | [diff] [blame] | 282 | if (VG_(clo_verbosity) > 0) { |
| 283 | if (len > 100 * 1000 * 1000) { |
| 284 | VG_(message)(Vg_UserMsg, |
| 285 | "Warning: set address range perms: " |
| 286 | "large range %u, a %d, v %d", |
| 287 | len, example_a_bit, example_v_bit ); |
| 288 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 289 | } |
| 290 | |
| 291 | VGP_PUSHCC(VgpSetMem); |
| 292 | |
| 293 | /* Requests to change permissions of huge address ranges may |
| 294 | indicate bugs in our machinery. 30,000,000 is arbitrary, but so |
| 295 | far all legitimate requests have fallen beneath that size. */ |
| 296 | /* 4 Mar 02: this is just stupid; get rid of it. */ |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 297 | /* tl_assert(len < 30000000); */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 298 | |
| 299 | /* Check the permissions make sense. */ |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 300 | tl_assert(example_a_bit == VGM_BIT_VALID |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 301 | || example_a_bit == VGM_BIT_INVALID); |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 302 | tl_assert(example_v_bit == VGM_BIT_VALID |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 303 | || example_v_bit == VGM_BIT_INVALID); |
| 304 | if (example_a_bit == VGM_BIT_INVALID) |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 305 | tl_assert(example_v_bit == VGM_BIT_INVALID); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 306 | |
| 307 | /* The validity bits to write. */ |
| 308 | vbyte = example_v_bit==VGM_BIT_VALID |
| 309 | ? VGM_BYTE_VALID : VGM_BYTE_INVALID; |
| 310 | |
| 311 | /* In order that we can charge through the address space at 8 |
| 312 | bytes/main-loop iteration, make up some perms. */ |
| 313 | abyte8 = (example_a_bit << 7) |
| 314 | | (example_a_bit << 6) |
| 315 | | (example_a_bit << 5) |
| 316 | | (example_a_bit << 4) |
| 317 | | (example_a_bit << 3) |
| 318 | | (example_a_bit << 2) |
| 319 | | (example_a_bit << 1) |
| 320 | | (example_a_bit << 0); |
| 321 | vword4 = (vbyte << 24) | (vbyte << 16) | (vbyte << 8) | vbyte; |
| 322 | |
| 323 | # ifdef VG_DEBUG_MEMORY |
| 324 | /* Do it ... */ |
| 325 | while (True) { |
| 326 | PROF_EVENT(31); |
| 327 | if (len == 0) break; |
| 328 | set_abit ( a, example_a_bit ); |
| 329 | set_vbyte ( a, vbyte ); |
| 330 | a++; |
| 331 | len--; |
| 332 | } |
| 333 | |
| 334 | # else |
| 335 | /* Slowly do parts preceding 8-byte alignment. */ |
| 336 | while (True) { |
| 337 | PROF_EVENT(31); |
| 338 | if (len == 0) break; |
| 339 | if ((a % 8) == 0) break; |
| 340 | set_abit ( a, example_a_bit ); |
| 341 | set_vbyte ( a, vbyte ); |
| 342 | a++; |
| 343 | len--; |
| 344 | } |
| 345 | |
| 346 | if (len == 0) { |
| 347 | VGP_POPCC(VgpSetMem); |
| 348 | return; |
| 349 | } |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 350 | tl_assert((a % 8) == 0 && len > 0); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 351 | |
| 352 | /* Once aligned, go fast. */ |
| 353 | while (True) { |
| 354 | PROF_EVENT(32); |
| 355 | if (len < 8) break; |
| 356 | ENSURE_MAPPABLE(a, "set_address_range_perms(fast)"); |
| 357 | sm = primary_map[a >> 16]; |
| 358 | sm_off = a & 0xFFFF; |
| 359 | sm->abits[sm_off >> 3] = abyte8; |
| 360 | ((UInt*)(sm->vbyte))[(sm_off >> 2) + 0] = vword4; |
| 361 | ((UInt*)(sm->vbyte))[(sm_off >> 2) + 1] = vword4; |
| 362 | a += 8; |
| 363 | len -= 8; |
| 364 | } |
| 365 | |
| 366 | if (len == 0) { |
| 367 | VGP_POPCC(VgpSetMem); |
| 368 | return; |
| 369 | } |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 370 | tl_assert((a % 8) == 0 && len > 0 && len < 8); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 371 | |
| 372 | /* Finish the upper fragment. */ |
| 373 | while (True) { |
| 374 | PROF_EVENT(33); |
| 375 | if (len == 0) break; |
| 376 | set_abit ( a, example_a_bit ); |
| 377 | set_vbyte ( a, vbyte ); |
| 378 | a++; |
| 379 | len--; |
| 380 | } |
| 381 | # endif |
| 382 | |
| 383 | /* Check that zero page and highest page have not been written to |
| 384 | -- this could happen with buggy syscall wrappers. Today |
| 385 | (2001-04-26) had precisely such a problem with __NR_setitimer. */ |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 386 | tl_assert(SK_(cheap_sanity_check)()); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 387 | VGP_POPCC(VgpSetMem); |
| 388 | } |
| 389 | |
| 390 | /* Set permissions for address ranges ... */ |
| 391 | |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 392 | static void mc_make_noaccess ( Addr a, SizeT len ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 393 | { |
| 394 | PROF_EVENT(35); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 395 | DEBUG("mc_make_noaccess(%p, %llu)\n", a, (ULong)len); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 396 | set_address_range_perms ( a, len, VGM_BIT_INVALID, VGM_BIT_INVALID ); |
| 397 | } |
| 398 | |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 399 | static void mc_make_writable ( Addr a, SizeT len ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 400 | { |
| 401 | PROF_EVENT(36); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 402 | DEBUG("mc_make_writable(%p, %llu)\n", a, (ULong)len); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 403 | set_address_range_perms ( a, len, VGM_BIT_VALID, VGM_BIT_INVALID ); |
| 404 | } |
| 405 | |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 406 | static void mc_make_readable ( Addr a, SizeT len ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 407 | { |
| 408 | PROF_EVENT(37); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 409 | DEBUG("mc_make_readable(%p, %llu)\n", a, (ULong)len); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 410 | set_address_range_perms ( a, len, VGM_BIT_VALID, VGM_BIT_VALID ); |
| 411 | } |
| 412 | |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 413 | static __inline__ |
| 414 | void make_aligned_word_writable(Addr a) |
| 415 | { |
| 416 | SecMap* sm; |
| 417 | UInt sm_off; |
| 418 | UChar mask; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 419 | |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 420 | VGP_PUSHCC(VgpESPAdj); |
| 421 | ENSURE_MAPPABLE(a, "make_aligned_word_writable"); |
| 422 | sm = primary_map[a >> 16]; |
| 423 | sm_off = a & 0xFFFF; |
| 424 | ((UInt*)(sm->vbyte))[sm_off >> 2] = VGM_WORD_INVALID; |
| 425 | mask = 0x0F; |
| 426 | mask <<= (a & 4 /* 100b */); /* a & 4 is either 0 or 4 */ |
| 427 | /* mask now contains 1s where we wish to make address bits invalid (0s). */ |
| 428 | sm->abits[sm_off >> 3] &= ~mask; |
| 429 | VGP_POPCC(VgpESPAdj); |
| 430 | } |
| 431 | |
| 432 | static __inline__ |
| 433 | void make_aligned_word_noaccess(Addr a) |
| 434 | { |
| 435 | SecMap* sm; |
| 436 | UInt sm_off; |
| 437 | UChar mask; |
| 438 | |
| 439 | VGP_PUSHCC(VgpESPAdj); |
| 440 | ENSURE_MAPPABLE(a, "make_aligned_word_noaccess"); |
| 441 | sm = primary_map[a >> 16]; |
| 442 | sm_off = a & 0xFFFF; |
| 443 | ((UInt*)(sm->vbyte))[sm_off >> 2] = VGM_WORD_INVALID; |
| 444 | mask = 0x0F; |
| 445 | mask <<= (a & 4 /* 100b */); /* a & 4 is either 0 or 4 */ |
| 446 | /* mask now contains 1s where we wish to make address bits invalid (1s). */ |
| 447 | sm->abits[sm_off >> 3] |= mask; |
| 448 | VGP_POPCC(VgpESPAdj); |
| 449 | } |
| 450 | |
| 451 | /* Nb: by "aligned" here we mean 8-byte aligned */ |
| 452 | static __inline__ |
| 453 | void make_aligned_doubleword_writable(Addr a) |
| 454 | { |
| 455 | SecMap* sm; |
| 456 | UInt sm_off; |
| 457 | |
| 458 | VGP_PUSHCC(VgpESPAdj); |
| 459 | ENSURE_MAPPABLE(a, "make_aligned_doubleword_writable"); |
| 460 | sm = primary_map[a >> 16]; |
| 461 | sm_off = a & 0xFFFF; |
| 462 | sm->abits[sm_off >> 3] = VGM_BYTE_VALID; |
| 463 | ((UInt*)(sm->vbyte))[(sm_off >> 2) + 0] = VGM_WORD_INVALID; |
| 464 | ((UInt*)(sm->vbyte))[(sm_off >> 2) + 1] = VGM_WORD_INVALID; |
| 465 | VGP_POPCC(VgpESPAdj); |
| 466 | } |
| 467 | |
| 468 | static __inline__ |
| 469 | void make_aligned_doubleword_noaccess(Addr a) |
| 470 | { |
| 471 | SecMap* sm; |
| 472 | UInt sm_off; |
| 473 | |
| 474 | VGP_PUSHCC(VgpESPAdj); |
| 475 | ENSURE_MAPPABLE(a, "make_aligned_doubleword_noaccess"); |
| 476 | sm = primary_map[a >> 16]; |
| 477 | sm_off = a & 0xFFFF; |
| 478 | sm->abits[sm_off >> 3] = VGM_BYTE_INVALID; |
| 479 | ((UInt*)(sm->vbyte))[(sm_off >> 2) + 0] = VGM_WORD_INVALID; |
| 480 | ((UInt*)(sm->vbyte))[(sm_off >> 2) + 1] = VGM_WORD_INVALID; |
| 481 | VGP_POPCC(VgpESPAdj); |
| 482 | } |
| 483 | |
| 484 | /* The %esp update handling functions */ |
| 485 | ESP_UPDATE_HANDLERS ( make_aligned_word_writable, |
| 486 | make_aligned_word_noaccess, |
| 487 | make_aligned_doubleword_writable, |
| 488 | make_aligned_doubleword_noaccess, |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 489 | mc_make_writable, |
| 490 | mc_make_noaccess |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 491 | ); |
| 492 | |
| 493 | /* Block-copy permissions (needed for implementing realloc()). */ |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 494 | static void mc_copy_address_range_state ( Addr src, Addr dst, SizeT len ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 495 | { |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 496 | SizeT i; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 497 | |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 498 | DEBUG("mc_copy_address_range_state\n"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 499 | |
| 500 | PROF_EVENT(40); |
| 501 | for (i = 0; i < len; i++) { |
| 502 | UChar abit = get_abit ( src+i ); |
| 503 | UChar vbyte = get_vbyte ( src+i ); |
| 504 | PROF_EVENT(41); |
| 505 | set_abit ( dst+i, abit ); |
| 506 | set_vbyte ( dst+i, vbyte ); |
| 507 | } |
| 508 | } |
| 509 | |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 510 | /*------------------------------------------------------------*/ |
| 511 | /*--- Checking memory ---*/ |
| 512 | /*------------------------------------------------------------*/ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 513 | |
| 514 | /* Check permissions for address range. If inadequate permissions |
| 515 | exist, *bad_addr is set to the offending address, so the caller can |
| 516 | know what it is. */ |
| 517 | |
sewardj | ecf8e10 | 2003-07-12 12:11:39 +0000 | [diff] [blame] | 518 | /* Returns True if [a .. a+len) is not addressible. Otherwise, |
| 519 | returns False, and if bad_addr is non-NULL, sets *bad_addr to |
| 520 | indicate the lowest failing address. Functions below are |
| 521 | similar. */ |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 522 | static Bool mc_check_noaccess ( Addr a, SizeT len, Addr* bad_addr ) |
sewardj | ecf8e10 | 2003-07-12 12:11:39 +0000 | [diff] [blame] | 523 | { |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 524 | SizeT i; |
sewardj | ecf8e10 | 2003-07-12 12:11:39 +0000 | [diff] [blame] | 525 | UChar abit; |
| 526 | PROF_EVENT(42); |
| 527 | for (i = 0; i < len; i++) { |
| 528 | PROF_EVENT(43); |
| 529 | abit = get_abit(a); |
| 530 | if (abit == VGM_BIT_VALID) { |
| 531 | if (bad_addr != NULL) *bad_addr = a; |
| 532 | return False; |
| 533 | } |
| 534 | a++; |
| 535 | } |
| 536 | return True; |
| 537 | } |
| 538 | |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 539 | static Bool mc_check_writable ( Addr a, SizeT len, Addr* bad_addr ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 540 | { |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 541 | SizeT i; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 542 | UChar abit; |
| 543 | PROF_EVENT(42); |
| 544 | for (i = 0; i < len; i++) { |
| 545 | PROF_EVENT(43); |
| 546 | abit = get_abit(a); |
| 547 | if (abit == VGM_BIT_INVALID) { |
| 548 | if (bad_addr != NULL) *bad_addr = a; |
| 549 | return False; |
| 550 | } |
| 551 | a++; |
| 552 | } |
| 553 | return True; |
| 554 | } |
| 555 | |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 556 | typedef enum { |
| 557 | MC_Ok = 5, MC_AddrErr = 6, MC_ValueErr = 7 |
| 558 | } MC_ReadResult; |
| 559 | |
| 560 | static MC_ReadResult mc_check_readable ( Addr a, SizeT len, Addr* bad_addr ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 561 | { |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 562 | SizeT i; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 563 | UChar abit; |
| 564 | UChar vbyte; |
| 565 | |
| 566 | PROF_EVENT(44); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 567 | DEBUG("mc_check_readable\n"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 568 | for (i = 0; i < len; i++) { |
| 569 | abit = get_abit(a); |
| 570 | vbyte = get_vbyte(a); |
| 571 | PROF_EVENT(45); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 572 | // Report addressability errors in preference to definedness errors |
| 573 | // by checking the A bits first. |
| 574 | if (abit != VGM_BIT_VALID) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 575 | if (bad_addr != NULL) *bad_addr = a; |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 576 | return MC_AddrErr; |
| 577 | } |
| 578 | if (vbyte != VGM_BYTE_VALID) { |
| 579 | if (bad_addr != NULL) *bad_addr = a; |
| 580 | return MC_ValueErr; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 581 | } |
| 582 | a++; |
| 583 | } |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 584 | return MC_Ok; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 585 | } |
| 586 | |
| 587 | |
| 588 | /* Check a zero-terminated ascii string. Tricky -- don't want to |
| 589 | examine the actual bytes, to find the end, until we're sure it is |
| 590 | safe to do so. */ |
| 591 | |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 592 | static Bool mc_check_readable_asciiz ( Addr a, Addr* bad_addr ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 593 | { |
| 594 | UChar abit; |
| 595 | UChar vbyte; |
| 596 | PROF_EVENT(46); |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 597 | DEBUG("mc_check_readable_asciiz\n"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 598 | while (True) { |
| 599 | PROF_EVENT(47); |
| 600 | abit = get_abit(a); |
| 601 | vbyte = get_vbyte(a); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 602 | // As in mc_check_readable(), check A bits first |
| 603 | if (abit != VGM_BIT_VALID) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 604 | if (bad_addr != NULL) *bad_addr = a; |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 605 | return MC_AddrErr; |
| 606 | } |
| 607 | if (vbyte != VGM_BYTE_VALID) { |
| 608 | if (bad_addr != NULL) *bad_addr = a; |
| 609 | return MC_ValueErr; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 610 | } |
| 611 | /* Ok, a is safe to read. */ |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 612 | if (* ((UChar*)a) == 0) return MC_Ok; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 613 | a++; |
| 614 | } |
| 615 | } |
| 616 | |
| 617 | |
| 618 | /*------------------------------------------------------------*/ |
| 619 | /*--- Memory event handlers ---*/ |
| 620 | /*------------------------------------------------------------*/ |
| 621 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 622 | static |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 623 | void mc_check_is_writable ( CorePart part, ThreadId tid, Char* s, |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 624 | Addr base, SizeT size ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 625 | { |
| 626 | Bool ok; |
| 627 | Addr bad_addr; |
| 628 | |
| 629 | VGP_PUSHCC(VgpCheckMem); |
| 630 | |
| 631 | /* VG_(message)(Vg_DebugMsg,"check is writable: %x .. %x", |
| 632 | base,base+size-1); */ |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 633 | ok = mc_check_writable ( base, size, &bad_addr ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 634 | if (!ok) { |
| 635 | switch (part) { |
| 636 | case Vg_CoreSysCall: |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 637 | MAC_(record_param_error) ( tid, bad_addr, /*isReg*/False, |
| 638 | /*isUnaddr*/True, s ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 639 | break; |
| 640 | |
| 641 | case Vg_CorePThread: |
| 642 | case Vg_CoreSignal: |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 643 | MAC_(record_core_mem_error)( tid, /*isUnaddr*/True, s ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 644 | break; |
| 645 | |
| 646 | default: |
njn | 6799325 | 2004-11-22 18:02:32 +0000 | [diff] [blame^] | 647 | VG_(tool_panic)("mc_check_is_writable: unexpected CorePart"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 648 | } |
| 649 | } |
| 650 | |
| 651 | VGP_POPCC(VgpCheckMem); |
| 652 | } |
| 653 | |
| 654 | static |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 655 | void mc_check_is_readable ( CorePart part, ThreadId tid, Char* s, |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 656 | Addr base, SizeT size ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 657 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 658 | Addr bad_addr; |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 659 | MC_ReadResult res; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 660 | |
| 661 | VGP_PUSHCC(VgpCheckMem); |
| 662 | |
| 663 | /* VG_(message)(Vg_DebugMsg,"check is readable: %x .. %x", |
| 664 | base,base+size-1); */ |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 665 | res = mc_check_readable ( base, size, &bad_addr ); |
| 666 | if (MC_Ok != res) { |
| 667 | Bool isUnaddr = ( MC_AddrErr == res ? True : False ); |
| 668 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 669 | switch (part) { |
| 670 | case Vg_CoreSysCall: |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 671 | MAC_(record_param_error) ( tid, bad_addr, /*isReg*/False, |
| 672 | isUnaddr, s ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 673 | break; |
| 674 | |
| 675 | case Vg_CorePThread: |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 676 | MAC_(record_core_mem_error)( tid, isUnaddr, s ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 677 | break; |
| 678 | |
| 679 | /* If we're being asked to jump to a silly address, record an error |
| 680 | message before potentially crashing the entire system. */ |
| 681 | case Vg_CoreTranslate: |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 682 | MAC_(record_jump_error)( tid, bad_addr ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 683 | break; |
| 684 | |
| 685 | default: |
njn | 6799325 | 2004-11-22 18:02:32 +0000 | [diff] [blame^] | 686 | VG_(tool_panic)("mc_check_is_readable: unexpected CorePart"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 687 | } |
| 688 | } |
| 689 | VGP_POPCC(VgpCheckMem); |
| 690 | } |
| 691 | |
| 692 | static |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 693 | void mc_check_is_readable_asciiz ( CorePart part, ThreadId tid, |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 694 | Char* s, Addr str ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 695 | { |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 696 | MC_ReadResult res; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 697 | Addr bad_addr; |
| 698 | /* VG_(message)(Vg_DebugMsg,"check is readable asciiz: 0x%x",str); */ |
| 699 | |
| 700 | VGP_PUSHCC(VgpCheckMem); |
| 701 | |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 702 | tl_assert(part == Vg_CoreSysCall); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 703 | res = mc_check_readable_asciiz ( (Addr)str, &bad_addr ); |
| 704 | if (MC_Ok != res) { |
| 705 | Bool isUnaddr = ( MC_AddrErr == res ? True : False ); |
| 706 | MAC_(record_param_error) ( tid, bad_addr, /*isReg*/False, isUnaddr, s ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 707 | } |
| 708 | |
| 709 | VGP_POPCC(VgpCheckMem); |
| 710 | } |
| 711 | |
| 712 | |
| 713 | static |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 714 | void mc_new_mem_startup( Addr a, SizeT len, Bool rr, Bool ww, Bool xx ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 715 | { |
njn | 1f3a909 | 2002-10-04 09:22:30 +0000 | [diff] [blame] | 716 | /* Ignore the permissions, just make it readable. Seems to work... */ |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 717 | DEBUG("mc_new_mem_startup(%p, %llu, rr=%u, ww=%u, xx=%u)\n", |
| 718 | a,(ULong)len,rr,ww,xx); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 719 | mc_make_readable(a, len); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 720 | } |
| 721 | |
| 722 | static |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 723 | void mc_new_mem_heap ( Addr a, SizeT len, Bool is_inited ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 724 | { |
| 725 | if (is_inited) { |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 726 | mc_make_readable(a, len); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 727 | } else { |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 728 | mc_make_writable(a, len); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 729 | } |
| 730 | } |
| 731 | |
| 732 | static |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 733 | void mc_set_perms (Addr a, SizeT len, Bool rr, Bool ww, Bool xx) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 734 | { |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 735 | DEBUG("mc_set_perms(%p, %llu, rr=%u ww=%u, xx=%u)\n", |
| 736 | a, (ULong)len, rr, ww, xx); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 737 | if (rr) mc_make_readable(a, len); |
| 738 | else if (ww) mc_make_writable(a, len); |
| 739 | else mc_make_noaccess(a, len); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 740 | } |
| 741 | |
| 742 | |
| 743 | /*------------------------------------------------------------*/ |
njn | d304045 | 2003-05-19 15:04:06 +0000 | [diff] [blame] | 744 | /*--- Register event handlers ---*/ |
| 745 | /*------------------------------------------------------------*/ |
| 746 | |
| 747 | static void mc_post_regs_write_init ( void ) |
| 748 | { |
| 749 | UInt i; |
nethercote | c06e213 | 2004-09-03 13:45:29 +0000 | [diff] [blame] | 750 | for (i = FIRST_ARCH_REG; i <= LAST_ARCH_REG; i++) |
njn | d304045 | 2003-05-19 15:04:06 +0000 | [diff] [blame] | 751 | VG_(set_shadow_archreg)( i, VGM_WORD_VALID ); |
| 752 | VG_(set_shadow_eflags)( VGM_EFLAGS_VALID ); |
| 753 | } |
| 754 | |
| 755 | static void mc_post_reg_write(ThreadId tid, UInt reg) |
| 756 | { |
| 757 | VG_(set_thread_shadow_archreg)( tid, reg, VGM_WORD_VALID ); |
| 758 | } |
| 759 | |
| 760 | static void mc_post_reg_write_clientcall(ThreadId tid, UInt reg, Addr f ) |
| 761 | { |
| 762 | VG_(set_thread_shadow_archreg)( tid, reg, VGM_WORD_VALID ); |
| 763 | } |
| 764 | |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 765 | static void mc_pre_reg_read(CorePart part, ThreadId tid, Char* s, UInt reg, |
| 766 | SizeT size) |
| 767 | { |
| 768 | UWord mask; |
| 769 | |
| 770 | // XXX: the only one at the moment |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 771 | tl_assert(Vg_CoreSysCall == part); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 772 | |
| 773 | switch (size) { |
| 774 | case 4: mask = 0xffffffff; break; |
| 775 | case 2: mask = 0xffff; break; |
| 776 | case 1: mask = 0xff; break; |
njn | 6799325 | 2004-11-22 18:02:32 +0000 | [diff] [blame^] | 777 | default: VG_(tool_panic)("Unhandled size in mc_pre_reg_read"); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 778 | } |
| 779 | |
| 780 | if (VGM_WORD_VALID != (mask & VG_(get_thread_shadow_archreg)( tid, reg )) ) |
| 781 | MAC_(record_param_error) ( tid, 0, /*isReg*/True, /*isUnaddr*/False, s ); |
| 782 | } |
njn | d304045 | 2003-05-19 15:04:06 +0000 | [diff] [blame] | 783 | |
| 784 | /*------------------------------------------------------------*/ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 785 | /*--- Functions called directly from generated code. ---*/ |
| 786 | /*------------------------------------------------------------*/ |
| 787 | |
| 788 | static __inline__ UInt rotateRight16 ( UInt x ) |
| 789 | { |
| 790 | /* Amazingly, gcc turns this into a single rotate insn. */ |
| 791 | return (x >> 16) | (x << 16); |
| 792 | } |
| 793 | |
| 794 | |
| 795 | static __inline__ UInt shiftRight16 ( UInt x ) |
| 796 | { |
| 797 | return x >> 16; |
| 798 | } |
| 799 | |
| 800 | |
| 801 | /* Read/write 1/2/4 sized V bytes, and emit an address error if |
| 802 | needed. */ |
| 803 | |
| 804 | /* VG_(helperc_{LD,ST}V{1,2,4}) handle the common case fast. |
| 805 | Under all other circumstances, it defers to the relevant _SLOWLY |
| 806 | function, which can handle all situations. |
| 807 | */ |
nethercote | eec4630 | 2004-08-23 15:06:23 +0000 | [diff] [blame] | 808 | REGPARM(1) |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 809 | UInt MC_(helperc_LOADV4) ( Addr a ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 810 | { |
| 811 | # ifdef VG_DEBUG_MEMORY |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 812 | return mc_rd_V4_SLOWLY(a); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 813 | # else |
| 814 | UInt sec_no = rotateRight16(a) & 0x3FFFF; |
| 815 | SecMap* sm = primary_map[sec_no]; |
| 816 | UInt a_off = (a & 0xFFFF) >> 3; |
| 817 | UChar abits = sm->abits[a_off]; |
| 818 | abits >>= (a & 4); |
| 819 | abits &= 15; |
| 820 | PROF_EVENT(60); |
| 821 | if (abits == VGM_NIBBLE_VALID) { |
| 822 | /* Handle common case quickly: a is suitably aligned, is mapped, |
| 823 | and is addressible. */ |
| 824 | UInt v_off = a & 0xFFFF; |
| 825 | return ((UInt*)(sm->vbyte))[ v_off >> 2 ]; |
| 826 | } else { |
| 827 | /* Slow but general case. */ |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 828 | return mc_rd_V4_SLOWLY(a); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 829 | } |
| 830 | # endif |
| 831 | } |
| 832 | |
nethercote | eec4630 | 2004-08-23 15:06:23 +0000 | [diff] [blame] | 833 | REGPARM(2) |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 834 | void MC_(helperc_STOREV4) ( Addr a, UInt vbytes ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 835 | { |
| 836 | # ifdef VG_DEBUG_MEMORY |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 837 | mc_wr_V4_SLOWLY(a, vbytes); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 838 | # else |
| 839 | UInt sec_no = rotateRight16(a) & 0x3FFFF; |
| 840 | SecMap* sm = primary_map[sec_no]; |
| 841 | UInt a_off = (a & 0xFFFF) >> 3; |
| 842 | UChar abits = sm->abits[a_off]; |
| 843 | abits >>= (a & 4); |
| 844 | abits &= 15; |
| 845 | PROF_EVENT(61); |
| 846 | if (abits == VGM_NIBBLE_VALID) { |
| 847 | /* Handle common case quickly: a is suitably aligned, is mapped, |
| 848 | and is addressible. */ |
| 849 | UInt v_off = a & 0xFFFF; |
| 850 | ((UInt*)(sm->vbyte))[ v_off >> 2 ] = vbytes; |
| 851 | } else { |
| 852 | /* Slow but general case. */ |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 853 | mc_wr_V4_SLOWLY(a, vbytes); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 854 | } |
| 855 | # endif |
| 856 | } |
| 857 | |
nethercote | eec4630 | 2004-08-23 15:06:23 +0000 | [diff] [blame] | 858 | REGPARM(1) |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 859 | UInt MC_(helperc_LOADV2) ( Addr a ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 860 | { |
| 861 | # ifdef VG_DEBUG_MEMORY |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 862 | return mc_rd_V2_SLOWLY(a); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 863 | # else |
| 864 | UInt sec_no = rotateRight16(a) & 0x1FFFF; |
| 865 | SecMap* sm = primary_map[sec_no]; |
| 866 | UInt a_off = (a & 0xFFFF) >> 3; |
| 867 | PROF_EVENT(62); |
| 868 | if (sm->abits[a_off] == VGM_BYTE_VALID) { |
| 869 | /* Handle common case quickly. */ |
| 870 | UInt v_off = a & 0xFFFF; |
| 871 | return 0xFFFF0000 |
| 872 | | |
| 873 | (UInt)( ((UShort*)(sm->vbyte))[ v_off >> 1 ] ); |
| 874 | } else { |
| 875 | /* Slow but general case. */ |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 876 | return mc_rd_V2_SLOWLY(a); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 877 | } |
| 878 | # endif |
| 879 | } |
| 880 | |
nethercote | eec4630 | 2004-08-23 15:06:23 +0000 | [diff] [blame] | 881 | REGPARM(2) |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 882 | void MC_(helperc_STOREV2) ( Addr a, UInt vbytes ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 883 | { |
| 884 | # ifdef VG_DEBUG_MEMORY |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 885 | mc_wr_V2_SLOWLY(a, vbytes); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 886 | # else |
| 887 | UInt sec_no = rotateRight16(a) & 0x1FFFF; |
| 888 | SecMap* sm = primary_map[sec_no]; |
| 889 | UInt a_off = (a & 0xFFFF) >> 3; |
| 890 | PROF_EVENT(63); |
| 891 | if (sm->abits[a_off] == VGM_BYTE_VALID) { |
| 892 | /* Handle common case quickly. */ |
| 893 | UInt v_off = a & 0xFFFF; |
| 894 | ((UShort*)(sm->vbyte))[ v_off >> 1 ] = vbytes & 0x0000FFFF; |
| 895 | } else { |
| 896 | /* Slow but general case. */ |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 897 | mc_wr_V2_SLOWLY(a, vbytes); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 898 | } |
| 899 | # endif |
| 900 | } |
| 901 | |
nethercote | eec4630 | 2004-08-23 15:06:23 +0000 | [diff] [blame] | 902 | REGPARM(1) |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 903 | UInt MC_(helperc_LOADV1) ( Addr a ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 904 | { |
| 905 | # ifdef VG_DEBUG_MEMORY |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 906 | return mc_rd_V1_SLOWLY(a); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 907 | # else |
| 908 | UInt sec_no = shiftRight16(a); |
| 909 | SecMap* sm = primary_map[sec_no]; |
| 910 | UInt a_off = (a & 0xFFFF) >> 3; |
| 911 | PROF_EVENT(64); |
| 912 | if (sm->abits[a_off] == VGM_BYTE_VALID) { |
| 913 | /* Handle common case quickly. */ |
| 914 | UInt v_off = a & 0xFFFF; |
| 915 | return 0xFFFFFF00 |
| 916 | | |
| 917 | (UInt)( ((UChar*)(sm->vbyte))[ v_off ] ); |
| 918 | } else { |
| 919 | /* Slow but general case. */ |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 920 | return mc_rd_V1_SLOWLY(a); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 921 | } |
| 922 | # endif |
| 923 | } |
| 924 | |
nethercote | eec4630 | 2004-08-23 15:06:23 +0000 | [diff] [blame] | 925 | REGPARM(2) |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 926 | void MC_(helperc_STOREV1) ( Addr a, UInt vbytes ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 927 | { |
| 928 | # ifdef VG_DEBUG_MEMORY |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 929 | mc_wr_V1_SLOWLY(a, vbytes); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 930 | # else |
| 931 | UInt sec_no = shiftRight16(a); |
| 932 | SecMap* sm = primary_map[sec_no]; |
| 933 | UInt a_off = (a & 0xFFFF) >> 3; |
| 934 | PROF_EVENT(65); |
| 935 | if (sm->abits[a_off] == VGM_BYTE_VALID) { |
| 936 | /* Handle common case quickly. */ |
| 937 | UInt v_off = a & 0xFFFF; |
| 938 | ((UChar*)(sm->vbyte))[ v_off ] = vbytes & 0x000000FF; |
| 939 | } else { |
| 940 | /* Slow but general case. */ |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 941 | mc_wr_V1_SLOWLY(a, vbytes); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 942 | } |
| 943 | # endif |
| 944 | } |
| 945 | |
| 946 | |
| 947 | /*------------------------------------------------------------*/ |
| 948 | /*--- Fallback functions to handle cases that the above ---*/ |
| 949 | /*--- VG_(helperc_{LD,ST}V{1,2,4}) can't manage. ---*/ |
| 950 | /*------------------------------------------------------------*/ |
| 951 | |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 952 | static UInt mc_rd_V4_SLOWLY ( Addr a ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 953 | { |
| 954 | Bool a0ok, a1ok, a2ok, a3ok; |
| 955 | UInt vb0, vb1, vb2, vb3; |
| 956 | |
| 957 | PROF_EVENT(70); |
| 958 | |
| 959 | /* First establish independently the addressibility of the 4 bytes |
| 960 | involved. */ |
| 961 | a0ok = get_abit(a+0) == VGM_BIT_VALID; |
| 962 | a1ok = get_abit(a+1) == VGM_BIT_VALID; |
| 963 | a2ok = get_abit(a+2) == VGM_BIT_VALID; |
| 964 | a3ok = get_abit(a+3) == VGM_BIT_VALID; |
| 965 | |
| 966 | /* Also get the validity bytes for the address. */ |
| 967 | vb0 = (UInt)get_vbyte(a+0); |
| 968 | vb1 = (UInt)get_vbyte(a+1); |
| 969 | vb2 = (UInt)get_vbyte(a+2); |
| 970 | vb3 = (UInt)get_vbyte(a+3); |
| 971 | |
| 972 | /* Now distinguish 3 cases */ |
| 973 | |
| 974 | /* Case 1: the address is completely valid, so: |
| 975 | - no addressing error |
| 976 | - return V bytes as read from memory |
| 977 | */ |
| 978 | if (a0ok && a1ok && a2ok && a3ok) { |
| 979 | UInt vw = VGM_WORD_INVALID; |
| 980 | vw <<= 8; vw |= vb3; |
| 981 | vw <<= 8; vw |= vb2; |
| 982 | vw <<= 8; vw |= vb1; |
| 983 | vw <<= 8; vw |= vb0; |
| 984 | return vw; |
| 985 | } |
| 986 | |
| 987 | /* Case 2: the address is completely invalid. |
| 988 | - emit addressing error |
| 989 | - return V word indicating validity. |
| 990 | This sounds strange, but if we make loads from invalid addresses |
| 991 | give invalid data, we also risk producing a number of confusing |
| 992 | undefined-value errors later, which confuses the fact that the |
| 993 | error arose in the first place from an invalid address. |
| 994 | */ |
| 995 | /* VG_(printf)("%p (%d %d %d %d)\n", a, a0ok, a1ok, a2ok, a3ok); */ |
njn | 43c799e | 2003-04-08 00:08:52 +0000 | [diff] [blame] | 996 | if (!MAC_(clo_partial_loads_ok) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 997 | || ((a & 3) != 0) |
| 998 | || (!a0ok && !a1ok && !a2ok && !a3ok)) { |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 999 | MAC_(record_address_error)( VG_(get_current_tid)(), a, 4, False ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1000 | return (VGM_BYTE_VALID << 24) | (VGM_BYTE_VALID << 16) |
| 1001 | | (VGM_BYTE_VALID << 8) | VGM_BYTE_VALID; |
| 1002 | } |
| 1003 | |
| 1004 | /* Case 3: the address is partially valid. |
| 1005 | - no addressing error |
| 1006 | - returned V word is invalid where the address is invalid, |
| 1007 | and contains V bytes from memory otherwise. |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1008 | Case 3 is only allowed if MC_(clo_partial_loads_ok) is True |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1009 | (which is the default), and the address is 4-aligned. |
| 1010 | If not, Case 2 will have applied. |
| 1011 | */ |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 1012 | tl_assert(MAC_(clo_partial_loads_ok)); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1013 | { |
| 1014 | UInt vw = VGM_WORD_INVALID; |
| 1015 | vw <<= 8; vw |= (a3ok ? vb3 : VGM_BYTE_INVALID); |
| 1016 | vw <<= 8; vw |= (a2ok ? vb2 : VGM_BYTE_INVALID); |
| 1017 | vw <<= 8; vw |= (a1ok ? vb1 : VGM_BYTE_INVALID); |
| 1018 | vw <<= 8; vw |= (a0ok ? vb0 : VGM_BYTE_INVALID); |
| 1019 | return vw; |
| 1020 | } |
| 1021 | } |
| 1022 | |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1023 | static void mc_wr_V4_SLOWLY ( Addr a, UInt vbytes ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1024 | { |
| 1025 | /* Check the address for validity. */ |
| 1026 | Bool aerr = False; |
| 1027 | PROF_EVENT(71); |
| 1028 | |
| 1029 | if (get_abit(a+0) != VGM_BIT_VALID) aerr = True; |
| 1030 | if (get_abit(a+1) != VGM_BIT_VALID) aerr = True; |
| 1031 | if (get_abit(a+2) != VGM_BIT_VALID) aerr = True; |
| 1032 | if (get_abit(a+3) != VGM_BIT_VALID) aerr = True; |
| 1033 | |
| 1034 | /* Store the V bytes, remembering to do it little-endian-ly. */ |
| 1035 | set_vbyte( a+0, vbytes & 0x000000FF ); vbytes >>= 8; |
| 1036 | set_vbyte( a+1, vbytes & 0x000000FF ); vbytes >>= 8; |
| 1037 | set_vbyte( a+2, vbytes & 0x000000FF ); vbytes >>= 8; |
| 1038 | set_vbyte( a+3, vbytes & 0x000000FF ); |
| 1039 | |
| 1040 | /* If an address error has happened, report it. */ |
| 1041 | if (aerr) |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1042 | MAC_(record_address_error)( VG_(get_current_tid)(), a, 4, True ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1043 | } |
| 1044 | |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1045 | static UInt mc_rd_V2_SLOWLY ( Addr a ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1046 | { |
| 1047 | /* Check the address for validity. */ |
| 1048 | UInt vw = VGM_WORD_INVALID; |
| 1049 | Bool aerr = False; |
| 1050 | PROF_EVENT(72); |
| 1051 | |
| 1052 | if (get_abit(a+0) != VGM_BIT_VALID) aerr = True; |
| 1053 | if (get_abit(a+1) != VGM_BIT_VALID) aerr = True; |
| 1054 | |
| 1055 | /* Fetch the V bytes, remembering to do it little-endian-ly. */ |
| 1056 | vw <<= 8; vw |= (UInt)get_vbyte(a+1); |
| 1057 | vw <<= 8; vw |= (UInt)get_vbyte(a+0); |
| 1058 | |
| 1059 | /* If an address error has happened, report it. */ |
| 1060 | if (aerr) { |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1061 | MAC_(record_address_error)( VG_(get_current_tid)(), a, 2, False ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1062 | vw = (VGM_BYTE_INVALID << 24) | (VGM_BYTE_INVALID << 16) |
| 1063 | | (VGM_BYTE_VALID << 8) | (VGM_BYTE_VALID); |
| 1064 | } |
| 1065 | return vw; |
| 1066 | } |
| 1067 | |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1068 | static void mc_wr_V2_SLOWLY ( Addr a, UInt vbytes ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1069 | { |
| 1070 | /* Check the address for validity. */ |
| 1071 | Bool aerr = False; |
| 1072 | PROF_EVENT(73); |
| 1073 | |
| 1074 | if (get_abit(a+0) != VGM_BIT_VALID) aerr = True; |
| 1075 | if (get_abit(a+1) != VGM_BIT_VALID) aerr = True; |
| 1076 | |
| 1077 | /* Store the V bytes, remembering to do it little-endian-ly. */ |
| 1078 | set_vbyte( a+0, vbytes & 0x000000FF ); vbytes >>= 8; |
| 1079 | set_vbyte( a+1, vbytes & 0x000000FF ); |
| 1080 | |
| 1081 | /* If an address error has happened, report it. */ |
| 1082 | if (aerr) |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1083 | MAC_(record_address_error)( VG_(get_current_tid)(), a, 2, True ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1084 | } |
| 1085 | |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1086 | static UInt mc_rd_V1_SLOWLY ( Addr a ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1087 | { |
| 1088 | /* Check the address for validity. */ |
| 1089 | UInt vw = VGM_WORD_INVALID; |
| 1090 | Bool aerr = False; |
| 1091 | PROF_EVENT(74); |
| 1092 | |
| 1093 | if (get_abit(a+0) != VGM_BIT_VALID) aerr = True; |
| 1094 | |
| 1095 | /* Fetch the V byte. */ |
| 1096 | vw <<= 8; vw |= (UInt)get_vbyte(a+0); |
| 1097 | |
| 1098 | /* If an address error has happened, report it. */ |
| 1099 | if (aerr) { |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1100 | MAC_(record_address_error)( VG_(get_current_tid)(), a, 1, False ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1101 | vw = (VGM_BYTE_INVALID << 24) | (VGM_BYTE_INVALID << 16) |
| 1102 | | (VGM_BYTE_INVALID << 8) | (VGM_BYTE_VALID); |
| 1103 | } |
| 1104 | return vw; |
| 1105 | } |
| 1106 | |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1107 | static void mc_wr_V1_SLOWLY ( Addr a, UInt vbytes ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1108 | { |
| 1109 | /* Check the address for validity. */ |
| 1110 | Bool aerr = False; |
| 1111 | PROF_EVENT(75); |
| 1112 | if (get_abit(a+0) != VGM_BIT_VALID) aerr = True; |
| 1113 | |
| 1114 | /* Store the V bytes, remembering to do it little-endian-ly. */ |
| 1115 | set_vbyte( a+0, vbytes & 0x000000FF ); |
| 1116 | |
| 1117 | /* If an address error has happened, report it. */ |
| 1118 | if (aerr) |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1119 | MAC_(record_address_error)( VG_(get_current_tid)(), a, 1, True ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1120 | } |
| 1121 | |
| 1122 | |
| 1123 | /* --------------------------------------------------------------------- |
| 1124 | Called from generated code, or from the assembly helpers. |
| 1125 | Handlers for value check failures. |
| 1126 | ------------------------------------------------------------------ */ |
| 1127 | |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1128 | void MC_(helperc_value_check0_fail) ( void ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1129 | { |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1130 | MC_(record_value_error) ( VG_(get_current_tid)(), 0 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1131 | } |
| 1132 | |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1133 | void MC_(helperc_value_check1_fail) ( void ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1134 | { |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1135 | MC_(record_value_error) ( VG_(get_current_tid)(), 1 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1136 | } |
| 1137 | |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1138 | void MC_(helperc_value_check2_fail) ( void ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1139 | { |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1140 | MC_(record_value_error) ( VG_(get_current_tid)(), 2 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1141 | } |
| 1142 | |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1143 | void MC_(helperc_value_check4_fail) ( void ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1144 | { |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1145 | MC_(record_value_error) ( VG_(get_current_tid)(), 4 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1146 | } |
| 1147 | |
| 1148 | |
| 1149 | /* --------------------------------------------------------------------- |
| 1150 | FPU load and store checks, called from generated code. |
| 1151 | ------------------------------------------------------------------ */ |
| 1152 | |
nethercote | eec4630 | 2004-08-23 15:06:23 +0000 | [diff] [blame] | 1153 | REGPARM(2) |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 1154 | void MC_(fpu_read_check) ( Addr addr, SizeT size ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1155 | { |
| 1156 | /* Ensure the read area is both addressible and valid (ie, |
| 1157 | readable). If there's an address error, don't report a value |
| 1158 | error too; but if there isn't an address error, check for a |
| 1159 | value error. |
| 1160 | |
| 1161 | Try to be reasonably fast on the common case; wimp out and defer |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1162 | to mc_fpu_read_check_SLOWLY for everything else. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1163 | |
| 1164 | SecMap* sm; |
| 1165 | UInt sm_off, v_off, a_off; |
| 1166 | Addr addr4; |
| 1167 | |
| 1168 | PROF_EVENT(80); |
| 1169 | |
| 1170 | # ifdef VG_DEBUG_MEMORY |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1171 | mc_fpu_read_check_SLOWLY ( addr, size ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1172 | # else |
| 1173 | |
| 1174 | if (size == 4) { |
| 1175 | if (!IS_ALIGNED4_ADDR(addr)) goto slow4; |
| 1176 | PROF_EVENT(81); |
| 1177 | /* Properly aligned. */ |
| 1178 | sm = primary_map[addr >> 16]; |
| 1179 | sm_off = addr & 0xFFFF; |
| 1180 | a_off = sm_off >> 3; |
| 1181 | if (sm->abits[a_off] != VGM_BYTE_VALID) goto slow4; |
| 1182 | /* Properly aligned and addressible. */ |
| 1183 | v_off = addr & 0xFFFF; |
| 1184 | if (((UInt*)(sm->vbyte))[ v_off >> 2 ] != VGM_WORD_VALID) |
| 1185 | goto slow4; |
| 1186 | /* Properly aligned, addressible and with valid data. */ |
| 1187 | return; |
| 1188 | slow4: |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1189 | mc_fpu_read_check_SLOWLY ( addr, 4 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1190 | return; |
| 1191 | } |
| 1192 | |
| 1193 | if (size == 8) { |
| 1194 | if (!IS_ALIGNED4_ADDR(addr)) goto slow8; |
| 1195 | PROF_EVENT(82); |
| 1196 | /* Properly aligned. Do it in two halves. */ |
| 1197 | addr4 = addr + 4; |
| 1198 | /* First half. */ |
| 1199 | sm = primary_map[addr >> 16]; |
| 1200 | sm_off = addr & 0xFFFF; |
| 1201 | a_off = sm_off >> 3; |
| 1202 | if (sm->abits[a_off] != VGM_BYTE_VALID) goto slow8; |
| 1203 | /* First half properly aligned and addressible. */ |
| 1204 | v_off = addr & 0xFFFF; |
| 1205 | if (((UInt*)(sm->vbyte))[ v_off >> 2 ] != VGM_WORD_VALID) |
| 1206 | goto slow8; |
| 1207 | /* Second half. */ |
| 1208 | sm = primary_map[addr4 >> 16]; |
| 1209 | sm_off = addr4 & 0xFFFF; |
| 1210 | a_off = sm_off >> 3; |
| 1211 | if (sm->abits[a_off] != VGM_BYTE_VALID) goto slow8; |
| 1212 | /* Second half properly aligned and addressible. */ |
| 1213 | v_off = addr4 & 0xFFFF; |
| 1214 | if (((UInt*)(sm->vbyte))[ v_off >> 2 ] != VGM_WORD_VALID) |
| 1215 | goto slow8; |
| 1216 | /* Both halves properly aligned, addressible and with valid |
| 1217 | data. */ |
| 1218 | return; |
| 1219 | slow8: |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1220 | mc_fpu_read_check_SLOWLY ( addr, 8 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1221 | return; |
| 1222 | } |
| 1223 | |
| 1224 | /* Can't be bothered to huff'n'puff to make these (allegedly) rare |
| 1225 | cases go quickly. */ |
| 1226 | if (size == 2) { |
| 1227 | PROF_EVENT(83); |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1228 | mc_fpu_read_check_SLOWLY ( addr, 2 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1229 | return; |
| 1230 | } |
| 1231 | |
sewardj | 93992e2 | 2003-05-26 09:17:41 +0000 | [diff] [blame] | 1232 | if (size == 16 /*SSE*/ |
jseward | fca6018 | 2004-01-04 23:30:55 +0000 | [diff] [blame] | 1233 | || size == 10 || size == 28 || size == 108 || size == 512) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1234 | PROF_EVENT(84); |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1235 | mc_fpu_read_check_SLOWLY ( addr, size ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1236 | return; |
| 1237 | } |
| 1238 | |
| 1239 | VG_(printf)("size is %d\n", size); |
njn | 6799325 | 2004-11-22 18:02:32 +0000 | [diff] [blame^] | 1240 | VG_(tool_panic)("MC_(fpu_read_check): unhandled size"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1241 | # endif |
| 1242 | } |
| 1243 | |
| 1244 | |
nethercote | eec4630 | 2004-08-23 15:06:23 +0000 | [diff] [blame] | 1245 | REGPARM(2) |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 1246 | void MC_(fpu_write_check) ( Addr addr, SizeT size ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1247 | { |
| 1248 | /* Ensure the written area is addressible, and moan if otherwise. |
| 1249 | If it is addressible, make it valid, otherwise invalid. |
| 1250 | */ |
| 1251 | |
| 1252 | SecMap* sm; |
| 1253 | UInt sm_off, v_off, a_off; |
| 1254 | Addr addr4; |
| 1255 | |
| 1256 | PROF_EVENT(85); |
| 1257 | |
| 1258 | # ifdef VG_DEBUG_MEMORY |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1259 | mc_fpu_write_check_SLOWLY ( addr, size ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1260 | # else |
| 1261 | |
| 1262 | if (size == 4) { |
| 1263 | if (!IS_ALIGNED4_ADDR(addr)) goto slow4; |
| 1264 | PROF_EVENT(86); |
| 1265 | /* Properly aligned. */ |
| 1266 | sm = primary_map[addr >> 16]; |
| 1267 | sm_off = addr & 0xFFFF; |
| 1268 | a_off = sm_off >> 3; |
| 1269 | if (sm->abits[a_off] != VGM_BYTE_VALID) goto slow4; |
| 1270 | /* Properly aligned and addressible. Make valid. */ |
| 1271 | v_off = addr & 0xFFFF; |
| 1272 | ((UInt*)(sm->vbyte))[ v_off >> 2 ] = VGM_WORD_VALID; |
| 1273 | return; |
| 1274 | slow4: |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1275 | mc_fpu_write_check_SLOWLY ( addr, 4 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1276 | return; |
| 1277 | } |
| 1278 | |
| 1279 | if (size == 8) { |
| 1280 | if (!IS_ALIGNED4_ADDR(addr)) goto slow8; |
| 1281 | PROF_EVENT(87); |
| 1282 | /* Properly aligned. Do it in two halves. */ |
| 1283 | addr4 = addr + 4; |
| 1284 | /* First half. */ |
| 1285 | sm = primary_map[addr >> 16]; |
| 1286 | sm_off = addr & 0xFFFF; |
| 1287 | a_off = sm_off >> 3; |
| 1288 | if (sm->abits[a_off] != VGM_BYTE_VALID) goto slow8; |
| 1289 | /* First half properly aligned and addressible. Make valid. */ |
| 1290 | v_off = addr & 0xFFFF; |
| 1291 | ((UInt*)(sm->vbyte))[ v_off >> 2 ] = VGM_WORD_VALID; |
| 1292 | /* Second half. */ |
| 1293 | sm = primary_map[addr4 >> 16]; |
| 1294 | sm_off = addr4 & 0xFFFF; |
| 1295 | a_off = sm_off >> 3; |
| 1296 | if (sm->abits[a_off] != VGM_BYTE_VALID) goto slow8; |
| 1297 | /* Second half properly aligned and addressible. */ |
| 1298 | v_off = addr4 & 0xFFFF; |
| 1299 | ((UInt*)(sm->vbyte))[ v_off >> 2 ] = VGM_WORD_VALID; |
| 1300 | /* Properly aligned, addressible and with valid data. */ |
| 1301 | return; |
| 1302 | slow8: |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1303 | mc_fpu_write_check_SLOWLY ( addr, 8 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1304 | return; |
| 1305 | } |
| 1306 | |
| 1307 | /* Can't be bothered to huff'n'puff to make these (allegedly) rare |
| 1308 | cases go quickly. */ |
| 1309 | if (size == 2) { |
| 1310 | PROF_EVENT(88); |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1311 | mc_fpu_write_check_SLOWLY ( addr, 2 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1312 | return; |
| 1313 | } |
| 1314 | |
sewardj | 93992e2 | 2003-05-26 09:17:41 +0000 | [diff] [blame] | 1315 | if (size == 16 /*SSE*/ |
jseward | fca6018 | 2004-01-04 23:30:55 +0000 | [diff] [blame] | 1316 | || size == 10 || size == 28 || size == 108 || size == 512) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1317 | PROF_EVENT(89); |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1318 | mc_fpu_write_check_SLOWLY ( addr, size ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1319 | return; |
| 1320 | } |
| 1321 | |
| 1322 | VG_(printf)("size is %d\n", size); |
njn | 6799325 | 2004-11-22 18:02:32 +0000 | [diff] [blame^] | 1323 | VG_(tool_panic)("MC_(fpu_write_check): unhandled size"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1324 | # endif |
| 1325 | } |
| 1326 | |
| 1327 | |
| 1328 | /* --------------------------------------------------------------------- |
| 1329 | Slow, general cases for FPU load and store checks. |
| 1330 | ------------------------------------------------------------------ */ |
| 1331 | |
| 1332 | /* Generic version. Test for both addr and value errors, but if |
| 1333 | there's an addr error, don't report a value error even if it |
| 1334 | exists. */ |
| 1335 | |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 1336 | void mc_fpu_read_check_SLOWLY ( Addr addr, SizeT size ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1337 | { |
| 1338 | Int i; |
| 1339 | Bool aerr = False; |
| 1340 | Bool verr = False; |
| 1341 | PROF_EVENT(90); |
| 1342 | for (i = 0; i < size; i++) { |
| 1343 | PROF_EVENT(91); |
| 1344 | if (get_abit(addr+i) != VGM_BIT_VALID) |
| 1345 | aerr = True; |
| 1346 | if (get_vbyte(addr+i) != VGM_BYTE_VALID) |
| 1347 | verr = True; |
| 1348 | } |
| 1349 | |
| 1350 | if (aerr) { |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1351 | MAC_(record_address_error)( VG_(get_current_tid)(), addr, size, False ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1352 | } else { |
| 1353 | if (verr) |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1354 | MC_(record_value_error)( VG_(get_current_tid)(), size ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1355 | } |
| 1356 | } |
| 1357 | |
| 1358 | |
| 1359 | /* Generic version. Test for addr errors. Valid addresses are |
| 1360 | given valid values, and invalid addresses invalid values. */ |
| 1361 | |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 1362 | void mc_fpu_write_check_SLOWLY ( Addr addr, SizeT size ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1363 | { |
| 1364 | Int i; |
| 1365 | Addr a_here; |
| 1366 | Bool a_ok; |
| 1367 | Bool aerr = False; |
| 1368 | PROF_EVENT(92); |
| 1369 | for (i = 0; i < size; i++) { |
| 1370 | PROF_EVENT(93); |
| 1371 | a_here = addr+i; |
| 1372 | a_ok = get_abit(a_here) == VGM_BIT_VALID; |
| 1373 | if (a_ok) { |
| 1374 | set_vbyte(a_here, VGM_BYTE_VALID); |
| 1375 | } else { |
| 1376 | set_vbyte(a_here, VGM_BYTE_INVALID); |
| 1377 | aerr = True; |
| 1378 | } |
| 1379 | } |
| 1380 | if (aerr) { |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1381 | MAC_(record_address_error)( VG_(get_current_tid)(), addr, size, True ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1382 | } |
| 1383 | } |
| 1384 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1385 | |
| 1386 | /*------------------------------------------------------------*/ |
sewardj | ee07084 | 2003-07-05 17:53:55 +0000 | [diff] [blame] | 1387 | /*--- Metadata get/set functions, for client requests. ---*/ |
| 1388 | /*------------------------------------------------------------*/ |
| 1389 | |
| 1390 | /* Copy Vbits for src into vbits. Returns: 1 == OK, 2 == alignment |
| 1391 | error, 3 == addressing error. */ |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 1392 | static Int mc_get_or_set_vbits_for_client ( |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1393 | ThreadId tid, |
sewardj | ee07084 | 2003-07-05 17:53:55 +0000 | [diff] [blame] | 1394 | Addr dataV, |
| 1395 | Addr vbitsV, |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 1396 | SizeT size, |
sewardj | ee07084 | 2003-07-05 17:53:55 +0000 | [diff] [blame] | 1397 | Bool setting /* True <=> set vbits, False <=> get vbits */ |
| 1398 | ) |
| 1399 | { |
| 1400 | Bool addressibleD = True; |
| 1401 | Bool addressibleV = True; |
| 1402 | UInt* data = (UInt*)dataV; |
| 1403 | UInt* vbits = (UInt*)vbitsV; |
nethercote | 451eae9 | 2004-11-02 13:06:32 +0000 | [diff] [blame] | 1404 | SizeT szW = size / 4; /* sigh */ |
| 1405 | SizeT i; |
sewardj | af48a60 | 2003-07-06 00:54:47 +0000 | [diff] [blame] | 1406 | UInt* dataP = NULL; /* bogus init to keep gcc happy */ |
| 1407 | UInt* vbitsP = NULL; /* ditto */ |
sewardj | ee07084 | 2003-07-05 17:53:55 +0000 | [diff] [blame] | 1408 | |
| 1409 | /* Check alignment of args. */ |
| 1410 | if (!(IS_ALIGNED4_ADDR(data) && IS_ALIGNED4_ADDR(vbits))) |
| 1411 | return 2; |
| 1412 | if ((size & 3) != 0) |
| 1413 | return 2; |
| 1414 | |
| 1415 | /* Check that arrays are addressible. */ |
| 1416 | for (i = 0; i < szW; i++) { |
sewardj | af48a60 | 2003-07-06 00:54:47 +0000 | [diff] [blame] | 1417 | dataP = &data[i]; |
| 1418 | vbitsP = &vbits[i]; |
sewardj | ee07084 | 2003-07-05 17:53:55 +0000 | [diff] [blame] | 1419 | if (get_abits4_ALIGNED((Addr)dataP) != VGM_NIBBLE_VALID) { |
| 1420 | addressibleD = False; |
| 1421 | break; |
| 1422 | } |
| 1423 | if (get_abits4_ALIGNED((Addr)vbitsP) != VGM_NIBBLE_VALID) { |
| 1424 | addressibleV = False; |
| 1425 | break; |
| 1426 | } |
| 1427 | } |
| 1428 | if (!addressibleD) { |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1429 | MAC_(record_address_error)( tid, (Addr)dataP, 4, |
sewardj | ee07084 | 2003-07-05 17:53:55 +0000 | [diff] [blame] | 1430 | setting ? True : False ); |
| 1431 | return 3; |
| 1432 | } |
| 1433 | if (!addressibleV) { |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1434 | MAC_(record_address_error)( tid, (Addr)vbitsP, 4, |
sewardj | ee07084 | 2003-07-05 17:53:55 +0000 | [diff] [blame] | 1435 | setting ? False : True ); |
| 1436 | return 3; |
| 1437 | } |
| 1438 | |
| 1439 | /* Do the copy */ |
| 1440 | if (setting) { |
| 1441 | /* setting */ |
| 1442 | for (i = 0; i < szW; i++) { |
| 1443 | if (get_vbytes4_ALIGNED( (Addr)&vbits[i] ) != VGM_WORD_VALID) |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 1444 | MC_(record_value_error)(tid, 4); |
sewardj | ee07084 | 2003-07-05 17:53:55 +0000 | [diff] [blame] | 1445 | set_vbytes4_ALIGNED( (Addr)&data[i], vbits[i] ); |
| 1446 | } |
| 1447 | } else { |
| 1448 | /* getting */ |
| 1449 | for (i = 0; i < szW; i++) { |
| 1450 | vbits[i] = get_vbytes4_ALIGNED( (Addr)&data[i] ); |
| 1451 | set_vbytes4_ALIGNED( (Addr)&vbits[i], VGM_WORD_VALID ); |
| 1452 | } |
| 1453 | } |
| 1454 | |
| 1455 | return 1; |
| 1456 | } |
| 1457 | |
| 1458 | |
| 1459 | /*------------------------------------------------------------*/ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1460 | /*--- Detecting leaked (unreachable) malloc'd blocks. ---*/ |
| 1461 | /*------------------------------------------------------------*/ |
| 1462 | |
sewardj | a449568 | 2002-10-21 07:29:59 +0000 | [diff] [blame] | 1463 | /* For the memory leak detector, say whether an entire 64k chunk of |
| 1464 | address space is possibly in use, or not. If in doubt return |
| 1465 | True. |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1466 | */ |
sewardj | a449568 | 2002-10-21 07:29:59 +0000 | [diff] [blame] | 1467 | static |
| 1468 | Bool mc_is_valid_64k_chunk ( UInt chunk_number ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1469 | { |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 1470 | tl_assert(chunk_number >= 0 && chunk_number < 65536); |
sewardj | a449568 | 2002-10-21 07:29:59 +0000 | [diff] [blame] | 1471 | if (IS_DISTINGUISHED_SM(primary_map[chunk_number])) { |
| 1472 | /* Definitely not in use. */ |
| 1473 | return False; |
| 1474 | } else { |
| 1475 | return True; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1476 | } |
| 1477 | } |
| 1478 | |
| 1479 | |
sewardj | a449568 | 2002-10-21 07:29:59 +0000 | [diff] [blame] | 1480 | /* For the memory leak detector, say whether or not a given word |
| 1481 | address is to be regarded as valid. */ |
| 1482 | static |
| 1483 | Bool mc_is_valid_address ( Addr a ) |
| 1484 | { |
| 1485 | UInt vbytes; |
| 1486 | UChar abits; |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 1487 | tl_assert(IS_ALIGNED4_ADDR(a)); |
sewardj | a449568 | 2002-10-21 07:29:59 +0000 | [diff] [blame] | 1488 | abits = get_abits4_ALIGNED(a); |
| 1489 | vbytes = get_vbytes4_ALIGNED(a); |
| 1490 | if (abits == VGM_NIBBLE_VALID && vbytes == VGM_WORD_VALID) { |
| 1491 | return True; |
| 1492 | } else { |
| 1493 | return False; |
| 1494 | } |
| 1495 | } |
| 1496 | |
| 1497 | |
nethercote | 996901a | 2004-08-03 13:29:09 +0000 | [diff] [blame] | 1498 | /* Leak detector for this tool. We don't actually do anything, merely |
sewardj | a449568 | 2002-10-21 07:29:59 +0000 | [diff] [blame] | 1499 | run the generic leak detector with suitable parameters for this |
nethercote | 996901a | 2004-08-03 13:29:09 +0000 | [diff] [blame] | 1500 | tool. */ |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 1501 | static void mc_detect_memory_leaks ( void ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1502 | { |
njn | 43c799e | 2003-04-08 00:08:52 +0000 | [diff] [blame] | 1503 | MAC_(do_detect_memory_leaks) ( mc_is_valid_64k_chunk, mc_is_valid_address ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1504 | } |
| 1505 | |
| 1506 | |
| 1507 | /* --------------------------------------------------------------------- |
| 1508 | Sanity check machinery (permanently engaged). |
| 1509 | ------------------------------------------------------------------ */ |
| 1510 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1511 | Bool SK_(cheap_sanity_check) ( void ) |
| 1512 | { |
jseward | 9800fd3 | 2004-01-04 23:08:04 +0000 | [diff] [blame] | 1513 | /* nothing useful we can rapidly check */ |
| 1514 | return True; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1515 | } |
| 1516 | |
| 1517 | Bool SK_(expensive_sanity_check) ( void ) |
| 1518 | { |
| 1519 | Int i; |
| 1520 | |
| 1521 | /* Make sure nobody changed the distinguished secondary. */ |
| 1522 | for (i = 0; i < 8192; i++) |
| 1523 | if (distinguished_secondary_map.abits[i] != VGM_BYTE_INVALID) |
| 1524 | return False; |
| 1525 | |
| 1526 | for (i = 0; i < 65536; i++) |
| 1527 | if (distinguished_secondary_map.vbyte[i] != VGM_BYTE_INVALID) |
| 1528 | return False; |
| 1529 | |
| 1530 | /* Make sure that the upper 3/4 of the primary map hasn't |
| 1531 | been messed with. */ |
| 1532 | for (i = 65536; i < 262144; i++) |
| 1533 | if (primary_map[i] != & distinguished_secondary_map) |
| 1534 | return False; |
| 1535 | |
| 1536 | return True; |
| 1537 | } |
| 1538 | |
| 1539 | /* --------------------------------------------------------------------- |
| 1540 | Debugging machinery (turn on to debug). Something of a mess. |
| 1541 | ------------------------------------------------------------------ */ |
| 1542 | |
| 1543 | #if 0 |
| 1544 | /* Print the value tags on the 8 integer registers & flag reg. */ |
| 1545 | |
| 1546 | static void uint_to_bits ( UInt x, Char* str ) |
| 1547 | { |
| 1548 | Int i; |
| 1549 | Int w = 0; |
| 1550 | /* str must point to a space of at least 36 bytes. */ |
| 1551 | for (i = 31; i >= 0; i--) { |
| 1552 | str[w++] = (x & ( ((UInt)1) << i)) ? '1' : '0'; |
| 1553 | if (i == 24 || i == 16 || i == 8) |
| 1554 | str[w++] = ' '; |
| 1555 | } |
| 1556 | str[w++] = 0; |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 1557 | tl_assert(w == 36); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1558 | } |
| 1559 | |
| 1560 | /* Caution! Not vthread-safe; looks in VG_(baseBlock), not the thread |
| 1561 | state table. */ |
| 1562 | |
| 1563 | static void vg_show_reg_tags ( void ) |
| 1564 | { |
| 1565 | Char buf1[36]; |
| 1566 | Char buf2[36]; |
| 1567 | UInt z_eax, z_ebx, z_ecx, z_edx, |
| 1568 | z_esi, z_edi, z_ebp, z_esp, z_eflags; |
| 1569 | |
| 1570 | z_eax = VG_(baseBlock)[VGOFF_(sh_eax)]; |
| 1571 | z_ebx = VG_(baseBlock)[VGOFF_(sh_ebx)]; |
| 1572 | z_ecx = VG_(baseBlock)[VGOFF_(sh_ecx)]; |
| 1573 | z_edx = VG_(baseBlock)[VGOFF_(sh_edx)]; |
| 1574 | z_esi = VG_(baseBlock)[VGOFF_(sh_esi)]; |
| 1575 | z_edi = VG_(baseBlock)[VGOFF_(sh_edi)]; |
| 1576 | z_ebp = VG_(baseBlock)[VGOFF_(sh_ebp)]; |
| 1577 | z_esp = VG_(baseBlock)[VGOFF_(sh_esp)]; |
| 1578 | z_eflags = VG_(baseBlock)[VGOFF_(sh_eflags)]; |
| 1579 | |
| 1580 | uint_to_bits(z_eflags, buf1); |
njn | 9b6d34e | 2002-10-15 08:48:08 +0000 | [diff] [blame] | 1581 | VG_(message)(Vg_DebugMsg, "efl %s\n", buf1); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1582 | |
| 1583 | uint_to_bits(z_eax, buf1); |
| 1584 | uint_to_bits(z_ebx, buf2); |
| 1585 | VG_(message)(Vg_DebugMsg, "eax %s ebx %s\n", buf1, buf2); |
| 1586 | |
| 1587 | uint_to_bits(z_ecx, buf1); |
| 1588 | uint_to_bits(z_edx, buf2); |
| 1589 | VG_(message)(Vg_DebugMsg, "ecx %s edx %s\n", buf1, buf2); |
| 1590 | |
| 1591 | uint_to_bits(z_esi, buf1); |
| 1592 | uint_to_bits(z_edi, buf2); |
| 1593 | VG_(message)(Vg_DebugMsg, "esi %s edi %s\n", buf1, buf2); |
| 1594 | |
| 1595 | uint_to_bits(z_ebp, buf1); |
| 1596 | uint_to_bits(z_esp, buf2); |
| 1597 | VG_(message)(Vg_DebugMsg, "ebp %s esp %s\n", buf1, buf2); |
| 1598 | } |
| 1599 | |
| 1600 | |
| 1601 | /* For debugging only. Scan the address space and touch all allegedly |
| 1602 | addressible words. Useful for establishing where Valgrind's idea of |
| 1603 | addressibility has diverged from what the kernel believes. */ |
| 1604 | |
| 1605 | static |
| 1606 | void zzzmemscan_notify_word ( Addr a, UInt w ) |
| 1607 | { |
| 1608 | } |
| 1609 | |
| 1610 | void zzzmemscan ( void ) |
| 1611 | { |
| 1612 | Int n_notifies |
| 1613 | = VG_(scan_all_valid_memory)( zzzmemscan_notify_word ); |
| 1614 | VG_(printf)("zzzmemscan: n_bytes = %d\n", 4 * n_notifies ); |
| 1615 | } |
| 1616 | #endif |
| 1617 | |
| 1618 | |
| 1619 | |
| 1620 | |
| 1621 | #if 0 |
| 1622 | static Int zzz = 0; |
| 1623 | |
| 1624 | void show_bb ( Addr eip_next ) |
| 1625 | { |
| 1626 | VG_(printf)("[%4d] ", zzz); |
| 1627 | vg_show_reg_tags( &VG_(m_shadow ); |
| 1628 | VG_(translate) ( eip_next, NULL, NULL, NULL ); |
| 1629 | } |
| 1630 | #endif /* 0 */ |
| 1631 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1632 | |
| 1633 | /*------------------------------------------------------------*/ |
njn | d304045 | 2003-05-19 15:04:06 +0000 | [diff] [blame] | 1634 | /*--- Command line args ---*/ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1635 | /*------------------------------------------------------------*/ |
| 1636 | |
njn | 43c799e | 2003-04-08 00:08:52 +0000 | [diff] [blame] | 1637 | Bool MC_(clo_avoid_strlen_errors) = True; |
| 1638 | Bool MC_(clo_cleanup) = True; |
| 1639 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1640 | Bool SK_(process_cmd_line_option)(Char* arg) |
| 1641 | { |
nethercote | 27fec90 | 2004-06-16 21:26:32 +0000 | [diff] [blame] | 1642 | VG_BOOL_CLO("--avoid-strlen-errors", MC_(clo_avoid_strlen_errors)) |
| 1643 | else VG_BOOL_CLO("--cleanup", MC_(clo_cleanup)) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1644 | else |
njn | 43c799e | 2003-04-08 00:08:52 +0000 | [diff] [blame] | 1645 | return MAC_(process_common_cmd_line_option)(arg); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1646 | |
| 1647 | return True; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1648 | } |
| 1649 | |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1650 | void SK_(print_usage)(void) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1651 | { |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1652 | MAC_(print_common_usage)(); |
| 1653 | VG_(printf)( |
| 1654 | " --avoid-strlen-errors=no|yes suppress errs from inlined strlen [yes]\n" |
| 1655 | ); |
| 1656 | } |
| 1657 | |
| 1658 | void SK_(print_debug_usage)(void) |
| 1659 | { |
| 1660 | MAC_(print_common_debug_usage)(); |
| 1661 | VG_(printf)( |
sewardj | 8ec2cfc | 2002-10-13 00:57:26 +0000 | [diff] [blame] | 1662 | " --cleanup=no|yes improve after instrumentation? [yes]\n" |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1663 | ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1664 | } |
| 1665 | |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 1666 | /*------------------------------------------------------------*/ |
| 1667 | /*--- Client requests ---*/ |
| 1668 | /*------------------------------------------------------------*/ |
| 1669 | |
| 1670 | /* Client block management: |
| 1671 | |
| 1672 | This is managed as an expanding array of client block descriptors. |
| 1673 | Indices of live descriptors are issued to the client, so it can ask |
| 1674 | to free them later. Therefore we cannot slide live entries down |
| 1675 | over dead ones. Instead we must use free/inuse flags and scan for |
| 1676 | an empty slot at allocation time. This in turn means allocation is |
| 1677 | relatively expensive, so we hope this does not happen too often. |
| 1678 | */ |
| 1679 | |
| 1680 | typedef |
| 1681 | enum { CG_NotInUse, CG_NoAccess, CG_Writable, CG_Readable } |
| 1682 | CGenBlockKind; |
| 1683 | |
| 1684 | typedef |
| 1685 | struct { |
| 1686 | Addr start; |
| 1687 | SizeT size; |
| 1688 | ExeContext* where; |
| 1689 | CGenBlockKind kind; |
| 1690 | } |
| 1691 | CGenBlock; |
| 1692 | |
| 1693 | /* This subsystem is self-initialising. */ |
| 1694 | static UInt vg_cgb_size = 0; |
| 1695 | static UInt vg_cgb_used = 0; |
| 1696 | static CGenBlock* vg_cgbs = NULL; |
| 1697 | |
| 1698 | /* Stats for this subsystem. */ |
| 1699 | static UInt vg_cgb_used_MAX = 0; /* Max in use. */ |
| 1700 | static UInt vg_cgb_allocs = 0; /* Number of allocs. */ |
| 1701 | static UInt vg_cgb_discards = 0; /* Number of discards. */ |
| 1702 | static UInt vg_cgb_search = 0; /* Number of searches. */ |
| 1703 | |
| 1704 | |
| 1705 | static |
| 1706 | Int vg_alloc_client_block ( void ) |
| 1707 | { |
| 1708 | UInt i, sz_new; |
| 1709 | CGenBlock* cgbs_new; |
| 1710 | |
| 1711 | vg_cgb_allocs++; |
| 1712 | |
| 1713 | for (i = 0; i < vg_cgb_used; i++) { |
| 1714 | vg_cgb_search++; |
| 1715 | if (vg_cgbs[i].kind == CG_NotInUse) |
| 1716 | return i; |
| 1717 | } |
| 1718 | |
| 1719 | /* Not found. Try to allocate one at the end. */ |
| 1720 | if (vg_cgb_used < vg_cgb_size) { |
| 1721 | vg_cgb_used++; |
| 1722 | return vg_cgb_used-1; |
| 1723 | } |
| 1724 | |
| 1725 | /* Ok, we have to allocate a new one. */ |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 1726 | tl_assert(vg_cgb_used == vg_cgb_size); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 1727 | sz_new = (vg_cgbs == NULL) ? 10 : (2 * vg_cgb_size); |
| 1728 | |
| 1729 | cgbs_new = VG_(malloc)( sz_new * sizeof(CGenBlock) ); |
| 1730 | for (i = 0; i < vg_cgb_used; i++) |
| 1731 | cgbs_new[i] = vg_cgbs[i]; |
| 1732 | |
| 1733 | if (vg_cgbs != NULL) |
| 1734 | VG_(free)( vg_cgbs ); |
| 1735 | vg_cgbs = cgbs_new; |
| 1736 | |
| 1737 | vg_cgb_size = sz_new; |
| 1738 | vg_cgb_used++; |
| 1739 | if (vg_cgb_used > vg_cgb_used_MAX) |
| 1740 | vg_cgb_used_MAX = vg_cgb_used; |
| 1741 | return vg_cgb_used-1; |
| 1742 | } |
| 1743 | |
| 1744 | |
| 1745 | static void show_client_block_stats ( void ) |
| 1746 | { |
| 1747 | VG_(message)(Vg_DebugMsg, |
| 1748 | "general CBs: %d allocs, %d discards, %d maxinuse, %d search", |
| 1749 | vg_cgb_allocs, vg_cgb_discards, vg_cgb_used_MAX, vg_cgb_search |
| 1750 | ); |
| 1751 | } |
| 1752 | |
| 1753 | static Bool find_addr(VgHashNode* sh_ch, void* ap) |
| 1754 | { |
| 1755 | MAC_Chunk *m = (MAC_Chunk*)sh_ch; |
| 1756 | Addr a = *(Addr*)ap; |
| 1757 | |
| 1758 | return VG_(addr_is_in_block)(a, m->data, m->size); |
| 1759 | } |
| 1760 | |
| 1761 | static Bool client_perm_maybe_describe( Addr a, AddrInfo* ai ) |
| 1762 | { |
| 1763 | UInt i; |
| 1764 | /* VG_(printf)("try to identify %d\n", a); */ |
| 1765 | |
| 1766 | /* Perhaps it's a general block ? */ |
| 1767 | for (i = 0; i < vg_cgb_used; i++) { |
| 1768 | if (vg_cgbs[i].kind == CG_NotInUse) |
| 1769 | continue; |
| 1770 | if (VG_(addr_is_in_block)(a, vg_cgbs[i].start, vg_cgbs[i].size)) { |
| 1771 | MAC_Mempool **d, *mp; |
| 1772 | |
| 1773 | /* OK - maybe it's a mempool, too? */ |
| 1774 | mp = (MAC_Mempool*)VG_(HT_get_node)(MAC_(mempool_list), |
| 1775 | (UWord)vg_cgbs[i].start, |
| 1776 | (void*)&d); |
| 1777 | if(mp != NULL) { |
| 1778 | if(mp->chunks != NULL) { |
| 1779 | MAC_Chunk *mc; |
| 1780 | |
| 1781 | mc = (MAC_Chunk*)VG_(HT_first_match)(mp->chunks, find_addr, &a); |
| 1782 | if(mc != NULL) { |
| 1783 | ai->akind = UserG; |
| 1784 | ai->blksize = mc->size; |
| 1785 | ai->rwoffset = (Int)(a) - (Int)mc->data; |
| 1786 | ai->lastchange = mc->where; |
| 1787 | return True; |
| 1788 | } |
| 1789 | } |
| 1790 | ai->akind = Mempool; |
| 1791 | ai->blksize = vg_cgbs[i].size; |
| 1792 | ai->rwoffset = (Int)(a) - (Int)(vg_cgbs[i].start); |
| 1793 | ai->lastchange = vg_cgbs[i].where; |
| 1794 | return True; |
| 1795 | } |
| 1796 | ai->akind = UserG; |
| 1797 | ai->blksize = vg_cgbs[i].size; |
| 1798 | ai->rwoffset = (Int)(a) - (Int)(vg_cgbs[i].start); |
| 1799 | ai->lastchange = vg_cgbs[i].where; |
| 1800 | return True; |
| 1801 | } |
| 1802 | } |
| 1803 | return False; |
| 1804 | } |
| 1805 | |
| 1806 | Bool SK_(handle_client_request) ( ThreadId tid, UWord* arg, UWord* ret ) |
| 1807 | { |
| 1808 | Int i; |
| 1809 | Bool ok; |
| 1810 | Addr bad_addr; |
| 1811 | |
| 1812 | if (!VG_IS_SKIN_USERREQ('M','C',arg[0]) |
| 1813 | && VG_USERREQ__MALLOCLIKE_BLOCK != arg[0] |
| 1814 | && VG_USERREQ__FREELIKE_BLOCK != arg[0] |
| 1815 | && VG_USERREQ__CREATE_MEMPOOL != arg[0] |
| 1816 | && VG_USERREQ__DESTROY_MEMPOOL != arg[0] |
| 1817 | && VG_USERREQ__MEMPOOL_ALLOC != arg[0] |
| 1818 | && VG_USERREQ__MEMPOOL_FREE != arg[0]) |
| 1819 | return False; |
| 1820 | |
| 1821 | switch (arg[0]) { |
| 1822 | case VG_USERREQ__CHECK_WRITABLE: /* check writable */ |
| 1823 | ok = mc_check_writable ( arg[1], arg[2], &bad_addr ); |
| 1824 | if (!ok) |
| 1825 | MC_(record_user_error) ( tid, bad_addr, /*isWrite*/True, |
| 1826 | /*isUnaddr*/True ); |
| 1827 | *ret = ok ? (UWord)NULL : bad_addr; |
| 1828 | break; |
| 1829 | |
| 1830 | case VG_USERREQ__CHECK_READABLE: { /* check readable */ |
| 1831 | MC_ReadResult res; |
| 1832 | res = mc_check_readable ( arg[1], arg[2], &bad_addr ); |
| 1833 | if (MC_AddrErr == res) |
| 1834 | MC_(record_user_error) ( tid, bad_addr, /*isWrite*/False, |
| 1835 | /*isUnaddr*/True ); |
| 1836 | else if (MC_ValueErr == res) |
| 1837 | MC_(record_user_error) ( tid, bad_addr, /*isWrite*/False, |
| 1838 | /*isUnaddr*/False ); |
| 1839 | *ret = ( res==MC_Ok ? (UWord)NULL : bad_addr ); |
| 1840 | break; |
| 1841 | } |
| 1842 | |
| 1843 | case VG_USERREQ__DO_LEAK_CHECK: |
| 1844 | mc_detect_memory_leaks(); |
| 1845 | *ret = 0; /* return value is meaningless */ |
| 1846 | break; |
| 1847 | |
| 1848 | case VG_USERREQ__MAKE_NOACCESS: /* make no access */ |
| 1849 | i = vg_alloc_client_block(); |
| 1850 | /* VG_(printf)("allocated %d %p\n", i, vg_cgbs); */ |
| 1851 | vg_cgbs[i].kind = CG_NoAccess; |
| 1852 | vg_cgbs[i].start = arg[1]; |
| 1853 | vg_cgbs[i].size = arg[2]; |
| 1854 | vg_cgbs[i].where = VG_(get_ExeContext) ( tid ); |
| 1855 | mc_make_noaccess ( arg[1], arg[2] ); |
| 1856 | *ret = i; |
| 1857 | break; |
| 1858 | |
| 1859 | case VG_USERREQ__MAKE_WRITABLE: /* make writable */ |
| 1860 | i = vg_alloc_client_block(); |
| 1861 | vg_cgbs[i].kind = CG_Writable; |
| 1862 | vg_cgbs[i].start = arg[1]; |
| 1863 | vg_cgbs[i].size = arg[2]; |
| 1864 | vg_cgbs[i].where = VG_(get_ExeContext) ( tid ); |
| 1865 | mc_make_writable ( arg[1], arg[2] ); |
| 1866 | *ret = i; |
| 1867 | break; |
| 1868 | |
| 1869 | case VG_USERREQ__MAKE_READABLE: /* make readable */ |
| 1870 | i = vg_alloc_client_block(); |
| 1871 | vg_cgbs[i].kind = CG_Readable; |
| 1872 | vg_cgbs[i].start = arg[1]; |
| 1873 | vg_cgbs[i].size = arg[2]; |
| 1874 | vg_cgbs[i].where = VG_(get_ExeContext) ( tid ); |
| 1875 | mc_make_readable ( arg[1], arg[2] ); |
| 1876 | *ret = i; |
| 1877 | break; |
| 1878 | |
| 1879 | case VG_USERREQ__DISCARD: /* discard */ |
| 1880 | if (vg_cgbs == NULL |
| 1881 | || arg[2] >= vg_cgb_used || vg_cgbs[arg[2]].kind == CG_NotInUse) |
| 1882 | return 1; |
njn | ca82cc0 | 2004-11-22 17:18:48 +0000 | [diff] [blame] | 1883 | tl_assert(arg[2] >= 0 && arg[2] < vg_cgb_used); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 1884 | vg_cgbs[arg[2]].kind = CG_NotInUse; |
| 1885 | vg_cgb_discards++; |
| 1886 | *ret = 0; |
| 1887 | break; |
| 1888 | |
| 1889 | case VG_USERREQ__GET_VBITS: |
| 1890 | /* Returns: 1 == OK, 2 == alignment error, 3 == addressing |
| 1891 | error. */ |
| 1892 | /* VG_(printf)("get_vbits %p %p %d\n", arg[1], arg[2], arg[3] ); */ |
| 1893 | *ret = mc_get_or_set_vbits_for_client |
| 1894 | ( tid, arg[1], arg[2], arg[3], False /* get them */ ); |
| 1895 | break; |
| 1896 | |
| 1897 | case VG_USERREQ__SET_VBITS: |
| 1898 | /* Returns: 1 == OK, 2 == alignment error, 3 == addressing |
| 1899 | error. */ |
| 1900 | /* VG_(printf)("set_vbits %p %p %d\n", arg[1], arg[2], arg[3] ); */ |
| 1901 | *ret = mc_get_or_set_vbits_for_client |
| 1902 | ( tid, arg[1], arg[2], arg[3], True /* set them */ ); |
| 1903 | break; |
| 1904 | |
| 1905 | default: |
| 1906 | if (MAC_(handle_common_client_requests)(tid, arg, ret )) { |
| 1907 | return True; |
| 1908 | } else { |
| 1909 | VG_(message)(Vg_UserMsg, |
| 1910 | "Warning: unknown memcheck client request code %llx", |
| 1911 | (ULong)arg[0]); |
| 1912 | return False; |
| 1913 | } |
| 1914 | } |
| 1915 | return True; |
| 1916 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1917 | |
| 1918 | /*------------------------------------------------------------*/ |
| 1919 | /*--- Setup ---*/ |
| 1920 | /*------------------------------------------------------------*/ |
| 1921 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1922 | void SK_(pre_clo_init)(void) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1923 | { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1924 | VG_(details_name) ("Memcheck"); |
| 1925 | VG_(details_version) (NULL); |
nethercote | 262eedf | 2003-11-13 17:57:18 +0000 | [diff] [blame] | 1926 | VG_(details_description) ("a memory error detector"); |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1927 | VG_(details_copyright_author)( |
nethercote | 08fa9a7 | 2004-07-16 17:44:00 +0000 | [diff] [blame] | 1928 | "Copyright (C) 2002-2004, and GNU GPL'd, by Julian Seward et al."); |
nethercote | 421281e | 2003-11-20 16:20:55 +0000 | [diff] [blame] | 1929 | VG_(details_bug_reports_to) (VG_BUGS_TO); |
sewardj | 78210aa | 2002-12-01 02:55:46 +0000 | [diff] [blame] | 1930 | VG_(details_avg_translation_sizeB) ( 228 ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1931 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1932 | VG_(needs_core_errors) (); |
njn | 95ec870 | 2004-11-22 16:46:13 +0000 | [diff] [blame] | 1933 | VG_(needs_tool_errors) (); |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1934 | VG_(needs_libc_freeres) (); |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1935 | VG_(needs_shadow_regs) (); |
| 1936 | VG_(needs_command_line_options)(); |
| 1937 | VG_(needs_client_requests) (); |
| 1938 | VG_(needs_extended_UCode) (); |
| 1939 | VG_(needs_syscall_wrapper) (); |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1940 | VG_(needs_sanity_checks) (); |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 1941 | VG_(needs_shadow_memory) (); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1942 | |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1943 | MAC_( new_mem_heap) = & mc_new_mem_heap; |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 1944 | MAC_( ban_mem_heap) = & mc_make_noaccess; |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1945 | MAC_(copy_mem_heap) = & mc_copy_address_range_state; |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 1946 | MAC_( die_mem_heap) = & mc_make_noaccess; |
| 1947 | MAC_(check_noaccess) = & mc_check_noaccess; |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1948 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 1949 | VG_(init_new_mem_startup) ( & mc_new_mem_startup ); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 1950 | VG_(init_new_mem_stack_signal) ( & mc_make_writable ); |
| 1951 | VG_(init_new_mem_brk) ( & mc_make_writable ); |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 1952 | VG_(init_new_mem_mmap) ( & mc_set_perms ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1953 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 1954 | VG_(init_copy_mem_remap) ( & mc_copy_address_range_state ); |
| 1955 | VG_(init_change_mem_mprotect) ( & mc_set_perms ); |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1956 | |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 1957 | VG_(init_die_mem_stack_signal) ( & mc_make_noaccess ); |
| 1958 | VG_(init_die_mem_brk) ( & mc_make_noaccess ); |
| 1959 | VG_(init_die_mem_munmap) ( & mc_make_noaccess ); |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 1960 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 1961 | VG_(init_new_mem_stack_4) ( & MAC_(new_mem_stack_4) ); |
| 1962 | VG_(init_new_mem_stack_8) ( & MAC_(new_mem_stack_8) ); |
| 1963 | VG_(init_new_mem_stack_12) ( & MAC_(new_mem_stack_12) ); |
| 1964 | VG_(init_new_mem_stack_16) ( & MAC_(new_mem_stack_16) ); |
| 1965 | VG_(init_new_mem_stack_32) ( & MAC_(new_mem_stack_32) ); |
| 1966 | VG_(init_new_mem_stack) ( & MAC_(new_mem_stack) ); |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1967 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 1968 | VG_(init_die_mem_stack_4) ( & MAC_(die_mem_stack_4) ); |
| 1969 | VG_(init_die_mem_stack_8) ( & MAC_(die_mem_stack_8) ); |
| 1970 | VG_(init_die_mem_stack_12) ( & MAC_(die_mem_stack_12) ); |
| 1971 | VG_(init_die_mem_stack_16) ( & MAC_(die_mem_stack_16) ); |
| 1972 | VG_(init_die_mem_stack_32) ( & MAC_(die_mem_stack_32) ); |
| 1973 | VG_(init_die_mem_stack) ( & MAC_(die_mem_stack) ); |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1974 | |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 1975 | VG_(init_ban_mem_stack) ( & mc_make_noaccess ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1976 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 1977 | VG_(init_pre_mem_read) ( & mc_check_is_readable ); |
| 1978 | VG_(init_pre_mem_read_asciiz) ( & mc_check_is_readable_asciiz ); |
| 1979 | VG_(init_pre_mem_write) ( & mc_check_is_writable ); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 1980 | VG_(init_post_mem_write) ( & mc_make_readable ); |
| 1981 | |
| 1982 | VG_(init_pre_reg_read) ( & mc_pre_reg_read ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1983 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 1984 | VG_(init_post_regs_write_init) ( & mc_post_regs_write_init ); |
| 1985 | VG_(init_post_reg_write_syscall_return) ( & mc_post_reg_write ); |
| 1986 | VG_(init_post_reg_write_deliver_signal) ( & mc_post_reg_write ); |
| 1987 | VG_(init_post_reg_write_pthread_return) ( & mc_post_reg_write ); |
| 1988 | VG_(init_post_reg_write_clientreq_return) ( & mc_post_reg_write ); |
| 1989 | VG_(init_post_reg_write_clientcall_return) ( & mc_post_reg_write_clientcall ); |
njn | d304045 | 2003-05-19 15:04:06 +0000 | [diff] [blame] | 1990 | |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1991 | /* Three compact slots taken up by stack memory helpers */ |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1992 | VG_(register_compact_helper)((Addr) & MC_(helper_value_check4_fail)); |
| 1993 | VG_(register_compact_helper)((Addr) & MC_(helper_value_check0_fail)); |
| 1994 | VG_(register_compact_helper)((Addr) & MC_(helper_value_check2_fail)); |
| 1995 | VG_(register_compact_helper)((Addr) & MC_(helperc_STOREV4)); |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1996 | VG_(register_compact_helper)((Addr) & MC_(helperc_LOADV4)); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1997 | |
njn | d04b7c6 | 2002-10-03 14:05:52 +0000 | [diff] [blame] | 1998 | /* These two made non-compact because 2-byte transactions are rare. */ |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 1999 | VG_(register_noncompact_helper)((Addr) & MC_(helperc_STOREV2)); |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 2000 | VG_(register_noncompact_helper)((Addr) & MC_(helperc_STOREV1)); |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 2001 | VG_(register_noncompact_helper)((Addr) & MC_(helperc_LOADV2)); |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 2002 | VG_(register_noncompact_helper)((Addr) & MC_(helperc_LOADV1)); |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 2003 | VG_(register_noncompact_helper)((Addr) & MC_(fpu_write_check)); |
| 2004 | VG_(register_noncompact_helper)((Addr) & MC_(fpu_read_check)); |
| 2005 | VG_(register_noncompact_helper)((Addr) & MC_(helper_value_check1_fail)); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2006 | |
| 2007 | VGP_(register_profile_event) ( VgpSetMem, "set-mem-perms" ); |
| 2008 | VGP_(register_profile_event) ( VgpCheckMem, "check-mem-perms" ); |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 2009 | VGP_(register_profile_event) ( VgpESPAdj, "adjust-ESP" ); |
njn | d04b7c6 | 2002-10-03 14:05:52 +0000 | [diff] [blame] | 2010 | |
njn | 43c799e | 2003-04-08 00:08:52 +0000 | [diff] [blame] | 2011 | /* Additional block description for VG_(describe_addr)() */ |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 2012 | MAC_(describe_addr_supp) = client_perm_maybe_describe; |
njn | 43c799e | 2003-04-08 00:08:52 +0000 | [diff] [blame] | 2013 | |
njn | d04b7c6 | 2002-10-03 14:05:52 +0000 | [diff] [blame] | 2014 | init_shadow_memory(); |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 2015 | MAC_(common_pre_clo_init)(); |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 2016 | } |
| 2017 | |
| 2018 | void SK_(post_clo_init) ( void ) |
| 2019 | { |
| 2020 | } |
| 2021 | |
njn | 7d9f94d | 2003-04-22 21:41:40 +0000 | [diff] [blame] | 2022 | void SK_(fini) ( Int exitcode ) |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 2023 | { |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 2024 | MAC_(common_fini)( mc_detect_memory_leaks ); |
njn | 3e88418 | 2003-04-15 13:03:23 +0000 | [diff] [blame] | 2025 | |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 2026 | if (0) { |
| 2027 | VG_(message)(Vg_DebugMsg, |
| 2028 | "------ Valgrind's client block stats follow ---------------" ); |
nethercote | 8b76fe5 | 2004-11-08 19:20:09 +0000 | [diff] [blame] | 2029 | show_client_block_stats(); |
njn | 5c004e4 | 2002-11-18 11:04:50 +0000 | [diff] [blame] | 2030 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2031 | } |
| 2032 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2033 | VG_DETERMINE_INTERFACE_VERSION(SK_(pre_clo_init), 9./8) |
| 2034 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2035 | /*--------------------------------------------------------------------*/ |
njn25 | cac76cb | 2002-09-23 11:21:57 +0000 | [diff] [blame] | 2036 | /*--- end mc_main.c ---*/ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2037 | /*--------------------------------------------------------------------*/ |