sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
| 3 | /*--- ---*/ |
| 4 | /*--- This file (host-amd64/hdefs.h) is ---*/ |
| 5 | /*--- Copyright (c) 2005 OpenWorks LLP. All rights reserved. ---*/ |
| 6 | /*--- ---*/ |
| 7 | /*---------------------------------------------------------------*/ |
| 8 | |
| 9 | /* |
| 10 | This file is part of LibVEX, a library for dynamic binary |
| 11 | instrumentation and translation. |
| 12 | |
| 13 | Copyright (C) 2004-2005 OpenWorks, LLP. |
| 14 | |
| 15 | This program is free software; you can redistribute it and/or modify |
| 16 | it under the terms of the GNU General Public License as published by |
| 17 | the Free Software Foundation; Version 2 dated June 1991 of the |
| 18 | license. |
| 19 | |
| 20 | This program is distributed in the hope that it will be useful, |
| 21 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, or liability |
| 23 | for damages. See the GNU General Public License for more details. |
| 24 | |
| 25 | Neither the names of the U.S. Department of Energy nor the |
| 26 | University of California nor the names of its contributors may be |
| 27 | used to endorse or promote products derived from this software |
| 28 | without prior written permission. |
| 29 | |
| 30 | You should have received a copy of the GNU General Public License |
| 31 | along with this program; if not, write to the Free Software |
| 32 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 |
| 33 | USA. |
| 34 | */ |
| 35 | |
| 36 | #ifndef __LIBVEX_HOST_AMD64_HDEFS_H |
| 37 | #define __LIBVEX_HOST_AMD64_HDEFS_H |
| 38 | |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 39 | |
| 40 | /* --------- Registers. --------- */ |
| 41 | |
| 42 | /* The usual HReg abstraction. There are 16 real int regs, 6 real |
| 43 | float regs, and 16 real vector regs. |
| 44 | */ |
| 45 | |
| 46 | extern void ppHRegAMD64 ( HReg ); |
| 47 | |
| 48 | extern HReg hregAMD64_RAX ( void ); |
| 49 | extern HReg hregAMD64_RBX ( void ); |
| 50 | extern HReg hregAMD64_RCX ( void ); |
| 51 | extern HReg hregAMD64_RDX ( void ); |
| 52 | extern HReg hregAMD64_RSP ( void ); |
| 53 | extern HReg hregAMD64_RBP ( void ); |
| 54 | extern HReg hregAMD64_RSI ( void ); |
| 55 | extern HReg hregAMD64_RDI ( void ); |
| 56 | extern HReg hregAMD64_R8 ( void ); |
| 57 | extern HReg hregAMD64_R9 ( void ); |
| 58 | extern HReg hregAMD64_R10 ( void ); |
| 59 | extern HReg hregAMD64_R11 ( void ); |
| 60 | extern HReg hregAMD64_R12 ( void ); |
| 61 | extern HReg hregAMD64_R13 ( void ); |
| 62 | extern HReg hregAMD64_R14 ( void ); |
| 63 | extern HReg hregAMD64_R15 ( void ); |
| 64 | |
| 65 | extern HReg hregAMD64_FAKE0 ( void ); |
| 66 | extern HReg hregAMD64_FAKE1 ( void ); |
| 67 | extern HReg hregAMD64_FAKE2 ( void ); |
| 68 | extern HReg hregAMD64_FAKE3 ( void ); |
| 69 | extern HReg hregAMD64_FAKE4 ( void ); |
| 70 | extern HReg hregAMD64_FAKE5 ( void ); |
| 71 | |
| 72 | extern HReg hregAMD64_XMM0 ( void ); |
| 73 | extern HReg hregAMD64_XMM1 ( void ); |
sewardj | 53df061 | 2005-02-04 21:15:39 +0000 | [diff] [blame] | 74 | extern HReg hregAMD64_XMM2 ( void ); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 75 | extern HReg hregAMD64_XMM3 ( void ); |
| 76 | extern HReg hregAMD64_XMM4 ( void ); |
| 77 | extern HReg hregAMD64_XMM5 ( void ); |
| 78 | extern HReg hregAMD64_XMM6 ( void ); |
| 79 | extern HReg hregAMD64_XMM7 ( void ); |
| 80 | extern HReg hregAMD64_XMM8 ( void ); |
| 81 | extern HReg hregAMD64_XMM9 ( void ); |
| 82 | extern HReg hregAMD64_XMM10 ( void ); |
| 83 | extern HReg hregAMD64_XMM11 ( void ); |
| 84 | extern HReg hregAMD64_XMM12 ( void ); |
| 85 | extern HReg hregAMD64_XMM13 ( void ); |
| 86 | extern HReg hregAMD64_XMM14 ( void ); |
| 87 | extern HReg hregAMD64_XMM15 ( void ); |
| 88 | |
| 89 | |
| 90 | /* --------- Condition codes, AMD encoding. --------- */ |
| 91 | |
| 92 | typedef |
| 93 | enum { |
| 94 | Acc_O = 0, /* overflow */ |
| 95 | Acc_NO = 1, /* no overflow */ |
| 96 | |
| 97 | Acc_B = 2, /* below */ |
| 98 | Acc_NB = 3, /* not below */ |
| 99 | |
| 100 | Acc_Z = 4, /* zero */ |
| 101 | Acc_NZ = 5, /* not zero */ |
| 102 | |
| 103 | Acc_BE = 6, /* below or equal */ |
| 104 | Acc_NBE = 7, /* not below or equal */ |
| 105 | |
| 106 | Acc_S = 8, /* negative */ |
| 107 | Acc_NS = 9, /* not negative */ |
| 108 | |
| 109 | Acc_P = 10, /* parity even */ |
| 110 | Acc_NP = 11, /* not parity even */ |
| 111 | |
| 112 | Acc_L = 12, /* jump less */ |
| 113 | Acc_NL = 13, /* not less */ |
| 114 | |
| 115 | Acc_LE = 14, /* less or equal */ |
| 116 | Acc_NLE = 15, /* not less or equal */ |
| 117 | |
| 118 | Acc_ALWAYS = 16 /* the usual hack */ |
| 119 | } |
| 120 | AMD64CondCode; |
| 121 | |
| 122 | extern HChar* showAMD64CondCode ( AMD64CondCode ); |
| 123 | |
| 124 | |
| 125 | /* --------- Memory address expressions (amodes). --------- */ |
| 126 | |
| 127 | typedef |
| 128 | enum { |
| 129 | Aam_IR, /* Immediate + Reg */ |
| 130 | Aam_IRRS /* Immediate + Reg1 + (Reg2 << Shift) */ |
| 131 | } |
| 132 | AMD64AModeTag; |
| 133 | |
| 134 | typedef |
| 135 | struct { |
| 136 | AMD64AModeTag tag; |
| 137 | union { |
| 138 | struct { |
| 139 | UInt imm; |
| 140 | HReg reg; |
| 141 | } IR; |
| 142 | struct { |
| 143 | UInt imm; |
| 144 | HReg base; |
| 145 | HReg index; |
| 146 | Int shift; /* 0, 1, 2 or 3 only */ |
| 147 | } IRRS; |
| 148 | } Aam; |
| 149 | } |
| 150 | AMD64AMode; |
| 151 | |
| 152 | extern AMD64AMode* AMD64AMode_IR ( UInt, HReg ); |
| 153 | extern AMD64AMode* AMD64AMode_IRRS ( UInt, HReg, HReg, Int ); |
| 154 | |
| 155 | extern AMD64AMode* dopyAMD64AMode ( AMD64AMode* ); |
| 156 | |
| 157 | extern void ppAMD64AMode ( AMD64AMode* ); |
| 158 | |
| 159 | |
| 160 | /* --------- Operand, which can be reg, immediate or memory. --------- */ |
| 161 | |
| 162 | typedef |
| 163 | enum { |
| 164 | Armi_Imm, |
| 165 | Armi_Reg, |
| 166 | Armi_Mem |
| 167 | } |
| 168 | AMD64RMITag; |
| 169 | |
| 170 | typedef |
| 171 | struct { |
| 172 | AMD64RMITag tag; |
| 173 | union { |
| 174 | struct { |
| 175 | UInt imm32; |
| 176 | } Imm; |
| 177 | struct { |
| 178 | HReg reg; |
| 179 | } Reg; |
| 180 | struct { |
| 181 | AMD64AMode* am; |
| 182 | } Mem; |
| 183 | } |
| 184 | Armi; |
| 185 | } |
| 186 | AMD64RMI; |
| 187 | |
| 188 | extern AMD64RMI* AMD64RMI_Imm ( UInt ); |
| 189 | extern AMD64RMI* AMD64RMI_Reg ( HReg ); |
| 190 | extern AMD64RMI* AMD64RMI_Mem ( AMD64AMode* ); |
| 191 | |
| 192 | extern void ppAMD64RMI ( AMD64RMI* ); |
| 193 | |
| 194 | |
| 195 | /* --------- Operand, which can be reg or immediate only. --------- */ |
| 196 | |
| 197 | typedef |
| 198 | enum { |
| 199 | Ari_Imm, |
| 200 | Ari_Reg |
| 201 | } |
| 202 | AMD64RITag; |
| 203 | |
| 204 | typedef |
| 205 | struct { |
| 206 | AMD64RITag tag; |
| 207 | union { |
| 208 | struct { |
| 209 | UInt imm32; |
| 210 | } Imm; |
| 211 | struct { |
| 212 | HReg reg; |
| 213 | } Reg; |
| 214 | } |
| 215 | Ari; |
| 216 | } |
| 217 | AMD64RI; |
| 218 | |
| 219 | extern AMD64RI* AMD64RI_Imm ( UInt ); |
| 220 | extern AMD64RI* AMD64RI_Reg ( HReg ); |
| 221 | |
| 222 | extern void ppAMD64RI ( AMD64RI* ); |
| 223 | |
| 224 | |
| 225 | /* --------- Operand, which can be reg or memory only. --------- */ |
| 226 | |
| 227 | typedef |
| 228 | enum { |
| 229 | Arm_Reg, |
| 230 | Arm_Mem |
| 231 | } |
| 232 | AMD64RMTag; |
| 233 | |
| 234 | typedef |
| 235 | struct { |
| 236 | AMD64RMTag tag; |
| 237 | union { |
| 238 | struct { |
| 239 | HReg reg; |
| 240 | } Reg; |
| 241 | struct { |
| 242 | AMD64AMode* am; |
| 243 | } Mem; |
| 244 | } |
| 245 | Arm; |
| 246 | } |
| 247 | AMD64RM; |
| 248 | |
| 249 | extern AMD64RM* AMD64RM_Reg ( HReg ); |
| 250 | extern AMD64RM* AMD64RM_Mem ( AMD64AMode* ); |
| 251 | |
| 252 | extern void ppAMD64RM ( AMD64RM* ); |
| 253 | |
| 254 | |
sewardj | d0a12df | 2005-02-10 02:07:43 +0000 | [diff] [blame] | 255 | /* --------- Instructions. --------- */ |
| 256 | |
| 257 | /* --------- */ |
| 258 | typedef |
| 259 | enum { |
| 260 | Aun_NEG, |
| 261 | Aun_NOT |
| 262 | } |
| 263 | AMD64UnaryOp; |
| 264 | |
| 265 | extern HChar* showAMD64UnaryOp ( AMD64UnaryOp ); |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 266 | |
| 267 | |
| 268 | /* --------- */ |
| 269 | typedef |
| 270 | enum { |
| 271 | Aalu_INVALID, |
| 272 | Aalu_MOV, |
| 273 | Aalu_CMP, |
| 274 | Aalu_ADD, Aalu_SUB, Aalu_ADC, Aalu_SBB, |
| 275 | Aalu_AND, Aalu_OR, Aalu_XOR, |
| 276 | Aalu_MUL |
| 277 | } |
| 278 | AMD64AluOp; |
| 279 | |
| 280 | extern HChar* showAMD64AluOp ( AMD64AluOp ); |
| 281 | |
| 282 | |
sewardj | 8258a8c | 2005-02-02 03:11:24 +0000 | [diff] [blame] | 283 | /* --------- */ |
| 284 | typedef |
| 285 | enum { |
| 286 | Ash_INVALID, |
| 287 | Ash_SHL, Ash_SHR, Ash_SAR |
| 288 | } |
| 289 | AMD64ShiftOp; |
| 290 | |
| 291 | extern HChar* showAMD64ShiftOp ( AMD64ShiftOp ); |
| 292 | |
| 293 | |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 294 | //.. /* --------- */ |
| 295 | //.. typedef |
| 296 | //.. enum { |
| 297 | //.. Xfp_INVALID, |
| 298 | //.. /* Binary */ |
| 299 | //.. Xfp_ADD, Xfp_SUB, Xfp_MUL, Xfp_DIV, |
| 300 | //.. Xfp_SCALE, Xfp_ATAN, Xfp_YL2X, Xfp_YL2XP1, Xfp_PREM, Xfp_PREM1, |
| 301 | //.. /* Unary */ |
| 302 | //.. Xfp_SQRT, Xfp_ABS, Xfp_NEG, Xfp_MOV, Xfp_SIN, Xfp_COS, Xfp_TAN, |
| 303 | //.. Xfp_ROUND, Xfp_2XM1 |
| 304 | //.. } |
| 305 | //.. X86FpOp; |
| 306 | //.. |
| 307 | //.. extern HChar* showX86FpOp ( X86FpOp ); |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 308 | |
| 309 | |
| 310 | /* --------- */ |
| 311 | typedef |
| 312 | enum { |
| 313 | Asse_INVALID, |
| 314 | /* mov */ |
| 315 | Asse_MOV, |
| 316 | /* Floating point binary */ |
| 317 | Asse_ADDF, Asse_SUBF, Asse_MULF, Asse_DIVF, |
sewardj | 1a01e65 | 2005-02-23 11:39:21 +0000 | [diff] [blame] | 318 | Asse_MAXF, Asse_MINF, |
sewardj | 8d96531 | 2005-02-25 02:48:47 +0000 | [diff] [blame^] | 319 | Asse_CMPEQF, Asse_CMPLTF, Asse_CMPLEF, Asse_CMPUNF, |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 320 | /* Floating point unary */ |
| 321 | Asse_RCPF, Asse_RSQRTF, Asse_SQRTF, |
| 322 | /* Bitwise */ |
| 323 | Asse_AND, Asse_OR, Asse_XOR, Asse_ANDN, |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 324 | //.. /* Integer binary */ |
| 325 | //.. Xsse_ADD8, Xsse_ADD16, Xsse_ADD32, Xsse_ADD64, |
| 326 | //.. Xsse_QADD8U, Xsse_QADD16U, |
| 327 | //.. Xsse_QADD8S, Xsse_QADD16S, |
| 328 | //.. Xsse_SUB8, Xsse_SUB16, Xsse_SUB32, Xsse_SUB64, |
| 329 | //.. Xsse_QSUB8U, Xsse_QSUB16U, |
| 330 | //.. Xsse_QSUB8S, Xsse_QSUB16S, |
| 331 | //.. Xsse_MUL16, |
| 332 | //.. Xsse_MULHI16U, |
| 333 | //.. Xsse_MULHI16S, |
| 334 | //.. Xsse_AVG8U, Xsse_AVG16U, |
| 335 | //.. Xsse_MAX16S, |
| 336 | //.. Xsse_MAX8U, |
| 337 | //.. Xsse_MIN16S, |
| 338 | //.. Xsse_MIN8U, |
| 339 | //.. Xsse_CMPEQ8, Xsse_CMPEQ16, Xsse_CMPEQ32, |
| 340 | //.. Xsse_CMPGT8S, Xsse_CMPGT16S, Xsse_CMPGT32S, |
| 341 | //.. Xsse_SHL16, Xsse_SHL32, Xsse_SHL64, |
| 342 | //.. Xsse_SHR16, Xsse_SHR32, Xsse_SHR64, |
| 343 | //.. Xsse_SAR16, Xsse_SAR32, |
| 344 | //.. Xsse_PACKSSD, Xsse_PACKSSW, Xsse_PACKUSW, |
| 345 | //.. Xsse_UNPCKHB, Xsse_UNPCKHW, Xsse_UNPCKHD, Xsse_UNPCKHQ, |
| 346 | //.. Xsse_UNPCKLB, Xsse_UNPCKLW, Xsse_UNPCKLD, Xsse_UNPCKLQ |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 347 | } |
| 348 | AMD64SseOp; |
| 349 | |
| 350 | extern HChar* showAMD64SseOp ( AMD64SseOp ); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 351 | |
| 352 | |
| 353 | /* --------- */ |
| 354 | typedef |
| 355 | enum { |
sewardj | 53df061 | 2005-02-04 21:15:39 +0000 | [diff] [blame] | 356 | Ain_Imm64, /* Generate 64-bit literal to register */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 357 | Ain_Alu64R, /* 64-bit mov/arith/logical, dst=REG */ |
| 358 | Ain_Alu64M, /* 64-bit mov/arith/logical, dst=MEM */ |
sewardj | 8258a8c | 2005-02-02 03:11:24 +0000 | [diff] [blame] | 359 | Ain_Sh64, /* 64-bit shift/rotate, dst=REG or MEM */ |
sewardj | 05b3b6a | 2005-02-04 01:44:33 +0000 | [diff] [blame] | 360 | Ain_Test64, /* 64-bit test (AND, set flags, discard result) */ |
sewardj | d0a12df | 2005-02-10 02:07:43 +0000 | [diff] [blame] | 361 | Ain_Unary64, /* 64-bit not and neg */ |
sewardj | 9b96767 | 2005-02-08 11:13:09 +0000 | [diff] [blame] | 362 | Ain_MulL, /* widening multiply */ |
sewardj | 7de0d3c | 2005-02-13 02:26:41 +0000 | [diff] [blame] | 363 | Ain_Div, /* div and mod */ |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 364 | //.. Xin_Sh3232, /* shldl or shrdl */ |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 365 | Ain_Push, /* push 64-bit value on stack */ |
sewardj | 05b3b6a | 2005-02-04 01:44:33 +0000 | [diff] [blame] | 366 | Ain_Call, /* call to address in register */ |
sewardj | f67eadf | 2005-02-03 03:53:52 +0000 | [diff] [blame] | 367 | Ain_Goto, /* conditional/unconditional jmp to dst */ |
sewardj | 05b3b6a | 2005-02-04 01:44:33 +0000 | [diff] [blame] | 368 | Ain_CMov64, /* conditional move */ |
sewardj | f67eadf | 2005-02-03 03:53:52 +0000 | [diff] [blame] | 369 | Ain_MovZLQ, /* reg-reg move, zeroing out top half */ |
sewardj | 8258a8c | 2005-02-02 03:11:24 +0000 | [diff] [blame] | 370 | Ain_LoadEX, /* mov{s,z}{b,w,l}q from mem to reg */ |
sewardj | f67eadf | 2005-02-03 03:53:52 +0000 | [diff] [blame] | 371 | Ain_Store, /* store 32/16/8 bit value in memory */ |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 372 | //.. Xin_Set32, /* convert condition code to 32-bit value */ |
| 373 | //.. Xin_Bsfr32, /* 32-bit bsf/bsr */ |
sewardj | d0a12df | 2005-02-10 02:07:43 +0000 | [diff] [blame] | 374 | Ain_MFence, /* mem fence */ |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 375 | //.. |
| 376 | //.. Xin_FpUnary, /* FP fake unary op */ |
| 377 | //.. Xin_FpBinary, /* FP fake binary op */ |
| 378 | //.. Xin_FpLdSt, /* FP fake load/store */ |
| 379 | //.. Xin_FpLdStI, /* FP fake load/store, converting to/from Int */ |
| 380 | //.. Xin_Fp64to32, /* FP round IEEE754 double to IEEE754 single */ |
| 381 | //.. Xin_FpCMov, /* FP fake floating point conditional move */ |
sewardj | 1a01e65 | 2005-02-23 11:39:21 +0000 | [diff] [blame] | 382 | Ain_LdMXCSR, /* load %mxcsr */ |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 383 | //.. Xin_FpStSW_AX, /* fstsw %ax */ |
sewardj | 1830386 | 2005-02-21 12:36:54 +0000 | [diff] [blame] | 384 | Ain_SseUComIS, /* ucomisd/ucomiss, then get %rflags into int |
| 385 | register */ |
sewardj | 1a01e65 | 2005-02-23 11:39:21 +0000 | [diff] [blame] | 386 | Ain_SseSI2SF, /* scalar 32/64 int to 32/64 float conversion */ |
| 387 | Ain_SseSF2SI, /* scalar 32/64 float to 32/64 int conversion */ |
sewardj | 8d96531 | 2005-02-25 02:48:47 +0000 | [diff] [blame^] | 388 | Ain_SseSDSS, /* scalar float32 to/from float64 */ |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 389 | //.. |
| 390 | //.. Xin_SseConst, /* Generate restricted SSE literal */ |
sewardj | 1830386 | 2005-02-21 12:36:54 +0000 | [diff] [blame] | 391 | Ain_SseLdSt, /* SSE load/store 32/64/128 bits, no alignment |
| 392 | constraints, upper 96/64/0 bits arbitrary */ |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 393 | Ain_SseLdzLO, /* SSE load low 32/64 bits, zero remainder of reg */ |
sewardj | 8d96531 | 2005-02-25 02:48:47 +0000 | [diff] [blame^] | 394 | Ain_Sse32Fx4, /* SSE binary, 32Fx4 */ |
| 395 | Ain_Sse32FLo, /* SSE binary, 32F in lowest lane only */ |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 396 | //.. Xin_Sse64Fx2, /* SSE binary, 64Fx2 */ |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 397 | Ain_Sse64FLo, /* SSE binary, 64F in lowest lane only */ |
| 398 | Ain_SseReRg, /* SSE binary general reg-reg, Re, Rg */ |
sewardj | 8d96531 | 2005-02-25 02:48:47 +0000 | [diff] [blame^] | 399 | Ain_SseCMov, /* SSE conditional move */ |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 400 | //.. Xin_SseShuf /* SSE2 shuffle (pshufd) */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 401 | } |
| 402 | AMD64InstrTag; |
| 403 | |
| 404 | /* Destinations are on the RIGHT (second operand) */ |
| 405 | |
| 406 | typedef |
| 407 | struct { |
| 408 | AMD64InstrTag tag; |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 409 | union { |
| 410 | struct { |
sewardj | 53df061 | 2005-02-04 21:15:39 +0000 | [diff] [blame] | 411 | ULong imm64; |
| 412 | HReg dst; |
| 413 | } Imm64; |
| 414 | struct { |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 415 | AMD64AluOp op; |
| 416 | AMD64RMI* src; |
| 417 | HReg dst; |
| 418 | } Alu64R; |
| 419 | struct { |
| 420 | AMD64AluOp op; |
| 421 | AMD64RI* src; |
| 422 | AMD64AMode* dst; |
| 423 | } Alu64M; |
sewardj | 8258a8c | 2005-02-02 03:11:24 +0000 | [diff] [blame] | 424 | struct { |
| 425 | AMD64ShiftOp op; |
| 426 | UInt src; /* shift amount, or 0 means %cl */ |
| 427 | AMD64RM* dst; |
| 428 | } Sh64; |
sewardj | 05b3b6a | 2005-02-04 01:44:33 +0000 | [diff] [blame] | 429 | struct { |
| 430 | AMD64RI* src; |
| 431 | AMD64RM* dst; |
| 432 | } Test64; |
sewardj | d0a12df | 2005-02-10 02:07:43 +0000 | [diff] [blame] | 433 | /* Not and Neg */ |
| 434 | struct { |
| 435 | AMD64UnaryOp op; |
| 436 | AMD64RM* dst; |
| 437 | } Unary64; |
sewardj | 9b96767 | 2005-02-08 11:13:09 +0000 | [diff] [blame] | 438 | /* DX:AX = AX *s/u r/m16, or EDX:EAX = EAX *s/u r/m32, |
| 439 | or RDX:RAX = RAX *s/u r/m64 */ |
| 440 | struct { |
| 441 | Bool syned; |
| 442 | Int sz; /* 2, 4 or 8 only */ |
| 443 | AMD64RM* src; |
| 444 | } MulL; |
sewardj | 7de0d3c | 2005-02-13 02:26:41 +0000 | [diff] [blame] | 445 | /* amd64 div/idiv instruction. Modifies RDX and RAX and |
| 446 | reads src. */ |
| 447 | struct { |
| 448 | Bool syned; |
| 449 | Int sz; /* 4 or 8 only */ |
| 450 | AMD64RM* src; |
| 451 | } Div; |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 452 | //.. /* shld/shrd. op may only be Xsh_SHL or Xsh_SHR */ |
| 453 | //.. struct { |
| 454 | //.. X86ShiftOp op; |
| 455 | //.. UInt amt; /* shift amount, or 0 means %cl */ |
| 456 | //.. HReg src; |
| 457 | //.. HReg dst; |
| 458 | //.. } Sh3232; |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 459 | struct { |
| 460 | AMD64RMI* src; |
| 461 | } Push; |
sewardj | 05b3b6a | 2005-02-04 01:44:33 +0000 | [diff] [blame] | 462 | /* Pseudo-insn. Call target (an absolute address), on given |
| 463 | condition (which could be Xcc_ALWAYS). */ |
| 464 | struct { |
| 465 | AMD64CondCode cond; |
| 466 | Addr64 target; |
| 467 | Int regparms; /* 0 .. 6 */ |
| 468 | } Call; |
sewardj | f67eadf | 2005-02-03 03:53:52 +0000 | [diff] [blame] | 469 | /* Pseudo-insn. Goto dst, on given condition (which could be |
| 470 | Acc_ALWAYS). */ |
| 471 | struct { |
| 472 | IRJumpKind jk; |
| 473 | AMD64CondCode cond; |
| 474 | AMD64RI* dst; |
| 475 | } Goto; |
sewardj | 05b3b6a | 2005-02-04 01:44:33 +0000 | [diff] [blame] | 476 | /* Mov src to dst on the given condition, which may not |
| 477 | be the bogus Acc_ALWAYS. */ |
| 478 | struct { |
| 479 | AMD64CondCode cond; |
| 480 | AMD64RM* src; |
| 481 | HReg dst; |
| 482 | } CMov64; |
sewardj | f67eadf | 2005-02-03 03:53:52 +0000 | [diff] [blame] | 483 | /* reg-reg move, zeroing out top half */ |
| 484 | struct { |
| 485 | HReg src; |
| 486 | HReg dst; |
| 487 | } MovZLQ; |
sewardj | 8258a8c | 2005-02-02 03:11:24 +0000 | [diff] [blame] | 488 | /* Sign/Zero extending loads. Dst size is always 64 bits. */ |
| 489 | struct { |
sewardj | 1830386 | 2005-02-21 12:36:54 +0000 | [diff] [blame] | 490 | UChar szSmall; /* only 1, 2 or 4 */ |
sewardj | 8258a8c | 2005-02-02 03:11:24 +0000 | [diff] [blame] | 491 | Bool syned; |
| 492 | AMD64AMode* src; |
| 493 | HReg dst; |
| 494 | } LoadEX; |
sewardj | f67eadf | 2005-02-03 03:53:52 +0000 | [diff] [blame] | 495 | /* 32/16/8 bit stores. */ |
| 496 | struct { |
| 497 | UChar sz; /* only 1, 2 or 4 */ |
| 498 | HReg src; |
| 499 | AMD64AMode* dst; |
| 500 | } Store; |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 501 | //.. /* Convert a x86 condition code to a 32-bit value (0 or 1). */ |
| 502 | //.. struct { |
| 503 | //.. X86CondCode cond; |
| 504 | //.. HReg dst; |
| 505 | //.. } Set32; |
| 506 | //.. /* 32-bit bsf or bsr. */ |
| 507 | //.. struct { |
| 508 | //.. Bool isFwds; |
| 509 | //.. HReg src; |
| 510 | //.. HReg dst; |
| 511 | //.. } Bsfr32; |
sewardj | d0a12df | 2005-02-10 02:07:43 +0000 | [diff] [blame] | 512 | /* Mem fence. In short, an insn which flushes all preceding |
| 513 | loads and stores as much as possible before continuing. |
| 514 | On AMD64 we emit a real "mfence". */ |
| 515 | struct { |
| 516 | } MFence; |
| 517 | |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 518 | //.. /* X86 Floating point (fake 3-operand, "flat reg file" insns) */ |
| 519 | //.. struct { |
| 520 | //.. X86FpOp op; |
| 521 | //.. HReg src; |
| 522 | //.. HReg dst; |
| 523 | //.. } FpUnary; |
| 524 | //.. struct { |
| 525 | //.. X86FpOp op; |
| 526 | //.. HReg srcL; |
| 527 | //.. HReg srcR; |
| 528 | //.. HReg dst; |
| 529 | //.. } FpBinary; |
| 530 | //.. struct { |
| 531 | //.. Bool isLoad; |
| 532 | //.. UChar sz; /* only 4 (IEEE single) or 8 (IEEE double) */ |
| 533 | //.. HReg reg; |
| 534 | //.. X86AMode* addr; |
| 535 | //.. } FpLdSt; |
| 536 | //.. /* Move 64-bit float to/from memory, converting to/from |
| 537 | //.. signed int on the way. Note the conversions will observe |
| 538 | //.. the host FPU rounding mode currently in force. */ |
| 539 | //.. struct { |
| 540 | //.. Bool isLoad; |
| 541 | //.. UChar sz; /* only 2, 4 or 8 */ |
| 542 | //.. HReg reg; |
| 543 | //.. X86AMode* addr; |
| 544 | //.. } FpLdStI; |
| 545 | //.. /* By observing the current FPU rounding mode, round (etc) |
| 546 | //.. src into dst given that dst should be interpreted as an |
| 547 | //.. IEEE754 32-bit (float) type. */ |
| 548 | //.. struct { |
| 549 | //.. HReg src; |
| 550 | //.. HReg dst; |
| 551 | //.. } Fp64to32; |
| 552 | //.. /* Mov src to dst on the given condition, which may not |
| 553 | //.. be the bogus Xcc_ALWAYS. */ |
| 554 | //.. struct { |
| 555 | //.. X86CondCode cond; |
| 556 | //.. HReg src; |
| 557 | //.. HReg dst; |
| 558 | //.. } FpCMov; |
sewardj | 1a01e65 | 2005-02-23 11:39:21 +0000 | [diff] [blame] | 559 | /* Load 32 bits into %mxcsr. */ |
| 560 | struct { |
| 561 | AMD64AMode* addr; |
| 562 | } |
| 563 | LdMXCSR; |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 564 | //.. /* fstsw %ax */ |
| 565 | //.. struct { |
| 566 | //.. /* no fields */ |
| 567 | //.. } |
| 568 | //.. FpStSW_AX; |
sewardj | 1830386 | 2005-02-21 12:36:54 +0000 | [diff] [blame] | 569 | /* ucomisd/ucomiss, then get %rflags into int register */ |
| 570 | struct { |
| 571 | UChar sz; /* 4 or 8 only */ |
| 572 | HReg srcL; /* xmm */ |
| 573 | HReg srcR; /* xmm */ |
| 574 | HReg dst; /* int */ |
| 575 | } SseUComIS; |
sewardj | 1a01e65 | 2005-02-23 11:39:21 +0000 | [diff] [blame] | 576 | /* scalar 32/64 int to 32/64 float conversion */ |
| 577 | struct { |
| 578 | UChar szS; /* 4 or 8 */ |
| 579 | UChar szD; /* 4 or 8 */ |
| 580 | HReg src; /* i class */ |
| 581 | HReg dst; /* v class */ |
| 582 | } SseSI2SF; |
| 583 | /* scalar 32/64 float to 32/64 int conversion */ |
| 584 | struct { |
| 585 | UChar szS; /* 4 or 8 */ |
| 586 | UChar szD; /* 4 or 8 */ |
| 587 | HReg src; /* v class */ |
| 588 | HReg dst; /* i class */ |
| 589 | } SseSF2SI; |
sewardj | 8d96531 | 2005-02-25 02:48:47 +0000 | [diff] [blame^] | 590 | /* scalar float32 to/from float64 */ |
| 591 | struct { |
| 592 | Bool from64; /* True: 64->32; False: 32->64 */ |
| 593 | HReg src; |
| 594 | HReg dst; |
| 595 | } SseSDSS; |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 596 | //.. |
| 597 | //.. /* Simplistic SSE[123] */ |
| 598 | //.. struct { |
| 599 | //.. UShort con; |
| 600 | //.. HReg dst; |
| 601 | //.. } SseConst; |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 602 | struct { |
| 603 | Bool isLoad; |
sewardj | 1830386 | 2005-02-21 12:36:54 +0000 | [diff] [blame] | 604 | UChar sz; /* 4, 8 or 16 only */ |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 605 | HReg reg; |
| 606 | AMD64AMode* addr; |
| 607 | } SseLdSt; |
| 608 | struct { |
| 609 | Int sz; /* 4 or 8 only */ |
| 610 | HReg reg; |
| 611 | AMD64AMode* addr; |
| 612 | } SseLdzLO; |
sewardj | 8d96531 | 2005-02-25 02:48:47 +0000 | [diff] [blame^] | 613 | struct { |
| 614 | AMD64SseOp op; |
| 615 | HReg src; |
| 616 | HReg dst; |
| 617 | } Sse32Fx4; |
| 618 | struct { |
| 619 | AMD64SseOp op; |
| 620 | HReg src; |
| 621 | HReg dst; |
| 622 | } Sse32FLo; |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 623 | //.. struct { |
| 624 | //.. X86SseOp op; |
| 625 | //.. HReg src; |
| 626 | //.. HReg dst; |
| 627 | //.. } Sse64Fx2; |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 628 | struct { |
| 629 | AMD64SseOp op; |
| 630 | HReg src; |
| 631 | HReg dst; |
| 632 | } Sse64FLo; |
| 633 | struct { |
| 634 | AMD64SseOp op; |
| 635 | HReg src; |
| 636 | HReg dst; |
| 637 | } SseReRg; |
sewardj | 8d96531 | 2005-02-25 02:48:47 +0000 | [diff] [blame^] | 638 | /* Mov src to dst on the given condition, which may not |
| 639 | be the bogus Xcc_ALWAYS. */ |
| 640 | struct { |
| 641 | AMD64CondCode cond; |
| 642 | HReg src; |
| 643 | HReg dst; |
| 644 | } SseCMov; |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 645 | //.. struct { |
| 646 | //.. Int order; /* 0 <= order <= 0xFF */ |
| 647 | //.. HReg src; |
| 648 | //.. HReg dst; |
| 649 | //.. } SseShuf; |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 650 | |
| 651 | } Ain; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 652 | } |
| 653 | AMD64Instr; |
| 654 | |
sewardj | 53df061 | 2005-02-04 21:15:39 +0000 | [diff] [blame] | 655 | extern AMD64Instr* AMD64Instr_Imm64 ( ULong imm64, HReg dst ); |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 656 | extern AMD64Instr* AMD64Instr_Alu64R ( AMD64AluOp, AMD64RMI*, HReg ); |
sewardj | f67eadf | 2005-02-03 03:53:52 +0000 | [diff] [blame] | 657 | extern AMD64Instr* AMD64Instr_Alu64M ( AMD64AluOp, AMD64RI*, AMD64AMode* ); |
sewardj | d0a12df | 2005-02-10 02:07:43 +0000 | [diff] [blame] | 658 | extern AMD64Instr* AMD64Instr_Unary64 ( AMD64UnaryOp op, AMD64RM* dst ); |
sewardj | 8258a8c | 2005-02-02 03:11:24 +0000 | [diff] [blame] | 659 | extern AMD64Instr* AMD64Instr_Sh64 ( AMD64ShiftOp, UInt, AMD64RM* ); |
sewardj | 05b3b6a | 2005-02-04 01:44:33 +0000 | [diff] [blame] | 660 | extern AMD64Instr* AMD64Instr_Test64 ( AMD64RI* src, AMD64RM* dst ); |
sewardj | 9b96767 | 2005-02-08 11:13:09 +0000 | [diff] [blame] | 661 | extern AMD64Instr* AMD64Instr_MulL ( Bool syned, Int sz, AMD64RM* ); |
sewardj | 7de0d3c | 2005-02-13 02:26:41 +0000 | [diff] [blame] | 662 | extern AMD64Instr* AMD64Instr_Div ( Bool syned, Int sz, AMD64RM* ); |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 663 | //.. extern AMD64Instr* AMD64Instr_Sh3232 ( AMD64ShiftOp, UInt amt, HReg src, HReg dst ); |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 664 | extern AMD64Instr* AMD64Instr_Push ( AMD64RMI* ); |
sewardj | 05b3b6a | 2005-02-04 01:44:33 +0000 | [diff] [blame] | 665 | extern AMD64Instr* AMD64Instr_Call ( AMD64CondCode, Addr64, Int ); |
sewardj | f67eadf | 2005-02-03 03:53:52 +0000 | [diff] [blame] | 666 | extern AMD64Instr* AMD64Instr_Goto ( IRJumpKind, AMD64CondCode cond, AMD64RI* dst ); |
sewardj | 05b3b6a | 2005-02-04 01:44:33 +0000 | [diff] [blame] | 667 | extern AMD64Instr* AMD64Instr_CMov64 ( AMD64CondCode, AMD64RM* src, HReg dst ); |
sewardj | f67eadf | 2005-02-03 03:53:52 +0000 | [diff] [blame] | 668 | extern AMD64Instr* AMD64Instr_MovZLQ ( HReg src, HReg dst ); |
sewardj | 8258a8c | 2005-02-02 03:11:24 +0000 | [diff] [blame] | 669 | extern AMD64Instr* AMD64Instr_LoadEX ( UChar szSmall, Bool syned, |
| 670 | AMD64AMode* src, HReg dst ); |
sewardj | f67eadf | 2005-02-03 03:53:52 +0000 | [diff] [blame] | 671 | extern AMD64Instr* AMD64Instr_Store ( UChar sz, HReg src, AMD64AMode* dst ); |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 672 | //.. extern AMD64Instr* AMD64Instr_Set32 ( AMD64CondCode cond, HReg dst ); |
| 673 | //.. extern AMD64Instr* AMD64Instr_Bsfr32 ( Bool isFwds, HReg src, HReg dst ); |
sewardj | d0a12df | 2005-02-10 02:07:43 +0000 | [diff] [blame] | 674 | extern AMD64Instr* AMD64Instr_MFence ( void ); |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 675 | //.. |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 676 | //.. extern AMD64Instr* AMD64Instr_FpUnary ( AMD64FpOp op, HReg src, HReg dst ); |
| 677 | //.. extern AMD64Instr* AMD64Instr_FpBinary ( AMD64FpOp op, HReg srcL, HReg srcR, HReg dst ); |
| 678 | //.. extern AMD64Instr* AMD64Instr_FpLdSt ( Bool isLoad, UChar sz, HReg reg, AMD64AMode* ); |
| 679 | //.. extern AMD64Instr* AMD64Instr_FpLdStI ( Bool isLoad, UChar sz, HReg reg, AMD64AMode* ); |
| 680 | //.. extern AMD64Instr* AMD64Instr_Fp64to32 ( HReg src, HReg dst ); |
| 681 | //.. extern AMD64Instr* AMD64Instr_FpCMov ( AMD64CondCode, HReg src, HReg dst ); |
sewardj | 1a01e65 | 2005-02-23 11:39:21 +0000 | [diff] [blame] | 682 | extern AMD64Instr* AMD64Instr_LdMXCSR ( AMD64AMode* ); |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 683 | //.. extern AMD64Instr* AMD64Instr_FpStSW_AX ( void ); |
sewardj | 1830386 | 2005-02-21 12:36:54 +0000 | [diff] [blame] | 684 | extern AMD64Instr* AMD64Instr_SseUComIS ( Int sz, HReg srcL, HReg srcR, HReg dst ); |
sewardj | 1a01e65 | 2005-02-23 11:39:21 +0000 | [diff] [blame] | 685 | extern AMD64Instr* AMD64Instr_SseSI2SF ( Int szS, Int szD, HReg src, HReg dst ); |
| 686 | extern AMD64Instr* AMD64Instr_SseSF2SI ( Int szS, Int szD, HReg src, HReg dst ); |
sewardj | 8d96531 | 2005-02-25 02:48:47 +0000 | [diff] [blame^] | 687 | extern AMD64Instr* AMD64Instr_SseSDSS ( Bool from64, HReg src, HReg dst ); |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 688 | //.. |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 689 | //.. extern AMD64Instr* AMD64Instr_SseConst ( UShort con, HReg dst ); |
sewardj | 1830386 | 2005-02-21 12:36:54 +0000 | [diff] [blame] | 690 | extern AMD64Instr* AMD64Instr_SseLdSt ( Bool isLoad, Int sz, HReg, AMD64AMode* ); |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 691 | extern AMD64Instr* AMD64Instr_SseLdzLO ( Int sz, HReg, AMD64AMode* ); |
sewardj | 8d96531 | 2005-02-25 02:48:47 +0000 | [diff] [blame^] | 692 | extern AMD64Instr* AMD64Instr_Sse32Fx4 ( AMD64SseOp, HReg, HReg ); |
| 693 | extern AMD64Instr* AMD64Instr_Sse32FLo ( AMD64SseOp, HReg, HReg ); |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 694 | //.. extern AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp, HReg, HReg ); |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 695 | extern AMD64Instr* AMD64Instr_Sse64FLo ( AMD64SseOp, HReg, HReg ); |
| 696 | extern AMD64Instr* AMD64Instr_SseReRg ( AMD64SseOp, HReg, HReg ); |
sewardj | 8d96531 | 2005-02-25 02:48:47 +0000 | [diff] [blame^] | 697 | extern AMD64Instr* AMD64Instr_SseCMov ( AMD64CondCode, HReg src, HReg dst ); |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 698 | //.. extern AMD64Instr* AMD64Instr_SseShuf ( Int order, HReg src, HReg dst ); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 699 | |
| 700 | |
| 701 | extern void ppAMD64Instr ( AMD64Instr* ); |
| 702 | |
| 703 | /* Some functions that insulate the register allocator from details |
| 704 | of the underlying instruction set. */ |
| 705 | extern void getRegUsage_AMD64Instr ( HRegUsage*, AMD64Instr* ); |
| 706 | extern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr* ); |
| 707 | extern Bool isMove_AMD64Instr ( AMD64Instr*, HReg*, HReg* ); |
| 708 | extern Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* ); |
| 709 | extern AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offset ); |
| 710 | extern AMD64Instr* genReload_AMD64 ( HReg rreg, Int offset ); |
| 711 | extern void getAllocableRegs_AMD64 ( Int*, HReg** ); |
| 712 | extern HInstrArray* iselBB_AMD64 ( IRBB*, VexSubArch ); |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 713 | |
| 714 | #endif /* ndef __LIBVEX_HOST_AMD64_HDEFS_H */ |
| 715 | |
| 716 | /*---------------------------------------------------------------*/ |
| 717 | /*--- end host-amd64/hdefs.h ---*/ |
| 718 | /*---------------------------------------------------------------*/ |