cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 3 | /*--- begin host_ppc_defs.h ---*/ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 4 | /*---------------------------------------------------------------*/ |
| 5 | |
| 6 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 9 | |
sewardj | 785952d | 2015-08-21 11:29:16 +0000 | [diff] [blame] | 10 | Copyright (C) 2004-2015 OpenWorks LLP |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 11 | info@open-works.net |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 12 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 17 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 26 | 02110-1301, USA. |
| 27 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 28 | The GNU General Public License is contained in the file COPYING. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 29 | |
| 30 | Neither the names of the U.S. Department of Energy nor the |
| 31 | University of California nor the names of its contributors may be |
| 32 | used to endorse or promote products derived from this software |
| 33 | without prior written permission. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 34 | */ |
| 35 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 36 | #ifndef __VEX_HOST_PPC_DEFS_H |
| 37 | #define __VEX_HOST_PPC_DEFS_H |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 38 | |
florian | 58a637b | 2012-09-30 20:30:17 +0000 | [diff] [blame] | 39 | #include "libvex_basictypes.h" |
| 40 | #include "libvex.h" // VexArch |
| 41 | #include "host_generic_regs.h" // HReg |
| 42 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 43 | |
| 44 | /* --------- Registers. --------- */ |
| 45 | |
sewardj | a5b5022 | 2015-03-26 07:18:32 +0000 | [diff] [blame] | 46 | #define ST_IN static inline |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 47 | |
sewardj | a5b5022 | 2015-03-26 07:18:32 +0000 | [diff] [blame] | 48 | #define GPR(_mode64, _enc, _ix64, _ix32) \ |
| 49 | mkHReg(False, (_mode64) ? HRcInt64 : HRcInt32, \ |
| 50 | (_enc), (_mode64) ? (_ix64) : (_ix32)) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 51 | |
sewardj | a5b5022 | 2015-03-26 07:18:32 +0000 | [diff] [blame] | 52 | #define FPR(_mode64, _enc, _ix64, _ix32) \ |
| 53 | mkHReg(False, HRcFlt64, \ |
| 54 | (_enc), (_mode64) ? (_ix64) : (_ix32)) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 55 | |
sewardj | a5b5022 | 2015-03-26 07:18:32 +0000 | [diff] [blame] | 56 | #define VR(_mode64, _enc, _ix64, _ix32) \ |
| 57 | mkHReg(False, HRcVec128, \ |
| 58 | (_enc), (_mode64) ? (_ix64) : (_ix32)) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 59 | |
sewardj | a5b5022 | 2015-03-26 07:18:32 +0000 | [diff] [blame] | 60 | ST_IN HReg hregPPC_GPR3 ( Bool mode64 ) { return GPR(mode64, 3, 0, 0); } |
| 61 | ST_IN HReg hregPPC_GPR4 ( Bool mode64 ) { return GPR(mode64, 4, 1, 1); } |
| 62 | ST_IN HReg hregPPC_GPR5 ( Bool mode64 ) { return GPR(mode64, 5, 2, 2); } |
| 63 | ST_IN HReg hregPPC_GPR6 ( Bool mode64 ) { return GPR(mode64, 6, 3, 3); } |
| 64 | ST_IN HReg hregPPC_GPR7 ( Bool mode64 ) { return GPR(mode64, 7, 4, 4); } |
| 65 | ST_IN HReg hregPPC_GPR8 ( Bool mode64 ) { return GPR(mode64, 8, 5, 5); } |
| 66 | ST_IN HReg hregPPC_GPR9 ( Bool mode64 ) { return GPR(mode64, 9, 6, 6); } |
| 67 | ST_IN HReg hregPPC_GPR10 ( Bool mode64 ) { return GPR(mode64, 10, 7, 7); } |
| 68 | |
| 69 | // r11 and r12 are only allocatable in 32-bit mode. Hence the 64-bit |
| 70 | // index numbering doesn't advance for these two. |
| 71 | ST_IN HReg hregPPC_GPR11 ( Bool mode64 ) { return GPR(mode64, 11, 0, 8); } |
| 72 | ST_IN HReg hregPPC_GPR12 ( Bool mode64 ) { return GPR(mode64, 12, 0, 9); } |
| 73 | |
| 74 | ST_IN HReg hregPPC_GPR14 ( Bool mode64 ) { return GPR(mode64, 14, 8, 10); } |
| 75 | ST_IN HReg hregPPC_GPR15 ( Bool mode64 ) { return GPR(mode64, 15, 9, 11); } |
| 76 | ST_IN HReg hregPPC_GPR16 ( Bool mode64 ) { return GPR(mode64, 16, 10, 12); } |
| 77 | ST_IN HReg hregPPC_GPR17 ( Bool mode64 ) { return GPR(mode64, 17, 11, 13); } |
| 78 | ST_IN HReg hregPPC_GPR18 ( Bool mode64 ) { return GPR(mode64, 18, 12, 14); } |
| 79 | ST_IN HReg hregPPC_GPR19 ( Bool mode64 ) { return GPR(mode64, 19, 13, 15); } |
| 80 | ST_IN HReg hregPPC_GPR20 ( Bool mode64 ) { return GPR(mode64, 20, 14, 16); } |
| 81 | ST_IN HReg hregPPC_GPR21 ( Bool mode64 ) { return GPR(mode64, 21, 15, 17); } |
| 82 | ST_IN HReg hregPPC_GPR22 ( Bool mode64 ) { return GPR(mode64, 22, 16, 18); } |
| 83 | ST_IN HReg hregPPC_GPR23 ( Bool mode64 ) { return GPR(mode64, 23, 17, 19); } |
| 84 | ST_IN HReg hregPPC_GPR24 ( Bool mode64 ) { return GPR(mode64, 24, 18, 20); } |
| 85 | ST_IN HReg hregPPC_GPR25 ( Bool mode64 ) { return GPR(mode64, 25, 19, 21); } |
| 86 | ST_IN HReg hregPPC_GPR26 ( Bool mode64 ) { return GPR(mode64, 26, 20, 22); } |
| 87 | ST_IN HReg hregPPC_GPR27 ( Bool mode64 ) { return GPR(mode64, 27, 21, 23); } |
| 88 | ST_IN HReg hregPPC_GPR28 ( Bool mode64 ) { return GPR(mode64, 28, 22, 24); } |
| 89 | |
| 90 | ST_IN HReg hregPPC_FPR14 ( Bool mode64 ) { return FPR(mode64, 14, 23, 25); } |
| 91 | ST_IN HReg hregPPC_FPR15 ( Bool mode64 ) { return FPR(mode64, 15, 24, 26); } |
| 92 | ST_IN HReg hregPPC_FPR16 ( Bool mode64 ) { return FPR(mode64, 16, 25, 27); } |
| 93 | ST_IN HReg hregPPC_FPR17 ( Bool mode64 ) { return FPR(mode64, 17, 26, 28); } |
| 94 | ST_IN HReg hregPPC_FPR18 ( Bool mode64 ) { return FPR(mode64, 18, 27, 29); } |
| 95 | ST_IN HReg hregPPC_FPR19 ( Bool mode64 ) { return FPR(mode64, 19, 28, 30); } |
| 96 | ST_IN HReg hregPPC_FPR20 ( Bool mode64 ) { return FPR(mode64, 20, 29, 31); } |
| 97 | ST_IN HReg hregPPC_FPR21 ( Bool mode64 ) { return FPR(mode64, 21, 30, 32); } |
| 98 | |
| 99 | ST_IN HReg hregPPC_VR20 ( Bool mode64 ) { return VR (mode64, 20, 31, 33); } |
| 100 | ST_IN HReg hregPPC_VR21 ( Bool mode64 ) { return VR (mode64, 21, 32, 34); } |
| 101 | ST_IN HReg hregPPC_VR22 ( Bool mode64 ) { return VR (mode64, 22, 33, 35); } |
| 102 | ST_IN HReg hregPPC_VR23 ( Bool mode64 ) { return VR (mode64, 23, 34, 36); } |
| 103 | ST_IN HReg hregPPC_VR24 ( Bool mode64 ) { return VR (mode64, 24, 35, 37); } |
| 104 | ST_IN HReg hregPPC_VR25 ( Bool mode64 ) { return VR (mode64, 25, 36, 38); } |
| 105 | ST_IN HReg hregPPC_VR26 ( Bool mode64 ) { return VR (mode64, 26, 37, 39); } |
| 106 | ST_IN HReg hregPPC_VR27 ( Bool mode64 ) { return VR (mode64, 27, 38, 40); } |
| 107 | |
| 108 | ST_IN HReg hregPPC_GPR1 ( Bool mode64 ) { return GPR(mode64, 1, 39, 41); } |
| 109 | ST_IN HReg hregPPC_GPR29 ( Bool mode64 ) { return GPR(mode64, 29, 40, 42); } |
| 110 | ST_IN HReg hregPPC_GPR30 ( Bool mode64 ) { return GPR(mode64, 30, 41, 43); } |
| 111 | ST_IN HReg hregPPC_GPR31 ( Bool mode64 ) { return GPR(mode64, 31, 42, 44); } |
| 112 | ST_IN HReg hregPPC_VR29 ( Bool mode64 ) { return VR (mode64, 29, 43, 45); } |
| 113 | |
| 114 | #undef ST_IN |
| 115 | #undef GPR |
| 116 | #undef FPR |
| 117 | #undef VR |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 118 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 119 | #define StackFramePtr(_mode64) hregPPC_GPR1(_mode64) |
| 120 | #define GuestStatePtr(_mode64) hregPPC_GPR31(_mode64) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 121 | |
sewardj | a5b5022 | 2015-03-26 07:18:32 +0000 | [diff] [blame] | 122 | /* Num registers used for function calls */ |
| 123 | #define PPC_N_REGPARMS 8 |
| 124 | |
| 125 | extern void ppHRegPPC ( HReg ); |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 126 | |
| 127 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 128 | /* --------- Condition codes --------- */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 129 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 130 | /* This gives names from bitfields in CR; hence it names BI numbers */ |
| 131 | /* Using IBM/hardware indexing convention */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 132 | typedef |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 133 | enum { |
| 134 | // CR7, which we use for integer compares |
| 135 | Pcf_7LT = 28, /* neg | lt */ |
| 136 | Pcf_7GT = 29, /* pos | gt */ |
| 137 | Pcf_7EQ = 30, /* zero | equal */ |
sewardj | 7e30807 | 2011-05-04 09:50:48 +0000 | [diff] [blame] | 138 | Pcf_7SO = 31, /* summary overflow */ |
| 139 | Pcf_NONE = 32 /* no condition; used with Pct_ALWAYS */ |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 140 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 141 | PPCCondFlag; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 142 | |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 143 | typedef |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 144 | enum { /* Maps bc bitfield BO */ |
sewardj | 7e30807 | 2011-05-04 09:50:48 +0000 | [diff] [blame] | 145 | Pct_FALSE = 0x4, /* associated PPCCondFlag must not be Pcf_NONE */ |
| 146 | Pct_TRUE = 0xC, /* associated PPCCondFlag must not be Pcf_NONE */ |
| 147 | Pct_ALWAYS = 0x14 /* associated PPCCondFlag must be Pcf_NONE */ |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 148 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 149 | PPCCondTest; |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 150 | |
| 151 | typedef |
| 152 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 153 | PPCCondFlag flag; |
| 154 | PPCCondTest test; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 155 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 156 | PPCCondCode; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 157 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 158 | extern const HChar* showPPCCondCode ( PPCCondCode ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 159 | |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 160 | /* constructor */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 161 | extern PPCCondCode mk_PPCCondCode ( PPCCondTest, PPCCondFlag ); |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 162 | |
| 163 | /* false->true, true->false */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 164 | extern PPCCondTest invertCondTest ( PPCCondTest ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 165 | |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 166 | |
| 167 | |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 168 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 169 | /* --------- Memory address expressions (amodes). --------- */ |
| 170 | |
| 171 | typedef |
| 172 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 173 | Pam_IR=1, /* Immediate (signed 16-bit) + Reg */ |
| 174 | Pam_RR=2 /* Reg1 + Reg2 */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 175 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 176 | PPCAModeTag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 177 | |
| 178 | typedef |
| 179 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 180 | PPCAModeTag tag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 181 | union { |
| 182 | struct { |
| 183 | HReg base; |
sewardj | a5f957d | 2005-07-02 01:29:32 +0000 | [diff] [blame] | 184 | Int index; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 185 | } IR; |
| 186 | struct { |
| 187 | HReg base; |
| 188 | HReg index; |
| 189 | } RR; |
| 190 | } Pam; |
| 191 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 192 | PPCAMode; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 193 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 194 | extern PPCAMode* PPCAMode_IR ( Int, HReg ); |
| 195 | extern PPCAMode* PPCAMode_RR ( HReg, HReg ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 196 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 197 | extern PPCAMode* dopyPPCAMode ( PPCAMode* ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 198 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 199 | extern void ppPPCAMode ( PPCAMode* ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 200 | |
| 201 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 202 | /* --------- Operand, which can be a reg or a u16/s16. --------- */ |
| 203 | /* ("RH" == "Register or Halfword immediate") */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 204 | typedef |
| 205 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 206 | Prh_Imm=3, |
| 207 | Prh_Reg=4 |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 208 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 209 | PPCRHTag; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 210 | |
| 211 | typedef |
| 212 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 213 | PPCRHTag tag; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 214 | union { |
| 215 | struct { |
| 216 | Bool syned; |
| 217 | UShort imm16; |
| 218 | } Imm; |
| 219 | struct { |
| 220 | HReg reg; |
| 221 | } Reg; |
| 222 | } |
| 223 | Prh; |
| 224 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 225 | PPCRH; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 226 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 227 | extern PPCRH* PPCRH_Imm ( Bool, UShort ); |
| 228 | extern PPCRH* PPCRH_Reg ( HReg ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 229 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 230 | extern void ppPPCRH ( PPCRH* ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 231 | |
| 232 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 233 | /* --------- Operand, which can be a reg or a u32/64. --------- */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 234 | |
| 235 | typedef |
| 236 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 237 | Pri_Imm=5, |
| 238 | Pri_Reg=6 |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 239 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 240 | PPCRITag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 241 | |
| 242 | typedef |
| 243 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 244 | PPCRITag tag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 245 | union { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 246 | ULong Imm; |
| 247 | HReg Reg; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 248 | } |
| 249 | Pri; |
| 250 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 251 | PPCRI; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 252 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 253 | extern PPCRI* PPCRI_Imm ( ULong ); |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 254 | extern PPCRI* PPCRI_Reg( HReg ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 255 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 256 | extern void ppPPCRI ( PPCRI* ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 257 | |
| 258 | |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 259 | /* --------- Operand, which can be a vector reg or a s6. --------- */ |
| 260 | /* ("VI" == "Vector Register or Immediate") */ |
| 261 | typedef |
| 262 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 263 | Pvi_Imm=7, |
| 264 | Pvi_Reg=8 |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 265 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 266 | PPCVI5sTag; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 267 | |
| 268 | typedef |
| 269 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 270 | PPCVI5sTag tag; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 271 | union { |
| 272 | Char Imm5s; |
| 273 | HReg Reg; |
| 274 | } |
| 275 | Pvi; |
| 276 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 277 | PPCVI5s; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 278 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 279 | extern PPCVI5s* PPCVI5s_Imm ( Char ); |
| 280 | extern PPCVI5s* PPCVI5s_Reg ( HReg ); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 281 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 282 | extern void ppPPCVI5s ( PPCVI5s* ); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 283 | |
| 284 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 285 | /* --------- Instructions. --------- */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 286 | |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 287 | /* --------- */ |
| 288 | typedef |
| 289 | enum { |
| 290 | Pun_NEG, |
cerion | e13bb31 | 2005-02-10 19:51:03 +0000 | [diff] [blame] | 291 | Pun_NOT, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 292 | Pun_CLZ32, |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 293 | Pun_CLZ64, |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 294 | Pun_CTZ32, |
| 295 | Pun_CTZ64, |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 296 | Pun_EXTSW |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 297 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 298 | PPCUnaryOp; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 299 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 300 | extern const HChar* showPPCUnaryOp ( PPCUnaryOp ); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 301 | |
| 302 | |
| 303 | /* --------- */ |
| 304 | typedef |
| 305 | enum { |
| 306 | Palu_INVALID, |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 307 | Palu_ADD, Palu_SUB, |
| 308 | Palu_AND, Palu_OR, Palu_XOR, |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 309 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 310 | PPCAluOp; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 311 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 312 | extern |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 313 | const HChar* showPPCAluOp ( PPCAluOp, |
| 314 | Bool /* is the 2nd operand an immediate? */); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 315 | |
| 316 | |
| 317 | /* --------- */ |
| 318 | typedef |
| 319 | enum { |
| 320 | Pshft_INVALID, |
| 321 | Pshft_SHL, Pshft_SHR, Pshft_SAR, |
| 322 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 323 | PPCShftOp; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 324 | |
| 325 | extern |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 326 | const HChar* showPPCShftOp ( PPCShftOp, |
| 327 | Bool /* is the 2nd operand an immediate? */, |
| 328 | Bool /* is this a 32bit or 64bit op? */ ); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 329 | |
| 330 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 331 | /* --------- */ |
| 332 | typedef |
| 333 | enum { |
| 334 | Pfp_INVALID, |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 335 | |
| 336 | /* Ternary */ |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 337 | Pfp_MADDD, Pfp_MSUBD, |
| 338 | Pfp_MADDS, Pfp_MSUBS, |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 339 | Pfp_FPADDQ, Pfp_FPADDQRNDODD, |
| 340 | Pfp_FPSUBQ, Pfp_FPSUBQRNDODD, |
| 341 | Pfp_FPMULQ, Pfp_FPMULQRNDODD, |
| 342 | Pfp_FPDIVQ, Pfp_FPDIVQRNDODD, |
| 343 | Pfp_FPMULADDQ, Pfp_FPMULADDQRNDODD, |
| 344 | Pfp_FPMULSUBQ, Pfp_FPMULSUBQRNDODD, |
| 345 | Pfp_FPNEGMULADDQ, Pfp_FPNEGMULADDQRNDODD, |
| 346 | Pfp_FPNEGMULSUBQ, Pfp_FPNEGMULSUBQRNDODD, |
| 347 | Pfp_FPSQRTQ, Pfp_FPSQRTQRNDODD, |
| 348 | Pfp_FPQTOD, Pfp_FPQTODRNDODD, |
| 349 | Pfp_FPQTOW, Pfp_FPQTOWRNDODD, |
| 350 | Pfp_FPDTOQ, |
| 351 | Pfp_IDSTOQ, |
| 352 | Pfp_IDUTOQ, |
| 353 | Pfp_TRUNCFPQTOISD, |
| 354 | Pfp_TRUNCFPQTOISW, |
| 355 | Pfp_TRUNCFPQTOIUD, |
| 356 | Pfp_TRUNCFPQTOIUW, |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 357 | Pfp_DFPADD, Pfp_DFPADDQ, |
| 358 | Pfp_DFPSUB, Pfp_DFPSUBQ, |
| 359 | Pfp_DFPMUL, Pfp_DFPMULQ, |
| 360 | Pfp_DFPDIV, Pfp_DFPDIVQ, |
| 361 | Pfp_DQUAQ, Pfp_DRRNDQ, |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 362 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 363 | /* Binary */ |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 364 | Pfp_ADDD, Pfp_SUBD, Pfp_MULD, Pfp_DIVD, |
| 365 | Pfp_ADDS, Pfp_SUBS, Pfp_MULS, Pfp_DIVS, |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 366 | Pfp_DRSP, Pfp_DRDPQ, Pfp_DCTFIX, Pfp_DCTFIXQ, Pfp_DCFFIX, |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 367 | Pfp_DQUA, Pfp_RRDTR, Pfp_DIEX, Pfp_DIEXQ, Pfp_DRINTN, |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 368 | |
| 369 | /* Unary */ |
sewardj | 0f1ef86 | 2008-08-08 08:37:06 +0000 | [diff] [blame] | 370 | Pfp_SQRT, Pfp_ABS, Pfp_NEG, Pfp_MOV, Pfp_RES, Pfp_RSQRTE, |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 371 | Pfp_FRIN, Pfp_FRIM, Pfp_FRIP, Pfp_FRIZ, |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 372 | Pfp_DSCLI, Pfp_DSCRI, Pfp_DSCLIQ, Pfp_DSCRIQ, Pfp_DCTDP, |
| 373 | Pfp_DCTQPQ, Pfp_DCFFIXQ, Pfp_DXEX, Pfp_DXEXQ, |
| 374 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 375 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 376 | PPCFpOp; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 377 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 378 | extern const HChar* showPPCFpOp ( PPCFpOp ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 379 | |
| 380 | |
| 381 | /* --------- */ |
| 382 | typedef |
| 383 | enum { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 384 | Pav_INVALID, |
| 385 | |
| 386 | /* Integer Unary */ |
| 387 | Pav_MOV, /* Mov */ |
| 388 | Pav_NOT, /* Bitwise */ |
| 389 | Pav_UNPCKH8S, Pav_UNPCKH16S, /* Unpack */ |
| 390 | Pav_UNPCKL8S, Pav_UNPCKL16S, |
| 391 | Pav_UNPCKHPIX, Pav_UNPCKLPIX, |
| 392 | |
| 393 | /* Integer Binary */ |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 394 | Pav_AND, Pav_OR, Pav_XOR, /* Bitwise */ |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 395 | Pav_ADDU, Pav_QADDU, Pav_QADDS, |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 396 | Pav_SUBU, Pav_QSUBU, Pav_QSUBS, |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 397 | Pav_MULU, |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 398 | Pav_OMULU, Pav_OMULS, Pav_EMULU, Pav_EMULS, |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 399 | Pav_AVGU, Pav_AVGS, |
| 400 | Pav_MAXU, Pav_MAXS, |
| 401 | Pav_MINU, Pav_MINS, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 402 | |
| 403 | /* Compare (always affects CR field 6) */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 404 | Pav_CMPEQU, Pav_CMPGTU, Pav_CMPGTS, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 405 | |
| 406 | /* Shift */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 407 | Pav_SHL, Pav_SHR, Pav_SAR, Pav_ROTL, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 408 | |
| 409 | /* Pack */ |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 410 | Pav_PACKUU, Pav_QPACKUU, Pav_QPACKSU, Pav_QPACKSS, |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 411 | Pav_PACKPXL, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 412 | |
| 413 | /* Merge */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 414 | Pav_MRGHI, Pav_MRGLO, |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 415 | |
| 416 | /* Concatenation */ |
| 417 | Pav_CATODD, Pav_CATEVEN, |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 418 | |
| 419 | /* Polynomial Multipy-Add */ |
| 420 | Pav_POLYMULADD, |
| 421 | |
| 422 | /* Cipher */ |
| 423 | Pav_CIPHERV128, Pav_CIPHERLV128, Pav_NCIPHERV128, Pav_NCIPHERLV128, |
| 424 | Pav_CIPHERSUBV128, |
| 425 | |
| 426 | /* Hash */ |
| 427 | Pav_SHA256, Pav_SHA512, |
| 428 | |
| 429 | /* BCD Arithmetic */ |
| 430 | Pav_BCDAdd, Pav_BCDSub, |
| 431 | |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 432 | /* Conversion signed 128-bit value to signed BCD 128-bit */ |
| 433 | Pav_I128StoBCD128, |
| 434 | |
| 435 | /* Conversion signed BCD 128-bit to signed 128-bit value */ |
| 436 | Pav_BCD128toI128S, |
| 437 | |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 438 | /* zero count */ |
| 439 | Pav_ZEROCNTBYTE, Pav_ZEROCNTWORD, Pav_ZEROCNTHALF, Pav_ZEROCNTDBL, |
carll | 60c6bac | 2013-10-18 01:19:06 +0000 | [diff] [blame] | 440 | |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 441 | /* trailing zero count */ |
| 442 | Pav_TRAILINGZEROCNTBYTE, Pav_TRAILINGZEROCNTWORD, |
| 443 | Pav_TRAILINGZEROCNTHALF, Pav_TRAILINGZEROCNTDBL, |
| 444 | |
carll | 60c6bac | 2013-10-18 01:19:06 +0000 | [diff] [blame] | 445 | /* Vector bit matrix transpose by byte */ |
| 446 | Pav_BITMTXXPOSE, |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 447 | |
| 448 | /* Vector Half-precision format to single precision conversion */ |
| 449 | Pav_F16toF32x4, |
| 450 | |
| 451 | /* Vector Single precision format to Half-precision conversion */ |
| 452 | Pav_F32toF16x4, |
| 453 | |
| 454 | /* Vector Half-precision format to Double precision conversion */ |
| 455 | Pav_F16toF64x2, |
| 456 | |
| 457 | /* Vector Double precision format to Half-precision conversion */ |
| 458 | Pav_F64toF16x2, |
| 459 | |
| 460 | /* 128 bit mult by 10 */ |
| 461 | Pav_MulI128by10, |
| 462 | |
| 463 | /* 128 bit mult by 10, carry out */ |
| 464 | Pav_MulI128by10Carry, |
| 465 | |
| 466 | /* 128 bit mult by 10 plus carry in */ |
| 467 | Pav_MulI128by10E, |
| 468 | |
| 469 | /* 128 bit mult by 10 plus carry in, carry out */ |
| 470 | Pav_MulI128by10ECarry, |
| 471 | |
| 472 | /* F128 to I128 */ |
| 473 | Pav_F128toI128S, |
| 474 | |
| 475 | /* Round F128 to F128 */ |
| 476 | Pav_ROUNDFPQ, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 477 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 478 | PPCAvOp; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 479 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 480 | extern const HChar* showPPCAvOp ( PPCAvOp ); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 481 | |
| 482 | |
| 483 | /* --------- */ |
| 484 | typedef |
| 485 | enum { |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 486 | Pavfp_INVALID, |
| 487 | |
| 488 | /* Floating point binary */ |
| 489 | Pavfp_ADDF, Pavfp_SUBF, Pavfp_MULF, |
| 490 | Pavfp_MAXF, Pavfp_MINF, |
| 491 | Pavfp_CMPEQF, Pavfp_CMPGTF, Pavfp_CMPGEF, |
| 492 | |
| 493 | /* Floating point unary */ |
| 494 | Pavfp_RCPF, Pavfp_RSQRTF, |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 495 | Pavfp_CVTU2F, Pavfp_CVTS2F, Pavfp_QCVTF2U, Pavfp_QCVTF2S, |
| 496 | Pavfp_ROUNDM, Pavfp_ROUNDP, Pavfp_ROUNDN, Pavfp_ROUNDZ, |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 497 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 498 | PPCAvFpOp; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 499 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 500 | extern const HChar* showPPCAvFpOp ( PPCAvFpOp ); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 501 | |
| 502 | |
| 503 | /* --------- */ |
| 504 | typedef |
| 505 | enum { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 506 | Pin_LI, /* load word (32/64-bit) immediate (fake insn) */ |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 507 | Pin_Alu, /* word add/sub/and/or/xor */ |
| 508 | Pin_Shft, /* word shl/shr/sar */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 509 | Pin_AddSubC, /* add/sub with read/write carry */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 510 | Pin_Cmp, /* word compare */ |
| 511 | Pin_Unary, /* not, neg, clz */ |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 512 | Pin_MulL, /* widening multiply */ |
| 513 | Pin_Div, /* div */ |
| 514 | Pin_Call, /* call to address in register */ |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 515 | Pin_XDirect, /* direct transfer to GA */ |
| 516 | Pin_XIndir, /* indirect transfer to GA */ |
| 517 | Pin_XAssisted, /* assisted transfer to GA */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 518 | Pin_CMov, /* conditional move */ |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 519 | Pin_Load, /* zero-extending load a 8|16|32|64 bit value from mem */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 520 | Pin_LoadL, /* load-linked (lwarx/ldarx) 32|64 bit value from mem */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 521 | Pin_Store, /* store a 8|16|32|64 bit value to mem */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 522 | Pin_StoreC, /* store-conditional (stwcx./stdcx.) 32|64 bit val */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 523 | Pin_Set, /* convert condition code to value 0 or 1 */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 524 | Pin_MfCR, /* move from condition register to GPR */ |
| 525 | Pin_MFence, /* mem fence */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 526 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 527 | Pin_FpUnary, /* FP unary op */ |
| 528 | Pin_FpBinary, /* FP binary op */ |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 529 | Pin_Fp128Unary, /* FP unary op for 128-bit floating point */ |
| 530 | Pin_Fp128Binary, /* FP binary op for 128-bit floating point */ |
| 531 | Pin_Fp128Trinary, /* FP trinary op for 128-bit floating point */ |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 532 | Pin_FpMulAcc, /* FP multipy-accumulate style op */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 533 | Pin_FpLdSt, /* FP load/store */ |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 534 | Pin_FpSTFIW, /* stfiwx */ |
| 535 | Pin_FpRSP, /* FP round IEEE754 double to IEEE754 single */ |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 536 | Pin_FpCftI, /* fcfid[u,s,us]/fctid[u]/fctiw[u] */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 537 | Pin_FpCMov, /* FP floating point conditional move */ |
| 538 | Pin_FpLdFPSCR, /* mtfsf */ |
| 539 | Pin_FpCmp, /* FP compare, generating value into int reg */ |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 540 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 541 | Pin_RdWrLR, /* Read/Write Link Register */ |
| 542 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 543 | Pin_AvLdSt, /* AV load/store (kludging for AMode_IR) */ |
| 544 | Pin_AvUnary, /* AV unary general reg=>reg */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 545 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 546 | Pin_AvBinary, /* AV binary general reg,reg=>reg */ |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 547 | Pin_AvBinaryInt,/* AV binary reg,int=>reg */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 548 | Pin_AvBin8x16, /* AV binary, 8x4 */ |
| 549 | Pin_AvBin16x8, /* AV binary, 16x4 */ |
| 550 | Pin_AvBin32x4, /* AV binary, 32x4 */ |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 551 | Pin_AvBin64x2, /* AV binary, 64x2 */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 552 | |
| 553 | Pin_AvBin32Fx4, /* AV FP binary, 32Fx4 */ |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 554 | Pin_AvUn32Fx4, /* AV FP unary, 32Fx4 */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 555 | |
| 556 | Pin_AvPerm, /* AV permute (shuffle) */ |
| 557 | Pin_AvSel, /* AV select */ |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 558 | Pin_AvSh, /* AV shift left or right */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 559 | Pin_AvShlDbl, /* AV shift-left double by imm */ |
| 560 | Pin_AvSplat, /* One elem repeated throughout dst */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 561 | Pin_AvLdVSCR, /* mtvscr */ |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 562 | Pin_AvCMov, /* AV conditional move */ |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 563 | Pin_AvCipherV128Unary, /* AV Vector unary Cipher */ |
| 564 | Pin_AvCipherV128Binary, /* AV Vector binary Cipher */ |
| 565 | Pin_AvHashV128Binary, /* AV Vector binary Hash */ |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 566 | Pin_AvBCDV128Binary, /* BCD Arithmetic */ |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 567 | Pin_Dfp64Unary, /* DFP64 unary op */ |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 568 | Pin_Dfp128Unary, /* DFP128 unary op */ |
| 569 | Pin_DfpShift, /* Decimal floating point shift by immediate value */ |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 570 | Pin_Dfp64Binary, /* DFP64 binary op */ |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 571 | Pin_Dfp128Binary, /* DFP128 binary op */ |
| 572 | Pin_DfpShift128, /* 128-bit Decimal floating point shift by |
| 573 | * immediate value */ |
| 574 | Pin_DfpD128toD64, /* DFP 128 to DFP 64 op */ |
| 575 | Pin_DfpI64StoD128, /* DFP signed integer to DFP 128 */ |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 576 | Pin_DfpRound, /* D64 round to D64 */ |
| 577 | Pin_DfpRound128, /* D128 round to D128 */ |
| 578 | Pin_ExtractExpD128, /* DFP, extract 64 bit exponent */ |
| 579 | Pin_InsertExpD128, /* DFP, insert 64 bit exponent and 128 bit binary |
| 580 | * significand into a DFP 128-bit value*/ |
| 581 | Pin_Dfp64Cmp, /* DFP 64-bit compare, generating value into |
| 582 | * int reg */ |
| 583 | Pin_Dfp128Cmp, /* DFP 128-bit compare, generating value into |
| 584 | * int reg */ |
| 585 | Pin_DfpQuantize, /* D64 quantize using register value, significance |
| 586 | * round */ |
| 587 | Pin_DfpQuantize128, /* D128 quantize using register value, significance |
| 588 | * round */ |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 589 | Pin_EvCheck, /* Event check */ |
| 590 | Pin_ProfInc /* 64-bit profile counter increment */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 591 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 592 | PPCInstrTag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 593 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 594 | /* Destinations are on the LEFT (first operand) */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 595 | |
| 596 | typedef |
| 597 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 598 | PPCInstrTag tag; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 599 | union { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 600 | /* Get a 32/64-bit literal into a register. |
| 601 | May turn into a number of real insns. */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 602 | struct { |
| 603 | HReg dst; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 604 | ULong imm64; |
| 605 | } LI; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 606 | /* Integer add/sub/and/or/xor. Limitations: |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 607 | - For add, the immediate, if it exists, is a signed 16. |
| 608 | - For sub, the immediate, if it exists, is a signed 16 |
| 609 | which may not be -32768, since no such instruction |
| 610 | exists, and so we have to emit addi with +32768, but |
| 611 | that is not possible. |
| 612 | - For and/or/xor, the immediate, if it exists, |
| 613 | is an unsigned 16. |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 614 | */ |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 615 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 616 | PPCAluOp op; |
| 617 | HReg dst; |
| 618 | HReg srcL; |
| 619 | PPCRH* srcR; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 620 | } Alu; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 621 | /* Integer shl/shr/sar. |
| 622 | Limitations: the immediate, if it exists, |
| 623 | is a signed 5-bit value between 1 and 31 inclusive. |
| 624 | */ |
| 625 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 626 | PPCShftOp op; |
| 627 | Bool sz32; /* mode64 has both 32 and 64bit shft */ |
| 628 | HReg dst; |
| 629 | HReg srcL; |
| 630 | PPCRH* srcR; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 631 | } Shft; |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 632 | /* */ |
| 633 | struct { |
| 634 | Bool isAdd; /* else sub */ |
| 635 | Bool setC; /* else read carry */ |
| 636 | HReg dst; |
| 637 | HReg srcL; |
| 638 | HReg srcR; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 639 | } AddSubC; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 640 | /* If signed, the immediate, if it exists, is a signed 16, |
| 641 | else it is an unsigned 16. */ |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 642 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 643 | Bool syned; |
| 644 | Bool sz32; /* mode64 has both 32 and 64bit cmp */ |
| 645 | UInt crfD; |
| 646 | HReg srcL; |
| 647 | PPCRH* srcR; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 648 | } Cmp; |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 649 | /* Not, Neg, Clz32/64, Extsw */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 650 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 651 | PPCUnaryOp op; |
| 652 | HReg dst; |
| 653 | HReg src; |
| 654 | } Unary; |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 655 | struct { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 656 | Bool syned; /* meaningless if hi32==False */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 657 | Bool hi; /* False=>low, True=>high */ |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 658 | Bool sz32; /* mode64 has both 32 & 64bit mull */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 659 | HReg dst; |
| 660 | HReg srcL; |
| 661 | HReg srcR; |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 662 | } MulL; |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 663 | /* ppc32 div/divu instruction. */ |
cerion | c0e707e | 2005-02-10 22:35:34 +0000 | [diff] [blame] | 664 | struct { |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 665 | Bool extended; |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 666 | Bool syned; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 667 | Bool sz32; /* mode64 has both 32 & 64bit div */ |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 668 | HReg dst; |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 669 | HReg srcL; |
| 670 | HReg srcR; |
cerion | c0e707e | 2005-02-10 22:35:34 +0000 | [diff] [blame] | 671 | } Div; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 672 | /* Pseudo-insn. Call target (an absolute address), on given |
sewardj | 6a64a9f | 2005-08-21 00:48:37 +0000 | [diff] [blame] | 673 | condition (which could be Pct_ALWAYS). argiregs indicates |
| 674 | which of r3 .. r10 carries argument values for this call, |
| 675 | using a bit mask (1<<N is set if rN holds an arg, for N in |
| 676 | 3 .. 10 inclusive). */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 677 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 678 | PPCCondCode cond; |
| 679 | Addr64 target; |
| 680 | UInt argiregs; |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 681 | RetLoc rloc; /* where the return value will be */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 682 | } Call; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 683 | /* Update the guest CIA value, then exit requesting to chain |
| 684 | to it. May be conditional. Use of Addr64 in order to cope |
| 685 | with 64-bit hosts. */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 686 | struct { |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 687 | Addr64 dstGA; /* next guest address */ |
| 688 | PPCAMode* amCIA; /* amode in guest state for CIA */ |
| 689 | PPCCondCode cond; /* can be ALWAYS */ |
| 690 | Bool toFastEP; /* chain to the slow or fast point? */ |
| 691 | } XDirect; |
| 692 | /* Boring transfer to a guest address not known at JIT time. |
| 693 | Not chainable. May be conditional. */ |
| 694 | struct { |
| 695 | HReg dstGA; |
| 696 | PPCAMode* amCIA; |
| 697 | PPCCondCode cond; /* can be ALWAYS */ |
| 698 | } XIndir; |
| 699 | /* Assisted transfer to a guest address, most general case. |
| 700 | Not chainable. May be conditional. */ |
| 701 | struct { |
| 702 | HReg dstGA; |
| 703 | PPCAMode* amCIA; |
| 704 | PPCCondCode cond; /* can be ALWAYS */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 705 | IRJumpKind jk; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 706 | } XAssisted; |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 707 | /* Mov src to dst on the given condition, which may not |
cerion | 9abfcbc | 2005-02-25 11:16:58 +0000 | [diff] [blame] | 708 | be the bogus Pct_ALWAYS. */ |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 709 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 710 | PPCCondCode cond; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 711 | HReg dst; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 712 | PPCRI* src; |
| 713 | } CMov; |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 714 | /* Zero extending loads. Dst size is host word size */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 715 | struct { |
| 716 | UChar sz; /* 1|2|4|8 */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 717 | HReg dst; |
| 718 | PPCAMode* src; |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 719 | } Load; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 720 | /* Load-and-reserve (lwarx, ldarx) */ |
| 721 | struct { |
| 722 | UChar sz; /* 4|8 */ |
| 723 | HReg dst; |
| 724 | HReg src; |
| 725 | } LoadL; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 726 | /* 64/32/16/8 bit stores */ |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 727 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 728 | UChar sz; /* 1|2|4|8 */ |
| 729 | PPCAMode* dst; |
| 730 | HReg src; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 731 | } Store; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 732 | /* Store-conditional (stwcx., stdcx.) */ |
| 733 | struct { |
| 734 | UChar sz; /* 4|8 */ |
| 735 | HReg dst; |
| 736 | HReg src; |
| 737 | } StoreC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 738 | /* Convert a ppc condition code to value 0 or 1. */ |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 739 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 740 | PPCCondCode cond; |
| 741 | HReg dst; |
| 742 | } Set; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 743 | /* Move the entire CR to a GPR */ |
| 744 | struct { |
| 745 | HReg dst; |
| 746 | } MfCR; |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 747 | /* Mem fence. In short, an insn which flushes all preceding |
| 748 | loads and stores as much as possible before continuing. |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 749 | On PPC we emit a "sync". */ |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 750 | struct { |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 751 | } MFence; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 752 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 753 | /* PPC Floating point */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 754 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 755 | PPCFpOp op; |
| 756 | HReg dst; |
| 757 | HReg src; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 758 | } FpUnary; |
| 759 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 760 | PPCFpOp op; |
| 761 | HReg dst; |
| 762 | HReg srcL; |
| 763 | HReg srcR; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 764 | } FpBinary; |
| 765 | struct { |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 766 | PPCFpOp op; |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 767 | HReg dst; |
| 768 | HReg src; |
| 769 | } Fp128Unary; |
| 770 | struct { |
| 771 | PPCFpOp op; |
| 772 | HReg dst; |
| 773 | HReg srcL; |
| 774 | HReg srcR; |
| 775 | } Fp128Binary; |
| 776 | struct { |
| 777 | PPCFpOp op; |
| 778 | HReg dst; |
| 779 | HReg srcL; |
| 780 | HReg srcR; |
| 781 | } Fp128Trinary; |
| 782 | struct { |
| 783 | PPCFpOp op; |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 784 | HReg dst; |
| 785 | HReg srcML; |
| 786 | HReg srcMR; |
| 787 | HReg srcAcc; |
| 788 | } FpMulAcc; |
| 789 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 790 | Bool isLoad; |
| 791 | UChar sz; /* only 4 (IEEE single) or 8 (IEEE double) */ |
| 792 | HReg reg; |
| 793 | PPCAMode* addr; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 794 | } FpLdSt; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 795 | struct { |
| 796 | HReg addr; /* int reg */ |
| 797 | HReg data; /* float reg */ |
| 798 | } FpSTFIW; |
| 799 | /* Round 64-bit FP value to 32-bit FP value in an FP reg. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 800 | struct { |
| 801 | HReg src; |
| 802 | HReg dst; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 803 | } FpRSP; |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 804 | /* fcfid[u,s,us]/fctid[u]/fctiw[u]. Only some combinations |
| 805 | of the various fields are allowed. This is asserted for |
| 806 | and documented in the code for the constructor, |
| 807 | PPCInstr_FpCftI, in host_ppc_defs.c. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 808 | struct { |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 809 | Bool fromI; /* True== I->F, False== F->I */ |
| 810 | Bool int32; /* True== I is 32, False== I is 64 */ |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 811 | Bool syned; |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 812 | Bool flt64; /* True== F is 64, False== F is 32 */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 813 | HReg src; |
| 814 | HReg dst; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 815 | } FpCftI; |
| 816 | /* FP mov src to dst on the given condition. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 817 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 818 | PPCCondCode cond; |
| 819 | HReg dst; |
| 820 | HReg src; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 821 | } FpCMov; |
| 822 | /* Load FP Status & Control Register */ |
| 823 | struct { |
| 824 | HReg src; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 825 | UInt dfp_rm; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 826 | } FpLdFPSCR; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 827 | /* Do a compare, generating result into an int register. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 828 | struct { |
| 829 | UChar crfD; |
| 830 | HReg dst; |
| 831 | HReg srcL; |
| 832 | HReg srcR; |
| 833 | } FpCmp; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 834 | |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 835 | /* Read/Write Link Register */ |
| 836 | struct { |
| 837 | Bool wrLR; |
| 838 | HReg gpr; |
| 839 | } RdWrLR; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 840 | |
| 841 | /* Simplistic AltiVec */ |
| 842 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 843 | Bool isLoad; |
| 844 | UChar sz; /* 8|16|32|128 */ |
| 845 | HReg reg; |
| 846 | PPCAMode* addr; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 847 | } AvLdSt; |
| 848 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 849 | PPCAvOp op; |
| 850 | HReg dst; |
| 851 | HReg src; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 852 | } AvUnary; |
| 853 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 854 | PPCAvOp op; |
| 855 | HReg dst; |
| 856 | HReg srcL; |
| 857 | HReg srcR; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 858 | } AvBinary; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 859 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 860 | PPCAvOp op; |
| 861 | HReg dst; |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 862 | HReg src; |
| 863 | PPCRI* val; |
| 864 | } AvBinaryInt; |
| 865 | struct { |
| 866 | PPCAvOp op; |
| 867 | HReg dst; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 868 | HReg srcL; |
| 869 | HReg srcR; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 870 | } AvBin8x16; |
| 871 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 872 | PPCAvOp op; |
| 873 | HReg dst; |
| 874 | HReg srcL; |
| 875 | HReg srcR; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 876 | } AvBin16x8; |
| 877 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 878 | PPCAvOp op; |
| 879 | HReg dst; |
| 880 | HReg srcL; |
| 881 | HReg srcR; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 882 | } AvBin32x4; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 883 | /* Can only be generated for CPUs capable of ISA 2.07 or above */ |
| 884 | struct { |
| 885 | PPCAvOp op; |
| 886 | HReg dst; |
| 887 | HReg srcL; |
| 888 | HReg srcR; |
| 889 | } AvBin64x2; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 890 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 891 | PPCAvFpOp op; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 892 | HReg dst; |
| 893 | HReg srcL; |
| 894 | HReg srcR; |
| 895 | } AvBin32Fx4; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 896 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 897 | PPCAvFpOp op; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 898 | HReg dst; |
| 899 | HReg src; |
| 900 | } AvUn32Fx4; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 901 | /* Perm,Sel,SlDbl,Splat are all weird AV permutations */ |
| 902 | struct { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 903 | HReg dst; |
| 904 | HReg srcL; |
| 905 | HReg srcR; |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 906 | HReg ctl; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 907 | } AvPerm; |
| 908 | struct { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 909 | HReg dst; |
| 910 | HReg srcL; |
| 911 | HReg srcR; |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 912 | HReg ctl; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 913 | } AvSel; |
| 914 | struct { |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 915 | Bool shLeft; |
| 916 | HReg dst; |
carll | 99de41e | 2014-10-07 18:20:39 +0000 | [diff] [blame] | 917 | PPCAMode* addr; |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 918 | } AvSh; |
| 919 | struct { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 920 | UChar shift; |
| 921 | HReg dst; |
| 922 | HReg srcL; |
| 923 | HReg srcR; |
| 924 | } AvShlDbl; |
| 925 | struct { |
| 926 | UChar sz; /* 8,16,32 */ |
| 927 | HReg dst; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 928 | PPCVI5s* src; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 929 | } AvSplat; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 930 | /* Mov src to dst on the given condition, which may not |
| 931 | be the bogus Xcc_ALWAYS. */ |
| 932 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 933 | PPCCondCode cond; |
| 934 | HReg dst; |
| 935 | HReg src; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 936 | } AvCMov; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 937 | /* Load AltiVec Status & Control Register */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 938 | struct { |
| 939 | HReg src; |
| 940 | } AvLdVSCR; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 941 | struct { |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 942 | PPCAvOp op; |
| 943 | HReg dst; |
| 944 | HReg src; |
| 945 | } AvCipherV128Unary; |
| 946 | struct { |
| 947 | PPCAvOp op; |
| 948 | HReg dst; |
| 949 | HReg src; |
| 950 | PPCRI* s_field; |
| 951 | } AvHashV128Binary; |
| 952 | struct { |
| 953 | PPCAvOp op; |
| 954 | HReg dst; |
| 955 | HReg src1; |
| 956 | HReg src2; |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 957 | } AvBCDV128Binary; |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 958 | struct { |
| 959 | PPCAvOp op; |
| 960 | HReg dst; |
| 961 | HReg srcL; |
| 962 | HReg srcR; |
| 963 | } AvCipherV128Binary; |
| 964 | struct { |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 965 | PPCFpOp op; |
| 966 | HReg dst; |
| 967 | HReg src; |
| 968 | } Dfp64Unary; |
| 969 | struct { |
| 970 | PPCFpOp op; |
| 971 | HReg dst; |
| 972 | HReg srcL; |
| 973 | HReg srcR; |
| 974 | } Dfp64Binary; |
| 975 | struct { |
| 976 | PPCFpOp op; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 977 | HReg dst; |
| 978 | HReg src; |
| 979 | PPCRI* shift; |
| 980 | } DfpShift; |
| 981 | struct { |
| 982 | PPCFpOp op; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 983 | HReg dst_hi; |
| 984 | HReg dst_lo; |
| 985 | HReg src_hi; |
| 986 | HReg src_lo; |
| 987 | } Dfp128Unary; |
| 988 | struct { |
| 989 | /* The dst is used to pass the left source operand in and return |
| 990 | * the result. |
| 991 | */ |
| 992 | PPCFpOp op; |
| 993 | HReg dst_hi; |
| 994 | HReg dst_lo; |
| 995 | HReg srcR_hi; |
| 996 | HReg srcR_lo; |
| 997 | } Dfp128Binary; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 998 | struct { |
| 999 | PPCFpOp op; |
| 1000 | HReg dst_hi; |
| 1001 | HReg dst_lo; |
| 1002 | HReg src_hi; |
| 1003 | HReg src_lo; |
| 1004 | PPCRI* shift; |
| 1005 | } DfpShift128; |
| 1006 | struct { |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1007 | HReg dst; |
| 1008 | HReg src; |
| 1009 | PPCRI* r_rmc; |
| 1010 | } DfpRound; |
| 1011 | struct { |
| 1012 | HReg dst_hi; |
| 1013 | HReg dst_lo; |
| 1014 | HReg src_hi; |
| 1015 | HReg src_lo; |
| 1016 | PPCRI* r_rmc; |
| 1017 | } DfpRound128; |
| 1018 | struct { |
| 1019 | PPCFpOp op; |
| 1020 | HReg dst; |
| 1021 | HReg srcL; |
| 1022 | HReg srcR; |
| 1023 | PPCRI* rmc; |
| 1024 | } DfpQuantize; |
| 1025 | struct { |
| 1026 | PPCFpOp op; |
| 1027 | HReg dst_hi; |
| 1028 | HReg dst_lo; |
| 1029 | HReg src_hi; |
| 1030 | HReg src_lo; |
| 1031 | PPCRI* rmc; |
| 1032 | } DfpQuantize128; |
| 1033 | struct { |
| 1034 | PPCFpOp op; |
| 1035 | HReg dst; |
| 1036 | HReg src_hi; |
| 1037 | HReg src_lo; |
| 1038 | } ExtractExpD128; |
| 1039 | struct { |
| 1040 | PPCFpOp op; |
| 1041 | HReg dst_hi; |
| 1042 | HReg dst_lo; |
| 1043 | HReg srcL; |
| 1044 | HReg srcR_hi; |
| 1045 | HReg srcR_lo; |
| 1046 | } InsertExpD128; |
| 1047 | struct { |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1048 | PPCFpOp op; |
| 1049 | HReg dst; |
| 1050 | HReg src_hi; |
| 1051 | HReg src_lo; |
| 1052 | } DfpD128toD64; |
| 1053 | struct { |
| 1054 | PPCFpOp op; |
| 1055 | HReg dst_hi; |
| 1056 | HReg dst_lo; |
| 1057 | HReg src; |
| 1058 | } DfpI64StoD128; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1059 | struct { |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1060 | UChar crfD; |
| 1061 | HReg dst; |
| 1062 | HReg srcL; |
| 1063 | HReg srcR; |
| 1064 | } Dfp64Cmp; |
| 1065 | struct { |
| 1066 | UChar crfD; |
| 1067 | HReg dst; |
| 1068 | HReg srcL_hi; |
| 1069 | HReg srcL_lo; |
| 1070 | HReg srcR_hi; |
| 1071 | HReg srcR_lo; |
| 1072 | } Dfp128Cmp; |
| 1073 | struct { |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1074 | PPCAMode* amCounter; |
| 1075 | PPCAMode* amFailAddr; |
| 1076 | } EvCheck; |
| 1077 | struct { |
| 1078 | /* No fields. The address of the counter to inc is |
| 1079 | installed later, post-translation, by patching it in, |
| 1080 | as it is not known at translation time. */ |
| 1081 | } ProfInc; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1082 | } Pin; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1083 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1084 | PPCInstr; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1085 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 1086 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1087 | extern PPCInstr* PPCInstr_LI ( HReg, ULong, Bool ); |
| 1088 | extern PPCInstr* PPCInstr_Alu ( PPCAluOp, HReg, HReg, PPCRH* ); |
| 1089 | extern PPCInstr* PPCInstr_Shft ( PPCShftOp, Bool sz32, HReg, HReg, PPCRH* ); |
| 1090 | extern PPCInstr* PPCInstr_AddSubC ( Bool, Bool, HReg, HReg, HReg ); |
| 1091 | extern PPCInstr* PPCInstr_Cmp ( Bool, Bool, UInt, HReg, PPCRH* ); |
| 1092 | extern PPCInstr* PPCInstr_Unary ( PPCUnaryOp op, HReg dst, HReg src ); |
| 1093 | extern PPCInstr* PPCInstr_MulL ( Bool syned, Bool hi32, Bool sz32, HReg, HReg, HReg ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 1094 | extern PPCInstr* PPCInstr_Div ( Bool extended, Bool syned, Bool sz32, HReg dst, HReg srcL, HReg srcR ); |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 1095 | extern PPCInstr* PPCInstr_Call ( PPCCondCode, Addr64, UInt, RetLoc ); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1096 | extern PPCInstr* PPCInstr_XDirect ( Addr64 dstGA, PPCAMode* amCIA, |
| 1097 | PPCCondCode cond, Bool toFastEP ); |
| 1098 | extern PPCInstr* PPCInstr_XIndir ( HReg dstGA, PPCAMode* amCIA, |
| 1099 | PPCCondCode cond ); |
| 1100 | extern PPCInstr* PPCInstr_XAssisted ( HReg dstGA, PPCAMode* amCIA, |
| 1101 | PPCCondCode cond, IRJumpKind jk ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1102 | extern PPCInstr* PPCInstr_CMov ( PPCCondCode, HReg dst, PPCRI* src ); |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 1103 | extern PPCInstr* PPCInstr_Load ( UChar sz, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1104 | HReg dst, PPCAMode* src, Bool mode64 ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1105 | extern PPCInstr* PPCInstr_LoadL ( UChar sz, |
| 1106 | HReg dst, HReg src, Bool mode64 ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1107 | extern PPCInstr* PPCInstr_Store ( UChar sz, PPCAMode* dst, |
| 1108 | HReg src, Bool mode64 ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1109 | extern PPCInstr* PPCInstr_StoreC ( UChar sz, HReg dst, HReg src, |
| 1110 | Bool mode64 ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1111 | extern PPCInstr* PPCInstr_Set ( PPCCondCode cond, HReg dst ); |
| 1112 | extern PPCInstr* PPCInstr_MfCR ( HReg dst ); |
| 1113 | extern PPCInstr* PPCInstr_MFence ( void ); |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 1114 | |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 1115 | extern PPCInstr* PPCInstr_Fp128Unary ( PPCFpOp op, HReg dst, HReg src ); |
| 1116 | extern PPCInstr* PPCInstr_Fp128Binary ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR ); |
| 1117 | extern PPCInstr* PPCInstr_Fp128Trinary ( PPCFpOp op, HReg dst, HReg srcL, |
| 1118 | HReg srcR); |
| 1119 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1120 | extern PPCInstr* PPCInstr_FpUnary ( PPCFpOp op, HReg dst, HReg src ); |
| 1121 | extern PPCInstr* PPCInstr_FpBinary ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR ); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 1122 | extern PPCInstr* PPCInstr_FpMulAcc ( PPCFpOp op, HReg dst, HReg srcML, |
| 1123 | HReg srcMR, HReg srcAcc ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1124 | extern PPCInstr* PPCInstr_FpLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* ); |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 1125 | extern PPCInstr* PPCInstr_FpSTFIW ( HReg addr, HReg data ); |
| 1126 | extern PPCInstr* PPCInstr_FpRSP ( HReg dst, HReg src ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1127 | extern PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32, Bool syned, |
| 1128 | Bool dst64, HReg dst, HReg src ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1129 | extern PPCInstr* PPCInstr_FpCMov ( PPCCondCode, HReg dst, HReg src ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1130 | extern PPCInstr* PPCInstr_FpLdFPSCR ( HReg src, Bool dfp_rm ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1131 | extern PPCInstr* PPCInstr_FpCmp ( HReg dst, HReg srcL, HReg srcR ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1132 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1133 | extern PPCInstr* PPCInstr_RdWrLR ( Bool wrLR, HReg gpr ); |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 1134 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1135 | extern PPCInstr* PPCInstr_AvLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* ); |
| 1136 | extern PPCInstr* PPCInstr_AvUnary ( PPCAvOp op, HReg dst, HReg src ); |
| 1137 | extern PPCInstr* PPCInstr_AvBinary ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 1138 | extern PPCInstr* PPCInstr_AvBinaryInt( PPCAvOp op, HReg dst, HReg src, PPCRI* val ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1139 | extern PPCInstr* PPCInstr_AvBin8x16 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
| 1140 | extern PPCInstr* PPCInstr_AvBin16x8 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
| 1141 | extern PPCInstr* PPCInstr_AvBin32x4 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 1142 | extern PPCInstr* PPCInstr_AvBin64x2 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
sewardj | e522d4b | 2011-04-26 21:36:09 +0000 | [diff] [blame] | 1143 | extern PPCInstr* PPCInstr_AvBin32Fx4 ( PPCAvFpOp op, HReg dst, HReg srcL, HReg srcR ); |
| 1144 | extern PPCInstr* PPCInstr_AvUn32Fx4 ( PPCAvFpOp op, HReg dst, HReg src ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1145 | extern PPCInstr* PPCInstr_AvPerm ( HReg dst, HReg srcL, HReg srcR, HReg ctl ); |
| 1146 | extern PPCInstr* PPCInstr_AvSel ( HReg ctl, HReg dst, HReg srcL, HReg srcR ); |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 1147 | extern PPCInstr* PPCInstr_AvSh ( Bool shLeft, HReg dst, PPCAMode* am_addr ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1148 | extern PPCInstr* PPCInstr_AvShlDbl ( UChar shift, HReg dst, HReg srcL, HReg srcR ); |
| 1149 | extern PPCInstr* PPCInstr_AvSplat ( UChar sz, HReg dst, PPCVI5s* src ); |
| 1150 | extern PPCInstr* PPCInstr_AvCMov ( PPCCondCode, HReg dst, HReg src ); |
| 1151 | extern PPCInstr* PPCInstr_AvLdVSCR ( HReg src ); |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 1152 | extern PPCInstr* PPCInstr_AvCipherV128Unary ( PPCAvOp op, HReg dst, |
| 1153 | HReg srcR ); |
| 1154 | extern PPCInstr* PPCInstr_AvCipherV128Binary ( PPCAvOp op, HReg dst, |
| 1155 | HReg srcL, HReg srcR ); |
| 1156 | extern PPCInstr* PPCInstr_AvHashV128Binary ( PPCAvOp op, HReg dst, |
| 1157 | HReg src, PPCRI* s_field ); |
Elliott Hughes | a0664b9 | 2017-04-18 17:46:52 -0700 | [diff] [blame^] | 1158 | extern PPCInstr* PPCInstr_AvBCDV128Binary ( PPCAvOp op, HReg dst, |
| 1159 | HReg src1, HReg src2 ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1160 | extern PPCInstr* PPCInstr_Dfp64Unary ( PPCFpOp op, HReg dst, HReg src ); |
| 1161 | extern PPCInstr* PPCInstr_Dfp64Binary ( PPCFpOp op, HReg dst, HReg srcL, |
| 1162 | HReg srcR ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1163 | extern PPCInstr* PPCInstr_DfpShift ( PPCFpOp op, HReg dst, HReg src, |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1164 | PPCRI* shift ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1165 | extern PPCInstr* PPCInstr_Dfp128Unary ( PPCFpOp op, HReg dst_hi, HReg dst_lo, |
| 1166 | HReg srcR_hi, HReg srcR_lo ); |
| 1167 | extern PPCInstr* PPCInstr_Dfp128Binary ( PPCFpOp op, HReg dst_hi, HReg dst_lo, |
| 1168 | HReg srcR_hi, HReg srcR_lo ); |
| 1169 | extern PPCInstr* PPCInstr_DfpShift128 ( PPCFpOp op, HReg dst_hi, HReg src_hi, |
| 1170 | HReg dst_lo, HReg src_lo, |
| 1171 | PPCRI* shift ); |
| 1172 | extern PPCInstr* PPCInstr_DfpD128toD64 ( PPCFpOp op, HReg dst, |
| 1173 | HReg dst_lo, HReg src_lo); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1174 | extern PPCInstr* PPCInstr_DfpI64StoD128 ( PPCFpOp op, HReg dst_hi, |
| 1175 | HReg dst_lo, HReg src); |
| 1176 | extern PPCInstr* PPCInstr_DfpRound ( HReg dst, HReg src, PPCRI* r_rmc ); |
| 1177 | extern PPCInstr* PPCInstr_DfpRound128 ( HReg dst_hi, HReg dst_lo, HReg src_hi, |
| 1178 | HReg src_lo, PPCRI* r_rmc ); |
florian | a7b0d10 | 2012-06-15 20:55:43 +0000 | [diff] [blame] | 1179 | extern PPCInstr* PPCInstr_DfpQuantize ( PPCFpOp op, HReg dst, HReg srcL, |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1180 | HReg srcR, PPCRI* rmc ); |
florian | a7b0d10 | 2012-06-15 20:55:43 +0000 | [diff] [blame] | 1181 | extern PPCInstr* PPCInstr_DfpQuantize128 ( PPCFpOp op, HReg dst_hi, |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1182 | HReg dst_lo, |
| 1183 | HReg src_hi, |
| 1184 | HReg src_lo, PPCRI* rmc ); |
| 1185 | extern PPCInstr* PPCInstr_ExtractExpD128 ( PPCFpOp op, HReg dst, |
| 1186 | HReg src_hi, HReg src_lo ); |
| 1187 | extern PPCInstr* PPCInstr_InsertExpD128 ( PPCFpOp op, HReg dst_hi, |
| 1188 | HReg dst_lo, HReg srcL, |
| 1189 | HReg srcR_hi, HReg srcR_lo ); |
| 1190 | extern PPCInstr* PPCInstr_Dfp64Cmp ( HReg dst, HReg srcL, HReg srcR ); |
| 1191 | extern PPCInstr* PPCInstr_Dfp128Cmp ( HReg dst, HReg srcL_hi, HReg srcL_lo, |
| 1192 | HReg srcR_hi, HReg srcR_lo ); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1193 | extern PPCInstr* PPCInstr_EvCheck ( PPCAMode* amCounter, |
| 1194 | PPCAMode* amFailAddr ); |
| 1195 | extern PPCInstr* PPCInstr_ProfInc ( void ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1196 | |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 1197 | extern void ppPPCInstr(const PPCInstr*, Bool mode64); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1198 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1199 | |
| 1200 | /* Some functions that insulate the register allocator from details |
| 1201 | of the underlying instruction set. */ |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 1202 | extern void getRegUsage_PPCInstr ( HRegUsage*, const PPCInstr*, Bool mode64 ); |
| 1203 | extern void mapRegs_PPCInstr ( HRegRemap*, PPCInstr* , Bool mode64); |
| 1204 | extern Bool isMove_PPCInstr ( const PPCInstr*, HReg*, HReg* ); |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 1205 | extern Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 1206 | UChar* buf, Int nbuf, const PPCInstr* i, |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 1207 | Bool mode64, |
| 1208 | VexEndness endness_host, |
| 1209 | const void* disp_cp_chain_me_to_slowEP, |
| 1210 | const void* disp_cp_chain_me_to_fastEP, |
| 1211 | const void* disp_cp_xindir, |
| 1212 | const void* disp_cp_xassisted ); |
sewardj | 2a0cc85 | 2010-01-02 13:23:54 +0000 | [diff] [blame] | 1213 | |
| 1214 | extern void genSpill_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, |
| 1215 | HReg rreg, Int offsetB, Bool mode64 ); |
| 1216 | extern void genReload_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, |
| 1217 | HReg rreg, Int offsetB, Bool mode64 ); |
| 1218 | |
sewardj | a5b5022 | 2015-03-26 07:18:32 +0000 | [diff] [blame] | 1219 | extern const RRegUniverse* getRRegUniverse_PPC ( Bool mode64 ); |
| 1220 | |
florian | cacba8e | 2014-12-15 18:58:07 +0000 | [diff] [blame] | 1221 | extern HInstrArray* iselSB_PPC ( const IRSB*, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1222 | VexArch, |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 1223 | const VexArchInfo*, |
| 1224 | const VexAbiInfo*, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1225 | Int offs_Host_EvC_Counter, |
| 1226 | Int offs_Host_EvC_FailAddr, |
| 1227 | Bool chainingAllowed, |
| 1228 | Bool addProfInc, |
florian | dcd6d23 | 2015-01-02 17:32:21 +0000 | [diff] [blame] | 1229 | Addr max_ga ); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1230 | |
| 1231 | /* How big is an event check? This is kind of a kludge because it |
| 1232 | depends on the offsets of host_EvC_FAILADDR and |
| 1233 | host_EvC_COUNTER. */ |
florian | 7ce2cc8 | 2015-01-10 16:10:58 +0000 | [diff] [blame] | 1234 | extern Int evCheckSzB_PPC (void); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1235 | |
| 1236 | /* Perform a chaining and unchaining of an XDirect jump. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1237 | extern VexInvalRange chainXDirect_PPC ( VexEndness endness_host, |
| 1238 | void* place_to_chain, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1239 | const void* disp_cp_chain_me_EXPECTED, |
| 1240 | const void* place_to_jump_to, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1241 | Bool mode64 ); |
| 1242 | |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1243 | extern VexInvalRange unchainXDirect_PPC ( VexEndness endness_host, |
| 1244 | void* place_to_unchain, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1245 | const void* place_to_jump_to_EXPECTED, |
| 1246 | const void* disp_cp_chain_me, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1247 | Bool mode64 ); |
| 1248 | |
| 1249 | /* Patch the counter location into an existing ProfInc point. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1250 | extern VexInvalRange patchProfInc_PPC ( VexEndness endness_host, |
| 1251 | void* place_to_patch, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1252 | const ULong* location_of_counter, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1253 | Bool mode64 ); |
| 1254 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1255 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 1256 | #endif /* ndef __VEX_HOST_PPC_DEFS_H */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1257 | |
| 1258 | /*---------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 1259 | /*--- end host_ppc_defs.h ---*/ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1260 | /*---------------------------------------------------------------*/ |