cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
| 3 | /*--- ---*/ |
cerion | d0eae2d | 2005-12-23 11:43:01 +0000 | [diff] [blame] | 4 | /*--- This file (host-ppc/hdefs.h) is ---*/ |
sewardj | dbcfae7 | 2005-08-02 11:14:04 +0000 | [diff] [blame] | 5 | /*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 6 | /*--- ---*/ |
| 7 | /*---------------------------------------------------------------*/ |
| 8 | |
| 9 | /* |
| 10 | This file is part of LibVEX, a library for dynamic binary |
| 11 | instrumentation and translation. |
| 12 | |
sewardj | a33e9a4 | 2006-06-05 23:13:19 +0000 | [diff] [blame] | 13 | Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 14 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 15 | This library is made available under a dual licensing scheme. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 16 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 17 | If you link LibVEX against other code all of which is itself |
| 18 | licensed under the GNU General Public License, version 2 dated June |
| 19 | 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL |
| 20 | v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL |
| 21 | is missing, you can obtain a copy of the GPL v2 from the Free |
| 22 | Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 23 | 02110-1301, USA. |
| 24 | |
| 25 | For any other uses of LibVEX, you must first obtain a commercial |
| 26 | license from OpenWorks LLP. Please contact info@open-works.co.uk |
| 27 | for information about commercial licensing. |
| 28 | |
| 29 | This software is provided by OpenWorks LLP "as is" and any express |
| 30 | or implied warranties, including, but not limited to, the implied |
| 31 | warranties of merchantability and fitness for a particular purpose |
| 32 | are disclaimed. In no event shall OpenWorks LLP be liable for any |
| 33 | direct, indirect, incidental, special, exemplary, or consequential |
| 34 | damages (including, but not limited to, procurement of substitute |
| 35 | goods or services; loss of use, data, or profits; or business |
| 36 | interruption) however caused and on any theory of liability, |
| 37 | whether in contract, strict liability, or tort (including |
| 38 | negligence or otherwise) arising in any way out of the use of this |
| 39 | software, even if advised of the possibility of such damage. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 40 | |
| 41 | Neither the names of the U.S. Department of Energy nor the |
| 42 | University of California nor the names of its contributors may be |
| 43 | used to endorse or promote products derived from this software |
| 44 | without prior written permission. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 45 | */ |
| 46 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 47 | #ifndef __LIBVEX_HOST_PPC_HDEFS_H |
| 48 | #define __LIBVEX_HOST_PPC_HDEFS_H |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 49 | |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 50 | /* Num registers used for function calls */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 51 | #define PPC_N_REGPARMS 8 |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 52 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 53 | |
| 54 | /* --------- Registers. --------- */ |
| 55 | |
| 56 | /* The usual HReg abstraction. There are 32 real int regs, |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 57 | 32 real float regs, and 32 real vector regs. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 58 | */ |
| 59 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 60 | extern void ppHRegPPC ( HReg ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 61 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 62 | extern HReg hregPPC_GPR0 ( Bool mode64 ); // scratch reg / zero reg |
| 63 | extern HReg hregPPC_GPR1 ( Bool mode64 ); // Stack Frame Pointer |
| 64 | extern HReg hregPPC_GPR2 ( Bool mode64 ); // not used: TOC pointer |
| 65 | extern HReg hregPPC_GPR3 ( Bool mode64 ); |
| 66 | extern HReg hregPPC_GPR4 ( Bool mode64 ); |
| 67 | extern HReg hregPPC_GPR5 ( Bool mode64 ); |
| 68 | extern HReg hregPPC_GPR6 ( Bool mode64 ); |
| 69 | extern HReg hregPPC_GPR7 ( Bool mode64 ); |
| 70 | extern HReg hregPPC_GPR8 ( Bool mode64 ); |
| 71 | extern HReg hregPPC_GPR9 ( Bool mode64 ); |
| 72 | extern HReg hregPPC_GPR10 ( Bool mode64 ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 73 | extern HReg hregPPC_GPR11 ( Bool mode64 ); |
| 74 | extern HReg hregPPC_GPR12 ( Bool mode64 ); |
| 75 | extern HReg hregPPC_GPR13 ( Bool mode64 ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 76 | extern HReg hregPPC_GPR14 ( Bool mode64 ); |
| 77 | extern HReg hregPPC_GPR15 ( Bool mode64 ); |
| 78 | extern HReg hregPPC_GPR16 ( Bool mode64 ); |
| 79 | extern HReg hregPPC_GPR17 ( Bool mode64 ); |
| 80 | extern HReg hregPPC_GPR18 ( Bool mode64 ); |
| 81 | extern HReg hregPPC_GPR19 ( Bool mode64 ); |
| 82 | extern HReg hregPPC_GPR20 ( Bool mode64 ); |
| 83 | extern HReg hregPPC_GPR21 ( Bool mode64 ); |
| 84 | extern HReg hregPPC_GPR22 ( Bool mode64 ); |
| 85 | extern HReg hregPPC_GPR23 ( Bool mode64 ); |
| 86 | extern HReg hregPPC_GPR24 ( Bool mode64 ); |
| 87 | extern HReg hregPPC_GPR25 ( Bool mode64 ); |
| 88 | extern HReg hregPPC_GPR26 ( Bool mode64 ); |
| 89 | extern HReg hregPPC_GPR27 ( Bool mode64 ); |
| 90 | extern HReg hregPPC_GPR28 ( Bool mode64 ); |
sewardj | b8a8dba | 2005-12-15 21:33:50 +0000 | [diff] [blame] | 91 | extern HReg hregPPC_GPR29 ( Bool mode64 ); // reserved for dispatcher |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 92 | extern HReg hregPPC_GPR30 ( Bool mode64 ); // used as VMX spill temp |
sewardj | b8a8dba | 2005-12-15 21:33:50 +0000 | [diff] [blame] | 93 | extern HReg hregPPC_GPR31 ( Bool mode64 ); // GuestStatePtr (callee-saved) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 94 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 95 | extern HReg hregPPC_FPR0 ( void ); |
| 96 | extern HReg hregPPC_FPR1 ( void ); |
| 97 | extern HReg hregPPC_FPR2 ( void ); |
| 98 | extern HReg hregPPC_FPR3 ( void ); |
| 99 | extern HReg hregPPC_FPR4 ( void ); |
| 100 | extern HReg hregPPC_FPR5 ( void ); |
| 101 | extern HReg hregPPC_FPR6 ( void ); |
| 102 | extern HReg hregPPC_FPR7 ( void ); |
| 103 | extern HReg hregPPC_FPR8 ( void ); |
| 104 | extern HReg hregPPC_FPR9 ( void ); |
| 105 | extern HReg hregPPC_FPR10 ( void ); |
| 106 | extern HReg hregPPC_FPR11 ( void ); |
| 107 | extern HReg hregPPC_FPR12 ( void ); |
| 108 | extern HReg hregPPC_FPR13 ( void ); |
| 109 | extern HReg hregPPC_FPR14 ( void ); |
| 110 | extern HReg hregPPC_FPR15 ( void ); |
| 111 | extern HReg hregPPC_FPR16 ( void ); |
| 112 | extern HReg hregPPC_FPR17 ( void ); |
| 113 | extern HReg hregPPC_FPR18 ( void ); |
| 114 | extern HReg hregPPC_FPR19 ( void ); |
| 115 | extern HReg hregPPC_FPR20 ( void ); |
| 116 | extern HReg hregPPC_FPR21 ( void ); |
| 117 | extern HReg hregPPC_FPR22 ( void ); |
| 118 | extern HReg hregPPC_FPR23 ( void ); |
| 119 | extern HReg hregPPC_FPR24 ( void ); |
| 120 | extern HReg hregPPC_FPR25 ( void ); |
| 121 | extern HReg hregPPC_FPR26 ( void ); |
| 122 | extern HReg hregPPC_FPR27 ( void ); |
| 123 | extern HReg hregPPC_FPR28 ( void ); |
| 124 | extern HReg hregPPC_FPR29 ( void ); |
| 125 | extern HReg hregPPC_FPR30 ( void ); |
| 126 | extern HReg hregPPC_FPR31 ( void ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 127 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 128 | extern HReg hregPPC_VR0 ( void ); |
| 129 | extern HReg hregPPC_VR1 ( void ); |
| 130 | extern HReg hregPPC_VR2 ( void ); |
| 131 | extern HReg hregPPC_VR3 ( void ); |
| 132 | extern HReg hregPPC_VR4 ( void ); |
| 133 | extern HReg hregPPC_VR5 ( void ); |
| 134 | extern HReg hregPPC_VR6 ( void ); |
| 135 | extern HReg hregPPC_VR7 ( void ); |
| 136 | extern HReg hregPPC_VR8 ( void ); |
| 137 | extern HReg hregPPC_VR9 ( void ); |
| 138 | extern HReg hregPPC_VR10 ( void ); |
| 139 | extern HReg hregPPC_VR11 ( void ); |
| 140 | extern HReg hregPPC_VR12 ( void ); |
| 141 | extern HReg hregPPC_VR13 ( void ); |
| 142 | extern HReg hregPPC_VR14 ( void ); |
| 143 | extern HReg hregPPC_VR15 ( void ); |
| 144 | extern HReg hregPPC_VR16 ( void ); |
| 145 | extern HReg hregPPC_VR17 ( void ); |
| 146 | extern HReg hregPPC_VR18 ( void ); |
| 147 | extern HReg hregPPC_VR19 ( void ); |
| 148 | extern HReg hregPPC_VR20 ( void ); |
| 149 | extern HReg hregPPC_VR21 ( void ); |
| 150 | extern HReg hregPPC_VR22 ( void ); |
| 151 | extern HReg hregPPC_VR23 ( void ); |
| 152 | extern HReg hregPPC_VR24 ( void ); |
| 153 | extern HReg hregPPC_VR25 ( void ); |
| 154 | extern HReg hregPPC_VR26 ( void ); |
| 155 | extern HReg hregPPC_VR27 ( void ); |
| 156 | extern HReg hregPPC_VR28 ( void ); |
| 157 | extern HReg hregPPC_VR29 ( void ); |
| 158 | extern HReg hregPPC_VR30 ( void ); |
| 159 | extern HReg hregPPC_VR31 ( void ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 160 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 161 | #define StackFramePtr(_mode64) hregPPC_GPR1(_mode64) |
| 162 | #define GuestStatePtr(_mode64) hregPPC_GPR31(_mode64) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 163 | |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 164 | |
| 165 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 166 | /* --------- Condition codes --------- */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 167 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 168 | /* This gives names from bitfields in CR; hence it names BI numbers */ |
| 169 | /* Using IBM/hardware indexing convention */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 170 | typedef |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 171 | enum { |
| 172 | // CR7, which we use for integer compares |
| 173 | Pcf_7LT = 28, /* neg | lt */ |
| 174 | Pcf_7GT = 29, /* pos | gt */ |
| 175 | Pcf_7EQ = 30, /* zero | equal */ |
| 176 | Pcf_7SO = 31 /* summary overflow */ |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 177 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 178 | PPCCondFlag; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 179 | |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 180 | typedef |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 181 | enum { /* Maps bc bitfield BO */ |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 182 | Pct_FALSE = 0x4, |
| 183 | Pct_TRUE = 0xC, |
| 184 | Pct_ALWAYS = 0x14 |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 185 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 186 | PPCCondTest; |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 187 | |
| 188 | typedef |
| 189 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 190 | PPCCondFlag flag; |
| 191 | PPCCondTest test; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 192 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 193 | PPCCondCode; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 194 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 195 | extern HChar* showPPCCondCode ( PPCCondCode ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 196 | |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 197 | /* constructor */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 198 | extern PPCCondCode mk_PPCCondCode ( PPCCondTest, PPCCondFlag ); |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 199 | |
| 200 | /* false->true, true->false */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 201 | extern PPCCondTest invertCondTest ( PPCCondTest ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 202 | |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 203 | |
| 204 | |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 205 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 206 | /* --------- Memory address expressions (amodes). --------- */ |
| 207 | |
| 208 | typedef |
| 209 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 210 | Pam_IR=1, /* Immediate (signed 16-bit) + Reg */ |
| 211 | Pam_RR=2 /* Reg1 + Reg2 */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 212 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 213 | PPCAModeTag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 214 | |
| 215 | typedef |
| 216 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 217 | PPCAModeTag tag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 218 | union { |
| 219 | struct { |
| 220 | HReg base; |
sewardj | a5f957d | 2005-07-02 01:29:32 +0000 | [diff] [blame] | 221 | Int index; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 222 | } IR; |
| 223 | struct { |
| 224 | HReg base; |
| 225 | HReg index; |
| 226 | } RR; |
| 227 | } Pam; |
| 228 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 229 | PPCAMode; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 230 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 231 | extern PPCAMode* PPCAMode_IR ( Int, HReg ); |
| 232 | extern PPCAMode* PPCAMode_RR ( HReg, HReg ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 233 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 234 | extern PPCAMode* dopyPPCAMode ( PPCAMode* ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 235 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 236 | extern void ppPPCAMode ( PPCAMode* ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 237 | |
| 238 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 239 | /* --------- Operand, which can be a reg or a u16/s16. --------- */ |
| 240 | /* ("RH" == "Register or Halfword immediate") */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 241 | typedef |
| 242 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 243 | Prh_Imm=3, |
| 244 | Prh_Reg=4 |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 245 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 246 | PPCRHTag; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 247 | |
| 248 | typedef |
| 249 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 250 | PPCRHTag tag; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 251 | union { |
| 252 | struct { |
| 253 | Bool syned; |
| 254 | UShort imm16; |
| 255 | } Imm; |
| 256 | struct { |
| 257 | HReg reg; |
| 258 | } Reg; |
| 259 | } |
| 260 | Prh; |
| 261 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 262 | PPCRH; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 263 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 264 | extern PPCRH* PPCRH_Imm ( Bool, UShort ); |
| 265 | extern PPCRH* PPCRH_Reg ( HReg ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 266 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 267 | extern void ppPPCRH ( PPCRH* ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 268 | |
| 269 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 270 | /* --------- Operand, which can be a reg or a u32/64. --------- */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 271 | |
| 272 | typedef |
| 273 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 274 | Pri_Imm=5, |
| 275 | Pri_Reg=6 |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 276 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 277 | PPCRITag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 278 | |
| 279 | typedef |
| 280 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 281 | PPCRITag tag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 282 | union { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 283 | ULong Imm; |
| 284 | HReg Reg; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 285 | } |
| 286 | Pri; |
| 287 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 288 | PPCRI; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 289 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 290 | extern PPCRI* PPCRI_Imm ( ULong ); |
| 291 | extern PPCRI* PPCRI_Reg ( HReg ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 292 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 293 | extern void ppPPCRI ( PPCRI* ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 294 | |
| 295 | |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 296 | /* --------- Operand, which can be a vector reg or a s6. --------- */ |
| 297 | /* ("VI" == "Vector Register or Immediate") */ |
| 298 | typedef |
| 299 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 300 | Pvi_Imm=7, |
| 301 | Pvi_Reg=8 |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 302 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 303 | PPCVI5sTag; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 304 | |
| 305 | typedef |
| 306 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 307 | PPCVI5sTag tag; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 308 | union { |
| 309 | Char Imm5s; |
| 310 | HReg Reg; |
| 311 | } |
| 312 | Pvi; |
| 313 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 314 | PPCVI5s; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 315 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 316 | extern PPCVI5s* PPCVI5s_Imm ( Char ); |
| 317 | extern PPCVI5s* PPCVI5s_Reg ( HReg ); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 318 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 319 | extern void ppPPCVI5s ( PPCVI5s* ); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 320 | |
| 321 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 322 | /* --------- Instructions. --------- */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 323 | |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 324 | /* --------- */ |
| 325 | typedef |
| 326 | enum { |
| 327 | Pun_NEG, |
cerion | e13bb31 | 2005-02-10 19:51:03 +0000 | [diff] [blame] | 328 | Pun_NOT, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 329 | Pun_CLZ32, |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 330 | Pun_CLZ64, |
| 331 | Pun_EXTSW |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 332 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 333 | PPCUnaryOp; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 334 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 335 | extern HChar* showPPCUnaryOp ( PPCUnaryOp ); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 336 | |
| 337 | |
| 338 | /* --------- */ |
| 339 | typedef |
| 340 | enum { |
| 341 | Palu_INVALID, |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 342 | Palu_ADD, Palu_SUB, |
| 343 | Palu_AND, Palu_OR, Palu_XOR, |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 344 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 345 | PPCAluOp; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 346 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 347 | extern |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 348 | HChar* showPPCAluOp ( PPCAluOp, |
| 349 | Bool /* is the 2nd operand an immediate? */); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 350 | |
| 351 | |
| 352 | /* --------- */ |
| 353 | typedef |
| 354 | enum { |
| 355 | Pshft_INVALID, |
| 356 | Pshft_SHL, Pshft_SHR, Pshft_SAR, |
| 357 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 358 | PPCShftOp; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 359 | |
| 360 | extern |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 361 | HChar* showPPCShftOp ( PPCShftOp, |
| 362 | Bool /* is the 2nd operand an immediate? */, |
| 363 | Bool /* is this a 32bit or 64bit op? */ ); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 364 | |
| 365 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 366 | /* --------- */ |
| 367 | typedef |
| 368 | enum { |
| 369 | Pfp_INVALID, |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 370 | |
| 371 | /* Ternary */ |
| 372 | Pfp_MADDD, Pfp_MSUBD, |
| 373 | Pfp_MADDS, Pfp_MSUBS, |
| 374 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 375 | /* Binary */ |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 376 | Pfp_ADDD, Pfp_SUBD, Pfp_MULD, Pfp_DIVD, |
| 377 | Pfp_ADDS, Pfp_SUBS, Pfp_MULS, Pfp_DIVS, |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 378 | |
| 379 | /* Unary */ |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 380 | Pfp_SQRT, Pfp_ABS, Pfp_NEG, Pfp_MOV, Pfp_RES, Pfp_RSQRTE |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 381 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 382 | PPCFpOp; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 383 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 384 | extern HChar* showPPCFpOp ( PPCFpOp ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 385 | |
| 386 | |
| 387 | /* --------- */ |
| 388 | typedef |
| 389 | enum { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 390 | Pav_INVALID, |
| 391 | |
| 392 | /* Integer Unary */ |
| 393 | Pav_MOV, /* Mov */ |
| 394 | Pav_NOT, /* Bitwise */ |
| 395 | Pav_UNPCKH8S, Pav_UNPCKH16S, /* Unpack */ |
| 396 | Pav_UNPCKL8S, Pav_UNPCKL16S, |
| 397 | Pav_UNPCKHPIX, Pav_UNPCKLPIX, |
| 398 | |
| 399 | /* Integer Binary */ |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 400 | Pav_AND, Pav_OR, Pav_XOR, /* Bitwise */ |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 401 | Pav_ADDU, Pav_QADDU, Pav_QADDS, |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 402 | Pav_SUBU, Pav_QSUBU, Pav_QSUBS, |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 403 | Pav_OMULU, Pav_OMULS, Pav_EMULU, Pav_EMULS, |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 404 | Pav_AVGU, Pav_AVGS, |
| 405 | Pav_MAXU, Pav_MAXS, |
| 406 | Pav_MINU, Pav_MINS, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 407 | |
| 408 | /* Compare (always affects CR field 6) */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 409 | Pav_CMPEQU, Pav_CMPGTU, Pav_CMPGTS, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 410 | |
| 411 | /* Shift */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 412 | Pav_SHL, Pav_SHR, Pav_SAR, Pav_ROTL, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 413 | |
| 414 | /* Pack */ |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 415 | Pav_PACKUU, Pav_QPACKUU, Pav_QPACKSU, Pav_QPACKSS, |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 416 | Pav_PACKPXL, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 417 | |
| 418 | /* Merge */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 419 | Pav_MRGHI, Pav_MRGLO, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 420 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 421 | PPCAvOp; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 422 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 423 | extern HChar* showPPCAvOp ( PPCAvOp ); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 424 | |
| 425 | |
| 426 | /* --------- */ |
| 427 | typedef |
| 428 | enum { |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 429 | Pavfp_INVALID, |
| 430 | |
| 431 | /* Floating point binary */ |
| 432 | Pavfp_ADDF, Pavfp_SUBF, Pavfp_MULF, |
| 433 | Pavfp_MAXF, Pavfp_MINF, |
| 434 | Pavfp_CMPEQF, Pavfp_CMPGTF, Pavfp_CMPGEF, |
| 435 | |
| 436 | /* Floating point unary */ |
| 437 | Pavfp_RCPF, Pavfp_RSQRTF, |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 438 | Pavfp_CVTU2F, Pavfp_CVTS2F, Pavfp_QCVTF2U, Pavfp_QCVTF2S, |
| 439 | Pavfp_ROUNDM, Pavfp_ROUNDP, Pavfp_ROUNDN, Pavfp_ROUNDZ, |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 440 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 441 | PPCAvFpOp; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 442 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 443 | extern HChar* showPPCAvFpOp ( PPCAvFpOp ); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 444 | |
| 445 | |
| 446 | /* --------- */ |
| 447 | typedef |
| 448 | enum { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 449 | Pin_LI, /* load word (32/64-bit) immediate (fake insn) */ |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 450 | Pin_Alu, /* word add/sub/and/or/xor */ |
| 451 | Pin_Shft, /* word shl/shr/sar */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 452 | Pin_AddSubC, /* add/sub with read/write carry */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 453 | Pin_Cmp, /* word compare */ |
| 454 | Pin_Unary, /* not, neg, clz */ |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 455 | Pin_MulL, /* widening multiply */ |
| 456 | Pin_Div, /* div */ |
| 457 | Pin_Call, /* call to address in register */ |
| 458 | Pin_Goto, /* conditional/unconditional jmp to dst */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 459 | Pin_CMov, /* conditional move */ |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 460 | Pin_Load, /* zero-extending load a 8|16|32|64 bit value from mem */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 461 | Pin_Store, /* store a 8|16|32|64 bit value to mem */ |
| 462 | Pin_Set, /* convert condition code to value 0 or 1 */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 463 | Pin_MfCR, /* move from condition register to GPR */ |
| 464 | Pin_MFence, /* mem fence */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 465 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 466 | Pin_FpUnary, /* FP unary op */ |
| 467 | Pin_FpBinary, /* FP binary op */ |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 468 | Pin_FpMulAcc, /* FP multipy-accumulate style op */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 469 | Pin_FpLdSt, /* FP load/store */ |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 470 | Pin_FpSTFIW, /* stfiwx */ |
| 471 | Pin_FpRSP, /* FP round IEEE754 double to IEEE754 single */ |
| 472 | Pin_FpCftI, /* fcfid/fctid/fctiw */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 473 | Pin_FpCMov, /* FP floating point conditional move */ |
| 474 | Pin_FpLdFPSCR, /* mtfsf */ |
| 475 | Pin_FpCmp, /* FP compare, generating value into int reg */ |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 476 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 477 | Pin_RdWrLR, /* Read/Write Link Register */ |
| 478 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 479 | Pin_AvLdSt, /* AV load/store (kludging for AMode_IR) */ |
| 480 | Pin_AvUnary, /* AV unary general reg=>reg */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 481 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 482 | Pin_AvBinary, /* AV binary general reg,reg=>reg */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 483 | Pin_AvBin8x16, /* AV binary, 8x4 */ |
| 484 | Pin_AvBin16x8, /* AV binary, 16x4 */ |
| 485 | Pin_AvBin32x4, /* AV binary, 32x4 */ |
| 486 | |
| 487 | Pin_AvBin32Fx4, /* AV FP binary, 32Fx4 */ |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 488 | Pin_AvUn32Fx4, /* AV FP unary, 32Fx4 */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 489 | |
| 490 | Pin_AvPerm, /* AV permute (shuffle) */ |
| 491 | Pin_AvSel, /* AV select */ |
| 492 | Pin_AvShlDbl, /* AV shift-left double by imm */ |
| 493 | Pin_AvSplat, /* One elem repeated throughout dst */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 494 | Pin_AvLdVSCR, /* mtvscr */ |
| 495 | Pin_AvCMov /* AV conditional move */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 496 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 497 | PPCInstrTag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 498 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 499 | /* Destinations are on the LEFT (first operand) */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 500 | |
| 501 | typedef |
| 502 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 503 | PPCInstrTag tag; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 504 | union { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 505 | /* Get a 32/64-bit literal into a register. |
| 506 | May turn into a number of real insns. */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 507 | struct { |
| 508 | HReg dst; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 509 | ULong imm64; |
| 510 | } LI; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 511 | /* Integer add/sub/and/or/xor. Limitations: |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 512 | - For add, the immediate, if it exists, is a signed 16. |
| 513 | - For sub, the immediate, if it exists, is a signed 16 |
| 514 | which may not be -32768, since no such instruction |
| 515 | exists, and so we have to emit addi with +32768, but |
| 516 | that is not possible. |
| 517 | - For and/or/xor, the immediate, if it exists, |
| 518 | is an unsigned 16. |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 519 | */ |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 520 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 521 | PPCAluOp op; |
| 522 | HReg dst; |
| 523 | HReg srcL; |
| 524 | PPCRH* srcR; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 525 | } Alu; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 526 | /* Integer shl/shr/sar. |
| 527 | Limitations: the immediate, if it exists, |
| 528 | is a signed 5-bit value between 1 and 31 inclusive. |
| 529 | */ |
| 530 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 531 | PPCShftOp op; |
| 532 | Bool sz32; /* mode64 has both 32 and 64bit shft */ |
| 533 | HReg dst; |
| 534 | HReg srcL; |
| 535 | PPCRH* srcR; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 536 | } Shft; |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 537 | /* */ |
| 538 | struct { |
| 539 | Bool isAdd; /* else sub */ |
| 540 | Bool setC; /* else read carry */ |
| 541 | HReg dst; |
| 542 | HReg srcL; |
| 543 | HReg srcR; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 544 | } AddSubC; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 545 | /* If signed, the immediate, if it exists, is a signed 16, |
| 546 | else it is an unsigned 16. */ |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 547 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 548 | Bool syned; |
| 549 | Bool sz32; /* mode64 has both 32 and 64bit cmp */ |
| 550 | UInt crfD; |
| 551 | HReg srcL; |
| 552 | PPCRH* srcR; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 553 | } Cmp; |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 554 | /* Not, Neg, Clz32/64, Extsw */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 555 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 556 | PPCUnaryOp op; |
| 557 | HReg dst; |
| 558 | HReg src; |
| 559 | } Unary; |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 560 | struct { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 561 | Bool syned; /* meaningless if hi32==False */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 562 | Bool hi; /* False=>low, True=>high */ |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 563 | Bool sz32; /* mode64 has both 32 & 64bit mull */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 564 | HReg dst; |
| 565 | HReg srcL; |
| 566 | HReg srcR; |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 567 | } MulL; |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 568 | /* ppc32 div/divu instruction. */ |
cerion | c0e707e | 2005-02-10 22:35:34 +0000 | [diff] [blame] | 569 | struct { |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 570 | Bool syned; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 571 | Bool sz32; /* mode64 has both 32 & 64bit div */ |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 572 | HReg dst; |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 573 | HReg srcL; |
| 574 | HReg srcR; |
cerion | c0e707e | 2005-02-10 22:35:34 +0000 | [diff] [blame] | 575 | } Div; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 576 | /* Pseudo-insn. Call target (an absolute address), on given |
sewardj | 6a64a9f | 2005-08-21 00:48:37 +0000 | [diff] [blame] | 577 | condition (which could be Pct_ALWAYS). argiregs indicates |
| 578 | which of r3 .. r10 carries argument values for this call, |
| 579 | using a bit mask (1<<N is set if rN holds an arg, for N in |
| 580 | 3 .. 10 inclusive). */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 581 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 582 | PPCCondCode cond; |
| 583 | Addr64 target; |
| 584 | UInt argiregs; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 585 | } Call; |
| 586 | /* Pseudo-insn. Goto dst, on given condition (which could be |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 587 | Pct_ALWAYS). */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 588 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 589 | IRJumpKind jk; |
| 590 | PPCCondCode cond; |
| 591 | PPCRI* dst; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 592 | } Goto; |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 593 | /* Mov src to dst on the given condition, which may not |
cerion | 9abfcbc | 2005-02-25 11:16:58 +0000 | [diff] [blame] | 594 | be the bogus Pct_ALWAYS. */ |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 595 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 596 | PPCCondCode cond; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 597 | HReg dst; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 598 | PPCRI* src; |
| 599 | } CMov; |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 600 | /* Zero extending loads. Dst size is host word size */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 601 | struct { |
| 602 | UChar sz; /* 1|2|4|8 */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 603 | HReg dst; |
| 604 | PPCAMode* src; |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 605 | } Load; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 606 | /* 64/32/16/8 bit stores */ |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 607 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 608 | UChar sz; /* 1|2|4|8 */ |
| 609 | PPCAMode* dst; |
| 610 | HReg src; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 611 | } Store; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 612 | /* Convert a ppc condition code to value 0 or 1. */ |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 613 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 614 | PPCCondCode cond; |
| 615 | HReg dst; |
| 616 | } Set; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 617 | /* Move the entire CR to a GPR */ |
| 618 | struct { |
| 619 | HReg dst; |
| 620 | } MfCR; |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 621 | /* Mem fence. In short, an insn which flushes all preceding |
| 622 | loads and stores as much as possible before continuing. |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 623 | On PPC we emit a "sync". */ |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 624 | struct { |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 625 | } MFence; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 626 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 627 | /* PPC Floating point */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 628 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 629 | PPCFpOp op; |
| 630 | HReg dst; |
| 631 | HReg src; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 632 | } FpUnary; |
| 633 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 634 | PPCFpOp op; |
| 635 | HReg dst; |
| 636 | HReg srcL; |
| 637 | HReg srcR; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 638 | } FpBinary; |
| 639 | struct { |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 640 | PPCFpOp op; |
| 641 | HReg dst; |
| 642 | HReg srcML; |
| 643 | HReg srcMR; |
| 644 | HReg srcAcc; |
| 645 | } FpMulAcc; |
| 646 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 647 | Bool isLoad; |
| 648 | UChar sz; /* only 4 (IEEE single) or 8 (IEEE double) */ |
| 649 | HReg reg; |
| 650 | PPCAMode* addr; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 651 | } FpLdSt; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 652 | struct { |
| 653 | HReg addr; /* int reg */ |
| 654 | HReg data; /* float reg */ |
| 655 | } FpSTFIW; |
| 656 | /* Round 64-bit FP value to 32-bit FP value in an FP reg. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 657 | struct { |
| 658 | HReg src; |
| 659 | HReg dst; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 660 | } FpRSP; |
| 661 | /* fcfid/fctid/fctiw. Note there's no fcfiw so fromI==True |
| 662 | && int32==True is not allowed. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 663 | struct { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 664 | Bool fromI; /* False==F->I, True==I->F */ |
| 665 | Bool int32; /* True== I is 32, False==I is 64 */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 666 | HReg src; |
| 667 | HReg dst; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 668 | } FpCftI; |
| 669 | /* FP mov src to dst on the given condition. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 670 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 671 | PPCCondCode cond; |
| 672 | HReg dst; |
| 673 | HReg src; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 674 | } FpCMov; |
| 675 | /* Load FP Status & Control Register */ |
| 676 | struct { |
| 677 | HReg src; |
| 678 | } FpLdFPSCR; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 679 | /* Do a compare, generating result into an int register. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 680 | struct { |
| 681 | UChar crfD; |
| 682 | HReg dst; |
| 683 | HReg srcL; |
| 684 | HReg srcR; |
| 685 | } FpCmp; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 686 | |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 687 | /* Read/Write Link Register */ |
| 688 | struct { |
| 689 | Bool wrLR; |
| 690 | HReg gpr; |
| 691 | } RdWrLR; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 692 | |
| 693 | /* Simplistic AltiVec */ |
| 694 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 695 | Bool isLoad; |
| 696 | UChar sz; /* 8|16|32|128 */ |
| 697 | HReg reg; |
| 698 | PPCAMode* addr; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 699 | } AvLdSt; |
| 700 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 701 | PPCAvOp op; |
| 702 | HReg dst; |
| 703 | HReg src; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 704 | } AvUnary; |
| 705 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 706 | PPCAvOp op; |
| 707 | HReg dst; |
| 708 | HReg srcL; |
| 709 | HReg srcR; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 710 | } AvBinary; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 711 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 712 | PPCAvOp op; |
| 713 | HReg dst; |
| 714 | HReg srcL; |
| 715 | HReg srcR; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 716 | } AvBin8x16; |
| 717 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 718 | PPCAvOp op; |
| 719 | HReg dst; |
| 720 | HReg srcL; |
| 721 | HReg srcR; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 722 | } AvBin16x8; |
| 723 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 724 | PPCAvOp op; |
| 725 | HReg dst; |
| 726 | HReg srcL; |
| 727 | HReg srcR; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 728 | } AvBin32x4; |
| 729 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 730 | PPCAvFpOp op; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 731 | HReg dst; |
| 732 | HReg srcL; |
| 733 | HReg srcR; |
| 734 | } AvBin32Fx4; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 735 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 736 | PPCAvFpOp op; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 737 | HReg dst; |
| 738 | HReg src; |
| 739 | } AvUn32Fx4; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 740 | /* Perm,Sel,SlDbl,Splat are all weird AV permutations */ |
| 741 | struct { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 742 | HReg dst; |
| 743 | HReg srcL; |
| 744 | HReg srcR; |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 745 | HReg ctl; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 746 | } AvPerm; |
| 747 | struct { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 748 | HReg dst; |
| 749 | HReg srcL; |
| 750 | HReg srcR; |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 751 | HReg ctl; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 752 | } AvSel; |
| 753 | struct { |
| 754 | UChar shift; |
| 755 | HReg dst; |
| 756 | HReg srcL; |
| 757 | HReg srcR; |
| 758 | } AvShlDbl; |
| 759 | struct { |
| 760 | UChar sz; /* 8,16,32 */ |
| 761 | HReg dst; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 762 | PPCVI5s* src; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 763 | } AvSplat; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 764 | /* Mov src to dst on the given condition, which may not |
| 765 | be the bogus Xcc_ALWAYS. */ |
| 766 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 767 | PPCCondCode cond; |
| 768 | HReg dst; |
| 769 | HReg src; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 770 | } AvCMov; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 771 | /* Load AltiVec Status & Control Register */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 772 | struct { |
| 773 | HReg src; |
| 774 | } AvLdVSCR; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 775 | } Pin; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 776 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 777 | PPCInstr; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 778 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 779 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 780 | extern PPCInstr* PPCInstr_LI ( HReg, ULong, Bool ); |
| 781 | extern PPCInstr* PPCInstr_Alu ( PPCAluOp, HReg, HReg, PPCRH* ); |
| 782 | extern PPCInstr* PPCInstr_Shft ( PPCShftOp, Bool sz32, HReg, HReg, PPCRH* ); |
| 783 | extern PPCInstr* PPCInstr_AddSubC ( Bool, Bool, HReg, HReg, HReg ); |
| 784 | extern PPCInstr* PPCInstr_Cmp ( Bool, Bool, UInt, HReg, PPCRH* ); |
| 785 | extern PPCInstr* PPCInstr_Unary ( PPCUnaryOp op, HReg dst, HReg src ); |
| 786 | extern PPCInstr* PPCInstr_MulL ( Bool syned, Bool hi32, Bool sz32, HReg, HReg, HReg ); |
| 787 | extern PPCInstr* PPCInstr_Div ( Bool syned, Bool sz32, HReg dst, HReg srcL, HReg srcR ); |
| 788 | extern PPCInstr* PPCInstr_Call ( PPCCondCode, Addr64, UInt ); |
| 789 | extern PPCInstr* PPCInstr_Goto ( IRJumpKind, PPCCondCode cond, PPCRI* dst ); |
| 790 | extern PPCInstr* PPCInstr_CMov ( PPCCondCode, HReg dst, PPCRI* src ); |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 791 | extern PPCInstr* PPCInstr_Load ( UChar sz, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 792 | HReg dst, PPCAMode* src, Bool mode64 ); |
| 793 | extern PPCInstr* PPCInstr_Store ( UChar sz, PPCAMode* dst, |
| 794 | HReg src, Bool mode64 ); |
| 795 | extern PPCInstr* PPCInstr_Set ( PPCCondCode cond, HReg dst ); |
| 796 | extern PPCInstr* PPCInstr_MfCR ( HReg dst ); |
| 797 | extern PPCInstr* PPCInstr_MFence ( void ); |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 798 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 799 | extern PPCInstr* PPCInstr_FpUnary ( PPCFpOp op, HReg dst, HReg src ); |
| 800 | extern PPCInstr* PPCInstr_FpBinary ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR ); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 801 | extern PPCInstr* PPCInstr_FpMulAcc ( PPCFpOp op, HReg dst, HReg srcML, |
| 802 | HReg srcMR, HReg srcAcc ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 803 | extern PPCInstr* PPCInstr_FpLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* ); |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 804 | extern PPCInstr* PPCInstr_FpSTFIW ( HReg addr, HReg data ); |
| 805 | extern PPCInstr* PPCInstr_FpRSP ( HReg dst, HReg src ); |
| 806 | extern PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32, |
| 807 | HReg dst, HReg src ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 808 | extern PPCInstr* PPCInstr_FpCMov ( PPCCondCode, HReg dst, HReg src ); |
| 809 | extern PPCInstr* PPCInstr_FpLdFPSCR ( HReg src ); |
| 810 | extern PPCInstr* PPCInstr_FpCmp ( HReg dst, HReg srcL, HReg srcR ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 811 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 812 | extern PPCInstr* PPCInstr_RdWrLR ( Bool wrLR, HReg gpr ); |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 813 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 814 | extern PPCInstr* PPCInstr_AvLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* ); |
| 815 | extern PPCInstr* PPCInstr_AvUnary ( PPCAvOp op, HReg dst, HReg src ); |
| 816 | extern PPCInstr* PPCInstr_AvBinary ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
| 817 | extern PPCInstr* PPCInstr_AvBin8x16 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
| 818 | extern PPCInstr* PPCInstr_AvBin16x8 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
| 819 | extern PPCInstr* PPCInstr_AvBin32x4 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
| 820 | extern PPCInstr* PPCInstr_AvBin32Fx4 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
| 821 | extern PPCInstr* PPCInstr_AvUn32Fx4 ( PPCAvOp op, HReg dst, HReg src ); |
| 822 | extern PPCInstr* PPCInstr_AvPerm ( HReg dst, HReg srcL, HReg srcR, HReg ctl ); |
| 823 | extern PPCInstr* PPCInstr_AvSel ( HReg ctl, HReg dst, HReg srcL, HReg srcR ); |
| 824 | extern PPCInstr* PPCInstr_AvShlDbl ( UChar shift, HReg dst, HReg srcL, HReg srcR ); |
| 825 | extern PPCInstr* PPCInstr_AvSplat ( UChar sz, HReg dst, PPCVI5s* src ); |
| 826 | extern PPCInstr* PPCInstr_AvCMov ( PPCCondCode, HReg dst, HReg src ); |
| 827 | extern PPCInstr* PPCInstr_AvLdVSCR ( HReg src ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 828 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 829 | extern void ppPPCInstr ( PPCInstr*, Bool mode64 ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 830 | |
| 831 | /* Some functions that insulate the register allocator from details |
| 832 | of the underlying instruction set. */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 833 | extern void getRegUsage_PPCInstr ( HRegUsage*, PPCInstr*, Bool mode64 ); |
| 834 | extern void mapRegs_PPCInstr ( HRegRemap*, PPCInstr* , Bool mode64); |
| 835 | extern Bool isMove_PPCInstr ( PPCInstr*, HReg*, HReg* ); |
| 836 | extern Int emit_PPCInstr ( UChar* buf, Int nbuf, PPCInstr*, |
| 837 | Bool mode64, void* dispatch ); |
| 838 | extern PPCInstr* genSpill_PPC ( HReg rreg, UShort offsetB, Bool mode64 ); |
| 839 | extern PPCInstr* genReload_PPC ( HReg rreg, UShort offsetB, Bool mode64 ); |
| 840 | extern void getAllocableRegs_PPC ( Int*, HReg**, Bool mode64 ); |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame^] | 841 | extern HInstrArray* iselBB_PPC ( IRBB*, VexArch, |
| 842 | VexArchInfo*, |
| 843 | VexMiscInfo* ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 844 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 845 | #endif /* ndef __LIBVEX_HOST_PPC_HDEFS_H */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 846 | |
| 847 | /*---------------------------------------------------------------*/ |
cerion | d0eae2d | 2005-12-23 11:43:01 +0000 | [diff] [blame] | 848 | /*--- end host-ppc/hdefs.h ---*/ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 849 | /*---------------------------------------------------------------*/ |