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gerrit-public.fairphone.software / platform / external / valgrind / ad00ea9f40f930d98bb2d278291a6c4c6636d6d6 / . / priv / guest_mips_defs.h
blob: c540c156736e1d3eeb35818804e832769747e09f [file] [log] [blame]
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]1
2/*---------------------------------------------------------------*/
3/*--- begin guest_mips_defs.h ---*/
4/*---------------------------------------------------------------*/
5
6/*
7 This file is part of Valgrind, a dynamic binary instrumentation
8 framework.
9
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]10 Copyright (C) 2010-2013 RT-RK
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]11 mips-valgrind@rt-rk.com
12
13 This program is free software; you can redistribute it and/or
14 modify it under the terms of the GNU General Public License as
15 published by the Free Software Foundation; either version 2 of the
16 License, or (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful, but
19 WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the Free Software
25 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
26 02111-1307, USA.
27
28 The GNU General Public License is contained in the file COPYING.
29*/
30
31/* Only to be used within the guest-mips directory. */
32
33#ifndef __VEX_GUEST_MIPS_DEFS_H
34#define __VEX_GUEST_MIPS_DEFS_H
35
florian58a637b2012-09-30 20:30:17 +0000[diff] [blame]36#include "libvex_basictypes.h"
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]37#include "guest_generic_bb_to_IR.h" /* DisResult */
florian58a637b2012-09-30 20:30:17 +0000[diff] [blame]38
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]39/*---------------------------------------------------------*/
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]40/*--- mips to IR conversion ---*/
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]41/*---------------------------------------------------------*/
42
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]43/* Convert one MIPS insn to IR. See the type DisOneInstrFn in bb_to_IR.h. */
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]44extern DisResult disInstr_MIPS ( IRSB* irbb,
45 Bool (*resteerOkFn) (void *, Addr64),
46 Bool resteerCisOk,
47 void* callback_opaque,
florian8462d112014-09-24 15:18:09 +0000[diff] [blame]48 const UChar* guest_code,
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]49 Long delta,
50 Addr64 guest_IP,
51 VexArch guest_arch,
52 VexArchInfo* archinfo,
53 VexAbiInfo* abiinfo,
sewardj9b769162014-07-24 12:42:03 +0000[diff] [blame]54 VexEndness host_endness,
sewardj442e51a2012-12-06 18:08:04 +0000[diff] [blame]55 Bool sigill_diag );
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]56
57/* Used by the optimiser to specialise calls to helpers. */
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]58extern IRExpr *guest_mips32_spechelper ( const HChar * function_name,
59 IRExpr ** args,
60 IRStmt ** precedingStmts,
61 Int n_precedingStmts );
62
63extern IRExpr *guest_mips64_spechelper ( const HChar * function_name,
64 IRExpr ** args,
65 IRStmt ** precedingStmts,
66 Int n_precedingStmts);
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]67
68/* Describes to the optimser which part of the guest state require
69 precise memory exceptions. This is logically part of the guest
70 state description. */
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]71extern Bool guest_mips32_state_requires_precise_mem_exns ( Int, Int );
72
73extern Bool guest_mips64_state_requires_precise_mem_exns ( Int, Int );
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]74
75extern VexGuestLayout mips32Guest_layout;
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]76extern VexGuestLayout mips64Guest_layout;
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]77
78/*---------------------------------------------------------*/
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]79/*--- mips guest helpers ---*/
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]80/*---------------------------------------------------------*/
dejanj8007ea62013-09-18 10:06:13 +0000[diff] [blame]81typedef enum {
82 CEILWS=0, CEILWD, CEILLS, CEILLD,
83 FLOORWS, FLOORWD, FLOORLS, FLOORLD,
84 ROUNDWS, ROUNDWD, ROUNDLS, ROUNDLD,
85 TRUNCWS, TRUNCWD, TRUNCLS, TRUNCLD,
86 CVTDS, CVTDW, CVTSD, CVTSW,
87 CVTWS, CVTWD, CVTDL, CVTLS,
dejanj41833222013-11-14 15:44:42 +0000[diff] [blame]88 CVTLD, CVTSL, ADDS, ADDD,
89 SUBS, SUBD, DIVS
dejanj8007ea62013-09-18 10:06:13 +0000[diff] [blame]90} flt_op;
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]91
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]92extern UInt mips32_dirtyhelper_mfc0 ( UInt rd, UInt sel );
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]93
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]94extern ULong mips64_dirtyhelper_dmfc0 ( UInt rd, UInt sel );
95
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]96
97#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
dejanja445f1b2013-10-22 08:52:46 +0000[diff] [blame]98extern UInt mips32_dirtyhelper_rdhwr ( UInt rt, UInt rd );
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]99extern ULong mips64_dirtyhelper_rdhwr ( ULong rt, ULong rd );
100#endif
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]101
dejanj0e006f22014-02-19 11:56:29 +0000[diff] [blame]102/* Calculate FCSR in fp32 mode. */
103extern UInt mips_dirtyhelper_calculate_FCSR_fp32 ( void* guest_state, UInt fs,
104 UInt ft, flt_op op );
105/* Calculate FCSR in fp64 mode. */
106extern UInt mips_dirtyhelper_calculate_FCSR_fp64 ( void* guest_state, UInt fs,
107 UInt ft, flt_op op );
dejanj8007ea62013-09-18 10:06:13 +0000[diff] [blame]108
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]109/*---------------------------------------------------------*/
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]110/*--- Condition code stuff ---*/
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]111/*---------------------------------------------------------*/
112
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]113typedef enum {
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]114 MIPSCondEQ = 0, /* equal : Z=1 */
115 MIPSCondNE = 1, /* not equal : Z=0 */
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]116
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]117 MIPSCondHS = 2, /* >=u (higher or same) : C=1 */
118 MIPSCondLO = 3, /* <u (lower) : C=0 */
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]119
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]120 MIPSCondMI = 4, /* minus (negative) : N=1 */
121 MIPSCondPL = 5, /* plus (zero or +ve) : N=0 */
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]122
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]123 MIPSCondVS = 6, /* overflow : V=1 */
124 MIPSCondVC = 7, /* no overflow : V=0 */
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]125
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]126 MIPSCondHI = 8, /* >u (higher) : C=1 && Z=0 */
127 MIPSCondLS = 9, /* <=u (lower or same) : C=0 || Z=1 */
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]128
129 MIPSCondGE = 10, /* >=s (signed greater or equal) : N=V */
130 MIPSCondLT = 11, /* <s (signed less than) : N!=V */
131
132 MIPSCondGT = 12, /* >s (signed greater) : Z=0 && N=V */
133 MIPSCondLE = 13, /* <=s (signed less or equal) : Z=1 || N!=V */
134
135 MIPSCondAL = 14, /* always (unconditional) : 1 */
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]136 MIPSCondNV = 15 /* never (unconditional): : 0 */
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]137} MIPSCondcode;
138
139#endif /* __VEX_GUEST_MIPS_DEFS_H */
140
141/*---------------------------------------------------------------*/
142/*--- end guest_mips_defs.h ---*/
143/*---------------------------------------------------------------*/