Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / external / valgrind / add683d5f374b40576458fa386c7d75369014e11 / . / VEX / priv / guest_mips_defs.h
blob: f4c3bbc90ac1d3e2995c815d496d553deb94db4e [file] [log] [blame]
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]1
2/*---------------------------------------------------------------*/
3/*--- begin guest_mips_defs.h ---*/
4/*---------------------------------------------------------------*/
5
6/*
7 This file is part of Valgrind, a dynamic binary instrumentation
8 framework.
9
sewardj785952d2015-08-21 11:29:16 +0000[diff] [blame]10 Copyright (C) 2010-2015 RT-RK
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]11 mips-valgrind@rt-rk.com
12
13 This program is free software; you can redistribute it and/or
14 modify it under the terms of the GNU General Public License as
15 published by the Free Software Foundation; either version 2 of the
16 License, or (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful, but
19 WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the Free Software
25 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
26 02111-1307, USA.
27
28 The GNU General Public License is contained in the file COPYING.
29*/
30
31/* Only to be used within the guest-mips directory. */
32
33#ifndef __VEX_GUEST_MIPS_DEFS_H
34#define __VEX_GUEST_MIPS_DEFS_H
35
florian58a637b2012-09-30 20:30:17 +0000[diff] [blame]36#include "libvex_basictypes.h"
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]37#include "guest_generic_bb_to_IR.h" /* DisResult */
florian58a637b2012-09-30 20:30:17 +0000[diff] [blame]38
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]39/*---------------------------------------------------------*/
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]40/*--- mips to IR conversion ---*/
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]41/*---------------------------------------------------------*/
42
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]43/* Convert one MIPS insn to IR. See the type DisOneInstrFn in bb_to_IR.h. */
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]44extern DisResult disInstr_MIPS ( IRSB* irbb,
florianbeac5302014-12-31 12:09:38 +0000[diff] [blame]45 Bool (*resteerOkFn) (void *, Addr),
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]46 Bool resteerCisOk,
47 void* callback_opaque,
florian8462d112014-09-24 15:18:09 +0000[diff] [blame]48 const UChar* guest_code,
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]49 Long delta,
floriand4cc0de2015-01-02 11:44:12 +0000[diff] [blame]50 Addr guest_IP,
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]51 VexArch guest_arch,
floriancacba8e2014-12-15 18:58:07 +0000[diff] [blame]52 const VexArchInfo* archinfo,
53 const VexAbiInfo* abiinfo,
sewardj9b769162014-07-24 12:42:03 +0000[diff] [blame]54 VexEndness host_endness,
sewardj442e51a2012-12-06 18:08:04 +0000[diff] [blame]55 Bool sigill_diag );
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]56
57/* Used by the optimiser to specialise calls to helpers. */
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]58extern IRExpr *guest_mips32_spechelper ( const HChar * function_name,
59 IRExpr ** args,
60 IRStmt ** precedingStmts,
61 Int n_precedingStmts );
62
63extern IRExpr *guest_mips64_spechelper ( const HChar * function_name,
64 IRExpr ** args,
65 IRStmt ** precedingStmts,
66 Int n_precedingStmts);
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]67
68/* Describes to the optimser which part of the guest state require
69 precise memory exceptions. This is logically part of the guest
70 state description. */
sewardjca2c3c72015-02-05 12:53:20 +0000[diff] [blame]71extern
72Bool guest_mips32_state_requires_precise_mem_exns ( Int, Int,
73 VexRegisterUpdates );
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]74
sewardjca2c3c72015-02-05 12:53:20 +0000[diff] [blame]75extern
76Bool guest_mips64_state_requires_precise_mem_exns ( Int, Int,
77 VexRegisterUpdates );
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]78
79extern VexGuestLayout mips32Guest_layout;
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]80extern VexGuestLayout mips64Guest_layout;
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]81
82/*---------------------------------------------------------*/
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]83/*--- mips guest helpers ---*/
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]84/*---------------------------------------------------------*/
dejanj8007ea62013-09-18 10:06:13 +0000[diff] [blame]85typedef enum {
86 CEILWS=0, CEILWD, CEILLS, CEILLD,
87 FLOORWS, FLOORWD, FLOORLS, FLOORLD,
88 ROUNDWS, ROUNDWD, ROUNDLS, ROUNDLD,
89 TRUNCWS, TRUNCWD, TRUNCLS, TRUNCLD,
90 CVTDS, CVTDW, CVTSD, CVTSW,
91 CVTWS, CVTWD, CVTDL, CVTLS,
dejanj41833222013-11-14 15:44:42 +0000[diff] [blame]92 CVTLD, CVTSL, ADDS, ADDD,
93 SUBS, SUBD, DIVS
dejanj8007ea62013-09-18 10:06:13 +0000[diff] [blame]94} flt_op;
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]95
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]96extern UInt mips32_dirtyhelper_mfc0 ( UInt rd, UInt sel );
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]97
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]98extern ULong mips64_dirtyhelper_dmfc0 ( UInt rd, UInt sel );
99
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]100
101#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
dejanja445f1b2013-10-22 08:52:46 +0000[diff] [blame]102extern UInt mips32_dirtyhelper_rdhwr ( UInt rt, UInt rd );
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]103extern ULong mips64_dirtyhelper_rdhwr ( ULong rt, ULong rd );
104#endif
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]105
dejanj0e006f22014-02-19 11:56:29 +0000[diff] [blame]106/* Calculate FCSR in fp32 mode. */
107extern UInt mips_dirtyhelper_calculate_FCSR_fp32 ( void* guest_state, UInt fs,
108 UInt ft, flt_op op );
109/* Calculate FCSR in fp64 mode. */
110extern UInt mips_dirtyhelper_calculate_FCSR_fp64 ( void* guest_state, UInt fs,
111 UInt ft, flt_op op );
dejanj8007ea62013-09-18 10:06:13 +0000[diff] [blame]112
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]113/*---------------------------------------------------------*/
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]114/*--- Condition code stuff ---*/
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]115/*---------------------------------------------------------*/
116
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]117typedef enum {
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]118 MIPSCondEQ = 0, /* equal : Z=1 */
119 MIPSCondNE = 1, /* not equal : Z=0 */
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]120
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]121 MIPSCondHS = 2, /* >=u (higher or same) : C=1 */
122 MIPSCondLO = 3, /* <u (lower) : C=0 */
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]123
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]124 MIPSCondMI = 4, /* minus (negative) : N=1 */
125 MIPSCondPL = 5, /* plus (zero or +ve) : N=0 */
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]126
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]127 MIPSCondVS = 6, /* overflow : V=1 */
128 MIPSCondVC = 7, /* no overflow : V=0 */
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]129
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]130 MIPSCondHI = 8, /* >u (higher) : C=1 && Z=0 */
131 MIPSCondLS = 9, /* <=u (lower or same) : C=0 || Z=1 */
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]132
133 MIPSCondGE = 10, /* >=s (signed greater or equal) : N=V */
134 MIPSCondLT = 11, /* <s (signed less than) : N!=V */
135
136 MIPSCondGT = 12, /* >s (signed greater) : Z=0 && N=V */
137 MIPSCondLE = 13, /* <=s (signed less or equal) : Z=1 || N!=V */
138
139 MIPSCondAL = 14, /* always (unconditional) : 1 */
petarjb92a9542013-02-27 22:57:17 +0000[diff] [blame]140 MIPSCondNV = 15 /* never (unconditional): : 0 */
sewardj362cf842012-06-07 08:59:53 +0000[diff] [blame]141} MIPSCondcode;
142
143#endif /* __VEX_GUEST_MIPS_DEFS_H */
144
145/*---------------------------------------------------------------*/
146/*--- end guest_mips_defs.h ---*/
147/*---------------------------------------------------------------*/