cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 3 | /*--- begin host_ppc_defs.h ---*/ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 4 | /*---------------------------------------------------------------*/ |
| 5 | |
| 6 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 9 | |
sewardj | 89ae847 | 2013-10-18 14:12:58 +0000 | [diff] [blame] | 10 | Copyright (C) 2004-2013 OpenWorks LLP |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 11 | info@open-works.net |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 12 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 17 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 26 | 02110-1301, USA. |
| 27 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 28 | The GNU General Public License is contained in the file COPYING. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 29 | |
| 30 | Neither the names of the U.S. Department of Energy nor the |
| 31 | University of California nor the names of its contributors may be |
| 32 | used to endorse or promote products derived from this software |
| 33 | without prior written permission. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 34 | */ |
| 35 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 36 | #ifndef __VEX_HOST_PPC_DEFS_H |
| 37 | #define __VEX_HOST_PPC_DEFS_H |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 38 | |
florian | 58a637b | 2012-09-30 20:30:17 +0000 | [diff] [blame] | 39 | #include "libvex_basictypes.h" |
| 40 | #include "libvex.h" // VexArch |
| 41 | #include "host_generic_regs.h" // HReg |
| 42 | |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 43 | /* Num registers used for function calls */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 44 | #define PPC_N_REGPARMS 8 |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 45 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 46 | |
| 47 | /* --------- Registers. --------- */ |
| 48 | |
| 49 | /* The usual HReg abstraction. There are 32 real int regs, |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 50 | 32 real float regs, and 32 real vector regs. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 51 | */ |
| 52 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 53 | extern void ppHRegPPC ( HReg ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 54 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 55 | extern HReg hregPPC_GPR0 ( Bool mode64 ); // scratch reg / zero reg |
| 56 | extern HReg hregPPC_GPR1 ( Bool mode64 ); // Stack Frame Pointer |
| 57 | extern HReg hregPPC_GPR2 ( Bool mode64 ); // not used: TOC pointer |
| 58 | extern HReg hregPPC_GPR3 ( Bool mode64 ); |
| 59 | extern HReg hregPPC_GPR4 ( Bool mode64 ); |
| 60 | extern HReg hregPPC_GPR5 ( Bool mode64 ); |
| 61 | extern HReg hregPPC_GPR6 ( Bool mode64 ); |
| 62 | extern HReg hregPPC_GPR7 ( Bool mode64 ); |
| 63 | extern HReg hregPPC_GPR8 ( Bool mode64 ); |
| 64 | extern HReg hregPPC_GPR9 ( Bool mode64 ); |
| 65 | extern HReg hregPPC_GPR10 ( Bool mode64 ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 66 | extern HReg hregPPC_GPR11 ( Bool mode64 ); |
| 67 | extern HReg hregPPC_GPR12 ( Bool mode64 ); |
| 68 | extern HReg hregPPC_GPR13 ( Bool mode64 ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 69 | extern HReg hregPPC_GPR14 ( Bool mode64 ); |
| 70 | extern HReg hregPPC_GPR15 ( Bool mode64 ); |
| 71 | extern HReg hregPPC_GPR16 ( Bool mode64 ); |
| 72 | extern HReg hregPPC_GPR17 ( Bool mode64 ); |
| 73 | extern HReg hregPPC_GPR18 ( Bool mode64 ); |
| 74 | extern HReg hregPPC_GPR19 ( Bool mode64 ); |
| 75 | extern HReg hregPPC_GPR20 ( Bool mode64 ); |
| 76 | extern HReg hregPPC_GPR21 ( Bool mode64 ); |
| 77 | extern HReg hregPPC_GPR22 ( Bool mode64 ); |
| 78 | extern HReg hregPPC_GPR23 ( Bool mode64 ); |
| 79 | extern HReg hregPPC_GPR24 ( Bool mode64 ); |
| 80 | extern HReg hregPPC_GPR25 ( Bool mode64 ); |
| 81 | extern HReg hregPPC_GPR26 ( Bool mode64 ); |
| 82 | extern HReg hregPPC_GPR27 ( Bool mode64 ); |
| 83 | extern HReg hregPPC_GPR28 ( Bool mode64 ); |
sewardj | b8a8dba | 2005-12-15 21:33:50 +0000 | [diff] [blame] | 84 | extern HReg hregPPC_GPR29 ( Bool mode64 ); // reserved for dispatcher |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 85 | extern HReg hregPPC_GPR30 ( Bool mode64 ); // used as VMX spill temp |
sewardj | b8a8dba | 2005-12-15 21:33:50 +0000 | [diff] [blame] | 86 | extern HReg hregPPC_GPR31 ( Bool mode64 ); // GuestStatePtr (callee-saved) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 87 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 88 | extern HReg hregPPC_FPR0 ( void ); |
| 89 | extern HReg hregPPC_FPR1 ( void ); |
| 90 | extern HReg hregPPC_FPR2 ( void ); |
| 91 | extern HReg hregPPC_FPR3 ( void ); |
| 92 | extern HReg hregPPC_FPR4 ( void ); |
| 93 | extern HReg hregPPC_FPR5 ( void ); |
| 94 | extern HReg hregPPC_FPR6 ( void ); |
| 95 | extern HReg hregPPC_FPR7 ( void ); |
| 96 | extern HReg hregPPC_FPR8 ( void ); |
| 97 | extern HReg hregPPC_FPR9 ( void ); |
| 98 | extern HReg hregPPC_FPR10 ( void ); |
| 99 | extern HReg hregPPC_FPR11 ( void ); |
| 100 | extern HReg hregPPC_FPR12 ( void ); |
| 101 | extern HReg hregPPC_FPR13 ( void ); |
| 102 | extern HReg hregPPC_FPR14 ( void ); |
| 103 | extern HReg hregPPC_FPR15 ( void ); |
| 104 | extern HReg hregPPC_FPR16 ( void ); |
| 105 | extern HReg hregPPC_FPR17 ( void ); |
| 106 | extern HReg hregPPC_FPR18 ( void ); |
| 107 | extern HReg hregPPC_FPR19 ( void ); |
| 108 | extern HReg hregPPC_FPR20 ( void ); |
| 109 | extern HReg hregPPC_FPR21 ( void ); |
| 110 | extern HReg hregPPC_FPR22 ( void ); |
| 111 | extern HReg hregPPC_FPR23 ( void ); |
| 112 | extern HReg hregPPC_FPR24 ( void ); |
| 113 | extern HReg hregPPC_FPR25 ( void ); |
| 114 | extern HReg hregPPC_FPR26 ( void ); |
| 115 | extern HReg hregPPC_FPR27 ( void ); |
| 116 | extern HReg hregPPC_FPR28 ( void ); |
| 117 | extern HReg hregPPC_FPR29 ( void ); |
| 118 | extern HReg hregPPC_FPR30 ( void ); |
| 119 | extern HReg hregPPC_FPR31 ( void ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 120 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 121 | extern HReg hregPPC_VR0 ( void ); |
| 122 | extern HReg hregPPC_VR1 ( void ); |
| 123 | extern HReg hregPPC_VR2 ( void ); |
| 124 | extern HReg hregPPC_VR3 ( void ); |
| 125 | extern HReg hregPPC_VR4 ( void ); |
| 126 | extern HReg hregPPC_VR5 ( void ); |
| 127 | extern HReg hregPPC_VR6 ( void ); |
| 128 | extern HReg hregPPC_VR7 ( void ); |
| 129 | extern HReg hregPPC_VR8 ( void ); |
| 130 | extern HReg hregPPC_VR9 ( void ); |
| 131 | extern HReg hregPPC_VR10 ( void ); |
| 132 | extern HReg hregPPC_VR11 ( void ); |
| 133 | extern HReg hregPPC_VR12 ( void ); |
| 134 | extern HReg hregPPC_VR13 ( void ); |
| 135 | extern HReg hregPPC_VR14 ( void ); |
| 136 | extern HReg hregPPC_VR15 ( void ); |
| 137 | extern HReg hregPPC_VR16 ( void ); |
| 138 | extern HReg hregPPC_VR17 ( void ); |
| 139 | extern HReg hregPPC_VR18 ( void ); |
| 140 | extern HReg hregPPC_VR19 ( void ); |
| 141 | extern HReg hregPPC_VR20 ( void ); |
| 142 | extern HReg hregPPC_VR21 ( void ); |
| 143 | extern HReg hregPPC_VR22 ( void ); |
| 144 | extern HReg hregPPC_VR23 ( void ); |
| 145 | extern HReg hregPPC_VR24 ( void ); |
| 146 | extern HReg hregPPC_VR25 ( void ); |
| 147 | extern HReg hregPPC_VR26 ( void ); |
| 148 | extern HReg hregPPC_VR27 ( void ); |
| 149 | extern HReg hregPPC_VR28 ( void ); |
| 150 | extern HReg hregPPC_VR29 ( void ); |
| 151 | extern HReg hregPPC_VR30 ( void ); |
| 152 | extern HReg hregPPC_VR31 ( void ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 153 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 154 | #define StackFramePtr(_mode64) hregPPC_GPR1(_mode64) |
| 155 | #define GuestStatePtr(_mode64) hregPPC_GPR31(_mode64) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 156 | |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 157 | |
| 158 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 159 | /* --------- Condition codes --------- */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 160 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 161 | /* This gives names from bitfields in CR; hence it names BI numbers */ |
| 162 | /* Using IBM/hardware indexing convention */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 163 | typedef |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 164 | enum { |
| 165 | // CR7, which we use for integer compares |
| 166 | Pcf_7LT = 28, /* neg | lt */ |
| 167 | Pcf_7GT = 29, /* pos | gt */ |
| 168 | Pcf_7EQ = 30, /* zero | equal */ |
sewardj | 7e30807 | 2011-05-04 09:50:48 +0000 | [diff] [blame] | 169 | Pcf_7SO = 31, /* summary overflow */ |
| 170 | Pcf_NONE = 32 /* no condition; used with Pct_ALWAYS */ |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 171 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 172 | PPCCondFlag; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 173 | |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 174 | typedef |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 175 | enum { /* Maps bc bitfield BO */ |
sewardj | 7e30807 | 2011-05-04 09:50:48 +0000 | [diff] [blame] | 176 | Pct_FALSE = 0x4, /* associated PPCCondFlag must not be Pcf_NONE */ |
| 177 | Pct_TRUE = 0xC, /* associated PPCCondFlag must not be Pcf_NONE */ |
| 178 | Pct_ALWAYS = 0x14 /* associated PPCCondFlag must be Pcf_NONE */ |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 179 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 180 | PPCCondTest; |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 181 | |
| 182 | typedef |
| 183 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 184 | PPCCondFlag flag; |
| 185 | PPCCondTest test; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 186 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 187 | PPCCondCode; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 188 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 189 | extern const HChar* showPPCCondCode ( PPCCondCode ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 190 | |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 191 | /* constructor */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 192 | extern PPCCondCode mk_PPCCondCode ( PPCCondTest, PPCCondFlag ); |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 193 | |
| 194 | /* false->true, true->false */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 195 | extern PPCCondTest invertCondTest ( PPCCondTest ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 196 | |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 197 | |
| 198 | |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 199 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 200 | /* --------- Memory address expressions (amodes). --------- */ |
| 201 | |
| 202 | typedef |
| 203 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 204 | Pam_IR=1, /* Immediate (signed 16-bit) + Reg */ |
| 205 | Pam_RR=2 /* Reg1 + Reg2 */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 206 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 207 | PPCAModeTag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 208 | |
| 209 | typedef |
| 210 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 211 | PPCAModeTag tag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 212 | union { |
| 213 | struct { |
| 214 | HReg base; |
sewardj | a5f957d | 2005-07-02 01:29:32 +0000 | [diff] [blame] | 215 | Int index; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 216 | } IR; |
| 217 | struct { |
| 218 | HReg base; |
| 219 | HReg index; |
| 220 | } RR; |
| 221 | } Pam; |
| 222 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 223 | PPCAMode; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 224 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 225 | extern PPCAMode* PPCAMode_IR ( Int, HReg ); |
| 226 | extern PPCAMode* PPCAMode_RR ( HReg, HReg ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 227 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 228 | extern PPCAMode* dopyPPCAMode ( PPCAMode* ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 229 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 230 | extern void ppPPCAMode ( PPCAMode* ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 231 | |
| 232 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 233 | /* --------- Operand, which can be a reg or a u16/s16. --------- */ |
| 234 | /* ("RH" == "Register or Halfword immediate") */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 235 | typedef |
| 236 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 237 | Prh_Imm=3, |
| 238 | Prh_Reg=4 |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 239 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 240 | PPCRHTag; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 241 | |
| 242 | typedef |
| 243 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 244 | PPCRHTag tag; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 245 | union { |
| 246 | struct { |
| 247 | Bool syned; |
| 248 | UShort imm16; |
| 249 | } Imm; |
| 250 | struct { |
| 251 | HReg reg; |
| 252 | } Reg; |
| 253 | } |
| 254 | Prh; |
| 255 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 256 | PPCRH; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 257 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 258 | extern PPCRH* PPCRH_Imm ( Bool, UShort ); |
| 259 | extern PPCRH* PPCRH_Reg ( HReg ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 260 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 261 | extern void ppPPCRH ( PPCRH* ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 262 | |
| 263 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 264 | /* --------- Operand, which can be a reg or a u32/64. --------- */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 265 | |
| 266 | typedef |
| 267 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 268 | Pri_Imm=5, |
| 269 | Pri_Reg=6 |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 270 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 271 | PPCRITag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 272 | |
| 273 | typedef |
| 274 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 275 | PPCRITag tag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 276 | union { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 277 | ULong Imm; |
| 278 | HReg Reg; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 279 | } |
| 280 | Pri; |
| 281 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 282 | PPCRI; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 283 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 284 | extern PPCRI* PPCRI_Imm ( ULong ); |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 285 | extern PPCRI* PPCRI_Reg( HReg ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 286 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 287 | extern void ppPPCRI ( PPCRI* ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 288 | |
| 289 | |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 290 | /* --------- Operand, which can be a vector reg or a s6. --------- */ |
| 291 | /* ("VI" == "Vector Register or Immediate") */ |
| 292 | typedef |
| 293 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 294 | Pvi_Imm=7, |
| 295 | Pvi_Reg=8 |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 296 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 297 | PPCVI5sTag; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 298 | |
| 299 | typedef |
| 300 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 301 | PPCVI5sTag tag; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 302 | union { |
| 303 | Char Imm5s; |
| 304 | HReg Reg; |
| 305 | } |
| 306 | Pvi; |
| 307 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 308 | PPCVI5s; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 309 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 310 | extern PPCVI5s* PPCVI5s_Imm ( Char ); |
| 311 | extern PPCVI5s* PPCVI5s_Reg ( HReg ); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 312 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 313 | extern void ppPPCVI5s ( PPCVI5s* ); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 314 | |
| 315 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 316 | /* --------- Instructions. --------- */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 317 | |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 318 | /* --------- */ |
| 319 | typedef |
| 320 | enum { |
| 321 | Pun_NEG, |
cerion | e13bb31 | 2005-02-10 19:51:03 +0000 | [diff] [blame] | 322 | Pun_NOT, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 323 | Pun_CLZ32, |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 324 | Pun_CLZ64, |
| 325 | Pun_EXTSW |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 326 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 327 | PPCUnaryOp; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 328 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 329 | extern const HChar* showPPCUnaryOp ( PPCUnaryOp ); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 330 | |
| 331 | |
| 332 | /* --------- */ |
| 333 | typedef |
| 334 | enum { |
| 335 | Palu_INVALID, |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 336 | Palu_ADD, Palu_SUB, |
| 337 | Palu_AND, Palu_OR, Palu_XOR, |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 338 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 339 | PPCAluOp; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 340 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 341 | extern |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 342 | const HChar* showPPCAluOp ( PPCAluOp, |
| 343 | Bool /* is the 2nd operand an immediate? */); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 344 | |
| 345 | |
| 346 | /* --------- */ |
| 347 | typedef |
| 348 | enum { |
| 349 | Pshft_INVALID, |
| 350 | Pshft_SHL, Pshft_SHR, Pshft_SAR, |
| 351 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 352 | PPCShftOp; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 353 | |
| 354 | extern |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 355 | const HChar* showPPCShftOp ( PPCShftOp, |
| 356 | Bool /* is the 2nd operand an immediate? */, |
| 357 | Bool /* is this a 32bit or 64bit op? */ ); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 358 | |
| 359 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 360 | /* --------- */ |
| 361 | typedef |
| 362 | enum { |
| 363 | Pfp_INVALID, |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 364 | |
| 365 | /* Ternary */ |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 366 | Pfp_MADDD, Pfp_MSUBD, |
| 367 | Pfp_MADDS, Pfp_MSUBS, |
| 368 | Pfp_DFPADD, Pfp_DFPADDQ, |
| 369 | Pfp_DFPSUB, Pfp_DFPSUBQ, |
| 370 | Pfp_DFPMUL, Pfp_DFPMULQ, |
| 371 | Pfp_DFPDIV, Pfp_DFPDIVQ, |
| 372 | Pfp_DQUAQ, Pfp_DRRNDQ, |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 373 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 374 | /* Binary */ |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 375 | Pfp_ADDD, Pfp_SUBD, Pfp_MULD, Pfp_DIVD, |
| 376 | Pfp_ADDS, Pfp_SUBS, Pfp_MULS, Pfp_DIVS, |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 377 | Pfp_DRSP, Pfp_DRDPQ, Pfp_DCTFIX, Pfp_DCTFIXQ, Pfp_DCFFIX, |
carll | cea07cc | 2013-01-22 20:25:31 +0000 | [diff] [blame] | 378 | Pfp_DQUA, Pfp_RRDTR, Pfp_DIEX, Pfp_DIEXQ, Pfp_DRINTN, |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 379 | |
| 380 | /* Unary */ |
sewardj | 0f1ef86 | 2008-08-08 08:37:06 +0000 | [diff] [blame] | 381 | Pfp_SQRT, Pfp_ABS, Pfp_NEG, Pfp_MOV, Pfp_RES, Pfp_RSQRTE, |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 382 | Pfp_FRIN, Pfp_FRIM, Pfp_FRIP, Pfp_FRIZ, |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 383 | Pfp_DSCLI, Pfp_DSCRI, Pfp_DSCLIQ, Pfp_DSCRIQ, Pfp_DCTDP, |
| 384 | Pfp_DCTQPQ, Pfp_DCFFIXQ, Pfp_DXEX, Pfp_DXEXQ, |
| 385 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 386 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 387 | PPCFpOp; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 388 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 389 | extern const HChar* showPPCFpOp ( PPCFpOp ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 390 | |
| 391 | |
| 392 | /* --------- */ |
| 393 | typedef |
| 394 | enum { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 395 | Pav_INVALID, |
| 396 | |
| 397 | /* Integer Unary */ |
| 398 | Pav_MOV, /* Mov */ |
| 399 | Pav_NOT, /* Bitwise */ |
| 400 | Pav_UNPCKH8S, Pav_UNPCKH16S, /* Unpack */ |
| 401 | Pav_UNPCKL8S, Pav_UNPCKL16S, |
| 402 | Pav_UNPCKHPIX, Pav_UNPCKLPIX, |
| 403 | |
| 404 | /* Integer Binary */ |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 405 | Pav_AND, Pav_OR, Pav_XOR, /* Bitwise */ |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 406 | Pav_ADDU, Pav_QADDU, Pav_QADDS, |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 407 | Pav_SUBU, Pav_QSUBU, Pav_QSUBS, |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 408 | Pav_MULU, |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 409 | Pav_OMULU, Pav_OMULS, Pav_EMULU, Pav_EMULS, |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 410 | Pav_AVGU, Pav_AVGS, |
| 411 | Pav_MAXU, Pav_MAXS, |
| 412 | Pav_MINU, Pav_MINS, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 413 | |
| 414 | /* Compare (always affects CR field 6) */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 415 | Pav_CMPEQU, Pav_CMPGTU, Pav_CMPGTS, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 416 | |
| 417 | /* Shift */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 418 | Pav_SHL, Pav_SHR, Pav_SAR, Pav_ROTL, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 419 | |
| 420 | /* Pack */ |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 421 | Pav_PACKUU, Pav_QPACKUU, Pav_QPACKSU, Pav_QPACKSS, |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 422 | Pav_PACKPXL, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 423 | |
| 424 | /* Merge */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 425 | Pav_MRGHI, Pav_MRGLO, |
carll | 48ae46b | 2013-10-01 15:45:54 +0000 | [diff] [blame] | 426 | |
| 427 | /* Concatenation */ |
| 428 | Pav_CATODD, Pav_CATEVEN, |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 429 | |
| 430 | /* Polynomial Multipy-Add */ |
| 431 | Pav_POLYMULADD, |
| 432 | |
| 433 | /* Cipher */ |
| 434 | Pav_CIPHERV128, Pav_CIPHERLV128, Pav_NCIPHERV128, Pav_NCIPHERLV128, |
| 435 | Pav_CIPHERSUBV128, |
| 436 | |
| 437 | /* Hash */ |
| 438 | Pav_SHA256, Pav_SHA512, |
| 439 | |
| 440 | /* BCD Arithmetic */ |
| 441 | Pav_BCDAdd, Pav_BCDSub, |
| 442 | |
| 443 | /* zero count */ |
| 444 | Pav_ZEROCNTBYTE, Pav_ZEROCNTWORD, Pav_ZEROCNTHALF, Pav_ZEROCNTDBL, |
carll | 60c6bac | 2013-10-18 01:19:06 +0000 | [diff] [blame] | 445 | |
| 446 | /* Vector bit matrix transpose by byte */ |
| 447 | Pav_BITMTXXPOSE, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 448 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 449 | PPCAvOp; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 450 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 451 | extern const HChar* showPPCAvOp ( PPCAvOp ); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 452 | |
| 453 | |
| 454 | /* --------- */ |
| 455 | typedef |
| 456 | enum { |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 457 | Pavfp_INVALID, |
| 458 | |
| 459 | /* Floating point binary */ |
| 460 | Pavfp_ADDF, Pavfp_SUBF, Pavfp_MULF, |
| 461 | Pavfp_MAXF, Pavfp_MINF, |
| 462 | Pavfp_CMPEQF, Pavfp_CMPGTF, Pavfp_CMPGEF, |
| 463 | |
| 464 | /* Floating point unary */ |
| 465 | Pavfp_RCPF, Pavfp_RSQRTF, |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 466 | Pavfp_CVTU2F, Pavfp_CVTS2F, Pavfp_QCVTF2U, Pavfp_QCVTF2S, |
| 467 | Pavfp_ROUNDM, Pavfp_ROUNDP, Pavfp_ROUNDN, Pavfp_ROUNDZ, |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 468 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 469 | PPCAvFpOp; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 470 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 471 | extern const HChar* showPPCAvFpOp ( PPCAvFpOp ); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 472 | |
| 473 | |
| 474 | /* --------- */ |
| 475 | typedef |
| 476 | enum { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 477 | Pin_LI, /* load word (32/64-bit) immediate (fake insn) */ |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 478 | Pin_Alu, /* word add/sub/and/or/xor */ |
| 479 | Pin_Shft, /* word shl/shr/sar */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 480 | Pin_AddSubC, /* add/sub with read/write carry */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 481 | Pin_Cmp, /* word compare */ |
| 482 | Pin_Unary, /* not, neg, clz */ |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 483 | Pin_MulL, /* widening multiply */ |
| 484 | Pin_Div, /* div */ |
| 485 | Pin_Call, /* call to address in register */ |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 486 | Pin_XDirect, /* direct transfer to GA */ |
| 487 | Pin_XIndir, /* indirect transfer to GA */ |
| 488 | Pin_XAssisted, /* assisted transfer to GA */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 489 | Pin_CMov, /* conditional move */ |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 490 | Pin_Load, /* zero-extending load a 8|16|32|64 bit value from mem */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 491 | Pin_LoadL, /* load-linked (lwarx/ldarx) 32|64 bit value from mem */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 492 | Pin_Store, /* store a 8|16|32|64 bit value to mem */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 493 | Pin_StoreC, /* store-conditional (stwcx./stdcx.) 32|64 bit val */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 494 | Pin_Set, /* convert condition code to value 0 or 1 */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 495 | Pin_MfCR, /* move from condition register to GPR */ |
| 496 | Pin_MFence, /* mem fence */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 497 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 498 | Pin_FpUnary, /* FP unary op */ |
| 499 | Pin_FpBinary, /* FP binary op */ |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 500 | Pin_FpMulAcc, /* FP multipy-accumulate style op */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 501 | Pin_FpLdSt, /* FP load/store */ |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 502 | Pin_FpSTFIW, /* stfiwx */ |
| 503 | Pin_FpRSP, /* FP round IEEE754 double to IEEE754 single */ |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 504 | Pin_FpCftI, /* fcfid[u,s,us]/fctid[u]/fctiw[u] */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 505 | Pin_FpCMov, /* FP floating point conditional move */ |
| 506 | Pin_FpLdFPSCR, /* mtfsf */ |
| 507 | Pin_FpCmp, /* FP compare, generating value into int reg */ |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 508 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 509 | Pin_RdWrLR, /* Read/Write Link Register */ |
| 510 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 511 | Pin_AvLdSt, /* AV load/store (kludging for AMode_IR) */ |
| 512 | Pin_AvUnary, /* AV unary general reg=>reg */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 513 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 514 | Pin_AvBinary, /* AV binary general reg,reg=>reg */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 515 | Pin_AvBin8x16, /* AV binary, 8x4 */ |
| 516 | Pin_AvBin16x8, /* AV binary, 16x4 */ |
| 517 | Pin_AvBin32x4, /* AV binary, 32x4 */ |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 518 | Pin_AvBin64x2, /* AV binary, 64x2 */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 519 | |
| 520 | Pin_AvBin32Fx4, /* AV FP binary, 32Fx4 */ |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 521 | Pin_AvUn32Fx4, /* AV FP unary, 32Fx4 */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 522 | |
| 523 | Pin_AvPerm, /* AV permute (shuffle) */ |
| 524 | Pin_AvSel, /* AV select */ |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 525 | Pin_AvSh, /* AV shift left or right */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 526 | Pin_AvShlDbl, /* AV shift-left double by imm */ |
| 527 | Pin_AvSplat, /* One elem repeated throughout dst */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 528 | Pin_AvLdVSCR, /* mtvscr */ |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 529 | Pin_AvCMov, /* AV conditional move */ |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 530 | Pin_AvCipherV128Unary, /* AV Vector unary Cipher */ |
| 531 | Pin_AvCipherV128Binary, /* AV Vector binary Cipher */ |
| 532 | Pin_AvHashV128Binary, /* AV Vector binary Hash */ |
| 533 | Pin_AvBCDV128Trinary, /* BCD Arithmetic */ |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 534 | Pin_Dfp64Unary, /* DFP64 unary op */ |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 535 | Pin_Dfp128Unary, /* DFP128 unary op */ |
| 536 | Pin_DfpShift, /* Decimal floating point shift by immediate value */ |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 537 | Pin_Dfp64Binary, /* DFP64 binary op */ |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 538 | Pin_Dfp128Binary, /* DFP128 binary op */ |
| 539 | Pin_DfpShift128, /* 128-bit Decimal floating point shift by |
| 540 | * immediate value */ |
| 541 | Pin_DfpD128toD64, /* DFP 128 to DFP 64 op */ |
| 542 | Pin_DfpI64StoD128, /* DFP signed integer to DFP 128 */ |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 543 | Pin_DfpRound, /* D64 round to D64 */ |
| 544 | Pin_DfpRound128, /* D128 round to D128 */ |
| 545 | Pin_ExtractExpD128, /* DFP, extract 64 bit exponent */ |
| 546 | Pin_InsertExpD128, /* DFP, insert 64 bit exponent and 128 bit binary |
| 547 | * significand into a DFP 128-bit value*/ |
| 548 | Pin_Dfp64Cmp, /* DFP 64-bit compare, generating value into |
| 549 | * int reg */ |
| 550 | Pin_Dfp128Cmp, /* DFP 128-bit compare, generating value into |
| 551 | * int reg */ |
| 552 | Pin_DfpQuantize, /* D64 quantize using register value, significance |
| 553 | * round */ |
| 554 | Pin_DfpQuantize128, /* D128 quantize using register value, significance |
| 555 | * round */ |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 556 | Pin_EvCheck, /* Event check */ |
| 557 | Pin_ProfInc /* 64-bit profile counter increment */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 558 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 559 | PPCInstrTag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 560 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 561 | /* Destinations are on the LEFT (first operand) */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 562 | |
| 563 | typedef |
| 564 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 565 | PPCInstrTag tag; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 566 | union { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 567 | /* Get a 32/64-bit literal into a register. |
| 568 | May turn into a number of real insns. */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 569 | struct { |
| 570 | HReg dst; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 571 | ULong imm64; |
| 572 | } LI; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 573 | /* Integer add/sub/and/or/xor. Limitations: |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 574 | - For add, the immediate, if it exists, is a signed 16. |
| 575 | - For sub, the immediate, if it exists, is a signed 16 |
| 576 | which may not be -32768, since no such instruction |
| 577 | exists, and so we have to emit addi with +32768, but |
| 578 | that is not possible. |
| 579 | - For and/or/xor, the immediate, if it exists, |
| 580 | is an unsigned 16. |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 581 | */ |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 582 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 583 | PPCAluOp op; |
| 584 | HReg dst; |
| 585 | HReg srcL; |
| 586 | PPCRH* srcR; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 587 | } Alu; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 588 | /* Integer shl/shr/sar. |
| 589 | Limitations: the immediate, if it exists, |
| 590 | is a signed 5-bit value between 1 and 31 inclusive. |
| 591 | */ |
| 592 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 593 | PPCShftOp op; |
| 594 | Bool sz32; /* mode64 has both 32 and 64bit shft */ |
| 595 | HReg dst; |
| 596 | HReg srcL; |
| 597 | PPCRH* srcR; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 598 | } Shft; |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 599 | /* */ |
| 600 | struct { |
| 601 | Bool isAdd; /* else sub */ |
| 602 | Bool setC; /* else read carry */ |
| 603 | HReg dst; |
| 604 | HReg srcL; |
| 605 | HReg srcR; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 606 | } AddSubC; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 607 | /* If signed, the immediate, if it exists, is a signed 16, |
| 608 | else it is an unsigned 16. */ |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 609 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 610 | Bool syned; |
| 611 | Bool sz32; /* mode64 has both 32 and 64bit cmp */ |
| 612 | UInt crfD; |
| 613 | HReg srcL; |
| 614 | PPCRH* srcR; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 615 | } Cmp; |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 616 | /* Not, Neg, Clz32/64, Extsw */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 617 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 618 | PPCUnaryOp op; |
| 619 | HReg dst; |
| 620 | HReg src; |
| 621 | } Unary; |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 622 | struct { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 623 | Bool syned; /* meaningless if hi32==False */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 624 | Bool hi; /* False=>low, True=>high */ |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 625 | Bool sz32; /* mode64 has both 32 & 64bit mull */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 626 | HReg dst; |
| 627 | HReg srcL; |
| 628 | HReg srcR; |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 629 | } MulL; |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 630 | /* ppc32 div/divu instruction. */ |
cerion | c0e707e | 2005-02-10 22:35:34 +0000 | [diff] [blame] | 631 | struct { |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 632 | Bool extended; |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 633 | Bool syned; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 634 | Bool sz32; /* mode64 has both 32 & 64bit div */ |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 635 | HReg dst; |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 636 | HReg srcL; |
| 637 | HReg srcR; |
cerion | c0e707e | 2005-02-10 22:35:34 +0000 | [diff] [blame] | 638 | } Div; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 639 | /* Pseudo-insn. Call target (an absolute address), on given |
sewardj | 6a64a9f | 2005-08-21 00:48:37 +0000 | [diff] [blame] | 640 | condition (which could be Pct_ALWAYS). argiregs indicates |
| 641 | which of r3 .. r10 carries argument values for this call, |
| 642 | using a bit mask (1<<N is set if rN holds an arg, for N in |
| 643 | 3 .. 10 inclusive). */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 644 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 645 | PPCCondCode cond; |
| 646 | Addr64 target; |
| 647 | UInt argiregs; |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 648 | RetLoc rloc; /* where the return value will be */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 649 | } Call; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 650 | /* Update the guest CIA value, then exit requesting to chain |
| 651 | to it. May be conditional. Use of Addr64 in order to cope |
| 652 | with 64-bit hosts. */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 653 | struct { |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 654 | Addr64 dstGA; /* next guest address */ |
| 655 | PPCAMode* amCIA; /* amode in guest state for CIA */ |
| 656 | PPCCondCode cond; /* can be ALWAYS */ |
| 657 | Bool toFastEP; /* chain to the slow or fast point? */ |
| 658 | } XDirect; |
| 659 | /* Boring transfer to a guest address not known at JIT time. |
| 660 | Not chainable. May be conditional. */ |
| 661 | struct { |
| 662 | HReg dstGA; |
| 663 | PPCAMode* amCIA; |
| 664 | PPCCondCode cond; /* can be ALWAYS */ |
| 665 | } XIndir; |
| 666 | /* Assisted transfer to a guest address, most general case. |
| 667 | Not chainable. May be conditional. */ |
| 668 | struct { |
| 669 | HReg dstGA; |
| 670 | PPCAMode* amCIA; |
| 671 | PPCCondCode cond; /* can be ALWAYS */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 672 | IRJumpKind jk; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 673 | } XAssisted; |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 674 | /* Mov src to dst on the given condition, which may not |
cerion | 9abfcbc | 2005-02-25 11:16:58 +0000 | [diff] [blame] | 675 | be the bogus Pct_ALWAYS. */ |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 676 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 677 | PPCCondCode cond; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 678 | HReg dst; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 679 | PPCRI* src; |
| 680 | } CMov; |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 681 | /* Zero extending loads. Dst size is host word size */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 682 | struct { |
| 683 | UChar sz; /* 1|2|4|8 */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 684 | HReg dst; |
| 685 | PPCAMode* src; |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 686 | } Load; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 687 | /* Load-and-reserve (lwarx, ldarx) */ |
| 688 | struct { |
| 689 | UChar sz; /* 4|8 */ |
| 690 | HReg dst; |
| 691 | HReg src; |
| 692 | } LoadL; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 693 | /* 64/32/16/8 bit stores */ |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 694 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 695 | UChar sz; /* 1|2|4|8 */ |
| 696 | PPCAMode* dst; |
| 697 | HReg src; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 698 | } Store; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 699 | /* Store-conditional (stwcx., stdcx.) */ |
| 700 | struct { |
| 701 | UChar sz; /* 4|8 */ |
| 702 | HReg dst; |
| 703 | HReg src; |
| 704 | } StoreC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 705 | /* Convert a ppc condition code to value 0 or 1. */ |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 706 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 707 | PPCCondCode cond; |
| 708 | HReg dst; |
| 709 | } Set; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 710 | /* Move the entire CR to a GPR */ |
| 711 | struct { |
| 712 | HReg dst; |
| 713 | } MfCR; |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 714 | /* Mem fence. In short, an insn which flushes all preceding |
| 715 | loads and stores as much as possible before continuing. |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 716 | On PPC we emit a "sync". */ |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 717 | struct { |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 718 | } MFence; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 719 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 720 | /* PPC Floating point */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 721 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 722 | PPCFpOp op; |
| 723 | HReg dst; |
| 724 | HReg src; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 725 | } FpUnary; |
| 726 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 727 | PPCFpOp op; |
| 728 | HReg dst; |
| 729 | HReg srcL; |
| 730 | HReg srcR; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 731 | } FpBinary; |
| 732 | struct { |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 733 | PPCFpOp op; |
| 734 | HReg dst; |
| 735 | HReg srcML; |
| 736 | HReg srcMR; |
| 737 | HReg srcAcc; |
| 738 | } FpMulAcc; |
| 739 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 740 | Bool isLoad; |
| 741 | UChar sz; /* only 4 (IEEE single) or 8 (IEEE double) */ |
| 742 | HReg reg; |
| 743 | PPCAMode* addr; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 744 | } FpLdSt; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 745 | struct { |
| 746 | HReg addr; /* int reg */ |
| 747 | HReg data; /* float reg */ |
| 748 | } FpSTFIW; |
| 749 | /* Round 64-bit FP value to 32-bit FP value in an FP reg. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 750 | struct { |
| 751 | HReg src; |
| 752 | HReg dst; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 753 | } FpRSP; |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 754 | /* fcfid[u,s,us]/fctid[u]/fctiw[u]. Only some combinations |
| 755 | of the various fields are allowed. This is asserted for |
| 756 | and documented in the code for the constructor, |
| 757 | PPCInstr_FpCftI, in host_ppc_defs.c. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 758 | struct { |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 759 | Bool fromI; /* True== I->F, False== F->I */ |
| 760 | Bool int32; /* True== I is 32, False== I is 64 */ |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 761 | Bool syned; |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 762 | Bool flt64; /* True== F is 64, False== F is 32 */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 763 | HReg src; |
| 764 | HReg dst; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 765 | } FpCftI; |
| 766 | /* FP mov src to dst on the given condition. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 767 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 768 | PPCCondCode cond; |
| 769 | HReg dst; |
| 770 | HReg src; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 771 | } FpCMov; |
| 772 | /* Load FP Status & Control Register */ |
| 773 | struct { |
| 774 | HReg src; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 775 | UInt dfp_rm; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 776 | } FpLdFPSCR; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 777 | /* Do a compare, generating result into an int register. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 778 | struct { |
| 779 | UChar crfD; |
| 780 | HReg dst; |
| 781 | HReg srcL; |
| 782 | HReg srcR; |
| 783 | } FpCmp; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 784 | |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 785 | /* Read/Write Link Register */ |
| 786 | struct { |
| 787 | Bool wrLR; |
| 788 | HReg gpr; |
| 789 | } RdWrLR; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 790 | |
| 791 | /* Simplistic AltiVec */ |
| 792 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 793 | Bool isLoad; |
| 794 | UChar sz; /* 8|16|32|128 */ |
| 795 | HReg reg; |
| 796 | PPCAMode* addr; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 797 | } AvLdSt; |
| 798 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 799 | PPCAvOp op; |
| 800 | HReg dst; |
| 801 | HReg src; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 802 | } AvUnary; |
| 803 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 804 | PPCAvOp op; |
| 805 | HReg dst; |
| 806 | HReg srcL; |
| 807 | HReg srcR; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 808 | } AvBinary; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 809 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 810 | PPCAvOp op; |
| 811 | HReg dst; |
| 812 | HReg srcL; |
| 813 | HReg srcR; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 814 | } AvBin8x16; |
| 815 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 816 | PPCAvOp op; |
| 817 | HReg dst; |
| 818 | HReg srcL; |
| 819 | HReg srcR; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 820 | } AvBin16x8; |
| 821 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 822 | PPCAvOp op; |
| 823 | HReg dst; |
| 824 | HReg srcL; |
| 825 | HReg srcR; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 826 | } AvBin32x4; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 827 | /* Can only be generated for CPUs capable of ISA 2.07 or above */ |
| 828 | struct { |
| 829 | PPCAvOp op; |
| 830 | HReg dst; |
| 831 | HReg srcL; |
| 832 | HReg srcR; |
| 833 | } AvBin64x2; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 834 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 835 | PPCAvFpOp op; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 836 | HReg dst; |
| 837 | HReg srcL; |
| 838 | HReg srcR; |
| 839 | } AvBin32Fx4; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 840 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 841 | PPCAvFpOp op; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 842 | HReg dst; |
| 843 | HReg src; |
| 844 | } AvUn32Fx4; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 845 | /* Perm,Sel,SlDbl,Splat are all weird AV permutations */ |
| 846 | struct { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 847 | HReg dst; |
| 848 | HReg srcL; |
| 849 | HReg srcR; |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 850 | HReg ctl; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 851 | } AvPerm; |
| 852 | struct { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 853 | HReg dst; |
| 854 | HReg srcL; |
| 855 | HReg srcR; |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 856 | HReg ctl; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 857 | } AvSel; |
| 858 | struct { |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 859 | Bool shLeft; |
| 860 | HReg dst; |
carll | 99de41e | 2014-10-07 18:20:39 +0000 | [diff] [blame] | 861 | PPCAMode* addr; |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 862 | } AvSh; |
| 863 | struct { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 864 | UChar shift; |
| 865 | HReg dst; |
| 866 | HReg srcL; |
| 867 | HReg srcR; |
| 868 | } AvShlDbl; |
| 869 | struct { |
| 870 | UChar sz; /* 8,16,32 */ |
| 871 | HReg dst; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 872 | PPCVI5s* src; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 873 | } AvSplat; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 874 | /* Mov src to dst on the given condition, which may not |
| 875 | be the bogus Xcc_ALWAYS. */ |
| 876 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 877 | PPCCondCode cond; |
| 878 | HReg dst; |
| 879 | HReg src; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 880 | } AvCMov; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 881 | /* Load AltiVec Status & Control Register */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 882 | struct { |
| 883 | HReg src; |
| 884 | } AvLdVSCR; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 885 | struct { |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 886 | PPCAvOp op; |
| 887 | HReg dst; |
| 888 | HReg src; |
| 889 | } AvCipherV128Unary; |
| 890 | struct { |
| 891 | PPCAvOp op; |
| 892 | HReg dst; |
| 893 | HReg src; |
| 894 | PPCRI* s_field; |
| 895 | } AvHashV128Binary; |
| 896 | struct { |
| 897 | PPCAvOp op; |
| 898 | HReg dst; |
| 899 | HReg src1; |
| 900 | HReg src2; |
| 901 | PPCRI* ps; |
| 902 | } AvBCDV128Trinary; |
| 903 | struct { |
| 904 | PPCAvOp op; |
| 905 | HReg dst; |
| 906 | HReg srcL; |
| 907 | HReg srcR; |
| 908 | } AvCipherV128Binary; |
| 909 | struct { |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 910 | PPCFpOp op; |
| 911 | HReg dst; |
| 912 | HReg src; |
| 913 | } Dfp64Unary; |
| 914 | struct { |
| 915 | PPCFpOp op; |
| 916 | HReg dst; |
| 917 | HReg srcL; |
| 918 | HReg srcR; |
| 919 | } Dfp64Binary; |
| 920 | struct { |
| 921 | PPCFpOp op; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 922 | HReg dst; |
| 923 | HReg src; |
| 924 | PPCRI* shift; |
| 925 | } DfpShift; |
| 926 | struct { |
| 927 | PPCFpOp op; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 928 | HReg dst_hi; |
| 929 | HReg dst_lo; |
| 930 | HReg src_hi; |
| 931 | HReg src_lo; |
| 932 | } Dfp128Unary; |
| 933 | struct { |
| 934 | /* The dst is used to pass the left source operand in and return |
| 935 | * the result. |
| 936 | */ |
| 937 | PPCFpOp op; |
| 938 | HReg dst_hi; |
| 939 | HReg dst_lo; |
| 940 | HReg srcR_hi; |
| 941 | HReg srcR_lo; |
| 942 | } Dfp128Binary; |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 943 | struct { |
| 944 | PPCFpOp op; |
| 945 | HReg dst_hi; |
| 946 | HReg dst_lo; |
| 947 | HReg src_hi; |
| 948 | HReg src_lo; |
| 949 | PPCRI* shift; |
| 950 | } DfpShift128; |
| 951 | struct { |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 952 | HReg dst; |
| 953 | HReg src; |
| 954 | PPCRI* r_rmc; |
| 955 | } DfpRound; |
| 956 | struct { |
| 957 | HReg dst_hi; |
| 958 | HReg dst_lo; |
| 959 | HReg src_hi; |
| 960 | HReg src_lo; |
| 961 | PPCRI* r_rmc; |
| 962 | } DfpRound128; |
| 963 | struct { |
| 964 | PPCFpOp op; |
| 965 | HReg dst; |
| 966 | HReg srcL; |
| 967 | HReg srcR; |
| 968 | PPCRI* rmc; |
| 969 | } DfpQuantize; |
| 970 | struct { |
| 971 | PPCFpOp op; |
| 972 | HReg dst_hi; |
| 973 | HReg dst_lo; |
| 974 | HReg src_hi; |
| 975 | HReg src_lo; |
| 976 | PPCRI* rmc; |
| 977 | } DfpQuantize128; |
| 978 | struct { |
| 979 | PPCFpOp op; |
| 980 | HReg dst; |
| 981 | HReg src_hi; |
| 982 | HReg src_lo; |
| 983 | } ExtractExpD128; |
| 984 | struct { |
| 985 | PPCFpOp op; |
| 986 | HReg dst_hi; |
| 987 | HReg dst_lo; |
| 988 | HReg srcL; |
| 989 | HReg srcR_hi; |
| 990 | HReg srcR_lo; |
| 991 | } InsertExpD128; |
| 992 | struct { |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 993 | PPCFpOp op; |
| 994 | HReg dst; |
| 995 | HReg src_hi; |
| 996 | HReg src_lo; |
| 997 | } DfpD128toD64; |
| 998 | struct { |
| 999 | PPCFpOp op; |
| 1000 | HReg dst_hi; |
| 1001 | HReg dst_lo; |
| 1002 | HReg src; |
| 1003 | } DfpI64StoD128; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1004 | struct { |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1005 | UChar crfD; |
| 1006 | HReg dst; |
| 1007 | HReg srcL; |
| 1008 | HReg srcR; |
| 1009 | } Dfp64Cmp; |
| 1010 | struct { |
| 1011 | UChar crfD; |
| 1012 | HReg dst; |
| 1013 | HReg srcL_hi; |
| 1014 | HReg srcL_lo; |
| 1015 | HReg srcR_hi; |
| 1016 | HReg srcR_lo; |
| 1017 | } Dfp128Cmp; |
| 1018 | struct { |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1019 | PPCAMode* amCounter; |
| 1020 | PPCAMode* amFailAddr; |
| 1021 | } EvCheck; |
| 1022 | struct { |
| 1023 | /* No fields. The address of the counter to inc is |
| 1024 | installed later, post-translation, by patching it in, |
| 1025 | as it is not known at translation time. */ |
| 1026 | } ProfInc; |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1027 | } Pin; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1028 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1029 | PPCInstr; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1030 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 1031 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1032 | extern PPCInstr* PPCInstr_LI ( HReg, ULong, Bool ); |
| 1033 | extern PPCInstr* PPCInstr_Alu ( PPCAluOp, HReg, HReg, PPCRH* ); |
| 1034 | extern PPCInstr* PPCInstr_Shft ( PPCShftOp, Bool sz32, HReg, HReg, PPCRH* ); |
| 1035 | extern PPCInstr* PPCInstr_AddSubC ( Bool, Bool, HReg, HReg, HReg ); |
| 1036 | extern PPCInstr* PPCInstr_Cmp ( Bool, Bool, UInt, HReg, PPCRH* ); |
| 1037 | extern PPCInstr* PPCInstr_Unary ( PPCUnaryOp op, HReg dst, HReg src ); |
| 1038 | extern PPCInstr* PPCInstr_MulL ( Bool syned, Bool hi32, Bool sz32, HReg, HReg, HReg ); |
sewardj | 4aa412a | 2011-07-24 14:13:21 +0000 | [diff] [blame] | 1039 | extern PPCInstr* PPCInstr_Div ( Bool extended, Bool syned, Bool sz32, HReg dst, HReg srcL, HReg srcR ); |
sewardj | cfe046e | 2013-01-17 14:23:53 +0000 | [diff] [blame] | 1040 | extern PPCInstr* PPCInstr_Call ( PPCCondCode, Addr64, UInt, RetLoc ); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1041 | extern PPCInstr* PPCInstr_XDirect ( Addr64 dstGA, PPCAMode* amCIA, |
| 1042 | PPCCondCode cond, Bool toFastEP ); |
| 1043 | extern PPCInstr* PPCInstr_XIndir ( HReg dstGA, PPCAMode* amCIA, |
| 1044 | PPCCondCode cond ); |
| 1045 | extern PPCInstr* PPCInstr_XAssisted ( HReg dstGA, PPCAMode* amCIA, |
| 1046 | PPCCondCode cond, IRJumpKind jk ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1047 | extern PPCInstr* PPCInstr_CMov ( PPCCondCode, HReg dst, PPCRI* src ); |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 1048 | extern PPCInstr* PPCInstr_Load ( UChar sz, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1049 | HReg dst, PPCAMode* src, Bool mode64 ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1050 | extern PPCInstr* PPCInstr_LoadL ( UChar sz, |
| 1051 | HReg dst, HReg src, Bool mode64 ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1052 | extern PPCInstr* PPCInstr_Store ( UChar sz, PPCAMode* dst, |
| 1053 | HReg src, Bool mode64 ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1054 | extern PPCInstr* PPCInstr_StoreC ( UChar sz, HReg dst, HReg src, |
| 1055 | Bool mode64 ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1056 | extern PPCInstr* PPCInstr_Set ( PPCCondCode cond, HReg dst ); |
| 1057 | extern PPCInstr* PPCInstr_MfCR ( HReg dst ); |
| 1058 | extern PPCInstr* PPCInstr_MFence ( void ); |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 1059 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1060 | extern PPCInstr* PPCInstr_FpUnary ( PPCFpOp op, HReg dst, HReg src ); |
| 1061 | extern PPCInstr* PPCInstr_FpBinary ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR ); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 1062 | extern PPCInstr* PPCInstr_FpMulAcc ( PPCFpOp op, HReg dst, HReg srcML, |
| 1063 | HReg srcMR, HReg srcAcc ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1064 | extern PPCInstr* PPCInstr_FpLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* ); |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 1065 | extern PPCInstr* PPCInstr_FpSTFIW ( HReg addr, HReg data ); |
| 1066 | extern PPCInstr* PPCInstr_FpRSP ( HReg dst, HReg src ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1067 | extern PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32, Bool syned, |
| 1068 | Bool dst64, HReg dst, HReg src ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1069 | extern PPCInstr* PPCInstr_FpCMov ( PPCCondCode, HReg dst, HReg src ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1070 | extern PPCInstr* PPCInstr_FpLdFPSCR ( HReg src, Bool dfp_rm ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1071 | extern PPCInstr* PPCInstr_FpCmp ( HReg dst, HReg srcL, HReg srcR ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1072 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1073 | extern PPCInstr* PPCInstr_RdWrLR ( Bool wrLR, HReg gpr ); |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 1074 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1075 | extern PPCInstr* PPCInstr_AvLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* ); |
| 1076 | extern PPCInstr* PPCInstr_AvUnary ( PPCAvOp op, HReg dst, HReg src ); |
| 1077 | extern PPCInstr* PPCInstr_AvBinary ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
| 1078 | extern PPCInstr* PPCInstr_AvBin8x16 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
| 1079 | extern PPCInstr* PPCInstr_AvBin16x8 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
| 1080 | extern PPCInstr* PPCInstr_AvBin32x4 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 1081 | extern PPCInstr* PPCInstr_AvBin64x2 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
sewardj | e522d4b | 2011-04-26 21:36:09 +0000 | [diff] [blame] | 1082 | extern PPCInstr* PPCInstr_AvBin32Fx4 ( PPCAvFpOp op, HReg dst, HReg srcL, HReg srcR ); |
| 1083 | extern PPCInstr* PPCInstr_AvUn32Fx4 ( PPCAvFpOp op, HReg dst, HReg src ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1084 | extern PPCInstr* PPCInstr_AvPerm ( HReg dst, HReg srcL, HReg srcR, HReg ctl ); |
| 1085 | extern PPCInstr* PPCInstr_AvSel ( HReg ctl, HReg dst, HReg srcL, HReg srcR ); |
carll | 9877fe5 | 2014-10-07 17:49:14 +0000 | [diff] [blame] | 1086 | extern PPCInstr* PPCInstr_AvSh ( Bool shLeft, HReg dst, PPCAMode* am_addr ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1087 | extern PPCInstr* PPCInstr_AvShlDbl ( UChar shift, HReg dst, HReg srcL, HReg srcR ); |
| 1088 | extern PPCInstr* PPCInstr_AvSplat ( UChar sz, HReg dst, PPCVI5s* src ); |
| 1089 | extern PPCInstr* PPCInstr_AvCMov ( PPCCondCode, HReg dst, HReg src ); |
| 1090 | extern PPCInstr* PPCInstr_AvLdVSCR ( HReg src ); |
carll | 7deaf95 | 2013-10-15 18:11:20 +0000 | [diff] [blame] | 1091 | extern PPCInstr* PPCInstr_AvCipherV128Unary ( PPCAvOp op, HReg dst, |
| 1092 | HReg srcR ); |
| 1093 | extern PPCInstr* PPCInstr_AvCipherV128Binary ( PPCAvOp op, HReg dst, |
| 1094 | HReg srcL, HReg srcR ); |
| 1095 | extern PPCInstr* PPCInstr_AvHashV128Binary ( PPCAvOp op, HReg dst, |
| 1096 | HReg src, PPCRI* s_field ); |
| 1097 | extern PPCInstr* PPCInstr_AvBCDV128Trinary ( PPCAvOp op, HReg dst, |
| 1098 | HReg src1, HReg src2, |
| 1099 | PPCRI* ps ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1100 | extern PPCInstr* PPCInstr_Dfp64Unary ( PPCFpOp op, HReg dst, HReg src ); |
| 1101 | extern PPCInstr* PPCInstr_Dfp64Binary ( PPCFpOp op, HReg dst, HReg srcL, |
| 1102 | HReg srcR ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1103 | extern PPCInstr* PPCInstr_DfpShift ( PPCFpOp op, HReg dst, HReg src, |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1104 | PPCRI* shift ); |
sewardj | 26217b0 | 2012-04-12 17:19:48 +0000 | [diff] [blame] | 1105 | extern PPCInstr* PPCInstr_Dfp128Unary ( PPCFpOp op, HReg dst_hi, HReg dst_lo, |
| 1106 | HReg srcR_hi, HReg srcR_lo ); |
| 1107 | extern PPCInstr* PPCInstr_Dfp128Binary ( PPCFpOp op, HReg dst_hi, HReg dst_lo, |
| 1108 | HReg srcR_hi, HReg srcR_lo ); |
| 1109 | extern PPCInstr* PPCInstr_DfpShift128 ( PPCFpOp op, HReg dst_hi, HReg src_hi, |
| 1110 | HReg dst_lo, HReg src_lo, |
| 1111 | PPCRI* shift ); |
| 1112 | extern PPCInstr* PPCInstr_DfpD128toD64 ( PPCFpOp op, HReg dst, |
| 1113 | HReg dst_lo, HReg src_lo); |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1114 | extern PPCInstr* PPCInstr_DfpI64StoD128 ( PPCFpOp op, HReg dst_hi, |
| 1115 | HReg dst_lo, HReg src); |
| 1116 | extern PPCInstr* PPCInstr_DfpRound ( HReg dst, HReg src, PPCRI* r_rmc ); |
| 1117 | extern PPCInstr* PPCInstr_DfpRound128 ( HReg dst_hi, HReg dst_lo, HReg src_hi, |
| 1118 | HReg src_lo, PPCRI* r_rmc ); |
florian | a7b0d10 | 2012-06-15 20:55:43 +0000 | [diff] [blame] | 1119 | extern PPCInstr* PPCInstr_DfpQuantize ( PPCFpOp op, HReg dst, HReg srcL, |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1120 | HReg srcR, PPCRI* rmc ); |
florian | a7b0d10 | 2012-06-15 20:55:43 +0000 | [diff] [blame] | 1121 | extern PPCInstr* PPCInstr_DfpQuantize128 ( PPCFpOp op, HReg dst_hi, |
sewardj | cdc376d | 2012-04-23 11:21:12 +0000 | [diff] [blame] | 1122 | HReg dst_lo, |
| 1123 | HReg src_hi, |
| 1124 | HReg src_lo, PPCRI* rmc ); |
| 1125 | extern PPCInstr* PPCInstr_ExtractExpD128 ( PPCFpOp op, HReg dst, |
| 1126 | HReg src_hi, HReg src_lo ); |
| 1127 | extern PPCInstr* PPCInstr_InsertExpD128 ( PPCFpOp op, HReg dst_hi, |
| 1128 | HReg dst_lo, HReg srcL, |
| 1129 | HReg srcR_hi, HReg srcR_lo ); |
| 1130 | extern PPCInstr* PPCInstr_Dfp64Cmp ( HReg dst, HReg srcL, HReg srcR ); |
| 1131 | extern PPCInstr* PPCInstr_Dfp128Cmp ( HReg dst, HReg srcL_hi, HReg srcL_lo, |
| 1132 | HReg srcR_hi, HReg srcR_lo ); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1133 | extern PPCInstr* PPCInstr_EvCheck ( PPCAMode* amCounter, |
| 1134 | PPCAMode* amFailAddr ); |
| 1135 | extern PPCInstr* PPCInstr_ProfInc ( void ); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1136 | |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 1137 | extern void ppPPCInstr(const PPCInstr*, Bool mode64); |
sewardj | c6bbd47 | 2012-04-02 10:20:48 +0000 | [diff] [blame] | 1138 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1139 | |
| 1140 | /* Some functions that insulate the register allocator from details |
| 1141 | of the underlying instruction set. */ |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 1142 | extern void getRegUsage_PPCInstr ( HRegUsage*, const PPCInstr*, Bool mode64 ); |
| 1143 | extern void mapRegs_PPCInstr ( HRegRemap*, PPCInstr* , Bool mode64); |
| 1144 | extern Bool isMove_PPCInstr ( const PPCInstr*, HReg*, HReg* ); |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 1145 | extern Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 1146 | UChar* buf, Int nbuf, const PPCInstr* i, |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 1147 | Bool mode64, |
| 1148 | VexEndness endness_host, |
| 1149 | const void* disp_cp_chain_me_to_slowEP, |
| 1150 | const void* disp_cp_chain_me_to_fastEP, |
| 1151 | const void* disp_cp_xindir, |
| 1152 | const void* disp_cp_xassisted ); |
sewardj | 2a0cc85 | 2010-01-02 13:23:54 +0000 | [diff] [blame] | 1153 | |
| 1154 | extern void genSpill_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, |
| 1155 | HReg rreg, Int offsetB, Bool mode64 ); |
| 1156 | extern void genReload_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, |
| 1157 | HReg rreg, Int offsetB, Bool mode64 ); |
| 1158 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1159 | extern void getAllocableRegs_PPC ( Int*, HReg**, Bool mode64 ); |
florian | cacba8e | 2014-12-15 18:58:07 +0000 | [diff] [blame] | 1160 | extern HInstrArray* iselSB_PPC ( const IRSB*, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1161 | VexArch, |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 1162 | const VexArchInfo*, |
| 1163 | const VexAbiInfo*, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1164 | Int offs_Host_EvC_Counter, |
| 1165 | Int offs_Host_EvC_FailAddr, |
| 1166 | Bool chainingAllowed, |
| 1167 | Bool addProfInc, |
florian | dcd6d23 | 2015-01-02 17:32:21 +0000 | [diff] [blame] | 1168 | Addr max_ga ); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1169 | |
| 1170 | /* How big is an event check? This is kind of a kludge because it |
| 1171 | depends on the offsets of host_EvC_FAILADDR and |
| 1172 | host_EvC_COUNTER. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1173 | extern Int evCheckSzB_PPC ( VexEndness endness_host ); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1174 | |
| 1175 | /* Perform a chaining and unchaining of an XDirect jump. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1176 | extern VexInvalRange chainXDirect_PPC ( VexEndness endness_host, |
| 1177 | void* place_to_chain, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1178 | const void* disp_cp_chain_me_EXPECTED, |
| 1179 | const void* place_to_jump_to, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1180 | Bool mode64 ); |
| 1181 | |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1182 | extern VexInvalRange unchainXDirect_PPC ( VexEndness endness_host, |
| 1183 | void* place_to_unchain, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1184 | const void* place_to_jump_to_EXPECTED, |
| 1185 | const void* disp_cp_chain_me, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1186 | Bool mode64 ); |
| 1187 | |
| 1188 | /* Patch the counter location into an existing ProfInc point. */ |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1189 | extern VexInvalRange patchProfInc_PPC ( VexEndness endness_host, |
| 1190 | void* place_to_patch, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1191 | const ULong* location_of_counter, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1192 | Bool mode64 ); |
| 1193 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1194 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 1195 | #endif /* ndef __VEX_HOST_PPC_DEFS_H */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1196 | |
| 1197 | /*---------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 1198 | /*--- end host_ppc_defs.h ---*/ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1199 | /*---------------------------------------------------------------*/ |