sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1 | |
| 2 | /*--------------------------------------------------------------------*/ |
| 3 | /*--- The JITter proper: register allocation & code improvement ---*/ |
| 4 | /*--- vg_translate.c ---*/ |
| 5 | /*--------------------------------------------------------------------*/ |
| 6 | |
| 7 | /* |
njn | c953984 | 2002-10-02 13:26:35 +0000 | [diff] [blame] | 8 | This file is part of Valgrind, an extensible x86 protected-mode |
| 9 | emulator for monitoring program execution on x86-Unixes. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 10 | |
nethercote | bb1c991 | 2004-01-04 16:43:23 +0000 | [diff] [blame] | 11 | Copyright (C) 2000-2004 Julian Seward |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 12 | jseward@acm.org |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 13 | |
| 14 | This program is free software; you can redistribute it and/or |
| 15 | modify it under the terms of the GNU General Public License as |
| 16 | published by the Free Software Foundation; either version 2 of the |
| 17 | License, or (at your option) any later version. |
| 18 | |
| 19 | This program is distributed in the hope that it will be useful, but |
| 20 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 22 | General Public License for more details. |
| 23 | |
| 24 | You should have received a copy of the GNU General Public License |
| 25 | along with this program; if not, write to the Free Software |
| 26 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 27 | 02111-1307, USA. |
| 28 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 29 | The GNU General Public License is contained in the file COPYING. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 30 | */ |
| 31 | |
| 32 | #include "vg_include.h" |
| 33 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 34 | /*------------------------------------------------------------*/ |
| 35 | /*--- Renamings of frequently-used global functions. ---*/ |
| 36 | /*------------------------------------------------------------*/ |
| 37 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 38 | #define dis VG_(print_codegen) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 39 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 40 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 41 | /*------------------------------------------------------------*/ |
| 42 | /*--- Basics ---*/ |
| 43 | /*------------------------------------------------------------*/ |
| 44 | |
nethercote | 85cdd34 | 2004-08-01 22:36:40 +0000 | [diff] [blame] | 45 | #define VG_IS_FLAG_SUBSET(set1,set2) \ |
| 46 | (( ((FlagSet)set1) & ((FlagSet)set2) ) == ((FlagSet)set1) ) |
| 47 | |
| 48 | #define VG_UNION_FLAG_SETS(set1,set2) \ |
| 49 | ( ((FlagSet)set1) | ((FlagSet)set2) ) |
| 50 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 51 | /* This one is called by the core */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 52 | UCodeBlock* VG_(alloc_UCodeBlock) ( void ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 53 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 54 | UCodeBlock* cb = VG_(arena_malloc)(VG_AR_CORE, sizeof(UCodeBlock)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 55 | cb->used = cb->size = cb->nextTemp = 0; |
| 56 | cb->instrs = NULL; |
| 57 | return cb; |
| 58 | } |
| 59 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 60 | /* This one is called by skins */ |
| 61 | UCodeBlock* VG_(setup_UCodeBlock) ( UCodeBlock* cb_in ) |
| 62 | { |
| 63 | UCodeBlock* cb = VG_(arena_malloc)(VG_AR_CORE, sizeof(UCodeBlock)); |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 64 | cb->orig_eip = cb_in->orig_eip; |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 65 | cb->used = cb->size = 0; |
| 66 | cb->nextTemp = cb_in->nextTemp; |
| 67 | cb->instrs = NULL; |
| 68 | return cb; |
| 69 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 70 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 71 | void VG_(free_UCodeBlock) ( UCodeBlock* cb ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 72 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 73 | if (cb->instrs) VG_(arena_free)(VG_AR_CORE, cb->instrs); |
| 74 | VG_(arena_free)(VG_AR_CORE, cb); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | |
| 78 | /* Ensure there's enough space in a block to add one uinstr. */ |
daywalker | b18d253 | 2003-09-27 20:15:01 +0000 | [diff] [blame] | 79 | static |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 80 | void ensureUInstr ( UCodeBlock* cb ) |
| 81 | { |
| 82 | if (cb->used == cb->size) { |
| 83 | if (cb->instrs == NULL) { |
| 84 | vg_assert(cb->size == 0); |
| 85 | vg_assert(cb->used == 0); |
| 86 | cb->size = 8; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 87 | cb->instrs = VG_(arena_malloc)(VG_AR_CORE, 8 * sizeof(UInstr)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 88 | } else { |
| 89 | Int i; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 90 | UInstr* instrs2 = VG_(arena_malloc)(VG_AR_CORE, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 91 | 2 * sizeof(UInstr) * cb->size); |
| 92 | for (i = 0; i < cb->used; i++) |
| 93 | instrs2[i] = cb->instrs[i]; |
| 94 | cb->size *= 2; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 95 | VG_(arena_free)(VG_AR_CORE, cb->instrs); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 96 | cb->instrs = instrs2; |
| 97 | } |
| 98 | } |
| 99 | |
| 100 | vg_assert(cb->used < cb->size); |
| 101 | } |
| 102 | |
| 103 | |
| 104 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 105 | void VG_(new_NOP) ( UInstr* u ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 106 | { |
| 107 | u->val1 = u->val2 = u->val3 = 0; |
| 108 | u->tag1 = u->tag2 = u->tag3 = NoValue; |
| 109 | u->flags_r = u->flags_w = FlagsEmpty; |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 110 | u->jmpkind = JmpBoring; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 111 | u->signed_widen = u->has_ret_val = False; |
| 112 | u->regs_live_after = ALL_RREGS_LIVE; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 113 | u->lit32 = 0; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 114 | u->opcode = NOP; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 115 | u->size = 0; |
| 116 | u->cond = 0; |
| 117 | u->extra4b = 0; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 118 | u->argc = u->regparms_n = 0; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | |
| 122 | /* Add an instruction to a ucode block, and return the index of the |
| 123 | instruction. */ |
| 124 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 125 | void VG_(new_UInstr3) ( UCodeBlock* cb, Opcode opcode, Int sz, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 126 | Tag tag1, UInt val1, |
| 127 | Tag tag2, UInt val2, |
| 128 | Tag tag3, UInt val3 ) |
| 129 | { |
| 130 | UInstr* ui; |
| 131 | ensureUInstr(cb); |
| 132 | ui = & cb->instrs[cb->used]; |
| 133 | cb->used++; |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 134 | VG_(new_NOP)(ui); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 135 | ui->val1 = val1; |
| 136 | ui->val2 = val2; |
| 137 | ui->val3 = val3; |
| 138 | ui->opcode = opcode; |
| 139 | ui->tag1 = tag1; |
| 140 | ui->tag2 = tag2; |
| 141 | ui->tag3 = tag3; |
| 142 | ui->size = sz; |
| 143 | if (tag1 == TempReg) vg_assert(val1 != INVALID_TEMPREG); |
| 144 | if (tag2 == TempReg) vg_assert(val2 != INVALID_TEMPREG); |
| 145 | if (tag3 == TempReg) vg_assert(val3 != INVALID_TEMPREG); |
| 146 | } |
| 147 | |
| 148 | |
| 149 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 150 | void VG_(new_UInstr2) ( UCodeBlock* cb, Opcode opcode, Int sz, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 151 | Tag tag1, UInt val1, |
| 152 | Tag tag2, UInt val2 ) |
| 153 | { |
| 154 | UInstr* ui; |
| 155 | ensureUInstr(cb); |
| 156 | ui = & cb->instrs[cb->used]; |
| 157 | cb->used++; |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 158 | VG_(new_NOP)(ui); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 159 | ui->val1 = val1; |
| 160 | ui->val2 = val2; |
| 161 | ui->opcode = opcode; |
| 162 | ui->tag1 = tag1; |
| 163 | ui->tag2 = tag2; |
| 164 | ui->size = sz; |
| 165 | if (tag1 == TempReg) vg_assert(val1 != INVALID_TEMPREG); |
| 166 | if (tag2 == TempReg) vg_assert(val2 != INVALID_TEMPREG); |
| 167 | } |
| 168 | |
| 169 | |
| 170 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 171 | void VG_(new_UInstr1) ( UCodeBlock* cb, Opcode opcode, Int sz, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 172 | Tag tag1, UInt val1 ) |
| 173 | { |
| 174 | UInstr* ui; |
| 175 | ensureUInstr(cb); |
| 176 | ui = & cb->instrs[cb->used]; |
| 177 | cb->used++; |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 178 | VG_(new_NOP)(ui); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 179 | ui->val1 = val1; |
| 180 | ui->opcode = opcode; |
| 181 | ui->tag1 = tag1; |
| 182 | ui->size = sz; |
| 183 | if (tag1 == TempReg) vg_assert(val1 != INVALID_TEMPREG); |
| 184 | } |
| 185 | |
| 186 | |
| 187 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 188 | void VG_(new_UInstr0) ( UCodeBlock* cb, Opcode opcode, Int sz ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 189 | { |
| 190 | UInstr* ui; |
| 191 | ensureUInstr(cb); |
| 192 | ui = & cb->instrs[cb->used]; |
| 193 | cb->used++; |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 194 | VG_(new_NOP)(ui); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 195 | ui->opcode = opcode; |
| 196 | ui->size = sz; |
| 197 | } |
| 198 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 199 | /* Copy an instruction into the given codeblock. */ |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 200 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 201 | void VG_(copy_UInstr) ( UCodeBlock* cb, UInstr* instr ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 202 | { |
| 203 | ensureUInstr(cb); |
| 204 | cb->instrs[cb->used] = *instr; |
| 205 | cb->used++; |
| 206 | } |
| 207 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 208 | /* Set the lit32 field of the most recent uinsn. */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 209 | void VG_(set_lit_field) ( UCodeBlock* cb, UInt lit32 ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 210 | { |
| 211 | LAST_UINSTR(cb).lit32 = lit32; |
| 212 | } |
| 213 | |
| 214 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 215 | /* Set the C call info fields of the most recent uinsn. */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 216 | void VG_(set_ccall_fields) ( UCodeBlock* cb, Addr fn, UChar argc, UChar |
| 217 | regparms_n, Bool has_ret_val ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 218 | { |
| 219 | vg_assert(argc < 4); |
| 220 | vg_assert(regparms_n <= argc); |
| 221 | LAST_UINSTR(cb).lit32 = fn; |
| 222 | LAST_UINSTR(cb).argc = argc; |
| 223 | LAST_UINSTR(cb).regparms_n = regparms_n; |
| 224 | LAST_UINSTR(cb).has_ret_val = has_ret_val; |
| 225 | } |
| 226 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 227 | /* For the last uinsn inserted into cb, set the read, written and |
| 228 | undefined flags. Undefined flags are counted as written, but it |
| 229 | seems worthwhile to distinguish them. |
| 230 | */ |
| 231 | __inline__ |
| 232 | void VG_(set_flag_fields) ( UCodeBlock* cb, |
| 233 | FlagSet rr, FlagSet ww, FlagSet uu ) |
| 234 | { |
| 235 | FlagSet uw = VG_UNION_FLAG_SETS(ww,uu); |
| 236 | |
| 237 | vg_assert(rr == (rr & FlagsALL)); |
| 238 | vg_assert(uw == (uw & FlagsALL)); |
| 239 | LAST_UINSTR(cb).flags_r = rr; |
| 240 | LAST_UINSTR(cb).flags_w = uw; |
| 241 | } |
| 242 | |
nethercote | 911cc37 | 2004-04-18 12:23:02 +0000 | [diff] [blame] | 243 | void VG_(set_cond_field) ( UCodeBlock* cb, Condcode cond ) |
| 244 | { |
| 245 | LAST_UINSTR(cb).cond = cond; |
| 246 | } |
| 247 | |
| 248 | void VG_(set_widen_fields) ( UCodeBlock* cb, UInt szs, Bool is_signed ) |
| 249 | { |
| 250 | LAST_UINSTR(cb).extra4b = szs; |
| 251 | LAST_UINSTR(cb).signed_widen = is_signed; |
| 252 | } |
| 253 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 254 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 255 | Bool VG_(any_flag_use) ( UInstr* u ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 256 | { |
| 257 | return (u->flags_r != FlagsEmpty |
| 258 | || u->flags_w != FlagsEmpty); |
| 259 | } |
| 260 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 261 | #if 1 |
| 262 | # define BEST_ALLOC_ORDER |
| 263 | #endif |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 264 | |
| 265 | /* Convert a rank in the range 0 .. VG_MAX_REALREGS-1 into an Intel |
| 266 | register number. This effectively defines the order in which real |
| 267 | registers are allocated. %ebp is excluded since it is permanently |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 268 | reserved for pointing at VG_(baseBlock). |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 269 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 270 | Important! This function must correspond with the value of |
| 271 | VG_MAX_REALREGS (actually, VG_MAX_REALREGS can be reduced without |
| 272 | a problem, except the generated code will obviously be worse). |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 273 | */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 274 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 275 | Int VG_(rank_to_realreg) ( Int rank ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 276 | { |
| 277 | switch (rank) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 278 | # ifdef BEST_ALLOC_ORDER |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 279 | /* Probably the best allocation ordering. */ |
| 280 | case 0: return R_EAX; |
| 281 | case 1: return R_EBX; |
| 282 | case 2: return R_ECX; |
| 283 | case 3: return R_EDX; |
| 284 | case 4: return R_ESI; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 285 | case 5: return R_EDI; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 286 | # else |
| 287 | /* Contrary; probably the worst. Helpful for debugging, tho. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 288 | case 5: return R_EAX; |
| 289 | case 4: return R_EBX; |
| 290 | case 3: return R_ECX; |
| 291 | case 2: return R_EDX; |
| 292 | case 1: return R_ESI; |
| 293 | case 0: return R_EDI; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 294 | # endif |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 295 | default: VG_(core_panic)("VG_(rank_to_realreg)"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 296 | } |
| 297 | } |
| 298 | |
| 299 | /* Convert an Intel register number into a rank in the range 0 .. |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 300 | VG_MAX_REALREGS-1. See related comments for rank_to_realreg() |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 301 | above. */ |
| 302 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 303 | Int VG_(realreg_to_rank) ( Int realReg ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 304 | { |
| 305 | switch (realReg) { |
| 306 | # ifdef BEST_ALLOC_ORDER |
| 307 | case R_EAX: return 0; |
| 308 | case R_EBX: return 1; |
| 309 | case R_ECX: return 2; |
| 310 | case R_EDX: return 3; |
| 311 | case R_ESI: return 4; |
| 312 | case R_EDI: return 5; |
| 313 | # else |
| 314 | case R_EAX: return 5; |
| 315 | case R_EBX: return 4; |
| 316 | case R_ECX: return 3; |
| 317 | case R_EDX: return 2; |
| 318 | case R_ESI: return 1; |
| 319 | case R_EDI: return 0; |
| 320 | # endif |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 321 | default: VG_(core_panic)("VG_(realreg_to_rank)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 322 | } |
| 323 | } |
| 324 | |
| 325 | |
| 326 | /*------------------------------------------------------------*/ |
| 327 | /*--- Sanity checking uinstrs. ---*/ |
| 328 | /*------------------------------------------------------------*/ |
| 329 | |
| 330 | /* This seems as good a place as any to record some important stuff |
| 331 | about ucode semantics. |
| 332 | |
| 333 | * TempRegs are 32 bits wide. LOADs of 8/16 bit values into a |
| 334 | TempReg are defined to zero-extend the loaded value to 32 bits. |
| 335 | This is needed to make the translation of movzbl et al work |
| 336 | properly. |
| 337 | |
| 338 | * Similarly, GETs of a 8/16 bit ArchRegs are zero-extended. |
| 339 | |
| 340 | * Arithmetic on TempRegs is at the specified size. For example, |
| 341 | SUBW t1, t2 has to result in a real 16 bit x86 subtraction |
| 342 | being emitted -- not a 32 bit one. |
| 343 | |
| 344 | * On some insns we allow the cc bit to be set. If so, the |
| 345 | intention is that the simulated machine's %eflags register |
| 346 | is copied into that of the real machine before the insn, |
| 347 | and copied back again afterwards. This means that the |
| 348 | code generated for that insn must be very careful only to |
| 349 | update %eflags in the intended way. This is particularly |
| 350 | important for the routines referenced by CALL insns. |
| 351 | */ |
| 352 | |
| 353 | /* Meaning of operand kinds is as follows: |
| 354 | |
| 355 | ArchReg is a register of the simulated CPU, stored in memory, |
| 356 | in vg_m_state.m_eax .. m_edi. These values are stored |
| 357 | using the Intel register encoding. |
| 358 | |
| 359 | RealReg is a register of the real CPU. There are VG_MAX_REALREGS |
| 360 | available for allocation. As with ArchRegs, these values |
| 361 | are stored using the Intel register encoding. |
| 362 | |
| 363 | TempReg is a temporary register used to express the results of |
| 364 | disassembly. There is an unlimited supply of them -- |
| 365 | register allocation and spilling eventually assigns them |
| 366 | to RealRegs. |
| 367 | |
| 368 | SpillNo is a spill slot number. The number of required spill |
| 369 | slots is VG_MAX_PSEUDOS, in general. Only allowed |
| 370 | as the ArchReg operand of GET and PUT. |
| 371 | |
| 372 | Lit16 is a signed 16-bit literal value. |
| 373 | |
| 374 | Literal is a 32-bit literal value. Each uinstr can only hold |
| 375 | one of these. |
| 376 | |
| 377 | The disassembled code is expressed purely in terms of ArchReg, |
| 378 | TempReg and Literal operands. Eventually, register allocation |
| 379 | removes all the TempRegs, giving a result using ArchRegs, RealRegs, |
| 380 | and Literals. New x86 code can easily be synthesised from this. |
| 381 | There are carefully designed restrictions on which insns can have |
| 382 | which operands, intended to make it possible to generate x86 code |
| 383 | from the result of register allocation on the ucode efficiently and |
| 384 | without need of any further RealRegs. |
| 385 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 386 | Restrictions for the individual UInstrs are clear from the checks below. |
| 387 | Abbreviations: A=ArchReg S=SpillNo T=TempReg L=Literal |
| 388 | Ls=Lit16 R=RealReg N=NoValue |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 389 | As=ArchRegS |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 390 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 391 | Before register allocation, S operands should not appear anywhere. |
| 392 | After register allocation, all T operands should have been |
| 393 | converted into Rs, and S operands are allowed in GET and PUT -- |
| 394 | denoting spill saves/restores. |
| 395 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 396 | Before liveness analysis, save_e[acd]x fields should all be True. |
| 397 | Afterwards, they may be False. |
| 398 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 399 | The size field should be 0 for insns for which it is meaningless, |
| 400 | ie those which do not directly move/operate on data. |
| 401 | */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 402 | Bool VG_(saneUInstr) ( Bool beforeRA, Bool beforeLiveness, UInstr* u ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 403 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 404 | # define LIT0 (u->lit32 == 0) |
sewardj | b31b06d | 2003-06-13 00:26:02 +0000 | [diff] [blame] | 405 | # define LIT8 (((u->lit32) & 0xFFFFFF00) == 0) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 406 | # define LIT1 (!(LIT0)) |
| 407 | # define LITm (u->tag1 == Literal ? True : LIT0 ) |
sewardj | 77d30a2 | 2003-10-19 08:18:52 +0000 | [diff] [blame] | 408 | # define SZ16 (u->size == 16) |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 409 | # define SZ8 (u->size == 8) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 410 | # define SZ4 (u->size == 4) |
| 411 | # define SZ2 (u->size == 2) |
| 412 | # define SZ1 (u->size == 1) |
| 413 | # define SZ0 (u->size == 0) |
| 414 | # define SZ42 (u->size == 4 || u->size == 2) |
sewardj | d797101 | 2003-04-04 00:21:58 +0000 | [diff] [blame] | 415 | # define SZ48 (u->size == 4 || u->size == 8) |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 416 | # define SZ416 (u->size == 4 || u->size == 16) |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 417 | # define SZ816 (u->size == 8 || u->size == 16) |
| 418 | # define SZsse2 (u->size == 4 || u->size == 8 || u->size == 16 || u->size == 512) |
jseward | fca6018 | 2004-01-04 23:30:55 +0000 | [diff] [blame] | 419 | # define SZsse3 (u->size == 4 || u->size == 8 || u->size == 16) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 420 | # define SZi (u->size == 4 || u->size == 2 || u->size == 1) |
| 421 | # define SZf ( u->size == 4 || u->size == 8 || u->size == 2 \ |
| 422 | || u->size == 10 || u->size == 28 || u->size == 108) |
| 423 | # define SZ4m ((u->tag1 == TempReg || u->tag1 == RealReg) \ |
nethercote | afa17ef | 2004-04-26 09:21:25 +0000 | [diff] [blame] | 424 | ? (u->size == 4) : SZi) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 425 | |
| 426 | /* For these ones, two cases: |
| 427 | * |
| 428 | * 1. They are transliterations of the corresponding x86 instruction, in |
| 429 | * which case they should have its flags (except that redundant write |
| 430 | * flags can be annulled by the optimisation pass). |
| 431 | * |
| 432 | * 2. They are being used generally for other purposes, eg. helping with a |
| 433 | * 'rep'-prefixed instruction, in which case should have empty flags . |
| 434 | */ |
| 435 | # define emptyR (u->flags_r == FlagsEmpty) |
| 436 | # define emptyW (u->flags_w == FlagsEmpty) |
| 437 | # define CC0 (emptyR && emptyW) |
| 438 | # define CCr (u->flags_r == FlagsALL && emptyW) |
| 439 | # define CCw (emptyR && u->flags_w == FlagsALL) |
| 440 | # define CCa (emptyR && (u->flags_w == FlagsOSZACP || emptyW)) |
| 441 | # define CCc (emptyR && (u->flags_w == FlagsOC || emptyW)) |
| 442 | # define CCe (emptyR && (u->flags_w == FlagsOSZAP || emptyW)) |
| 443 | # define CCb ((u->flags_r==FlagC || emptyR) && \ |
| 444 | (u->flags_w==FlagsOSZACP || emptyW)) |
| 445 | # define CCd ((u->flags_r==FlagC || emptyR) && \ |
| 446 | (u->flags_w==FlagsOC || emptyW)) |
sewardj | c232b21 | 2002-12-10 22:24:03 +0000 | [diff] [blame] | 447 | # define CCf (CC0 || (emptyR && u->flags_w==FlagsZCP) \ |
| 448 | || (u->flags_r==FlagsZCP && emptyW)) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 449 | # define CCg ((u->flags_r==FlagsOSZACP || emptyR) && emptyW) |
| 450 | # define CCj (u->cond==CondAlways ? CC0 : CCg) |
| 451 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 452 | # define TR1 (beforeRA ? (u->tag1 == TempReg) : (u->tag1 == RealReg)) |
| 453 | # define TR2 (beforeRA ? (u->tag2 == TempReg) : (u->tag2 == RealReg)) |
| 454 | # define TR3 (beforeRA ? (u->tag3 == TempReg) : (u->tag3 == RealReg)) |
| 455 | # define A1 (u->tag1 == ArchReg) |
| 456 | # define A2 (u->tag2 == ArchReg) |
| 457 | # define AS1 ((u->tag1 == ArchReg) || ((!beforeRA && (u->tag1 == SpillNo)))) |
| 458 | # define AS2 ((u->tag2 == ArchReg) || ((!beforeRA && (u->tag2 == SpillNo)))) |
| 459 | # define AS3 ((u->tag3 == ArchReg) || ((!beforeRA && (u->tag3 == SpillNo)))) |
| 460 | # define L1 (u->tag1 == Literal && u->val1 == 0) |
| 461 | # define L2 (u->tag2 == Literal && u->val2 == 0) |
| 462 | # define Ls1 (u->tag1 == Lit16) |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 463 | # define Ls2 (u->tag2 == Lit16) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 464 | # define Ls3 (u->tag3 == Lit16) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 465 | # define TRL1 (TR1 || L1) |
| 466 | # define TRAL1 (TR1 || A1 || L1) |
jsgf | 5efa4fd | 2003-10-14 21:49:11 +0000 | [diff] [blame] | 467 | # define TRA1 (TR1 || A1) |
| 468 | # define TRA2 (TR2 || A2) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 469 | # define N1 (u->tag1 == NoValue) |
| 470 | # define N2 (u->tag2 == NoValue) |
| 471 | # define N3 (u->tag3 == NoValue) |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 472 | # define Se1 (u->tag1 == ArchRegS) |
| 473 | # define Se2 (u->tag2 == ArchRegS) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 474 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 475 | # define COND0 (u->cond == 0) |
| 476 | # define EXTRA4b0 (u->extra4b == 0) |
nethercote | 4a12dbd | 2004-04-16 16:16:34 +0000 | [diff] [blame] | 477 | # define EXTRA4b12 (u->extra4b == 1 || u->extra4b == 2) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 478 | # define SG_WD0 (u->signed_widen == 0) |
| 479 | # define JMPKIND0 (u->jmpkind == 0) |
| 480 | # define CCALL0 (u->argc==0 && u->regparms_n==0 && u->has_ret_val==0 && \ |
| 481 | ( beforeLiveness \ |
| 482 | ? u->regs_live_after == ALL_RREGS_LIVE \ |
| 483 | : True )) |
| 484 | |
| 485 | # define XCONDi ( EXTRA4b0 && SG_WD0 && JMPKIND0 && CCALL0) |
nethercote | 4a12dbd | 2004-04-16 16:16:34 +0000 | [diff] [blame] | 486 | # define XLEA2 (COND0 && SG_WD0 && JMPKIND0 && CCALL0) |
| 487 | # define XWIDEN (COND0 && EXTRA4b12 && JMPKIND0 && CCALL0) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 488 | # define XJMP ( SG_WD0 && CCALL0) |
| 489 | # define XCCALL (COND0 && EXTRA4b0 && SG_WD0 && JMPKIND0 ) |
| 490 | # define XOTHER (COND0 && EXTRA4b0 && SG_WD0 && JMPKIND0 && CCALL0) |
| 491 | |
| 492 | /* 0 or 1 Literal args per UInstr */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 493 | Int n_lits = 0; |
| 494 | if (u->tag1 == Literal) n_lits++; |
| 495 | if (u->tag2 == Literal) n_lits++; |
| 496 | if (u->tag3 == Literal) n_lits++; |
| 497 | if (n_lits > 1) |
| 498 | return False; |
| 499 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 500 | /* Fields not checked: val1, val2, val3 */ |
| 501 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 502 | switch (u->opcode) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 503 | |
| 504 | /* Fields checked: lit32 size flags_r/w tag1 tag2 tag3 (rest) */ |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 505 | case PUTSEG: return LIT0 && SZ2 && CC0 && TR1 && Se2 && N3 && XOTHER; |
| 506 | case GETSEG: return LIT0 && SZ2 && CC0 && Se1 && TR2 && N3 && XOTHER; |
| 507 | case USESEG: return LIT0 && SZ0 && CC0 && TR1 && TR2 && N3 && XOTHER; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 508 | case NOP: return LIT0 && SZ0 && CC0 && N1 && N2 && N3 && XOTHER; |
sewardj | 7a5ebcf | 2002-11-13 22:42:13 +0000 | [diff] [blame] | 509 | case LOCK: return LIT0 && SZ0 && CC0 && N1 && N2 && N3 && XOTHER; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 510 | case GETF: return LIT0 && SZ42 && CCr && TR1 && N2 && N3 && XOTHER; |
| 511 | case PUTF: return LIT0 && SZ42 && CCw && TR1 && N2 && N3 && XOTHER; |
| 512 | case GET: return LIT0 && SZi && CC0 && AS1 && TR2 && N3 && XOTHER; |
| 513 | case PUT: return LIT0 && SZi && CC0 && TR1 && AS2 && N3 && XOTHER; |
| 514 | case LOAD: |
| 515 | case STORE: return LIT0 && SZi && CC0 && TR1 && TR2 && N3 && XOTHER; |
| 516 | case MOV: return LITm && SZ4m && CC0 && TRL1 && TR2 && N3 && XOTHER; |
| 517 | case CMOV: return LIT0 && SZ4 && CCg && TR1 && TR2 && N3 && XCONDi; |
njn | 95bc386 | 2003-09-30 13:22:30 +0000 | [diff] [blame] | 518 | case WIDEN: return LIT0 && SZ42 && CC0 && TR1 && N2 && N3 && XWIDEN; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 519 | case JMP: return LITm && SZ0 && CCj && TRL1 && N2 && N3 && XJMP; |
| 520 | case CALLM: return LIT0 && SZ0 /*any*/ && Ls1 && N2 && N3 && XOTHER; |
| 521 | case CALLM_S: |
| 522 | case CALLM_E:return LIT0 && SZ0 && CC0 && N1 && N2 && N3 && XOTHER; |
| 523 | case PUSH: |
| 524 | case POP: return LIT0 && SZi && CC0 && TR1 && N2 && N3 && XOTHER; |
| 525 | case CLEAR: return LIT0 && SZ0 && CC0 && Ls1 && N2 && N3 && XOTHER; |
| 526 | case AND: |
| 527 | case OR: return LIT0 && SZi && CCa && TR1 && TR2 && N3 && XOTHER; |
jsgf | 5efa4fd | 2003-10-14 21:49:11 +0000 | [diff] [blame] | 528 | case MUL: return LIT0 && SZ42 && CCa && TRA1 &&TRA2 && N3 && XOTHER; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 529 | case ADD: |
| 530 | case XOR: |
| 531 | case SUB: return LITm && SZi && CCa &&TRAL1 && TR2 && N3 && XOTHER; |
| 532 | case SBB: |
| 533 | case ADC: return LITm && SZi && CCb &&TRAL1 && TR2 && N3 && XOTHER; |
| 534 | case SHL: |
| 535 | case SHR: |
| 536 | case SAR: return LITm && SZi && CCa && TRL1 && TR2 && N3 && XOTHER; |
| 537 | case ROL: |
| 538 | case ROR: return LITm && SZi && CCc && TRL1 && TR2 && N3 && XOTHER; |
| 539 | case RCL: |
| 540 | case RCR: return LITm && SZi && CCd && TRL1 && TR2 && N3 && XOTHER; |
| 541 | case NOT: return LIT0 && SZi && CC0 && TR1 && N2 && N3 && XOTHER; |
| 542 | case NEG: return LIT0 && SZi && CCa && TR1 && N2 && N3 && XOTHER; |
| 543 | case INC: |
| 544 | case DEC: return LIT0 && SZi && CCe && TR1 && N2 && N3 && XOTHER; |
| 545 | case CC2VAL: return LIT0 && SZ1 && CCg && TR1 && N2 && N3 && XCONDi; |
| 546 | case BSWAP: return LIT0 && SZ4 && CC0 && TR1 && N2 && N3 && XOTHER; |
| 547 | case JIFZ: return LIT1 && SZ4 && CC0 && TR1 && L2 && N3 && XOTHER; |
| 548 | case FPU_R: |
| 549 | case FPU_W: return LIT0 && SZf && CC0 && Ls1 && TR2 && N3 && XOTHER; |
| 550 | case FPU: return LIT0 && SZ0 && CCf && Ls1 && N2 && N3 && XOTHER; |
| 551 | case LEA1: return /*any*/ SZ4 && CC0 && TR1 && TR2 && N3 && XOTHER; |
nethercote | 4a12dbd | 2004-04-16 16:16:34 +0000 | [diff] [blame] | 552 | case LEA2: return /*any*/ SZ4 && CC0 && TR1 && TR2 && TR3 && XLEA2; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 553 | case INCEIP: return LIT0 && SZ0 && CC0 && Ls1 && N2 && N3 && XOTHER; |
| 554 | case CCALL: return LIT1 && SZ0 && CC0 && |
| 555 | (u->argc > 0 ? TR1 : N1) && |
| 556 | (u->argc > 1 ? TR2 : N2) && |
| 557 | (u->argc > 2 || u->has_ret_val ? TR3 : N3) && |
| 558 | u->regparms_n <= u->argc && XCCALL; |
thughes | 96b466a | 2004-03-15 16:43:58 +0000 | [diff] [blame] | 559 | /* Fields checked: lit32 size flags_r/w tag1 tag2 tag3 (rest) */ |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 560 | case MMX1: |
thughes | 96b466a | 2004-03-15 16:43:58 +0000 | [diff] [blame] | 561 | case MMX2: return LIT0 && SZ0 && CC0 && Ls1 && N2 && N3 && XOTHER; |
| 562 | case MMX3: return LIT0 && SZ0 && CC0 && Ls1 && Ls2 && N3 && XOTHER; |
| 563 | case MMX2_MemRd: return LIT0 && SZ48 && CC0 && Ls1 && TR2 && N3 && XOTHER; |
| 564 | case MMX2_MemWr: return LIT0 && SZ48 && CC0 && Ls1 && TR2 && N3 && XOTHER; |
| 565 | case MMX2a1_MemRd: return LIT0 && SZ8 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 566 | case MMX2_ERegRd: return LIT0 && SZ4 && CC0 && Ls1 && TR2 && N3 && XOTHER; |
| 567 | case MMX2_ERegWr: return LIT0 && SZ4 && CC0 && Ls1 && TR2 && N3 && XOTHER; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 568 | |
| 569 | /* Fields checked: lit32 size flags_r/w tag1 tag2 tag3 (rest) */ |
jseward | fca6018 | 2004-01-04 23:30:55 +0000 | [diff] [blame] | 570 | case SSE2a_MemWr: return LIT0 && SZsse2 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 571 | case SSE2a_MemRd: return LIT0 && SZsse2 && CCa && Ls1 && Ls2 && TR3 && XOTHER; |
nethercote | 1018bdd | 2004-02-11 23:33:29 +0000 | [diff] [blame] | 572 | case SSE2a1_MemRd: return LIT0 && SZsse3 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 573 | case SSE2g_RegWr: return LIT0 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 574 | case SSE2g1_RegWr: return LIT8 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 575 | case SSE2e1_RegRd: return LIT8 && SZ2 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
jseward | fca6018 | 2004-01-04 23:30:55 +0000 | [diff] [blame] | 576 | case SSE3a_MemWr: return LIT0 && SZsse3 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 577 | case SSE3a_MemRd: return LIT0 && SZsse3 && CCa && Ls1 && Ls2 && TR3 && XOTHER; |
| 578 | case SSE3e_RegRd: return LIT0 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 579 | case SSE3e_RegWr: return LIT0 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 580 | case SSE3a1_MemRd: return LIT8 && SZ816 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
jseward | fca6018 | 2004-01-04 23:30:55 +0000 | [diff] [blame] | 581 | case SSE3g_RegWr: return LIT0 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 582 | case SSE3g1_RegWr: return LIT8 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 583 | case SSE3e1_RegRd: return LIT8 && SZ2 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 584 | case SSE3: return LIT0 && SZ0 && CCa && Ls1 && Ls2 && N3 && XOTHER; |
| 585 | case SSE4: return LIT0 && SZ0 && CCa && Ls1 && Ls2 && N3 && XOTHER; |
| 586 | case SSE5: return LIT0 && SZ0 && CC0 && Ls1 && Ls2 && Ls3 && XOTHER; |
sewardj | e3891fa | 2003-06-15 03:13:48 +0000 | [diff] [blame] | 587 | case SSE3ag_MemRd_RegWr: |
jseward | fca6018 | 2004-01-04 23:30:55 +0000 | [diff] [blame] | 588 | return SZ48 && CC0 && TR1 && TR2 && N3 && XOTHER; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 589 | default: |
| 590 | if (VG_(needs).extended_UCode) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 591 | return SK_(sane_XUInstr)(beforeRA, beforeLiveness, u); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 592 | else { |
| 593 | VG_(printf)("unhandled opcode: %u. Perhaps " |
| 594 | "VG_(needs).extended_UCode should be set?", |
| 595 | u->opcode); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 596 | VG_(core_panic)("VG_(saneUInstr): unhandled opcode"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 597 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 598 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 599 | # undef LIT0 |
| 600 | # undef LIT1 |
sewardj | b31b06d | 2003-06-13 00:26:02 +0000 | [diff] [blame] | 601 | # undef LIT8 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 602 | # undef LITm |
sewardj | 77d30a2 | 2003-10-19 08:18:52 +0000 | [diff] [blame] | 603 | # undef SZ16 |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 604 | # undef SZ8 |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 605 | # undef SZ4 |
| 606 | # undef SZ2 |
| 607 | # undef SZ1 |
| 608 | # undef SZ0 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 609 | # undef SZ42 |
sewardj | d797101 | 2003-04-04 00:21:58 +0000 | [diff] [blame] | 610 | # undef SZ48 |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 611 | # undef SZ416 |
nethercote | 4a12dbd | 2004-04-16 16:16:34 +0000 | [diff] [blame] | 612 | # undef SZ816 |
jseward | fca6018 | 2004-01-04 23:30:55 +0000 | [diff] [blame] | 613 | # undef SZsse2 |
| 614 | # undef SZsse3 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 615 | # undef SZi |
| 616 | # undef SZf |
| 617 | # undef SZ4m |
| 618 | # undef emptyR |
| 619 | # undef emptyW |
| 620 | # undef CC0 |
| 621 | # undef CCr |
| 622 | # undef CCw |
| 623 | # undef CCa |
| 624 | # undef CCb |
| 625 | # undef CCc |
| 626 | # undef CCd |
| 627 | # undef CCe |
| 628 | # undef CCf |
| 629 | # undef CCg |
| 630 | # undef CCj |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 631 | # undef TR1 |
| 632 | # undef TR2 |
| 633 | # undef TR3 |
| 634 | # undef A1 |
| 635 | # undef A2 |
| 636 | # undef AS1 |
| 637 | # undef AS2 |
| 638 | # undef AS3 |
| 639 | # undef L1 |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 640 | # undef L2 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 641 | # undef Ls1 |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 642 | # undef Ls2 |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 643 | # undef Ls3 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 644 | # undef TRL1 |
| 645 | # undef TRAL1 |
nethercote | 4a12dbd | 2004-04-16 16:16:34 +0000 | [diff] [blame] | 646 | # undef TRA1 |
| 647 | # undef TRA2 |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 648 | # undef N1 |
| 649 | # undef N2 |
| 650 | # undef N3 |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 651 | # undef Se2 |
| 652 | # undef Se1 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 653 | # undef COND0 |
| 654 | # undef EXTRA4b0 |
nethercote | 4a12dbd | 2004-04-16 16:16:34 +0000 | [diff] [blame] | 655 | # undef EXTRA4b12 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 656 | # undef SG_WD0 |
| 657 | # undef JMPKIND0 |
| 658 | # undef CCALL0 |
nethercote | 4a12dbd | 2004-04-16 16:16:34 +0000 | [diff] [blame] | 659 | # undef XCONDi |
| 660 | # undef XLEA2 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 661 | # undef XWIDEN |
| 662 | # undef XJMP |
| 663 | # undef XCCALL |
| 664 | # undef XOTHER |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 665 | } |
| 666 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 667 | void VG_(saneUCodeBlock) ( UCodeBlock* cb ) |
| 668 | { |
| 669 | Int i; |
| 670 | |
| 671 | for (i = 0; i < cb->used; i++) { |
| 672 | Bool sane = VG_(saneUInstr)(True, True, &cb->instrs[i]); |
| 673 | if (!sane) { |
| 674 | VG_(printf)("Instruction failed sanity check:\n"); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 675 | VG_(up_UInstr)(i, &cb->instrs[i]); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 676 | } |
| 677 | vg_assert(sane); |
| 678 | } |
| 679 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 680 | |
| 681 | /* Sanity checks to do with CALLMs in UCodeBlocks. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 682 | Bool VG_(saneUCodeBlockCalls) ( UCodeBlock* cb ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 683 | { |
| 684 | Int callm = 0; |
| 685 | Int callm_s = 0; |
| 686 | Int callm_e = 0; |
| 687 | Int callm_ptr, calls_ptr; |
| 688 | Int i, j, t; |
| 689 | Bool incall = False; |
| 690 | |
| 691 | /* Ensure the number of CALLM, CALLM_S and CALLM_E are the same. */ |
| 692 | |
| 693 | for (i = 0; i < cb->used; i++) { |
| 694 | switch (cb->instrs[i].opcode) { |
| 695 | case CALLM: |
| 696 | if (!incall) return False; |
| 697 | callm++; |
| 698 | break; |
| 699 | case CALLM_S: |
| 700 | if (incall) return False; |
| 701 | incall = True; |
| 702 | callm_s++; |
| 703 | break; |
| 704 | case CALLM_E: |
| 705 | if (!incall) return False; |
| 706 | incall = False; |
| 707 | callm_e++; |
| 708 | break; |
| 709 | case PUSH: case POP: case CLEAR: |
| 710 | if (!incall) return False; |
| 711 | break; |
| 712 | default: |
| 713 | break; |
| 714 | } |
| 715 | } |
| 716 | if (incall) return False; |
| 717 | if (callm != callm_s || callm != callm_e) return False; |
| 718 | |
| 719 | /* Check the sections between CALLM_S and CALLM's. Ensure that no |
| 720 | PUSH uinsn pushes any TempReg that any other PUSH in the same |
| 721 | section pushes. Ie, check that the TempReg args to PUSHes in |
| 722 | the section are unique. If not, the instrumenter generates |
| 723 | incorrect code for CALLM insns. */ |
| 724 | |
| 725 | callm_ptr = 0; |
| 726 | |
| 727 | find_next_CALLM: |
| 728 | /* Search for the next interval, making calls_ptr .. callm_ptr |
| 729 | bracket it. */ |
| 730 | while (callm_ptr < cb->used |
| 731 | && cb->instrs[callm_ptr].opcode != CALLM) |
| 732 | callm_ptr++; |
| 733 | if (callm_ptr == cb->used) |
| 734 | return True; |
| 735 | vg_assert(cb->instrs[callm_ptr].opcode == CALLM); |
| 736 | |
| 737 | calls_ptr = callm_ptr - 1; |
| 738 | while (cb->instrs[calls_ptr].opcode != CALLM_S) |
| 739 | calls_ptr--; |
| 740 | vg_assert(cb->instrs[calls_ptr].opcode == CALLM_S); |
| 741 | vg_assert(calls_ptr >= 0); |
| 742 | |
| 743 | /* VG_(printf)("interval from %d to %d\n", calls_ptr, callm_ptr ); */ |
| 744 | |
| 745 | /* For each PUSH insn in the interval ... */ |
| 746 | for (i = calls_ptr + 1; i < callm_ptr; i++) { |
| 747 | if (cb->instrs[i].opcode != PUSH) continue; |
| 748 | t = cb->instrs[i].val1; |
| 749 | /* Ensure no later PUSH insns up to callm_ptr push the same |
| 750 | TempReg. Return False if any such are found. */ |
| 751 | for (j = i+1; j < callm_ptr; j++) { |
| 752 | if (cb->instrs[j].opcode == PUSH && |
| 753 | cb->instrs[j].val1 == t) |
| 754 | return False; |
| 755 | } |
| 756 | } |
| 757 | |
| 758 | /* This interval is clean. Keep going ... */ |
| 759 | callm_ptr++; |
| 760 | goto find_next_CALLM; |
| 761 | } |
| 762 | |
| 763 | |
| 764 | /*------------------------------------------------------------*/ |
| 765 | /*--- Printing uinstrs. ---*/ |
| 766 | /*------------------------------------------------------------*/ |
| 767 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 768 | /* Global that dictates whether to print generated code at all stages */ |
| 769 | Bool VG_(print_codegen); |
| 770 | |
njn | 563f96f | 2003-02-03 11:17:46 +0000 | [diff] [blame] | 771 | Char* VG_(name_UCondcode) ( Condcode cond ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 772 | { |
| 773 | switch (cond) { |
| 774 | case CondO: return "o"; |
| 775 | case CondNO: return "no"; |
| 776 | case CondB: return "b"; |
| 777 | case CondNB: return "nb"; |
| 778 | case CondZ: return "z"; |
| 779 | case CondNZ: return "nz"; |
| 780 | case CondBE: return "be"; |
| 781 | case CondNBE: return "nbe"; |
| 782 | case CondS: return "s"; |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 783 | case CondNS: return "ns"; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 784 | case CondP: return "p"; |
| 785 | case CondNP: return "np"; |
| 786 | case CondL: return "l"; |
| 787 | case CondNL: return "nl"; |
| 788 | case CondLE: return "le"; |
| 789 | case CondNLE: return "nle"; |
| 790 | case CondAlways: return "MP"; /* hack! */ |
njn | 563f96f | 2003-02-03 11:17:46 +0000 | [diff] [blame] | 791 | default: VG_(core_panic)("name_UCondcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 792 | } |
| 793 | } |
| 794 | |
| 795 | |
| 796 | static void vg_ppFlagSet ( Char* prefix, FlagSet set ) |
| 797 | { |
| 798 | VG_(printf)("%s", prefix); |
| 799 | if (set & FlagD) VG_(printf)("D"); |
| 800 | if (set & FlagO) VG_(printf)("O"); |
| 801 | if (set & FlagS) VG_(printf)("S"); |
| 802 | if (set & FlagZ) VG_(printf)("Z"); |
| 803 | if (set & FlagA) VG_(printf)("A"); |
| 804 | if (set & FlagC) VG_(printf)("C"); |
| 805 | if (set & FlagP) VG_(printf)("P"); |
| 806 | } |
| 807 | |
| 808 | |
| 809 | static void ppTempReg ( Int tt ) |
| 810 | { |
| 811 | if ((tt & 1) == 0) |
| 812 | VG_(printf)("t%d", tt); |
| 813 | else |
| 814 | VG_(printf)("q%d", tt-1); |
| 815 | } |
| 816 | |
| 817 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 818 | void VG_(pp_UOperand) ( UInstr* u, Int operandNo, Int sz, Bool parens ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 819 | { |
| 820 | UInt tag, val; |
| 821 | switch (operandNo) { |
| 822 | case 1: tag = u->tag1; val = u->val1; break; |
| 823 | case 2: tag = u->tag2; val = u->val2; break; |
| 824 | case 3: tag = u->tag3; val = u->val3; break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 825 | default: VG_(core_panic)("VG_(pp_UOperand)(1)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 826 | } |
| 827 | if (tag == Literal) val = u->lit32; |
| 828 | |
| 829 | if (parens) VG_(printf)("("); |
| 830 | switch (tag) { |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 831 | case TempReg: ppTempReg(val); break; |
| 832 | case RealReg: VG_(printf)("%s",nameIReg(sz==0 ? 4 : sz,val)); break; |
| 833 | case Literal: VG_(printf)("$0x%x", val); break; |
| 834 | case Lit16: VG_(printf)("$0x%x", val); break; |
| 835 | case NoValue: VG_(printf)("NoValue"); break; |
| 836 | case ArchReg: VG_(printf)("%S",nameIReg(sz,val)); break; |
| 837 | case ArchRegS: VG_(printf)("%S",nameSReg(val)); break; |
| 838 | case SpillNo: VG_(printf)("spill%d", val); break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 839 | default: VG_(core_panic)("VG_(ppUOperand)(2)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 840 | } |
| 841 | if (parens) VG_(printf)(")"); |
| 842 | } |
| 843 | |
| 844 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 845 | Char* VG_(name_UOpcode) ( Bool upper, Opcode opc ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 846 | { |
| 847 | switch (opc) { |
| 848 | case ADD: return (upper ? "ADD" : "add"); |
| 849 | case ADC: return (upper ? "ADC" : "adc"); |
| 850 | case AND: return (upper ? "AND" : "and"); |
| 851 | case OR: return (upper ? "OR" : "or"); |
| 852 | case XOR: return (upper ? "XOR" : "xor"); |
| 853 | case SUB: return (upper ? "SUB" : "sub"); |
| 854 | case SBB: return (upper ? "SBB" : "sbb"); |
| 855 | case SHL: return (upper ? "SHL" : "shl"); |
| 856 | case SHR: return (upper ? "SHR" : "shr"); |
| 857 | case SAR: return (upper ? "SAR" : "sar"); |
| 858 | case ROL: return (upper ? "ROL" : "rol"); |
| 859 | case ROR: return (upper ? "ROR" : "ror"); |
| 860 | case RCL: return (upper ? "RCL" : "rcl"); |
| 861 | case RCR: return (upper ? "RCR" : "rcr"); |
jsgf | 5efa4fd | 2003-10-14 21:49:11 +0000 | [diff] [blame] | 862 | case MUL: return (upper ? "MUL" : "mul"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 863 | case NOT: return (upper ? "NOT" : "not"); |
| 864 | case NEG: return (upper ? "NEG" : "neg"); |
| 865 | case INC: return (upper ? "INC" : "inc"); |
| 866 | case DEC: return (upper ? "DEC" : "dec"); |
| 867 | case BSWAP: return (upper ? "BSWAP" : "bswap"); |
| 868 | default: break; |
| 869 | } |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 870 | if (!upper) VG_(core_panic)("vg_name_UOpcode: invalid !upper"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 871 | switch (opc) { |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 872 | case CALLM_S: return "CALLM_S"; |
| 873 | case CALLM_E: return "CALLM_E"; |
| 874 | case INCEIP: return "INCEIP"; |
| 875 | case LEA1: return "LEA1"; |
| 876 | case LEA2: return "LEA2"; |
| 877 | case NOP: return "NOP"; |
sewardj | 7a5ebcf | 2002-11-13 22:42:13 +0000 | [diff] [blame] | 878 | case LOCK: return "LOCK"; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 879 | case GET: return "GET"; |
| 880 | case PUT: return "PUT"; |
| 881 | case GETF: return "GETF"; |
| 882 | case PUTF: return "PUTF"; |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 883 | case GETSEG: return "GETSEG"; |
| 884 | case PUTSEG: return "PUTSEG"; |
| 885 | case USESEG: return "USESEG"; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 886 | case LOAD: return "LD" ; |
| 887 | case STORE: return "ST" ; |
| 888 | case MOV: return "MOV"; |
| 889 | case CMOV: return "CMOV"; |
| 890 | case WIDEN: return "WIDEN"; |
| 891 | case JMP: return "J" ; |
| 892 | case JIFZ: return "JIFZ" ; |
| 893 | case CALLM: return "CALLM"; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 894 | case CCALL: return "CCALL"; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 895 | case PUSH: return "PUSH" ; |
| 896 | case POP: return "POP" ; |
| 897 | case CLEAR: return "CLEAR"; |
| 898 | case CC2VAL: return "CC2VAL"; |
| 899 | case FPU_R: return "FPU_R"; |
| 900 | case FPU_W: return "FPU_W"; |
| 901 | case FPU: return "FPU" ; |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 902 | case MMX1: return "MMX1" ; |
| 903 | case MMX2: return "MMX2" ; |
sewardj | ca86001 | 2003-03-27 23:52:58 +0000 | [diff] [blame] | 904 | case MMX3: return "MMX3" ; |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 905 | case MMX2_MemRd: return "MMX2_MRd" ; |
| 906 | case MMX2_MemWr: return "MMX2_MWr" ; |
thughes | 96b466a | 2004-03-15 16:43:58 +0000 | [diff] [blame] | 907 | case MMX2a1_MemRd: return "MMX2a1_MRd" ; |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 908 | case MMX2_ERegRd: return "MMX2_eRRd" ; |
| 909 | case MMX2_ERegWr: return "MMX2_eRWr" ; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 910 | case SSE2a_MemWr: return "SSE2a_MWr"; |
| 911 | case SSE2a_MemRd: return "SSE2a_MRd"; |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 912 | case SSE2g_RegWr: return "SSE2g_RWr"; |
sewardj | 9dd209f | 2003-06-18 23:30:52 +0000 | [diff] [blame] | 913 | case SSE2a1_MemRd: return "SSE2a1_MRd"; |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 914 | case SSE2g1_RegWr: return "SSE2g1_RWr"; |
| 915 | case SSE2e1_RegRd: return "SSE2e1_RRd"; |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 916 | case SSE3e_RegRd: return "SSE3e_RRd"; |
sewardj | abf8bf8 | 2003-06-15 22:28:05 +0000 | [diff] [blame] | 917 | case SSE3e_RegWr: return "SSE3e_RWr"; |
sewardj | 02af6bc | 2003-06-12 00:56:06 +0000 | [diff] [blame] | 918 | case SSE3g_RegWr: return "SSE3g_RWr"; |
sewardj | 77d30a2 | 2003-10-19 08:18:52 +0000 | [diff] [blame] | 919 | case SSE3a1_MemRd: return "SSE3a1_MRd"; |
sewardj | b31b06d | 2003-06-13 00:26:02 +0000 | [diff] [blame] | 920 | case SSE3g1_RegWr: return "SSE3g1_RWr"; |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 921 | case SSE3e1_RegRd: return "SSE3e1_RRd"; |
sewardj | a60be0e | 2003-05-26 08:47:27 +0000 | [diff] [blame] | 922 | case SSE3: return "SSE3"; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 923 | case SSE4: return "SSE4"; |
sewardj | a453fb0 | 2003-06-14 13:22:36 +0000 | [diff] [blame] | 924 | case SSE5: return "SSE5"; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 925 | case SSE3a_MemWr: return "SSE3a_MWr"; |
| 926 | case SSE3a_MemRd: return "SSE3a_MRd"; |
sewardj | e3891fa | 2003-06-15 03:13:48 +0000 | [diff] [blame] | 927 | case SSE3ag_MemRd_RegWr: return "SSE3ag_MemRd_RegWr"; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 928 | default: |
| 929 | if (VG_(needs).extended_UCode) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 930 | return SK_(name_XUOpcode)(opc); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 931 | else { |
| 932 | VG_(printf)("unhandled opcode: %u. Perhaps " |
| 933 | "VG_(needs).extended_UCode should be set?", |
| 934 | opc); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 935 | VG_(core_panic)("name_UOpcode: unhandled opcode"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 936 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 937 | } |
| 938 | } |
| 939 | |
sewardj | a38e092 | 2002-10-01 00:50:47 +0000 | [diff] [blame] | 940 | static |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 941 | void pp_realregs_liveness ( UInstr* u ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 942 | { |
| 943 | # define PRINT_RREG_LIVENESS(realReg,s) \ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 944 | VG_(printf)( IS_RREG_LIVE(VG_(realreg_to_rank)(realReg), \ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 945 | u->regs_live_after) \ |
| 946 | ? s : "-"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 947 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 948 | VG_(printf)("["); |
| 949 | PRINT_RREG_LIVENESS(R_EAX, "a"); |
| 950 | PRINT_RREG_LIVENESS(R_EBX, "b"); |
| 951 | PRINT_RREG_LIVENESS(R_ECX, "c"); |
| 952 | PRINT_RREG_LIVENESS(R_EDX, "d"); |
| 953 | PRINT_RREG_LIVENESS(R_ESI, "S"); |
| 954 | PRINT_RREG_LIVENESS(R_EDI, "D"); |
| 955 | VG_(printf)("]"); |
| 956 | |
| 957 | # undef PRINT_RREG_LIVENESS |
| 958 | } |
| 959 | |
| 960 | /* Ugly-print UInstr :) */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 961 | void VG_(up_UInstr) ( Int i, UInstr* u ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 962 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 963 | VG_(pp_UInstr_regs)(i, u); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 964 | |
| 965 | VG_(printf)("opcode: %d\n", u->opcode); |
sewardj | c1b8688 | 2002-10-06 21:43:50 +0000 | [diff] [blame] | 966 | VG_(printf)("lit32: 0x%x\n", u->lit32); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 967 | VG_(printf)("size: %d\n", u->size); |
| 968 | VG_(printf)("val1,val2,val3: %d, %d, %d\n", u->val1, u->val2, u->val3); |
| 969 | VG_(printf)("tag1,tag2,tag3: %d, %d, %d\n", u->tag1, u->tag2, u->tag3); |
sewardj | c1b8688 | 2002-10-06 21:43:50 +0000 | [diff] [blame] | 970 | VG_(printf)("flags_r: 0x%x\n", u->flags_r); |
| 971 | VG_(printf)("flags_w: 0x%x\n", u->flags_w); |
| 972 | VG_(printf)("extra4b: 0x%x\n", u->extra4b); |
| 973 | VG_(printf)("cond: 0x%x\n", u->cond); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 974 | VG_(printf)("signed_widen: %d\n", u->signed_widen); |
| 975 | VG_(printf)("jmpkind: %d\n", u->jmpkind); |
| 976 | VG_(printf)("argc,regparms_n: %d, %d\n", u->argc, u->regparms_n); |
| 977 | VG_(printf)("has_ret_val: %d\n", u->has_ret_val); |
| 978 | VG_(printf)("regs_live_after: "); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 979 | pp_realregs_liveness(u); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 980 | VG_(printf)("\n"); |
| 981 | } |
| 982 | |
sewardj | a38e092 | 2002-10-01 00:50:47 +0000 | [diff] [blame] | 983 | static |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 984 | void pp_UInstrWorker ( Int instrNo, UInstr* u, Bool ppRegsLiveness ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 985 | { |
| 986 | VG_(printf)("\t%4d: %s", instrNo, |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 987 | VG_(name_UOpcode)(True, u->opcode)); |
nethercote | e00f1ff | 2004-04-16 11:33:53 +0000 | [diff] [blame] | 988 | // For JMP, the condition goes before the size |
| 989 | if (u->opcode == JMP) |
njn | 563f96f | 2003-02-03 11:17:46 +0000 | [diff] [blame] | 990 | VG_(printf)("%s", VG_(name_UCondcode)(u->cond)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 991 | |
| 992 | switch (u->size) { |
| 993 | case 0: VG_(printf)("o"); break; |
| 994 | case 1: VG_(printf)("B"); break; |
| 995 | case 2: VG_(printf)("W"); break; |
| 996 | case 4: VG_(printf)("L"); break; |
| 997 | case 8: VG_(printf)("Q"); break; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 998 | case 16: VG_(printf)("QQ"); break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 999 | default: VG_(printf)("%d", (Int)u->size); break; |
| 1000 | } |
| 1001 | |
nethercote | e00f1ff | 2004-04-16 11:33:53 +0000 | [diff] [blame] | 1002 | // For CC2VAL and CMOV, the condition goes after the size |
| 1003 | if (u->opcode == CC2VAL || u->opcode == CMOV) |
| 1004 | VG_(printf)("%s", VG_(name_UCondcode)(u->cond)); |
| 1005 | |
nethercote | bbcfb58 | 2004-04-16 15:39:22 +0000 | [diff] [blame] | 1006 | // Append extra bits |
| 1007 | switch (u->opcode) { |
| 1008 | case JMP: |
nethercote | e00f1ff | 2004-04-16 11:33:53 +0000 | [diff] [blame] | 1009 | switch (u->jmpkind) { |
| 1010 | case JmpCall: VG_(printf)("-c"); break; |
| 1011 | case JmpRet: VG_(printf)("-r"); break; |
| 1012 | case JmpSyscall: VG_(printf)("-sys"); break; |
| 1013 | case JmpClientReq: VG_(printf)("-cli"); break; |
| 1014 | case JmpYield: VG_(printf)("-yld"); break; |
| 1015 | default: break; |
| 1016 | } |
nethercote | bbcfb58 | 2004-04-16 15:39:22 +0000 | [diff] [blame] | 1017 | break; |
| 1018 | |
| 1019 | case WIDEN: |
| 1020 | VG_(printf)("_%c%c", VG_(toupper)(nameISize(u->extra4b)), |
| 1021 | u->signed_widen?'s':'z'); |
| 1022 | } |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1023 | VG_(printf)(" \t"); |
| 1024 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1025 | switch (u->opcode) { |
| 1026 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1027 | case CALLM_S: case CALLM_E: |
| 1028 | break; |
| 1029 | |
| 1030 | case INCEIP: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1031 | VG_(printf)("$%d", u->val1); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1032 | break; |
| 1033 | |
| 1034 | case LEA2: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1035 | VG_(printf)("%d(" , u->lit32); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1036 | VG_(pp_UOperand)(u, 1, 4, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1037 | VG_(printf)(","); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1038 | VG_(pp_UOperand)(u, 2, 4, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1039 | VG_(printf)(",%d), ", (Int)u->extra4b); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1040 | VG_(pp_UOperand)(u, 3, 4, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1041 | break; |
| 1042 | |
| 1043 | case LEA1: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1044 | VG_(printf)("%d" , u->lit32); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1045 | VG_(pp_UOperand)(u, 1, 4, True); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1046 | VG_(printf)(", "); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1047 | VG_(pp_UOperand)(u, 2, 4, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1048 | break; |
| 1049 | |
sewardj | 7a5ebcf | 2002-11-13 22:42:13 +0000 | [diff] [blame] | 1050 | case NOP: case LOCK: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1051 | break; |
| 1052 | |
| 1053 | case FPU_W: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1054 | VG_(printf)("0x%x:0x%x, ", |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1055 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF ); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1056 | VG_(pp_UOperand)(u, 2, 4, True); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1057 | break; |
| 1058 | |
| 1059 | case FPU_R: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1060 | VG_(printf)(""); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1061 | VG_(pp_UOperand)(u, 2, 4, True); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1062 | VG_(printf)(", 0x%x:0x%x", |
| 1063 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF ); |
| 1064 | break; |
| 1065 | |
| 1066 | case FPU: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1067 | VG_(printf)("0x%x:0x%x", |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1068 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF ); |
| 1069 | break; |
| 1070 | |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 1071 | case MMX1: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1072 | VG_(printf)("0x%x", |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 1073 | u->val1 & 0xFF ); |
| 1074 | break; |
| 1075 | |
| 1076 | case MMX2: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1077 | VG_(printf)("0x%x:0x%x", |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 1078 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF ); |
| 1079 | break; |
| 1080 | |
sewardj | ca86001 | 2003-03-27 23:52:58 +0000 | [diff] [blame] | 1081 | case MMX3: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1082 | VG_(printf)("0x%x:0x%x:0x%x", |
sewardj | ca86001 | 2003-03-27 23:52:58 +0000 | [diff] [blame] | 1083 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, u->val2 & 0xFF ); |
| 1084 | break; |
| 1085 | |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1086 | case MMX2_ERegWr: |
| 1087 | case MMX2_ERegRd: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1088 | VG_(printf)("0x%x:0x%x, ", |
sewardj | ca86001 | 2003-03-27 23:52:58 +0000 | [diff] [blame] | 1089 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF ); |
| 1090 | VG_(pp_UOperand)(u, 2, 4, False); |
| 1091 | break; |
| 1092 | |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 1093 | case MMX2_MemWr: |
| 1094 | case MMX2_MemRd: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1095 | VG_(printf)("0x%x:0x%x", |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 1096 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF ); |
| 1097 | VG_(pp_UOperand)(u, 2, 4, True); |
| 1098 | break; |
| 1099 | |
thughes | 96b466a | 2004-03-15 16:43:58 +0000 | [diff] [blame] | 1100 | case MMX2a1_MemRd: |
| 1101 | VG_(printf)("0x%x:0x%x:0x%x", |
| 1102 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, u->val2 & 0xFF ); |
| 1103 | VG_(pp_UOperand)(u, 3, 4, True); |
| 1104 | break; |
| 1105 | |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1106 | case SSE2a_MemWr: |
| 1107 | case SSE2a_MemRd: |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 1108 | case SSE2g_RegWr: |
| 1109 | case SSE2g1_RegWr: |
| 1110 | case SSE2e1_RegRd: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1111 | VG_(printf)("0x%x:0x%x:0x%x", |
| 1112 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, u->val2 & 0xFF ); |
| 1113 | VG_(pp_UOperand)(u, 3, 4, True); |
| 1114 | break; |
| 1115 | |
sewardj | 9dd209f | 2003-06-18 23:30:52 +0000 | [diff] [blame] | 1116 | case SSE2a1_MemRd: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1117 | case SSE3a_MemWr: |
| 1118 | case SSE3a_MemRd: |
| 1119 | VG_(printf)("0x%x:0x%x:0x%x:0x%x", |
| 1120 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, |
sewardj | de8aecf | 2003-05-27 00:46:28 +0000 | [diff] [blame] | 1121 | (u->val2 >> 8) & 0xFF, u->val2 & 0xFF ); |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1122 | VG_(pp_UOperand)(u, 3, 4, True); |
| 1123 | break; |
| 1124 | |
sewardj | abf8bf8 | 2003-06-15 22:28:05 +0000 | [diff] [blame] | 1125 | case SSE3e_RegWr: |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1126 | case SSE3e_RegRd: |
sewardj | 02af6bc | 2003-06-12 00:56:06 +0000 | [diff] [blame] | 1127 | case SSE3g_RegWr: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1128 | VG_(printf)("0x%x:0x%x:0x%x:0x%x", |
| 1129 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, |
| 1130 | (u->val2 >> 8) & 0xFF, u->val2 & 0xFF ); |
| 1131 | VG_(pp_UOperand)(u, 3, 4, True); |
| 1132 | break; |
| 1133 | |
sewardj | b31b06d | 2003-06-13 00:26:02 +0000 | [diff] [blame] | 1134 | case SSE3g1_RegWr: |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1135 | case SSE3e1_RegRd: |
sewardj | 77d30a2 | 2003-10-19 08:18:52 +0000 | [diff] [blame] | 1136 | case SSE3a1_MemRd: |
sewardj | b31b06d | 2003-06-13 00:26:02 +0000 | [diff] [blame] | 1137 | VG_(printf)("0x%x:0x%x:0x%x:0x%x:0x%x", |
| 1138 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, |
| 1139 | (u->val2 >> 8) & 0xFF, u->val2 & 0xFF, |
| 1140 | u->lit32 ); |
| 1141 | VG_(pp_UOperand)(u, 3, 4, True); |
| 1142 | break; |
| 1143 | |
sewardj | a60be0e | 2003-05-26 08:47:27 +0000 | [diff] [blame] | 1144 | case SSE3: |
| 1145 | VG_(printf)("0x%x:0x%x:0x%x", |
| 1146 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, |
| 1147 | u->val2 & 0xFF ); |
| 1148 | break; |
| 1149 | |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1150 | case SSE4: |
| 1151 | VG_(printf)("0x%x:0x%x:0x%x:0x%x", |
| 1152 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, |
| 1153 | (u->val2 >> 8) & 0xFF, u->val2 & 0xFF ); |
| 1154 | break; |
| 1155 | |
sewardj | a453fb0 | 2003-06-14 13:22:36 +0000 | [diff] [blame] | 1156 | case SSE5: |
| 1157 | VG_(printf)("0x%x:0x%x:0x%x:0x%x:0x%x", |
| 1158 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, |
| 1159 | (u->val2 >> 8) & 0xFF, u->val2 & 0xFF, |
| 1160 | u->val3 & 0xFF ); |
| 1161 | break; |
| 1162 | |
sewardj | e3891fa | 2003-06-15 03:13:48 +0000 | [diff] [blame] | 1163 | case SSE3ag_MemRd_RegWr: |
| 1164 | VG_(printf)("0x%x(addr=", u->lit32 ); |
| 1165 | VG_(pp_UOperand)(u, 1, 4, False); |
| 1166 | VG_(printf)(", dst="); |
| 1167 | VG_(pp_UOperand)(u, 2, 4, False); |
| 1168 | VG_(printf)(")"); |
| 1169 | break; |
| 1170 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1171 | case GET: case PUT: case MOV: case LOAD: case STORE: case CMOV: |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 1172 | case GETSEG: case PUTSEG: |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1173 | VG_(pp_UOperand)(u, 1, u->size, u->opcode==LOAD); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1174 | VG_(printf)(", "); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1175 | VG_(pp_UOperand)(u, 2, u->size, u->opcode==STORE); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1176 | break; |
| 1177 | |
| 1178 | case JMP: |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1179 | VG_(pp_UOperand)(u, 1, u->size, False); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1180 | if (CondAlways == u->cond) { |
| 1181 | /* Print x86 instruction size if filled in */ |
| 1182 | if (0 != u->extra4b) |
| 1183 | VG_(printf)(" ($%u)", u->extra4b); |
| 1184 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1185 | break; |
| 1186 | |
| 1187 | case GETF: case PUTF: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1188 | case CC2VAL: case PUSH: case POP: case CLEAR: case CALLM: |
| 1189 | case NOT: case NEG: case INC: case DEC: case BSWAP: |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1190 | VG_(pp_UOperand)(u, 1, u->size, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1191 | break; |
| 1192 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1193 | /* Print a "(s)" after args passed on stack */ |
| 1194 | case CCALL: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1195 | if (u->has_ret_val) { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1196 | VG_(pp_UOperand)(u, 3, 0, False); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1197 | VG_(printf)(" = "); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1198 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1199 | VG_(printf)("%p(", u->lit32); |
| 1200 | if (u->argc > 0) { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1201 | VG_(pp_UOperand)(u, 1, 0, False); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1202 | if (u->regparms_n < 1) |
| 1203 | VG_(printf)("(s)"); |
| 1204 | } |
| 1205 | if (u->argc > 1) { |
| 1206 | VG_(printf)(", "); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1207 | VG_(pp_UOperand)(u, 2, 0, False); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1208 | if (u->regparms_n < 2) |
| 1209 | VG_(printf)("(s)"); |
| 1210 | } |
| 1211 | if (u->argc > 2) { |
| 1212 | VG_(printf)(", "); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1213 | VG_(pp_UOperand)(u, 3, 0, False); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1214 | if (u->regparms_n < 3) |
| 1215 | VG_(printf)("(s)"); |
| 1216 | } |
| 1217 | VG_(printf)(") "); |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1218 | break; |
| 1219 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 1220 | case USESEG: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1221 | case JIFZ: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1222 | case ADD: case ADC: case AND: case OR: |
| 1223 | case XOR: case SUB: case SBB: |
| 1224 | case SHL: case SHR: case SAR: |
jsgf | 5efa4fd | 2003-10-14 21:49:11 +0000 | [diff] [blame] | 1225 | case ROL: case ROR: case RCL: case RCR: |
| 1226 | case MUL: |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1227 | VG_(pp_UOperand)(u, 1, u->size, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1228 | VG_(printf)(", "); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1229 | VG_(pp_UOperand)(u, 2, u->size, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1230 | break; |
| 1231 | |
| 1232 | case WIDEN: |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1233 | VG_(pp_UOperand)(u, 1, u->size, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1234 | break; |
| 1235 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1236 | default: |
| 1237 | if (VG_(needs).extended_UCode) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1238 | SK_(pp_XUInstr)(u); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1239 | else { |
| 1240 | VG_(printf)("unhandled opcode: %u. Perhaps " |
| 1241 | "VG_(needs).extended_UCode should be set?", |
| 1242 | u->opcode); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1243 | VG_(core_panic)("pp_UInstr: unhandled opcode"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1244 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1245 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1246 | if (u->flags_r != FlagsEmpty || u->flags_w != FlagsEmpty) { |
| 1247 | VG_(printf)(" ("); |
| 1248 | if (u->flags_r != FlagsEmpty) |
| 1249 | vg_ppFlagSet("-r", u->flags_r); |
| 1250 | if (u->flags_w != FlagsEmpty) |
| 1251 | vg_ppFlagSet("-w", u->flags_w); |
| 1252 | VG_(printf)(")"); |
| 1253 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1254 | |
| 1255 | if (ppRegsLiveness) { |
| 1256 | VG_(printf)("\t\t"); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1257 | pp_realregs_liveness ( u ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1258 | } |
| 1259 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1260 | VG_(printf)("\n"); |
| 1261 | } |
| 1262 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1263 | void VG_(pp_UInstr) ( Int instrNo, UInstr* u ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1264 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1265 | pp_UInstrWorker ( instrNo, u, /*ppRegsLiveness*/False ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1266 | } |
| 1267 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1268 | void VG_(pp_UInstr_regs) ( Int instrNo, UInstr* u ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1269 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1270 | pp_UInstrWorker ( instrNo, u, /*ppRegsLiveness*/True ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1271 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1272 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1273 | void VG_(pp_UCodeBlock) ( UCodeBlock* cb, Char* title ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1274 | { |
| 1275 | Int i; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1276 | VG_(printf)("%s\n", title); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1277 | for (i = 0; i < cb->used; i++) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1278 | if (cb->instrs[i].opcode != NOP) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1279 | VG_(pp_UInstr) ( i, &cb->instrs[i] ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1280 | VG_(printf)("\n"); |
| 1281 | } |
| 1282 | |
| 1283 | |
| 1284 | /*------------------------------------------------------------*/ |
| 1285 | /*--- uinstr helpers for register allocation ---*/ |
| 1286 | /*--- and code improvement. ---*/ |
| 1287 | /*------------------------------------------------------------*/ |
| 1288 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1289 | /* Get the temp/reg use of a uinstr, parking them in an array supplied by |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1290 | the caller (regs), which is assumed to be big enough. Return the number |
| 1291 | of entries. Written regs are indicated in parallel array isWrites. |
| 1292 | Insns which read _and_ write a register wind up mentioning it twice. |
| 1293 | Entries are placed in the array in program order, so that if a reg is |
| 1294 | read-modified-written, it appears first as a read and then as a write. |
| 1295 | 'tag' indicates whether we are looking at TempRegs or RealRegs. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1296 | */ |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1297 | Int VG_(get_reg_usage) ( UInstr* u, Tag tag, Int* regs, Bool* isWrites ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1298 | { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1299 | # define RD(ono) VG_UINSTR_READS_REG(ono, regs, isWrites) |
| 1300 | # define WR(ono) VG_UINSTR_WRITES_REG(ono, regs, isWrites) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1301 | |
| 1302 | Int n = 0; |
| 1303 | switch (u->opcode) { |
| 1304 | case LEA1: RD(1); WR(2); break; |
| 1305 | case LEA2: RD(1); RD(2); WR(3); break; |
| 1306 | |
sewardj | 77d30a2 | 2003-10-19 08:18:52 +0000 | [diff] [blame] | 1307 | case SSE3a1_MemRd: |
sewardj | 9dd209f | 2003-06-18 23:30:52 +0000 | [diff] [blame] | 1308 | case SSE2a1_MemRd: |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 1309 | case SSE2e1_RegRd: |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1310 | case SSE3e_RegRd: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1311 | case SSE3a_MemWr: |
| 1312 | case SSE3a_MemRd: |
| 1313 | case SSE2a_MemWr: |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1314 | case SSE3e1_RegRd: |
sewardj | 02af6bc | 2003-06-12 00:56:06 +0000 | [diff] [blame] | 1315 | case SSE2a_MemRd: RD(3); break; |
| 1316 | |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 1317 | case SSE2g_RegWr: |
| 1318 | case SSE2g1_RegWr: |
sewardj | abf8bf8 | 2003-06-15 22:28:05 +0000 | [diff] [blame] | 1319 | case SSE3e_RegWr: |
sewardj | b31b06d | 2003-06-13 00:26:02 +0000 | [diff] [blame] | 1320 | case SSE3g1_RegWr: |
sewardj | 02af6bc | 2003-06-12 00:56:06 +0000 | [diff] [blame] | 1321 | case SSE3g_RegWr: WR(3); break; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1322 | |
sewardj | e3891fa | 2003-06-15 03:13:48 +0000 | [diff] [blame] | 1323 | case SSE3ag_MemRd_RegWr: RD(1); WR(2); break; |
| 1324 | |
thughes | 96b466a | 2004-03-15 16:43:58 +0000 | [diff] [blame] | 1325 | case MMX2a1_MemRd: RD(3); break; |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1326 | case MMX2_ERegRd: RD(2); break; |
| 1327 | case MMX2_ERegWr: WR(2); break; |
sewardj | ca86001 | 2003-03-27 23:52:58 +0000 | [diff] [blame] | 1328 | |
sewardj | a453fb0 | 2003-06-14 13:22:36 +0000 | [diff] [blame] | 1329 | case SSE4: case SSE3: case SSE5: |
sewardj | ca86001 | 2003-03-27 23:52:58 +0000 | [diff] [blame] | 1330 | case MMX1: case MMX2: case MMX3: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1331 | case NOP: case FPU: case INCEIP: case CALLM_S: case CALLM_E: |
sewardj | 7a5ebcf | 2002-11-13 22:42:13 +0000 | [diff] [blame] | 1332 | case CLEAR: case CALLM: case LOCK: break; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1333 | |
| 1334 | case CCALL: |
| 1335 | if (u->argc > 0) RD(1); |
| 1336 | if (u->argc > 1) RD(2); |
| 1337 | if (u->argc > 2) RD(3); |
| 1338 | if (u->has_ret_val) WR(3); |
| 1339 | break; |
| 1340 | |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 1341 | case MMX2_MemRd: case MMX2_MemWr: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1342 | case FPU_R: case FPU_W: RD(2); break; |
| 1343 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 1344 | case GETSEG: WR(2); break; |
| 1345 | case PUTSEG: RD(1); break; |
| 1346 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1347 | case GETF: WR(1); break; |
| 1348 | case PUTF: RD(1); break; |
| 1349 | |
| 1350 | case GET: WR(2); break; |
| 1351 | case PUT: RD(1); break; |
| 1352 | case LOAD: RD(1); WR(2); break; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1353 | case STORE: RD(1); RD(2); break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1354 | case MOV: RD(1); WR(2); break; |
| 1355 | |
| 1356 | case JMP: RD(1); break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1357 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1358 | case PUSH: RD(1); break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1359 | case POP: WR(1); break; |
| 1360 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 1361 | case USESEG: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1362 | case CMOV: |
| 1363 | case ADD: case ADC: case AND: case OR: |
| 1364 | case XOR: case SUB: case SBB: |
jsgf | 5efa4fd | 2003-10-14 21:49:11 +0000 | [diff] [blame] | 1365 | case MUL: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1366 | RD(1); RD(2); WR(2); break; |
| 1367 | |
| 1368 | case SHL: case SHR: case SAR: |
| 1369 | case ROL: case ROR: case RCL: case RCR: |
| 1370 | RD(1); RD(2); WR(2); break; |
| 1371 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1372 | case NOT: case NEG: case INC: case DEC: case BSWAP: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1373 | RD(1); WR(1); break; |
| 1374 | |
| 1375 | case WIDEN: RD(1); WR(1); break; |
| 1376 | |
| 1377 | case CC2VAL: WR(1); break; |
| 1378 | case JIFZ: RD(1); break; |
| 1379 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1380 | default: |
| 1381 | if (VG_(needs).extended_UCode) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1382 | return SK_(get_Xreg_usage)(u, tag, regs, isWrites); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1383 | else { |
| 1384 | VG_(printf)("unhandled opcode: %u. Perhaps " |
| 1385 | "VG_(needs).extended_UCode should be set?", |
| 1386 | u->opcode); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1387 | VG_(core_panic)("VG_(get_reg_usage): unhandled opcode"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1388 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1389 | } |
| 1390 | return n; |
| 1391 | |
| 1392 | # undef RD |
| 1393 | # undef WR |
| 1394 | } |
| 1395 | |
| 1396 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1397 | /* Change temp regs in u into real regs, as directed by the |
| 1398 | * temps[i]-->reals[i] mapping. */ |
sewardj | 5686735 | 2003-10-12 10:27:06 +0000 | [diff] [blame] | 1399 | static |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1400 | void patchUInstr ( UInstr* u, Int temps[], UInt reals[], Int n_tmap ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1401 | { |
| 1402 | Int i; |
| 1403 | if (u->tag1 == TempReg) { |
| 1404 | for (i = 0; i < n_tmap; i++) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1405 | if (temps[i] == u->val1) break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1406 | if (i == n_tmap) VG_(core_panic)("patchUInstr(1)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1407 | u->tag1 = RealReg; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1408 | u->val1 = reals[i]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1409 | } |
| 1410 | if (u->tag2 == TempReg) { |
| 1411 | for (i = 0; i < n_tmap; i++) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1412 | if (temps[i] == u->val2) break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1413 | if (i == n_tmap) VG_(core_panic)("patchUInstr(2)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1414 | u->tag2 = RealReg; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1415 | u->val2 = reals[i]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1416 | } |
| 1417 | if (u->tag3 == TempReg) { |
| 1418 | for (i = 0; i < n_tmap; i++) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1419 | if (temps[i] == u->val3) break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1420 | if (i == n_tmap) VG_(core_panic)("patchUInstr(3)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1421 | u->tag3 = RealReg; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1422 | u->val3 = reals[i]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1423 | } |
| 1424 | } |
| 1425 | |
| 1426 | |
| 1427 | /* Tedious x86-specific hack which compensates for the fact that the |
| 1428 | register numbers for %ah .. %dh do not correspond to those for %eax |
| 1429 | .. %edx. It maps a (reg size, reg no) pair to the number of the |
| 1430 | containing 32-bit reg. */ |
| 1431 | static __inline__ |
| 1432 | Int containingArchRegOf ( Int sz, Int aregno ) |
| 1433 | { |
| 1434 | switch (sz) { |
| 1435 | case 4: return aregno; |
| 1436 | case 2: return aregno; |
| 1437 | case 1: return aregno >= 4 ? aregno-4 : aregno; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1438 | default: VG_(core_panic)("containingArchRegOf"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1439 | } |
| 1440 | } |
| 1441 | |
| 1442 | |
| 1443 | /* If u reads an ArchReg, return the number of the containing arch |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1444 | reg. Otherwise return -1. Used in redundant-PUT elimination. |
| 1445 | Note that this is not required for skins extending UCode because |
| 1446 | this happens before instrumentation. */ |
sewardj | 5686735 | 2003-10-12 10:27:06 +0000 | [diff] [blame] | 1447 | static |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1448 | Int maybe_uinstrReadsArchReg ( UInstr* u ) |
| 1449 | { |
| 1450 | switch (u->opcode) { |
| 1451 | case GET: |
| 1452 | case ADD: case ADC: case AND: case OR: |
| 1453 | case XOR: case SUB: case SBB: |
| 1454 | case SHL: case SHR: case SAR: case ROL: |
| 1455 | case ROR: case RCL: case RCR: |
jsgf | 5efa4fd | 2003-10-14 21:49:11 +0000 | [diff] [blame] | 1456 | case MUL: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1457 | if (u->tag1 == ArchReg) |
| 1458 | return containingArchRegOf ( u->size, u->val1 ); |
| 1459 | else |
| 1460 | return -1; |
| 1461 | |
| 1462 | case GETF: case PUTF: |
| 1463 | case CALLM_S: case CALLM_E: |
| 1464 | case INCEIP: |
| 1465 | case LEA1: |
| 1466 | case LEA2: |
| 1467 | case NOP: |
sewardj | 7a5ebcf | 2002-11-13 22:42:13 +0000 | [diff] [blame] | 1468 | case LOCK: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1469 | case PUT: |
| 1470 | case LOAD: |
| 1471 | case STORE: |
| 1472 | case MOV: |
| 1473 | case CMOV: |
| 1474 | case JMP: |
| 1475 | case CALLM: case CLEAR: case PUSH: case POP: |
| 1476 | case NOT: case NEG: case INC: case DEC: case BSWAP: |
| 1477 | case CC2VAL: |
| 1478 | case JIFZ: |
| 1479 | case FPU: case FPU_R: case FPU_W: |
sewardj | ca86001 | 2003-03-27 23:52:58 +0000 | [diff] [blame] | 1480 | case MMX1: case MMX2: case MMX3: |
thughes | 96b466a | 2004-03-15 16:43:58 +0000 | [diff] [blame] | 1481 | case MMX2_MemRd: case MMX2_MemWr: case MMX2a1_MemRd: |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1482 | case MMX2_ERegRd: case MMX2_ERegWr: |
sewardj | 9dd209f | 2003-06-18 23:30:52 +0000 | [diff] [blame] | 1483 | case SSE2a_MemWr: case SSE2a_MemRd: case SSE2a1_MemRd: |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 1484 | case SSE2g_RegWr: case SSE2g1_RegWr: case SSE2e1_RegRd: |
sewardj | 77d30a2 | 2003-10-19 08:18:52 +0000 | [diff] [blame] | 1485 | case SSE3a_MemWr: case SSE3a_MemRd: case SSE3a1_MemRd: |
sewardj | abf8bf8 | 2003-06-15 22:28:05 +0000 | [diff] [blame] | 1486 | case SSE3e_RegRd: case SSE3g_RegWr: case SSE3e_RegWr: |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1487 | case SSE3g1_RegWr: case SSE3e1_RegRd: |
sewardj | e3891fa | 2003-06-15 03:13:48 +0000 | [diff] [blame] | 1488 | case SSE4: case SSE3: case SSE5: case SSE3ag_MemRd_RegWr: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1489 | case WIDEN: |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 1490 | /* GETSEG and USESEG are to do with ArchRegS, not ArchReg */ |
| 1491 | case GETSEG: case PUTSEG: |
| 1492 | case USESEG: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1493 | return -1; |
| 1494 | |
| 1495 | default: |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1496 | VG_(pp_UInstr)(0,u); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1497 | VG_(core_panic)("maybe_uinstrReadsArchReg: unhandled opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1498 | } |
| 1499 | } |
| 1500 | |
| 1501 | static __inline__ |
| 1502 | Bool uInstrMentionsTempReg ( UInstr* u, Int tempreg ) |
| 1503 | { |
| 1504 | Int i, k; |
njn | f4ce3d3 | 2003-02-10 10:17:26 +0000 | [diff] [blame] | 1505 | Int tempUse[VG_MAX_REGS_USED]; |
| 1506 | Bool notUsed[VG_MAX_REGS_USED]; |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1507 | |
| 1508 | k = VG_(get_reg_usage) ( u, TempReg, &tempUse[0], ¬Used[0] ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1509 | for (i = 0; i < k; i++) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1510 | if (tempUse[i] == tempreg) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1511 | return True; |
| 1512 | return False; |
| 1513 | } |
| 1514 | |
| 1515 | |
| 1516 | /*------------------------------------------------------------*/ |
| 1517 | /*--- ucode improvement. ---*/ |
| 1518 | /*------------------------------------------------------------*/ |
| 1519 | |
| 1520 | /* Improve the code in cb by doing |
| 1521 | -- Redundant ArchReg-fetch elimination |
| 1522 | -- Redundant PUT elimination |
| 1523 | -- Redundant cond-code restore/save elimination |
| 1524 | The overall effect of these is to allow target registers to be |
| 1525 | cached in host registers over multiple target insns. |
| 1526 | */ |
| 1527 | static void vg_improve ( UCodeBlock* cb ) |
| 1528 | { |
| 1529 | Int i, j, k, m, n, ar, tr, told, actual_areg; |
| 1530 | Int areg_map[8]; |
| 1531 | Bool annul_put[8]; |
njn | f4ce3d3 | 2003-02-10 10:17:26 +0000 | [diff] [blame] | 1532 | Int tempUse[VG_MAX_REGS_USED]; |
| 1533 | Bool isWrites[VG_MAX_REGS_USED]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1534 | UInstr* u; |
| 1535 | Bool wr; |
| 1536 | Int* last_live_before; |
| 1537 | FlagSet future_dead_flags; |
| 1538 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1539 | if (dis) |
| 1540 | VG_(printf) ("Improvements:\n"); |
| 1541 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1542 | if (cb->nextTemp > 0) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1543 | last_live_before = VG_(arena_malloc) ( VG_AR_JITTER, |
| 1544 | cb->nextTemp * sizeof(Int) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1545 | else |
| 1546 | last_live_before = NULL; |
| 1547 | |
| 1548 | |
| 1549 | /* PASS 1: redundant GET elimination. (Actually, more general than |
| 1550 | that -- eliminates redundant fetches of ArchRegs). */ |
| 1551 | |
| 1552 | /* Find the live-range-ends for all temporaries. Duplicates code |
| 1553 | in the register allocator :-( */ |
| 1554 | |
| 1555 | for (i = 0; i < cb->nextTemp; i++) last_live_before[i] = -1; |
| 1556 | |
| 1557 | for (i = cb->used-1; i >= 0; i--) { |
| 1558 | u = &cb->instrs[i]; |
| 1559 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1560 | k = VG_(get_reg_usage)(u, TempReg, &tempUse[0], &isWrites[0]); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1561 | |
| 1562 | /* For each temp usage ... bwds in program order. */ |
| 1563 | for (j = k-1; j >= 0; j--) { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1564 | tr = tempUse[j]; |
| 1565 | wr = isWrites[j]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1566 | if (last_live_before[tr] == -1) { |
| 1567 | vg_assert(tr >= 0 && tr < cb->nextTemp); |
| 1568 | last_live_before[tr] = wr ? (i+1) : i; |
| 1569 | } |
| 1570 | } |
| 1571 | |
| 1572 | } |
| 1573 | |
| 1574 | # define BIND_ARCH_TO_TEMP(archreg,tempreg)\ |
| 1575 | { Int q; \ |
| 1576 | /* Invalidate any old binding(s) to tempreg. */ \ |
| 1577 | for (q = 0; q < 8; q++) \ |
| 1578 | if (areg_map[q] == tempreg) areg_map[q] = -1; \ |
| 1579 | /* Add the new binding. */ \ |
| 1580 | areg_map[archreg] = (tempreg); \ |
| 1581 | } |
| 1582 | |
| 1583 | /* Set up the A-reg map. */ |
| 1584 | for (i = 0; i < 8; i++) areg_map[i] = -1; |
| 1585 | |
| 1586 | /* Scan insns. */ |
| 1587 | for (i = 0; i < cb->used; i++) { |
| 1588 | u = &cb->instrs[i]; |
| 1589 | if (u->opcode == GET && u->size == 4) { |
| 1590 | /* GET; see if it can be annulled. */ |
| 1591 | vg_assert(u->tag1 == ArchReg); |
| 1592 | vg_assert(u->tag2 == TempReg); |
| 1593 | ar = u->val1; |
| 1594 | tr = u->val2; |
| 1595 | told = areg_map[ar]; |
| 1596 | if (told != -1 && last_live_before[told] <= i) { |
| 1597 | /* ar already has an old mapping to told, but that runs |
| 1598 | out here. Annul this GET, rename tr to told for the |
| 1599 | rest of the block, and extend told's live range to that |
| 1600 | of tr. */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1601 | VG_(new_NOP)(u); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1602 | n = last_live_before[tr] + 1; |
| 1603 | if (n > cb->used) n = cb->used; |
| 1604 | last_live_before[told] = last_live_before[tr]; |
| 1605 | last_live_before[tr] = i-1; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1606 | if (dis) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1607 | VG_(printf)( |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1608 | " at %2d: delete GET, rename t%d to t%d in (%d .. %d)\n", |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1609 | i, tr, told,i+1, n-1); |
| 1610 | for (m = i+1; m < n; m++) { |
| 1611 | if (cb->instrs[m].tag1 == TempReg |
| 1612 | && cb->instrs[m].val1 == tr) |
| 1613 | cb->instrs[m].val1 = told; |
| 1614 | if (cb->instrs[m].tag2 == TempReg |
| 1615 | && cb->instrs[m].val2 == tr) |
| 1616 | cb->instrs[m].val2 = told; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1617 | if (cb->instrs[m].tag3 == TempReg |
| 1618 | && cb->instrs[m].val3 == tr) |
| 1619 | cb->instrs[m].val3 = told; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1620 | } |
| 1621 | BIND_ARCH_TO_TEMP(ar,told); |
| 1622 | } |
| 1623 | else |
| 1624 | BIND_ARCH_TO_TEMP(ar,tr); |
| 1625 | } |
| 1626 | else if (u->opcode == GET && u->size != 4) { |
| 1627 | /* Invalidate any mapping for this archreg. */ |
| 1628 | actual_areg = containingArchRegOf ( u->size, u->val1 ); |
| 1629 | areg_map[actual_areg] = -1; |
| 1630 | } |
| 1631 | else if (u->opcode == PUT && u->size == 4) { |
| 1632 | /* PUT; re-establish t -> a binding */ |
| 1633 | vg_assert(u->tag1 == TempReg); |
| 1634 | vg_assert(u->tag2 == ArchReg); |
| 1635 | BIND_ARCH_TO_TEMP(u->val2, u->val1); |
| 1636 | } |
| 1637 | else if (u->opcode == PUT && u->size != 4) { |
| 1638 | /* Invalidate any mapping for this archreg. */ |
| 1639 | actual_areg = containingArchRegOf ( u->size, u->val2 ); |
| 1640 | areg_map[actual_areg] = -1; |
| 1641 | } else { |
| 1642 | |
| 1643 | /* see if insn has an archreg as a read operand; if so try to |
| 1644 | map it. */ |
| 1645 | if (u->tag1 == ArchReg && u->size == 4 |
| 1646 | && areg_map[u->val1] != -1) { |
| 1647 | switch (u->opcode) { |
| 1648 | case ADD: case SUB: case AND: case OR: case XOR: |
| 1649 | case ADC: case SBB: |
| 1650 | case SHL: case SHR: case SAR: case ROL: case ROR: |
| 1651 | case RCL: case RCR: |
jsgf | 5efa4fd | 2003-10-14 21:49:11 +0000 | [diff] [blame] | 1652 | case MUL: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1653 | if (dis) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1654 | VG_(printf)( |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1655 | " at %2d: change ArchReg %S to TempReg t%d\n", |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1656 | i, nameIReg(4,u->val1), areg_map[u->val1]); |
| 1657 | u->tag1 = TempReg; |
| 1658 | u->val1 = areg_map[u->val1]; |
| 1659 | /* Remember to extend the live range of the TempReg, |
| 1660 | if necessary. */ |
| 1661 | if (last_live_before[u->val1] < i) |
| 1662 | last_live_before[u->val1] = i; |
| 1663 | break; |
| 1664 | default: |
| 1665 | break; |
| 1666 | } |
| 1667 | } |
| 1668 | |
| 1669 | /* boring insn; invalidate any mappings to temps it writes */ |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1670 | k = VG_(get_reg_usage)(u, TempReg, &tempUse[0], &isWrites[0]); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1671 | |
| 1672 | for (j = 0; j < k; j++) { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1673 | wr = isWrites[j]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1674 | if (!wr) continue; |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1675 | tr = tempUse[j]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1676 | for (m = 0; m < 8; m++) |
| 1677 | if (areg_map[m] == tr) areg_map[m] = -1; |
| 1678 | } |
| 1679 | } |
| 1680 | |
| 1681 | } |
| 1682 | |
| 1683 | # undef BIND_ARCH_TO_TEMP |
| 1684 | |
sewardj | 05f1aa1 | 2002-04-30 00:29:36 +0000 | [diff] [blame] | 1685 | /* PASS 2: redundant PUT elimination. Don't annul (delay) puts of |
| 1686 | %ESP, since the memory check machinery always requires the |
| 1687 | in-memory value of %ESP to be up to date. Although this isn't |
| 1688 | actually required by other analyses (cache simulation), it's |
| 1689 | simplest to be consistent for all end-uses. */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1690 | for (j = 0; j < 8; j++) |
| 1691 | annul_put[j] = False; |
| 1692 | |
| 1693 | for (i = cb->used-1; i >= 0; i--) { |
| 1694 | u = &cb->instrs[i]; |
| 1695 | if (u->opcode == NOP) continue; |
| 1696 | |
| 1697 | if (u->opcode == PUT && u->size == 4) { |
| 1698 | vg_assert(u->tag2 == ArchReg); |
| 1699 | actual_areg = containingArchRegOf ( 4, u->val2 ); |
| 1700 | if (annul_put[actual_areg]) { |
sewardj | 05f1aa1 | 2002-04-30 00:29:36 +0000 | [diff] [blame] | 1701 | vg_assert(actual_areg != R_ESP); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1702 | VG_(new_NOP)(u); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1703 | if (dis) |
| 1704 | VG_(printf)(" at %2d: delete PUT\n", i ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1705 | } else { |
sewardj | 05f1aa1 | 2002-04-30 00:29:36 +0000 | [diff] [blame] | 1706 | if (actual_areg != R_ESP) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1707 | annul_put[actual_areg] = True; |
| 1708 | } |
| 1709 | } |
| 1710 | else if (u->opcode == PUT && u->size != 4) { |
| 1711 | actual_areg = containingArchRegOf ( u->size, u->val2 ); |
| 1712 | annul_put[actual_areg] = False; |
| 1713 | } |
| 1714 | else if (u->opcode == JMP || u->opcode == JIFZ |
| 1715 | || u->opcode == CALLM) { |
| 1716 | for (j = 0; j < 8; j++) |
| 1717 | annul_put[j] = False; |
| 1718 | } |
| 1719 | else { |
| 1720 | /* If an instruction reads an ArchReg, the immediately |
| 1721 | preceding PUT cannot be annulled. */ |
| 1722 | actual_areg = maybe_uinstrReadsArchReg ( u ); |
| 1723 | if (actual_areg != -1) |
| 1724 | annul_put[actual_areg] = False; |
| 1725 | } |
| 1726 | } |
| 1727 | |
| 1728 | /* PASS 2a: redundant-move elimination. Given MOV t1, t2 and t1 is |
| 1729 | dead after this point, annul the MOV insn and rename t2 to t1. |
| 1730 | Further modifies the last_live_before map. */ |
| 1731 | |
| 1732 | # if 0 |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1733 | VG_(pp_UCodeBlock)(cb, "Before MOV elimination" ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1734 | for (i = 0; i < cb->nextTemp; i++) |
| 1735 | VG_(printf)("llb[t%d]=%d ", i, last_live_before[i]); |
| 1736 | VG_(printf)("\n"); |
| 1737 | # endif |
| 1738 | |
| 1739 | for (i = 0; i < cb->used-1; i++) { |
| 1740 | u = &cb->instrs[i]; |
| 1741 | if (u->opcode != MOV) continue; |
| 1742 | if (u->tag1 == Literal) continue; |
| 1743 | vg_assert(u->tag1 == TempReg); |
| 1744 | vg_assert(u->tag2 == TempReg); |
| 1745 | if (last_live_before[u->val1] == i) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1746 | if (dis) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1747 | VG_(printf)( |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1748 | " at %2d: delete MOV, rename t%d to t%d in (%d .. %d)\n", |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1749 | i, u->val2, u->val1, i+1, last_live_before[u->val2] ); |
| 1750 | for (j = i+1; j <= last_live_before[u->val2]; j++) { |
| 1751 | if (cb->instrs[j].tag1 == TempReg |
| 1752 | && cb->instrs[j].val1 == u->val2) |
| 1753 | cb->instrs[j].val1 = u->val1; |
| 1754 | if (cb->instrs[j].tag2 == TempReg |
| 1755 | && cb->instrs[j].val2 == u->val2) |
| 1756 | cb->instrs[j].val2 = u->val1; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1757 | if (cb->instrs[j].tag3 == TempReg |
| 1758 | && cb->instrs[j].val3 == u->val2) |
| 1759 | cb->instrs[j].val3 = u->val1; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1760 | } |
| 1761 | last_live_before[u->val1] = last_live_before[u->val2]; |
| 1762 | last_live_before[u->val2] = i-1; |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1763 | VG_(new_NOP)(u); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1764 | } |
| 1765 | } |
| 1766 | |
| 1767 | /* PASS 3: redundant condition-code restore/save elimination. |
| 1768 | Scan backwards from the end. future_dead_flags records the set |
| 1769 | of flags which are dead at this point, that is, will be written |
| 1770 | before they are next read. Earlier uinsns which write flags |
| 1771 | already in future_dead_flags can have their writes annulled. |
| 1772 | */ |
| 1773 | future_dead_flags = FlagsEmpty; |
| 1774 | |
| 1775 | for (i = cb->used-1; i >= 0; i--) { |
| 1776 | u = &cb->instrs[i]; |
| 1777 | |
| 1778 | /* We might never make it to insns beyond this one, so be |
| 1779 | conservative. */ |
| 1780 | if (u->opcode == JIFZ || u->opcode == JMP) { |
| 1781 | future_dead_flags = FlagsEmpty; |
| 1782 | continue; |
| 1783 | } |
| 1784 | |
sewardj | fbb6cda | 2002-07-24 09:33:52 +0000 | [diff] [blame] | 1785 | /* PUTF modifies the %EFLAGS in essentially unpredictable ways. |
| 1786 | For example people try to mess with bit 21 to see if CPUID |
| 1787 | works. The setting may or may not actually take hold. So we |
| 1788 | play safe here. */ |
| 1789 | if (u->opcode == PUTF) { |
| 1790 | future_dead_flags = FlagsEmpty; |
| 1791 | continue; |
| 1792 | } |
| 1793 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1794 | /* We can annul the flags written by this insn if it writes a |
| 1795 | subset (or eq) of the set of flags known to be dead after |
| 1796 | this insn. If not, just record the flags also written by |
| 1797 | this insn.*/ |
| 1798 | if (u->flags_w != FlagsEmpty |
| 1799 | && VG_IS_FLAG_SUBSET(u->flags_w, future_dead_flags)) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1800 | if (dis) { |
| 1801 | VG_(printf)(" at %2d: annul flag write ", i); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1802 | vg_ppFlagSet("", u->flags_w); |
| 1803 | VG_(printf)(" due to later "); |
| 1804 | vg_ppFlagSet("", future_dead_flags); |
| 1805 | VG_(printf)("\n"); |
| 1806 | } |
| 1807 | u->flags_w = FlagsEmpty; |
| 1808 | } else { |
| 1809 | future_dead_flags |
| 1810 | = VG_UNION_FLAG_SETS ( u->flags_w, future_dead_flags ); |
| 1811 | } |
| 1812 | |
| 1813 | /* If this insn also reads flags, empty out future_dead_flags so |
| 1814 | as to force preceding writes not to be annulled. */ |
| 1815 | if (u->flags_r != FlagsEmpty) |
| 1816 | future_dead_flags = FlagsEmpty; |
| 1817 | } |
| 1818 | |
| 1819 | if (last_live_before) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1820 | VG_(arena_free) ( VG_AR_JITTER, last_live_before ); |
| 1821 | |
| 1822 | if (dis) { |
| 1823 | VG_(printf)("\n"); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1824 | VG_(pp_UCodeBlock) ( cb, "Improved UCode:" ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1825 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1826 | } |
| 1827 | |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1828 | /*------------------------------------------------------------*/ |
| 1829 | /*--- %ESP-update pass ---*/ |
| 1830 | /*------------------------------------------------------------*/ |
| 1831 | |
| 1832 | /* For skins that want to know about %ESP changes, this pass adds |
| 1833 | in the appropriate hooks. We have to do it after the skin's |
| 1834 | instrumentation, so the skin doesn't have to worry about the CCALLs |
| 1835 | it adds in, and we must do it before register allocation because |
| 1836 | spilled temps make it much harder to work out the %esp deltas. |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1837 | Thus we have it as an extra phase between the two. |
| 1838 | |
| 1839 | We look for "GETL %ESP, t_ESP", then track ADDs and SUBs of |
| 1840 | literal values to t_ESP, and the total delta of the ADDs/SUBs. Then if |
| 1841 | "PUTL t_ESP, %ESP" happens, we call the helper with the known delta. We |
| 1842 | also cope with "MOVL t_ESP, tX", making tX the new t_ESP. If any other |
| 1843 | instruction clobbers t_ESP, we don't track it anymore, and fall back to |
| 1844 | the delta-is-unknown case. That case is also used when the delta is not |
| 1845 | a nice small amount, or an unknown amount. |
| 1846 | */ |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1847 | static |
| 1848 | UCodeBlock* vg_ESP_update_pass(UCodeBlock* cb_in) |
| 1849 | { |
| 1850 | UCodeBlock* cb; |
| 1851 | UInstr* u; |
| 1852 | Int delta = 0; |
| 1853 | UInt t_ESP = INVALID_TEMPREG; |
sewardj | 05bcdcb | 2003-05-18 10:05:38 +0000 | [diff] [blame] | 1854 | Int i; |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1855 | |
| 1856 | cb = VG_(setup_UCodeBlock)(cb_in); |
| 1857 | |
| 1858 | for (i = 0; i < VG_(get_num_instrs)(cb_in); i++) { |
| 1859 | u = VG_(get_instr)(cb_in, i); |
| 1860 | |
| 1861 | if (GET == u->opcode && R_ESP == u->val1) { |
| 1862 | t_ESP = u->val2; |
| 1863 | delta = 0; |
| 1864 | |
| 1865 | } else if (PUT == u->opcode && R_ESP == u->val2 && 4 == u->size) { |
| 1866 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 1867 | # define DO_GENERIC \ |
| 1868 | if (VG_(defined_new_mem_stack)() || \ |
| 1869 | VG_(defined_die_mem_stack)()) { \ |
| 1870 | uInstr1(cb, CCALL, 0, TempReg, u->val1); \ |
| 1871 | uCCall(cb, (Addr) VG_(unknown_esp_update), \ |
| 1872 | 1, 1, False); \ |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1873 | } |
| 1874 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 1875 | # define DO(kind, size) \ |
| 1876 | if (VG_(defined_##kind##_mem_stack_##size)()) { \ |
| 1877 | uInstr1(cb, CCALL, 0, TempReg, u->val1); \ |
| 1878 | uCCall(cb, (Addr) VG_(tool_interface).track_##kind##_mem_stack_##size, \ |
| 1879 | 1, 1, False); \ |
| 1880 | \ |
| 1881 | } else \ |
| 1882 | DO_GENERIC \ |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1883 | break |
| 1884 | |
| 1885 | if (u->val1 == t_ESP) { |
| 1886 | /* Known delta, common cases handled specially. */ |
| 1887 | switch (delta) { |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1888 | case 0: break; |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1889 | case 4: DO(die, 4); |
| 1890 | case -4: DO(new, 4); |
| 1891 | case 8: DO(die, 8); |
| 1892 | case -8: DO(new, 8); |
| 1893 | case 12: DO(die, 12); |
| 1894 | case -12: DO(new, 12); |
| 1895 | case 16: DO(die, 16); |
| 1896 | case -16: DO(new, 16); |
| 1897 | case 32: DO(die, 32); |
| 1898 | case -32: DO(new, 32); |
| 1899 | default: DO_GENERIC; break; |
| 1900 | } |
| 1901 | } else { |
| 1902 | /* Unknown delta */ |
| 1903 | DO_GENERIC; |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1904 | |
daywalker | 972a759 | 2003-10-01 10:19:08 +0000 | [diff] [blame] | 1905 | /* now we know the temp that points to %ESP */ |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1906 | t_ESP = u->val1; |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1907 | } |
| 1908 | delta = 0; |
| 1909 | |
| 1910 | # undef DO |
| 1911 | # undef DO_GENERIC |
| 1912 | |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1913 | } else if (ADD == u->opcode && Literal == u->tag1 && t_ESP == u->val2) { |
| 1914 | delta += u->lit32; |
| 1915 | |
| 1916 | } else if (SUB == u->opcode && Literal == u->tag1 && t_ESP == u->val2) { |
| 1917 | delta -= u->lit32; |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1918 | |
| 1919 | } else if (MOV == u->opcode && TempReg == u->tag1 && t_ESP == u->val1 && |
| 1920 | TempReg == u->tag2) { |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1921 | // t_ESP is transferred |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1922 | t_ESP = u->val2; |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1923 | |
| 1924 | } else { |
| 1925 | // Stop tracking t_ESP if it's clobbered by this instruction. |
| 1926 | Int tempUse [VG_MAX_REGS_USED]; |
| 1927 | Bool isWrites[VG_MAX_REGS_USED]; |
| 1928 | Int j, n = VG_(get_reg_usage)(u, TempReg, tempUse, isWrites); |
| 1929 | |
| 1930 | for (j = 0; j < n; j++) { |
| 1931 | if (tempUse[j] == t_ESP && isWrites[j]) |
| 1932 | t_ESP = INVALID_TEMPREG; |
| 1933 | } |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1934 | } |
| 1935 | VG_(copy_UInstr) ( cb, u ); |
| 1936 | } |
| 1937 | |
| 1938 | VG_(free_UCodeBlock)(cb_in); |
| 1939 | return cb; |
| 1940 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1941 | |
| 1942 | /*------------------------------------------------------------*/ |
| 1943 | /*--- The new register allocator. ---*/ |
| 1944 | /*------------------------------------------------------------*/ |
| 1945 | |
| 1946 | typedef |
| 1947 | struct { |
| 1948 | /* Becomes live for the first time after this insn ... */ |
| 1949 | Int live_after; |
jseward | fa70a8e | 2004-07-01 11:38:36 +0000 | [diff] [blame] | 1950 | /* Becomes dead for the last time before this insn ... */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1951 | Int dead_before; |
| 1952 | /* The "home" spill slot, if needed. Never changes. */ |
| 1953 | Int spill_no; |
| 1954 | /* Where is it? VG_NOVALUE==in a spill slot; else in reg. */ |
| 1955 | Int real_no; |
| 1956 | } |
| 1957 | TempInfo; |
| 1958 | |
| 1959 | |
| 1960 | /* Take a ucode block and allocate its TempRegs to RealRegs, or put |
| 1961 | them in spill locations, and add spill code, if there are not |
| 1962 | enough real regs. The usual register allocation deal, in short. |
| 1963 | |
| 1964 | Important redundancy of representation: |
| 1965 | |
| 1966 | real_to_temp maps real reg ranks (RRRs) to TempReg nos, or |
| 1967 | to VG_NOVALUE if the real reg has no currently assigned TempReg. |
| 1968 | |
| 1969 | The .real_no field of a TempInfo gives the current RRR for |
| 1970 | this TempReg, or VG_NOVALUE if the TempReg is currently |
| 1971 | in memory, in which case it is in the SpillNo denoted by |
| 1972 | spillno. |
| 1973 | |
| 1974 | These pieces of information (a fwds-bwds mapping, really) must |
| 1975 | be kept consistent! |
| 1976 | |
| 1977 | This allocator uses the so-called Second Chance Bin Packing |
| 1978 | algorithm, as described in "Quality and Speed in Linear-scan |
| 1979 | Register Allocation" (Traub, Holloway and Smith, ACM PLDI98, |
| 1980 | pp142-151). It is simple and fast and remarkably good at |
| 1981 | minimising the amount of spill code introduced. |
| 1982 | */ |
| 1983 | |
| 1984 | static |
| 1985 | UCodeBlock* vg_do_register_allocation ( UCodeBlock* c1 ) |
| 1986 | { |
| 1987 | TempInfo* temp_info; |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1988 | Int real_to_temp [VG_MAX_REALREGS]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1989 | Bool is_spill_cand[VG_MAX_REALREGS]; |
| 1990 | Int ss_busy_until_before[VG_MAX_SPILLSLOTS]; |
| 1991 | Int i, j, k, m, r, tno, max_ss_no; |
| 1992 | Bool wr, defer, isRead, spill_reqd; |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1993 | UInt realUse [VG_MAX_REGS_USED]; |
| 1994 | Int tempUse [VG_MAX_REGS_USED]; |
njn | f4ce3d3 | 2003-02-10 10:17:26 +0000 | [diff] [blame] | 1995 | Bool isWrites[VG_MAX_REGS_USED]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1996 | UCodeBlock* c2; |
| 1997 | |
| 1998 | /* Used to denote ... well, "no value" in this fn. */ |
| 1999 | # define VG_NOTHING (-2) |
| 2000 | |
| 2001 | /* Initialise the TempReg info. */ |
| 2002 | if (c1->nextTemp > 0) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2003 | temp_info = VG_(arena_malloc)(VG_AR_JITTER, |
| 2004 | c1->nextTemp * sizeof(TempInfo) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2005 | else |
| 2006 | temp_info = NULL; |
| 2007 | |
| 2008 | for (i = 0; i < c1->nextTemp; i++) { |
| 2009 | temp_info[i].live_after = VG_NOTHING; |
| 2010 | temp_info[i].dead_before = VG_NOTHING; |
| 2011 | temp_info[i].spill_no = VG_NOTHING; |
| 2012 | /* temp_info[i].real_no is not yet relevant. */ |
| 2013 | } |
| 2014 | |
| 2015 | spill_reqd = False; |
| 2016 | |
| 2017 | /* Scan fwds to establish live ranges. */ |
| 2018 | |
| 2019 | for (i = 0; i < c1->used; i++) { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2020 | k = VG_(get_reg_usage)(&c1->instrs[i], TempReg, &tempUse[0], |
| 2021 | &isWrites[0]); |
njn | f4ce3d3 | 2003-02-10 10:17:26 +0000 | [diff] [blame] | 2022 | vg_assert(k >= 0 && k <= VG_MAX_REGS_USED); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2023 | |
| 2024 | /* For each temp usage ... fwds in program order */ |
| 2025 | for (j = 0; j < k; j++) { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2026 | tno = tempUse[j]; |
| 2027 | wr = isWrites[j]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2028 | if (wr) { |
| 2029 | /* Writes hold a reg live until after this insn. */ |
| 2030 | if (temp_info[tno].live_after == VG_NOTHING) |
| 2031 | temp_info[tno].live_after = i; |
| 2032 | if (temp_info[tno].dead_before < i + 1) |
| 2033 | temp_info[tno].dead_before = i + 1; |
| 2034 | } else { |
| 2035 | /* First use of a tmp should be a write. */ |
njn | fa0ad42 | 2003-02-03 11:07:03 +0000 | [diff] [blame] | 2036 | if (temp_info[tno].live_after == VG_NOTHING) { |
| 2037 | VG_(printf)("At instr %d...\n", i); |
| 2038 | VG_(core_panic)("First use of tmp not a write," |
| 2039 | " probably a skin instrumentation error"); |
| 2040 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2041 | /* Reads only hold it live until before this insn. */ |
| 2042 | if (temp_info[tno].dead_before < i) |
| 2043 | temp_info[tno].dead_before = i; |
| 2044 | } |
| 2045 | } |
| 2046 | } |
| 2047 | |
| 2048 | # if 0 |
| 2049 | /* Sanity check on live ranges. Expensive but correct. */ |
| 2050 | for (i = 0; i < c1->nextTemp; i++) { |
| 2051 | vg_assert( (temp_info[i].live_after == VG_NOTHING |
| 2052 | && temp_info[i].dead_before == VG_NOTHING) |
| 2053 | || (temp_info[i].live_after != VG_NOTHING |
| 2054 | && temp_info[i].dead_before != VG_NOTHING) ); |
| 2055 | } |
| 2056 | # endif |
| 2057 | |
| 2058 | /* Do a rank-based allocation of TempRegs to spill slot numbers. |
| 2059 | We put as few as possible values in spill slots, but |
| 2060 | nevertheless need to have an assignment to them just in case. */ |
| 2061 | |
| 2062 | max_ss_no = -1; |
| 2063 | |
| 2064 | for (i = 0; i < VG_MAX_SPILLSLOTS; i++) |
| 2065 | ss_busy_until_before[i] = 0; |
| 2066 | |
| 2067 | for (i = 0; i < c1->nextTemp; i++) { |
| 2068 | |
| 2069 | /* True iff this temp is unused. */ |
| 2070 | if (temp_info[i].live_after == VG_NOTHING) |
| 2071 | continue; |
| 2072 | |
| 2073 | /* Find the lowest-numbered spill slot which is available at the |
| 2074 | start point of this interval, and assign the interval to |
| 2075 | it. */ |
| 2076 | for (j = 0; j < VG_MAX_SPILLSLOTS; j++) |
| 2077 | if (ss_busy_until_before[j] <= temp_info[i].live_after) |
| 2078 | break; |
| 2079 | if (j == VG_MAX_SPILLSLOTS) { |
| 2080 | VG_(printf)("VG_MAX_SPILLSLOTS is too low; increase and recompile.\n"); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2081 | VG_(core_panic)("register allocation failed -- out of spill slots"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2082 | } |
| 2083 | ss_busy_until_before[j] = temp_info[i].dead_before; |
| 2084 | temp_info[i].spill_no = j; |
| 2085 | if (j > max_ss_no) |
| 2086 | max_ss_no = j; |
| 2087 | } |
| 2088 | |
| 2089 | VG_(total_reg_rank) += (max_ss_no+1); |
| 2090 | |
| 2091 | /* Show live ranges and assigned spill slot nos. */ |
| 2092 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2093 | if (dis) { |
| 2094 | VG_(printf)("Live range assignments:\n"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2095 | |
| 2096 | for (i = 0; i < c1->nextTemp; i++) { |
| 2097 | if (temp_info[i].live_after == VG_NOTHING) |
| 2098 | continue; |
| 2099 | VG_(printf)( |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2100 | " LR %d is after %d to before %d\tspillno %d\n", |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2101 | i, |
| 2102 | temp_info[i].live_after, |
| 2103 | temp_info[i].dead_before, |
| 2104 | temp_info[i].spill_no |
| 2105 | ); |
| 2106 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2107 | VG_(printf)("\n"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2108 | } |
| 2109 | |
| 2110 | /* Now that we've established a spill slot number for each used |
| 2111 | temporary, we can go ahead and do the core of the "Second-chance |
| 2112 | binpacking" allocation algorithm. */ |
| 2113 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2114 | if (dis) VG_(printf)("Register allocated UCode:\n"); |
| 2115 | |
| 2116 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2117 | /* Resulting code goes here. We generate it all in a forwards |
| 2118 | pass. */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2119 | c2 = VG_(alloc_UCodeBlock)(); |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 2120 | c2->orig_eip = c1->orig_eip; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2121 | |
| 2122 | /* At the start, no TempRegs are assigned to any real register. |
| 2123 | Correspondingly, all temps claim to be currently resident in |
| 2124 | their spill slots, as computed by the previous two passes. */ |
| 2125 | for (i = 0; i < VG_MAX_REALREGS; i++) |
| 2126 | real_to_temp[i] = VG_NOTHING; |
| 2127 | for (i = 0; i < c1->nextTemp; i++) |
| 2128 | temp_info[i].real_no = VG_NOTHING; |
| 2129 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2130 | /* Process each insn in turn. */ |
| 2131 | for (i = 0; i < c1->used; i++) { |
| 2132 | |
| 2133 | if (c1->instrs[i].opcode == NOP) continue; |
| 2134 | VG_(uinstrs_prealloc)++; |
| 2135 | |
| 2136 | # if 0 |
| 2137 | /* Check map consistency. Expensive but correct. */ |
| 2138 | for (r = 0; r < VG_MAX_REALREGS; r++) { |
| 2139 | if (real_to_temp[r] != VG_NOTHING) { |
| 2140 | tno = real_to_temp[r]; |
| 2141 | vg_assert(tno >= 0 && tno < c1->nextTemp); |
| 2142 | vg_assert(temp_info[tno].real_no == r); |
| 2143 | } |
| 2144 | } |
| 2145 | for (tno = 0; tno < c1->nextTemp; tno++) { |
| 2146 | if (temp_info[tno].real_no != VG_NOTHING) { |
| 2147 | r = temp_info[tno].real_no; |
| 2148 | vg_assert(r >= 0 && r < VG_MAX_REALREGS); |
| 2149 | vg_assert(real_to_temp[r] == tno); |
| 2150 | } |
| 2151 | } |
| 2152 | # endif |
| 2153 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2154 | if (dis) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2155 | VG_(pp_UInstr)(i, &c1->instrs[i]); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2156 | |
| 2157 | /* First, free up enough real regs for this insn. This may |
| 2158 | generate spill stores since we may have to evict some TempRegs |
| 2159 | currently in real regs. Also generates spill loads. */ |
| 2160 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2161 | k = VG_(get_reg_usage)(&c1->instrs[i], TempReg, &tempUse[0], |
| 2162 | &isWrites[0]); |
njn | f4ce3d3 | 2003-02-10 10:17:26 +0000 | [diff] [blame] | 2163 | vg_assert(k >= 0 && k <= VG_MAX_REGS_USED); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2164 | |
| 2165 | /* For each ***different*** temp mentioned in the insn .... */ |
| 2166 | for (j = 0; j < k; j++) { |
| 2167 | |
| 2168 | /* First check if the temp is mentioned again later; if so, |
| 2169 | ignore this mention. We only want to process each temp |
| 2170 | used by the insn once, even if it is mentioned more than |
| 2171 | once. */ |
| 2172 | defer = False; |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2173 | tno = tempUse[j]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2174 | for (m = j+1; m < k; m++) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2175 | if (tempUse[m] == tno) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2176 | defer = True; |
| 2177 | if (defer) |
| 2178 | continue; |
| 2179 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2180 | /* Now we're trying to find a register for tempUse[j]. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2181 | First of all, if it already has a register assigned, we |
| 2182 | don't need to do anything more. */ |
| 2183 | if (temp_info[tno].real_no != VG_NOTHING) |
| 2184 | continue; |
| 2185 | |
| 2186 | /* No luck. The next thing to do is see if there is a |
| 2187 | currently unassigned register available. If so, bag it. */ |
| 2188 | for (r = 0; r < VG_MAX_REALREGS; r++) { |
| 2189 | if (real_to_temp[r] == VG_NOTHING) |
| 2190 | break; |
| 2191 | } |
| 2192 | if (r < VG_MAX_REALREGS) { |
| 2193 | real_to_temp[r] = tno; |
| 2194 | temp_info[tno].real_no = r; |
| 2195 | continue; |
| 2196 | } |
| 2197 | |
| 2198 | /* Unfortunately, that didn't pan out either. So we'll have |
| 2199 | to eject some other unfortunate TempReg into a spill slot |
| 2200 | in order to free up a register. Of course, we need to be |
| 2201 | careful not to eject some other TempReg needed by this |
| 2202 | insn. |
| 2203 | |
| 2204 | Select r in 0 .. VG_MAX_REALREGS-1 such that |
| 2205 | real_to_temp[r] is not mentioned in |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2206 | tempUse[0 .. k-1], since it would be just plain |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2207 | wrong to eject some other TempReg which we need to use in |
| 2208 | this insn. |
| 2209 | |
| 2210 | It is here that it is important to make a good choice of |
| 2211 | register to spill. */ |
| 2212 | |
| 2213 | /* First, mark those regs which are not spill candidates. */ |
| 2214 | for (r = 0; r < VG_MAX_REALREGS; r++) { |
| 2215 | is_spill_cand[r] = True; |
| 2216 | for (m = 0; m < k; m++) { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2217 | if (real_to_temp[r] == tempUse[m]) { |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2218 | is_spill_cand[r] = False; |
| 2219 | break; |
| 2220 | } |
| 2221 | } |
| 2222 | } |
| 2223 | |
| 2224 | /* We can choose any r satisfying is_spill_cand[r]. However, |
| 2225 | try to make a good choice. First, try and find r such |
| 2226 | that the associated TempReg is already dead. */ |
| 2227 | for (r = 0; r < VG_MAX_REALREGS; r++) { |
| 2228 | if (is_spill_cand[r] && |
| 2229 | temp_info[real_to_temp[r]].dead_before <= i) |
| 2230 | goto have_spill_cand; |
| 2231 | } |
| 2232 | |
| 2233 | /* No spill cand is mapped to a dead TempReg. Now we really |
| 2234 | _do_ have to generate spill code. Choose r so that the |
| 2235 | next use of its associated TempReg is as far ahead as |
| 2236 | possible, in the hope that this will minimise the number of |
| 2237 | consequent reloads required. This is a bit expensive, but |
| 2238 | we don't have to do it very often. */ |
| 2239 | { |
| 2240 | Int furthest_r = VG_MAX_REALREGS; |
| 2241 | Int furthest = 0; |
| 2242 | for (r = 0; r < VG_MAX_REALREGS; r++) { |
| 2243 | if (!is_spill_cand[r]) continue; |
| 2244 | for (m = i+1; m < c1->used; m++) |
| 2245 | if (uInstrMentionsTempReg(&c1->instrs[m], |
| 2246 | real_to_temp[r])) |
| 2247 | break; |
| 2248 | if (m > furthest) { |
| 2249 | furthest = m; |
| 2250 | furthest_r = r; |
| 2251 | } |
| 2252 | } |
| 2253 | r = furthest_r; |
| 2254 | goto have_spill_cand; |
| 2255 | } |
| 2256 | |
| 2257 | have_spill_cand: |
| 2258 | if (r == VG_MAX_REALREGS) |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2259 | VG_(core_panic)("new reg alloc: out of registers ?!"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2260 | |
| 2261 | /* Eject r. Important refinement: don't bother if the |
| 2262 | associated TempReg is now dead. */ |
| 2263 | vg_assert(real_to_temp[r] != VG_NOTHING); |
| 2264 | vg_assert(real_to_temp[r] != tno); |
| 2265 | temp_info[real_to_temp[r]].real_no = VG_NOTHING; |
| 2266 | if (temp_info[real_to_temp[r]].dead_before > i) { |
| 2267 | uInstr2(c2, PUT, 4, |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2268 | RealReg, VG_(rank_to_realreg)(r), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2269 | SpillNo, temp_info[real_to_temp[r]].spill_no); |
| 2270 | VG_(uinstrs_spill)++; |
| 2271 | spill_reqd = True; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2272 | if (dis) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2273 | VG_(pp_UInstr)(c2->used-1, &LAST_UINSTR(c2)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2274 | } |
| 2275 | |
| 2276 | /* Decide if tno is read. */ |
| 2277 | isRead = False; |
| 2278 | for (m = 0; m < k; m++) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2279 | if (tempUse[m] == tno && !isWrites[m]) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2280 | isRead = True; |
| 2281 | |
| 2282 | /* If so, generate a spill load. */ |
| 2283 | if (isRead) { |
| 2284 | uInstr2(c2, GET, 4, |
| 2285 | SpillNo, temp_info[tno].spill_no, |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2286 | RealReg, VG_(rank_to_realreg)(r) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2287 | VG_(uinstrs_spill)++; |
| 2288 | spill_reqd = True; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2289 | if (dis) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2290 | VG_(pp_UInstr)(c2->used-1, &LAST_UINSTR(c2)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2291 | } |
| 2292 | |
| 2293 | /* Update the forwards and backwards maps. */ |
| 2294 | real_to_temp[r] = tno; |
| 2295 | temp_info[tno].real_no = r; |
| 2296 | } |
| 2297 | |
| 2298 | /* By this point, all TempRegs mentioned by the insn have been |
| 2299 | bought into real regs. We now copy the insn to the output |
| 2300 | and use patchUInstr to convert its rTempRegs into |
| 2301 | realregs. */ |
| 2302 | for (j = 0; j < k; j++) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2303 | realUse[j] = VG_(rank_to_realreg)(temp_info[tempUse[j]].real_no); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2304 | VG_(copy_UInstr)(c2, &c1->instrs[i]); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2305 | patchUInstr(&LAST_UINSTR(c2), &tempUse[0], &realUse[0], k); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2306 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2307 | if (dis) { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2308 | VG_(pp_UInstr)(c2->used-1, &LAST_UINSTR(c2)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2309 | VG_(printf)("\n"); |
| 2310 | } |
| 2311 | } |
| 2312 | |
| 2313 | if (temp_info != NULL) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2314 | VG_(arena_free)(VG_AR_JITTER, temp_info); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2315 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2316 | VG_(free_UCodeBlock)(c1); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2317 | |
| 2318 | if (spill_reqd) |
| 2319 | VG_(translations_needing_spill)++; |
| 2320 | |
| 2321 | return c2; |
| 2322 | |
| 2323 | # undef VG_NOTHING |
| 2324 | |
| 2325 | } |
sewardj | 7c4b604 | 2003-06-14 15:47:15 +0000 | [diff] [blame] | 2326 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2327 | /* Analysis records liveness of all general-use RealRegs in the UCode. */ |
| 2328 | static void vg_realreg_liveness_analysis ( UCodeBlock* cb ) |
| 2329 | { |
| 2330 | Int i, j, k; |
| 2331 | RRegSet rregs_live; |
njn | f4ce3d3 | 2003-02-10 10:17:26 +0000 | [diff] [blame] | 2332 | Int regUse[VG_MAX_REGS_USED]; |
| 2333 | Bool isWrites[VG_MAX_REGS_USED]; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2334 | UInstr* u; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2335 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2336 | /* All regs are dead at the end of the block */ |
| 2337 | rregs_live = ALL_RREGS_DEAD; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2338 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2339 | for (i = cb->used-1; i >= 0; i--) { |
| 2340 | u = &cb->instrs[i]; |
| 2341 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2342 | u->regs_live_after = rregs_live; |
sewardj | 97ced73 | 2002-03-25 00:07:36 +0000 | [diff] [blame] | 2343 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2344 | k = VG_(get_reg_usage)(u, RealReg, ®Use[0], &isWrites[0]); |
sewardj | 97ced73 | 2002-03-25 00:07:36 +0000 | [diff] [blame] | 2345 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2346 | /* For each reg usage ... bwds in program order. Variable is live |
| 2347 | before this UInstr if it is read by this UInstr. |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2348 | Note that regUse[j] holds the Intel reg number, so we must |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2349 | convert it to our rank number. */ |
| 2350 | for (j = k-1; j >= 0; j--) { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2351 | SET_RREG_LIVENESS ( VG_(realreg_to_rank)(regUse[j]), |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2352 | rregs_live, |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2353 | !isWrites[j] ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2354 | } |
| 2355 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2356 | } |
| 2357 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2358 | /*------------------------------------------------------------*/ |
| 2359 | /*--- Main entry point for the JITter. ---*/ |
| 2360 | /*------------------------------------------------------------*/ |
| 2361 | |
| 2362 | /* Translate the basic block beginning at orig_addr, placing the |
| 2363 | translation in a vg_malloc'd block, the address and size of which |
| 2364 | are returned in trans_addr and trans_size. Length of the original |
| 2365 | block is also returned in orig_size. If the latter three are NULL, |
| 2366 | this call is being done for debugging purposes, in which case (a) |
| 2367 | throw away the translation once it is made, and (b) produce a load |
| 2368 | of debugging output. |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2369 | |
| 2370 | 'tst' is the identity of the thread needing this block. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2371 | */ |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 2372 | void VG_(translate) ( /*IN*/ ThreadId tid, |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2373 | /*IN*/ Addr orig_addr, |
| 2374 | /*OUT*/ UInt* orig_size, |
| 2375 | /*OUT*/ Addr* trans_addr, |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 2376 | /*OUT*/ UInt* trans_size, |
| 2377 | /*OUT*/ UShort jumps[VG_MAX_JUMPS]) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2378 | { |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2379 | Int n_disassembled_bytes, final_code_size; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2380 | Bool debugging_translation; |
| 2381 | UChar* final_code; |
| 2382 | UCodeBlock* cb; |
sewardj | a60be0e | 2003-05-26 08:47:27 +0000 | [diff] [blame] | 2383 | Bool notrace_until_done; |
sewardj | 1e86b8b | 2003-06-16 23:34:12 +0000 | [diff] [blame] | 2384 | UInt notrace_until_limit = 0; |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2385 | Segment *seg; |
| 2386 | Addr redir; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2387 | |
| 2388 | VGP_PUSHCC(VgpTranslate); |
| 2389 | debugging_translation |
| 2390 | = orig_size == NULL || trans_addr == NULL || trans_size == NULL; |
| 2391 | |
sewardj | 25c7c3a | 2003-07-10 00:17:58 +0000 | [diff] [blame] | 2392 | /* Look in the code redirect table to see if we should |
| 2393 | translate an alternative address for orig_addr. */ |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2394 | redir = VG_(code_redirect)(orig_addr); |
| 2395 | |
| 2396 | if (redir != orig_addr && VG_(clo_verbosity) >= 2) |
| 2397 | VG_(message)(Vg_UserMsg, |
| 2398 | "TRANSLATE: %p redirected to %p", |
| 2399 | orig_addr, |
| 2400 | redir ); |
| 2401 | orig_addr = redir; |
sewardj | 25c7c3a | 2003-07-10 00:17:58 +0000 | [diff] [blame] | 2402 | |
sewardj | a60be0e | 2003-05-26 08:47:27 +0000 | [diff] [blame] | 2403 | /* If codegen tracing, don't start tracing until |
| 2404 | notrace_until_limit blocks have gone by. This avoids printing |
| 2405 | huge amounts of useless junk when all we want to see is the last |
| 2406 | few blocks translated prior to a failure. Set |
| 2407 | notrace_until_limit to be the number of translations to be made |
| 2408 | before --trace-codegen= style printing takes effect. */ |
| 2409 | notrace_until_done |
fitzhardinge | 15117d2 | 2003-12-19 17:16:54 +0000 | [diff] [blame] | 2410 | = VG_(overall_in_count) >= notrace_until_limit; |
sewardj | a60be0e | 2003-05-26 08:47:27 +0000 | [diff] [blame] | 2411 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2412 | seg = VG_(find_segment)(orig_addr); |
| 2413 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2414 | if (!debugging_translation) |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 2415 | VG_TRACK( pre_mem_read, Vg_CoreTranslate, tid, "", orig_addr, 1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2416 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2417 | if (seg == NULL || |
| 2418 | !VG_(seg_contains)(seg, orig_addr, 1) || |
| 2419 | (seg->prot & (VKI_PROT_READ|VKI_PROT_EXEC)) == 0) { |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2420 | /* Code address is bad - deliver a signal instead */ |
| 2421 | vg_assert(!VG_(is_addressable)(orig_addr, 1)); |
| 2422 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2423 | if (seg != NULL && VG_(seg_contains)(seg, orig_addr, 1)) { |
| 2424 | vg_assert((seg->prot & VKI_PROT_EXEC) == 0); |
fitzhardinge | f1beb25 | 2004-03-16 09:49:08 +0000 | [diff] [blame] | 2425 | VG_(synth_fault_perms)(tid, orig_addr); |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2426 | } else |
fitzhardinge | f1beb25 | 2004-03-16 09:49:08 +0000 | [diff] [blame] | 2427 | VG_(synth_fault_mapping)(tid, orig_addr); |
jsgf | 855d93d | 2003-10-13 22:26:55 +0000 | [diff] [blame] | 2428 | |
jsgf | 855d93d | 2003-10-13 22:26:55 +0000 | [diff] [blame] | 2429 | return; |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2430 | } else |
| 2431 | seg->flags |= SF_CODE; /* contains cached code */ |
jsgf | 855d93d | 2003-10-13 22:26:55 +0000 | [diff] [blame] | 2432 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2433 | cb = VG_(alloc_UCodeBlock)(); |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 2434 | cb->orig_eip = orig_addr; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2435 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2436 | /* If doing any code printing, print a basic block start marker */ |
sewardj | a60be0e | 2003-05-26 08:47:27 +0000 | [diff] [blame] | 2437 | if (VG_(clo_trace_codegen) && notrace_until_done) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2438 | Char fnname[64] = ""; |
| 2439 | VG_(get_fnname_if_entry)(orig_addr, fnname, 64); |
| 2440 | VG_(printf)( |
njn | e0205ff | 2003-04-08 00:56:14 +0000 | [diff] [blame] | 2441 | "==== BB %d %s(%p) in %dB, out %dB, BBs exec'd %llu ====\n\n", |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2442 | VG_(overall_in_count), fnname, orig_addr, |
| 2443 | VG_(overall_in_osize), VG_(overall_in_tsize), |
| 2444 | VG_(bbs_done)); |
| 2445 | } |
| 2446 | |
| 2447 | /* True if a debug trans., or if bit N set in VG_(clo_trace_codegen). */ |
sewardj | a60be0e | 2003-05-26 08:47:27 +0000 | [diff] [blame] | 2448 | # define DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(n) \ |
| 2449 | ( debugging_translation \ |
| 2450 | || (notrace_until_done \ |
| 2451 | && (VG_(clo_trace_codegen) & (1 << (n-1))) )) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2452 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2453 | /* Disassemble this basic block into cb. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2454 | VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(1); |
| 2455 | VGP_PUSHCC(VgpToUCode); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2456 | n_disassembled_bytes = VG_(disBB) ( cb, orig_addr ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2457 | VGP_POPCC(VgpToUCode); |
| 2458 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2459 | /* Try and improve the code a bit. */ |
| 2460 | if (VG_(clo_optimise)) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2461 | VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(2); |
| 2462 | VGP_PUSHCC(VgpImprove); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2463 | vg_improve ( cb ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2464 | VGP_POPCC(VgpImprove); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2465 | } |
| 2466 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2467 | /* Skin's instrumentation (Nb: must set VG_(print_codegen) in case |
| 2468 | SK_(instrument) looks at it. */ |
| 2469 | VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(3); |
| 2470 | VGP_PUSHCC(VgpInstrument); |
| 2471 | cb = SK_(instrument) ( cb, orig_addr ); |
| 2472 | if (VG_(print_codegen)) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2473 | VG_(pp_UCodeBlock) ( cb, "Instrumented UCode:" ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2474 | VG_(saneUCodeBlock)( cb ); |
| 2475 | VGP_POPCC(VgpInstrument); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 2476 | |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 2477 | /* Add %ESP-update hooks if the skin requires them */ |
| 2478 | /* Nb: We don't print out this phase, because it doesn't do much */ |
| 2479 | if (VG_(need_to_handle_esp_assignment)()) { |
| 2480 | VGP_PUSHCC(VgpESPUpdate); |
| 2481 | cb = vg_ESP_update_pass ( cb ); |
| 2482 | VGP_POPCC(VgpESPUpdate); |
| 2483 | } |
| 2484 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2485 | /* Allocate registers. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2486 | VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(4); |
| 2487 | VGP_PUSHCC(VgpRegAlloc); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2488 | cb = vg_do_register_allocation ( cb ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2489 | VGP_POPCC(VgpRegAlloc); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2490 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2491 | /* Do post reg-alloc %e[acd]x liveness analysis (too boring to print |
| 2492 | * anything; results can be seen when emitting final code). */ |
| 2493 | VGP_PUSHCC(VgpLiveness); |
| 2494 | vg_realreg_liveness_analysis ( cb ); |
| 2495 | VGP_POPCC(VgpLiveness); |
| 2496 | |
| 2497 | /* Emit final code */ |
| 2498 | VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(5); |
| 2499 | |
| 2500 | VGP_PUSHCC(VgpFromUcode); |
sewardj | 22854b9 | 2002-11-30 14:00:47 +0000 | [diff] [blame] | 2501 | final_code = VG_(emit_code)(cb, &final_code_size, jumps ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2502 | VGP_POPCC(VgpFromUcode); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2503 | VG_(free_UCodeBlock)(cb); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2504 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2505 | #undef DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE |
| 2506 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2507 | if (debugging_translation) { |
| 2508 | /* Only done for debugging -- throw away final result. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2509 | VG_(arena_free)(VG_AR_JITTER, final_code); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2510 | } else { |
| 2511 | /* Doing it for real -- return values to caller. */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2512 | *orig_size = n_disassembled_bytes; |
| 2513 | *trans_addr = (Addr)final_code; |
| 2514 | *trans_size = final_code_size; |
| 2515 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2516 | VGP_POPCC(VgpTranslate); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2517 | } |
| 2518 | |
| 2519 | /*--------------------------------------------------------------------*/ |
| 2520 | /*--- end vg_translate.c ---*/ |
| 2521 | /*--------------------------------------------------------------------*/ |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 2522 | |