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2/*---------------------------------------------------------------*/
3/*--- ---*/
4/*--- This file (libvex_guest_x86.h) is ---*/
5/*--- Copyright (c) 2004 OpenWorks LLP. All rights reserved. ---*/
6/*--- ---*/
7/*---------------------------------------------------------------*/
8
sewardjf8ed9d82004-11-12 17:40:23 +00009/*
10 This file is part of LibVEX, a library for dynamic binary
11 instrumentation and translation.
12
13 Copyright (C) 2004 OpenWorks, LLP.
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; Version 2 dated June 1991 of the
18 license.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, or liability
23 for damages. See the GNU General Public License for more details.
24
25 Neither the names of the U.S. Department of Energy nor the
26 University of California nor the names of its contributors may be
27 used to endorse or promote products derived from this software
28 without prior written permission.
29
30 You should have received a copy of the GNU General Public License
31 along with this program; if not, write to the Free Software
32 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
33 USA.
34*/
35
sewardj0c2cb622004-09-06 23:21:21 +000036#ifndef __LIBVEX_PUB_GUEST_X86_H
37#define __LIBVEX_PUB_GUEST_X86_H
38
39#include "libvex_basictypes.h"
sewardj893aada2004-11-29 19:57:54 +000040#include "libvex_emwarn.h"
41
sewardj0c2cb622004-09-06 23:21:21 +000042
43/*---------------------------------------------------------------*/
sewardjf6dc3ce2004-10-19 01:03:46 +000044/*--- Vex's representation of the x86 CPU state. ---*/
45/*---------------------------------------------------------------*/
46
47/* The integer parts should be pretty straightforward. */
48
49/* Hmm, subregisters. The simulated state is stored in memory in the
50 host's byte ordering, so we can't say here what the offsets of %ax,
51 %al, %ah etc are since that depends on the host's byte ordering,
52 which we don't know. */
53
54/* FPU. For now, just simulate 8 64-bit registers, their tags, and
55 the reg-stack top pointer, of which only the least significant
56 three bits are relevant.
57
58 The model is:
59 F0 .. F7 are the 8 registers. FTOP[2:0] contains the
60 index of the current 'stack top' -- pretty meaningless, but
61 still. FTOP is a 32-bit value. FTOP[31:3] can be anything
62 (not guaranteed to be zero).
63
64 When a value is pushed onto the stack, ftop is first replaced by
65 (ftop-1) & 7, and then F[ftop] is assigned the value.
66
67 When a value is popped off the stack, the value is read from
68 F[ftop], and then ftop is replaced by (ftop+1) & 7.
69
70 In general, a reference to a register ST(i) actually references
71 F[ (ftop+i) & 7 ].
72
73 FTAG0 .. FTAG0+7 are the tags. Each is a byte, zero means empty,
74 non-zero means non-empty.
75
76 The general rule appears to be that a read or modify of a register
77 gets a stack underflow fault if the register is empty. A write of
78 a register (only a write, not a modify) gets a stack overflow fault
79 if the register is full. Note that "over" vs "under" is pretty
80 meaningless since the FP stack pointer can move around arbitrarily,
81 so it's really just two different kinds of exceptions:
82 register-empty and register full.
83
84 Naturally Intel (in its infinite wisdom) has seen fit to throw in
85 some ad-hoc inconsistencies to the fault-generation rules of the
86 above para, just to complicate everything. Known inconsistencies:
87
88 * fxam can read a register in any state without taking an underflow
89 fault.
90
91 * fst from st(0) to st(i) does not take an overflow fault even if the
92 destination is already full.
93
sewardjd01a9632004-11-30 13:18:37 +000094 FPROUND[1:0] is the FPU's notional rounding mode, encoded as per
95 the IRRoundingMode type (see libvex_ir.h). This just happens to be
96 the Intel encoding. Note carefully, the rounding mode is only
sewardj7df596b2004-12-06 14:29:12 +000097 observed on float-to-int conversions, and on float-to-float
98 rounding, but not for general float-to-float operations, which are
99 always rounded-to-nearest.
100
101 Loads/stores of the FPU control word are faked accordingly -- on
102 loads, everything except the rounding mode is ignored, and on
103 stores, you get a vanilla control world (0x037F) with the rounding
104 mode patched in. Hence the only values you can get are 0x037F,
105 0x077F, 0x0B7F or 0x0F7F. Vex will emit an emulation warning if
106 you try and load a control word which either (1) unmasks FP
107 exceptions, or (2) changes the default (80-bit) precision.
sewardjf6dc3ce2004-10-19 01:03:46 +0000108
109 FC3210 contains the C3, C2, C1 and C0 bits in the same place they
110 are in the FPU's status word. (bits 14, 10, 9, 8 respectively).
111 All other bits should be zero. The relevant mask to select just
112 those bits is 0x4700. To select C3, C2 and C0 only, the mask is
sewardj7df596b2004-12-06 14:29:12 +0000113 0x4500.
114
115 SSEROUND[1:0] is the SSE unit's notional rounding mode, encoded as
116 per the IRRoundingMode type. As with the FPU control word, the
117 rounding mode is the only part of %MXCSR that Vex observes. On
118 storing %MXCSR, you will get a vanilla word (0x1F80) with the
119 rounding mode patched in. Hence the only values you will get are
120 0x1F80, 0x3F80, 0x5F80 or 0x7F80. Vex will emit an emulation
121 warning if you try and load a control word which either (1) unmasks
122 any exceptions, (2) sets FZ (flush-to-zero) to 1, or (3) sets DAZ
sewardj3bd6f3e2004-12-13 10:48:19 +0000123 (denormals-are-zeroes) to 1.
sewardjf6dc3ce2004-10-19 01:03:46 +0000124
sewardj3bd6f3e2004-12-13 10:48:19 +0000125 Segments: initial prefixes of local and global segment descriptor
126 tables are modelled. guest_LDT is either zero (NULL) or points in
127 the host address space to an array of VEX_GUEST_X86_LDT_NENT
128 descriptors, which have the type VexGuestX86SegDescr, defined
129 below. Similarly, guest_GDT is either zero or points in the host
130 address space to an array of VEX_GUEST_X86_GDT_NENT descriptors.
131 The only place where these are used are in the helper function
132 x86g_use_seg(). LibVEX's client is responsible for pointing
133 guest_LDT and guest_GDT at suitable tables. The contents of these
134 tables are expected not to change during the execution of any given
135 superblock, but they may validly be changed by LibVEX's client in
136 between superblock executions.
137
138 Since x86g_use_seg() only expects these tables to have
139 VEX_GUEST_X86_{LDT,GDT}_NENT entries, LibVEX's client should not
140 attempt to write entries beyond those limits.
141*/
sewardjf6dc3ce2004-10-19 01:03:46 +0000142typedef
143 struct {
sewardj70f676d2004-12-10 14:59:57 +0000144 UInt guest_EAX; /* 0 */
sewardjf6dc3ce2004-10-19 01:03:46 +0000145 UInt guest_ECX;
146 UInt guest_EDX;
147 UInt guest_EBX;
148 UInt guest_ESP;
149 UInt guest_EBP;
150 UInt guest_ESI;
sewardj70f676d2004-12-10 14:59:57 +0000151 UInt guest_EDI; /* 28 */
sewardj2a2ba8b2004-11-08 13:14:06 +0000152 /* 4-word thunk used to calculate O S Z A C P flags. */
sewardj70f676d2004-12-10 14:59:57 +0000153 UInt guest_CC_OP; /* 32 */
sewardj2a2ba8b2004-11-08 13:14:06 +0000154 UInt guest_CC_DEP1;
155 UInt guest_CC_DEP2;
sewardj70f676d2004-12-10 14:59:57 +0000156 UInt guest_CC_NDEP; /* 44 */
sewardj2a2ba8b2004-11-08 13:14:06 +0000157 /* The D flag is stored here, encoded as either -1 or +1 */
sewardj70f676d2004-12-10 14:59:57 +0000158 UInt guest_DFLAG; /* 48 */
sewardj006a6a22004-10-26 00:50:52 +0000159 /* Bit 21 (ID) of eflags stored here, as either 0 or 1. */
sewardj70f676d2004-12-10 14:59:57 +0000160 UInt guest_IDFLAG; /* 52 */
sewardjf6dc3ce2004-10-19 01:03:46 +0000161 /* EIP */
sewardj70f676d2004-12-10 14:59:57 +0000162 UInt guest_EIP; /* 56 */
sewardjf6dc3ce2004-10-19 01:03:46 +0000163 /* FPU */
sewardj70f676d2004-12-10 14:59:57 +0000164 UInt guest_FTOP; /* 60 */
165 ULong guest_FPREG[8]; /* 64 */
166 UChar guest_FPTAG[8]; /* 128 */
167 UInt guest_FPROUND; /* 136 */
168 UInt guest_FC3210; /* 140 */
sewardjc9a43662004-11-30 18:51:59 +0000169 /* SSE */
sewardj70f676d2004-12-10 14:59:57 +0000170 UInt guest_SSEROUND; /* 144 */
171 U128 guest_XMM0; /* 148 */
sewardjc9a43662004-11-30 18:51:59 +0000172 U128 guest_XMM1;
173 U128 guest_XMM2;
174 U128 guest_XMM3;
175 U128 guest_XMM4;
176 U128 guest_XMM5;
177 U128 guest_XMM6;
178 U128 guest_XMM7;
sewardj063f02f2004-10-20 12:36:12 +0000179 /* Segment registers. */
180 UShort guest_CS;
181 UShort guest_DS;
182 UShort guest_ES;
183 UShort guest_FS;
184 UShort guest_GS;
185 UShort guest_SS;
sewardj3bd6f3e2004-12-13 10:48:19 +0000186 /* LDT/GDT stuff. */
187 HWord guest_LDT; /* host addr, a VexGuestX86SegDescr* */
188 HWord guest_GDT; /* host addr, a VexGuestX86SegDescr* */
sewardj1f126c52005-03-16 13:57:58 +0000189
sewardj893aada2004-11-29 19:57:54 +0000190 /* Emulation warnings */
191 UInt guest_EMWARN;
sewardj1f126c52005-03-16 13:57:58 +0000192
193 /* Translation-invalidation area description. Not used on x86
194 (there is no invalidate-icache insn), but needed so as to
195 allow users of the library to uniformly assume that the guest
196 state contains these two fields -- otherwise there is
197 compilation breakage. On x86, these two fields are set to
198 zero by LibVEX_GuestX86_initialise and then should be ignored
199 forever thereafter. */
200 UInt guest_TISTART;
201 UInt guest_TILEN;
202
sewardj81ec4182004-10-25 23:15:52 +0000203 /* Padding to make it have an 8-aligned size */
sewardjc9a43662004-11-30 18:51:59 +0000204 UInt padding;
sewardjf6dc3ce2004-10-19 01:03:46 +0000205 }
206 VexGuestX86State;
207
sewardj3bd6f3e2004-12-13 10:48:19 +0000208#define VEX_GUEST_X86_LDT_NENT 64
209#define VEX_GUEST_X86_GDT_NENT 16
210
211
212/*---------------------------------------------------------------*/
213/*--- Types for x86 guest stuff. ---*/
214/*---------------------------------------------------------------*/
215
216/* VISIBLE TO LIBRARY CLIENT */
217
218/* This is the hardware-format for a segment descriptor, ie what the
219 x86 actually deals with. It is 8 bytes long. It's ugly. */
220
221typedef struct {
222 union {
223 struct {
224 UShort LimitLow;
225 UShort BaseLow;
226 UInt BaseMid : 8;
227 UInt Type : 5;
228 UInt Dpl : 2;
229 UInt Pres : 1;
230 UInt LimitHi : 4;
231 UInt Sys : 1;
232 UInt Reserved_0 : 1;
233 UInt Default_Big : 1;
234 UInt Granularity : 1;
235 UInt BaseHi : 8;
236 } Bits;
237 struct {
238 UInt word1;
239 UInt word2;
240 } Words;
241 }
242 LdtEnt;
243} VexGuestX86SegDescr;
sewardjf6dc3ce2004-10-19 01:03:46 +0000244
sewardj8d2291c2004-10-25 14:50:21 +0000245
sewardjf6dc3ce2004-10-19 01:03:46 +0000246/*---------------------------------------------------------------*/
sewardj0c2cb622004-09-06 23:21:21 +0000247/*--- Utility functions for x86 guest stuff. ---*/
248/*---------------------------------------------------------------*/
249
sewardj8d2291c2004-10-25 14:50:21 +0000250/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT */
251
sewardj76bdc802004-10-25 15:33:26 +0000252/* Initialise all guest x86 state. The FPU is put in default mode. */
253extern
254void LibVEX_GuestX86_initialise ( /*OUT*/VexGuestX86State* vex_state );
255
256
sewardjf6dc3ce2004-10-19 01:03:46 +0000257/* Extract from the supplied VexGuestX86State structure the
258 corresponding native %eflags value. */
sewardjf6dc3ce2004-10-19 01:03:46 +0000259extern
sewardj76bdc802004-10-25 15:33:26 +0000260UInt LibVEX_GuestX86_get_eflags ( /*IN*/VexGuestX86State* vex_state );
sewardjf6dc3ce2004-10-19 01:03:46 +0000261
sewardj0c2cb622004-09-06 23:21:21 +0000262
sewardj38a3f862005-01-13 15:06:51 +0000263
sewardj0c2cb622004-09-06 23:21:21 +0000264#endif /* ndef __LIBVEX_PUB_GUEST_X86_H */
265
266/*---------------------------------------------------------------*/
267/*--- libvex_guest_x86.h ---*/
268/*---------------------------------------------------------------*/