bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 1 | /* -*- mode: C; c-basic-offset: 3; -*- */ |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 2 | /* |
bart | 86562bd | 2009-02-16 19:43:56 +0000 | [diff] [blame] | 3 | This file is part of drd, a thread error detector. |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 4 | |
| 5 | Copyright (C) 2006-2009 Bart Van Assche <bart.vanassche@gmail.com>. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or |
| 8 | modify it under the terms of the GNU General Public License as |
| 9 | published by the Free Software Foundation; either version 2 of the |
| 10 | License, or (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, but |
| 13 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program; if not, write to the Free Software |
| 19 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 20 | 02111-1307, USA. |
| 21 | |
| 22 | The GNU General Public License is contained in the file COPYING. |
| 23 | */ |
| 24 | |
| 25 | |
| 26 | #include "drd_bitmap.h" |
| 27 | #include "drd_thread_bitmap.h" |
bart | 41b226c | 2009-02-14 16:55:19 +0000 | [diff] [blame] | 28 | #include "drd_vc.h" /* DRD_(vc_snprint)() */ |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 29 | |
| 30 | /* Include several source files here in order to allow the compiler to */ |
| 31 | /* do more inlining. */ |
| 32 | #include "drd_bitmap.c" |
| 33 | #include "drd_load_store.h" |
| 34 | #include "drd_segment.c" |
| 35 | #include "drd_thread.c" |
| 36 | #include "drd_vc.c" |
| 37 | #include "libvex_guest_offsets.h" |
| 38 | |
| 39 | |
| 40 | /* STACK_POINTER_OFFSET: VEX register offset for the stack pointer register. */ |
| 41 | #if defined(VGA_x86) |
| 42 | #define STACK_POINTER_OFFSET OFFSET_x86_ESP |
| 43 | #elif defined(VGA_amd64) |
| 44 | #define STACK_POINTER_OFFSET OFFSET_amd64_RSP |
| 45 | #elif defined(VGA_ppc32) |
| 46 | #define STACK_POINTER_OFFSET ((OFFSET_ppc32_GPR0 + OFFSET_ppc32_GPR2) / 2) |
| 47 | #elif defined(VGA_ppc64) |
| 48 | #define STACK_POINTER_OFFSET ((OFFSET_ppc64_GPR0 + OFFSET_ppc64_GPR2) / 2) |
| 49 | #else |
| 50 | #error Unknown architecture. |
| 51 | #endif |
| 52 | |
| 53 | |
| 54 | /* Local variables. */ |
| 55 | |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 56 | static Bool s_check_stack_accesses = False; |
| 57 | static Bool s_first_race_only = False; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 58 | |
| 59 | |
| 60 | /* Function definitions. */ |
| 61 | |
| 62 | Bool DRD_(get_check_stack_accesses)() |
| 63 | { |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 64 | return s_check_stack_accesses; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | void DRD_(set_check_stack_accesses)(const Bool c) |
| 68 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 69 | tl_assert(c == False || c == True); |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 70 | s_check_stack_accesses = c; |
| 71 | } |
| 72 | |
| 73 | Bool DRD_(get_first_race_only)() |
| 74 | { |
| 75 | return s_first_race_only; |
| 76 | } |
| 77 | |
| 78 | void DRD_(set_first_race_only)(const Bool fro) |
| 79 | { |
| 80 | tl_assert(fro == False || fro == True); |
| 81 | s_first_race_only = fro; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 82 | } |
| 83 | |
bart | 1335ecc | 2009-02-14 16:10:53 +0000 | [diff] [blame] | 84 | void DRD_(trace_mem_access)(const Addr addr, const SizeT size, |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 85 | const BmAccessTypeT access_type) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 86 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 87 | if (DRD_(is_any_traced)(addr, addr + size)) |
| 88 | { |
bart | 8f822af | 2009-06-08 18:20:42 +0000 | [diff] [blame] | 89 | char* vc; |
| 90 | |
| 91 | vc = DRD_(vc_aprint)(DRD_(thread_get_vc)(DRD_(thread_get_running_tid)())); |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 92 | VG_(message)(Vg_UserMsg, |
bart | 63c92ea | 2009-07-19 17:53:56 +0000 | [diff] [blame] | 93 | "%s 0x%lx size %ld (thread %d / vc %s)\n", |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 94 | access_type == eLoad |
| 95 | ? "load " |
| 96 | : access_type == eStore |
| 97 | ? "store" |
| 98 | : access_type == eStart |
| 99 | ? "start" |
| 100 | : access_type == eEnd |
| 101 | ? "end " |
| 102 | : "????", |
| 103 | addr, |
| 104 | size, |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 105 | DRD_(thread_get_running_tid)(), |
| 106 | vc); |
bart | 8f822af | 2009-06-08 18:20:42 +0000 | [diff] [blame] | 107 | VG_(free)(vc); |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 108 | VG_(get_and_pp_StackTrace)(VG_(get_running_tid)(), |
| 109 | VG_(clo_backtrace_size)); |
| 110 | tl_assert(DRD_(DrdThreadIdToVgThreadId)(DRD_(thread_get_running_tid)()) |
| 111 | == VG_(get_running_tid)()); |
| 112 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 113 | } |
| 114 | |
| 115 | static VG_REGPARM(2) void drd_trace_mem_load(const Addr addr, const SizeT size) |
| 116 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 117 | return DRD_(trace_mem_access)(addr, size, eLoad); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 118 | } |
| 119 | |
| 120 | static VG_REGPARM(2) void drd_trace_mem_store(const Addr addr,const SizeT size) |
| 121 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 122 | return DRD_(trace_mem_access)(addr, size, eStore); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | static void drd_report_race(const Addr addr, const SizeT size, |
| 126 | const BmAccessTypeT access_type) |
| 127 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 128 | DataRaceErrInfo drei; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 129 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 130 | drei.tid = DRD_(thread_get_running_tid)(); |
| 131 | drei.addr = addr; |
| 132 | drei.size = size; |
| 133 | drei.access_type = access_type; |
| 134 | VG_(maybe_record_error)(VG_(get_running_tid)(), |
| 135 | DataRaceErr, |
| 136 | VG_(get_IP)(VG_(get_running_tid)()), |
| 137 | "Conflicting accesses", |
| 138 | &drei); |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 139 | |
| 140 | if (s_first_race_only) |
| 141 | { |
| 142 | DRD_(start_suppression)(addr, addr + size, "first race only"); |
| 143 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 144 | } |
| 145 | |
bart | 99edb29 | 2009-02-15 15:59:20 +0000 | [diff] [blame] | 146 | VG_REGPARM(2) void DRD_(trace_load)(Addr addr, SizeT size) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 147 | { |
| 148 | #ifdef ENABLE_DRD_CONSISTENCY_CHECKS |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 149 | /* The assert below has been commented out because of performance reasons.*/ |
| 150 | tl_assert(thread_get_running_tid() |
| 151 | == VgThreadIdToDrdThreadId(VG_(get_running_tid()))); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 152 | #endif |
| 153 | |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 154 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 155 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 156 | || ! DRD_(thread_address_on_stack)(addr)) |
| 157 | && bm_access_load_triggers_conflict(addr, addr + size) |
| 158 | && ! DRD_(is_suppressed)(addr, addr + size)) |
| 159 | { |
| 160 | drd_report_race(addr, size, eLoad); |
| 161 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 162 | } |
| 163 | |
| 164 | static VG_REGPARM(1) void drd_trace_load_1(Addr addr) |
| 165 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 166 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 167 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 168 | || ! DRD_(thread_address_on_stack)(addr)) |
| 169 | && bm_access_load_1_triggers_conflict(addr) |
| 170 | && ! DRD_(is_suppressed)(addr, addr + 1)) |
| 171 | { |
| 172 | drd_report_race(addr, 1, eLoad); |
| 173 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 174 | } |
| 175 | |
| 176 | static VG_REGPARM(1) void drd_trace_load_2(Addr addr) |
| 177 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 178 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 179 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 180 | || ! DRD_(thread_address_on_stack)(addr)) |
| 181 | && bm_access_load_2_triggers_conflict(addr) |
| 182 | && ! DRD_(is_suppressed)(addr, addr + 2)) |
| 183 | { |
| 184 | drd_report_race(addr, 2, eLoad); |
| 185 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 186 | } |
| 187 | |
| 188 | static VG_REGPARM(1) void drd_trace_load_4(Addr addr) |
| 189 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 190 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 191 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 192 | || ! DRD_(thread_address_on_stack)(addr)) |
| 193 | && bm_access_load_4_triggers_conflict(addr) |
| 194 | && ! DRD_(is_suppressed)(addr, addr + 4)) |
| 195 | { |
| 196 | drd_report_race(addr, 4, eLoad); |
| 197 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 198 | } |
| 199 | |
| 200 | static VG_REGPARM(1) void drd_trace_load_8(Addr addr) |
| 201 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 202 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 203 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 204 | || ! DRD_(thread_address_on_stack)(addr)) |
| 205 | && bm_access_load_8_triggers_conflict(addr) |
| 206 | && ! DRD_(is_suppressed)(addr, addr + 8)) |
| 207 | { |
| 208 | drd_report_race(addr, 8, eLoad); |
| 209 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 210 | } |
| 211 | |
bart | 99edb29 | 2009-02-15 15:59:20 +0000 | [diff] [blame] | 212 | VG_REGPARM(2) void DRD_(trace_store)(Addr addr, SizeT size) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 213 | { |
| 214 | #ifdef ENABLE_DRD_CONSISTENCY_CHECKS |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 215 | /* The assert below has been commented out because of performance reasons.*/ |
| 216 | tl_assert(thread_get_running_tid() |
| 217 | == VgThreadIdToDrdThreadId(VG_(get_running_tid()))); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 218 | #endif |
| 219 | |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 220 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 221 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 222 | || ! DRD_(thread_address_on_stack)(addr)) |
| 223 | && bm_access_store_triggers_conflict(addr, addr + size) |
| 224 | && ! DRD_(is_suppressed)(addr, addr + size)) |
| 225 | { |
| 226 | drd_report_race(addr, size, eStore); |
| 227 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 228 | } |
| 229 | |
| 230 | static VG_REGPARM(1) void drd_trace_store_1(Addr addr) |
| 231 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 232 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 233 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 234 | || ! DRD_(thread_address_on_stack)(addr)) |
| 235 | && bm_access_store_1_triggers_conflict(addr) |
| 236 | && ! DRD_(is_suppressed)(addr, addr + 1)) |
| 237 | { |
| 238 | drd_report_race(addr, 1, eStore); |
| 239 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 240 | } |
| 241 | |
| 242 | static VG_REGPARM(1) void drd_trace_store_2(Addr addr) |
| 243 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 244 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 245 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 246 | || ! DRD_(thread_address_on_stack)(addr)) |
| 247 | && bm_access_store_2_triggers_conflict(addr) |
| 248 | && ! DRD_(is_suppressed)(addr, addr + 2)) |
| 249 | { |
| 250 | drd_report_race(addr, 2, eStore); |
| 251 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 252 | } |
| 253 | |
| 254 | static VG_REGPARM(1) void drd_trace_store_4(Addr addr) |
| 255 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 256 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 257 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 258 | || ! DRD_(thread_address_on_stack)(addr)) |
| 259 | && bm_access_store_4_triggers_conflict(addr) |
| 260 | && ! DRD_(is_suppressed)(addr, addr + 4)) |
| 261 | { |
| 262 | drd_report_race(addr, 4, eStore); |
| 263 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 264 | } |
| 265 | |
| 266 | static VG_REGPARM(1) void drd_trace_store_8(Addr addr) |
| 267 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 268 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 269 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 270 | || ! DRD_(thread_address_on_stack)(addr)) |
| 271 | && bm_access_store_8_triggers_conflict(addr) |
| 272 | && ! DRD_(is_suppressed)(addr, addr + 8)) |
| 273 | { |
| 274 | drd_report_race(addr, 8, eStore); |
| 275 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 276 | } |
| 277 | |
| 278 | /** |
| 279 | * Return true if and only if addr_expr matches the pattern (SP) or |
| 280 | * <offset>(SP). |
| 281 | */ |
| 282 | static Bool is_stack_access(IRSB* const bb, IRExpr* const addr_expr) |
| 283 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 284 | Bool result = False; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 285 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 286 | if (addr_expr->tag == Iex_RdTmp) |
| 287 | { |
| 288 | int i; |
| 289 | for (i = 0; i < bb->stmts_size; i++) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 290 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 291 | if (bb->stmts[i] |
| 292 | && bb->stmts[i]->tag == Ist_WrTmp |
| 293 | && bb->stmts[i]->Ist.WrTmp.tmp == addr_expr->Iex.RdTmp.tmp) |
| 294 | { |
| 295 | IRExpr* e = bb->stmts[i]->Ist.WrTmp.data; |
| 296 | if (e->tag == Iex_Get && e->Iex.Get.offset == STACK_POINTER_OFFSET) |
| 297 | { |
| 298 | result = True; |
| 299 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 300 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 301 | //ppIRExpr(e); |
| 302 | //VG_(printf)(" (%s)\n", result ? "True" : "False"); |
| 303 | break; |
| 304 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 305 | } |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 306 | } |
| 307 | return result; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 308 | } |
| 309 | |
| 310 | static void instrument_load(IRSB* const bb, |
| 311 | IRExpr* const addr_expr, |
| 312 | const HWord size) |
| 313 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 314 | IRExpr* size_expr; |
| 315 | IRExpr** argv; |
| 316 | IRDirty* di; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 317 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 318 | if (UNLIKELY(DRD_(any_address_is_traced)())) |
| 319 | { |
| 320 | addStmtToIRSB(bb, |
| 321 | IRStmt_Dirty( |
| 322 | unsafeIRDirty_0_N(/*regparms*/2, |
| 323 | "drd_trace_load", |
| 324 | VG_(fnptr_to_fnentry) |
| 325 | (drd_trace_mem_load), |
| 326 | mkIRExprVec_2(addr_expr, |
| 327 | mkIRExpr_HWord(size))))); |
| 328 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 329 | |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 330 | if (! s_check_stack_accesses && is_stack_access(bb, addr_expr)) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 331 | return; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 332 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 333 | switch (size) |
| 334 | { |
| 335 | case 1: |
| 336 | argv = mkIRExprVec_1(addr_expr); |
| 337 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 338 | "drd_trace_load_1", |
| 339 | VG_(fnptr_to_fnentry)(drd_trace_load_1), |
| 340 | argv); |
| 341 | break; |
| 342 | case 2: |
| 343 | argv = mkIRExprVec_1(addr_expr); |
| 344 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 345 | "drd_trace_load_2", |
| 346 | VG_(fnptr_to_fnentry)(drd_trace_load_2), |
| 347 | argv); |
| 348 | break; |
| 349 | case 4: |
| 350 | argv = mkIRExprVec_1(addr_expr); |
| 351 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 352 | "drd_trace_load_4", |
| 353 | VG_(fnptr_to_fnentry)(drd_trace_load_4), |
| 354 | argv); |
| 355 | break; |
| 356 | case 8: |
| 357 | argv = mkIRExprVec_1(addr_expr); |
| 358 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 359 | "drd_trace_load_8", |
| 360 | VG_(fnptr_to_fnentry)(drd_trace_load_8), |
| 361 | argv); |
| 362 | break; |
| 363 | default: |
| 364 | size_expr = mkIRExpr_HWord(size); |
| 365 | argv = mkIRExprVec_2(addr_expr, size_expr); |
| 366 | di = unsafeIRDirty_0_N(/*regparms*/2, |
| 367 | "drd_trace_load", |
| 368 | VG_(fnptr_to_fnentry)(DRD_(trace_load)), |
| 369 | argv); |
| 370 | break; |
| 371 | } |
| 372 | addStmtToIRSB(bb, IRStmt_Dirty(di)); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 373 | } |
| 374 | |
| 375 | static void instrument_store(IRSB* const bb, |
| 376 | IRExpr* const addr_expr, |
| 377 | const HWord size) |
| 378 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 379 | IRExpr* size_expr; |
| 380 | IRExpr** argv; |
| 381 | IRDirty* di; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 382 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 383 | if (UNLIKELY(DRD_(any_address_is_traced)())) |
| 384 | { |
| 385 | addStmtToIRSB(bb, |
| 386 | IRStmt_Dirty( |
| 387 | unsafeIRDirty_0_N(/*regparms*/2, |
| 388 | "drd_trace_store", |
| 389 | VG_(fnptr_to_fnentry) |
| 390 | (drd_trace_mem_store), |
| 391 | mkIRExprVec_2(addr_expr, |
| 392 | mkIRExpr_HWord(size))))); |
| 393 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 394 | |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 395 | if (! s_check_stack_accesses && is_stack_access(bb, addr_expr)) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 396 | return; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 397 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 398 | switch (size) |
| 399 | { |
| 400 | case 1: |
| 401 | argv = mkIRExprVec_1(addr_expr); |
| 402 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 403 | "drd_trace_store_1", |
| 404 | VG_(fnptr_to_fnentry)(drd_trace_store_1), |
| 405 | argv); |
| 406 | break; |
| 407 | case 2: |
| 408 | argv = mkIRExprVec_1(addr_expr); |
| 409 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 410 | "drd_trace_store_2", |
| 411 | VG_(fnptr_to_fnentry)(drd_trace_store_2), |
| 412 | argv); |
| 413 | break; |
| 414 | case 4: |
| 415 | argv = mkIRExprVec_1(addr_expr); |
| 416 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 417 | "drd_trace_store_4", |
| 418 | VG_(fnptr_to_fnentry)(drd_trace_store_4), |
| 419 | argv); |
| 420 | break; |
| 421 | case 8: |
| 422 | argv = mkIRExprVec_1(addr_expr); |
| 423 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 424 | "drd_trace_store_8", |
| 425 | VG_(fnptr_to_fnentry)(drd_trace_store_8), |
| 426 | argv); |
| 427 | break; |
| 428 | default: |
| 429 | size_expr = mkIRExpr_HWord(size); |
| 430 | argv = mkIRExprVec_2(addr_expr, size_expr); |
| 431 | di = unsafeIRDirty_0_N(/*regparms*/2, |
| 432 | "drd_trace_store", |
| 433 | VG_(fnptr_to_fnentry)(DRD_(trace_store)), |
| 434 | argv); |
| 435 | break; |
| 436 | } |
| 437 | addStmtToIRSB(bb, IRStmt_Dirty(di)); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 438 | } |
| 439 | |
bart | 1335ecc | 2009-02-14 16:10:53 +0000 | [diff] [blame] | 440 | IRSB* DRD_(instrument)(VgCallbackClosure* const closure, |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 441 | IRSB* const bb_in, |
| 442 | VexGuestLayout* const layout, |
| 443 | VexGuestExtents* const vge, |
| 444 | IRType const gWordTy, |
| 445 | IRType const hWordTy) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 446 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 447 | IRDirty* di; |
| 448 | Int i; |
| 449 | IRSB* bb; |
| 450 | IRExpr** argv; |
| 451 | Bool instrument = True; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 452 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 453 | /* Set up BB */ |
| 454 | bb = emptyIRSB(); |
| 455 | bb->tyenv = deepCopyIRTypeEnv(bb_in->tyenv); |
| 456 | bb->next = deepCopyIRExpr(bb_in->next); |
| 457 | bb->jumpkind = bb_in->jumpkind; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 458 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 459 | for (i = 0; i < bb_in->stmts_used; i++) |
| 460 | { |
| 461 | IRStmt* const st = bb_in->stmts[i]; |
| 462 | tl_assert(st); |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame^] | 463 | tl_assert(isFlatIRStmt(st)); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 464 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 465 | switch (st->tag) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 466 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 467 | /* Note: the code for not instrumenting the code in .plt */ |
| 468 | /* sections is only necessary on CentOS 3.0 x86 (kernel 2.4.21 */ |
| 469 | /* + glibc 2.3.2 + NPTL 0.60 + binutils 2.14.90.0.4). */ |
| 470 | /* This is because on this platform dynamic library symbols are */ |
| 471 | /* relocated in another way than by later binutils versions. The */ |
| 472 | /* linker e.g. does not generate .got.plt sections on CentOS 3.0. */ |
| 473 | case Ist_IMark: |
sewardj | e3f1e59 | 2009-07-31 09:41:29 +0000 | [diff] [blame] | 474 | instrument = VG_(DebugInfo_sect_kind)(NULL, 0, st->Ist.IMark.addr) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 475 | != Vg_SectPLT; |
| 476 | addStmtToIRSB(bb, st); |
| 477 | break; |
| 478 | |
| 479 | case Ist_MBE: |
| 480 | switch (st->Ist.MBE.event) |
| 481 | { |
| 482 | case Imbe_Fence: |
| 483 | break; /* not interesting */ |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 484 | default: |
| 485 | tl_assert(0); |
| 486 | } |
| 487 | addStmtToIRSB(bb, st); |
| 488 | break; |
| 489 | |
| 490 | case Ist_Store: |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame^] | 491 | if (instrument) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 492 | { |
| 493 | instrument_store(bb, |
| 494 | st->Ist.Store.addr, |
| 495 | sizeofIRType(typeOfIRExpr(bb->tyenv, |
| 496 | st->Ist.Store.data))); |
| 497 | } |
| 498 | addStmtToIRSB(bb, st); |
| 499 | break; |
| 500 | |
| 501 | case Ist_WrTmp: |
| 502 | if (instrument) |
| 503 | { |
| 504 | const IRExpr* const data = st->Ist.WrTmp.data; |
| 505 | if (data->tag == Iex_Load) |
| 506 | { |
| 507 | instrument_load(bb, |
| 508 | data->Iex.Load.addr, |
| 509 | sizeofIRType(data->Iex.Load.ty)); |
| 510 | } |
| 511 | } |
| 512 | addStmtToIRSB(bb, st); |
| 513 | break; |
| 514 | |
| 515 | case Ist_Dirty: |
| 516 | if (instrument) |
| 517 | { |
| 518 | IRDirty* d = st->Ist.Dirty.details; |
| 519 | IREffect const mFx = d->mFx; |
| 520 | switch (mFx) { |
| 521 | case Ifx_None: |
| 522 | break; |
| 523 | case Ifx_Read: |
| 524 | case Ifx_Write: |
| 525 | case Ifx_Modify: |
| 526 | tl_assert(d->mAddr); |
| 527 | tl_assert(d->mSize > 0); |
| 528 | argv = mkIRExprVec_2(d->mAddr, mkIRExpr_HWord(d->mSize)); |
| 529 | if (mFx == Ifx_Read || mFx == Ifx_Modify) { |
| 530 | di = unsafeIRDirty_0_N( |
| 531 | /*regparms*/2, |
| 532 | "drd_trace_load", |
| 533 | VG_(fnptr_to_fnentry)(DRD_(trace_load)), |
| 534 | argv); |
| 535 | addStmtToIRSB(bb, IRStmt_Dirty(di)); |
| 536 | } |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 537 | if (mFx == Ifx_Write || mFx == Ifx_Modify) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 538 | { |
| 539 | di = unsafeIRDirty_0_N( |
| 540 | /*regparms*/2, |
| 541 | "drd_trace_store", |
| 542 | VG_(fnptr_to_fnentry)(DRD_(trace_store)), |
| 543 | argv); |
| 544 | addStmtToIRSB(bb, IRStmt_Dirty(di)); |
| 545 | } |
| 546 | break; |
| 547 | default: |
| 548 | tl_assert(0); |
| 549 | } |
| 550 | } |
| 551 | addStmtToIRSB(bb, st); |
| 552 | break; |
| 553 | |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 554 | case Ist_CAS: |
| 555 | if (instrument) |
| 556 | { |
bart | a14e328 | 2009-07-11 14:35:59 +0000 | [diff] [blame] | 557 | /* |
| 558 | * Treat compare-and-swap as a read. By handling atomic |
| 559 | * instructions as read instructions no data races are reported |
| 560 | * between conflicting atomic operations nor between atomic |
| 561 | * operations and non-atomic reads. Conflicts between atomic |
| 562 | * operations and non-atomic write operations are still reported |
| 563 | * however. |
| 564 | */ |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 565 | Int dataSize; |
| 566 | IRCAS* cas = st->Ist.CAS.details; |
| 567 | tl_assert(cas->addr != NULL); |
| 568 | tl_assert(cas->dataLo != NULL); |
| 569 | dataSize = sizeofIRType(typeOfIRExpr(bb->tyenv, cas->dataLo)); |
| 570 | if (cas->dataHi != NULL) |
| 571 | dataSize *= 2; /* since it's a doubleword-CAS */ |
| 572 | instrument_load(bb, cas->addr, dataSize); |
| 573 | } |
| 574 | addStmtToIRSB(bb, st); |
| 575 | break; |
| 576 | |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame^] | 577 | case Ist_LLSC: { |
| 578 | /* Ignore store-conditionals, and handle load-linked's |
| 579 | exactly like normal loads. */ |
| 580 | IRType dataTy; |
| 581 | if (st->Ist.LLSC.storedata == NULL) |
| 582 | { |
| 583 | /* LL */ |
| 584 | dataTy = typeOfIRTemp(bb_in->tyenv, st->Ist.LLSC.result); |
| 585 | if (instrument) { |
| 586 | instrument_load(bb, |
| 587 | st->Ist.LLSC.addr, |
| 588 | sizeofIRType(dataTy)); |
| 589 | } |
| 590 | } |
| 591 | else |
| 592 | { |
| 593 | /* SC */ |
| 594 | /*ignore */ |
| 595 | } |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 596 | addStmtToIRSB(bb, st); |
| 597 | break; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 598 | } |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame^] | 599 | |
| 600 | case Ist_NoOp: |
| 601 | case Ist_AbiHint: |
| 602 | case Ist_Put: |
| 603 | case Ist_PutI: |
| 604 | case Ist_Exit: |
| 605 | /* None of these can contain any memory references. */ |
| 606 | addStmtToIRSB(bb, st); |
| 607 | break; |
| 608 | |
| 609 | default: |
| 610 | ppIRStmt(st); |
| 611 | tl_assert(0); |
| 612 | } |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 613 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 614 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 615 | return bb; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 616 | } |
| 617 | |