blob: 7dfcd12eb9cc3fbcad85b5a35486e75c236f4d87 [file] [log] [blame]
Ben Cheng663860b2013-01-31 15:38:14 -08001#define OFFSET_x86_EAX 8
2#define OFFSET_x86_EBX 20
3#define OFFSET_x86_ECX 12
4#define OFFSET_x86_EDX 16
5#define OFFSET_x86_ESI 32
6#define OFFSET_x86_EDI 36
7#define OFFSET_x86_EBP 28
8#define OFFSET_x86_ESP 24
9#define OFFSET_x86_EIP 68
10#define OFFSET_x86_CS 288
11#define OFFSET_x86_DS 290
12#define OFFSET_x86_ES 292
13#define OFFSET_x86_FS 294
14#define OFFSET_x86_GS 296
15#define OFFSET_x86_SS 298
16#define OFFSET_amd64_RAX 16
17#define OFFSET_amd64_RBX 40
18#define OFFSET_amd64_RCX 24
19#define OFFSET_amd64_RDX 32
20#define OFFSET_amd64_RSI 64
21#define OFFSET_amd64_RDI 72
22#define OFFSET_amd64_RSP 48
23#define OFFSET_amd64_RBP 56
24#define OFFSET_amd64_R8 80
25#define OFFSET_amd64_R9 88
26#define OFFSET_amd64_R10 96
27#define OFFSET_amd64_R11 104
28#define OFFSET_amd64_R12 112
29#define OFFSET_amd64_R13 120
30#define OFFSET_amd64_R14 128
31#define OFFSET_amd64_R15 136
32#define OFFSET_amd64_RIP 184
33#define OFFSET_ppc32_GPR0 16
34#define OFFSET_ppc32_GPR1 20
35#define OFFSET_ppc32_GPR2 24
36#define OFFSET_ppc32_GPR3 28
37#define OFFSET_ppc32_GPR4 32
38#define OFFSET_ppc32_GPR5 36
39#define OFFSET_ppc32_GPR6 40
40#define OFFSET_ppc32_GPR7 44
41#define OFFSET_ppc32_GPR8 48
42#define OFFSET_ppc32_GPR9 52
43#define OFFSET_ppc32_GPR10 56
44#define OFFSET_ppc32_CIA 1168
Elliott Hughesed398002017-06-21 14:41:24 -070045#define OFFSET_ppc32_CR0_0 1187
Ben Cheng663860b2013-01-31 15:38:14 -080046#define OFFSET_ppc64_GPR0 16
47#define OFFSET_ppc64_GPR1 24
48#define OFFSET_ppc64_GPR2 32
49#define OFFSET_ppc64_GPR3 40
50#define OFFSET_ppc64_GPR4 48
51#define OFFSET_ppc64_GPR5 56
52#define OFFSET_ppc64_GPR6 64
53#define OFFSET_ppc64_GPR7 72
54#define OFFSET_ppc64_GPR8 80
55#define OFFSET_ppc64_GPR9 88
56#define OFFSET_ppc64_GPR10 96
57#define OFFSET_ppc64_CIA 1296
Elliott Hughesed398002017-06-21 14:41:24 -070058#define OFFSET_ppc64_CR0_0 1327
Ben Cheng663860b2013-01-31 15:38:14 -080059#define OFFSET_arm_R0 8
60#define OFFSET_arm_R1 12
61#define OFFSET_arm_R2 16
62#define OFFSET_arm_R3 20
63#define OFFSET_arm_R4 24
64#define OFFSET_arm_R5 28
65#define OFFSET_arm_R7 36
66#define OFFSET_arm_R13 60
67#define OFFSET_arm_R14 64
68#define OFFSET_arm_R15T 68
Dmitriy Ivanov436e89c2014-03-07 10:01:05 -080069#define OFFSET_arm64_X0 16
70#define OFFSET_arm64_X1 24
71#define OFFSET_arm64_X2 32
72#define OFFSET_arm64_X3 40
73#define OFFSET_arm64_X4 48
74#define OFFSET_arm64_X5 56
75#define OFFSET_arm64_X6 64
76#define OFFSET_arm64_X7 72
77#define OFFSET_arm64_X8 80
78#define OFFSET_arm64_XSP 264
79#define OFFSET_arm64_PC 272
Evgeniy Stepanovb32f5802011-12-20 11:21:56 +040080#define OFFSET_s390x_r2 208
81#define OFFSET_s390x_r3 216
82#define OFFSET_s390x_r4 224
83#define OFFSET_s390x_r5 232
84#define OFFSET_s390x_r6 240
85#define OFFSET_s390x_r7 248
86#define OFFSET_s390x_r15 312
87#define OFFSET_s390x_IA 336
88#define OFFSET_s390x_SYSNO 344
89#define OFFSET_s390x_IP_AT_SYSCALL 408
90#define OFFSET_s390x_fpc 328
Ben Cheng663860b2013-01-31 15:38:14 -080091#define OFFSET_s390x_CC_OP 352
92#define OFFSET_s390x_CC_DEP1 360
93#define OFFSET_s390x_CC_DEP2 368
94#define OFFSET_s390x_CC_NDEP 376
Elliott Hughesed398002017-06-21 14:41:24 -070095#define OFFSET_mips32_r0 8
96#define OFFSET_mips32_r1 12
97#define OFFSET_mips32_r2 16
98#define OFFSET_mips32_r3 20
99#define OFFSET_mips32_r4 24
100#define OFFSET_mips32_r5 28
101#define OFFSET_mips32_r6 32
102#define OFFSET_mips32_r7 36
103#define OFFSET_mips32_r8 40
104#define OFFSET_mips32_r9 44
105#define OFFSET_mips32_r10 48
106#define OFFSET_mips32_r11 52
107#define OFFSET_mips32_r12 56
108#define OFFSET_mips32_r13 60
109#define OFFSET_mips32_r14 64
110#define OFFSET_mips32_r15 68
111#define OFFSET_mips32_r15 68
112#define OFFSET_mips32_r17 76
113#define OFFSET_mips32_r18 80
114#define OFFSET_mips32_r19 84
115#define OFFSET_mips32_r20 88
116#define OFFSET_mips32_r21 92
117#define OFFSET_mips32_r22 96
118#define OFFSET_mips32_r23 100
119#define OFFSET_mips32_r24 104
120#define OFFSET_mips32_r25 108
121#define OFFSET_mips32_r26 112
122#define OFFSET_mips32_r27 116
123#define OFFSET_mips32_r28 120
124#define OFFSET_mips32_r29 124
125#define OFFSET_mips32_r30 128
126#define OFFSET_mips32_r31 132
127#define OFFSET_mips32_PC 136
128#define OFFSET_mips32_HI 140
129#define OFFSET_mips32_LO 144
130#define OFFSET_mips64_r0 16
131#define OFFSET_mips64_r1 24
132#define OFFSET_mips64_r2 32
133#define OFFSET_mips64_r3 40
134#define OFFSET_mips64_r4 48
135#define OFFSET_mips64_r5 56
136#define OFFSET_mips64_r6 64
137#define OFFSET_mips64_r7 72
138#define OFFSET_mips64_r8 80
139#define OFFSET_mips64_r9 88
140#define OFFSET_mips64_r10 96
141#define OFFSET_mips64_r11 104
142#define OFFSET_mips64_r12 112
143#define OFFSET_mips64_r13 120
144#define OFFSET_mips64_r14 128
145#define OFFSET_mips64_r15 136
146#define OFFSET_mips64_r15 136
147#define OFFSET_mips64_r17 152
148#define OFFSET_mips64_r18 160
149#define OFFSET_mips64_r19 168
150#define OFFSET_mips64_r20 176
151#define OFFSET_mips64_r21 184
152#define OFFSET_mips64_r22 192
153#define OFFSET_mips64_r23 200
154#define OFFSET_mips64_r24 208
155#define OFFSET_mips64_r25 216
156#define OFFSET_mips64_r26 224
157#define OFFSET_mips64_r27 232
158#define OFFSET_mips64_r28 240
159#define OFFSET_mips64_r29 248
160#define OFFSET_mips64_r30 256
161#define OFFSET_mips64_r31 264
162#define OFFSET_mips64_PC 272
163#define OFFSET_mips64_HI 280
164#define OFFSET_mips64_LO 288