blob: 02c4020ebf515c7fc52abd6593673aeddb0e338b [file] [log] [blame]
ceriondd56a482005-11-29 13:48:52 +00001
2/*---------------------------------------------------------------*/
sewardj752f9062010-05-03 21:38:49 +00003/*--- begin libvex_guest_ppc64.h ---*/
ceriondd56a482005-11-29 13:48:52 +00004/*---------------------------------------------------------------*/
5
6/*
sewardj752f9062010-05-03 21:38:49 +00007 This file is part of Valgrind, a dynamic binary instrumentation
8 framework.
ceriondd56a482005-11-29 13:48:52 +00009
Elliott Hughesed398002017-06-21 14:41:24 -070010 Copyright (C) 2004-2017 OpenWorks LLP
sewardj752f9062010-05-03 21:38:49 +000011 info@open-works.net
ceriondd56a482005-11-29 13:48:52 +000012
sewardj752f9062010-05-03 21:38:49 +000013 This program is free software; you can redistribute it and/or
14 modify it under the terms of the GNU General Public License as
15 published by the Free Software Foundation; either version 2 of the
16 License, or (at your option) any later version.
ceriondd56a482005-11-29 13:48:52 +000017
sewardj752f9062010-05-03 21:38:49 +000018 This program is distributed in the hope that it will be useful, but
19 WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the Free Software
25 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
ceriondd56a482005-11-29 13:48:52 +000026 02110-1301, USA.
27
sewardj752f9062010-05-03 21:38:49 +000028 The GNU General Public License is contained in the file COPYING.
ceriondd56a482005-11-29 13:48:52 +000029
30 Neither the names of the U.S. Department of Energy nor the
31 University of California nor the names of its contributors may be
32 used to endorse or promote products derived from this software
33 without prior written permission.
34*/
35
36#ifndef __LIBVEX_PUB_GUEST_PPC64_H
37#define __LIBVEX_PUB_GUEST_PPC64_H
38
39#include "libvex_basictypes.h"
ceriondd56a482005-11-29 13:48:52 +000040
41/*
42 volatile == caller-saved (not preserved across function calls)
43non-volatile == callee-saved (preserved across function calls)
44
45r0 Volatile register used in function prologs
46r1 Stack frame pointer
47r2 TOC pointer
48r3 Volatile parameter and return value register
49r4-r10 Volatile registers used for function parameters
50r11 Volatile register used in calls by pointer and as an
51 environment pointer for languages which require one
52r12 Volatile register used for exception handling and glink code
53r13 Reserved for use as system thread ID
54r14-r31 Nonvolatile registers used for local variables
55
56f0 Volatile scratch register
57f1-f4 Volatile floating point parameter and return value registers
58f5-f13 Volatile floating point parameter registers
59f14-f31 Nonvolatile registers
60
61LR Link register (volatile)
62CTR Loop counter register (volatile)
63XER Fixed point exception register (volatile)
64FPSCR Floating point status and control register (volatile)
65
66CR0-CR1 Volatile condition code register fields
67CR2-CR4 Nonvolatile condition code register fields
68CR5-CR7 Volatile condition code register fields
69
70On processors with the VMX feature.
71
72v0-v1 Volatile scratch registers
73v2-v13 Volatile vector parameters registers
74v14-v19 Volatile scratch registers
75v20-v31 Non-volatile registers
76vrsave Non-volatile 32-bit register
77*/
78
79
80/*---------------------------------------------------------------*/
81/*--- Vex's representation of the PPC64 CPU state ---*/
82/*---------------------------------------------------------------*/
83
sewardj5ff11dd2006-01-20 14:19:25 +000084#define VEX_GUEST_PPC64_REDIR_STACK_SIZE (16/*entries*/ * 2/*words per entry*/)
sewardjbe482ae2006-01-17 01:42:56 +000085
ceriondd56a482005-11-29 13:48:52 +000086typedef
87 struct {
sewardj3dee8492012-04-20 00:13:28 +000088 /* Event check fail addr, counter, and padding to make GPR0 16
89 aligned. */
90 /* 0 */ ULong host_EvC_FAILADDR;
91 /* 8 */ UInt host_EvC_COUNTER;
92 /* 12 */ UInt pad0;
93 /* Add 16 to all of the offsets below .. */
ceriondd56a482005-11-29 13:48:52 +000094 /* General Purpose Registers */
95 /* 0 */ ULong guest_GPR0;
96 /* 8 */ ULong guest_GPR1;
97 /* 16 */ ULong guest_GPR2;
98 /* 24 */ ULong guest_GPR3;
99 /* 32 */ ULong guest_GPR4;
100 /* 40 */ ULong guest_GPR5;
101 /* 48 */ ULong guest_GPR6;
102 /* 56 */ ULong guest_GPR7;
103 /* 64 */ ULong guest_GPR8;
104 /* 72 */ ULong guest_GPR9;
105 /* 80 */ ULong guest_GPR10;
106 /* 88 */ ULong guest_GPR11;
107 /* 96 */ ULong guest_GPR12;
108 /* 104 */ ULong guest_GPR13;
109 /* 112 */ ULong guest_GPR14;
110 /* 120 */ ULong guest_GPR15;
111 /* 128 */ ULong guest_GPR16;
112 /* 136 */ ULong guest_GPR17;
113 /* 144 */ ULong guest_GPR18;
114 /* 152 */ ULong guest_GPR19;
115 /* 160 */ ULong guest_GPR20;
116 /* 168 */ ULong guest_GPR21;
117 /* 176 */ ULong guest_GPR22;
118 /* 184 */ ULong guest_GPR23;
119 /* 192 */ ULong guest_GPR24;
120 /* 200 */ ULong guest_GPR25;
121 /* 208 */ ULong guest_GPR26;
122 /* 216 */ ULong guest_GPR27;
123 /* 224 */ ULong guest_GPR28;
124 /* 232 */ ULong guest_GPR29;
125 /* 240 */ ULong guest_GPR30;
126 /* 248 */ ULong guest_GPR31;
127
sewardj66d5ef22011-04-15 11:55:00 +0000128 // Vector Registers, Floating Point Registers, and VSX Registers
129 // With ISA 2.06, the "Vector-Scalar Floating-point" category
130 // provides facilities to support vector and scalar binary floating-
131 // point operations. A unified register file is an integral part
132 // of this new facility, combining floating point and vector registers
133 // using a 64x128-bit vector. These are referred to as VSR[0..63].
134 // The floating point registers are now mapped into double word element 0
135 // of VSR[0..31]. The 32x128-bit vector registers defined by the "Vector
136 // Facility [Category: Vector]" are now mapped to VSR[32..63].
ceriondd56a482005-11-29 13:48:52 +0000137
sewardj478646f2008-05-01 20:13:04 +0000138 // IMPORTANT: the user of libvex must place the guest state so as
sewardj66d5ef22011-04-15 11:55:00 +0000139 // to ensure that guest_VSR{0..63}, and any shadows thereof, are
sewardj478646f2008-05-01 20:13:04 +0000140 // 16-aligned.
ceriondd56a482005-11-29 13:48:52 +0000141
sewardj66d5ef22011-04-15 11:55:00 +0000142 /* 256 */ U128 guest_VSR0;
143 /* 272 */ U128 guest_VSR1;
144 /* 288 */ U128 guest_VSR2;
145 /* 304 */ U128 guest_VSR3;
146 /* 320 */ U128 guest_VSR4;
147 /* 336 */ U128 guest_VSR5;
148 /* 352 */ U128 guest_VSR6;
149 /* 368 */ U128 guest_VSR7;
150 /* 384 */ U128 guest_VSR8;
151 /* 400 */ U128 guest_VSR9;
152 /* 416 */ U128 guest_VSR10;
153 /* 432 */ U128 guest_VSR11;
154 /* 448 */ U128 guest_VSR12;
155 /* 464 */ U128 guest_VSR13;
156 /* 480 */ U128 guest_VSR14;
157 /* 496 */ U128 guest_VSR15;
158 /* 512 */ U128 guest_VSR16;
159 /* 528 */ U128 guest_VSR17;
160 /* 544 */ U128 guest_VSR18;
161 /* 560 */ U128 guest_VSR19;
162 /* 576 */ U128 guest_VSR20;
163 /* 592 */ U128 guest_VSR21;
164 /* 608 */ U128 guest_VSR22;
165 /* 624 */ U128 guest_VSR23;
166 /* 640 */ U128 guest_VSR24;
167 /* 656 */ U128 guest_VSR25;
168 /* 672 */ U128 guest_VSR26;
169 /* 688 */ U128 guest_VSR27;
170 /* 704 */ U128 guest_VSR28;
171 /* 720 */ U128 guest_VSR29;
172 /* 736 */ U128 guest_VSR30;
173 /* 752 */ U128 guest_VSR31;
174 /* 768 */ U128 guest_VSR32;
175 /* 784 */ U128 guest_VSR33;
176 /* 800 */ U128 guest_VSR34;
177 /* 816 */ U128 guest_VSR35;
178 /* 832 */ U128 guest_VSR36;
179 /* 848 */ U128 guest_VSR37;
180 /* 864 */ U128 guest_VSR38;
181 /* 880 */ U128 guest_VSR39;
182 /* 896 */ U128 guest_VSR40;
183 /* 912 */ U128 guest_VSR41;
184 /* 928 */ U128 guest_VSR42;
185 /* 944 */ U128 guest_VSR43;
186 /* 960 */ U128 guest_VSR44;
187 /* 976 */ U128 guest_VSR45;
188 /* 992 */ U128 guest_VSR46;
189 /* 1008 */ U128 guest_VSR47;
190 /* 1024 */ U128 guest_VSR48;
191 /* 1040 */ U128 guest_VSR49;
192 /* 1056 */ U128 guest_VSR50;
193 /* 1072 */ U128 guest_VSR51;
194 /* 1088 */ U128 guest_VSR52;
195 /* 1104 */ U128 guest_VSR53;
196 /* 1120 */ U128 guest_VSR54;
197 /* 1136 */ U128 guest_VSR55;
198 /* 1152 */ U128 guest_VSR56;
199 /* 1168 */ U128 guest_VSR57;
200 /* 1184 */ U128 guest_VSR58;
201 /* 1200 */ U128 guest_VSR59;
202 /* 1216 */ U128 guest_VSR60;
203 /* 1232 */ U128 guest_VSR61;
204 /* 1248 */ U128 guest_VSR62;
205 /* 1264 */ U128 guest_VSR63;
206
207 /* 1280 */ ULong guest_CIA; // IP (no arch visible register)
208 /* 1288 */ ULong guest_LR; // Link Register
209 /* 1296 */ ULong guest_CTR; // Count Register
ceriondd56a482005-11-29 13:48:52 +0000210
211 /* XER pieces */
sewardj66d5ef22011-04-15 11:55:00 +0000212 /* 1304 */ UChar guest_XER_SO; /* in lsb */
213 /* 1305 */ UChar guest_XER_OV; /* in lsb */
Elliott Hughesed398002017-06-21 14:41:24 -0700214 /* 1306 */ UChar guest_XER_OV32; /* in lsb */
215 /* 1307 */ UChar guest_XER_CA; /* in lsb */
216 /* 1308 */ UChar guest_XER_CA32; /* in lsb */
217 /* 1309 */ UChar guest_XER_BC; /* all bits */
ceriondd56a482005-11-29 13:48:52 +0000218
219 /* CR pieces */
Elliott Hughesed398002017-06-21 14:41:24 -0700220 /* 1310 */ UChar guest_CR0_321; /* in [3:1] */
221 /* 1311 */ UChar guest_CR0_0; /* in lsb */
222 /* 1312 */ UChar guest_CR1_321; /* in [3:1] */
223 /* 1313 */ UChar guest_CR1_0; /* in lsb */
224 /* 1314 */ UChar guest_CR2_321; /* in [3:1] */
225 /* 1315 */ UChar guest_CR2_0; /* in lsb */
226 /* 1316 */ UChar guest_CR3_321; /* in [3:1] */
227 /* 1317 */ UChar guest_CR3_0; /* in lsb */
228 /* 1318 */ UChar guest_CR4_321; /* in [3:1] */
229 /* 1319 */ UChar guest_CR4_0; /* in lsb */
230 /* 1320 */ UChar guest_CR5_321; /* in [3:1] */
231 /* 1321 */ UChar guest_CR5_0; /* in lsb */
232 /* 1322 */ UChar guest_CR6_321; /* in [3:1] */
233 /* 1323 */ UChar guest_CR6_0; /* in lsb */
234 /* 1324 */ UChar guest_CR7_321; /* in [3:1] */
235 /* 1325 */ UChar guest_CR7_0; /* in lsb */
ceriondd56a482005-11-29 13:48:52 +0000236
sewardjc6bbd472012-04-02 10:20:48 +0000237 /* FP Status and Control Register fields. Only rounding mode fields
Elliott Hughesa0664b92017-04-18 17:46:52 -0700238 * and Floating-point Condition Code (FPCC) fields are supported.
239 */
Elliott Hughesed398002017-06-21 14:41:24 -0700240 /* 1326 */ UChar guest_FPROUND; // Binary Floating Point Rounding Mode
241 /* 1327 */ UChar guest_DFPROUND; // Decimal Floating Point Rounding Mode
242 /* 1328 */ UChar guest_C_FPCC; // Floating-point Condition Code
Elliott Hughesa0664b92017-04-18 17:46:52 -0700243 // and Floating-point Condition Code
244
Elliott Hughesed398002017-06-21 14:41:24 -0700245 /* 1329 */ UChar pad2;
246 /* 1330 */ UChar pad3;
247 /* 1331 */ UChar pad4;
ceriondd56a482005-11-29 13:48:52 +0000248
249 /* Vector Save/Restore Register */
Elliott Hughesed398002017-06-21 14:41:24 -0700250 /* 1332 */ UInt guest_VRSAVE;
ceriondd56a482005-11-29 13:48:52 +0000251
252 /* Vector Status and Control Register */
Elliott Hughesed398002017-06-21 14:41:24 -0700253 /* 1336 */ UInt guest_VSCR;
ceriondd56a482005-11-29 13:48:52 +0000254
florian6ef84be2012-08-26 03:20:07 +0000255 /* Emulation notes */
Elliott Hughesed398002017-06-21 14:41:24 -0700256 /* 1340 */ UInt guest_EMNOTE;
ceriondd56a482005-11-29 13:48:52 +0000257
cerion7a3e39c2005-12-06 19:11:02 +0000258 /* gcc adds 4 bytes padding here: pre-empt it. */
Elliott Hughesed398002017-06-21 14:41:24 -0700259 /* 1344 */ UInt padding;
cerion7a3e39c2005-12-06 19:11:02 +0000260
ceriondd56a482005-11-29 13:48:52 +0000261 /* For icbi: record start and length of area to invalidate */
Elliott Hughesed398002017-06-21 14:41:24 -0700262 /* 1348 */ ULong guest_CMSTART;
263 /* 1356 */ ULong guest_CMLEN;
ceriondd56a482005-11-29 13:48:52 +0000264
sewardjce02aa72006-01-12 12:27:58 +0000265 /* Used to record the unredirected guest address at the start of
266 a translation whose start has been redirected. By reading
267 this pseudo-register shortly afterwards, the translation can
268 find out what the corresponding no-redirection address was.
269 Note, this is only set for wrap-style redirects, not for
270 replace-style ones. */
Elliott Hughesed398002017-06-21 14:41:24 -0700271 /* 1364 */ ULong guest_NRADDR;
272 /* 1372 */ ULong guest_NRADDR_GPR2;
sewardjce02aa72006-01-12 12:27:58 +0000273
sewardjbe482ae2006-01-17 01:42:56 +0000274 /* A grows-upwards stack for hidden saves/restores of LR and R2
275 needed for function interception and wrapping on ppc64-linux.
276 A horrible hack. REDIR_SP points to the highest live entry,
277 and so starts at -1. */
Elliott Hughesed398002017-06-21 14:41:24 -0700278 /* 1380 */ ULong guest_REDIR_SP;
279 /* 1388 */ ULong guest_REDIR_STACK[VEX_GUEST_PPC64_REDIR_STACK_SIZE];
sewardjbe482ae2006-01-17 01:42:56 +0000280
florian23223602015-01-08 20:45:42 +0000281 /* Needed for Darwin: CIA at the last SC insn. Used when backing up
sewardjaca070a2006-10-17 00:28:22 +0000282 to restart a syscall that has been interrupted by a signal. */
Elliott Hughesed398002017-06-21 14:41:24 -0700283 /* 1646 */ ULong guest_IP_AT_SYSCALL;
sewardjaca070a2006-10-17 00:28:22 +0000284
285 /* SPRG3, which AIUI is readonly in user space. Needed for
286 threading on AIX. */
Elliott Hughesed398002017-06-21 14:41:24 -0700287 /* 1654 */ ULong guest_SPRG3_RO;
sewardjaca070a2006-10-17 00:28:22 +0000288
Elliott Hughesed398002017-06-21 14:41:24 -0700289 /* 1662 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
290 /* 1670 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
291 /* 1678 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
292 /* 1686 */ ULong guest_PPR; // Program Priority register
293 /* 1694 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
294 /* 1698 */ UInt guest_PSPB; // Problem State Priority Boost register
carll486db122015-04-22 16:15:41 +0000295
296 /* Padding to make it have an 16-aligned size */
Elliott Hughesed398002017-06-21 14:41:24 -0700297 /* 1698 */ UInt padding1;
298 /* 1702 UInt padding2; */
299 /* 1706 UInt padding3; */
carll8943d022013-10-02 16:25:57 +0000300
ceriondd56a482005-11-29 13:48:52 +0000301 }
302 VexGuestPPC64State;
303
304
305/*---------------------------------------------------------------*/
306/*--- Utility functions for PPC64 guest stuff. ---*/
307/*---------------------------------------------------------------*/
308
309/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT */
310
311/* Initialise all guest PPC64 state. */
312extern
313void LibVEX_GuestPPC64_initialise ( /*OUT*/VexGuestPPC64State* vex_state );
314
315
316/* Write the given native %CR value to the supplied VexGuestPPC64State
317 structure. Note, %CR is 32-bits even for ppc64. */
318extern
319void LibVEX_GuestPPC64_put_CR ( UInt cr_native,
320 /*OUT*/VexGuestPPC64State* vex_state );
321
322/* Extract from the supplied VexGuestPPC64State structure the
323 corresponding native %CR value. Note, %CR is 32-bits even for
324 ppc64. */
325extern
florianefa834a2012-11-24 21:07:14 +0000326UInt LibVEX_GuestPPC64_get_CR ( /*IN*/const VexGuestPPC64State* vex_state );
ceriondd56a482005-11-29 13:48:52 +0000327
328
329/* Write the given native %XER value to the supplied
330 VexGuestPPC64State structure. Note, %XER is 32-bits even for
331 ppc64. */
332extern
333void LibVEX_GuestPPC64_put_XER ( UInt xer_native,
334 /*OUT*/VexGuestPPC64State* vex_state );
335
336/* Extract from the supplied VexGuestPPC64State structure the
337 corresponding native %XER value. Note, %CR is 32-bits even for
338 ppc64. */
339extern
florianefa834a2012-11-24 21:07:14 +0000340UInt LibVEX_GuestPPC64_get_XER ( /*IN*/const VexGuestPPC64State* vex_state );
ceriondd56a482005-11-29 13:48:52 +0000341
342#endif /* ndef __LIBVEX_PUB_GUEST_PPC64_H */
343
344
345/*---------------------------------------------------------------*/
346/*--- libvex_guest_ppc64.h ---*/
347/*---------------------------------------------------------------*/