sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 3 | /*--- begin host_x86_defs.h ---*/ |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 4 | /*---------------------------------------------------------------*/ |
| 5 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 6 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | |
sewardj | 25e5473 | 2012-08-05 15:36:51 +0000 | [diff] [blame] | 10 | Copyright (C) 2004-2012 OpenWorks LLP |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 11 | info@open-works.net |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 12 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 17 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 26 | 02110-1301, USA. |
| 27 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 28 | The GNU General Public License is contained in the file COPYING. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 29 | |
| 30 | Neither the names of the U.S. Department of Energy nor the |
| 31 | University of California nor the names of its contributors may be |
| 32 | used to endorse or promote products derived from this software |
| 33 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 34 | */ |
| 35 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 36 | #ifndef __VEX_HOST_X86_DEFS_H |
| 37 | #define __VEX_HOST_X86_DEFS_H |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 38 | |
florian | 58a637b | 2012-09-30 20:30:17 +0000 | [diff] [blame] | 39 | #include "libvex_basictypes.h" |
| 40 | #include "libvex.h" // VexArch |
| 41 | #include "host_generic_regs.h" // HReg |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 42 | |
| 43 | /* --------- Registers. --------- */ |
| 44 | |
| 45 | /* The usual HReg abstraction. There are 8 real int regs, |
sewardj | c0250e4 | 2005-02-01 20:27:57 +0000 | [diff] [blame] | 46 | 6 real float regs, and 8 real vector regs. |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 47 | */ |
| 48 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 49 | extern void ppHRegX86 ( HReg ); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 50 | |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 51 | extern HReg hregX86_EAX ( void ); |
sewardj | 2cd80dc | 2004-07-02 15:20:40 +0000 | [diff] [blame] | 52 | extern HReg hregX86_EBX ( void ); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 53 | extern HReg hregX86_ECX ( void ); |
sewardj | 2cd80dc | 2004-07-02 15:20:40 +0000 | [diff] [blame] | 54 | extern HReg hregX86_EDX ( void ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 55 | extern HReg hregX86_ESP ( void ); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 56 | extern HReg hregX86_EBP ( void ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 57 | extern HReg hregX86_ESI ( void ); |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 58 | extern HReg hregX86_EDI ( void ); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 59 | |
sewardj | 70dff0c | 2004-11-30 13:37:21 +0000 | [diff] [blame] | 60 | extern HReg hregX86_FAKE0 ( void ); |
| 61 | extern HReg hregX86_FAKE1 ( void ); |
| 62 | extern HReg hregX86_FAKE2 ( void ); |
| 63 | extern HReg hregX86_FAKE3 ( void ); |
| 64 | extern HReg hregX86_FAKE4 ( void ); |
| 65 | extern HReg hregX86_FAKE5 ( void ); |
| 66 | |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 67 | extern HReg hregX86_XMM0 ( void ); |
| 68 | extern HReg hregX86_XMM1 ( void ); |
| 69 | extern HReg hregX86_XMM2 ( void ); |
| 70 | extern HReg hregX86_XMM3 ( void ); |
| 71 | extern HReg hregX86_XMM4 ( void ); |
| 72 | extern HReg hregX86_XMM5 ( void ); |
| 73 | extern HReg hregX86_XMM6 ( void ); |
| 74 | extern HReg hregX86_XMM7 ( void ); |
| 75 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 76 | |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 77 | /* --------- Condition codes, Intel encoding. --------- */ |
| 78 | |
| 79 | typedef |
| 80 | enum { |
| 81 | Xcc_O = 0, /* overflow */ |
| 82 | Xcc_NO = 1, /* no overflow */ |
| 83 | |
| 84 | Xcc_B = 2, /* below */ |
| 85 | Xcc_NB = 3, /* not below */ |
| 86 | |
| 87 | Xcc_Z = 4, /* zero */ |
| 88 | Xcc_NZ = 5, /* not zero */ |
| 89 | |
| 90 | Xcc_BE = 6, /* below or equal */ |
| 91 | Xcc_NBE = 7, /* not below or equal */ |
| 92 | |
| 93 | Xcc_S = 8, /* negative */ |
| 94 | Xcc_NS = 9, /* not negative */ |
| 95 | |
| 96 | Xcc_P = 10, /* parity even */ |
| 97 | Xcc_NP = 11, /* not parity even */ |
| 98 | |
| 99 | Xcc_L = 12, /* jump less */ |
| 100 | Xcc_NL = 13, /* not less */ |
| 101 | |
| 102 | Xcc_LE = 14, /* less or equal */ |
| 103 | Xcc_NLE = 15, /* not less or equal */ |
| 104 | |
| 105 | Xcc_ALWAYS = 16 /* the usual hack */ |
| 106 | } |
| 107 | X86CondCode; |
| 108 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 109 | extern const HChar* showX86CondCode ( X86CondCode ); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 110 | |
| 111 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 112 | /* --------- Memory address expressions (amodes). --------- */ |
| 113 | |
| 114 | typedef |
| 115 | enum { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 116 | Xam_IR, /* Immediate + Reg */ |
| 117 | Xam_IRRS /* Immediate + Reg1 + (Reg2 << Shift) */ |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 118 | } |
| 119 | X86AModeTag; |
| 120 | |
| 121 | typedef |
| 122 | struct { |
| 123 | X86AModeTag tag; |
| 124 | union { |
| 125 | struct { |
| 126 | UInt imm; |
| 127 | HReg reg; |
| 128 | } IR; |
| 129 | struct { |
| 130 | UInt imm; |
| 131 | HReg base; |
| 132 | HReg index; |
| 133 | Int shift; /* 0, 1, 2 or 3 only */ |
| 134 | } IRRS; |
| 135 | } Xam; |
| 136 | } |
| 137 | X86AMode; |
| 138 | |
| 139 | extern X86AMode* X86AMode_IR ( UInt, HReg ); |
| 140 | extern X86AMode* X86AMode_IRRS ( UInt, HReg, HReg, Int ); |
| 141 | |
sewardj | 218e29f | 2004-11-07 18:45:15 +0000 | [diff] [blame] | 142 | extern X86AMode* dopyX86AMode ( X86AMode* ); |
| 143 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 144 | extern void ppX86AMode ( X86AMode* ); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 145 | |
| 146 | |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 147 | /* --------- Operand, which can be reg, immediate or memory. --------- */ |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 148 | |
| 149 | typedef |
| 150 | enum { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 151 | Xrmi_Imm, |
| 152 | Xrmi_Reg, |
| 153 | Xrmi_Mem |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 154 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 155 | X86RMITag; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 156 | |
| 157 | typedef |
| 158 | struct { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 159 | X86RMITag tag; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 160 | union { |
| 161 | struct { |
| 162 | UInt imm32; |
| 163 | } Imm; |
| 164 | struct { |
| 165 | HReg reg; |
| 166 | } Reg; |
| 167 | struct { |
| 168 | X86AMode* am; |
| 169 | } Mem; |
| 170 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 171 | Xrmi; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 172 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 173 | X86RMI; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 174 | |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 175 | extern X86RMI* X86RMI_Imm ( UInt ); |
| 176 | extern X86RMI* X86RMI_Reg ( HReg ); |
| 177 | extern X86RMI* X86RMI_Mem ( X86AMode* ); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 178 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 179 | extern void ppX86RMI ( X86RMI* ); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 180 | |
| 181 | |
| 182 | /* --------- Operand, which can be reg or immediate only. --------- */ |
| 183 | |
| 184 | typedef |
| 185 | enum { |
| 186 | Xri_Imm, |
| 187 | Xri_Reg |
| 188 | } |
| 189 | X86RITag; |
| 190 | |
| 191 | typedef |
| 192 | struct { |
| 193 | X86RITag tag; |
| 194 | union { |
| 195 | struct { |
| 196 | UInt imm32; |
| 197 | } Imm; |
| 198 | struct { |
| 199 | HReg reg; |
| 200 | } Reg; |
| 201 | } |
| 202 | Xri; |
| 203 | } |
| 204 | X86RI; |
| 205 | |
| 206 | extern X86RI* X86RI_Imm ( UInt ); |
| 207 | extern X86RI* X86RI_Reg ( HReg ); |
| 208 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 209 | extern void ppX86RI ( X86RI* ); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 210 | |
| 211 | |
| 212 | /* --------- Operand, which can be reg or memory only. --------- */ |
| 213 | |
| 214 | typedef |
| 215 | enum { |
| 216 | Xrm_Reg, |
| 217 | Xrm_Mem |
| 218 | } |
| 219 | X86RMTag; |
| 220 | |
| 221 | typedef |
| 222 | struct { |
| 223 | X86RMTag tag; |
| 224 | union { |
| 225 | struct { |
| 226 | HReg reg; |
| 227 | } Reg; |
| 228 | struct { |
| 229 | X86AMode* am; |
| 230 | } Mem; |
| 231 | } |
| 232 | Xrm; |
| 233 | } |
| 234 | X86RM; |
| 235 | |
| 236 | extern X86RM* X86RM_Reg ( HReg ); |
| 237 | extern X86RM* X86RM_Mem ( X86AMode* ); |
| 238 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 239 | extern void ppX86RM ( X86RM* ); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 240 | |
| 241 | |
| 242 | /* --------- Instructions. --------- */ |
| 243 | |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 244 | /* --------- */ |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 245 | typedef |
| 246 | enum { |
sewardj | 358b7d4 | 2004-11-08 18:54:50 +0000 | [diff] [blame] | 247 | Xun_NEG, |
| 248 | Xun_NOT |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 249 | } |
| 250 | X86UnaryOp; |
| 251 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 252 | extern const HChar* showX86UnaryOp ( X86UnaryOp ); |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 253 | |
| 254 | |
| 255 | /* --------- */ |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 256 | typedef |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 257 | enum { |
| 258 | Xalu_INVALID, |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 259 | Xalu_MOV, |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 260 | Xalu_CMP, |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 261 | Xalu_ADD, Xalu_SUB, Xalu_ADC, Xalu_SBB, |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 262 | Xalu_AND, Xalu_OR, Xalu_XOR, |
| 263 | Xalu_MUL |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 264 | } |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 265 | X86AluOp; |
| 266 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 267 | extern const HChar* showX86AluOp ( X86AluOp ); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 268 | |
| 269 | |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 270 | /* --------- */ |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 271 | typedef |
| 272 | enum { |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 273 | Xsh_INVALID, |
sewardj | df53045 | 2005-02-02 03:10:01 +0000 | [diff] [blame] | 274 | Xsh_SHL, Xsh_SHR, Xsh_SAR |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 275 | } |
| 276 | X86ShiftOp; |
| 277 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 278 | extern const HChar* showX86ShiftOp ( X86ShiftOp ); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 279 | |
| 280 | |
| 281 | /* --------- */ |
| 282 | typedef |
| 283 | enum { |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 284 | Xfp_INVALID, |
| 285 | /* Binary */ |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 286 | Xfp_ADD, Xfp_SUB, Xfp_MUL, Xfp_DIV, |
sewardj | 442d0be | 2004-10-15 22:57:13 +0000 | [diff] [blame] | 287 | Xfp_SCALE, Xfp_ATAN, Xfp_YL2X, Xfp_YL2XP1, Xfp_PREM, Xfp_PREM1, |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 288 | /* Unary */ |
sewardj | 99016a7 | 2004-10-15 22:09:17 +0000 | [diff] [blame] | 289 | Xfp_SQRT, Xfp_ABS, Xfp_NEG, Xfp_MOV, Xfp_SIN, Xfp_COS, Xfp_TAN, |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 290 | Xfp_ROUND, Xfp_2XM1 |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 291 | } |
| 292 | X86FpOp; |
| 293 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 294 | extern const HChar* showX86FpOp ( X86FpOp ); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 295 | |
| 296 | |
| 297 | /* --------- */ |
| 298 | typedef |
| 299 | enum { |
| 300 | Xsse_INVALID, |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 301 | /* mov */ |
| 302 | Xsse_MOV, |
| 303 | /* Floating point binary */ |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 304 | Xsse_ADDF, Xsse_SUBF, Xsse_MULF, Xsse_DIVF, |
| 305 | Xsse_MAXF, Xsse_MINF, |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 306 | Xsse_CMPEQF, Xsse_CMPLTF, Xsse_CMPLEF, Xsse_CMPUNF, |
| 307 | /* Floating point unary */ |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 308 | Xsse_RCPF, Xsse_RSQRTF, Xsse_SQRTF, |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 309 | /* Bitwise */ |
| 310 | Xsse_AND, Xsse_OR, Xsse_XOR, Xsse_ANDN, |
| 311 | /* Integer binary */ |
| 312 | Xsse_ADD8, Xsse_ADD16, Xsse_ADD32, Xsse_ADD64, |
| 313 | Xsse_QADD8U, Xsse_QADD16U, |
| 314 | Xsse_QADD8S, Xsse_QADD16S, |
| 315 | Xsse_SUB8, Xsse_SUB16, Xsse_SUB32, Xsse_SUB64, |
| 316 | Xsse_QSUB8U, Xsse_QSUB16U, |
| 317 | Xsse_QSUB8S, Xsse_QSUB16S, |
| 318 | Xsse_MUL16, |
| 319 | Xsse_MULHI16U, |
| 320 | Xsse_MULHI16S, |
| 321 | Xsse_AVG8U, Xsse_AVG16U, |
| 322 | Xsse_MAX16S, |
| 323 | Xsse_MAX8U, |
| 324 | Xsse_MIN16S, |
| 325 | Xsse_MIN8U, |
| 326 | Xsse_CMPEQ8, Xsse_CMPEQ16, Xsse_CMPEQ32, |
| 327 | Xsse_CMPGT8S, Xsse_CMPGT16S, Xsse_CMPGT32S, |
| 328 | Xsse_SHL16, Xsse_SHL32, Xsse_SHL64, |
| 329 | Xsse_SHR16, Xsse_SHR32, Xsse_SHR64, |
| 330 | Xsse_SAR16, Xsse_SAR32, |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 331 | Xsse_PACKSSD, Xsse_PACKSSW, Xsse_PACKUSW, |
| 332 | Xsse_UNPCKHB, Xsse_UNPCKHW, Xsse_UNPCKHD, Xsse_UNPCKHQ, |
| 333 | Xsse_UNPCKLB, Xsse_UNPCKLW, Xsse_UNPCKLD, Xsse_UNPCKLQ |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 334 | } |
| 335 | X86SseOp; |
| 336 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 337 | extern const HChar* showX86SseOp ( X86SseOp ); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 338 | |
| 339 | |
| 340 | /* --------- */ |
| 341 | typedef |
| 342 | enum { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 343 | Xin_Alu32R, /* 32-bit mov/arith/logical, dst=REG */ |
| 344 | Xin_Alu32M, /* 32-bit mov/arith/logical, dst=MEM */ |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 345 | Xin_Sh32, /* 32-bit shift/rotate, dst=REG */ |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 346 | Xin_Test32, /* 32-bit test of REG or MEM against imm32 (AND, set |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 347 | flags, discard result) */ |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 348 | Xin_Unary32, /* 32-bit not and neg */ |
sewardj | 79e04f8 | 2007-03-31 14:30:12 +0000 | [diff] [blame] | 349 | Xin_Lea32, /* 32-bit compute EA into a reg */ |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 350 | Xin_MulL, /* 32 x 32 -> 64 multiply */ |
| 351 | Xin_Div, /* 64/32 -> (32,32) div and mod */ |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 352 | Xin_Sh3232, /* shldl or shrdl */ |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 353 | Xin_Push, /* push (32-bit?) value on stack */ |
| 354 | Xin_Call, /* call to address in register */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 355 | Xin_XDirect, /* direct transfer to GA */ |
| 356 | Xin_XIndir, /* indirect transfer to GA */ |
| 357 | Xin_XAssisted, /* assisted transfer to GA */ |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 358 | Xin_CMov32, /* conditional move */ |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 359 | Xin_LoadEX, /* mov{s,z}{b,w}l from mem to reg */ |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 360 | Xin_Store, /* store 16/8 bit value in memory */ |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 361 | Xin_Set32, /* convert condition code to 32-bit value */ |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 362 | Xin_Bsfr32, /* 32-bit bsf/bsr */ |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 363 | Xin_MFence, /* mem fence (not just sse2, but sse0 and 1 too) */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 364 | Xin_ACAS, /* 8/16/32-bit lock;cmpxchg */ |
| 365 | Xin_DACAS, /* lock;cmpxchg8b (doubleword ACAS, 2 x 32-bit only) */ |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 366 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 367 | Xin_FpUnary, /* FP fake unary op */ |
| 368 | Xin_FpBinary, /* FP fake binary op */ |
| 369 | Xin_FpLdSt, /* FP fake load/store */ |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 370 | Xin_FpLdStI, /* FP fake load/store, converting to/from Int */ |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 371 | Xin_Fp64to32, /* FP round IEEE754 double to IEEE754 single */ |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 372 | Xin_FpCMov, /* FP fake floating point conditional move */ |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 373 | Xin_FpLdCW, /* fldcw */ |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 374 | Xin_FpStSW_AX, /* fstsw %ax */ |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 375 | Xin_FpCmp, /* FP compare, generating a C320 value into int reg */ |
| 376 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 377 | Xin_SseConst, /* Generate restricted SSE literal */ |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 378 | Xin_SseLdSt, /* SSE load/store, no alignment constraints */ |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 379 | Xin_SseLdzLO, /* SSE load low 32/64 bits, zero remainder of reg */ |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 380 | Xin_Sse32Fx4, /* SSE binary, 32Fx4 */ |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 381 | Xin_Sse32FLo, /* SSE binary, 32F in lowest lane only */ |
| 382 | Xin_Sse64Fx2, /* SSE binary, 64Fx2 */ |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 383 | Xin_Sse64FLo, /* SSE binary, 64F in lowest lane only */ |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 384 | Xin_SseReRg, /* SSE binary general reg-reg, Re, Rg */ |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 385 | Xin_SseCMov, /* SSE conditional move */ |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 386 | Xin_SseShuf, /* SSE2 shuffle (pshufd) */ |
| 387 | Xin_EvCheck, /* Event check */ |
| 388 | Xin_ProfInc /* 64-bit profile counter increment */ |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 389 | } |
| 390 | X86InstrTag; |
| 391 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 392 | /* Destinations are on the RIGHT (second operand) */ |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 393 | |
| 394 | typedef |
| 395 | struct { |
| 396 | X86InstrTag tag; |
| 397 | union { |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 398 | struct { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 399 | X86AluOp op; |
| 400 | X86RMI* src; |
| 401 | HReg dst; |
| 402 | } Alu32R; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 403 | struct { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 404 | X86AluOp op; |
| 405 | X86RI* src; |
| 406 | X86AMode* dst; |
| 407 | } Alu32M; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 408 | struct { |
| 409 | X86ShiftOp op; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 410 | UInt src; /* shift amount, or 0 means %cl */ |
| 411 | HReg dst; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 412 | } Sh32; |
| 413 | struct { |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 414 | UInt imm32; |
| 415 | X86RM* dst; /* not written, only read */ |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 416 | } Test32; |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 417 | /* Not and Neg */ |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 418 | struct { |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 419 | X86UnaryOp op; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 420 | HReg dst; |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 421 | } Unary32; |
sewardj | 79e04f8 | 2007-03-31 14:30:12 +0000 | [diff] [blame] | 422 | /* 32-bit compute EA into a reg */ |
| 423 | struct { |
| 424 | X86AMode* am; |
| 425 | HReg dst; |
| 426 | } Lea32; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 427 | /* EDX:EAX = EAX *s/u r/m32 */ |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 428 | struct { |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 429 | Bool syned; |
| 430 | X86RM* src; |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 431 | } MulL; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 432 | /* x86 div/idiv instruction. Modifies EDX and EAX and reads src. */ |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 433 | struct { |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 434 | Bool syned; |
| 435 | X86RM* src; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 436 | } Div; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 437 | /* shld/shrd. op may only be Xsh_SHL or Xsh_SHR */ |
| 438 | struct { |
| 439 | X86ShiftOp op; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 440 | UInt amt; /* shift amount, or 0 means %cl */ |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 441 | HReg src; |
| 442 | HReg dst; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 443 | } Sh3232; |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 444 | struct { |
| 445 | X86RMI* src; |
| 446 | } Push; |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 447 | /* Pseudo-insn. Call target (an absolute address), on given |
| 448 | condition (which could be Xcc_ALWAYS). */ |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 449 | struct { |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 450 | X86CondCode cond; |
| 451 | Addr32 target; |
| 452 | Int regparms; /* 0 .. 3 */ |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 453 | } Call; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 454 | /* Update the guest EIP value, then exit requesting to chain |
| 455 | to it. May be conditional. Urr, use of Addr32 implicitly |
| 456 | assumes that wordsize(guest) == wordsize(host). */ |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 457 | struct { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 458 | Addr32 dstGA; /* next guest address */ |
| 459 | X86AMode* amEIP; /* amode in guest state for EIP */ |
| 460 | X86CondCode cond; /* can be Xcc_ALWAYS */ |
| 461 | Bool toFastEP; /* chain to the slow or fast point? */ |
| 462 | } XDirect; |
| 463 | /* Boring transfer to a guest address not known at JIT time. |
| 464 | Not chainable. May be conditional. */ |
| 465 | struct { |
| 466 | HReg dstGA; |
| 467 | X86AMode* amEIP; |
| 468 | X86CondCode cond; /* can be Xcc_ALWAYS */ |
| 469 | } XIndir; |
| 470 | /* Assisted transfer to a guest address, most general case. |
| 471 | Not chainable. May be conditional. */ |
| 472 | struct { |
| 473 | HReg dstGA; |
| 474 | X86AMode* amEIP; |
| 475 | X86CondCode cond; /* can be Xcc_ALWAYS */ |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 476 | IRJumpKind jk; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 477 | } XAssisted; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 478 | /* Mov src to dst on the given condition, which may not |
| 479 | be the bogus Xcc_ALWAYS. */ |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 480 | struct { |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 481 | X86CondCode cond; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 482 | X86RM* src; |
| 483 | HReg dst; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 484 | } CMov32; |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 485 | /* Sign/Zero extending loads. Dst size is always 32 bits. */ |
| 486 | struct { |
| 487 | UChar szSmall; |
| 488 | Bool syned; |
| 489 | X86AMode* src; |
| 490 | HReg dst; |
| 491 | } LoadEX; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 492 | /* 16/8 bit stores, which are troublesome (particularly |
| 493 | 8-bit) */ |
| 494 | struct { |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 495 | UChar sz; /* only 1 or 2 */ |
| 496 | HReg src; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 497 | X86AMode* dst; |
| 498 | } Store; |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 499 | /* Convert a x86 condition code to a 32-bit value (0 or 1). */ |
| 500 | struct { |
| 501 | X86CondCode cond; |
| 502 | HReg dst; |
| 503 | } Set32; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 504 | /* 32-bit bsf or bsr. */ |
| 505 | struct { |
| 506 | Bool isFwds; |
| 507 | HReg src; |
| 508 | HReg dst; |
| 509 | } Bsfr32; |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 510 | /* Mem fence (not just sse2, but sse0 and 1 too). In short, |
| 511 | an insn which flushes all preceding loads and stores as |
| 512 | much as possible before continuing. On SSE2 we emit a |
| 513 | real "mfence", on SSE1 "sfence ; lock addl $0,0(%esp)" and |
| 514 | on SSE0 "lock addl $0,0(%esp)". This insn therefore |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 515 | carries the host's hwcaps so the assembler knows what to |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 516 | emit. */ |
| 517 | struct { |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 518 | UInt hwcaps; |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 519 | } MFence; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 520 | /* "lock;cmpxchg": mem address in .addr, |
| 521 | expected value in %eax, new value in %ebx */ |
| 522 | struct { |
| 523 | X86AMode* addr; |
| 524 | UChar sz; /* 1, 2 or 4 */ |
| 525 | } ACAS; |
| 526 | /* "lock;cmpxchg8b": mem address in .addr, expected value in |
| 527 | %edx:%eax, new value in %ecx:%ebx */ |
| 528 | struct { |
| 529 | X86AMode* addr; |
| 530 | } DACAS; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 531 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 532 | /* X86 Floating point (fake 3-operand, "flat reg file" insns) */ |
| 533 | struct { |
| 534 | X86FpOp op; |
| 535 | HReg src; |
| 536 | HReg dst; |
| 537 | } FpUnary; |
| 538 | struct { |
| 539 | X86FpOp op; |
| 540 | HReg srcL; |
| 541 | HReg srcR; |
| 542 | HReg dst; |
| 543 | } FpBinary; |
| 544 | struct { |
| 545 | Bool isLoad; |
| 546 | UChar sz; /* only 4 (IEEE single) or 8 (IEEE double) */ |
| 547 | HReg reg; |
| 548 | X86AMode* addr; |
| 549 | } FpLdSt; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 550 | /* Move 64-bit float to/from memory, converting to/from |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 551 | signed int on the way. Note the conversions will observe |
| 552 | the host FPU rounding mode currently in force. */ |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 553 | struct { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 554 | Bool isLoad; |
| 555 | UChar sz; /* only 2, 4 or 8 */ |
| 556 | HReg reg; |
| 557 | X86AMode* addr; |
| 558 | } FpLdStI; |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 559 | /* By observing the current FPU rounding mode, round (etc) |
| 560 | src into dst given that dst should be interpreted as an |
| 561 | IEEE754 32-bit (float) type. */ |
| 562 | struct { |
| 563 | HReg src; |
| 564 | HReg dst; |
| 565 | } Fp64to32; |
sewardj | 33124f6 | 2004-08-30 17:54:18 +0000 | [diff] [blame] | 566 | /* Mov src to dst on the given condition, which may not |
| 567 | be the bogus Xcc_ALWAYS. */ |
| 568 | struct { |
| 569 | X86CondCode cond; |
| 570 | HReg src; |
| 571 | HReg dst; |
| 572 | } FpCMov; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 573 | /* Load the FPU's 16-bit control word (fldcw) */ |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 574 | struct { |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 575 | X86AMode* addr; |
| 576 | } |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 577 | FpLdCW; |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 578 | /* fstsw %ax */ |
| 579 | struct { |
| 580 | /* no fields */ |
| 581 | } |
| 582 | FpStSW_AX; |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 583 | /* Do a compare, generating the C320 bits into the dst. */ |
| 584 | struct { |
| 585 | HReg srcL; |
| 586 | HReg srcR; |
| 587 | HReg dst; |
| 588 | } FpCmp; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 589 | |
| 590 | /* Simplistic SSE[123] */ |
| 591 | struct { |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 592 | UShort con; |
| 593 | HReg dst; |
| 594 | } SseConst; |
| 595 | struct { |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 596 | Bool isLoad; |
| 597 | HReg reg; |
| 598 | X86AMode* addr; |
| 599 | } SseLdSt; |
| 600 | struct { |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 601 | UChar sz; /* 4 or 8 only */ |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 602 | HReg reg; |
| 603 | X86AMode* addr; |
| 604 | } SseLdzLO; |
| 605 | struct { |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 606 | X86SseOp op; |
| 607 | HReg src; |
| 608 | HReg dst; |
| 609 | } Sse32Fx4; |
| 610 | struct { |
| 611 | X86SseOp op; |
| 612 | HReg src; |
| 613 | HReg dst; |
| 614 | } Sse32FLo; |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 615 | struct { |
| 616 | X86SseOp op; |
| 617 | HReg src; |
| 618 | HReg dst; |
| 619 | } Sse64Fx2; |
| 620 | struct { |
| 621 | X86SseOp op; |
| 622 | HReg src; |
| 623 | HReg dst; |
| 624 | } Sse64FLo; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 625 | struct { |
| 626 | X86SseOp op; |
| 627 | HReg src; |
| 628 | HReg dst; |
| 629 | } SseReRg; |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 630 | /* Mov src to dst on the given condition, which may not |
| 631 | be the bogus Xcc_ALWAYS. */ |
| 632 | struct { |
| 633 | X86CondCode cond; |
| 634 | HReg src; |
| 635 | HReg dst; |
| 636 | } SseCMov; |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 637 | struct { |
| 638 | Int order; /* 0 <= order <= 0xFF */ |
| 639 | HReg src; |
| 640 | HReg dst; |
| 641 | } SseShuf; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 642 | struct { |
| 643 | X86AMode* amCounter; |
| 644 | X86AMode* amFailAddr; |
| 645 | } EvCheck; |
| 646 | struct { |
| 647 | /* No fields. The address of the counter to inc is |
| 648 | installed later, post-translation, by patching it in, |
| 649 | as it is not known at translation time. */ |
| 650 | } ProfInc; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 651 | |
sewardj | 33124f6 | 2004-08-30 17:54:18 +0000 | [diff] [blame] | 652 | } Xin; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 653 | } |
| 654 | X86Instr; |
| 655 | |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 656 | extern X86Instr* X86Instr_Alu32R ( X86AluOp, X86RMI*, HReg ); |
| 657 | extern X86Instr* X86Instr_Alu32M ( X86AluOp, X86RI*, X86AMode* ); |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 658 | extern X86Instr* X86Instr_Unary32 ( X86UnaryOp op, HReg dst ); |
sewardj | 79e04f8 | 2007-03-31 14:30:12 +0000 | [diff] [blame] | 659 | extern X86Instr* X86Instr_Lea32 ( X86AMode* am, HReg dst ); |
| 660 | |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 661 | extern X86Instr* X86Instr_Sh32 ( X86ShiftOp, UInt, HReg ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 662 | extern X86Instr* X86Instr_Test32 ( UInt imm32, X86RM* dst ); |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 663 | extern X86Instr* X86Instr_MulL ( Bool syned, X86RM* ); |
| 664 | extern X86Instr* X86Instr_Div ( Bool syned, X86RM* ); |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 665 | extern X86Instr* X86Instr_Sh3232 ( X86ShiftOp, UInt amt, HReg src, HReg dst ); |
| 666 | extern X86Instr* X86Instr_Push ( X86RMI* ); |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 667 | extern X86Instr* X86Instr_Call ( X86CondCode, Addr32, Int ); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 668 | extern X86Instr* X86Instr_XDirect ( Addr32 dstGA, X86AMode* amEIP, |
| 669 | X86CondCode cond, Bool toFastEP ); |
| 670 | extern X86Instr* X86Instr_XIndir ( HReg dstGA, X86AMode* amEIP, |
| 671 | X86CondCode cond ); |
| 672 | extern X86Instr* X86Instr_XAssisted ( HReg dstGA, X86AMode* amEIP, |
| 673 | X86CondCode cond, IRJumpKind jk ); |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 674 | extern X86Instr* X86Instr_CMov32 ( X86CondCode, X86RM* src, HReg dst ); |
| 675 | extern X86Instr* X86Instr_LoadEX ( UChar szSmall, Bool syned, |
| 676 | X86AMode* src, HReg dst ); |
| 677 | extern X86Instr* X86Instr_Store ( UChar sz, HReg src, X86AMode* dst ); |
| 678 | extern X86Instr* X86Instr_Set32 ( X86CondCode cond, HReg dst ); |
| 679 | extern X86Instr* X86Instr_Bsfr32 ( Bool isFwds, HReg src, HReg dst ); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 680 | extern X86Instr* X86Instr_MFence ( UInt hwcaps ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 681 | extern X86Instr* X86Instr_ACAS ( X86AMode* addr, UChar sz ); |
| 682 | extern X86Instr* X86Instr_DACAS ( X86AMode* addr ); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 683 | |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 684 | extern X86Instr* X86Instr_FpUnary ( X86FpOp op, HReg src, HReg dst ); |
| 685 | extern X86Instr* X86Instr_FpBinary ( X86FpOp op, HReg srcL, HReg srcR, HReg dst ); |
| 686 | extern X86Instr* X86Instr_FpLdSt ( Bool isLoad, UChar sz, HReg reg, X86AMode* ); |
| 687 | extern X86Instr* X86Instr_FpLdStI ( Bool isLoad, UChar sz, HReg reg, X86AMode* ); |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 688 | extern X86Instr* X86Instr_Fp64to32 ( HReg src, HReg dst ); |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 689 | extern X86Instr* X86Instr_FpCMov ( X86CondCode, HReg src, HReg dst ); |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 690 | extern X86Instr* X86Instr_FpLdCW ( X86AMode* ); |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 691 | extern X86Instr* X86Instr_FpStSW_AX ( void ); |
| 692 | extern X86Instr* X86Instr_FpCmp ( HReg srcL, HReg srcR, HReg dst ); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 693 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 694 | extern X86Instr* X86Instr_SseConst ( UShort con, HReg dst ); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 695 | extern X86Instr* X86Instr_SseLdSt ( Bool isLoad, HReg, X86AMode* ); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 696 | extern X86Instr* X86Instr_SseLdzLO ( Int sz, HReg, X86AMode* ); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 697 | extern X86Instr* X86Instr_Sse32Fx4 ( X86SseOp, HReg, HReg ); |
| 698 | extern X86Instr* X86Instr_Sse32FLo ( X86SseOp, HReg, HReg ); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 699 | extern X86Instr* X86Instr_Sse64Fx2 ( X86SseOp, HReg, HReg ); |
| 700 | extern X86Instr* X86Instr_Sse64FLo ( X86SseOp, HReg, HReg ); |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 701 | extern X86Instr* X86Instr_SseReRg ( X86SseOp, HReg, HReg ); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 702 | extern X86Instr* X86Instr_SseCMov ( X86CondCode, HReg src, HReg dst ); |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 703 | extern X86Instr* X86Instr_SseShuf ( Int order, HReg src, HReg dst ); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 704 | extern X86Instr* X86Instr_EvCheck ( X86AMode* amCounter, |
| 705 | X86AMode* amFailAddr ); |
| 706 | extern X86Instr* X86Instr_ProfInc ( void ); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 707 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 708 | |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 709 | extern void ppX86Instr ( X86Instr*, Bool ); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 710 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 711 | /* Some functions that insulate the register allocator from details |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 712 | of the underlying instruction set. */ |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 713 | extern void getRegUsage_X86Instr ( HRegUsage*, X86Instr*, Bool ); |
| 714 | extern void mapRegs_X86Instr ( HRegRemap*, X86Instr*, Bool ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 715 | extern Bool isMove_X86Instr ( X86Instr*, HReg*, HReg* ); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 716 | extern Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc, |
| 717 | UChar* buf, Int nbuf, X86Instr* i, |
| 718 | Bool mode64, |
| 719 | void* disp_cp_chain_me_to_slowEP, |
| 720 | void* disp_cp_chain_me_to_fastEP, |
| 721 | void* disp_cp_xindir, |
| 722 | void* disp_cp_xassisted ); |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 723 | |
| 724 | extern void genSpill_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, |
| 725 | HReg rreg, Int offset, Bool ); |
| 726 | extern void genReload_X86 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, |
| 727 | HReg rreg, Int offset, Bool ); |
| 728 | |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 729 | extern X86Instr* directReload_X86 ( X86Instr* i, |
| 730 | HReg vreg, Short spill_off ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 731 | extern void getAllocableRegs_X86 ( Int*, HReg** ); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 732 | extern HInstrArray* iselSB_X86 ( IRSB*, |
| 733 | VexArch, |
| 734 | VexArchInfo*, |
| 735 | VexAbiInfo*, |
| 736 | Int offs_Host_EvC_Counter, |
| 737 | Int offs_Host_EvC_FailAddr, |
| 738 | Bool chainingAllowed, |
| 739 | Bool addProfInc, |
| 740 | Addr64 max_ga ); |
| 741 | |
| 742 | /* How big is an event check? This is kind of a kludge because it |
| 743 | depends on the offsets of host_EvC_FAILADDR and host_EvC_COUNTER, |
| 744 | and so assumes that they are both <= 128, and so can use the short |
| 745 | offset encoding. This is all checked with assertions, so in the |
| 746 | worst case we will merely assert at startup. */ |
| 747 | extern Int evCheckSzB_X86 ( void ); |
| 748 | |
| 749 | /* Perform a chaining and unchaining of an XDirect jump. */ |
| 750 | extern VexInvalRange chainXDirect_X86 ( void* place_to_chain, |
| 751 | void* disp_cp_chain_me_EXPECTED, |
| 752 | void* place_to_jump_to ); |
| 753 | |
| 754 | extern VexInvalRange unchainXDirect_X86 ( void* place_to_unchain, |
| 755 | void* place_to_jump_to_EXPECTED, |
| 756 | void* disp_cp_chain_me ); |
| 757 | |
| 758 | /* Patch the counter location into an existing ProfInc point. */ |
| 759 | extern VexInvalRange patchProfInc_X86 ( void* place_to_patch, |
| 760 | ULong* location_of_counter ); |
| 761 | |
sewardj | 6c77c95 | 2004-07-03 14:51:44 +0000 | [diff] [blame] | 762 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 763 | #endif /* ndef __VEX_HOST_X86_DEFS_H */ |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 764 | |
| 765 | /*---------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 766 | /*--- end host_x86_defs.h ---*/ |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 767 | /*---------------------------------------------------------------*/ |