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gerrit-public.fairphone.software / platform / external / valgrind / 0a4f4bb3e2a7a0119989ee0dc8fdffaab2f1b160
  1. 0a4f4bb Correctly handle add(hi) when the destination register is the PC. Fixes #332037. by sewardj · 11 years ago
  2. 505a27d Back-end handling of Iop_CmpNEZ32x4, Iop_CmpNEZ16x8, Iop_CmpNEZ8x16, by sewardj · 11 years ago
  3. 99c1f81 Implement a couple of backend artefacts needed by Memcheck on large by sewardj · 11 years ago
  4. e0bff8b Do early writeback of the base register for the following instruction by sewardj · 11 years ago
  5. f21a6ca * iselIntExpr_AMode_wrk: generate correct code for the case by sewardj · 11 years ago
  6. 1eaaec2 Support extra instruction bits and pieces, enough to get Firefox started: by sewardj · 11 years ago
  7. b176a6f mips32: Fix the problem with reading the guest_FCSR register from the wrong guest state. by dejanj · 11 years ago
  8. 5ba4130 Fix error in 64-bit and smaller load versions of by sewardj · 11 years ago
  9. 32d8675 Implement REV16, REV32, FCVTN, SHL (vector, immediate), NEG (vector) by sewardj · 11 years ago
  10. 5860ec7 Remove redundant FMOV (vector, immediate) case. by sewardj · 11 years ago
  11. 9b1cf5e Select and emit insns for Iop_ZeroHI64ofV128 Iop_Max8Sx16 Iop_Min8Sx16 by sewardj · 11 years ago
  12. 63ab9dd mips32: Fpu guest registers are ULong and the initial values need to be by dejanj · 11 years ago
  13. dc9259c Implement a few more integer instructions: NOP LDA{R,RH,RB} STL{R,RH,RB} RBIT by sewardj · 11 years ago
  14. f37c086 mips32: Fix the problem with the floating point compare instruction on mips32. by dejanj · 11 years ago
  15. d512d10 * add a kludgey fix for "mrs rT, dczid_el0" by sewardj · 11 years ago
  16. 7d00913 First pass at implementation of load/store exclusive and by sewardj · 11 years ago
  17. c6acaa4 Implement unchainXDirect_ARM64. by sewardj · 11 years ago
  18. 0e006f2 mips32: VEX Support for 64bit FPU on MIPS32 platforms. by dejanj · 11 years ago
  19. e520bb3 Implement more aarch64 vector insns: by sewardj · 11 years ago
  20. 95d9e8f mips64: add support for load indexed instructions from DSP ASE by petarj · 11 years ago
  21. 95a487b Fix comments and code snippets that were making incorrect claims about by florian · 11 years ago
  22. 08d02cb s390: Fix s390_amode_for_guest_state. In general the offset relative by florian · 11 years ago
  23. 2171afd Fix the ppc32 special-instruction magic sequence so it really does by sewardj · 11 years ago
  24. fab0914 Implement more aarch64 vector insns: by sewardj · 11 years ago
  25. f0bb679 Add support for syscall on x86 by tom · 11 years ago
  26. f5b0891 Implement a few more vector aarch64 insns: by sewardj · 11 years ago
  27. ecde697 Implement a few more vector aarch64 insns: by sewardj · 11 years ago
  28. d20794a mips64: Support for Cavium-specific load indexed instructions by petarj · 11 years ago
  29. 606c4ba Improve front and back end support for SIMD instructions on Arm64. by sewardj · 11 years ago
  30. 9571dc0 Make the following primops take a third (initial) argument to by sewardj · 11 years ago
  31. 9fcbb9a This patch by adrian.sendroiu@freescale.com fixes the lrmw and stmw by carll · 11 years ago
  32. 8b1715b Whitespace-only change: restrict to 80 col width. by sewardj · 11 years ago
  33. 1df406c mips64: Change the initial value of fpu registers. by dejanj · 11 years ago
  34. 6068788 arm64: rename guest_SP to guest_XSP so as to avoid a name clash with by sewardj · 11 years ago
  35. aeeb31d Add missing ULLs to some 64-bit immediates. by sewardj · 11 years ago
  36. bbcf188 Add support for ARMv8 AArch64 (the 64 bit ARM instruction set): by sewardj · 11 years ago
  37. 0e457fc LibVEX_GuestAMD64_initialise(): give an initial value for by sewardj · 11 years ago
  38. a2039c5 The result of rounding a 128-bit BFP/DFP value to 32/64 bit needs to by florian · 11 years ago
  39. d5453bf Bug 328100 - XABORT not implemented. by mjw · 11 years ago
  40. 4183322 mips32/64: Fixed the problem with fpu instructions. by dejanj · 11 years ago
  41. e03b600 Fix Bug 327284. The condition code of risbg was not correct. by cborntra · 11 years ago
  42. 781f1bd mips32: Fix problem with some mips32 dsp instructions. by dejanj · 11 years ago
  43. a445f1b mips32: Fixed the problem with FCSR register. by dejanj · 11 years ago
  44. f5530ec In 64 bit mode, allow 64 bit return values from clean helper calls. by sewardj · 11 years ago
  45. 89ae847 Update copyright dates (20XY-2012 ==> 20XY-2013) by sewardj · 11 years ago
  46. 83da6d7 Handle PCMPxSTRx cases 0x30 and 0x40. Fixes #320998. by sewardj · 11 years ago
  47. 60c6bac This commit adds support for the following instructions: by carll · 11 years ago
  48. 7deaf95 Power 8 support, phase 5 by carll · 11 years ago
  49. 6491f86 Tidyup -- no functional change. Replace all "pfx & PFX_LOCK" by sewardj · 11 years ago
  50. 38b1d69 amd64 front end: accept XACQUIRE and XRELEASE on exactly the insns that by sewardj · 11 years ago
  51. 66e40ae Add support for an alternative encoding of 'PUSH reg', viz FF /6, by sewardj · 11 years ago
  52. 2691a61 PPC32/64: Allow 16 byte icache lines. by sewardj · 11 years ago
  53. fcce5f8 Power PC, add the two privileged Transactional Memory instructions. by carll · 11 years ago
  54. 3bc88cc mips64: add extra Iop cases in VEX. by dejanj · 11 years ago
  55. 9d690c6 Fix guest_amd64_toIR xbegin and xtest to match cpuid given for AVX hwcaps. by mjw · 11 years ago
  56. 6c758b6 Phase 4 support for IBM Power ISA 2.07 by carll · 11 years ago
  57. 8943d02 Power PC, Approach 1, add Transactional Memory instruction support by carll · 11 years ago
  58. 48ae46b Phase 3 support for IBM Power ISA 2.07 by carll · 11 years ago
  59. 4ccd258 Implement LDRHT (Thumb), LDRSHT (Thumb), [LDR,ST]{S}[B,H]T (ARM). by sewardj · 11 years ago
  60. 3b22fc8 Implement LDRHT (Thumb), LDRSHT (Thumb), [LDR,ST]{S}[B,H]T (ARM). by sewardj · 11 years ago
  61. 9e4c376 Add a kludgey implementation of XTEST to go with the kludgey by sewardj · 11 years ago
  62. f7e5958 armg_calculate_condition: add missing masking (probably pointless, by sewardj · 11 years ago
  63. e8e46ab mips64: finetune mips_dirtyhelper_calculate_FCSR by petarj · 11 years ago
  64. 8e70cdc mips32: protect mips32r2 instructions with a flag by petarj · 11 years ago
  65. 1c56013 mips32/64: Save the value of FCSR register at the beginning and restore it by dejanj · 11 years ago
  66. a759d17 mips32/64: Code cleanup and VEX optimizations. No functional changes. by dejanj · 11 years ago
  67. 512f059 mips32/64: Fix the problem with dirty helper when the by dejanj · 11 years ago
  68. a56f369 Add support for the Intel TM "xbegin" instruction, by jumping directly by sewardj · 11 years ago
  69. 1bf44e3 x86 front ends: tighten up decoding of MOV Ib,Eb and MOV Iv,Ev. This by sewardj · 11 years ago
  70. aae16ca Unbreak the build on non-MIPS platforms. by tom · 11 years ago
  71. 8007ea6 mips32/mips64: additional VEX support for FCSR register. by dejanj · 11 years ago
  72. 5cc3b45 mips64: VEX support for MIPS64 Octeon Instructions by petarj · 11 years ago
  73. bc7d6f4 mips: clean-up in hardware detection (Cavium/DSP ASEs) by petarj · 11 years ago
  74. 994cc46 mips32: small cleanup in show_hwcaps_mips32 by petarj · 11 years ago
  75. af514c0 s390: Add spechelper for s390_calculate_cc. by florian · 11 years ago
  76. c31e6cb Bug 323893 - SSE3 not available on amd cpus in valgrind. by mjw · 11 years ago
  77. 6fef87a The Power ISA 2.07 document includes a correction to the description for the by carll · 11 years ago
  78. d6bc217 Remove dead code. by florian · 11 years ago
  79. 740da72 Enhance ado_treebuild_BB to allow an expression preceding a Put by florian · 11 years ago
  80. 81d4ff2 mips64: fixed problem with Iop's for mips64. by dejanj · 11 years ago
  81. 78850ae Bugzilla 323437, this is phase 2 in a series of patches adding support for IBM by carll · 11 years ago
  82. de6f710 Add a few more optimisations for CmpwNEZ64, CmpNEZ32, and CmpNEZ64. by florian · 11 years ago
  83. 38b79ac The existing overflow detection in VEX/priv/guest_ppc_toIR.c/set_XER_OV_64() by carll · 11 years ago
  84. 9708b6a The patch used the binary constants 0b10000 and 0b10001. The 0b designator by carll · 11 years ago
  85. c3a3791 Update list of ignored files. by florian · 11 years ago
  86. b77db0e The current code is not properly handling a non-zero TH field in the by carll · 11 years ago
  87. 2accb5e deltaIRExpr cannot handle Iex_VECRET and Iex_BBPTR and needs to be guarded. by florian · 11 years ago
  88. e3a103f mips32/mips64: Fix the problem with lwl and lwr for mips32 and mips64. by dejanj · 11 years ago
  89. 54eea4e Comment-only change. by sewardj · 11 years ago
  90. 854912a Add an optimisation for Iop_Left64. by florian · 11 years ago
  91. 55ce7b7 Add algebraic simplifications for Iop_And64 (same as for Iop_And32). by florian · 11 years ago
  92. 6c65c12 Support mmxext (integer sse) subset on i386 (athlon). by mjw · 11 years ago
  93. d69cd9a mips64: Fix a problem with CCall.retty type. by dejanj · 11 years ago
  94. 82cc37c Add support for 256-bit return values for dirty helpers (amd64 only). by sewardj · 11 years ago
  95. 9041956 Eliminate IRExprP__VECRET and IRExprP__BBPTR and introduce two new by florian · 11 years ago
  96. c529555 mips32/mips64: Fix compiler warnings. by dejanj · 11 years ago
  97. 0c74bb5 Initial ISA 2.07 support for POWER8-tuned libc by carll · 11 years ago
  98. 74142b8 Add infrastructural support (IR, VEX) to allow returns of 128- by sewardj · 11 years ago
  99. 3cfd1f0 Add a spec rule for SUBQ/NLE. by sewardj · 11 years ago
  100. 0af77fc Update Makefile-gcc to include additional files that were added in r2702. by florian · 11 years ago