- 88c5796 Add "make -j N" kludge to Vex too. by sewardj · 19 years ago
- 1bee561 Handle instrumentation artefacts arising from memchecking Altivec by sewardj · 19 years ago
- 24d06f1 Fix usage of Iop_MullEven* to give IR correct meaning of which lanes being multiplied, i.e. lowest significant lane = zero by cerion · 19 years ago
- 4a49b03 Frontend: by cerion · 19 years ago
- ccd0c84 Don't delete existing target-specific .a's when a target-switch happens. by sewardj · 19 years ago
- a1eb31c Changes for biarch (x86 and amd64) support. by sewardj · 19 years ago
- 90e91ee Handle some SSE3 instructions. A curious side-effect of this is that by sewardj · 19 years ago
- 3f46a01 Simulate complete LDT and GDT, rather than just a prefix thereof. by sewardj · 19 years ago
- 43f4573 format string wibble by sewardj · 19 years ago
- f526843 Stop gcc4 complaining. by sewardj · 19 years ago
- 0585a03 Implement FINIT. by sewardj · 19 years ago
- b928263 Implement vector FP unordered compares on amd64. by sewardj · 19 years ago
- a26f661 The earth's core is a vast mass of molten sse and sse2 instructions. by sewardj · 19 years ago
- 9fb2f47 Reenable FUCOMP %st(0),%st(?). by sewardj · 19 years ago
- 75ce365 Implement SHRDv imm8. by sewardj · 19 years ago
- 33ef9c2 Implement shld/shrd on amd64. Total timewasting nightmare, not helped by sewardj · 19 years ago
- 1ac656a New irop Iop_MullEven* - a widening un/signed multiply of even lanes by cerion · 19 years ago
- c01c1fa Handle jecxz in addition to jrcxz. by sewardj · 19 years ago
- 42561ef Handle address-size overrides in the common case (explicit memory references). by sewardj · 19 years ago
- 6d7c4f0 Handle any number of 0x66 (operand-size-override) prefixes. by sewardj · 19 years ago
- 5e55f49 wibble by sewardj · 19 years ago
- 4fa325a API change: make the handling of syscall-denoting instructions a bit by sewardj · 19 years ago
- 36e2355 Generate offsets for all amd64 integer registers. by sewardj · 19 years ago
- 240fd86 Implement 66 0F 11 = MOVUPD (untested) by sewardj · 19 years ago
- 62d0543 Tidy up a couple of format strings. by sewardj · 19 years ago
- d14c570 x86 front end: implement in/out insns. by sewardj · 19 years ago
- dc1f913 Fill in a few missing Altivec cases: by sewardj · 19 years ago
- 3f21fd3 Remove inefficient and not-completely-general logic in addHRegUse and by sewardj · 19 years ago
- d147094 Minor altivec changes: by sewardj · 19 years ago
- 69b7291 Unbreak build. by sewardj · 19 years ago
- f461149 API change: pass both the VexGuestExtents and the original by sewardj · 19 years ago
- 197bd17 Build fixes for gcc-2.96 (which does not allow declarations after the by sewardj · 19 years ago
- dfb1144 Handle the out-of-range shift cases for slw/srw in a different way by sewardj · 19 years ago
- 9d540e5 Enable chasing of unconditional branches and calls. by sewardj · 19 years ago
- 26b3320 Special-case rlwnms which are really slwi or srwi. This gives about by sewardj · 19 years ago
- fb6c179 Handle FUCOM %st(0),%st(?). by sewardj · 19 years ago
- a7690fb Handle BT/BTS/BTR/BTC at size 4 as well as 8. by sewardj · 19 years ago
- fdfa886 Implement JRCXZ. by sewardj · 19 years ago
- 59ff5d4 Handle the redundant-encoding (Grp5) versions of {inc,dec}{b,w}. by sewardj · 19 years ago
- b8a3dea Handle SSE2 pmaddwd. by sewardj · 19 years ago
- 7b5b998 Implement SSE2 psadbw. by sewardj · 19 years ago
- 8dfdc8a Implement LAHF. by sewardj · 19 years ago
- 9ca2640 Implement the 0F 7F encoding for movq mmreg, mmreg. by sewardj · 19 years ago
- fb470fa Enable Xin_MFence on VexSubArchX86_sse0. by sewardj · 19 years ago
- 2fbae08 Fix various adc/sbb instruction variants. by sewardj · 19 years ago
- fda10af x86 front end: implement FXTRACT. I knew there was a reason I'd been by sewardj · 19 years ago
- 6f1cc0f Some AltiVec vector-multiply arith insns by cerion · 19 years ago
- f34ccc4 spacing and var name chages only by cerion · 19 years ago
- 0a7b4f4 More AltiVec: shifts and rotates - vrl*, vsl*, vsr* by cerion · 19 years ago
- 7355d27 Rename primop Iop_Rot* Iop_Rotl* by cerion · 19 years ago
- 3c05279 Added packing/unpacking AltiVec insns - vpk*, vupk* by cerion · 19 years ago
- 92d9d87 Added AltiVec permutation insns: - vperm, vsldoi, vmrg*, vsplt* by cerion · 19 years ago
- 2a4b845 Couple more primops: Iop_ShlN8x16, Iop_ShrN8x16, Iop_SarN8x16 by cerion · 19 years ago
- 030fd36 Makefile fixes: by sewardj · 19 years ago
- 0c43922 Added AltiVec integer compare insns. by cerion · 19 years ago
- 36991ef Implemented simple AltiVec arithmetic insns: by cerion · 19 years ago
- 61c9274 Added AltiVec sub-vector load/store insns: by cerion · 19 years ago
- d3e5241 implemented vaddcuw by cerion · 19 years ago
- 27b3d7e more altivec insns: vsr, vspltw - only working with with --tool=none by cerion · 19 years ago
- 6f6c6a0 implemented guest-ppc32 lvsl, lvsr using dirty helper function by cerion · 19 years ago
- 9e7677b yet another new IR primop: Iop_QNarrow32Ux4 by cerion · 19 years ago
- f887b3e Added a number of new IR primops to support integer AltiVec insns by cerion · 19 years ago
- 6e7a0ea a couple more simple altivec insns - vandc, vnor, vsel by cerion · 19 years ago
- bd5cb07 ppc guest_state vector regs must be 16byte aligned for loads/stores by cerion · 19 years ago
- 225a034 by cerion · 19 years ago
- 32aad40 reinstated altivec insn disassembly framework by cerion · 19 years ago
- c7cd214 Typechecker cleanups (non-functional changes) by sewardj · 19 years ago
- a9135fd iselInt64Expr: handle 64-bit Mux0X. by sewardj · 19 years ago
- 55ccc3e Fix mcrxr. by sewardj · 19 years ago
- cb14e73 reinstate lhau, lhaux, sthux, mcrxr by cerion · 19 years ago
- f5936dc implemented Iop_64HLtoV128 in iselVecExpr_wrk by cerion · 19 years ago
- 5f63c0c Reinstate stfdux, fctiw. by sewardj · 19 years ago
- afe8583 Cleanups: by sewardj · 19 years ago
- 0f2c540 rm unused vars in dis_int_ldst_str by sewardj · 19 years ago
- 5876fa1 Implement stswi/stswx. by sewardj · 19 years ago
- e810c19 Enhance the dead-code removal pass so that it detects unconditional by sewardj · 19 years ago
- 87e651f Implement lswi and lswx. The generated IR should be good for by sewardj · 19 years ago
- fb95797 Reinstate stwbrx. by sewardj · 19 years ago
- 7c2dc71 Reinstate crand, crnand, crorc. by sewardj · 19 years ago
- 73a9197 Implement mftb{,u}. by sewardj · 19 years ago
- d269136 Remove some helper functions to do with flag handling. These are by sewardj · 19 years ago
- 602857d Reinstate lwbrx. by sewardj · 19 years ago
- 967de5c Observe any externally supplied $(CC). by sewardj · 19 years ago
- 8161abc Don't even mention malloc, since it screws up statically linked, glibc Valgrind. by sewardj · 19 years ago
- 3ed5484 Implement MOVUPS -- move from G (xmm) to E (mem or xmm) [UNVERIFIED] by sewardj · 19 years ago
- da46fdd vex_printf/sprintf hackery. by sewardj · 19 years ago
- 820611e Build rflag thunk for adc/sbb correctly. by sewardj · 19 years ago
- 9ed1680 amd64: Handle BT/BTS/BTR/BTC Gv, Ev. by sewardj · 19 years ago
- 3b3eacd Fix incorrect building of the flags thunk after ADC and SBB. by sewardj · 19 years ago
- eca2036 Enable ADC Ib, AL. by sewardj · 19 years ago
- e8f6525 Implement LOOP{,E,NE}. by sewardj · 19 years ago
- 8707fef Rename a couple of inconsistently-named helper functions. by sewardj · 19 years ago
- a5cbbdc Whitespace-only change. by sewardj · 19 years ago
- bc6af53 Implement RDTSC (amd64). by sewardj · 19 years ago
- 8f40b07 Rename a couple of inconsistently-named helper functions. by sewardj · 19 years ago
- 4ed6429 Implement RDTSC on x86. by sewardj · 19 years ago
- baa6608 Implement LOOP/LOOPE/LOOPNE. by sewardj · 19 years ago
- 4857d4f Enable testing of RCL insns. by sewardj · 19 years ago
- 2eef773 Support x86 RCL instructions. by sewardj · 19 years ago
- 6a64a9f On a PPC32Instr_Call, don't merely record how many integer registers by sewardj · 19 years ago