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gerrit-public.fairphone.software / platform / external / valgrind / 2a4de0bb56f33835bab59c0e483acc8410baed98
  1. 2a4de0b Fix some verbiage. by florian · 10 years ago
  2. 166d645 mips64: add support for Cavium BBIT032 and BBIT132 by petarj · 10 years ago
  3. 9e1c2b0 Implement FRINTI d_d, s_s. by sewardj · 10 years ago
  4. ca95f2d Implement RORV x_x_x, w_w_w by sewardj · 10 years ago
  5. 928540c Implement CLS x_x, w_w by sewardj · 10 years ago
  6. 39b5168 arm64: implement "BRK #imm16". by sewardj · 10 years ago
  7. 406ac94 Add function s390_isel_amode_b12_b20 to compile an expression into an by florian · 10 years ago
  8. 608e560 Remove dead code. by florian · 10 years ago
  9. 4687eb3 This change was triggered by BZ #247974 which suggested to include by florian · 10 years ago
  10. 266d596 arm64: enable FCVT{A,N}S X,S. by sewardj · 10 years ago
  11. 1aff76b Implement {S,U}CVTF (scalar, fixedpt). by sewardj · 10 years ago
  12. d6d13b3 Implement VFPv4 VFNMA, VFNMS d_d and s_s variants (not that by sewardj · 10 years ago
  13. b963eef Fix stupid bug introduced in r2993, which causes many simple scalar by sewardj · 10 years ago
  14. 76927e6 Implement arm64 insns: by sewardj · 10 years ago
  15. 0728a52 Implement "fcvtpu w, s". n-i-bz. by sewardj · 10 years ago
  16. e23ec11 Implement fcsel d_d, s_s. Fixes #340856. by sewardj · 10 years ago
  17. d2c19b4 Add detection of old ppc32 magic instructions from bug 278808. by mjw · 10 years ago
  18. e3a10d7 Add a nasty temporary kludge to CPUID that allows 64-bit MacOSX 10.10 by sewardj · 10 years ago
  19. 07ab40d Fix incorrect decoding of AVX2 insns: by sewardj · 10 years ago
  20. c871940 Bug 340632 arm64: unhandled instruction fcvtas by mjw · 10 years ago
  21. 2584255 Handle all DSB/DMB/ISB variants. Fixes #340033. by sewardj · 10 years ago
  22. 5b924c8 Implement PRFM (immediate). Fixes #335713. by sewardj · 10 years ago
  23. f67fcb9 Implement FCVTAS W_S and FCVTAU W_S. Fixes #340509. by sewardj · 10 years ago
  24. d0e5e53 Implement by sewardj · 10 years ago
  25. 31b29af Implement fcvtmu x_d. Fixes #339927. by sewardj · 10 years ago
  26. d8ad76a Implement frintx d_d and s_s. Fixes #339926. by sewardj · 10 years ago
  27. 23872f6 Tweak to allow the use of this Makefile with the ICC compiler. by florian · 10 years ago
  28. bed9f68 * add a missing extra m-reg check for some LD/ST vector cases by sewardj · 10 years ago
  29. 75d774c Companion patch of valgrind r14664. by florian · 10 years ago
  30. 74e5e6b Memove unused macro. Should have been part of r2955. by florian · 10 years ago
  31. 208a776 Implement SIMD (de)interleaving loads/stores: by sewardj · 10 years ago
  32. f4f25ff Bug 339858 arm64 recognize dmb sy. Data Memory Barrier full SYstem variant. by mjw · 10 years ago
  33. bde3406 Merge the memory allocation bits from libvex.h into main_util.c. by florian · 10 years ago
  34. 85175a7 This patch makes the needed changes to the lxvw4x for Little Endian. by carll · 10 years ago
  35. 67ec22c mips: add a missing break by petarj · 10 years ago
  36. 830ef70 mips: use putDReg/getDReg for ceil.l.d by petarj · 10 years ago
  37. d8c64e0 Constification part 5. by florian · 10 years ago
  38. b66ad46 Use __typeof__ to improve readability and future maintainability. by florian · 10 years ago
  39. 017c0d5 Remove unused prototype. Add a fixs390. by florian · 10 years ago
  40. 99de41e This commit just makes white space changes to the three files in commit by carll · 10 years ago
  41. 9877fe5 msg by carll · 10 years ago
  42. aedb859 guest_amd64_spechelper: fill in a number of missing cases for by sewardj · 10 years ago
  43. b979d7a Add folding rules for: Sar64(x,0) and Sar32(x,0). Immediate by sewardj · 10 years ago
  44. edccb44 guest_amd64_spechelper: number (in comments) and reorder the spec by sewardj · 10 years ago
  45. 4e303f2 ppc64: lxvw4x instruction uses four 32-byte loads. When run on an by carll · 10 years ago
  46. dff2041 Remove unneeded variable. by florian · 10 years ago
  47. 678ede2 The function mk_AvDuplicateRI() stores 16 bytes to memory and then by carll · 10 years ago
  48. 8462d11 Constification part 4. by florian · 10 years ago
  49. 0a5494e Constification part 3. by florian · 10 years ago
  50. a5c17c6 The PPC64 store quad instruction is updating the address register with the by carll · 10 years ago
  51. 7d6f81d Constification part 2. by florian · 10 years ago
  52. 9b696ac Remove the valgrind_support parameter from LibVEX_Init. It's unused by florian · 10 years ago
  53. 0b70efa Constification part 1. by florian · 10 years ago
  54. e74ce2e Couple of fixes: by florian · 10 years ago
  55. 2580da4 In s390_decode_and_irgen don't divert the default case to a decoding error. by florian · 10 years ago
  56. 28d71ed Change how FXSAVE and FXRSTOR are done, so as to avoid pushing the XMM by sewardj · 10 years ago
  57. afa3f04 Minor refactoring to avoid special handling of emulation by florian · 10 years ago
  58. efe536b Handle fcvtpu Xd,Sn. Fixes #335564. by sewardj · 10 years ago
  59. f72c2c1 Use const instead of a comment. by florian · 10 years ago
  60. 7842caf iselStmt, case Ist_Dirty: remove pointless conditional. Spotted by by sewardj · 10 years ago
  61. ef6f26a mips64: fix jmpKind for BLTZ and BGEZ by petarj · 10 years ago
  62. 7ec7750 arm64: enable support for: str bN, [reg, reg etc] by sewardj · 10 years ago
  63. a90baf7 mips64: implement Cavium BBIT0 and BBIT1 instructions by petarj · 10 years ago
  64. 5762841 Add a missing return statement. Spotted by the Coverity checker. by florian · 10 years ago
  65. 8def049 arm64: route all whole-vector shift/rotate/slice operations by sewardj · 10 years ago
  66. e6b9bd9 Rename Iop_Extract{64,V128} to Iop_Slice{64,V128}, improve their by sewardj · 10 years ago
  67. 0ad37a9 Add support for generating ProfInc sequences on ARM64, so as to by sewardj · 10 years ago
  68. eae4af6 mips: remove unused macro by petarj · 10 years ago
  69. c328e15 mips: fix typo (IRType/IRTemp) by petarj · 10 years ago
  70. 3ce4dec Add support for four IROps that Memcheck generates on arm64, that by sewardj · 10 years ago
  71. 15ceaef Comment-only change. by sewardj · 10 years ago
  72. fc261d9 arm64: implement: {zip,uzp,trn}{1,2} (vector) urecpe, ursqrte (vector) by sewardj · 10 years ago
  73. 1ddee21 Rename IROps for reciprocal estimate, reciprocal step, reciprocal sqrt by sewardj · 10 years ago
  74. e3fa0f8 Bug 330319 - vex amd64->IR: unhandled instruction bytes: 0xF 0x1 0xD5 (xend) by mjw · 10 years ago
  75. 150794d putGST_masked: correctly handle the case where the mask is for by sewardj · 10 years ago
  76. f7003bc arm64: implement: suqadd, usqadd (scalar) suqadd, usqadd (vector) by sewardj · 10 years ago
  77. 62ece66 arm64: implement srhadd, urhadd (vector) by sewardj · 10 years ago
  78. a6b61f0 arm64: implement by sewardj · 10 years ago
  79. 4a85b8e No functional change. Remove commented out code copied from the by sewardj · 10 years ago
  80. 1dd3ec1 Rename Iop_QSalN*, Iop_QShlN* and Iop_QShlN*S so as to more accurately by sewardj · 10 years ago
  81. acc2964 arm64: implement: {uqshl, sqshl, sqshlu} (scalar, imm) and fix two by sewardj · 10 years ago
  82. a97dddf arm64: implement: {uqshl, sqshl, sqshlu} (vector, imm). by sewardj · 10 years ago
  83. fbe569d Add a simple folding rule for Iop_ZeroHI64ofV128. by sewardj · 10 years ago
  84. e741d16 arm64: implement: uqshrn{2}, sqrshrun{2}, sqshrun{2} (scalar, imm) by sewardj · 10 years ago
  85. 2faf591 Small cleanups in VEX: by philippe · 10 years ago
  86. ecedd98 arm64: implement: by sewardj · 10 years ago
  87. 0caa0c0 Add a new folding rule: by sewardj · 10 years ago
  88. 99af243 Unbreak the build by philippe · 10 years ago
  89. 94e2de3 This commit is for Bugzilla 334834. by carll · 10 years ago
  90. 1f5fe1f This commit is for Bugzilla 334834. The Bugzilla contains patch 2 of 3 by carll · 10 years ago
  91. 1297218 arm64: add support for: sqshl, uqshl, sqrshl, uqrshl (reg) (vector and scalar) by sewardj · 10 years ago
  92. b01ff40 Add a folding rule: XorV128(t,0) ==> t. by sewardj · 10 years ago
  93. 257e99f arm64: implement remaining SQDMULH and SQRDMULH cases. by sewardj · 10 years ago
  94. 9b76916 Improve infrastructure for dealing with endianness in VEX. This patch by sewardj · 10 years ago
  95. 54ffa1d arm64: implement: by sewardj · 10 years ago
  96. f3eaabd Comment-only change. by sewardj · 10 years ago
  97. 51d012a arm64: implement: sqneg, {u,s}q{add,sub} (scalar), by sewardj · 10 years ago
  98. 7e67bb6 Initialise a couple of scalars that gcc -Og thinks might be by sewardj · 10 years ago
  99. 2782d21 Add a few more algebraic optimisations for Iop_And8/16. Observed on s390. by florian · 10 years ago
  100. d1526f2 Remove fields from VexAbiInfo that only had relevance to the old AIX5 by sewardj · 10 years ago