Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / external / valgrind / 899d1838d6fd60b141a3d808b02dc04be5901681 / priv / guest_ppc_toIR.c
  1. 738d9dd fix 303116 Add support for the POWER instruction popcntb (VEX part) by philippe · 12 years ago
  2. 4c96e61 POWER Processor decimal FP support, part 5 (VEX side). Bug #299694. by sewardj · 12 years ago
  3. c9069f2 Enhance the guest state effects notation on IRDirty calls, so as to be by sewardj · 12 years ago
  4. cb06d5e Don't use constants of the form 0b...; apparently older compilers by sewardj · 12 years ago
  5. 5eff1c5 Add support for POWER Power Decimal Floating Point (DFP) test class, by sewardj · 12 years ago
  6. cdc376d POWER Processor decimal floating point instruction support, part 3 by sewardj · 13 years ago
  7. db01409 Merge branches/TCHAIN from r2271 (its creation point) into trunk. by sewardj · 13 years ago
  8. 3dee849 Add translation chaining support for ppc32 (tested) and to by sewardj · 13 years ago
  9. 26217b0 by sewardj · 13 years ago
  10. c6f970f Add translation chaining support for amd64, x86 and ARM (VEX side). See #296422. by sewardj · 13 years ago
  11. c66d6fa Fixes for capabilities checking w.r.t. Power DFP instructions (VEX by sewardj · 13 years ago
  12. c6bbd47 Initial support for POWER Processor decimal floating point instruction by sewardj · 13 years ago
  13. dc7948f Add some VEX sanity checks for ppc64 unhandled instructions. by florian · 13 years ago
  14. e6c53e0 Update all copyright dates, from 20xy-2010 to 20xy-2011. by sewardj · 13 years ago
  15. e71e56a Add support for IBM Power ISA 2.06 -- stage 3. by sewardj · 13 years ago
  16. 4aa412a Add support for IBM Power ISA 2.06 -- stage 2. Bug 276784. by sewardj · 13 years ago
  17. 5f438dd Rename and rationalise the vector narrowing and widening primops, so by sewardj · 13 years ago
  18. c9bff7d Partially fix underspecification of saturating narrowing primops that by sewardj · 13 years ago
  19. 95d6f3a Fix up incorrect usage of Iop_I64UtoF32 in the PowerPC front and back by sewardj · 13 years ago
  20. 66d5ef2 Add support for IBM Power ISA 2.06 -- stage 1. Bug #267630 and by sewardj · 14 years ago
  21. 7e84630 Support new PowerISA_2.05 instructions available on Power6 CPUs. by sewardj · 14 years ago
  22. e971c6a Support the DCBZL instruction. Also, query the host CPU at startup by sewardj · 14 years ago
  23. 752f906 Update copyright dates to 2010 and change license to standard GPL2+. by sewardj · 14 years ago
  24. 984d9b1 by sewardj · 15 years ago
  25. 6c299f3 Merge r1925:1948 from branches/ARM. This temporarily breaks all other by sewardj · 15 years ago
  26. e768e92 by sewardj · 15 years ago
  27. 37b2ee8 Implement mfpvr (mfspr 287) (bug #201585). by sewardj · 15 years ago
  28. cef7d3e by sewardj · 15 years ago[Renamed (99%) from priv/guest-ppc/toIR.c]
  29. e9d8a26 Merge in branches/DCAS: by sewardj · 15 years ago
  30. e86310f In order to make it possible for Valgrind to restart client syscalls by sewardj · 16 years ago
  31. 1685c28 Tighten up decoding of isel instruction. by sewardj · 16 years ago
  32. cb07be2 Support isel (integer conditional move). by sewardj · 16 years ago
  33. 2b8db3e C89 fixes (stop gcc complaining). by sewardj · 16 years ago
  34. 0f1ef86 Handle frin, frim, frip, friz, in 64-bit mode only, for now. by sewardj · 16 years ago
  35. fe397a2 Ignore .EH bit in lwarx / ldarx as it appears to be merely a hint. by sewardj · 16 years ago
  36. 019f406 Add Imbe_SnoopedStoreBegin and Imbe_SnoopedStoreEnd, to be used for by sewardj · 16 years ago
  37. c85bf02 Allow 64-byte line sizes (PA6T cpu). by sewardj · 16 years ago
  38. 478646f Merge branches/OTRACK_BY_INSTRUMENTATION into the trunk. This by sewardj · 16 years ago
  39. a26d820 Update copyright dates ("200X-2007" --> "200X-2008"). by sewardj · 17 years ago
  40. c4356f0 by sewardj · 17 years ago
  41. 0f50004 Support x86 $int 0x40 .. 0x43 instructions on Linux. Apparently these by sewardj · 17 years ago
  42. b4f6d6b Support td (64-bit counterpart to r1784). by sewardj · 17 years ago
  43. 59c0d8f Better support for trap insns. This adds support for tw (previously twi and by sewardj · 17 years ago
  44. eb17e49 Merge from CGTUNE branch: by sewardj · 17 years ago
  45. 6d83422 Comment-only changes. by sewardj · 18 years ago
  46. e744153 Update copyright dates. by sewardj · 18 years ago
  47. 923c65b Enable support for altivec prefetches: dss, dst, dstt, dstst, dststt. by sewardj · 18 years ago
  48. d2fd864 Enable lvxl and stvxl. by sewardj · 18 years ago
  49. abb321c Implement mfspr 268 and 269. Fixes #139050. by sewardj · 18 years ago
  50. dd40fdf by sewardj · 18 years ago
  51. ef4433b When doing rlwinm in 64-bit mode, bind the intermediate 32-bit result by sewardj · 18 years ago
  52. ee4a859 ppc64: detect rldicl/rldicr which are simply 64-bit shifts left/right by sewardj · 18 years ago
  53. aca070a Merge r1663-r1666: by sewardj · 18 years ago
  54. 496b88f Reinstate support for 'mcrfs'. by sewardj · 18 years ago
  55. 9195aa1 Fix previous commit (r1640?) so that it's actually correct :-) by sewardj · 18 years ago
  56. a9cb67b Comparing a reg with itself produces a result which doesn't depend on by sewardj · 18 years ago
  57. a33e9a4 Update copyright dates. by sewardj · 18 years ago
  58. 413a468 Implement sthbrx. by sewardj · 18 years ago
  59. 40d8c09 Implement lhbrx. by sewardj · 18 years ago
  60. a5f55da Don't use the bits VexArchInfo.hwcaps to distinguish ppc32 and ppc64, by sewardj · 18 years ago
  61. 72aefb2 Implement mtocrf/mfocrf. by sewardj · 19 years ago
  62. 40c8026 Redo the way FP multiply-accumulate insns are done on ppc32/64. by sewardj · 19 years ago
  63. 2d19fe3 Word size fixes for twi/tdi (is trickier than it looks :-). Also add by sewardj · 19 years ago
  64. 334870d ppc32/64: handle twi/tdi (conditional trap) instructions by sewardj · 19 years ago
  65. 56de421 fre: observe the current rounding mode by sewardj · 19 years ago
  66. b183b85 by sewardj · 19 years ago
  67. 157b19b Do fre/fres in a way which makes minimal demands on the backend. by sewardj · 19 years ago
  68. 79fd33f Handle fre and frsqrtes. Even though the IBM docs manage to by sewardj · 19 years ago
  69. 2ef8a37 Make lsw work in 64-bit mode. by sewardj · 19 years ago
  70. 7c54586 Unbreak ppc32 following recent hw-capabilities hackery. by sewardj · 19 years ago
  71. 5117ce1 Change the way Vex represents architecture variants into something by sewardj · 19 years ago
  72. 09e88d1 Re-enable stfiwx. by sewardj · 19 years ago
  73. baf971a Handle ppc32/64 fres, frsqrte. by sewardj · 19 years ago
  74. 6332740 C89 fixes. by sewardj · 19 years ago
  75. 6be6723 Minor tweaks to handle instructions created by xlc 7.0. by sewardj · 19 years ago
  76. 870c84b Re-enable fsqrts. by sewardj · 19 years ago
  77. 5ff11dd More ppc64-only function wrapping hacks: by sewardj · 19 years ago
  78. cf8986c For ppc64, emit AbiHints from the front end so as to tell tools when by sewardj · 19 years ago
  79. c716aea Two different sets of changes (hard to disentangle): by sewardj · 19 years ago
  80. 1eb7e6b Update fn redirect/wrap hooks for ppc64. by sewardj · 19 years ago
  81. ce02aa7 Merge in function wrapping support from the FNWRAP branch. That by sewardj · 19 years ago
  82. e43bc88 ppc: deal with L flag properly for different sync forms. by cerion · 19 years ago
  83. 3ea49ee ppc: re-enable mtfsb1 instruction. by cerion · 19 years ago
  84. 7277be5 Fix magic-sequence spotting in 64-bit mode. by sewardj · 19 years ago
  85. dba87e2 ppc64 altivec: by cerion · 19 years ago
  86. 4c4f5ef Handle ppc64's function ptr's for toIR.c's dirtyhelper calls. by cerion · 19 years ago
  87. 4e2c2b3 ppc64 fixes: by cerion · 19 years ago
  88. b029a61 Apparently "sync" has an undocumented relative called "lwsync". Sigh. by sewardj · 19 years ago
  89. cb1f68e Handle dcbz in 64-bit mode. by sewardj · 19 years ago
  90. 7594920 Comment only changes - misc refs to ppc32 changed to ppc. by cerion · 19 years ago
  91. fb197c4 Fix AltiVec load/store on ppc64 - was only considering lo32 bits of address. by cerion · 19 years ago
  92. d0eae2d renamed VEX dirs guest-ppc32/ -> guest-ppc/, host-ppc32/ -> host-ppc/ by cerion · 19 years ago[Renamed (99%) from priv/guest-ppc32/toIR.c]
  93. 5b2325f Changed naming convention from 'PPC32' to 'PPC' for all VEX code common to both PPC32 and PPC64. by cerion · 19 years ago
  94. 07b07a9 Implemented almost all of the remaining 64bit-mode insns. by cerion · 19 years ago
  95. 59b2c31 Fix typos. by cerion · 19 years ago
  96. bb01b7c Fixed up front and backend for 32bit mul,div,cmp,shift in mode64 by cerion · 19 years ago
  97. 876ef41 Enable fsqrt Document store fp single-precision problem by cerion · 19 years ago
  98. f0de28c Implemented backend for ppc64, sharing ppc32 backend. by cerion · 19 years ago
  99. 729edb7 Re-enabled ppc32 frontend floating point load/store single precision insns: by cerion · 19 years ago
  100. 2831b00 Fixed a couple of mode32 bugs introduced by mode64 by cerion · 19 years ago