- 9e1c2b0 Implement FRINTI d_d, s_s. by sewardj · 10 years ago
- ca95f2d Implement RORV x_x_x, w_w_w by sewardj · 10 years ago
- 928540c Implement CLS x_x, w_w by sewardj · 10 years ago
- 39b5168 arm64: implement "BRK #imm16". by sewardj · 10 years ago
- 266d596 arm64: enable FCVT{A,N}S X,S. by sewardj · 10 years ago
- 1aff76b Implement {S,U}CVTF (scalar, fixedpt). by sewardj · 10 years ago
- b963eef Fix stupid bug introduced in r2993, which causes many simple scalar by sewardj · 10 years ago
- 76927e6 Implement arm64 insns: by sewardj · 10 years ago
- 0728a52 Implement "fcvtpu w, s". n-i-bz. by sewardj · 10 years ago
- e23ec11 Implement fcsel d_d, s_s. Fixes #340856. by sewardj · 10 years ago
- c871940 Bug 340632 arm64: unhandled instruction fcvtas by mjw · 10 years ago
- 2584255 Handle all DSB/DMB/ISB variants. Fixes #340033. by sewardj · 10 years ago
- 5b924c8 Implement PRFM (immediate). Fixes #335713. by sewardj · 10 years ago
- f67fcb9 Implement FCVTAS W_S and FCVTAU W_S. Fixes #340509. by sewardj · 10 years ago
- d0e5e53 Implement by sewardj · 10 years ago
- 31b29af Implement fcvtmu x_d. Fixes #339927. by sewardj · 10 years ago
- d8ad76a Implement frintx d_d and s_s. Fixes #339926. by sewardj · 10 years ago
- bed9f68 * add a missing extra m-reg check for some LD/ST vector cases by sewardj · 10 years ago
- 208a776 Implement SIMD (de)interleaving loads/stores: by sewardj · 10 years ago
- f4f25ff Bug 339858 arm64 recognize dmb sy. Data Memory Barrier full SYstem variant. by mjw · 10 years ago
- 8462d11 Constification part 4. by florian · 10 years ago
- efe536b Handle fcvtpu Xd,Sn. Fixes #335564. by sewardj · 10 years ago
- 7ec7750 arm64: enable support for: str bN, [reg, reg etc] by sewardj · 10 years ago
- 8def049 arm64: route all whole-vector shift/rotate/slice operations by sewardj · 10 years ago
- fc261d9 arm64: implement: {zip,uzp,trn}{1,2} (vector) urecpe, ursqrte (vector) by sewardj · 10 years ago
- f7003bc arm64: implement: suqadd, usqadd (scalar) suqadd, usqadd (vector) by sewardj · 10 years ago
- 62ece66 arm64: implement srhadd, urhadd (vector) by sewardj · 10 years ago
- a6b61f0 arm64: implement by sewardj · 10 years ago
- 1dd3ec1 Rename Iop_QSalN*, Iop_QShlN* and Iop_QShlN*S so as to more accurately by sewardj · 10 years ago
- acc2964 arm64: implement: {uqshl, sqshl, sqshlu} (scalar, imm) and fix two by sewardj · 10 years ago
- a97dddf arm64: implement: {uqshl, sqshl, sqshlu} (vector, imm). by sewardj · 10 years ago
- e741d16 arm64: implement: uqshrn{2}, sqrshrun{2}, sqshrun{2} (scalar, imm) by sewardj · 10 years ago
- 2faf591 Small cleanups in VEX: by philippe · 10 years ago
- ecedd98 arm64: implement: by sewardj · 10 years ago
- 1297218 arm64: add support for: sqshl, uqshl, sqrshl, uqrshl (reg) (vector and scalar) by sewardj · 10 years ago
- 257e99f arm64: implement remaining SQDMULH and SQRDMULH cases. by sewardj · 10 years ago
- 9b76916 Improve infrastructure for dealing with endianness in VEX. This patch by sewardj · 10 years ago
- 54ffa1d arm64: implement: by sewardj · 10 years ago
- 51d012a arm64: implement: sqneg, {u,s}q{add,sub} (scalar), by sewardj · 10 years ago
- 8a5ed54 arm64: implement: LD1/ST1 (multi 1-elem structs, 2 regs, post index) by sewardj · 10 years ago
- 6eb5ef8 arm64: implement "mrs Xt, cntvct_el0" by pass-through to the host. by sewardj · 10 years ago
- 8e91fd4 arm64: implement: {sli,sri} (vector & scalar), sqabs (vector & scalar) by sewardj · 10 years ago
- 487559e arm64: implement: shll #imm, shrn #imm, rshrn #imm, by sewardj · 10 years ago
- a5a6b75 arm64: implement: sadalp uadalp saddlp uaddlp saddlv uaddlv saddw{2} by sewardj · 10 years ago
- a0645d5 arm64: change the representation of FPSR.QC so that it can be by sewardj · 10 years ago
- 6f312d0 arm64: implement: sabal uabal sabdl uabdl saddl uaddl ssubl usubl by sewardj · 10 years ago
- df9d6d5 arm64: by sewardj · 10 years ago
- 715d162 arm64: implement: rbit 16b,8b, rev16 16b,8b by sewardj · 10 years ago
- a8c7b0f The vector versions of the count leading zeros/sign bits primops by sewardj · 10 years ago
- 31b5a95 arm64: implement pmull{2}. by sewardj · 10 years ago
- 168c8bd arm64: implement: by sewardj · 10 years ago
- 39f754d Implement LD1/ST1 {3 regs . 16b}, [ea] (no offset) by sewardj · 10 years ago
- 787a67f arm64: more SIMD instructions: by sewardj · 10 years ago
- ab33a7a Implement: dup_{d_d[], s_s[], h_h[], b_b[]}, ext by sewardj · 10 years ago
- 2b6fd5e Implement: orr_{8h,4h}_imm8_shifted, orr_{4s,2s}_imm8_shifted, by sewardj · 10 years ago
- b9aff1e arm64: implement: addp std7_std7_std7, addv vector, addp d_2d by sewardj · 10 years ago
- 25523c4 arm64: implement: abs d_d, neg d_d, abs std7_std7, addhn, subhn, raddhn, rsubhn by sewardj · 10 years ago
- d96daf6 Remove temporary front end scaffolding for Cat{Even,Odd}Lanes by sewardj · 10 years ago
- 18bf517 Implement LD1R (single structure, replicate). by sewardj · 10 years ago
- 85fbb02 Implement FMUL 2d_2d_d[], 4s_4s_s[], 2s_2s_s[]. by sewardj · 10 years ago
- fc83d2c Remove the old SIMD decoder entirely. by sewardj · 10 years ago
- 5747c4a Move remaining implemented SIMD instructions into the new SIMD/FP by sewardj · 10 years ago
- df1628c Reimplement the SIMD and FP instruction decoder, so as to avoid huge by sewardj · 10 years ago
- dee3050 Support ADC/ADCS/SBC/SBCS. Fixes #335496. (dimitry@google.com) by sewardj · 10 years ago
- ab102bd Support the "ishst" variant of "dmb". Fixes #335263. (dimitry@google.com) by sewardj · 10 years ago
- aec051d Support movi_{16b,8b}_#imm8. Fixes #335262. (dimitry@google.com) by sewardj · 10 years ago
- fda314f Implement SHL_d_d_#imm. by sewardj · 10 years ago
- b355347 Initial front-end fixings needed to handle code generated by gcc-4.9 by sewardj · 10 years ago
- 702054e Handle "blr lr" correctly -- read the destination register by sewardj · 10 years ago
- 7fce7cc Enable 'smulh'. by sewardj · 10 years ago
- 1955143 Allow early-writeback for the cases by sewardj · 10 years ago
- 05f5e01 Renaming only (no functional change): rename IR artefacts to do by sewardj · 10 years ago
- 6590299 ARM64: add support for cache management instructions (VEX side): by sewardj · 10 years ago
- 9301343 Finish off vector integer comparison instructions, and by sewardj · 10 years ago
- bd83e98 {FMOV,MOVI} (vector, immediate): fix incorrect DIP format string by sewardj · 11 years ago
- 950ca7a Implement by sewardj · 11 years ago
- 92d0ae3 Implement TBL and TBX instructions. by sewardj · 11 years ago
- 2bd1ffe Implement FCM{EQ,GE,GT}, FAC{GE,GT} (vector). by sewardj · 11 years ago
- e0bff8b Do early writeback of the base register for the following instruction by sewardj · 11 years ago
- 1eaaec2 Support extra instruction bits and pieces, enough to get Firefox started: by sewardj · 11 years ago
- 5ba4130 Fix error in 64-bit and smaller load versions of by sewardj · 11 years ago
- 32d8675 Implement REV16, REV32, FCVTN, SHL (vector, immediate), NEG (vector) by sewardj · 11 years ago
- 5860ec7 Remove redundant FMOV (vector, immediate) case. by sewardj · 11 years ago
- dc9259c Implement a few more integer instructions: NOP LDA{R,RH,RB} STL{R,RH,RB} RBIT by sewardj · 11 years ago
- d512d10 * add a kludgey fix for "mrs rT, dczid_el0" by sewardj · 11 years ago
- 7d00913 First pass at implementation of load/store exclusive and by sewardj · 11 years ago
- e520bb3 Implement more aarch64 vector insns: by sewardj · 11 years ago
- fab0914 Implement more aarch64 vector insns: by sewardj · 11 years ago
- f5b0891 Implement a few more vector aarch64 insns: by sewardj · 11 years ago
- ecde697 Implement a few more vector aarch64 insns: by sewardj · 11 years ago
- 606c4ba Improve front and back end support for SIMD instructions on Arm64. by sewardj · 11 years ago
- 6068788 arm64: rename guest_SP to guest_XSP so as to avoid a name clash with by sewardj · 11 years ago
- aeeb31d Add missing ULLs to some 64-bit immediates. by sewardj · 11 years ago
- bbcf188 Add support for ARMv8 AArch64 (the 64 bit ARM instruction set): by sewardj · 11 years ago