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gerrit-public.fairphone.software / platform / external / valgrind / ad00ea9f40f930d98bb2d278291a6c4c6636d6d6 / priv / guest_arm_toIR.c
  1. d6d13b3 Implement VFPv4 VFNMA, VFNMS d_d and s_s variants (not that by sewardj · 10 years ago
  2. 8462d11 Constification part 4. by florian · 10 years ago
  3. e6b9bd9 Rename Iop_Extract{64,V128} to Iop_Slice{64,V128}, improve their by sewardj · 10 years ago
  4. 1ddee21 Rename IROps for reciprocal estimate, reciprocal step, reciprocal sqrt by sewardj · 10 years ago
  5. 1dd3ec1 Rename Iop_QSalN*, Iop_QShlN* and Iop_QShlN*S so as to more accurately by sewardj · 10 years ago
  6. 2faf591 Small cleanups in VEX: by philippe · 10 years ago
  7. 9b76916 Improve infrastructure for dealing with endianness in VEX. This patch by sewardj · 10 years ago
  8. 51d012a arm64: implement: sqneg, {u,s}q{add,sub} (scalar), by sewardj · 10 years ago
  9. 7e67bb6 Initialise a couple of scalars that gcc -Og thinks might be by sewardj · 10 years ago
  10. fe1c2aa arm32: support (ARM) PLDW [reg, reg]. The non-W variant was already by sewardj · 10 years ago
  11. 0657e9a arm32: support (ARM) PLDW [reg, #imm]. The non-W variant was already by sewardj · 10 years ago
  12. 3368035 Rename the vector subparts-of-lanes-reversal IROps to names by sewardj · 10 years ago
  13. a8c7b0f The vector versions of the count leading zeros/sign bits primops by sewardj · 10 years ago
  14. a73ab63 Fix bogus-looking assertion. by sewardj · 10 years ago
  15. 7bfbbe9 Implement VFPv4 VFMA and VFMS (F32 and F64 versions). Fixes #331057. by sewardj · 10 years ago
  16. bd11c71 Thumb encoding: fix assertion failure caused by by sewardj · 10 years ago
  17. f36d9af Thumb encoding: correctly deal with misaligned loads of the form by sewardj · 10 years ago
  18. 05f5e01 Renaming only (no functional change): rename IR artefacts to do by sewardj · 10 years ago
  19. 1cf79f7 Bug 332658 - ldrd.w r1, r2, [PC, #imm] does not adjust for 32bit alignment by sewardj · 10 years ago
  20. e84eeb4 Un-break the arm32 compilation pipeline following the change of by sewardj · 10 years ago
  21. 055e93a LDRD/STRD reg+/-#imm8: allow PC as the base register in the by sewardj · 10 years ago
  22. 0a4f4bb Correctly handle add(hi) when the destination register is the PC. Fixes #332037. by sewardj · 10 years ago
  23. 89ae847 Update copyright dates (20XY-2012 ==> 20XY-2013) by sewardj · 11 years ago
  24. 4ccd258 Implement LDRHT (Thumb), LDRSHT (Thumb), [LDR,ST]{S}[B,H]T (ARM). by sewardj · 11 years ago
  25. 3b22fc8 Implement LDRHT (Thumb), LDRSHT (Thumb), [LDR,ST]{S}[B,H]T (ARM). by sewardj · 11 years ago
  26. a325ee1 by sewardj · 11 years ago
  27. 6ed5c34 Add support for by sewardj · 11 years ago
  28. 80f674a Implement STRT. Fixes #319395. (Vasily Golubev, w.golubev@mail.ru) by sewardj · 11 years ago
  29. e660158 Implement SSAT16. Fixes #318929. (Vasily Golubev, w.golubev@mail.ru) by sewardj · 11 years ago
  30. 92001d4 STRD (both ARM and Thumb): for push-like cases -- specifically, STRD by sewardj · 11 years ago
  31. ccff5f4 Implement SMMLA{r}, both ARM and Thumb. n-i-bz. by sewardj · 11 years ago
  32. 0adc2f2 VLD4/VST4: generate in-line interleave/de-interleave code, so that by sewardj · 11 years ago
  33. c1e23c4 VLD3/VST3: generate in-line interleave/de-interleave code, so that by sewardj · 11 years ago
  34. 1df8096 Improved front end translations for Neon V{LD,ST}{1,2} instructions, by sewardj · 11 years ago
  35. de61a39 Remove some unused ifdeffery that allowed disabling QC flag updating for Neon. by sewardj · 11 years ago
  36. 8bde7f1 Implement ARM SDIV and UDIV instructions. Fixes #314178. Partially by sewardj · 11 years ago
  37. 7af7687 Implement (T1) LDRT reg+#imm8. Fixes #315689. (Vasily, w.golubev@mail.ru) by sewardj · 11 years ago
  38. a39fb0c Fix an assertion failure on CVT.F64.S32 d16, d16, #1. Fixes #317186 (I think). by sewardj · 11 years ago
  39. ade5552 Implement VCVT.{S,U}32.F64 D[d], D[d], #frac_bits. Fixes #315738. by sewardj · 11 years ago
  40. 6b7bdec Implement VCVT.F64.{SU}32, #imm. Fixes #308717. by sewardj · 11 years ago
  41. 44db1e7 Implement SMLAL{BB,BT,TB,TT}. Fixes #308718. (Mans Rullgard, mans@mansr.com) by sewardj · 11 years ago
  42. 0ef8d9e Handle WFE and SEV, needed for spinlock hinting. by sewardj · 11 years ago
  43. 99dd03e Infrastructure cleanup part 2. by florian · 11 years ago
  44. 009230b Infrastructure cleanup: change type of the condition field of by sewardj · 11 years ago
  45. c6c7a0d Unreachable default case should vassert. by florian · 12 years ago
  46. cfe046e Merge, from branches/COMEM, revisions 2568 to 2641. by sewardj · 12 years ago
  47. abf3945 Support the UMAAL instruction. (n-i-bz). Based on a patch from by sewardj · 12 years ago
  48. 442e51a Make diagnostics for SIGILL more controllable (VEX part). by sewardj · 12 years ago
  49. 55085f8 Changes for -Wwrite-strings by florian · 12 years ago
  50. 5df8ab0 Fix HChar / UCHar / Char mixups. VEX now compiles without by florian · 12 years ago
  51. 32dd538 Add support for: uqsub16 shadd16 uhsub8 uhsub16. Fixes #304035. by sewardj · 12 years ago
  52. e7e1018 STM<c>.W <Rn>{!},<registers> (Encoding T2): allow the base register to by sewardj · 12 years ago
  53. a0d8eb8 Add ARM front/back end support for IR injection. by sewardj · 12 years ago
  54. 2245ce9 VEX-side support for the V-bit tester. by florian · 12 years ago
  55. 5a34b8b Implement QDADD and QDSUB. Fixes #305199. (Mans Rullgard, mans@mansr.com) by sewardj · 12 years ago
  56. 25e5473 Update copyright dates to include 2012. by sewardj · 12 years ago
  57. 9fe0cc7 Implement VCVT.F32.{S,U}32 S[d], S[d], #frac_bits. Fixes #287175. by sewardj · 12 years ago
  58. 5276ff5 Get rid of gcc warnings about uninitialised variables in the arm front end. by sewardj · 12 years ago
  59. ffd2093 Implement (T1) SMMUL{R}. Fixes #300140. (Evgeniy Stepanov, by sewardj · 12 years ago
  60. 44ce46d ARM: Implement QADD and QSUB. Fixes #286917. by sewardj · 12 years ago
  61. 9de2809 Implement (inexplicably missing) UHADD16. by sewardj · 12 years ago
  62. b0f1df2 16-bit Thumb PUSH and POP: fix incorrect assertions. by sewardj · 12 years ago
  63. c6f970f Add translation chaining support for amd64, x86 and ARM (VEX side). See #296422. by sewardj · 12 years ago
  64. fd5f4a4 For (T3) "ADD (SP plus register)", allow "add rX, SP, rY, lsl by sewardj · 12 years ago
  65. 1331f4d Accept DMB (mcr 15, 0, rT, c7, c10, 5) for any rT <= 14, not just when rT = r0. by sewardj · 12 years ago
  66. 51016d1 Handle "add.w reg, sp, #constT" and "addw reg, sp, #uimm12" for reg != by sewardj · 13 years ago
  67. e6c53e0 Update all copyright dates, from 20xy-2010 to 20xy-2011. by sewardj · 13 years ago
  68. 260abb1 Handle Thumb2 ROR (register) encoding T2. #284472. by sewardj · 13 years ago
  69. f580065 Mark IR level calls and returns derived from ARM and Thumb code by sewardj · 13 years ago
  70. 6d615ba Support ARM and Thumb "CLREX" instructions since Dalvik generates by sewardj · 13 years ago
  71. 2895832 Neon loads/stores: rename some vars, plus the main function, and add by sewardj · 13 years ago
  72. 7f5a841 Add support for Thumb2 encodings of PLD and PLDW. Bug 277653. by sewardj · 13 years ago
  73. f755839 Make VMOV.F32 load the correct value into the destination register. by sewardj · 13 years ago
  74. b706a0f Fix BLX r14 in ARM mode, which was broken due to incorrect sequencing by sewardj · 13 years ago
  75. a561f89 Fix NEON VMUL by float scalar. Bug 277663. (Mans Rullgard, mans@mansr.com) by sewardj · 13 years ago
  76. 3b49554 Tighten up an instruction decoding exception for add.w reg, sp, #constT. by sewardj · 13 years ago
  77. ff7f5b7 Complete the implementation of ARM atomic ops: {LD,ST}REX{,B,H,D} in by sewardj · 13 years ago
  78. dbf3d59 Add support for Thumb ADDW reg, reg, #uimm12 and SUBW ditto. Bug by sewardj · 13 years ago
  79. 66c8c9b Thumb2 front end: improved analysis of IT instructions that might by sewardj · 13 years ago
  80. 5f438dd Rename and rationalise the vector narrowing and widening primops, so by sewardj · 13 years ago
  81. b3a860f Fix jump kind for indirect BLX for Thumb insns. Bug 266035 comment by sewardj · 13 years ago
  82. 5bb6ca2 Support DMB and DSB variants on Thumb. Bug 266035 comment 6. by sewardj · 13 years ago
  83. e407ced Support DMB and DSB variants on ARM. Bug 266035 comment 3. by sewardj · 13 years ago
  84. f6d2cf9 Fix a bogus assertion observed by Florian Krohm. by sewardj · 13 years ago
  85. bb8b394 Improvements to condition code handling on ARM. by sewardj · 13 years ago
  86. 06122e7 Remove dead assignments that gcc-4.6.0 complains about by sewardj · 13 years ago
  87. 15c0104 Handle more cases of SUB (SP minus immediate/register). Also by sewardj · 13 years ago
  88. ed75a68 Handle moves from TPIDRURO to integer registers in Thumb mode. by sewardj · 13 years ago
  89. 4d47547 Get rid of unintended complex integral constant, that causes build by sewardj · 13 years ago
  90. 310d6b2 Add support for SMSAD{X}, SMLSD{X}, USAD{A}8. by sewardj · 14 years ago
  91. 64733c4 Update copyright notices. by sewardj · 14 years ago
  92. 646bc00 Handle NOP.W (Thumb) and NOP (ARM). Partial fix for #253636. by sewardj · 14 years ago
  93. 774b88b Fix bogus register constraints for ARM mode LDREX and STREX. by sewardj · 14 years ago
  94. b0d80ea NEON front end: fix bugs in VMIN, VZIP, VRSHL. by sewardj · 14 years ago
  95. a002def Thumb instructions: instead of generating tons of lardy boilerplate IR by sewardj · 14 years ago
  96. 27312d3 by sewardj · 14 years ago
  97. 04d6da3 Implement (Thumb) ORN (immediate) and ORN (register). Fixes #252326. by sewardj · 14 years ago
  98. 4aec376 Implement v7 barrier insns (DMB, DSB, ISB) in Thumb mode by sewardj · 14 years ago
  99. e1a9396 Implement LDREX and STREX in Thumb mode. Fixes #252258. by sewardj · 14 years ago
  100. 389239a Implement RBIT in ARM mode. by sewardj · 14 years ago