- 752f906 Update copyright dates to 2010 and change license to standard GPL2+. by sewardj · 15 years ago
- 2a0cc85 gen{Spill,Reload}_PPC: track recent change in genSpill/Reload signature. by sewardj · 15 years ago
- cef7d3e by sewardj · 15 years ago[Renamed (98%) from priv/host-ppc/hdefs.h]
- e9d8a26 Merge in branches/DCAS: by sewardj · 15 years ago
- 0f1ef86 Handle frin, frim, frip, friz, in 64-bit mode only, for now. by sewardj · 16 years ago
- 478646f Merge branches/OTRACK_BY_INSTRUMENTATION into the trunk. This by sewardj · 17 years ago
- a26d820 Update copyright dates ("200X-2007" --> "200X-2008"). by sewardj · 17 years ago
- e744153 Update copyright dates. by sewardj · 18 years ago
- dd40fdf by sewardj · 18 years ago
- aca070a Merge r1663-r1666: by sewardj · 18 years ago
- a33e9a4 Update copyright dates. by sewardj · 18 years ago
- 8f07359 Counterpart to r1605: in the ppc insn selector, don't use the bits by sewardj · 19 years ago
- 40c8026 Redo the way FP multiply-accumulate insns are done on ppc32/64. by sewardj · 19 years ago
- b183b85 by sewardj · 19 years ago
- baf971a Handle ppc32/64 fres, frsqrte. by sewardj · 19 years ago
- 7fd5bb0 A bit more backend tidying: by sewardj · 19 years ago
- 92923de by sewardj · 19 years ago
- d0eae2d renamed VEX dirs guest-ppc32/ -> guest-ppc/, host-ppc32/ -> host-ppc/ by cerion · 19 years ago[Renamed (99%) from priv/host-ppc32/hdefs.h]
- 5b2325f Changed naming convention from 'PPC32' to 'PPC' for all VEX code common to both PPC32 and PPC64. by cerion · 19 years ago
- 07b07a9 Implemented almost all of the remaining 64bit-mode insns. by cerion · 19 years ago
- 59b2c31 Fix typos. by cerion · 19 years ago
- bb01b7c Fixed up front and backend for 32bit mul,div,cmp,shift in mode64 by cerion · 19 years ago
- b8a8dba Make suitable changes for ppc32/ppc64 following recent x86/amd64 by sewardj · 19 years ago
- f0de28c Implemented backend for ppc64, sharing ppc32 backend. by cerion · 19 years ago
- 92b6436 Added 'Bool mode64' to the various backend functions, to distinguish 32/64bit arch's. by cerion · 19 years ago
- d963eb4 Implemented most of the remaining altivec fp ops: by cerion · 19 years ago
- 8ea0d3e Frontend by cerion · 19 years ago
- 4a49b03 Frontend: by cerion · 19 years ago
- f34ccc4 spacing and var name chages only by cerion · 19 years ago
- 92d9d87 Added AltiVec permutation insns: - vperm, vsldoi, vmrg*, vsplt* by cerion · 19 years ago
- 27b3d7e more altivec insns: vsr, vspltw - only working with with --tool=none by cerion · 19 years ago
- 225a034 by cerion · 19 years ago
- 6a64a9f On a PPC32Instr_Call, don't merely record how many integer registers by sewardj · 19 years ago
- 7bd6ffe by sewardj · 19 years ago
- dbcfae7 by sewardj · 19 years ago
- b51f0f4 by sewardj · 19 years ago
- a5f957d Fix backend bug: the immediate on PPC32AMode_IR is 16 bits signed, not unsigned. by sewardj · 19 years ago
- 27e1dd6 (API-visible change): generalise the VexSubArch idea. Everywhere by sewardj · 19 years ago
- 91c62fd Fixed coupla altivec typos - hopefully fixes FC4 build by cerion · 19 years ago
- 6b6f59e Reshuffled host-ppc32 AltiVec integer insns Added some AltiVec fp insns and CMov by cerion · 19 years ago
- c3d8bdc PPC32 AltiVec host-end framework & intruction output - no fp yet by cerion · 19 years ago
- 094d139 Floating-point for ppc32 by cerion · 19 years ago
- ed623db guest-ppc32 by cerion · 19 years ago
- a2f7588 Cleanup backend: var name chages like src1,2 -> srcL,R etc by cerion · 20 years ago
- 9e263e3 Cleaned up backend a little by cerion · 20 years ago
- 5e2527e Alu32::SUB was broken in the backend. by cerion · 20 years ago
- 9abfcbc Added a couple of unhandled isel instrs: by cerion · 20 years ago
- 7f000af Added new instruction RdWrLR to read/write link register. by cerion · 20 years ago
- a56e9cc Cleaned up a little more by cerion · 20 years ago
- 7cf8e4e Fixed emit_PPC32Instr::Pin_Goto by cerion · 20 years ago
- 98411db hdefs by cerion · 20 years ago
- 33aa6da More instr emitting: - most 'forms' done - had a go at Pin_Call, Pin_Goto by cerion · 20 years ago
- b85e8bb spacing/comment cleanup only by cerion · 20 years ago
- ab9132d Sorted out the condcode stuff - hopefully correctly... by cerion · 20 years ago
- c0e707e Added Div32 - that's the last for this .orig file! by cerion · 20 years ago
- e13bb31 Added CLZ Fixed Unary32 Added genSpill_PPC32, genReload_PPC32 by cerion · 20 years ago
- 92f5dc7 hdefs: MulL, MFence by cerion · 20 years ago
- b536af9 hdefs: CMov32, Set32 by cerion · 20 years ago
- b4a632a Changed the register setup a little by cerion · 20 years ago
- 2c49e03 A whole bunch more ppc32 backend code - just the isel stuff so far, no assembly by cerion · 20 years ago
- cd30449 A first swing at getting ppc32 backend working. Done: tmp, get, put, load, store by cerion · 20 years ago
- bcf8c3e Get the PPC32 back-end show on the road. by cerion · 20 years ago