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gerrit-public.fairphone.software / platform / external / valgrind / f46114961ae792675c2d123996432a8c5da66069
  1. a219519 More isel cases. by sewardj · 19 years ago
  2. 18e98d4 Some of the ppc32 front end stuff generates huge amounts of IR and by sewardj · 19 years ago
  3. 9053d22 Reenable an ADC variant. by sewardj · 19 years ago
  4. 41c0109 Implement ADC Ib, AL. by sewardj · 19 years ago
  5. a32ad6b Enable RCR tests. by sewardj · 19 years ago
  6. 112b099 An appallingly inefficient, but correct, implementation of rcr. On by sewardj · 19 years ago
  7. 98e9f34 Implement bswapq %reg. Generates pretty verbose code, but it works. by sewardj · 19 years ago
  8. e14bb9f Partially successful effort to get FP working again. by sewardj · 19 years ago
  9. 8a8588d Fix signedness of immediate. by sewardj · 19 years ago
  10. c965953 Reinstate rlwnm and change ROTL32 back to what it looked like before I by sewardj · 19 years ago
  11. 6fa6bf1 Fix XER.OV computation after multiply. by sewardj · 19 years ago
  12. 0e88d8f Fix very stupid bug in my mtxer implementation. The relevant IRStmts by sewardj · 19 years ago
  13. 20ef547 Do all ppc32 flag calculations in-line, partly for performance reasons by sewardj · 19 years ago
  14. bc21094 Implement STC/CLC/CMC, and take the opportunity to make PUSHFL work a by sewardj · 19 years ago
  15. 7a06b85 Implement SBB Ev,Gv. by sewardj · 19 years ago
  16. 6359f81 Implement LOOP disp8 (0xE2). by sewardj · 19 years ago
  17. c8b2635 Implement F3 90 (rep nop). by sewardj · 19 years ago
  18. 005b4ef Specialise NZ after ANDL/ORL/XORL. This fixes #109314. by sewardj · 19 years ago
  19. 3f81c4e Add some specialisation rules which are ultimately helpful in reduce by sewardj · 19 years ago
  20. 22cab06 Make ADC Ev,Gv work. by sewardj · 19 years ago
  21. 109e935 iselCondCode: handle literals. by sewardj · 19 years ago
  22. 68884ef Add a folding rule for 1Sto16. by sewardj · 19 years ago
  23. d45b446 Handle 0 :: Ity_I1 as well as 1 :: Ity_I1. by sewardj · 19 years ago
  24. feacf14 Fix up linking/relocation a bit, and track API changes in r1272. by sewardj · 19 years ago
  25. 5e0274d Track API changes in r1272. by sewardj · 19 years ago
  26. b51f0f4 by sewardj · 19 years ago
  27. 37b71bf Fix build breakage. by sewardj · 19 years ago
  28. 8ea6771 Implement 8-byte-transfer cases for lwsi and stswi. by sewardj · 19 years ago
  29. 900f6b5 Added LibVEX_GuestPPC32_put_cr7(), LibVEX_GuestPPC32_put_cr() by cerion · 19 years ago
  30. 51900a2 Added LibVEX_GuestPPC32_get_cr() for easy access to entire cond reg by cerion · 19 years ago
  31. 0bfc6b6 My life is one endless stream of small things which don't quite work. by sewardj · 19 years ago
  32. c24824a Comment-only-change: record subtle interactions between self-checks by sewardj · 19 years ago
  33. e8aaa87 Fix bits and pieces needed to make self-checking-translations work on amd64. by sewardj · 19 years ago
  34. 16a403b Tidy up some loose ends in the self-checking-translations machinery, by sewardj · 19 years ago
  35. ec3c885 Make LibVEX_Translate (an API fn) take a Bool indicating whether or by sewardj · 19 years ago
  36. db4738a Basic support for self-checking translations. It fits quite neatly by sewardj · 19 years ago
  37. a27cfc4 Keep older versions of gcc (3.0.4) happy. by sewardj · 19 years ago
  38. ab10ac2 ... and fix the fix (oh for clear documentation...) by cerion · 19 years ago
  39. 3182fd4 fixed load-mult-word bad-insn-check bug by cerion · 19 years ago
  40. d797899 What is it with me add and's! by cerion · 19 years ago
  41. b95a3db Bringing back load/store multiple word. *These insns not yet checked* by cerion · 19 years ago
  42. 8253ad3 Implement fcmovu/fcmovnu. gcc-4.0.1 -msse2 -ftree-vectorize generates them. by sewardj · 19 years ago
  43. d4d3dd6 Add some casts. by sewardj · 19 years ago
  44. 7d7f1b6 A further hack to reduce ppc32 reg-alloc costs: don't give the by sewardj · 19 years ago
  45. ee7d228 Fix (well, ameliorate, at least) some lurking performance problems by sewardj · 19 years ago
  46. 6485f25 Fix comment. by sewardj · 19 years ago
  47. 2f52de4 Get rid of endianness assumption in client-request-spotter. by sewardj · 19 years ago
  48. 270def4 Change type of deltas from ULong to Long throughout. Probably pointless. by sewardj · 19 years ago
  49. 52d0491 Change type of deltas from UInt to Int throughout. Probably pointless. by sewardj · 19 years ago
  50. db36c0f Type casting cleanups. by sewardj · 19 years ago
  51. 9e6491a The logic that drove basic block to IR disassembly had been duplicated by sewardj · 19 years ago
  52. a5f957d Fix backend bug: the immediate on PPC32AMode_IR is 16 bits signed, not unsigned. by sewardj · 19 years ago
  53. a50fde5 Implemented altivec load: lvx - xfontsel runs now (tool=none) by cerion · 19 years ago
  54. 807d0eb Cleaned up read/write register functions, wrt XER, and fixed a bug for write to VSCR. by cerion · 19 years ago
  55. bddbae6 Fixed a couple of bugs relating to condition register reading/writing, and conditional register logic by cerion · 19 years ago
  56. b66dfa3 comment-only change: renumber register offsets correctly by cerion · 19 years ago
  57. 2325699 Yet Another Folding Rule (YAFR) (tm) by sewardj · 19 years ago
  58. 151ba33 Track recent API change (introduction of VexArchInfo). by sewardj · 19 years ago
  59. af1ceca Enhance IR so as to distinguish between little- and big-endian loads and by sewardj · 19 years ago
  60. f486035 deltaIRStmt: handle IRStmt_MFence. by sewardj · 19 years ago
  61. 02ef716 Fix pointer-type mismatches. by sewardj · 19 years ago
  62. 2c039c9 Comment wibble by sewardj · 19 years ago
  63. e523a4b Fill in guest_ppc32_state_requires_precise_mem_exns() properly, so Vex by sewardj · 19 years ago
  64. d94b73a Connect up the plumbing which allows the ppc32 front end to know the by sewardj · 19 years ago
  65. 27e1dd6 (API-visible change): generalise the VexSubArch idea. Everywhere by sewardj · 19 years ago
  66. 0171310 We have more than 59 allocateable regs now (duh) by cerion · 19 years ago
  67. 6587f2f some more isel cases: v128,f32 by cerion · 19 years ago
  68. 336246a Fixed bug in doHelperCall, passing LONG_LONG params by cerion · 19 years ago
  69. 91c62fd Fixed coupla altivec typos - hopefully fixes FC4 build by cerion · 19 years ago
  70. e21595a Implemented just enough of isel for an AltiVec store - ls runs on g5 now, yay! by cerion · 19 years ago
  71. 6b6f59e Reshuffled host-ppc32 AltiVec integer insns Added some AltiVec fp insns and CMov by cerion · 19 years ago
  72. c3d8bdc PPC32 AltiVec host-end framework & intruction output - no fp yet by cerion · 19 years ago
  73. 6529aff PPC32 AltiVec reg offsets by cerion · 19 years ago
  74. a982c05 AltiVec insn parsing for guest end. by cerion · 19 years ago
  75. 6b30d85 fixed sign-extension bug for branches by cerion · 19 years ago
  76. a60e790 Disable i-am-kludged messages in the cache control insns. by sewardj · 19 years ago
  77. ee1357d Disable dangerous case in advance4 which is not currently needed. by sewardj · 19 years ago
  78. 84ad616 Added isel Ist_Tmp:Ity_I64, iselInt64Expr::Iex_Get by cerion · 19 years ago
  79. 82ea0d9 ... and write 64bit vals the right way around... by cerion · 19 years ago
  80. 02d0cb3 Added to insn selector: CmpNEZ8, Ist_Put::Ity_I64 by cerion · 19 years ago
  81. 9762bbf Fix ppc32 'Call' bug by cerion · 19 years ago
  82. ec93f98 amd64 back end: handle 8Uto32. by sewardj · 19 years ago
  83. 0fe6b7e comment wibble by cerion · 19 years ago
  84. 000a133 this one was x86 code. grr. by cerion · 19 years ago
  85. 80d326d more ppc32 .orig files by cerion · 19 years ago
  86. 094d139 Floating-point for ppc32 by cerion · 19 years ago
  87. ed623db guest-ppc32 by cerion · 19 years ago
  88. 7a41dd0 fix 'Usage:' by cerion · 19 years ago
  89. 81d72ea icc police strike again by sewardj · 19 years ago
  90. 328b54b Make iropt not complain about missing folding rules at the default by sewardj · 19 years ago
  91. 46813fc The guest-state effect declaration for x86 'fldenv' has been wrong for by sewardj · 19 years ago
  92. 4017a3b Implement fldenv/fstenv on amd64. by sewardj · 19 years ago
  93. 446d267 amd64: handle MOVUPS G to E by sewardj · 19 years ago
  94. 10ca4eb Apparently someone somewhere in some obscure library deep in the by sewardj · 19 years ago
  95. 4e1a1e9 Handle fnclex, needed by g95. by sewardj · 19 years ago
  96. 2716ff1 Add a folding rule for 1Uto64. by sewardj · 19 years ago
  97. 1bf9598 Handle XCHG Gb,Eb. by sewardj · 19 years ago
  98. 2d4fcd5 Handle XCHG rAX, reg for 32-bit regs as well as 64-bit regs. I'm not by sewardj · 19 years ago
  99. 8eb804f Handle XOR Ib, AL. by sewardj · 19 years ago
  100. 94a48b2 Fix behaviour of MOVQ on amd64. by sewardj · 19 years ago