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gerrit-public.fairphone.software / platform / external / valgrind / fc261d9dee8af161e24d6f7774dffc311f3e6737
  1. fc261d9 arm64: implement: {zip,uzp,trn}{1,2} (vector) urecpe, ursqrte (vector) by sewardj · 10 years ago
  2. 1ddee21 Rename IROps for reciprocal estimate, reciprocal step, reciprocal sqrt by sewardj · 10 years ago
  3. e3fa0f8 Bug 330319 - vex amd64->IR: unhandled instruction bytes: 0xF 0x1 0xD5 (xend) by mjw · 10 years ago
  4. 150794d putGST_masked: correctly handle the case where the mask is for by sewardj · 10 years ago
  5. f7003bc arm64: implement: suqadd, usqadd (scalar) suqadd, usqadd (vector) by sewardj · 10 years ago
  6. 62ece66 arm64: implement srhadd, urhadd (vector) by sewardj · 10 years ago
  7. a6b61f0 arm64: implement by sewardj · 10 years ago
  8. 4a85b8e No functional change. Remove commented out code copied from the by sewardj · 10 years ago
  9. 1dd3ec1 Rename Iop_QSalN*, Iop_QShlN* and Iop_QShlN*S so as to more accurately by sewardj · 10 years ago
  10. acc2964 arm64: implement: {uqshl, sqshl, sqshlu} (scalar, imm) and fix two by sewardj · 10 years ago
  11. a97dddf arm64: implement: {uqshl, sqshl, sqshlu} (vector, imm). by sewardj · 10 years ago
  12. fbe569d Add a simple folding rule for Iop_ZeroHI64ofV128. by sewardj · 10 years ago
  13. e741d16 arm64: implement: uqshrn{2}, sqrshrun{2}, sqshrun{2} (scalar, imm) by sewardj · 10 years ago
  14. 2faf591 Small cleanups in VEX: by philippe · 10 years ago
  15. ecedd98 arm64: implement: by sewardj · 10 years ago
  16. 0caa0c0 Add a new folding rule: by sewardj · 10 years ago
  17. 99af243 Unbreak the build by philippe · 10 years ago
  18. 94e2de3 This commit is for Bugzilla 334834. by carll · 10 years ago
  19. 1f5fe1f This commit is for Bugzilla 334834. The Bugzilla contains patch 2 of 3 by carll · 10 years ago
  20. 1297218 arm64: add support for: sqshl, uqshl, sqrshl, uqrshl (reg) (vector and scalar) by sewardj · 10 years ago
  21. b01ff40 Add a folding rule: XorV128(t,0) ==> t. by sewardj · 10 years ago
  22. 257e99f arm64: implement remaining SQDMULH and SQRDMULH cases. by sewardj · 10 years ago
  23. 9b76916 Improve infrastructure for dealing with endianness in VEX. This patch by sewardj · 10 years ago
  24. 54ffa1d arm64: implement: by sewardj · 10 years ago
  25. f3eaabd Comment-only change. by sewardj · 10 years ago
  26. 51d012a arm64: implement: sqneg, {u,s}q{add,sub} (scalar), by sewardj · 10 years ago
  27. 7e67bb6 Initialise a couple of scalars that gcc -Og thinks might be by sewardj · 10 years ago
  28. 2782d21 Add a few more algebraic optimisations for Iop_And8/16. Observed on s390. by florian · 10 years ago
  29. d1526f2 Remove fields from VexAbiInfo that only had relevance to the old AIX5 by sewardj · 10 years ago
  30. 40226d1 Comment out an unsed function to avoid a compiler warning. by florian · 10 years ago
  31. 1b7c471 Fix algebraic simplification for Iop_AndV256. by florian · 10 years ago
  32. 8a5ed54 arm64: implement: LD1/ST1 (multi 1-elem structs, 2 regs, post index) by sewardj · 10 years ago
  33. 6eb5ef8 arm64: implement "mrs Xt, cntvct_el0" by pass-through to the host. by sewardj · 10 years ago
  34. 8e91fd4 arm64: implement: {sli,sri} (vector & scalar), sqabs (vector & scalar) by sewardj · 10 years ago
  35. 487559e arm64: implement: shll #imm, shrn #imm, rshrn #imm, by sewardj · 10 years ago
  36. fe1c2aa arm32: support (ARM) PLDW [reg, reg]. The non-W variant was already by sewardj · 10 years ago
  37. 0657e9a arm32: support (ARM) PLDW [reg, #imm]. The non-W variant was already by sewardj · 10 years ago
  38. a5a6b75 arm64: implement: sadalp uadalp saddlp uaddlp saddlv uaddlv saddw{2} by sewardj · 10 years ago
  39. a0645d5 arm64: change the representation of FPSR.QC so that it can be by sewardj · 10 years ago
  40. 6f312d0 arm64: implement: sabal uabal sabdl uabdl saddl uaddl ssubl usubl by sewardj · 10 years ago
  41. df9d6d5 arm64: by sewardj · 10 years ago
  42. 715d162 arm64: implement: rbit 16b,8b, rev16 16b,8b by sewardj · 10 years ago
  43. 3368035 Rename the vector subparts-of-lanes-reversal IROps to names by sewardj · 10 years ago
  44. a8c7b0f The vector versions of the count leading zeros/sign bits primops by sewardj · 10 years ago
  45. 31b5a95 arm64: implement pmull{2}. by sewardj · 10 years ago
  46. 168c8bd arm64: implement: by sewardj · 10 years ago
  47. 633d9db Remove commented out junk which is never going to get used. by sewardj · 10 years ago
  48. a73ab63 Fix bogus-looking assertion. by sewardj · 10 years ago
  49. 39f754d Implement LD1/ST1 {3 regs . 16b}, [ea] (no offset) by sewardj · 10 years ago
  50. 787a67f arm64: more SIMD instructions: by sewardj · 10 years ago
  51. c4fa725 Fix an enum type confusion, PPCAvFpOp vs PPCAvOp, as excellently by sewardj · 10 years ago
  52. 76ac476 Increase the number of vector registers available for allocation from 3 to 5. by sewardj · 10 years ago
  53. ab33a7a Implement: dup_{d_d[], s_s[], h_h[], b_b[]}, ext by sewardj · 10 years ago
  54. 2b6fd5e Implement: orr_{8h,4h}_imm8_shifted, orr_{4s,2s}_imm8_shifted, by sewardj · 10 years ago
  55. b9aff1e arm64: implement: addp std7_std7_std7, addv vector, addp d_2d by sewardj · 10 years ago
  56. 25523c4 arm64: implement: abs d_d, neg d_d, abs std7_std7, addhn, subhn, raddhn, rsubhn by sewardj · 10 years ago
  57. d96daf6 Remove temporary front end scaffolding for Cat{Even,Odd}Lanes by sewardj · 10 years ago
  58. 18bf517 Implement LD1R (single structure, replicate). by sewardj · 10 years ago
  59. 85fbb02 Implement FMUL 2d_2d_d[], 4s_4s_s[], 2s_2s_s[]. by sewardj · 10 years ago
  60. fc83d2c Remove the old SIMD decoder entirely. by sewardj · 10 years ago
  61. 5747c4a Move remaining implemented SIMD instructions into the new SIMD/FP by sewardj · 10 years ago
  62. df1628c Reimplement the SIMD and FP instruction decoder, so as to avoid huge by sewardj · 10 years ago
  63. d3194d1 mips: Fix non mips compiler warning. by dejanj · 10 years ago
  64. dee3050 Support ADC/ADCS/SBC/SBCS. Fixes #335496. (dimitry@google.com) by sewardj · 10 years ago
  65. ab102bd Support the "ishst" variant of "dmb". Fixes #335263. (dimitry@google.com) by sewardj · 10 years ago
  66. aec051d Support movi_{16b,8b}_#imm8. Fixes #335262. (dimitry@google.com) by sewardj · 10 years ago
  67. 6ced72b mips64: Support for Cavium MIPS Octeon Atomic and Count Instructions. by dejanj · 10 years ago
  68. eead319 Implement PCMPxSTRx cases 0x0E, 0x34, 0x14, and reformat some of the by sewardj · 10 years ago
  69. fda314f Implement SHL_d_d_#imm. by sewardj · 10 years ago
  70. b355347 Initial front-end fixings needed to handle code generated by gcc-4.9 by sewardj · 10 years ago
  71. 7bfbbe9 Implement VFPv4 VFMA and VFMS (F32 and F64 versions). Fixes #331057. by sewardj · 10 years ago
  72. bd11c71 Thumb encoding: fix assertion failure caused by by sewardj · 10 years ago
  73. f36d9af Thumb encoding: correctly deal with misaligned loads of the form by sewardj · 10 years ago
  74. 67ac3fd Recognize MPX instructions and bnd prefix. Bug #333666. by mjw · 10 years ago
  75. 702054e Handle "blr lr" correctly -- read the destination register by sewardj · 10 years ago
  76. 7fce7cc Enable 'smulh'. by sewardj · 10 years ago
  77. ac0c92b Handle IRStmt::STle of type F32. by sewardj · 10 years ago
  78. 1955143 Allow early-writeback for the cases by sewardj · 10 years ago
  79. 20a760e Fix assertion failures resulting from change of arity of by sewardj · 10 years ago
  80. 05f5e01 Renaming only (no functional change): rename IR artefacts to do by sewardj · 10 years ago
  81. 6590299 ARM64: add support for cache management instructions (VEX side): by sewardj · 10 years ago
  82. e9c51c9 x87 instructions FSIN, FCOS, FSINCOS and FPTAN: handle out-of-range by sewardj · 10 years ago
  83. 9301343 Finish off vector integer comparison instructions, and by sewardj · 10 years ago
  84. 5d38425 Handle Iop_Max32U, so as to make origin tracking in Memcheck work. by sewardj · 10 years ago
  85. bd83e98 {FMOV,MOVI} (vector, immediate): fix incorrect DIP format string by sewardj · 10 years ago
  86. 950ca7a Implement by sewardj · 10 years ago
  87. 92d0ae3 Implement TBL and TBX instructions. by sewardj · 10 years ago
  88. 36a911a Add a couple more constant folding rules for vectors. by sewardj · 10 years ago
  89. 1cf79f7 Bug 332658 - ldrd.w r1, r2, [PC, #imm] does not adjust for 32bit alignment by sewardj · 10 years ago
  90. 2bd1ffe Implement FCM{EQ,GE,GT}, FAC{GE,GT} (vector). by sewardj · 10 years ago
  91. 14360e9 mips32: Avoid compiler warnings. by dejanj · 10 years ago
  92. e84eeb4 Un-break the arm32 compilation pipeline following the change of by sewardj · 10 years ago
  93. 055e93a LDRD/STRD reg+/-#imm8: allow PC as the base register in the by sewardj · 10 years ago
  94. 0a4f4bb Correctly handle add(hi) when the destination register is the PC. Fixes #332037. by sewardj · 10 years ago
  95. 505a27d Back-end handling of Iop_CmpNEZ32x4, Iop_CmpNEZ16x8, Iop_CmpNEZ8x16, by sewardj · 10 years ago
  96. 99c1f81 Implement a couple of backend artefacts needed by Memcheck on large by sewardj · 10 years ago
  97. e0bff8b Do early writeback of the base register for the following instruction by sewardj · 10 years ago
  98. f21a6ca * iselIntExpr_AMode_wrk: generate correct code for the case by sewardj · 10 years ago
  99. 1eaaec2 Support extra instruction bits and pieces, enough to get Firefox started: by sewardj · 10 years ago
  100. b176a6f mips32: Fix the problem with reading the guest_FCSR register from the wrong guest state. by dejanj · 10 years ago