| armvixl | 5289c59 | 2015-03-02 13:52:04 +0000 | [diff] [blame] | 1 | // Copyright 2015, ARM Limited |
| 2 | // All rights reserved. |
| 3 | // |
| 4 | // Redistribution and use in source and binary forms, with or without |
| 5 | // modification, are permitted provided that the following conditions are met: |
| 6 | // |
| 7 | // * Redistributions of source code must retain the above copyright notice, |
| 8 | // this list of conditions and the following disclaimer. |
| 9 | // * Redistributions in binary form must reproduce the above copyright notice, |
| 10 | // this list of conditions and the following disclaimer in the documentation |
| 11 | // and/or other materials provided with the distribution. |
| 12 | // * Neither the name of ARM Limited nor the names of its contributors may be |
| 13 | // used to endorse or promote products derived from this software without |
| 14 | // specific prior written permission. |
| 15 | // |
| 16 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND |
| 17 | // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 18 | // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 19 | // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE |
| 20 | // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 21 | // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 22 | // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| 23 | // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 24 | // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 25 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | |
| 27 | |
| 28 | // --------------------------------------------------------------------- |
| 29 | // This file is auto generated using tools/generate_simulator_traces.py. |
| 30 | // |
| 31 | // PLEASE DO NOT EDIT. |
| 32 | // --------------------------------------------------------------------- |
| 33 | |
| 34 | #ifndef VIXL_SIM_FMINP_S_TRACE_A64_H_ |
| 35 | #define VIXL_SIM_FMINP_S_TRACE_A64_H_ |
| 36 | |
| 37 | const uint32_t kExpected_NEON_fminp_S[] = { |
| 38 | 0x807fffff, |
| 39 | 0x807fffff, |
| 40 | 0x80000001, |
| 41 | 0x00000000, |
| 42 | 0x00800000, |
| 43 | 0x3effffff, |
| 44 | 0x3f000000, |
| 45 | 0x3f000001, |
| 46 | 0x3f7fffff, |
| 47 | 0x3f800000, |
| 48 | 0x3f800001, |
| 49 | 0x3fc00000, |
| 50 | 0x7fcfffff, |
| 51 | 0x7fcfffff, |
| 52 | 0x7fd23456, |
| 53 | 0x7fd23456, |
| 54 | 0x7fd23456, |
| 55 | 0x7fd23456, |
| 56 | 0x7fc00001, |
| 57 | 0x00123456, |
| 58 | 0x00000001, |
| 59 | 0x80000000, |
| 60 | 0x80800000, |
| 61 | 0xbeffffff, |
| 62 | 0xbf000000, |
| 63 | 0xbf000001, |
| 64 | 0xbf7fffff, |
| 65 | 0xbf800000, |
| 66 | 0xbf800001, |
| 67 | 0xbfc00000, |
| 68 | 0xc1200000, |
| 69 | 0xffcfffff, |
| 70 | 0xffcfffff, |
| 71 | 0xffd23456, |
| 72 | 0xffd23456, |
| 73 | 0xffd23456, |
| 74 | 0xffd23456, |
| 75 | 0xffc00001, |
| 76 | }; |
| 77 | const unsigned kExpectedCount_NEON_fminp_S = 38; |
| 78 | |
| 79 | #endif // VIXL_SIM_FMINP_S_TRACE_A64_H_ |