| #ifndef GEN_MI_XML |
| #define GEN_MI_XML |
| |
| /* Autogenerated file, DO NOT EDIT manually! |
| |
| This file was generated by the rules-ng-ng headergen tool in this git repository: |
| https://github.com/olvaffe/envytools/ |
| git clone https://github.com/olvaffe/envytools.git |
| |
| Copyright (C) 2014 by the following authors: |
| - Chia-I Wu <olvaffe@gmail.com> (olv) |
| |
| Permission is hereby granted, free of charge, to any person obtaining |
| a copy of this software and associated documentation files (the |
| "Software"), to deal in the Software without restriction, including |
| without limitation the rights to use, copy, modify, merge, publish, |
| distribute, sublicense, and/or sell copies of the Software, and to |
| permit persons to whom the Software is furnished to do so, subject to |
| the following conditions: |
| |
| The above copyright notice and this permission notice (including the |
| next paragraph) shall be included in all copies or substantial |
| portions of the Software. |
| |
| THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| |
| #define GEN6_MI_TYPE__MASK 0xe0000000 |
| #define GEN6_MI_TYPE__SHIFT 29 |
| #define GEN6_MI_TYPE_MI (0x0 << 29) |
| #define GEN6_MI_OPCODE__MASK 0x1f800000 |
| #define GEN6_MI_OPCODE__SHIFT 23 |
| #define GEN6_MI_OPCODE_MI_NOOP (0x0 << 23) |
| #define GEN6_MI_OPCODE_MI_BATCH_BUFFER_END (0xa << 23) |
| #define GEN6_MI_OPCODE_MI_STORE_DATA_IMM (0x20 << 23) |
| #define GEN6_MI_OPCODE_MI_LOAD_REGISTER_IMM (0x22 << 23) |
| #define GEN6_MI_OPCODE_MI_STORE_REGISTER_MEM (0x24 << 23) |
| #define GEN6_MI_OPCODE_MI_FLUSH_DW (0x26 << 23) |
| #define GEN6_MI_OPCODE_MI_REPORT_PERF_COUNT (0x28 << 23) |
| #define GEN7_MI_OPCODE_MI_LOAD_REGISTER_MEM (0x29 << 23) |
| #define GEN6_MI_OPCODE_MI_BATCH_BUFFER_START (0x31 << 23) |
| #define GEN6_MI_LENGTH__MASK 0x0000003f |
| #define GEN6_MI_LENGTH__SHIFT 0 |
| #define GEN6_MI_NOOP__SIZE 1 |
| |
| #define GEN6_MI_BATCH_BUFFER_END__SIZE 1 |
| |
| #define GEN6_MI_STORE_DATA_IMM__SIZE 5 |
| #define GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT (0x1 << 22) |
| |
| #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__MASK 0xfffffffc |
| #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHIFT 2 |
| #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHR 2 |
| |
| |
| #define GEN6_MI_LOAD_REGISTER_IMM__SIZE 3 |
| #define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__MASK 0x00000f00 |
| #define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__SHIFT 8 |
| |
| #define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__MASK 0x007ffffc |
| #define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHIFT 2 |
| #define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHR 2 |
| |
| |
| #define GEN6_MI_STORE_REGISTER_MEM__SIZE 3 |
| #define GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT (0x1 << 22) |
| #define GEN75_MI_STORE_REGISTER_MEM_DW0_PREDICATE_ENABLE (0x1 << 21) |
| |
| #define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__MASK 0x007ffffc |
| #define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__SHIFT 2 |
| #define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__SHR 2 |
| |
| #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__MASK 0xfffffffc |
| #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHIFT 2 |
| #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHR 2 |
| |
| #define GEN6_MI_FLUSH_DW__SIZE 4 |
| |
| #define GEN6_MI_REPORT_PERF_COUNT__SIZE 3 |
| |
| #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__MASK 0xffffffc0 |
| #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHIFT 6 |
| #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHR 6 |
| #define GEN6_MI_REPORT_PERF_COUNT_DW1_CORE_MODE_ENABLE (0x1 << 4) |
| #define GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT (0x1 << 0) |
| |
| |
| #define GEN7_MI_LOAD_REGISTER_MEM__SIZE 3 |
| #define GEN7_MI_LOAD_REGISTER_MEM_DW0_USE_GGTT (0x1 << 22) |
| #define GEN7_MI_LOAD_REGISTER_MEM_DW0_ASYNC_MODE_ENABLE (0x1 << 21) |
| |
| #define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__MASK 0x007ffffc |
| #define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__SHIFT 2 |
| #define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__SHR 2 |
| |
| #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__MASK 0xfffffffc |
| #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHIFT 2 |
| #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHR 2 |
| |
| #define GEN6_MI_BATCH_BUFFER_START__SIZE 2 |
| #define GEN75_MI_BATCH_BUFFER_START_DW0_SECOND_LEVEL (0x1 << 22) |
| #define GEN75_MI_BATCH_BUFFER_START_DW0_ADD_OFFSET_ENABLE (0x1 << 16) |
| #define GEN75_MI_BATCH_BUFFER_START_DW0_PREDICATION_ENABLE (0x1 << 15) |
| #define GEN75_MI_BATCH_BUFFER_START_DW0_NON_PRIVILEGED (0x1 << 13) |
| #define GEN6_MI_BATCH_BUFFER_START_DW0_CLEAR_COMMAND_BUFFER (0x1 << 11) |
| #define GEN6_MI_BATCH_BUFFER_START_DW0_USE_PPGTT (0x1 << 8) |
| |
| #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__MASK 0xfffffffc |
| #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHIFT 2 |
| #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHR 2 |
| |
| |
| #endif /* GEN_MI_XML */ |