blob: fe67fa6a84fbdbdaeda17f34909c6440630eea3e [file] [log] [blame]
/*
* Vulkan
*
* Copyright (C) 2014 LunarG, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Authors:
* Chia-I Wu <olv@lunarg.com>
*/
#include "genhw/genhw.h"
#include "kmd/winsys.h"
#include "cmd.h"
#include "dev.h"
#include "fence.h"
#include "queue.h"
static void queue_submit_hang(struct intel_queue *queue,
struct intel_cmd *cmd,
uint32_t active_lost,
uint32_t pending_lost)
{
intel_cmd_decode(cmd, true);
intel_dev_log(queue->dev, VK_DBG_MSG_ERROR,
VK_VALIDATION_LEVEL_0, VK_NULL_HANDLE, 0, 0,
"GPU hanged with %d/%d active/pending command buffers lost",
active_lost, pending_lost);
}
static VK_RESULT queue_submit_bo(struct intel_queue *queue,
struct intel_bo *bo,
VK_GPU_SIZE used)
{
struct intel_winsys *winsys = queue->dev->winsys;
int err;
if (intel_debug & INTEL_DEBUG_NOHW)
err = 0;
else
err = intel_winsys_submit_bo(winsys, queue->ring, bo, used, 0);
return (err) ? VK_ERROR_UNKNOWN : VK_SUCCESS;
}
static struct intel_bo *queue_create_bo(struct intel_queue *queue,
VK_GPU_SIZE size,
const void *cmd,
size_t cmd_len)
{
struct intel_bo *bo;
void *ptr;
bo = intel_winsys_alloc_bo(queue->dev->winsys,
"queue bo", size, true);
if (!bo)
return NULL;
if (!cmd_len)
return bo;
ptr = intel_bo_map(bo, true);
if (!ptr) {
intel_bo_unref(bo);
return NULL;
}
memcpy(ptr, cmd, cmd_len);
intel_bo_unmap(bo);
return bo;
}
static VK_RESULT queue_select_pipeline(struct intel_queue *queue,
int pipeline_select)
{
uint32_t pipeline_select_cmd[] = {
GEN6_RENDER_CMD(SINGLE_DW, PIPELINE_SELECT),
GEN6_MI_CMD(MI_BATCH_BUFFER_END),
};
struct intel_bo *bo;
VK_RESULT ret;
if (queue->ring != INTEL_RING_RENDER ||
queue->last_pipeline_select == pipeline_select)
return VK_SUCCESS;
switch (pipeline_select) {
case GEN6_PIPELINE_SELECT_DW0_SELECT_3D:
bo = queue->select_graphics_bo;
break;
case GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA:
bo = queue->select_compute_bo;
break;
default:
return VK_ERROR_INVALID_VALUE;
break;
}
if (!bo) {
pipeline_select_cmd[0] |= pipeline_select;
bo = queue_create_bo(queue, sizeof(pipeline_select_cmd),
pipeline_select_cmd, sizeof(pipeline_select_cmd));
if (!bo)
return VK_ERROR_OUT_OF_GPU_MEMORY;
switch (pipeline_select) {
case GEN6_PIPELINE_SELECT_DW0_SELECT_3D:
queue->select_graphics_bo = bo;
break;
case GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA:
queue->select_compute_bo = bo;
break;
default:
break;
}
}
ret = queue_submit_bo(queue, bo, sizeof(pipeline_select_cmd));
if (ret == VK_SUCCESS)
queue->last_pipeline_select = pipeline_select;
return ret;
}
static VK_RESULT queue_init_hw_and_atomic_bo(struct intel_queue *queue)
{
const uint32_t ctx_init_cmd[] = {
/* STATE_SIP */
GEN6_RENDER_CMD(COMMON, STATE_SIP),
0,
/* PIPELINE_SELECT */
GEN6_RENDER_CMD(SINGLE_DW, PIPELINE_SELECT) |
GEN6_PIPELINE_SELECT_DW0_SELECT_3D,
/* 3DSTATE_VF_STATISTICS */
GEN6_RENDER_CMD(SINGLE_DW, 3DSTATE_VF_STATISTICS),
/* end */
GEN6_MI_CMD(MI_BATCH_BUFFER_END),
GEN6_MI_CMD(MI_NOOP),
};
struct intel_bo *bo;
VK_RESULT ret;
if (queue->ring != INTEL_RING_RENDER) {
queue->last_pipeline_select = -1;
queue->atomic_bo = queue_create_bo(queue,
sizeof(uint32_t) * INTEL_QUEUE_ATOMIC_COUNTER_COUNT,
NULL, 0);
return (queue->atomic_bo) ? VK_SUCCESS : VK_ERROR_OUT_OF_GPU_MEMORY;
}
bo = queue_create_bo(queue,
sizeof(uint32_t) * INTEL_QUEUE_ATOMIC_COUNTER_COUNT,
ctx_init_cmd, sizeof(ctx_init_cmd));
if (!bo)
return VK_ERROR_OUT_OF_GPU_MEMORY;
ret = queue_submit_bo(queue, bo, sizeof(ctx_init_cmd));
if (ret != VK_SUCCESS) {
intel_bo_unref(bo);
return ret;
}
queue->last_pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
/* reuse */
queue->atomic_bo = bo;
return VK_SUCCESS;
}
static VK_RESULT queue_submit_cmd_prepare(struct intel_queue *queue,
struct intel_cmd *cmd)
{
if (unlikely(cmd->result != VK_SUCCESS)) {
intel_dev_log(cmd->dev, VK_DBG_MSG_ERROR,
VK_VALIDATION_LEVEL_0, VK_NULL_HANDLE, 0, 0,
"invalid command buffer submitted");
return cmd->result;
}
return queue_select_pipeline(queue, cmd->pipeline_select);
}
static VK_RESULT queue_submit_cmd_debug(struct intel_queue *queue,
struct intel_cmd *cmd)
{
uint32_t active[2], pending[2];
struct intel_bo *bo;
VK_GPU_SIZE used;
VK_RESULT ret;
ret = queue_submit_cmd_prepare(queue, cmd);
if (ret != VK_SUCCESS)
return ret;
if (intel_debug & INTEL_DEBUG_HANG) {
intel_winsys_get_reset_stats(queue->dev->winsys,
&active[0], &pending[0]);
}
bo = intel_cmd_get_batch(cmd, &used);
ret = queue_submit_bo(queue, bo, used);
if (ret != VK_SUCCESS)
return ret;
if (intel_debug & INTEL_DEBUG_HANG) {
intel_bo_wait(bo, -1);
intel_winsys_get_reset_stats(queue->dev->winsys,
&active[1], &pending[1]);
if (active[0] != active[1] || pending[0] != pending[1]) {
queue_submit_hang(queue, cmd, active[1] - active[0],
pending[1] - pending[0]);
}
}
if (intel_debug & INTEL_DEBUG_BATCH)
intel_cmd_decode(cmd, false);
return VK_SUCCESS;
}
static VK_RESULT queue_submit_cmd(struct intel_queue *queue,
struct intel_cmd *cmd)
{
struct intel_bo *bo;
VK_GPU_SIZE used;
VK_RESULT ret;
ret = queue_submit_cmd_prepare(queue, cmd);
if (ret == VK_SUCCESS) {
bo = intel_cmd_get_batch(cmd, &used);
ret = queue_submit_bo(queue, bo, used);
}
return ret;
}
VK_RESULT intel_queue_create(struct intel_dev *dev,
enum intel_gpu_engine_type engine,
struct intel_queue **queue_ret)
{
struct intel_queue *queue;
enum intel_ring_type ring;
VK_FENCE_CREATE_INFO fence_info;
VK_RESULT ret;
switch (engine) {
case INTEL_GPU_ENGINE_3D:
ring = INTEL_RING_RENDER;
break;
default:
return VK_ERROR_INVALID_VALUE;
break;
}
queue = (struct intel_queue *) intel_base_create(&dev->base.handle,
sizeof(*queue), dev->base.dbg, VK_DBG_OBJECT_QUEUE, NULL, 0);
if (!queue)
return VK_ERROR_OUT_OF_MEMORY;
queue->dev = dev;
queue->ring = ring;
if (queue_init_hw_and_atomic_bo(queue) != VK_SUCCESS) {
intel_queue_destroy(queue);
return VK_ERROR_INITIALIZATION_FAILED;
}
memset(&fence_info, 0, sizeof(fence_info));
fence_info.sType = VK_STRUCTURE_TYPE_FENCE_CREATE_INFO;
ret = intel_fence_create(dev, &fence_info, &queue->fence);
if (ret != VK_SUCCESS) {
intel_queue_destroy(queue);
return ret;
}
*queue_ret = queue;
return VK_SUCCESS;
}
void intel_queue_destroy(struct intel_queue *queue)
{
if (queue->fence)
intel_fence_destroy(queue->fence);
intel_bo_unref(queue->atomic_bo);
intel_bo_unref(queue->select_graphics_bo);
intel_bo_unref(queue->select_compute_bo);
intel_base_destroy(&queue->base);
}
VK_RESULT intel_queue_wait(struct intel_queue *queue, int64_t timeout)
{
/* return VK_SUCCESS instead of VK_ERROR_UNAVAILABLE */
if (!queue->fence->seqno_bo)
return VK_SUCCESS;
return intel_fence_wait(queue->fence, timeout);
}
ICD_EXPORT VK_RESULT VKAPI vkQueueAddMemReference(
VK_QUEUE queue,
VK_GPU_MEMORY mem)
{
/*
* The winsys maintains the list of memory references. These are ignored
* until we move away from the winsys.
*/
return VK_SUCCESS;
}
ICD_EXPORT VK_RESULT VKAPI vkQueueRemoveMemReference(
VK_QUEUE queue,
VK_GPU_MEMORY mem)
{
/*
* The winsys maintains the list of memory references. These are ignored
* until we move away from the winsys.
*/
return VK_SUCCESS;
}
ICD_EXPORT VK_RESULT VKAPI vkQueueWaitIdle(
VK_QUEUE queue_)
{
struct intel_queue *queue = intel_queue(queue_);
return intel_queue_wait(queue, -1);
}
ICD_EXPORT VK_RESULT VKAPI vkQueueSubmit(
VK_QUEUE queue_,
uint32_t cmdBufferCount,
const VK_CMD_BUFFER* pCmdBuffers,
VK_FENCE fence_)
{
struct intel_queue *queue = intel_queue(queue_);
VK_RESULT ret = VK_SUCCESS;
struct intel_cmd *last_cmd;
uint32_t i;
if (unlikely(intel_debug)) {
for (i = 0; i < cmdBufferCount; i++) {
struct intel_cmd *cmd = intel_cmd(pCmdBuffers[i]);
ret = queue_submit_cmd_debug(queue, cmd);
if (ret != VK_SUCCESS)
break;
}
} else {
for (i = 0; i < cmdBufferCount; i++) {
struct intel_cmd *cmd = intel_cmd(pCmdBuffers[i]);
ret = queue_submit_cmd(queue, cmd);
if (ret != VK_SUCCESS)
break;
}
}
/* no cmd submitted */
if (i == 0)
return ret;
last_cmd = intel_cmd(pCmdBuffers[i - 1]);
if (ret == VK_SUCCESS) {
intel_fence_set_seqno(queue->fence,
intel_bo_ref(intel_cmd_get_batch(last_cmd, NULL)));
if (fence_ != VK_NULL_HANDLE) {
struct intel_fence *fence = intel_fence(fence_);
intel_fence_copy(fence, queue->fence);
}
} else {
struct intel_bo *last_bo;
/* unbusy submitted BOs */
last_bo = intel_cmd_get_batch(last_cmd, NULL);
intel_bo_wait(last_bo, -1);
}
return ret;
}
ICD_EXPORT VK_RESULT VKAPI vkOpenSharedSemaphore(
VK_DEVICE device,
const VK_SEMAPHORE_OPEN_INFO* pOpenInfo,
VK_SEMAPHORE* pSemaphore)
{
return VK_ERROR_UNAVAILABLE;
}
ICD_EXPORT VK_RESULT VKAPI vkCreateSemaphore(
VK_DEVICE device,
const VK_SEMAPHORE_CREATE_INFO* pCreateInfo,
VK_SEMAPHORE* pSemaphore)
{
/*
* We want to find an unused semaphore register and initialize it. Signal
* will increment the register. Wait will atomically decrement it and
* block if the value is zero, or a large constant N if we do not want to
* go negative.
*
* XXX However, MI_SEMAPHORE_MBOX does not seem to have the flexibility.
*/
return VK_ERROR_UNAVAILABLE;
}
ICD_EXPORT VK_RESULT VKAPI vkQueueSignalSemaphore(
VK_QUEUE queue,
VK_SEMAPHORE semaphore)
{
return VK_ERROR_UNAVAILABLE;
}
ICD_EXPORT VK_RESULT VKAPI vkQueueWaitSemaphore(
VK_QUEUE queue,
VK_SEMAPHORE semaphore)
{
return VK_ERROR_UNAVAILABLE;
}