Chia-I Wu | ac6ba13 | 2014-08-07 14:21:43 +0800 | [diff] [blame] | 1 | /* |
| 2 | * XGL |
| 3 | * |
| 4 | * Copyright (C) 2014 LunarG, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included |
| 14 | * in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
Chia-I Wu | 44e4236 | 2014-09-02 08:32:09 +0800 | [diff] [blame] | 23 | * |
| 24 | * Authors: |
| 25 | * Chia-I Wu <olv@lunarg.com> |
Chia-I Wu | ac6ba13 | 2014-08-07 14:21:43 +0800 | [diff] [blame] | 26 | */ |
| 27 | |
| 28 | #include "genhw/genhw.h" |
| 29 | #include "dev.h" |
| 30 | #include "gpu.h" |
| 31 | #include "format.h" |
| 32 | |
| 33 | struct intel_sampler_cap { |
| 34 | int sampling; |
| 35 | int filtering; |
| 36 | int shadow_map; |
| 37 | int chroma_key; |
| 38 | }; |
| 39 | |
| 40 | struct intel_dp_cap { |
| 41 | int rt_write; |
| 42 | int rt_write_blending; |
| 43 | int typed_write; |
| 44 | int media_color_processing; |
| 45 | }; |
| 46 | |
| 47 | /* |
| 48 | * This table is based on: |
| 49 | * |
| 50 | * - the Sandy Bridge PRM, volume 4 part 1, page 88-97 |
| 51 | * - the Ivy Bridge PRM, volume 4 part 1, page 84-87 |
| 52 | */ |
| 53 | static const struct intel_sampler_cap intel_sampler_caps[] = { |
| 54 | #define CAP(sampling, filtering, shadow_map, chroma_key) \ |
| 55 | { INTEL_GEN(sampling), INTEL_GEN(filtering), INTEL_GEN(shadow_map), INTEL_GEN(chroma_key) } |
| 56 | [GEN6_FORMAT_R32G32B32A32_FLOAT] = CAP( 1, 5, 0, 0), |
| 57 | [GEN6_FORMAT_R32G32B32A32_SINT] = CAP( 1, 0, 0, 0), |
| 58 | [GEN6_FORMAT_R32G32B32A32_UINT] = CAP( 1, 0, 0, 0), |
| 59 | [GEN6_FORMAT_R32G32B32X32_FLOAT] = CAP( 1, 5, 0, 0), |
| 60 | [GEN6_FORMAT_R32G32B32_FLOAT] = CAP( 1, 5, 0, 0), |
| 61 | [GEN6_FORMAT_R32G32B32_SINT] = CAP( 1, 0, 0, 0), |
| 62 | [GEN6_FORMAT_R32G32B32_UINT] = CAP( 1, 0, 0, 0), |
| 63 | [GEN6_FORMAT_R16G16B16A16_UNORM] = CAP( 1, 1, 0, 0), |
| 64 | [GEN6_FORMAT_R16G16B16A16_SNORM] = CAP( 1, 1, 0, 0), |
| 65 | [GEN6_FORMAT_R16G16B16A16_SINT] = CAP( 1, 0, 0, 0), |
| 66 | [GEN6_FORMAT_R16G16B16A16_UINT] = CAP( 1, 0, 0, 0), |
| 67 | [GEN6_FORMAT_R16G16B16A16_FLOAT] = CAP( 1, 1, 0, 0), |
| 68 | [GEN6_FORMAT_R32G32_FLOAT] = CAP( 1, 5, 0, 0), |
| 69 | [GEN6_FORMAT_R32G32_SINT] = CAP( 1, 0, 0, 0), |
| 70 | [GEN6_FORMAT_R32G32_UINT] = CAP( 1, 0, 0, 0), |
| 71 | [GEN6_FORMAT_R32_FLOAT_X8X24_TYPELESS] = CAP( 1, 5, 1, 0), |
| 72 | [GEN6_FORMAT_X32_TYPELESS_G8X24_UINT] = CAP( 1, 0, 0, 0), |
| 73 | [GEN6_FORMAT_L32A32_FLOAT] = CAP( 1, 5, 0, 0), |
| 74 | [GEN6_FORMAT_R16G16B16X16_UNORM] = CAP( 1, 1, 0, 0), |
| 75 | [GEN6_FORMAT_R16G16B16X16_FLOAT] = CAP( 1, 1, 0, 0), |
| 76 | [GEN6_FORMAT_A32X32_FLOAT] = CAP( 1, 5, 0, 0), |
| 77 | [GEN6_FORMAT_L32X32_FLOAT] = CAP( 1, 5, 0, 0), |
| 78 | [GEN6_FORMAT_I32X32_FLOAT] = CAP( 1, 5, 0, 0), |
| 79 | [GEN6_FORMAT_B8G8R8A8_UNORM] = CAP( 1, 1, 0, 1), |
| 80 | [GEN6_FORMAT_B8G8R8A8_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 81 | [GEN6_FORMAT_R10G10B10A2_UNORM] = CAP( 1, 1, 0, 0), |
| 82 | [GEN6_FORMAT_R10G10B10A2_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 83 | [GEN6_FORMAT_R10G10B10A2_UINT] = CAP( 1, 0, 0, 0), |
| 84 | [GEN6_FORMAT_R10G10B10_SNORM_A2_UNORM] = CAP( 1, 1, 0, 0), |
| 85 | [GEN6_FORMAT_R8G8B8A8_UNORM] = CAP( 1, 1, 0, 0), |
| 86 | [GEN6_FORMAT_R8G8B8A8_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 87 | [GEN6_FORMAT_R8G8B8A8_SNORM] = CAP( 1, 1, 0, 0), |
| 88 | [GEN6_FORMAT_R8G8B8A8_SINT] = CAP( 1, 0, 0, 0), |
| 89 | [GEN6_FORMAT_R8G8B8A8_UINT] = CAP( 1, 0, 0, 0), |
| 90 | [GEN6_FORMAT_R16G16_UNORM] = CAP( 1, 1, 0, 0), |
| 91 | [GEN6_FORMAT_R16G16_SNORM] = CAP( 1, 1, 0, 0), |
| 92 | [GEN6_FORMAT_R16G16_SINT] = CAP( 1, 0, 0, 0), |
| 93 | [GEN6_FORMAT_R16G16_UINT] = CAP( 1, 0, 0, 0), |
| 94 | [GEN6_FORMAT_R16G16_FLOAT] = CAP( 1, 1, 0, 0), |
| 95 | [GEN6_FORMAT_B10G10R10A2_UNORM] = CAP( 1, 1, 0, 0), |
| 96 | [GEN6_FORMAT_B10G10R10A2_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 97 | [GEN6_FORMAT_R11G11B10_FLOAT] = CAP( 1, 1, 0, 0), |
| 98 | [GEN6_FORMAT_R32_SINT] = CAP( 1, 0, 0, 0), |
| 99 | [GEN6_FORMAT_R32_UINT] = CAP( 1, 0, 0, 0), |
| 100 | [GEN6_FORMAT_R32_FLOAT] = CAP( 1, 5, 1, 0), |
| 101 | [GEN6_FORMAT_R24_UNORM_X8_TYPELESS] = CAP( 1, 5, 1, 0), |
| 102 | [GEN6_FORMAT_X24_TYPELESS_G8_UINT] = CAP( 1, 0, 0, 0), |
| 103 | [GEN6_FORMAT_L16A16_UNORM] = CAP( 1, 1, 0, 0), |
| 104 | [GEN6_FORMAT_I24X8_UNORM] = CAP( 1, 5, 1, 0), |
| 105 | [GEN6_FORMAT_L24X8_UNORM] = CAP( 1, 5, 1, 0), |
| 106 | [GEN6_FORMAT_A24X8_UNORM] = CAP( 1, 5, 1, 0), |
| 107 | [GEN6_FORMAT_I32_FLOAT] = CAP( 1, 5, 1, 0), |
| 108 | [GEN6_FORMAT_L32_FLOAT] = CAP( 1, 5, 1, 0), |
| 109 | [GEN6_FORMAT_A32_FLOAT] = CAP( 1, 5, 1, 0), |
| 110 | [GEN6_FORMAT_B8G8R8X8_UNORM] = CAP( 1, 1, 0, 1), |
| 111 | [GEN6_FORMAT_B8G8R8X8_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 112 | [GEN6_FORMAT_R8G8B8X8_UNORM] = CAP( 1, 1, 0, 0), |
| 113 | [GEN6_FORMAT_R8G8B8X8_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 114 | [GEN6_FORMAT_R9G9B9E5_SHAREDEXP] = CAP( 1, 1, 0, 0), |
| 115 | [GEN6_FORMAT_B10G10R10X2_UNORM] = CAP( 1, 1, 0, 0), |
| 116 | [GEN6_FORMAT_L16A16_FLOAT] = CAP( 1, 1, 0, 0), |
| 117 | [GEN6_FORMAT_B5G6R5_UNORM] = CAP( 1, 1, 0, 1), |
| 118 | [GEN6_FORMAT_B5G6R5_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 119 | [GEN6_FORMAT_B5G5R5A1_UNORM] = CAP( 1, 1, 0, 1), |
| 120 | [GEN6_FORMAT_B5G5R5A1_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 121 | [GEN6_FORMAT_B4G4R4A4_UNORM] = CAP( 1, 1, 0, 1), |
| 122 | [GEN6_FORMAT_B4G4R4A4_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 123 | [GEN6_FORMAT_R8G8_UNORM] = CAP( 1, 1, 0, 0), |
| 124 | [GEN6_FORMAT_R8G8_SNORM] = CAP( 1, 1, 0, 1), |
| 125 | [GEN6_FORMAT_R8G8_SINT] = CAP( 1, 0, 0, 0), |
| 126 | [GEN6_FORMAT_R8G8_UINT] = CAP( 1, 0, 0, 0), |
| 127 | [GEN6_FORMAT_R16_UNORM] = CAP( 1, 1, 1, 0), |
| 128 | [GEN6_FORMAT_R16_SNORM] = CAP( 1, 1, 0, 0), |
| 129 | [GEN6_FORMAT_R16_SINT] = CAP( 1, 0, 0, 0), |
| 130 | [GEN6_FORMAT_R16_UINT] = CAP( 1, 0, 0, 0), |
| 131 | [GEN6_FORMAT_R16_FLOAT] = CAP( 1, 1, 0, 0), |
| 132 | [GEN6_FORMAT_A8P8_UNORM_PALETTE0] = CAP( 5, 5, 0, 0), |
| 133 | [GEN6_FORMAT_A8P8_UNORM_PALETTE1] = CAP( 5, 5, 0, 0), |
| 134 | [GEN6_FORMAT_I16_UNORM] = CAP( 1, 1, 1, 0), |
| 135 | [GEN6_FORMAT_L16_UNORM] = CAP( 1, 1, 1, 0), |
| 136 | [GEN6_FORMAT_A16_UNORM] = CAP( 1, 1, 1, 0), |
| 137 | [GEN6_FORMAT_L8A8_UNORM] = CAP( 1, 1, 0, 1), |
| 138 | [GEN6_FORMAT_I16_FLOAT] = CAP( 1, 1, 1, 0), |
| 139 | [GEN6_FORMAT_L16_FLOAT] = CAP( 1, 1, 1, 0), |
| 140 | [GEN6_FORMAT_A16_FLOAT] = CAP( 1, 1, 1, 0), |
| 141 | [GEN6_FORMAT_L8A8_UNORM_SRGB] = CAP(4.5, 4.5, 0, 0), |
| 142 | [GEN6_FORMAT_R5G5_SNORM_B6_UNORM] = CAP( 1, 1, 0, 1), |
| 143 | [GEN6_FORMAT_P8A8_UNORM_PALETTE0] = CAP( 5, 5, 0, 0), |
| 144 | [GEN6_FORMAT_P8A8_UNORM_PALETTE1] = CAP( 5, 5, 0, 0), |
| 145 | [GEN6_FORMAT_R8_UNORM] = CAP( 1, 1, 0, 4.5), |
| 146 | [GEN6_FORMAT_R8_SNORM] = CAP( 1, 1, 0, 0), |
| 147 | [GEN6_FORMAT_R8_SINT] = CAP( 1, 0, 0, 0), |
| 148 | [GEN6_FORMAT_R8_UINT] = CAP( 1, 0, 0, 0), |
| 149 | [GEN6_FORMAT_A8_UNORM] = CAP( 1, 1, 0, 1), |
| 150 | [GEN6_FORMAT_I8_UNORM] = CAP( 1, 1, 0, 0), |
| 151 | [GEN6_FORMAT_L8_UNORM] = CAP( 1, 1, 0, 1), |
| 152 | [GEN6_FORMAT_P4A4_UNORM_PALETTE0] = CAP( 1, 1, 0, 0), |
| 153 | [GEN6_FORMAT_A4P4_UNORM_PALETTE0] = CAP( 1, 1, 0, 0), |
| 154 | [GEN6_FORMAT_P8_UNORM_PALETTE0] = CAP(4.5, 4.5, 0, 0), |
| 155 | [GEN6_FORMAT_L8_UNORM_SRGB] = CAP(4.5, 4.5, 0, 0), |
| 156 | [GEN6_FORMAT_P8_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0), |
| 157 | [GEN6_FORMAT_P4A4_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0), |
| 158 | [GEN6_FORMAT_A4P4_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0), |
| 159 | [GEN6_FORMAT_DXT1_RGB_SRGB] = CAP(4.5, 4.5, 0, 0), |
| 160 | [GEN6_FORMAT_R1_UNORM] = CAP( 1, 1, 0, 0), |
| 161 | [GEN6_FORMAT_YCRCB_NORMAL] = CAP( 1, 1, 0, 1), |
| 162 | [GEN6_FORMAT_YCRCB_SWAPUVY] = CAP( 1, 1, 0, 1), |
| 163 | [GEN6_FORMAT_P2_UNORM_PALETTE0] = CAP(4.5, 4.5, 0, 0), |
| 164 | [GEN6_FORMAT_P2_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0), |
| 165 | [GEN6_FORMAT_BC1_UNORM] = CAP( 1, 1, 0, 1), |
| 166 | [GEN6_FORMAT_BC2_UNORM] = CAP( 1, 1, 0, 1), |
| 167 | [GEN6_FORMAT_BC3_UNORM] = CAP( 1, 1, 0, 1), |
| 168 | [GEN6_FORMAT_BC4_UNORM] = CAP( 1, 1, 0, 0), |
| 169 | [GEN6_FORMAT_BC5_UNORM] = CAP( 1, 1, 0, 0), |
| 170 | [GEN6_FORMAT_BC1_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 171 | [GEN6_FORMAT_BC2_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 172 | [GEN6_FORMAT_BC3_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 173 | [GEN6_FORMAT_MONO8] = CAP( 1, 0, 0, 0), |
| 174 | [GEN6_FORMAT_YCRCB_SWAPUV] = CAP( 1, 1, 0, 0), |
| 175 | [GEN6_FORMAT_YCRCB_SWAPY] = CAP( 1, 1, 0, 0), |
| 176 | [GEN6_FORMAT_DXT1_RGB] = CAP( 1, 1, 0, 0), |
| 177 | [GEN6_FORMAT_FXT1] = CAP( 1, 1, 0, 0), |
| 178 | [GEN6_FORMAT_BC4_SNORM] = CAP( 1, 1, 0, 0), |
| 179 | [GEN6_FORMAT_BC5_SNORM] = CAP( 1, 1, 0, 0), |
| 180 | [GEN6_FORMAT_R16G16B16_FLOAT] = CAP( 5, 5, 0, 0), |
| 181 | [GEN6_FORMAT_BC6H_SF16] = CAP( 7, 7, 0, 0), |
| 182 | [GEN6_FORMAT_BC7_UNORM] = CAP( 7, 7, 0, 0), |
| 183 | [GEN6_FORMAT_BC7_UNORM_SRGB] = CAP( 7, 7, 0, 0), |
| 184 | [GEN6_FORMAT_BC6H_UF16] = CAP( 7, 7, 0, 0), |
| 185 | #undef CAP |
| 186 | }; |
| 187 | |
| 188 | /* |
| 189 | * This table is based on: |
| 190 | * |
| 191 | * - the Sandy Bridge PRM, volume 4 part 1, page 88-97 |
| 192 | * - the Ivy Bridge PRM, volume 4 part 1, page 172, 252-253, and 277-278 |
| 193 | * - the Haswell PRM, volume 7, page 262-264 |
| 194 | */ |
| 195 | static const struct intel_dp_cap intel_dp_caps[] = { |
| 196 | #define CAP(rt_write, rt_write_blending, typed_write, media_color_processing) \ |
| 197 | { INTEL_GEN(rt_write), INTEL_GEN(rt_write_blending), INTEL_GEN(typed_write), INTEL_GEN(media_color_processing) } |
| 198 | [GEN6_FORMAT_R32G32B32A32_FLOAT] = CAP( 1, 1, 7, 0), |
| 199 | [GEN6_FORMAT_R32G32B32A32_SINT] = CAP( 1, 0, 7, 0), |
| 200 | [GEN6_FORMAT_R32G32B32A32_UINT] = CAP( 1, 0, 7, 0), |
| 201 | [GEN6_FORMAT_R16G16B16A16_UNORM] = CAP( 1, 4.5, 7, 6), |
| 202 | [GEN6_FORMAT_R16G16B16A16_SNORM] = CAP( 1, 6, 7, 0), |
| 203 | [GEN6_FORMAT_R16G16B16A16_SINT] = CAP( 1, 0, 7, 0), |
| 204 | [GEN6_FORMAT_R16G16B16A16_UINT] = CAP( 1, 0, 7, 0), |
| 205 | [GEN6_FORMAT_R16G16B16A16_FLOAT] = CAP( 1, 1, 7, 0), |
| 206 | [GEN6_FORMAT_R32G32_FLOAT] = CAP( 1, 1, 7, 0), |
| 207 | [GEN6_FORMAT_R32G32_SINT] = CAP( 1, 0, 7, 0), |
| 208 | [GEN6_FORMAT_R32G32_UINT] = CAP( 1, 0, 7, 0), |
| 209 | [GEN6_FORMAT_B8G8R8A8_UNORM] = CAP( 1, 1, 7, 6), |
| 210 | [GEN6_FORMAT_B8G8R8A8_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 211 | [GEN6_FORMAT_R10G10B10A2_UNORM] = CAP( 1, 1, 7, 6), |
| 212 | [GEN6_FORMAT_R10G10B10A2_UNORM_SRGB] = CAP( 0, 0, 0, 6), |
| 213 | [GEN6_FORMAT_R10G10B10A2_UINT] = CAP( 1, 0, 7, 0), |
| 214 | [GEN6_FORMAT_R8G8B8A8_UNORM] = CAP( 1, 1, 7, 6), |
| 215 | [GEN6_FORMAT_R8G8B8A8_UNORM_SRGB] = CAP( 1, 1, 0, 6), |
| 216 | [GEN6_FORMAT_R8G8B8A8_SNORM] = CAP( 1, 6, 7, 0), |
| 217 | [GEN6_FORMAT_R8G8B8A8_SINT] = CAP( 1, 0, 7, 0), |
| 218 | [GEN6_FORMAT_R8G8B8A8_UINT] = CAP( 1, 0, 7, 0), |
| 219 | [GEN6_FORMAT_R16G16_UNORM] = CAP( 1, 4.5, 7, 0), |
| 220 | [GEN6_FORMAT_R16G16_SNORM] = CAP( 1, 6, 7, 0), |
| 221 | [GEN6_FORMAT_R16G16_SINT] = CAP( 1, 0, 7, 0), |
| 222 | [GEN6_FORMAT_R16G16_UINT] = CAP( 1, 0, 7, 0), |
| 223 | [GEN6_FORMAT_R16G16_FLOAT] = CAP( 1, 1, 7, 0), |
| 224 | [GEN6_FORMAT_B10G10R10A2_UNORM] = CAP( 1, 1, 7, 6), |
| 225 | [GEN6_FORMAT_B10G10R10A2_UNORM_SRGB] = CAP( 1, 1, 0, 6), |
| 226 | [GEN6_FORMAT_R11G11B10_FLOAT] = CAP( 1, 1, 7, 0), |
| 227 | [GEN6_FORMAT_R32_SINT] = CAP( 1, 0, 7, 0), |
| 228 | [GEN6_FORMAT_R32_UINT] = CAP( 1, 0, 7, 0), |
| 229 | [GEN6_FORMAT_R32_FLOAT] = CAP( 1, 1, 7, 0), |
| 230 | [GEN6_FORMAT_B8G8R8X8_UNORM] = CAP( 0, 0, 0, 6), |
| 231 | [GEN6_FORMAT_B5G6R5_UNORM] = CAP( 1, 1, 7, 0), |
| 232 | [GEN6_FORMAT_B5G6R5_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 233 | [GEN6_FORMAT_B5G5R5A1_UNORM] = CAP( 1, 1, 7, 0), |
| 234 | [GEN6_FORMAT_B5G5R5A1_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 235 | [GEN6_FORMAT_B4G4R4A4_UNORM] = CAP( 1, 1, 7, 0), |
| 236 | [GEN6_FORMAT_B4G4R4A4_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 237 | [GEN6_FORMAT_R8G8_UNORM] = CAP( 1, 1, 7, 0), |
| 238 | [GEN6_FORMAT_R8G8_SNORM] = CAP( 1, 6, 7, 0), |
| 239 | [GEN6_FORMAT_R8G8_SINT] = CAP( 1, 0, 7, 0), |
| 240 | [GEN6_FORMAT_R8G8_UINT] = CAP( 1, 0, 7, 0), |
| 241 | [GEN6_FORMAT_R16_UNORM] = CAP( 1, 4.5, 7, 7), |
| 242 | [GEN6_FORMAT_R16_SNORM] = CAP( 1, 6, 7, 0), |
| 243 | [GEN6_FORMAT_R16_SINT] = CAP( 1, 0, 7, 0), |
| 244 | [GEN6_FORMAT_R16_UINT] = CAP( 1, 0, 7, 0), |
| 245 | [GEN6_FORMAT_R16_FLOAT] = CAP( 1, 1, 7, 0), |
| 246 | [GEN6_FORMAT_B5G5R5X1_UNORM] = CAP( 1, 1, 7, 0), |
| 247 | [GEN6_FORMAT_B5G5R5X1_UNORM_SRGB] = CAP( 1, 1, 0, 0), |
| 248 | [GEN6_FORMAT_R8_UNORM] = CAP( 1, 1, 7, 0), |
| 249 | [GEN6_FORMAT_R8_SNORM] = CAP( 1, 6, 7, 0), |
| 250 | [GEN6_FORMAT_R8_SINT] = CAP( 1, 0, 7, 0), |
| 251 | [GEN6_FORMAT_R8_UINT] = CAP( 1, 0, 7, 0), |
| 252 | [GEN6_FORMAT_A8_UNORM] = CAP( 1, 1, 7, 0), |
| 253 | [GEN6_FORMAT_YCRCB_NORMAL] = CAP( 1, 0, 0, 6), |
| 254 | [GEN6_FORMAT_YCRCB_SWAPUVY] = CAP( 1, 0, 0, 6), |
| 255 | [GEN6_FORMAT_YCRCB_SWAPUV] = CAP( 1, 0, 0, 6), |
| 256 | [GEN6_FORMAT_YCRCB_SWAPY] = CAP( 1, 0, 0, 6), |
| 257 | #undef CAP |
| 258 | }; |
| 259 | |
| 260 | static const int intel_color_mapping[XGL_MAX_CH_FMT + 1][6] = { |
| 261 | [XGL_CH_FMT_B5G6R5] = { GEN6_FORMAT_B5G6R5_UNORM, |
| 262 | 0, |
| 263 | 0, |
| 264 | 0, |
| 265 | 0, |
| 266 | GEN6_FORMAT_B5G6R5_UNORM_SRGB, }, |
| 267 | [XGL_CH_FMT_R8] = { GEN6_FORMAT_R8_UNORM, |
| 268 | GEN6_FORMAT_R8_SNORM, |
| 269 | GEN6_FORMAT_R8_UINT, |
| 270 | GEN6_FORMAT_R8_SINT, |
| 271 | 0, |
| 272 | 0, }, |
| 273 | [XGL_CH_FMT_R8G8] = { GEN6_FORMAT_R8G8_UNORM, |
| 274 | GEN6_FORMAT_R8G8_SNORM, |
| 275 | GEN6_FORMAT_R8G8_UINT, |
| 276 | GEN6_FORMAT_R8G8_SINT, |
| 277 | 0, |
| 278 | 0, }, |
| 279 | [XGL_CH_FMT_R8G8B8A8] = { GEN6_FORMAT_R8G8B8A8_UNORM, |
| 280 | GEN6_FORMAT_R8G8B8A8_SNORM, |
| 281 | GEN6_FORMAT_R8G8B8A8_UINT, |
| 282 | GEN6_FORMAT_R8G8B8A8_SINT, |
| 283 | 0, |
| 284 | GEN6_FORMAT_R8G8B8A8_UNORM_SRGB, }, |
| 285 | [XGL_CH_FMT_B8G8R8A8] = { GEN6_FORMAT_B8G8R8A8_UNORM, |
| 286 | 0, |
| 287 | 0, |
| 288 | 0, |
| 289 | 0, |
| 290 | GEN6_FORMAT_B8G8R8A8_UNORM_SRGB, }, |
| 291 | [XGL_CH_FMT_R11G11B10] = { 0, |
| 292 | 0, |
| 293 | 0, |
| 294 | 0, |
| 295 | GEN6_FORMAT_R11G11B10_FLOAT, |
| 296 | 0, }, |
| 297 | [XGL_CH_FMT_R10G10B10A2] = { GEN6_FORMAT_R10G10B10A2_UNORM, |
| 298 | GEN6_FORMAT_R10G10B10A2_SNORM, |
| 299 | GEN6_FORMAT_R10G10B10A2_UINT, |
| 300 | GEN6_FORMAT_R10G10B10A2_SINT, |
| 301 | 0, |
| 302 | 0, }, |
| 303 | [XGL_CH_FMT_R16] = { GEN6_FORMAT_R16_UNORM, |
| 304 | GEN6_FORMAT_R16_SNORM, |
| 305 | GEN6_FORMAT_R16_UINT, |
| 306 | GEN6_FORMAT_R16_SINT, |
| 307 | GEN6_FORMAT_R16_FLOAT, |
| 308 | 0, }, |
| 309 | [XGL_CH_FMT_R16G16] = { GEN6_FORMAT_R16G16_UNORM, |
| 310 | GEN6_FORMAT_R16G16_SNORM, |
| 311 | GEN6_FORMAT_R16G16_UINT, |
| 312 | GEN6_FORMAT_R16G16_SINT, |
| 313 | GEN6_FORMAT_R16G16_FLOAT, |
| 314 | 0, }, |
| 315 | [XGL_CH_FMT_R16G16B16A16] = { GEN6_FORMAT_R16G16B16A16_UNORM, |
| 316 | GEN6_FORMAT_R16G16B16A16_SNORM, |
| 317 | GEN6_FORMAT_R16G16B16A16_UINT, |
| 318 | GEN6_FORMAT_R16G16B16A16_SINT, |
| 319 | GEN6_FORMAT_R16G16B16A16_FLOAT, |
| 320 | 0, }, |
| 321 | [XGL_CH_FMT_R32] = { GEN6_FORMAT_R32_UNORM, |
| 322 | GEN6_FORMAT_R32_SNORM, |
| 323 | GEN6_FORMAT_R32_UINT, |
| 324 | GEN6_FORMAT_R32_SINT, |
| 325 | GEN6_FORMAT_R32_FLOAT, |
| 326 | 0, }, |
| 327 | [XGL_CH_FMT_R32G32] = { GEN6_FORMAT_R32G32_UNORM, |
| 328 | GEN6_FORMAT_R32G32_SNORM, |
| 329 | GEN6_FORMAT_R32G32_UINT, |
| 330 | GEN6_FORMAT_R32G32_SINT, |
| 331 | GEN6_FORMAT_R32G32_FLOAT, |
| 332 | 0, }, |
| 333 | [XGL_CH_FMT_R32G32B32] = { GEN6_FORMAT_R32G32B32_UNORM, |
| 334 | GEN6_FORMAT_R32G32B32_SNORM, |
| 335 | GEN6_FORMAT_R32G32B32_UINT, |
| 336 | GEN6_FORMAT_R32G32B32_SINT, |
| 337 | GEN6_FORMAT_R32G32B32_FLOAT, |
| 338 | 0, }, |
| 339 | [XGL_CH_FMT_R32G32B32A32] = { GEN6_FORMAT_R32G32B32A32_UNORM, |
| 340 | GEN6_FORMAT_R32G32B32A32_SNORM, |
| 341 | GEN6_FORMAT_R32G32B32A32_UINT, |
| 342 | GEN6_FORMAT_R32G32B32A32_SINT, |
| 343 | GEN6_FORMAT_R32G32B32A32_FLOAT, |
| 344 | 0, }, |
| 345 | [XGL_CH_FMT_R9G9B9E5] = { 0, |
| 346 | 0, |
| 347 | 0, |
| 348 | 0, |
| 349 | GEN6_FORMAT_R9G9B9E5_SHAREDEXP, |
| 350 | 0, }, |
| 351 | [XGL_CH_FMT_BC1] = { GEN6_FORMAT_BC1_UNORM, |
| 352 | 0, |
| 353 | 0, |
| 354 | 0, |
| 355 | 0, |
| 356 | GEN6_FORMAT_BC1_UNORM_SRGB, }, |
| 357 | [XGL_CH_FMT_BC2] = { GEN6_FORMAT_BC2_UNORM, |
| 358 | 0, |
| 359 | 0, |
| 360 | 0, |
| 361 | 0, |
| 362 | GEN6_FORMAT_BC2_UNORM_SRGB, }, |
| 363 | [XGL_CH_FMT_BC3] = { GEN6_FORMAT_BC3_UNORM, |
| 364 | 0, |
| 365 | 0, |
| 366 | 0, |
| 367 | 0, |
| 368 | GEN6_FORMAT_BC3_UNORM_SRGB, }, |
| 369 | [XGL_CH_FMT_BC4] = { GEN6_FORMAT_BC4_UNORM, |
| 370 | GEN6_FORMAT_BC4_SNORM, |
| 371 | 0, |
| 372 | 0, |
| 373 | 0, |
| 374 | 0, }, |
| 375 | [XGL_CH_FMT_BC5] = { GEN6_FORMAT_BC5_UNORM, |
| 376 | GEN6_FORMAT_BC5_SNORM, |
| 377 | 0, |
| 378 | 0, |
| 379 | 0, |
| 380 | 0, }, |
| 381 | [XGL_CH_FMT_BC6U] = { GEN6_FORMAT_BC6H_UF16, |
| 382 | 0, |
| 383 | 0, |
| 384 | 0, |
| 385 | 0, |
| 386 | 0, }, |
| 387 | [XGL_CH_FMT_BC6S] = { GEN6_FORMAT_BC6H_SF16, |
| 388 | 0, |
| 389 | 0, |
| 390 | 0, |
| 391 | 0, |
| 392 | 0, }, |
| 393 | [XGL_CH_FMT_BC7] = { GEN6_FORMAT_BC7_UNORM, |
| 394 | 0, |
| 395 | 0, |
| 396 | 0, |
| 397 | 0, |
| 398 | GEN6_FORMAT_BC7_UNORM_SRGB, }, |
| 399 | }; |
| 400 | |
Chia-I Wu | fb24026 | 2014-08-16 13:26:06 +0800 | [diff] [blame] | 401 | int intel_format_translate_color(const struct intel_gpu *gpu, |
| 402 | XGL_FORMAT format) |
Chia-I Wu | ac6ba13 | 2014-08-07 14:21:43 +0800 | [diff] [blame] | 403 | { |
| 404 | int fmt; |
| 405 | |
| 406 | assert(format.numericFormat != XGL_NUM_FMT_UNDEFINED && |
| 407 | format.numericFormat != XGL_NUM_FMT_DS); |
| 408 | |
| 409 | fmt = intel_color_mapping[format.channelFormat][format.numericFormat - 1]; |
| 410 | |
| 411 | /* GEN6_FORMAT_R32G32B32A32_FLOAT happens to be 0 */ |
| 412 | if (format.channelFormat == XGL_CH_FMT_R32G32B32A32 && |
| 413 | format.numericFormat == XGL_NUM_FMT_FLOAT) |
| 414 | assert(fmt == 0); |
| 415 | else if (!fmt) |
| 416 | fmt = -1; |
| 417 | |
| 418 | return fmt; |
| 419 | } |
| 420 | |
| 421 | static XGL_FLAGS intel_format_get_color_features(const struct intel_dev *dev, |
| 422 | XGL_FORMAT format) |
| 423 | { |
Chia-I Wu | fb24026 | 2014-08-16 13:26:06 +0800 | [diff] [blame] | 424 | const int fmt = intel_format_translate_color(dev->gpu, format); |
Chia-I Wu | ac6ba13 | 2014-08-07 14:21:43 +0800 | [diff] [blame] | 425 | const struct intel_sampler_cap *sampler; |
| 426 | const struct intel_dp_cap *dp; |
| 427 | XGL_FLAGS features; |
| 428 | |
| 429 | if (fmt < 0) |
| 430 | return 0; |
| 431 | |
| 432 | sampler = (fmt < ARRAY_SIZE(intel_sampler_caps)) ? |
| 433 | &intel_sampler_caps[fmt] : NULL; |
| 434 | dp = (fmt < ARRAY_SIZE(intel_dp_caps)) ? &intel_dp_caps[fmt] : NULL; |
| 435 | |
| 436 | features = XGL_FORMAT_MEMORY_SHADER_ACCESS_BIT; |
| 437 | |
Chia-I Wu | 9419289 | 2014-08-08 21:27:45 +0800 | [diff] [blame] | 438 | #define TEST(dev, func, cap) ((func) && (func)->cap && \ |
| 439 | intel_gpu_gen((dev)->gpu) >= (func)->cap) |
| 440 | if (TEST(dev, sampler, sampling)) { |
Chia-I Wu | ac6ba13 | 2014-08-07 14:21:43 +0800 | [diff] [blame] | 441 | if (format.numericFormat == XGL_NUM_FMT_UINT || |
| 442 | format.numericFormat == XGL_NUM_FMT_SINT || |
Chia-I Wu | 9419289 | 2014-08-08 21:27:45 +0800 | [diff] [blame] | 443 | TEST(dev, sampler, filtering)) |
Chia-I Wu | ac6ba13 | 2014-08-07 14:21:43 +0800 | [diff] [blame] | 444 | features |= XGL_FORMAT_IMAGE_SHADER_READ_BIT; |
| 445 | } |
| 446 | |
Chia-I Wu | 9419289 | 2014-08-08 21:27:45 +0800 | [diff] [blame] | 447 | if (TEST(dev, dp, typed_write)) |
Chia-I Wu | ac6ba13 | 2014-08-07 14:21:43 +0800 | [diff] [blame] | 448 | features |= XGL_FORMAT_IMAGE_SHADER_WRITE_BIT; |
| 449 | |
Chia-I Wu | 9419289 | 2014-08-08 21:27:45 +0800 | [diff] [blame] | 450 | if (TEST(dev, dp, rt_write)) { |
Chia-I Wu | ac6ba13 | 2014-08-07 14:21:43 +0800 | [diff] [blame] | 451 | features |= XGL_FORMAT_COLOR_ATTACHMENT_WRITE_BIT; |
| 452 | |
Chia-I Wu | 9419289 | 2014-08-08 21:27:45 +0800 | [diff] [blame] | 453 | if (TEST(dev, dp, rt_write_blending)) |
Chia-I Wu | ac6ba13 | 2014-08-07 14:21:43 +0800 | [diff] [blame] | 454 | features |= XGL_FORMAT_COLOR_ATTACHMENT_BLEND_BIT; |
| 455 | |
| 456 | if (features & XGL_FORMAT_IMAGE_SHADER_READ_BIT) { |
| 457 | features |= XGL_FORMAT_IMAGE_COPY_BIT | |
| 458 | XGL_FORMAT_CONVERSION_BIT; |
| 459 | } |
| 460 | } |
| 461 | #undef TEST |
| 462 | |
| 463 | return features; |
| 464 | } |
| 465 | |
| 466 | static XGL_FLAGS intel_format_get_ds_features(const struct intel_dev *dev, |
| 467 | XGL_FORMAT format) |
| 468 | { |
| 469 | XGL_FLAGS features; |
| 470 | |
| 471 | assert(format.numericFormat == XGL_NUM_FMT_DS); |
| 472 | |
| 473 | switch (format.channelFormat) { |
| 474 | case XGL_CH_FMT_R8: |
| 475 | features = XGL_FORMAT_STENCIL_ATTACHMENT_BIT;; |
| 476 | break; |
| 477 | case XGL_CH_FMT_R16: |
| 478 | case XGL_CH_FMT_R32: |
| 479 | features = XGL_FORMAT_DEPTH_ATTACHMENT_BIT; |
| 480 | break; |
| 481 | case XGL_CH_FMT_R32G8: |
| 482 | features = XGL_FORMAT_DEPTH_ATTACHMENT_BIT | |
| 483 | XGL_FORMAT_STENCIL_ATTACHMENT_BIT; |
| 484 | break; |
| 485 | default: |
| 486 | features = 0; |
| 487 | break; |
| 488 | } |
| 489 | |
| 490 | return features; |
| 491 | } |
| 492 | |
| 493 | static XGL_FLAGS intel_format_get_raw_features(const struct intel_dev *dev, |
| 494 | XGL_FORMAT format) |
| 495 | { |
| 496 | assert(format.numericFormat == XGL_NUM_FMT_UNDEFINED); |
| 497 | |
| 498 | return (format.channelFormat == XGL_CH_FMT_UNDEFINED) ? |
| 499 | XGL_FORMAT_MEMORY_SHADER_ACCESS_BIT : 0; |
| 500 | } |
| 501 | |
| 502 | static void intel_format_get_props(const struct intel_dev *dev, |
| 503 | XGL_FORMAT format, |
| 504 | XGL_FORMAT_PROPERTIES *props) |
| 505 | { |
| 506 | switch (format.numericFormat) { |
| 507 | case XGL_NUM_FMT_UNDEFINED: |
| 508 | props->linearTilingFeatures = |
| 509 | intel_format_get_raw_features(dev, format); |
| 510 | props->optimalTilingFeatures = 0; |
| 511 | break; |
| 512 | case XGL_NUM_FMT_UNORM: |
| 513 | case XGL_NUM_FMT_SNORM: |
| 514 | case XGL_NUM_FMT_UINT: |
| 515 | case XGL_NUM_FMT_SINT: |
| 516 | case XGL_NUM_FMT_FLOAT: |
| 517 | case XGL_NUM_FMT_SRGB: |
| 518 | props->linearTilingFeatures = |
| 519 | intel_format_get_color_features(dev, format); |
| 520 | props->optimalTilingFeatures = props->linearTilingFeatures; |
| 521 | break; |
| 522 | case XGL_NUM_FMT_DS: |
| 523 | props->linearTilingFeatures = 0; |
| 524 | props->optimalTilingFeatures = |
| 525 | intel_format_get_ds_features(dev, format); |
| 526 | break; |
| 527 | default: |
| 528 | props->linearTilingFeatures = 0; |
| 529 | props->optimalTilingFeatures = 0; |
| 530 | break; |
| 531 | } |
| 532 | } |
| 533 | |
| 534 | XGL_RESULT XGLAPI intelGetFormatInfo( |
| 535 | XGL_DEVICE device, |
| 536 | XGL_FORMAT format, |
| 537 | XGL_FORMAT_INFO_TYPE infoType, |
| 538 | XGL_SIZE* pDataSize, |
| 539 | XGL_VOID* pData) |
| 540 | { |
| 541 | const struct intel_dev *dev = intel_dev(device); |
| 542 | XGL_RESULT ret = XGL_SUCCESS; |
| 543 | |
| 544 | switch (infoType) { |
| 545 | case XGL_INFO_TYPE_FORMAT_PROPERTIES: |
| 546 | *pDataSize = sizeof(XGL_FORMAT_PROPERTIES); |
| 547 | intel_format_get_props(dev, format, pData); |
| 548 | break; |
| 549 | default: |
| 550 | ret = XGL_ERROR_INVALID_VALUE; |
| 551 | break; |
| 552 | } |
| 553 | |
| 554 | return ret; |
| 555 | } |