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gerrit-public.fairphone.software / platform / external / vulkan-validation-layers / 05a6054abf2be1cb10125077961a8e2a56a38277 / . / icd / intel / pipeline.h
blob: f38e4d73c4fc1dc0bb3dc66e92fd8addb7d7b368 [file] [log] [blame]
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600[diff] [blame^]1/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef PIPELINE_H
26#define PIPELINE_H
27
28#include "intel.h"
29#include "obj.h"
30#include "dev.h"
31
32#define INTEL_MAX_DRAW_BUFFERS 8
33#define INTEL_MAX_CONST_BUFFERS (1 + 12)
34#define INTEL_MAX_SAMPLER_VIEWS 16
35#define INTEL_MAX_SAMPLERS 16
36#define INTEL_MAX_SO_BINDINGS 64
37#define INTEL_MAX_SO_BUFFERS 4
38#define INTEL_MAX_VIEWPORTS 1
39
40#define INTEL_MAX_VS_SURFACES (INTEL_MAX_CONST_BUFFERS + INTEL_MAX_SAMPLER_VIEWS)
41#define INTEL_VS_CONST_SURFACE(i) (i)
42#define INTEL_VS_TEXTURE_SURFACE(i) (INTEL_MAX_CONST_BUFFERS + i)
43
44#define INTEL_MAX_GS_SURFACES (INTEL_MAX_SO_BINDINGS)
45#define INTEL_GS_SO_SURFACE(i) (i)
46
47#define INTEL_MAX_WM_SURFACES (INTEL_MAX_DRAW_BUFFERS + INTEL_MAX_CONST_BUFFERS + INTEL_MAX_SAMPLER_VIEWS)
48#define INTEL_WM_DRAW_SURFACE(i) (i)
49#define INTEL_WM_CONST_SURFACE(i) (INTEL_MAX_DRAW_BUFFERS + i)
50#define INTEL_WM_TEXTURE_SURFACE(i) (INTEL_MAX_DRAW_BUFFERS + INTEL_MAX_CONST_BUFFERS + i)
51
52#define SHADER_VERTEX_FLAG (1 << XGL_SHADER_STAGE_VERTEX)
53#define SHADER_TESS_CONTROL_FLAG (1 << XGL_SHADER_STAGE_TESS_CONTROL)
54#define SHADER_TESS_EVAL_FLAG (1 << XGL_SHADER_STAGE_TESS_EVALUATION)
55#define SHADER_GEOMETRY_FLAG (1 << XGL_SHADER_STAGE_GEOMETRY)
56#define SHADER_FRAGMENT_FLAG (1 << XGL_SHADER_STAGE_FRAGMENT)
57#define SHADER_COMPUTE_FLAG (1 << XGL_SHADER_STAGE_COMPUTE)
58
59/**
60 * 3D pipeline.
61 */
62struct intel_pipeline {
63 struct intel_obj obj;
64
65 struct intel_dev *dev;
66
67 struct intel_bo *workaround_bo;
68
69 uint32_t packed_sample_position_1x;
70 uint32_t packed_sample_position_4x;
71 uint32_t packed_sample_position_8x[2];
72
73 bool has_gen6_wa_pipe_control;
74
75 /* XGL IA_STATE */
76 int prim_type;
77 bool primitive_restart;
78 uint32_t primitive_restart_index;
79
80 /* Index of provoking vertex for each prim type */
81 int provoking_vertex_tri;
82 int provoking_vertex_trifan;
83 int provoking_vertex_line;
84
85 // TODO: This should probably be Intel HW state, not XGL state.
86 /* Depth Buffer format */
87 XGL_FORMAT db_format;
88
89 XGL_PIPELINE_CB_STATE cb_state;
90
91 // XGL_PIPELINE_RS_STATE_CREATE_INFO rs_state;
92 bool depthClipEnable;
93 bool rasterizerDiscardEnable;
94 float pointSize;
95
96 XGL_PIPELINE_TESS_STATE_CREATE_INFO tess_state;
97 XGL_PIPELINE_SHADER_STAGE_CREATE_INFO shader_state;
98
99 uint32_t active_shaders;
100 XGL_PIPELINE_SHADER vs;
101 XGL_PIPELINE_SHADER fs;
102 XGL_PIPELINE_SHADER gs;
103 XGL_PIPELINE_SHADER tess_control;
104 XGL_PIPELINE_SHADER tess_eval;
105 XGL_PIPELINE_SHADER compute;
106
107 int reduced_prim;
108 int so_num_vertices, so_max_vertices;
109
110 uint32_t SF_VIEWPORT;
111 uint32_t CLIP_VIEWPORT;
112 uint32_t SF_CLIP_VIEWPORT; /* GEN7+ */
113 uint32_t CC_VIEWPORT;
114
115 uint32_t COLOR_CALC_STATE;
116 uint32_t BLEND_STATE;
117 uint32_t DEPTH_STENCIL_STATE;
118
119 uint32_t SCISSOR_RECT;
120
121 struct {
122 uint32_t BINDING_TABLE_STATE;
123 int BINDING_TABLE_STATE_size;
124 uint32_t SURFACE_STATE[INTEL_MAX_VS_SURFACES];
125 uint32_t SAMPLER_STATE;
126 uint32_t SAMPLER_BORDER_COLOR_STATE[INTEL_MAX_SAMPLERS];
127 uint32_t PUSH_CONSTANT_BUFFER;
128 int PUSH_CONSTANT_BUFFER_size;
129 } vs_state;
130
131 struct {
132 uint32_t BINDING_TABLE_STATE;
133 int BINDING_TABLE_STATE_size;
134 uint32_t SURFACE_STATE[INTEL_MAX_GS_SURFACES];
135 bool active;
136 } gs_state;
137
138 struct {
139 uint32_t BINDING_TABLE_STATE;
140 int BINDING_TABLE_STATE_size;
141 uint32_t SURFACE_STATE[INTEL_MAX_WM_SURFACES];
142 uint32_t SAMPLER_STATE;
143 uint32_t SAMPLER_BORDER_COLOR_STATE[INTEL_MAX_SAMPLERS];
144 uint32_t PUSH_CONSTANT_BUFFER;
145 int PUSH_CONSTANT_BUFFER_size;
146 } wm_state;
147};
148
149static inline struct intel_pipeline *intel_pipeline(XGL_PIPELINE pipeline)
150{
151 return (struct intel_pipeline *) pipeline;
152}
153
154static inline struct intel_pipeline *intel_pipeline_from_obj(struct intel_obj *obj)
155{
156 return (struct intel_pipeline *) obj;
157}
158
159XGL_RESULT XGLAPI intelCreateGraphicsPipeline(
160 XGL_DEVICE device,
161 const XGL_GRAPHICS_PIPELINE_CREATE_INFO* pCreateInfo,
162 XGL_PIPELINE* pPipeline);
163
164XGL_RESULT XGLAPI intelCreateComputePipeline(
165 XGL_DEVICE device,
166 const XGL_COMPUTE_PIPELINE_CREATE_INFO* pCreateInfo,
167 XGL_PIPELINE* pPipeline);
168
169XGL_RESULT XGLAPI intelStorePipeline(
170 XGL_PIPELINE pipeline,
171 XGL_SIZE* pDataSize,
172 XGL_VOID* pData);
173
174XGL_RESULT XGLAPI intelLoadPipeline(
175 XGL_DEVICE device,
176 XGL_SIZE dataSize,
177 const XGL_VOID* pData,
178 XGL_PIPELINE* pPipeline);
179
180XGL_RESULT XGLAPI intelCreatePipelineDelta(
181 XGL_DEVICE device,
182 XGL_PIPELINE p1,
183 XGL_PIPELINE p2,
184 XGL_PIPELINE_DELTA* delta);
185#endif // PIPELINE_H