blob: ce787a40f9219d1b7b15019e4378a2f53531505a [file] [log] [blame]
Chia-I Wu9737a102014-08-07 07:59:51 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "kmd/winsys.h"
26#include "dev.h"
27#include "mem.h"
28#include "event.h"
29
30static XGL_RESULT event_map(struct intel_event *event, uint32_t **ptr_ret)
31{
32 void *ptr;
33
34 if (!event->obj.mem)
35 return XGL_ERROR_MEMORY_NOT_BOUND;
36
37 /*
38 * This is an unsynchronous mapping. It doesn't look like we want a
39 * synchronous mapping. But it is also unclear what would happen when GPU
40 * writes to it at the same time. We need atomicy here.
41 */
42 ptr = intel_mem_map(event->obj.mem, 0);
43 if (!ptr)
44 return XGL_ERROR_MEMORY_MAP_FAILED;
45
46 *ptr_ret = (uint32_t *) ((uint8_t *) ptr + event->obj.offset);
47
48 return XGL_SUCCESS;
49}
50
51static void event_unmap(struct intel_event *event)
52{
53 intel_mem_unmap(event->obj.mem);
54}
55
56static XGL_RESULT event_write(struct intel_event *event, uint32_t val)
57{
58 XGL_RESULT ret;
59 uint32_t *ptr;
60
61 ret = event_map(event, &ptr);
62 if (ret == XGL_SUCCESS) {
63 *ptr = val;
64 event_unmap(event);
65 }
66
67 return ret;
68}
69
70static XGL_RESULT event_read(struct intel_event *event, uint32_t *val)
71{
72 XGL_RESULT ret;
73 uint32_t *ptr;
74
75 ret = event_map(event, &ptr);
76 if (ret == XGL_SUCCESS) {
77 *val = *ptr;
78 event_unmap(event);
79 }
80
81 return ret;
82}
83
Chia-I Wu26f0bd02014-08-07 10:38:40 +080084static void event_destroy(struct intel_obj *obj)
Chia-I Wu9737a102014-08-07 07:59:51 +080085{
86 struct intel_event *event = intel_event_from_obj(obj);
87
88 intel_event_destroy(event);
89}
90
Chia-I Wu26f0bd02014-08-07 10:38:40 +080091static XGL_RESULT event_get_info(struct intel_base *base, int type,
92 XGL_SIZE *size, XGL_VOID *data)
93{
94 XGL_RESULT ret = XGL_SUCCESS;
95
96 switch (type) {
97 case XGL_INFO_TYPE_MEMORY_REQUIREMENTS:
98 {
99 XGL_MEMORY_REQUIREMENTS *mem_req = data;
100
101 /* use dword aligned to 64-byte boundaries */
102 mem_req->size = 4;
103 mem_req->alignment = 64;
104 mem_req->heapCount = 1;
105 mem_req->heaps[0] = 0;
106
107 *size = sizeof(*mem_req);
108 }
109 break;
110 default:
111 ret = intel_base_get_info(base, type, size, data);
112 break;
113 }
114
115 return ret;
116}
117
Chia-I Wu9737a102014-08-07 07:59:51 +0800118XGL_RESULT intel_event_create(struct intel_dev *dev,
119 const XGL_EVENT_CREATE_INFO *info,
120 struct intel_event **event_ret)
121{
122 struct intel_event *event;
Chia-I Wu9737a102014-08-07 07:59:51 +0800123
124 event = icd_alloc(sizeof(*event), 0, XGL_SYSTEM_ALLOC_API_OBJECT);
125 if (!event)
126 return XGL_ERROR_OUT_OF_MEMORY;
127
128 memset(event, 0, sizeof(*event));
129
Chia-I Wu26f0bd02014-08-07 10:38:40 +0800130 event->obj.destroy = event_destroy;
Chia-I Wu9737a102014-08-07 07:59:51 +0800131
132 event->obj.base.dispatch = dev->base.dispatch;
133 if (dev->base.dbg) {
134 event->obj.base.dbg =
135 intel_base_dbg_create(XGL_DBG_OBJECT_EVENT, info, sizeof(*info));
136 if (!event->obj.base.dbg) {
137 icd_free(event);
138 return XGL_ERROR_OUT_OF_MEMORY;
139 }
140 }
Chia-I Wu26f0bd02014-08-07 10:38:40 +0800141 event->obj.base.get_info = event_get_info;
Chia-I Wu9737a102014-08-07 07:59:51 +0800142
143 *event_ret = event;
144
145 return XGL_SUCCESS;
146}
147
148void intel_event_destroy(struct intel_event *event)
149{
150 if (event->obj.base.dbg)
151 intel_base_dbg_destroy(event->obj.base.dbg);
152
153 icd_free(event);
154}
155
156XGL_RESULT intel_event_set(struct intel_event *event)
157{
158 return event_write(event, 1);
159}
160
161XGL_RESULT intel_event_reset(struct intel_event *event)
162{
163 return event_write(event, 0);
164}
165
166XGL_RESULT intel_event_get_status(struct intel_event *event)
167{
168 XGL_RESULT ret;
169 uint32_t val;
170
171 ret = event_read(event, &val);
172 if (ret != XGL_SUCCESS)
173 return ret;
174
175 return (val) ? XGL_EVENT_SET : XGL_EVENT_RESET;
176}
177
178XGL_RESULT XGLAPI intelCreateEvent(
179 XGL_DEVICE device,
180 const XGL_EVENT_CREATE_INFO* pCreateInfo,
181 XGL_EVENT* pEvent)
182{
183 struct intel_dev *dev = intel_dev(device);
184
185 return intel_event_create(dev, pCreateInfo,
186 (struct intel_event **) pEvent);
187}
188
189XGL_RESULT XGLAPI intelGetEventStatus(
190 XGL_EVENT event_)
191{
192 struct intel_event *event = intel_event(event_);
193
194 return intel_event_get_status(event);
195}
196
197XGL_RESULT XGLAPI intelSetEvent(
198 XGL_EVENT event_)
199{
200 struct intel_event *event = intel_event(event_);
201
202 return intel_event_set(event);
203}
204
205XGL_RESULT XGLAPI intelResetEvent(
206 XGL_EVENT event_)
207{
208 struct intel_event *event = intel_event(event_);
209
210 return intel_event_reset(event);
211}