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Chia-I Wu1f7540b2014-08-22 13:56:18 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wu1f7540b2014-08-22 13:56:18 +080026 */
27
Chia-I Wu98824592014-09-02 09:42:46 +080028#include "shader.h"
Chia-I Wu1f7540b2014-08-22 13:56:18 +080029#include "pipeline_priv.h"
Cody Northropbc851432014-09-23 10:06:32 -060030#include "compiler/pipeline/pipeline_compiler_interface.h"
Chia-I Wu1f7540b2014-08-22 13:56:18 +080031
Chia-I Wu5667d6f2014-12-11 22:37:37 +080032static XGL_RESULT pipeline_build_shader(struct intel_pipeline *pipeline,
33 struct intel_pipeline_shader *sh,
34 const XGL_PIPELINE_SHADER *sh_info)
Chia-I Wu1f7540b2014-08-22 13:56:18 +080035{
Chia-I Wu39026c92014-09-02 10:03:19 +080036 XGL_RESULT ret;
37
Chia-I Wu5667d6f2014-12-11 22:37:37 +080038 ret = intel_pipeline_shader_compile(sh, pipeline->dev->gpu, sh_info);
Cody Northrop83e2b032014-09-25 17:00:31 -060039 if (ret != XGL_SUCCESS)
40 return ret;
41
Chia-I Wu3f4bd102014-12-19 13:14:42 +080042 sh->max_threads =
43 intel_gpu_get_max_threads(pipeline->dev->gpu, sh_info->stage);
Chia-I Wub1024732014-12-19 13:00:29 +080044
45 /* 1KB aligned */
46 sh->scratch_offset = u_align(pipeline->scratch_size, 1024);
47 pipeline->scratch_size = sh->scratch_offset +
48 sh->per_thread_scratch_size * sh->max_threads;
Chia-I Wu5667d6f2014-12-11 22:37:37 +080049
50 pipeline->active_shaders |= 1 << sh_info->stage;
51
52 return XGL_SUCCESS;
Chia-I Wu3f4bd102014-12-19 13:14:42 +080053}
54
Chia-I Wu98824592014-09-02 09:42:46 +080055XGL_RESULT pipeline_build_shaders(struct intel_pipeline *pipeline,
56 const struct intel_pipeline_create_info *info)
57{
58 XGL_RESULT ret = XGL_SUCCESS;
59
60 if (ret == XGL_SUCCESS && info->vs.shader)
Chia-I Wu5667d6f2014-12-11 22:37:37 +080061 ret = pipeline_build_shader(pipeline, &pipeline->vs, &info->vs);
Chia-I Wu98824592014-09-02 09:42:46 +080062 if (ret == XGL_SUCCESS && info->tcs.shader)
Chia-I Wu5667d6f2014-12-11 22:37:37 +080063 ret = pipeline_build_shader(pipeline, &pipeline->tcs, &info->tcs);
Chia-I Wu98824592014-09-02 09:42:46 +080064 if (ret == XGL_SUCCESS && info->tes.shader)
Chia-I Wu5667d6f2014-12-11 22:37:37 +080065 ret = pipeline_build_shader(pipeline, &pipeline->tes, &info->tes);
Chia-I Wu98824592014-09-02 09:42:46 +080066 if (ret == XGL_SUCCESS && info->gs.shader)
Chia-I Wu5667d6f2014-12-11 22:37:37 +080067 ret = pipeline_build_shader(pipeline, &pipeline->gs, &info->gs);
Chia-I Wu98824592014-09-02 09:42:46 +080068 if (ret == XGL_SUCCESS && info->fs.shader)
Chia-I Wu5667d6f2014-12-11 22:37:37 +080069 ret = pipeline_build_shader(pipeline, &pipeline->fs, &info->fs);
Chia-I Wu39026c92014-09-02 10:03:19 +080070
71 if (ret == XGL_SUCCESS && info->compute.cs.shader)
Chia-I Wu5667d6f2014-12-11 22:37:37 +080072 ret = pipeline_build_shader(pipeline, &pipeline->cs, &info->compute.cs);
Chia-I Wu3f4bd102014-12-19 13:14:42 +080073
Chia-I Wu98824592014-09-02 09:42:46 +080074 return ret;
75}
76
77void pipeline_tear_shaders(struct intel_pipeline *pipeline)
78{
79 if (pipeline->active_shaders & SHADER_VERTEX_FLAG) {
Chia-I Wu5667d6f2014-12-11 22:37:37 +080080 intel_pipeline_shader_cleanup(&pipeline->vs);
Chia-I Wu98824592014-09-02 09:42:46 +080081 }
82
Chia-I Wu39026c92014-09-02 10:03:19 +080083 if (pipeline->active_shaders & SHADER_TESS_CONTROL_FLAG) {
Chia-I Wu5667d6f2014-12-11 22:37:37 +080084 intel_pipeline_shader_cleanup(&pipeline->tcs);
Chia-I Wu39026c92014-09-02 10:03:19 +080085 }
86
87 if (pipeline->active_shaders & SHADER_TESS_EVAL_FLAG) {
Chia-I Wu5667d6f2014-12-11 22:37:37 +080088 intel_pipeline_shader_cleanup(&pipeline->tes);
Chia-I Wu39026c92014-09-02 10:03:19 +080089 }
90
91 if (pipeline->active_shaders & SHADER_GEOMETRY_FLAG) {
Chia-I Wu5667d6f2014-12-11 22:37:37 +080092 intel_pipeline_shader_cleanup(&pipeline->gs);
Chia-I Wu39026c92014-09-02 10:03:19 +080093 }
94
95 if (pipeline->active_shaders & SHADER_FRAGMENT_FLAG) {
Chia-I Wu5667d6f2014-12-11 22:37:37 +080096 intel_pipeline_shader_cleanup(&pipeline->fs);
Chia-I Wu39026c92014-09-02 10:03:19 +080097 }
98
99 if (pipeline->active_shaders & SHADER_COMPUTE_FLAG) {
Chia-I Wu5667d6f2014-12-11 22:37:37 +0800100 intel_pipeline_shader_cleanup(&pipeline->cs);
Chia-I Wu39026c92014-09-02 10:03:19 +0800101 }
Chia-I Wu98824592014-09-02 09:42:46 +0800102}
Chia-I Wu9fe3ec42014-10-17 09:49:16 +0800103
104struct intel_pipeline_shader *intel_pipeline_shader_create_meta(struct intel_dev *dev,
105 enum intel_dev_meta_shader id)
106{
Chia-I Wu9fe3ec42014-10-17 09:49:16 +0800107 struct intel_pipeline_shader *sh;
Chia-I Wu005c47c2014-10-22 13:49:13 +0800108 XGL_RESULT ret;
Chia-I Wu9fe3ec42014-10-17 09:49:16 +0800109
110 sh = icd_alloc(sizeof(*sh), 0, XGL_SYSTEM_ALLOC_INTERNAL);
111 if (!sh)
112 return NULL;
113 memset(sh, 0, sizeof(*sh));
114
Chia-I Wu005c47c2014-10-22 13:49:13 +0800115 ret = intel_pipeline_shader_compile_meta(sh, dev->gpu, id);
116 if (ret != XGL_SUCCESS) {
Chia-I Wu9fe3ec42014-10-17 09:49:16 +0800117 icd_free(sh);
118 return NULL;
119 }
120
Chia-I Wu3f4bd102014-12-19 13:14:42 +0800121 switch (id) {
122 case INTEL_DEV_META_VS_FILL_MEM:
123 case INTEL_DEV_META_VS_COPY_MEM:
124 case INTEL_DEV_META_VS_COPY_MEM_UNALIGNED:
125 sh->max_threads = intel_gpu_get_max_threads(dev->gpu,
126 XGL_SHADER_STAGE_VERTEX);
127 break;
128 default:
129 sh->max_threads = intel_gpu_get_max_threads(dev->gpu,
130 XGL_SHADER_STAGE_FRAGMENT);
131 break;
132 }
133
Chia-I Wu9fe3ec42014-10-17 09:49:16 +0800134 return sh;
135}
136
137void intel_pipeline_shader_destroy(struct intel_pipeline_shader *sh)
138{
Chia-I Wu5667d6f2014-12-11 22:37:37 +0800139 intel_pipeline_shader_cleanup(sh);
Chia-I Wu9fe3ec42014-10-17 09:49:16 +0800140 icd_free(sh);
141}