Chia-I Wu | 1f7540b | 2014-08-22 13:56:18 +0800 | [diff] [blame] | 1 | /* |
| 2 | * XGL |
| 3 | * |
| 4 | * Copyright (C) 2014 LunarG, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included |
| 14 | * in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
Chia-I Wu | 44e4236 | 2014-09-02 08:32:09 +0800 | [diff] [blame] | 23 | * |
| 24 | * Authors: |
| 25 | * Chia-I Wu <olv@lunarg.com> |
Chia-I Wu | 1f7540b | 2014-08-22 13:56:18 +0800 | [diff] [blame] | 26 | */ |
| 27 | |
Chia-I Wu | 9882459 | 2014-09-02 09:42:46 +0800 | [diff] [blame] | 28 | #include "shader.h" |
Chia-I Wu | 1f7540b | 2014-08-22 13:56:18 +0800 | [diff] [blame] | 29 | #include "pipeline_priv.h" |
Cody Northrop | bc85143 | 2014-09-23 10:06:32 -0600 | [diff] [blame] | 30 | #include "compiler/pipeline/pipeline_compiler_interface.h" |
Chia-I Wu | 1f7540b | 2014-08-22 13:56:18 +0800 | [diff] [blame] | 31 | |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 32 | static XGL_RESULT pipeline_build_shader(struct intel_pipeline *pipeline, |
| 33 | struct intel_pipeline_shader *sh, |
| 34 | const XGL_PIPELINE_SHADER *sh_info) |
Chia-I Wu | 1f7540b | 2014-08-22 13:56:18 +0800 | [diff] [blame] | 35 | { |
Chia-I Wu | 39026c9 | 2014-09-02 10:03:19 +0800 | [diff] [blame] | 36 | XGL_RESULT ret; |
| 37 | |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 38 | ret = intel_pipeline_shader_compile(sh, pipeline->dev->gpu, sh_info); |
Cody Northrop | 83e2b03 | 2014-09-25 17:00:31 -0600 | [diff] [blame] | 39 | if (ret != XGL_SUCCESS) |
| 40 | return ret; |
| 41 | |
Chia-I Wu | 3f4bd10 | 2014-12-19 13:14:42 +0800 | [diff] [blame] | 42 | sh->max_threads = |
| 43 | intel_gpu_get_max_threads(pipeline->dev->gpu, sh_info->stage); |
Chia-I Wu | b102473 | 2014-12-19 13:00:29 +0800 | [diff] [blame] | 44 | |
| 45 | /* 1KB aligned */ |
| 46 | sh->scratch_offset = u_align(pipeline->scratch_size, 1024); |
| 47 | pipeline->scratch_size = sh->scratch_offset + |
| 48 | sh->per_thread_scratch_size * sh->max_threads; |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 49 | |
| 50 | pipeline->active_shaders |= 1 << sh_info->stage; |
| 51 | |
| 52 | return XGL_SUCCESS; |
Chia-I Wu | 3f4bd10 | 2014-12-19 13:14:42 +0800 | [diff] [blame] | 53 | } |
| 54 | |
Chia-I Wu | 9882459 | 2014-09-02 09:42:46 +0800 | [diff] [blame] | 55 | XGL_RESULT pipeline_build_shaders(struct intel_pipeline *pipeline, |
| 56 | const struct intel_pipeline_create_info *info) |
| 57 | { |
| 58 | XGL_RESULT ret = XGL_SUCCESS; |
| 59 | |
| 60 | if (ret == XGL_SUCCESS && info->vs.shader) |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 61 | ret = pipeline_build_shader(pipeline, &pipeline->vs, &info->vs); |
Chia-I Wu | 9882459 | 2014-09-02 09:42:46 +0800 | [diff] [blame] | 62 | if (ret == XGL_SUCCESS && info->tcs.shader) |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 63 | ret = pipeline_build_shader(pipeline, &pipeline->tcs, &info->tcs); |
Chia-I Wu | 9882459 | 2014-09-02 09:42:46 +0800 | [diff] [blame] | 64 | if (ret == XGL_SUCCESS && info->tes.shader) |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 65 | ret = pipeline_build_shader(pipeline, &pipeline->tes, &info->tes); |
Chia-I Wu | 9882459 | 2014-09-02 09:42:46 +0800 | [diff] [blame] | 66 | if (ret == XGL_SUCCESS && info->gs.shader) |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 67 | ret = pipeline_build_shader(pipeline, &pipeline->gs, &info->gs); |
Chia-I Wu | 9882459 | 2014-09-02 09:42:46 +0800 | [diff] [blame] | 68 | if (ret == XGL_SUCCESS && info->fs.shader) |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 69 | ret = pipeline_build_shader(pipeline, &pipeline->fs, &info->fs); |
Chia-I Wu | 39026c9 | 2014-09-02 10:03:19 +0800 | [diff] [blame] | 70 | |
| 71 | if (ret == XGL_SUCCESS && info->compute.cs.shader) |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 72 | ret = pipeline_build_shader(pipeline, &pipeline->cs, &info->compute.cs); |
Chia-I Wu | 3f4bd10 | 2014-12-19 13:14:42 +0800 | [diff] [blame] | 73 | |
Chia-I Wu | 9882459 | 2014-09-02 09:42:46 +0800 | [diff] [blame] | 74 | return ret; |
| 75 | } |
| 76 | |
| 77 | void pipeline_tear_shaders(struct intel_pipeline *pipeline) |
| 78 | { |
| 79 | if (pipeline->active_shaders & SHADER_VERTEX_FLAG) { |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 80 | intel_pipeline_shader_cleanup(&pipeline->vs); |
Chia-I Wu | 9882459 | 2014-09-02 09:42:46 +0800 | [diff] [blame] | 81 | } |
| 82 | |
Chia-I Wu | 39026c9 | 2014-09-02 10:03:19 +0800 | [diff] [blame] | 83 | if (pipeline->active_shaders & SHADER_TESS_CONTROL_FLAG) { |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 84 | intel_pipeline_shader_cleanup(&pipeline->tcs); |
Chia-I Wu | 39026c9 | 2014-09-02 10:03:19 +0800 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | if (pipeline->active_shaders & SHADER_TESS_EVAL_FLAG) { |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 88 | intel_pipeline_shader_cleanup(&pipeline->tes); |
Chia-I Wu | 39026c9 | 2014-09-02 10:03:19 +0800 | [diff] [blame] | 89 | } |
| 90 | |
| 91 | if (pipeline->active_shaders & SHADER_GEOMETRY_FLAG) { |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 92 | intel_pipeline_shader_cleanup(&pipeline->gs); |
Chia-I Wu | 39026c9 | 2014-09-02 10:03:19 +0800 | [diff] [blame] | 93 | } |
| 94 | |
| 95 | if (pipeline->active_shaders & SHADER_FRAGMENT_FLAG) { |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 96 | intel_pipeline_shader_cleanup(&pipeline->fs); |
Chia-I Wu | 39026c9 | 2014-09-02 10:03:19 +0800 | [diff] [blame] | 97 | } |
| 98 | |
| 99 | if (pipeline->active_shaders & SHADER_COMPUTE_FLAG) { |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 100 | intel_pipeline_shader_cleanup(&pipeline->cs); |
Chia-I Wu | 39026c9 | 2014-09-02 10:03:19 +0800 | [diff] [blame] | 101 | } |
Chia-I Wu | 9882459 | 2014-09-02 09:42:46 +0800 | [diff] [blame] | 102 | } |
Chia-I Wu | 9fe3ec4 | 2014-10-17 09:49:16 +0800 | [diff] [blame] | 103 | |
| 104 | struct intel_pipeline_shader *intel_pipeline_shader_create_meta(struct intel_dev *dev, |
| 105 | enum intel_dev_meta_shader id) |
| 106 | { |
Chia-I Wu | 9fe3ec4 | 2014-10-17 09:49:16 +0800 | [diff] [blame] | 107 | struct intel_pipeline_shader *sh; |
Chia-I Wu | 005c47c | 2014-10-22 13:49:13 +0800 | [diff] [blame] | 108 | XGL_RESULT ret; |
Chia-I Wu | 9fe3ec4 | 2014-10-17 09:49:16 +0800 | [diff] [blame] | 109 | |
| 110 | sh = icd_alloc(sizeof(*sh), 0, XGL_SYSTEM_ALLOC_INTERNAL); |
| 111 | if (!sh) |
| 112 | return NULL; |
| 113 | memset(sh, 0, sizeof(*sh)); |
| 114 | |
Chia-I Wu | 005c47c | 2014-10-22 13:49:13 +0800 | [diff] [blame] | 115 | ret = intel_pipeline_shader_compile_meta(sh, dev->gpu, id); |
| 116 | if (ret != XGL_SUCCESS) { |
Chia-I Wu | 9fe3ec4 | 2014-10-17 09:49:16 +0800 | [diff] [blame] | 117 | icd_free(sh); |
| 118 | return NULL; |
| 119 | } |
| 120 | |
Chia-I Wu | 3f4bd10 | 2014-12-19 13:14:42 +0800 | [diff] [blame] | 121 | switch (id) { |
| 122 | case INTEL_DEV_META_VS_FILL_MEM: |
| 123 | case INTEL_DEV_META_VS_COPY_MEM: |
| 124 | case INTEL_DEV_META_VS_COPY_MEM_UNALIGNED: |
| 125 | sh->max_threads = intel_gpu_get_max_threads(dev->gpu, |
| 126 | XGL_SHADER_STAGE_VERTEX); |
| 127 | break; |
| 128 | default: |
| 129 | sh->max_threads = intel_gpu_get_max_threads(dev->gpu, |
| 130 | XGL_SHADER_STAGE_FRAGMENT); |
| 131 | break; |
| 132 | } |
| 133 | |
Chia-I Wu | 9fe3ec4 | 2014-10-17 09:49:16 +0800 | [diff] [blame] | 134 | return sh; |
| 135 | } |
| 136 | |
| 137 | void intel_pipeline_shader_destroy(struct intel_pipeline_shader *sh) |
| 138 | { |
Chia-I Wu | 5667d6f | 2014-12-11 22:37:37 +0800 | [diff] [blame^] | 139 | intel_pipeline_shader_cleanup(sh); |
Chia-I Wu | 9fe3ec4 | 2014-10-17 09:49:16 +0800 | [diff] [blame] | 140 | icd_free(sh); |
| 141 | } |