blob: a24995bbe2e7a210fe1920c01771cb1039b907b1 [file] [log] [blame]
Chia-I Wub2755562014-08-20 13:38:52 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
Chia-I Wu9f039862014-08-20 15:39:56 +080025#include "genhw/genhw.h"
Chia-I Wub2755562014-08-20 13:38:52 +080026#include "dset.h"
27#include "mem.h"
Chia-I Wu018a3962014-08-21 10:37:52 +080028#include "pipeline.h"
Chia-I Wub2755562014-08-20 13:38:52 +080029#include "state.h"
30#include "view.h"
31#include "cmd_priv.h"
32
33XGL_VOID XGLAPI intelCmdBindPipeline(
34 XGL_CMD_BUFFER cmdBuffer,
35 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
36 XGL_PIPELINE pipeline)
37{
38 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
39
40 switch (pipelineBindPoint) {
41 case XGL_PIPELINE_BIND_POINT_COMPUTE:
Chia-I Wu018a3962014-08-21 10:37:52 +080042 cmd->bind.pipeline.compute = intel_pipeline(pipeline);
Chia-I Wub2755562014-08-20 13:38:52 +080043 break;
44 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
Chia-I Wu018a3962014-08-21 10:37:52 +080045 cmd->bind.pipeline.graphics = intel_pipeline(pipeline);
Chia-I Wub2755562014-08-20 13:38:52 +080046 break;
47 default:
48 break;
49 }
50}
51
52XGL_VOID XGLAPI intelCmdBindPipelineDelta(
53 XGL_CMD_BUFFER cmdBuffer,
54 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
55 XGL_PIPELINE_DELTA delta)
56{
57 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
58
59 switch (pipelineBindPoint) {
60 case XGL_PIPELINE_BIND_POINT_COMPUTE:
61 cmd->bind.pipeline.compute_delta = delta;
62 break;
63 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
64 cmd->bind.pipeline.graphics_delta = delta;
65 break;
66 default:
67 break;
68 }
69}
70
71XGL_VOID XGLAPI intelCmdBindStateObject(
72 XGL_CMD_BUFFER cmdBuffer,
73 XGL_STATE_BIND_POINT stateBindPoint,
74 XGL_STATE_OBJECT state)
75{
76 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
77
78 switch (stateBindPoint) {
79 case XGL_STATE_BIND_VIEWPORT:
80 cmd->bind.state.viewport =
81 intel_viewport_state((XGL_VIEWPORT_STATE_OBJECT) state);
82 break;
83 case XGL_STATE_BIND_RASTER:
84 cmd->bind.state.raster =
85 intel_raster_state((XGL_RASTER_STATE_OBJECT) state);
86 break;
87 case XGL_STATE_BIND_DEPTH_STENCIL:
88 cmd->bind.state.ds =
89 intel_ds_state((XGL_DEPTH_STENCIL_STATE_OBJECT) state);
90 break;
91 case XGL_STATE_BIND_COLOR_BLEND:
92 cmd->bind.state.blend =
93 intel_blend_state((XGL_COLOR_BLEND_STATE_OBJECT) state);
94 break;
95 case XGL_STATE_BIND_MSAA:
96 cmd->bind.state.msaa =
97 intel_msaa_state((XGL_MSAA_STATE_OBJECT) state);
98 break;
99 default:
100 break;
101 }
102}
103
104XGL_VOID XGLAPI intelCmdBindDescriptorSet(
105 XGL_CMD_BUFFER cmdBuffer,
106 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
107 XGL_UINT index,
108 XGL_DESCRIPTOR_SET descriptorSet,
109 XGL_UINT slotOffset)
110{
111 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
112 struct intel_dset *dset = intel_dset(descriptorSet);
113
114 assert(!index);
115
116 switch (pipelineBindPoint) {
117 case XGL_PIPELINE_BIND_POINT_COMPUTE:
118 cmd->bind.dset.compute = dset;
119 cmd->bind.dset.compute_offset = slotOffset;
120 break;
121 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
122 cmd->bind.dset.graphics = dset;
123 cmd->bind.dset.graphics_offset = slotOffset;
124 break;
125 default:
126 break;
127 }
128}
129
130XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
131 XGL_CMD_BUFFER cmdBuffer,
132 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
133 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView)
134{
135 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
136
137 switch (pipelineBindPoint) {
138 case XGL_PIPELINE_BIND_POINT_COMPUTE:
139 intel_mem_view_init(&cmd->bind.mem_view.compute, cmd->dev, pMemView);
140 break;
141 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
142 intel_mem_view_init(&cmd->bind.mem_view.graphics, cmd->dev, pMemView);
143 break;
144 default:
145 break;
146 }
147}
148
Chia-I Wu9f039862014-08-20 15:39:56 +0800149static void gen6_3DSTATE_INDEX_BUFFER(struct intel_cmd *cmd,
150 struct intel_mem *mem,
151 XGL_GPU_SIZE offset,
152 XGL_INDEX_TYPE type,
153 bool enable_cut_index)
154{
155 const uint8_t cmd_len = 3;
156 uint32_t dw0, end_offset;
157 unsigned offset_align;
158
159 CMD_ASSERT(cmd, 6, 7.5);
160
161 dw0 = GEN_RENDER_CMD(3D, 3DSTATE_INDEX_BUFFER) | (cmd_len - 2);
162
163 /* the bit is moved to 3DSTATE_VF */
164 if (cmd_gen(cmd) >= INTEL_GEN(7.5))
165 assert(!enable_cut_index);
166 if (enable_cut_index)
167 dw0 |= GEN6_IB_DW0_CUT_INDEX_ENABLE;
168
169 switch (type) {
170 case XGL_INDEX_8:
171 dw0 |= GEN6_IB_DW0_FORMAT_BYTE;
172 offset_align = 1;
173 break;
174 case XGL_INDEX_16:
175 dw0 |= GEN6_IB_DW0_FORMAT_WORD;
176 offset_align = 2;
177 break;
178 case XGL_INDEX_32:
179 dw0 |= GEN6_IB_DW0_FORMAT_DWORD;
180 offset_align = 4;
181 break;
182 default:
183 cmd->result = XGL_ERROR_INVALID_VALUE;
184 return;
185 break;
186 }
187
188 if (offset % offset_align) {
189 cmd->result = XGL_ERROR_INVALID_VALUE;
190 return;
191 }
192
193 /* aligned and inclusive */
194 end_offset = mem->size - (mem->size % offset_align) - 1;
195
196 cmd_reserve(cmd, cmd_len);
197 cmd_write(cmd, dw0);
198 cmd_write_r(cmd, offset, mem, INTEL_DOMAIN_VERTEX, 0);
199 cmd_write_r(cmd, end_offset, mem, INTEL_DOMAIN_VERTEX, 0);
200}
201
Chia-I Wub2755562014-08-20 13:38:52 +0800202XGL_VOID XGLAPI intelCmdBindIndexData(
203 XGL_CMD_BUFFER cmdBuffer,
204 XGL_GPU_MEMORY mem_,
205 XGL_GPU_SIZE offset,
206 XGL_INDEX_TYPE indexType)
207{
208 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
209 struct intel_mem *mem = intel_mem(mem_);
210
Chia-I Wu9f039862014-08-20 15:39:56 +0800211 if (cmd_gen(cmd) >= INTEL_GEN(7.5)) {
212 gen6_3DSTATE_INDEX_BUFFER(cmd, mem, offset, indexType, false);
213 } else {
214 cmd->bind.index.mem = mem;
215 cmd->bind.index.offset = offset;
216 cmd->bind.index.type = indexType;
217 }
Chia-I Wub2755562014-08-20 13:38:52 +0800218}
219
220XGL_VOID XGLAPI intelCmdBindAttachments(
221 XGL_CMD_BUFFER cmdBuffer,
222 XGL_UINT colorAttachmentCount,
223 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
224 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment)
225{
226 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
227 XGL_UINT i;
228
229 for (i = 0; i < colorAttachmentCount; i++) {
230 const XGL_COLOR_ATTACHMENT_BIND_INFO *att = &pColorAttachments[i];
231 struct intel_rt_view *rt = intel_rt_view(att->view);
232
233 cmd->bind.att.rt[i] = rt;
234 }
235
236 cmd->bind.att.rt_count = colorAttachmentCount;
237
238 if (pDepthStencilAttachment) {
239 struct intel_ds_view *ds = intel_ds_view(pDepthStencilAttachment->view);
240 cmd->bind.att.ds = ds;
241 } else {
242 cmd->bind.att.ds = NULL;
243 }
244}
245
246XGL_VOID XGLAPI intelCmdDraw(
247 XGL_CMD_BUFFER cmdBuffer,
248 XGL_UINT firstVertex,
249 XGL_UINT vertexCount,
250 XGL_UINT firstInstance,
251 XGL_UINT instanceCount)
252{
253}
254
255XGL_VOID XGLAPI intelCmdDrawIndexed(
256 XGL_CMD_BUFFER cmdBuffer,
257 XGL_UINT firstIndex,
258 XGL_UINT indexCount,
259 XGL_INT vertexOffset,
260 XGL_UINT firstInstance,
261 XGL_UINT instanceCount)
262{
263}
264
265XGL_VOID XGLAPI intelCmdDrawIndirect(
266 XGL_CMD_BUFFER cmdBuffer,
267 XGL_GPU_MEMORY mem,
268 XGL_GPU_SIZE offset,
269 XGL_UINT32 count,
270 XGL_UINT32 stride)
271{
272}
273
274XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
275 XGL_CMD_BUFFER cmdBuffer,
276 XGL_GPU_MEMORY mem,
277 XGL_GPU_SIZE offset,
278 XGL_UINT32 count,
279 XGL_UINT32 stride)
280{
281}
282
283XGL_VOID XGLAPI intelCmdDispatch(
284 XGL_CMD_BUFFER cmdBuffer,
285 XGL_UINT x,
286 XGL_UINT y,
287 XGL_UINT z)
288{
289}
290
291XGL_VOID XGLAPI intelCmdDispatchIndirect(
292 XGL_CMD_BUFFER cmdBuffer,
293 XGL_GPU_MEMORY mem,
294 XGL_GPU_SIZE offset)
295{
296}