blob: b4b8d3c19ae658f29394ced67dfb1f1e9a9e6e1c [file] [log] [blame]
Chia-I Wuc14d1562014-10-17 09:49:22 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28#include "img.h"
29#include "mem.h"
Chia-I Wu429a0aa2014-10-24 11:57:51 +080030#include "state.h"
Chia-I Wuc14d1562014-10-17 09:49:22 +080031#include "cmd_priv.h"
32
33static void cmd_meta_init_mem_view(struct intel_cmd *cmd,
34 XGL_GPU_MEMORY mem,
35 XGL_GPU_SIZE range,
36 XGL_FORMAT format,
37 XGL_MEMORY_STATE state,
38 struct intel_mem_view *view)
39{
40 XGL_MEMORY_VIEW_ATTACH_INFO info;
41
42 memset(&info, 0, sizeof(info));
43 info.sType = XGL_STRUCTURE_TYPE_MEMORY_VIEW_ATTACH_INFO;
44 info.mem = mem;
45 info.range = range;
46 info.stride = icd_format_get_size(format);
47 info.format = format;
48 info.state = state;
49
Chia-I Wubc7a30c2014-12-13 15:54:10 +080050 /*
51 * We do not rely on the hardware to avoid out-of-bound access. But we do
52 * not want the hardware to ignore the last element either.
53 */
54 if (info.range % info.stride)
55 info.range += info.stride - (info.range % info.stride);
56
Chia-I Wuc14d1562014-10-17 09:49:22 +080057 intel_mem_view_init(view, cmd->dev, &info);
58}
59
60static void cmd_meta_set_src_for_mem(struct intel_cmd *cmd,
61 const struct intel_mem *mem,
62 XGL_FORMAT format,
63 struct intel_cmd_meta *meta)
64{
65 struct intel_mem_view view;
66
67 cmd_meta_init_mem_view(cmd, (XGL_GPU_MEMORY) mem, mem->size, format,
68 XGL_MEMORY_STATE_GRAPHICS_SHADER_READ_ONLY, &view);
69
70 meta->src.valid = true;
71
72 memcpy(meta->src.surface, view.cmd, sizeof(view.cmd[0]) * view.cmd_len);
73 meta->src.surface_len = view.cmd_len;
74
75 meta->src.reloc_target = (intptr_t) mem->bo;
76 meta->src.reloc_offset = 0;
77 meta->src.reloc_flags = 0;
78}
79
80static void cmd_meta_set_dst_for_mem(struct intel_cmd *cmd,
81 const struct intel_mem *mem,
82 XGL_FORMAT format,
83 struct intel_cmd_meta *meta)
84{
85 struct intel_mem_view view;
86
87 cmd_meta_init_mem_view(cmd, (XGL_GPU_MEMORY) mem, mem->size, format,
88 XGL_MEMORY_STATE_GRAPHICS_SHADER_WRITE_ONLY, &view);
89
90 meta->dst.valid = true;
91
92 memcpy(meta->dst.surface, view.cmd, sizeof(view.cmd[0]) * view.cmd_len);
93 meta->dst.surface_len = view.cmd_len;
94
95 meta->dst.reloc_target = (intptr_t) mem->bo;
96 meta->dst.reloc_offset = 0;
Chia-I Wuc5e2ae32014-11-25 11:00:12 +080097 meta->dst.reloc_flags = INTEL_RELOC_WRITE;
Chia-I Wuc14d1562014-10-17 09:49:22 +080098}
99
100static void cmd_meta_set_src_for_img(struct intel_cmd *cmd,
101 const struct intel_img *img,
102 XGL_FORMAT format,
103 XGL_IMAGE_ASPECT aspect,
104 struct intel_cmd_meta *meta)
105{
106 XGL_IMAGE_VIEW_CREATE_INFO info;
107 struct intel_img_view *view;
108 XGL_RESULT ret;
109
110 memset(&info, 0, sizeof(info));
111 info.sType = XGL_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO;
112 info.image = (XGL_IMAGE) img;
113
114 switch (img->type) {
115 case XGL_IMAGE_1D:
116 info.viewType = XGL_IMAGE_VIEW_1D;
117 break;
118 case XGL_IMAGE_2D:
119 info.viewType = XGL_IMAGE_VIEW_2D;
120 break;
121 case XGL_IMAGE_3D:
122 info.viewType = XGL_IMAGE_VIEW_3D;
123 break;
124 default:
125 break;
126 }
127
128 info.format = format;
129 info.channels.r = XGL_CHANNEL_SWIZZLE_R;
130 info.channels.g = XGL_CHANNEL_SWIZZLE_G;
131 info.channels.b = XGL_CHANNEL_SWIZZLE_B;
132 info.channels.a = XGL_CHANNEL_SWIZZLE_A;
133 info.subresourceRange.aspect = aspect;
134 info.subresourceRange.baseMipLevel = 0;
135 info.subresourceRange.mipLevels = XGL_LAST_MIP_OR_SLICE;
136 info.subresourceRange.baseArraySlice = 0;
137 info.subresourceRange.arraySize = XGL_LAST_MIP_OR_SLICE;
138
139 ret = intel_img_view_create(cmd->dev, &info, &view);
140 if (ret != XGL_SUCCESS) {
141 cmd->result = ret;
142 return;
143 }
144
145 meta->src.valid = true;
146
147 memcpy(meta->src.surface, view->cmd,
148 sizeof(view->cmd[0]) * view->cmd_len);
149 meta->src.surface_len = view->cmd_len;
150
151 meta->src.reloc_target = (intptr_t) img->obj.mem->bo;
152 meta->src.reloc_offset = 0;
153 meta->src.reloc_flags = 0;
154
155 intel_img_view_destroy(view);
156}
157
Chia-I Wu83084ba2014-12-04 12:49:52 +0800158static void cmd_meta_adjust_compressed_dst(struct intel_cmd *cmd,
159 const struct intel_img *img,
160 struct intel_cmd_meta *meta)
161{
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800162 XGL_INT w, h, layer;
163 unsigned x_offset, y_offset;
Chia-I Wu83084ba2014-12-04 12:49:52 +0800164
165 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
166 w = GEN_EXTRACT(meta->dst.surface[2], GEN7_SURFACE_DW2_WIDTH);
167 h = GEN_EXTRACT(meta->dst.surface[2], GEN7_SURFACE_DW2_HEIGHT);
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800168 layer = GEN_EXTRACT(meta->dst.surface[4],
169 GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800170 } else {
171 w = GEN_EXTRACT(meta->dst.surface[2], GEN6_SURFACE_DW2_WIDTH);
172 h = GEN_EXTRACT(meta->dst.surface[2], GEN6_SURFACE_DW2_HEIGHT);
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800173 layer = GEN_EXTRACT(meta->dst.surface[4],
174 GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800175 }
176
177 /* note that the width/height fields have the real values minus 1 */
178 w = (w + img->layout.block_width) / img->layout.block_width - 1;
179 h = (h + img->layout.block_height) / img->layout.block_height - 1;
180
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800181 /* adjust width and height */
Chia-I Wu83084ba2014-12-04 12:49:52 +0800182 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800183 meta->dst.surface[2] &= ~(GEN7_SURFACE_DW2_WIDTH__MASK |
184 GEN7_SURFACE_DW2_HEIGHT__MASK);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800185 meta->dst.surface[2] |= GEN_SHIFT32(w, GEN7_SURFACE_DW2_WIDTH) |
186 GEN_SHIFT32(h, GEN7_SURFACE_DW2_HEIGHT);
187 } else {
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800188 meta->dst.surface[2] &= ~(GEN6_SURFACE_DW2_WIDTH__MASK |
189 GEN6_SURFACE_DW2_HEIGHT__MASK);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800190 meta->dst.surface[2] |= GEN_SHIFT32(w, GEN6_SURFACE_DW2_WIDTH) |
191 GEN_SHIFT32(h, GEN6_SURFACE_DW2_HEIGHT);
192 }
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800193
194 if (!layer)
195 return;
196
197 meta->dst.reloc_offset = intel_layout_get_slice_tile_offset(&img->layout,
198 0, layer, &x_offset, &y_offset);
199
200 /*
201 * The lower 2 bits (or 1 bit for Y) are missing. This may be a problem
202 * for small images (16x16 or smaller). We will need to adjust the
203 * drawing rectangle instead.
204 */
205 x_offset = (x_offset / img->layout.block_width) >> 2;
206 y_offset = (y_offset / img->layout.block_height) >> 1;
207
208 /* adjust min array element and X/Y offsets */
209 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
210 meta->dst.surface[4] &= ~GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK;
211 meta->dst.surface[5] |= GEN_SHIFT32(x_offset, GEN7_SURFACE_DW5_X_OFFSET) |
212 GEN_SHIFT32(y_offset, GEN7_SURFACE_DW5_Y_OFFSET);
213 } else {
214 meta->dst.surface[4] &= ~GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK;
215 meta->dst.surface[5] |= GEN_SHIFT32(x_offset, GEN6_SURFACE_DW5_X_OFFSET) |
216 GEN_SHIFT32(y_offset, GEN6_SURFACE_DW5_Y_OFFSET);
217 }
Chia-I Wu83084ba2014-12-04 12:49:52 +0800218}
219
Chia-I Wuc14d1562014-10-17 09:49:22 +0800220static void cmd_meta_set_dst_for_img(struct intel_cmd *cmd,
221 const struct intel_img *img,
222 XGL_FORMAT format,
223 XGL_UINT lod, XGL_UINT layer,
224 struct intel_cmd_meta *meta)
225{
226 XGL_COLOR_ATTACHMENT_VIEW_CREATE_INFO info;
227 struct intel_rt_view *rt;
228 XGL_RESULT ret;
229
230 memset(&info, 0, sizeof(info));
231 info.sType = XGL_STRUCTURE_TYPE_COLOR_ATTACHMENT_VIEW_CREATE_INFO;
232 info.image = (XGL_IMAGE) img;
233 info.format = format;
234 info.mipLevel = lod;
235 info.baseArraySlice = layer;
236 info.arraySize = 1;
237
238 ret = intel_rt_view_create(cmd->dev, &info, &rt);
239 if (ret != XGL_SUCCESS) {
240 cmd->result = ret;
241 return;
242 }
243
244 meta->dst.valid = true;
245
246 memcpy(meta->dst.surface, rt->cmd, sizeof(rt->cmd[0]) * rt->cmd_len);
247 meta->dst.surface_len = rt->cmd_len;
248
249 meta->dst.reloc_target = (intptr_t) img->obj.mem->bo;
250 meta->dst.reloc_offset = 0;
Chia-I Wuc5e2ae32014-11-25 11:00:12 +0800251 meta->dst.reloc_flags = INTEL_RELOC_WRITE;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800252
Chia-I Wu83084ba2014-12-04 12:49:52 +0800253 if (icd_format_is_compressed(img->layout.format))
254 cmd_meta_adjust_compressed_dst(cmd, img, meta);
255
Chia-I Wuc14d1562014-10-17 09:49:22 +0800256 intel_rt_view_destroy(rt);
257}
258
259static void cmd_meta_set_src_for_writer(struct intel_cmd *cmd,
260 enum intel_cmd_writer_type writer,
261 XGL_GPU_SIZE size,
262 XGL_FORMAT format,
263 struct intel_cmd_meta *meta)
264{
265 struct intel_mem_view view;
266
267 cmd_meta_init_mem_view(cmd, XGL_NULL_HANDLE, size, format,
268 XGL_MEMORY_STATE_GRAPHICS_SHADER_READ_ONLY, &view);
269
270 meta->src.valid = true;
271
272 memcpy(meta->src.surface, view.cmd, sizeof(view.cmd[0]) * view.cmd_len);
273 meta->src.surface_len = view.cmd_len;
274
275 meta->src.reloc_target = (intptr_t) writer;
276 meta->src.reloc_offset = 0;
277 meta->src.reloc_flags = INTEL_CMD_RELOC_TARGET_IS_WRITER;
278}
279
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800280static void cmd_meta_set_ds_view(struct intel_cmd *cmd,
281 const struct intel_img *img,
282 XGL_UINT lod, XGL_UINT layer,
283 struct intel_cmd_meta *meta)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800284{
285 XGL_DEPTH_STENCIL_VIEW_CREATE_INFO info;
286 struct intel_ds_view *ds;
287 XGL_RESULT ret;
288
289 memset(&info, 0, sizeof(info));
290 info.sType = XGL_STRUCTURE_TYPE_DEPTH_STENCIL_VIEW_CREATE_INFO;
291 info.image = (XGL_IMAGE) img;
292 info.mipLevel = lod;
293 info.baseArraySlice = layer;
294 info.arraySize = 1;
295
296 ret = intel_ds_view_create(cmd->dev, &info, &ds);
297 if (ret != XGL_SUCCESS) {
298 cmd->result = ret;
299 return;
300 }
301
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800302 meta->ds.view = ds;
303}
304
305static void cmd_meta_set_ds_state(struct intel_cmd *cmd,
306 XGL_IMAGE_ASPECT aspect,
307 XGL_UINT32 stencil_ref,
308 struct intel_cmd_meta *meta)
309{
310 XGL_DEPTH_STENCIL_STATE_CREATE_INFO info;
311 struct intel_ds_state *state;
312 XGL_RESULT ret;
313
314 memset(&info, 0, sizeof(info));
315 info.sType = XGL_STRUCTURE_TYPE_DEPTH_STENCIL_STATE_CREATE_INFO;
316
317 if (aspect == XGL_IMAGE_ASPECT_DEPTH) {
318 info.depthWriteEnable = XGL_TRUE;
319 }
320 else if (aspect == XGL_IMAGE_ASPECT_STENCIL) {
321 info.stencilTestEnable = XGL_TRUE;
322 info.stencilReadMask = 0xff;
323 info.stencilWriteMask = 0xff;
324 info.front.stencilFailOp = XGL_STENCIL_OP_KEEP;
325 info.front.stencilPassOp = XGL_STENCIL_OP_REPLACE;
326 info.front.stencilDepthFailOp = XGL_STENCIL_OP_KEEP;
327 info.front.stencilFunc = XGL_COMPARE_ALWAYS;
328 info.front.stencilRef = stencil_ref;
329 info.back = info.front;
330 }
331
332 ret = intel_ds_state_create(cmd->dev, &info, &state);
333 if (ret != XGL_SUCCESS) {
334 cmd->result = ret;
335 return;
336 }
337
338 meta->ds.state = state;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800339}
340
341static enum intel_dev_meta_shader get_shader_id(const struct intel_dev *dev,
342 const struct intel_img *img,
343 bool copy_array)
344{
345 enum intel_dev_meta_shader shader_id;
346
347 switch (img->type) {
348 case XGL_IMAGE_1D:
349 shader_id = (copy_array) ?
350 INTEL_DEV_META_FS_COPY_1D_ARRAY : INTEL_DEV_META_FS_COPY_1D;
351 break;
352 case XGL_IMAGE_2D:
353 shader_id = (img->samples > 1) ? INTEL_DEV_META_FS_COPY_2D_MS :
354 (copy_array) ? INTEL_DEV_META_FS_COPY_2D_ARRAY :
355 INTEL_DEV_META_FS_COPY_2D;
356 break;
357 case XGL_IMAGE_3D:
358 default:
359 shader_id = INTEL_DEV_META_FS_COPY_2D_ARRAY;
360 break;
361 }
362
363 return shader_id;
364}
365
Chia-I Wuf3a27252014-11-24 15:27:01 +0800366static bool cmd_meta_mem_dword_aligned(const struct intel_cmd *cmd,
367 XGL_GPU_SIZE src_offset,
368 XGL_GPU_SIZE dst_offset,
369 XGL_GPU_SIZE size)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800370{
Chia-I Wuf3a27252014-11-24 15:27:01 +0800371 return !((src_offset | dst_offset | size) & 0x3);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800372}
373
374static XGL_FORMAT cmd_meta_img_raw_format(const struct intel_cmd *cmd,
375 XGL_FORMAT format)
376{
377 format.numericFormat = XGL_NUM_FMT_UINT;
378
379 if (icd_format_is_compressed(format)) {
380 switch (icd_format_get_size(format)) {
381 case 1:
382 format.channelFormat = XGL_CH_FMT_R8;
383 break;
384 case 2:
385 format.channelFormat = XGL_CH_FMT_R16;
386 break;
387 case 4:
388 format.channelFormat = XGL_CH_FMT_R32;
389 break;
390 case 8:
391 format.channelFormat = XGL_CH_FMT_R32G32;
392 break;
393 case 16:
394 format.channelFormat = XGL_CH_FMT_R32G32B32A32;
395 break;
396 default:
397 assert(!"unsupported compressed block size");
398 format.channelFormat = XGL_CH_FMT_R8;
399 break;
400 }
401 }
402
403 return format;
404}
405
406XGL_VOID XGLAPI intelCmdCopyMemory(
407 XGL_CMD_BUFFER cmdBuffer,
408 XGL_GPU_MEMORY srcMem,
409 XGL_GPU_MEMORY destMem,
410 XGL_UINT regionCount,
411 const XGL_MEMORY_COPY* pRegions)
412{
413 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
414 struct intel_mem *src = intel_mem(srcMem);
415 struct intel_mem *dst = intel_mem(destMem);
416 struct intel_cmd_meta meta;
417 XGL_FORMAT format;
418 XGL_UINT i;
419
420 memset(&meta, 0, sizeof(meta));
Chia-I Wuf3a27252014-11-24 15:27:01 +0800421 meta.mode = INTEL_CMD_META_VS_POINTS;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800422
Chia-I Wuc14d1562014-10-17 09:49:22 +0800423 meta.height = 1;
424 meta.samples = 1;
425
426 format.channelFormat = XGL_CH_FMT_UNDEFINED;
427 format.numericFormat = XGL_NUM_FMT_UINT;
428
429 for (i = 0; i < regionCount; i++) {
430 const XGL_MEMORY_COPY *region = &pRegions[i];
431 XGL_CHANNEL_FORMAT ch;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800432
Chia-I Wuf3a27252014-11-24 15:27:01 +0800433 meta.src.x = region->srcOffset;
434 meta.dst.x = region->destOffset;
435 meta.width = region->copySize;
436
437 if (cmd_meta_mem_dword_aligned(cmd, region->srcOffset,
438 region->destOffset, region->copySize)) {
439 meta.shader_id = INTEL_DEV_META_VS_COPY_MEM;
440 meta.src.x /= 4;
441 meta.dst.x /= 4;
442 meta.width /= 4;
443
444 /*
445 * INTEL_DEV_META_VS_COPY_MEM is untyped but expects the stride to
446 * be 16
447 */
448 ch = XGL_CH_FMT_R32G32B32A32;
449 } else {
450 if (cmd_gen(cmd) == INTEL_GEN(6)) {
451 intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR,
452 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
453 "unaligned xglCmdCopyMemory unsupported");
454 cmd->result = XGL_ERROR_UNKNOWN;
455 continue;
456 }
457
458 meta.shader_id = INTEL_DEV_META_VS_COPY_MEM_UNALIGNED;
459
460 /*
461 * INTEL_DEV_META_VS_COPY_MEM_UNALIGNED is untyped but expects the
462 * stride to be 4
463 */
464 ch = XGL_CH_FMT_R8G8B8A8;
465 }
Chia-I Wuc14d1562014-10-17 09:49:22 +0800466
467 if (format.channelFormat != ch) {
468 format.channelFormat = ch;
469
470 cmd_meta_set_src_for_mem(cmd, src, format, &meta);
471 cmd_meta_set_dst_for_mem(cmd, dst, format, &meta);
472 }
473
Chia-I Wuc14d1562014-10-17 09:49:22 +0800474 cmd_draw_meta(cmd, &meta);
475 }
476}
477
478XGL_VOID XGLAPI intelCmdCopyImage(
479 XGL_CMD_BUFFER cmdBuffer,
480 XGL_IMAGE srcImage,
481 XGL_IMAGE destImage,
482 XGL_UINT regionCount,
483 const XGL_IMAGE_COPY* pRegions)
484{
485 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
486 struct intel_img *src = intel_img(srcImage);
487 struct intel_img *dst = intel_img(destImage);
488 struct intel_cmd_meta meta;
489 XGL_FORMAT raw_format;
490 bool raw_copy;
491 XGL_UINT i;
492
493 if (src->type != dst->type) {
494 cmd->result = XGL_ERROR_UNKNOWN;
495 return;
496 }
497
498 if (icd_format_is_equal(src->layout.format, dst->layout.format)) {
499 raw_copy = true;
500 raw_format = cmd_meta_img_raw_format(cmd, src->layout.format);
501 } else if (icd_format_is_compressed(src->layout.format) ||
502 icd_format_is_compressed(dst->layout.format)) {
503 cmd->result = XGL_ERROR_UNKNOWN;
504 return;
505 }
506
507 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800508 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800509
510 cmd_meta_set_src_for_img(cmd, src,
511 (raw_copy) ? raw_format : src->layout.format,
512 XGL_IMAGE_ASPECT_COLOR, &meta);
513
514 meta.samples = dst->samples;
515
516 for (i = 0; i < regionCount; i++) {
517 const XGL_IMAGE_COPY *region = &pRegions[i];
518 XGL_UINT j;
519
520 meta.shader_id = get_shader_id(cmd->dev, src,
521 (region->extent.depth > 1));
522
523 meta.src.lod = region->srcSubresource.mipLevel;
524 meta.src.layer = region->srcSubresource.arraySlice +
525 region->srcOffset.z;
526 meta.src.x = region->srcOffset.x;
527 meta.src.y = region->srcOffset.y;
528
529 meta.dst.lod = region->destSubresource.mipLevel;
530 meta.dst.layer = region->destSubresource.arraySlice +
531 region->destOffset.z;
532 meta.dst.x = region->destOffset.x;
533 meta.dst.y = region->destOffset.y;
534
535 meta.width = region->extent.width;
536 meta.height = region->extent.height;
537
538 for (j = 0; j < region->extent.depth; j++) {
539 cmd_meta_set_dst_for_img(cmd, dst,
540 (raw_copy) ? raw_format : dst->layout.format,
541 meta.dst.lod, meta.dst.layer, &meta);
542
543 cmd_draw_meta(cmd, &meta);
544
545 meta.src.layer++;
546 meta.dst.layer++;
547 }
548 }
549}
550
551XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
552 XGL_CMD_BUFFER cmdBuffer,
553 XGL_GPU_MEMORY srcMem,
554 XGL_IMAGE destImage,
555 XGL_UINT regionCount,
556 const XGL_MEMORY_IMAGE_COPY* pRegions)
557{
558 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
559 struct intel_mem *mem = intel_mem(srcMem);
560 struct intel_img *img = intel_img(destImage);
561 struct intel_cmd_meta meta;
562 XGL_FORMAT format;
563 XGL_UINT i;
564
565 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800566 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800567
568 meta.shader_id = INTEL_DEV_META_FS_COPY_MEM_TO_IMG;
569 meta.samples = img->samples;
570
571 format = cmd_meta_img_raw_format(cmd, img->layout.format);
572 cmd_meta_set_src_for_mem(cmd, mem, format, &meta);
573
574 for (i = 0; i < regionCount; i++) {
575 const XGL_MEMORY_IMAGE_COPY *region = &pRegions[i];
576 XGL_UINT j;
577
578 meta.src.x = region->memOffset / icd_format_get_size(format);
579
580 meta.dst.lod = region->imageSubresource.mipLevel;
581 meta.dst.layer = region->imageSubresource.arraySlice +
582 region->imageOffset.z;
583 meta.dst.x = region->imageOffset.x;
584 meta.dst.y = region->imageOffset.y;
585
586 meta.width = region->imageExtent.width;
587 meta.height = region->imageExtent.height;
588
589 for (j = 0; j < region->imageExtent.depth; j++) {
590 cmd_meta_set_dst_for_img(cmd, img, format,
591 meta.dst.lod, meta.dst.layer, &meta);
592
593 cmd_draw_meta(cmd, &meta);
594
595 meta.src.x += meta.width * meta.height;
596 meta.dst.layer++;
597 }
598 }
599}
600
601XGL_VOID XGLAPI intelCmdCopyImageToMemory(
602 XGL_CMD_BUFFER cmdBuffer,
603 XGL_IMAGE srcImage,
604 XGL_GPU_MEMORY destMem,
605 XGL_UINT regionCount,
606 const XGL_MEMORY_IMAGE_COPY* pRegions)
607{
608 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
609 struct intel_img *img = intel_img(srcImage);
610 struct intel_mem *mem = intel_mem(destMem);
611 struct intel_cmd_meta meta;
612 XGL_FORMAT format;
613 XGL_UINT i;
614
615 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800616 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800617
618 format = cmd_meta_img_raw_format(cmd, img->layout.format);
619 cmd_meta_set_src_for_img(cmd, img, format, XGL_IMAGE_ASPECT_COLOR, &meta);
620 cmd_meta_set_dst_for_mem(cmd, mem, format, &meta);
621
622 meta.height = 1;
623 meta.samples = 1;
624
625 for (i = 0; i < regionCount; i++) {
626 const XGL_MEMORY_IMAGE_COPY *region = &pRegions[i];
627 XGL_UINT j;
628
629 meta.shader_id = get_shader_id(cmd->dev, img,
630 (region->imageExtent.depth > 1));
631
632 meta.src.lod = region->imageSubresource.mipLevel;
633 meta.src.layer = region->imageSubresource.arraySlice +
634 region->imageOffset.z;
635 meta.src.x = region->imageOffset.x;
636 meta.src.y = region->imageOffset.y;
637
638 meta.dst.x = region->memOffset / icd_format_get_size(format);
639
640 meta.width = region->imageExtent.width * region->imageExtent.height;
641
642 for (j = 0; j < region->imageExtent.depth; j++) {
643 cmd_draw_meta(cmd, &meta);
644
645 meta.src.layer++;
646 meta.dst.x += meta.width;
647 }
648 }
649}
650
651XGL_VOID XGLAPI intelCmdCloneImageData(
652 XGL_CMD_BUFFER cmdBuffer,
653 XGL_IMAGE srcImage,
654 XGL_IMAGE_STATE srcImageState,
655 XGL_IMAGE destImage,
656 XGL_IMAGE_STATE destImageState)
657{
658 const struct intel_img *src = intel_img(srcImage);
659 XGL_IMAGE_COPY region;
660 XGL_UINT lv;
661
662 memset(&region, 0, sizeof(region));
663 region.srcSubresource.aspect = XGL_IMAGE_ASPECT_COLOR;
664 region.destSubresource.aspect = XGL_IMAGE_ASPECT_COLOR;
665
666 for (lv = 0; lv < src->mip_levels; lv++) {
667 region.srcSubresource.mipLevel = lv;
668 region.destSubresource.mipLevel = lv;
669
670 region.extent.width = u_minify(src->layout.width0, lv);
671 region.extent.height = u_minify(src->layout.height0, lv);
672 region.extent.depth = src->array_size;
673
674 intelCmdCopyImage(cmdBuffer, srcImage, destImage, 1, &region);
675 }
676}
677
678XGL_VOID XGLAPI intelCmdUpdateMemory(
679 XGL_CMD_BUFFER cmdBuffer,
680 XGL_GPU_MEMORY destMem,
681 XGL_GPU_SIZE destOffset,
682 XGL_GPU_SIZE dataSize,
683 const XGL_UINT32* pData)
684{
685 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
686 struct intel_mem *dst = intel_mem(destMem);
687 struct intel_cmd_meta meta;
688 XGL_FORMAT format;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800689 uint32_t *ptr;
690 uint32_t offset;
691
Chia-I Wuf3a27252014-11-24 15:27:01 +0800692 /* must be 4-byte aligned */
693 if ((destOffset | dataSize) & 3) {
694 cmd->result = XGL_ERROR_UNKNOWN;
695 return;
696 }
697
Chia-I Wuc14d1562014-10-17 09:49:22 +0800698 /* write to dynamic state writer first */
699 offset = cmd_state_pointer(cmd, INTEL_CMD_ITEM_BLOB, 32,
700 (dataSize + 3) / 4, &ptr);
701 memcpy(ptr, pData, dataSize);
702
Chia-I Wuc14d1562014-10-17 09:49:22 +0800703 memset(&meta, 0, sizeof(meta));
Chia-I Wuf3a27252014-11-24 15:27:01 +0800704 meta.mode = INTEL_CMD_META_VS_POINTS;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800705
Chia-I Wuf3a27252014-11-24 15:27:01 +0800706 meta.shader_id = INTEL_DEV_META_VS_COPY_MEM;
707
708 meta.src.x = offset / 4;
709 meta.dst.x = destOffset / 4;
710 meta.width = dataSize / 4;
711 meta.height = 1;
712 meta.samples = 1;
713
714 /*
715 * INTEL_DEV_META_VS_COPY_MEM is untyped but expects the stride to be 16
716 */
717 format.channelFormat = XGL_CH_FMT_R32G32B32A32;
718 format.numericFormat = XGL_NUM_FMT_UINT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800719
720 cmd_meta_set_src_for_writer(cmd, INTEL_CMD_WRITER_STATE,
721 offset + dataSize, format, &meta);
722 cmd_meta_set_dst_for_mem(cmd, dst, format, &meta);
723
Chia-I Wuc14d1562014-10-17 09:49:22 +0800724 cmd_draw_meta(cmd, &meta);
725}
726
727XGL_VOID XGLAPI intelCmdFillMemory(
728 XGL_CMD_BUFFER cmdBuffer,
729 XGL_GPU_MEMORY destMem,
730 XGL_GPU_SIZE destOffset,
731 XGL_GPU_SIZE fillSize,
732 XGL_UINT32 data)
733{
734 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
735 struct intel_mem *dst = intel_mem(destMem);
736 struct intel_cmd_meta meta;
737 XGL_FORMAT format;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800738
739 /* must be 4-byte aligned */
740 if ((destOffset | fillSize) & 3) {
741 cmd->result = XGL_ERROR_UNKNOWN;
742 return;
743 }
744
745 memset(&meta, 0, sizeof(meta));
Chia-I Wuf3a27252014-11-24 15:27:01 +0800746 meta.mode = INTEL_CMD_META_VS_POINTS;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800747
Chia-I Wuf3a27252014-11-24 15:27:01 +0800748 meta.shader_id = INTEL_DEV_META_VS_FILL_MEM;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800749
750 meta.clear_val[0] = data;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800751
Chia-I Wuf3a27252014-11-24 15:27:01 +0800752 meta.dst.x = destOffset / 4;
753 meta.width = fillSize / 4;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800754 meta.height = 1;
755 meta.samples = 1;
756
Chia-I Wuf3a27252014-11-24 15:27:01 +0800757 /*
758 * INTEL_DEV_META_VS_FILL_MEM is untyped but expects the stride to be 16
759 */
760 format.channelFormat = XGL_CH_FMT_R32G32B32A32;
761 format.numericFormat = XGL_NUM_FMT_UINT;
762
763 cmd_meta_set_dst_for_mem(cmd, dst, format, &meta);
764
Chia-I Wuc14d1562014-10-17 09:49:22 +0800765 cmd_draw_meta(cmd, &meta);
766}
767
768static void cmd_meta_clear_image(struct intel_cmd *cmd,
769 struct intel_img *img,
770 XGL_FORMAT format,
771 struct intel_cmd_meta *meta,
772 const XGL_IMAGE_SUBRESOURCE_RANGE *range)
773{
774 XGL_UINT mip_levels, array_size;
775 XGL_UINT i, j;
776
777 if (range->baseMipLevel >= img->mip_levels ||
778 range->baseArraySlice >= img->array_size)
779 return;
780
781 mip_levels = img->mip_levels - range->baseMipLevel;
782 if (mip_levels > range->mipLevels)
783 mip_levels = range->mipLevels;
784
785 array_size = img->array_size - range->baseArraySlice;
786 if (array_size > range->arraySize)
787 array_size = range->arraySize;
788
Chia-I Wuc14d1562014-10-17 09:49:22 +0800789 for (i = 0; i < mip_levels; i++) {
Chia-I Wufaaed472014-10-28 14:17:43 +0800790 meta->dst.lod = range->baseMipLevel + i;
791 meta->dst.layer = range->baseArraySlice;
792
Chia-I Wuc14d1562014-10-17 09:49:22 +0800793 meta->width = u_minify(img->layout.width0, meta->dst.lod);
794 meta->height = u_minify(img->layout.height0, meta->dst.lod);
795
796 for (j = 0; j < array_size; j++) {
797 if (range->aspect == XGL_IMAGE_ASPECT_COLOR) {
798 cmd_meta_set_dst_for_img(cmd, img, format,
799 meta->dst.lod, meta->dst.layer, meta);
800
801 cmd_draw_meta(cmd, meta);
802 } else {
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800803 cmd_meta_set_ds_view(cmd, img, meta->dst.lod,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800804 meta->dst.layer, meta);
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800805 cmd_meta_set_ds_state(cmd, range->aspect,
806 meta->clear_val[1], meta);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800807
808 cmd_draw_meta(cmd, meta);
809
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800810 intel_ds_view_destroy(meta->ds.view);
811 intel_ds_state_destroy(meta->ds.state);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800812 }
813
814 meta->dst.layer++;
815 }
Chia-I Wuc14d1562014-10-17 09:49:22 +0800816 }
817}
818
819XGL_VOID XGLAPI intelCmdClearColorImage(
820 XGL_CMD_BUFFER cmdBuffer,
821 XGL_IMAGE image,
822 const XGL_FLOAT color[4],
823 XGL_UINT rangeCount,
824 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
825{
826 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
827 struct intel_img *img = intel_img(image);
828 struct intel_cmd_meta meta;
829 XGL_UINT i;
830
831 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800832 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800833
834 meta.shader_id = INTEL_DEV_META_FS_CLEAR_COLOR;
835 meta.samples = img->samples;
836
837 meta.clear_val[0] = u_fui(color[0]);
838 meta.clear_val[1] = u_fui(color[1]);
839 meta.clear_val[2] = u_fui(color[2]);
840 meta.clear_val[3] = u_fui(color[3]);
841
842 for (i = 0; i < rangeCount; i++) {
843 cmd_meta_clear_image(cmd, img, img->layout.format,
844 &meta, &pRanges[i]);
845 }
846}
847
848XGL_VOID XGLAPI intelCmdClearColorImageRaw(
849 XGL_CMD_BUFFER cmdBuffer,
850 XGL_IMAGE image,
851 const XGL_UINT32 color[4],
852 XGL_UINT rangeCount,
853 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
854{
855 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
856 struct intel_img *img = intel_img(image);
857 struct intel_cmd_meta meta;
858 XGL_FORMAT format;
859 XGL_UINT i;
860
861 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800862 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800863
864 meta.shader_id = INTEL_DEV_META_FS_CLEAR_COLOR;
865 meta.samples = img->samples;
866
867 meta.clear_val[0] = color[0];
868 meta.clear_val[1] = color[1];
869 meta.clear_val[2] = color[2];
870 meta.clear_val[3] = color[3];
871
872 format = cmd_meta_img_raw_format(cmd, img->layout.format);
873
874 for (i = 0; i < rangeCount; i++)
875 cmd_meta_clear_image(cmd, img, format, &meta, &pRanges[i]);
876}
877
878XGL_VOID XGLAPI intelCmdClearDepthStencil(
879 XGL_CMD_BUFFER cmdBuffer,
880 XGL_IMAGE image,
881 XGL_FLOAT depth,
882 XGL_UINT32 stencil,
883 XGL_UINT rangeCount,
884 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
885{
886 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
887 struct intel_img *img = intel_img(image);
888 struct intel_cmd_meta meta;
889 XGL_UINT i;
890
891 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800892 meta.mode = INTEL_CMD_META_DEPTH_STENCIL_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800893
894 meta.shader_id = INTEL_DEV_META_FS_CLEAR_DEPTH;
895 meta.samples = img->samples;
896
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800897 meta.clear_val[0] = u_fui(depth);
898 meta.clear_val[1] = stencil;
899
Chia-I Wuc14d1562014-10-17 09:49:22 +0800900 for (i = 0; i < rangeCount; i++) {
901 const XGL_IMAGE_SUBRESOURCE_RANGE *range = &pRanges[i];
902
Chia-I Wuc14d1562014-10-17 09:49:22 +0800903 cmd_meta_clear_image(cmd, img, img->layout.format,
904 &meta, range);
905 }
906}
907
908XGL_VOID XGLAPI intelCmdResolveImage(
909 XGL_CMD_BUFFER cmdBuffer,
910 XGL_IMAGE srcImage,
911 XGL_IMAGE destImage,
912 XGL_UINT rectCount,
913 const XGL_IMAGE_RESOLVE* pRects)
914{
915 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
916 struct intel_img *src = intel_img(srcImage);
917 struct intel_img *dst = intel_img(destImage);
918 struct intel_cmd_meta meta;
919 XGL_FORMAT format;
920 XGL_UINT i;
921
922 if (src->samples <= 1 || dst->samples > 1 ||
923 !icd_format_is_equal(src->layout.format, dst->layout.format)) {
924 cmd->result = XGL_ERROR_UNKNOWN;
925 return;
926 }
927
928 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800929 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800930
931 switch (src->samples) {
932 case 2:
933 default:
934 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_2X;
935 break;
936 case 4:
937 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_4X;
938 break;
939 case 8:
940 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_8X;
941 break;
942 case 16:
943 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_16X;
944 break;
945 }
946
947 meta.samples = 1;
948
949 format = cmd_meta_img_raw_format(cmd, src->layout.format);
950 cmd_meta_set_src_for_img(cmd, src, format, XGL_IMAGE_ASPECT_COLOR, &meta);
951
952 for (i = 0; i < rectCount; i++) {
953 const XGL_IMAGE_RESOLVE *rect = &pRects[i];
954
955 meta.src.lod = rect->srcSubresource.mipLevel;
956 meta.src.layer = rect->srcSubresource.arraySlice;
957 meta.src.x = rect->srcOffset.x;
958 meta.src.y = rect->srcOffset.y;
959
960 meta.dst.lod = rect->destSubresource.mipLevel;
961 meta.dst.layer = rect->destSubresource.arraySlice;
962 meta.dst.x = rect->destOffset.x;
963 meta.dst.y = rect->destOffset.y;
964
965 meta.width = rect->extent.width;
966 meta.height = rect->extent.height;
967
968 cmd_meta_set_dst_for_img(cmd, dst, format,
969 meta.dst.lod, meta.dst.layer, &meta);
970
971 cmd_draw_meta(cmd, &meta);
972 }
973}