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gerrit-public.fairphone.software / platform / external / vulkan-validation-layers / df5b51af6538cf9af0128fd9627f3d0d2f793708 / . / icd / intel / format.c
blob: b390dec1146e93ff7691363de72b6e446c1b9162 [file] [log] [blame]
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]1/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +0800[diff] [blame]23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]26 */
27
28#include "genhw/genhw.h"
29#include "dev.h"
30#include "gpu.h"
31#include "format.h"
32
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]33struct intel_vf_cap {
34 int vertex_element;
35};
36
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]37struct intel_sampler_cap {
38 int sampling;
39 int filtering;
40 int shadow_map;
41 int chroma_key;
42};
43
44struct intel_dp_cap {
45 int rt_write;
46 int rt_write_blending;
47 int typed_write;
48 int media_color_processing;
49};
50
51/*
52 * This table is based on:
53 *
54 * - the Sandy Bridge PRM, volume 4 part 1, page 88-97
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]55 * - the Ivy Bridge PRM, volume 2 part 1, page 97-99
56 * - the Haswell PRM, volume 7, page 467-470
57 */
58static const struct intel_vf_cap intel_vf_caps[] = {
59#define CAP(vertex_element) { INTEL_GEN(vertex_element) }
60 [GEN6_FORMAT_R32G32B32A32_FLOAT] = CAP( 1),
61 [GEN6_FORMAT_R32G32B32A32_SINT] = CAP( 1),
62 [GEN6_FORMAT_R32G32B32A32_UINT] = CAP( 1),
63 [GEN6_FORMAT_R32G32B32A32_UNORM] = CAP( 1),
64 [GEN6_FORMAT_R32G32B32A32_SNORM] = CAP( 1),
65 [GEN6_FORMAT_R64G64_FLOAT] = CAP( 1),
66 [GEN6_FORMAT_R32G32B32A32_SSCALED] = CAP( 1),
67 [GEN6_FORMAT_R32G32B32A32_USCALED] = CAP( 1),
68 [GEN6_FORMAT_R32G32B32A32_SFIXED] = CAP(7.5),
69 [GEN6_FORMAT_R32G32B32_FLOAT] = CAP( 1),
70 [GEN6_FORMAT_R32G32B32_SINT] = CAP( 1),
71 [GEN6_FORMAT_R32G32B32_UINT] = CAP( 1),
72 [GEN6_FORMAT_R32G32B32_UNORM] = CAP( 1),
73 [GEN6_FORMAT_R32G32B32_SNORM] = CAP( 1),
74 [GEN6_FORMAT_R32G32B32_SSCALED] = CAP( 1),
75 [GEN6_FORMAT_R32G32B32_USCALED] = CAP( 1),
76 [GEN6_FORMAT_R32G32B32_SFIXED] = CAP(7.5),
77 [GEN6_FORMAT_R16G16B16A16_UNORM] = CAP( 1),
78 [GEN6_FORMAT_R16G16B16A16_SNORM] = CAP( 1),
79 [GEN6_FORMAT_R16G16B16A16_SINT] = CAP( 1),
80 [GEN6_FORMAT_R16G16B16A16_UINT] = CAP( 1),
81 [GEN6_FORMAT_R16G16B16A16_FLOAT] = CAP( 1),
82 [GEN6_FORMAT_R32G32_FLOAT] = CAP( 1),
83 [GEN6_FORMAT_R32G32_SINT] = CAP( 1),
84 [GEN6_FORMAT_R32G32_UINT] = CAP( 1),
85 [GEN6_FORMAT_R32G32_UNORM] = CAP( 1),
86 [GEN6_FORMAT_R32G32_SNORM] = CAP( 1),
87 [GEN6_FORMAT_R64_FLOAT] = CAP( 1),
88 [GEN6_FORMAT_R16G16B16A16_SSCALED] = CAP( 1),
89 [GEN6_FORMAT_R16G16B16A16_USCALED] = CAP( 1),
90 [GEN6_FORMAT_R32G32_SSCALED] = CAP( 1),
91 [GEN6_FORMAT_R32G32_USCALED] = CAP( 1),
92 [GEN6_FORMAT_R32G32_SFIXED] = CAP(7.5),
93 [GEN6_FORMAT_B8G8R8A8_UNORM] = CAP( 1),
94 [GEN6_FORMAT_R10G10B10A2_UNORM] = CAP( 1),
95 [GEN6_FORMAT_R10G10B10A2_UINT] = CAP( 1),
96 [GEN6_FORMAT_R10G10B10_SNORM_A2_UNORM] = CAP( 1),
97 [GEN6_FORMAT_R8G8B8A8_UNORM] = CAP( 1),
98 [GEN6_FORMAT_R8G8B8A8_SNORM] = CAP( 1),
99 [GEN6_FORMAT_R8G8B8A8_SINT] = CAP( 1),
100 [GEN6_FORMAT_R8G8B8A8_UINT] = CAP( 1),
101 [GEN6_FORMAT_R16G16_UNORM] = CAP( 1),
102 [GEN6_FORMAT_R16G16_SNORM] = CAP( 1),
103 [GEN6_FORMAT_R16G16_SINT] = CAP( 1),
104 [GEN6_FORMAT_R16G16_UINT] = CAP( 1),
105 [GEN6_FORMAT_R16G16_FLOAT] = CAP( 1),
106 [GEN6_FORMAT_B10G10R10A2_UNORM] = CAP(7.5),
107 [GEN6_FORMAT_R11G11B10_FLOAT] = CAP( 1),
108 [GEN6_FORMAT_R32_SINT] = CAP( 1),
109 [GEN6_FORMAT_R32_UINT] = CAP( 1),
110 [GEN6_FORMAT_R32_FLOAT] = CAP( 1),
111 [GEN6_FORMAT_R32_UNORM] = CAP( 1),
112 [GEN6_FORMAT_R32_SNORM] = CAP( 1),
113 [GEN6_FORMAT_R10G10B10X2_USCALED] = CAP( 1),
114 [GEN6_FORMAT_R8G8B8A8_SSCALED] = CAP( 1),
115 [GEN6_FORMAT_R8G8B8A8_USCALED] = CAP( 1),
116 [GEN6_FORMAT_R16G16_SSCALED] = CAP( 1),
117 [GEN6_FORMAT_R16G16_USCALED] = CAP( 1),
118 [GEN6_FORMAT_R32_SSCALED] = CAP( 1),
119 [GEN6_FORMAT_R32_USCALED] = CAP( 1),
120 [GEN6_FORMAT_R8G8_UNORM] = CAP( 1),
121 [GEN6_FORMAT_R8G8_SNORM] = CAP( 1),
122 [GEN6_FORMAT_R8G8_SINT] = CAP( 1),
123 [GEN6_FORMAT_R8G8_UINT] = CAP( 1),
124 [GEN6_FORMAT_R16_UNORM] = CAP( 1),
125 [GEN6_FORMAT_R16_SNORM] = CAP( 1),
126 [GEN6_FORMAT_R16_SINT] = CAP( 1),
127 [GEN6_FORMAT_R16_UINT] = CAP( 1),
128 [GEN6_FORMAT_R16_FLOAT] = CAP( 1),
129 [GEN6_FORMAT_R8G8_SSCALED] = CAP( 1),
130 [GEN6_FORMAT_R8G8_USCALED] = CAP( 1),
131 [GEN6_FORMAT_R16_SSCALED] = CAP( 1),
132 [GEN6_FORMAT_R16_USCALED] = CAP( 1),
133 [GEN6_FORMAT_R8_UNORM] = CAP( 1),
134 [GEN6_FORMAT_R8_SNORM] = CAP( 1),
135 [GEN6_FORMAT_R8_SINT] = CAP( 1),
136 [GEN6_FORMAT_R8_UINT] = CAP( 1),
137 [GEN6_FORMAT_R8_SSCALED] = CAP( 1),
138 [GEN6_FORMAT_R8_USCALED] = CAP( 1),
139 [GEN6_FORMAT_R8G8B8_UNORM] = CAP( 1),
140 [GEN6_FORMAT_R8G8B8_SNORM] = CAP( 1),
141 [GEN6_FORMAT_R8G8B8_SSCALED] = CAP( 1),
142 [GEN6_FORMAT_R8G8B8_USCALED] = CAP( 1),
143 [GEN6_FORMAT_R64G64B64A64_FLOAT] = CAP( 1),
144 [GEN6_FORMAT_R64G64B64_FLOAT] = CAP( 1),
145 [GEN6_FORMAT_R16G16B16_FLOAT] = CAP( 6),
146 [GEN6_FORMAT_R16G16B16_UNORM] = CAP( 1),
147 [GEN6_FORMAT_R16G16B16_SNORM] = CAP( 1),
148 [GEN6_FORMAT_R16G16B16_SSCALED] = CAP( 1),
149 [GEN6_FORMAT_R16G16B16_USCALED] = CAP( 1),
150 [GEN6_FORMAT_R16G16B16_UINT] = CAP(7.5),
151 [GEN6_FORMAT_R16G16B16_SINT] = CAP(7.5),
152 [GEN6_FORMAT_R32_SFIXED] = CAP(7.5),
153 [GEN6_FORMAT_R10G10B10A2_SNORM] = CAP(7.5),
154 [GEN6_FORMAT_R10G10B10A2_USCALED] = CAP(7.5),
155 [GEN6_FORMAT_R10G10B10A2_SSCALED] = CAP(7.5),
156 [GEN6_FORMAT_R10G10B10A2_SINT] = CAP(7.5),
157 [GEN6_FORMAT_B10G10R10A2_SNORM] = CAP(7.5),
158 [GEN6_FORMAT_B10G10R10A2_USCALED] = CAP(7.5),
159 [GEN6_FORMAT_B10G10R10A2_SSCALED] = CAP(7.5),
160 [GEN6_FORMAT_B10G10R10A2_UINT] = CAP(7.5),
161 [GEN6_FORMAT_B10G10R10A2_SINT] = CAP(7.5),
162 [GEN6_FORMAT_R8G8B8_UINT] = CAP(7.5),
163 [GEN6_FORMAT_R8G8B8_SINT] = CAP(7.5),
164#undef CAP
165};
166
167/*
168 * This table is based on:
169 *
170 * - the Sandy Bridge PRM, volume 4 part 1, page 88-97
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]171 * - the Ivy Bridge PRM, volume 4 part 1, page 84-87
172 */
173static const struct intel_sampler_cap intel_sampler_caps[] = {
174#define CAP(sampling, filtering, shadow_map, chroma_key) \
175 { INTEL_GEN(sampling), INTEL_GEN(filtering), INTEL_GEN(shadow_map), INTEL_GEN(chroma_key) }
176 [GEN6_FORMAT_R32G32B32A32_FLOAT] = CAP( 1, 5, 0, 0),
177 [GEN6_FORMAT_R32G32B32A32_SINT] = CAP( 1, 0, 0, 0),
178 [GEN6_FORMAT_R32G32B32A32_UINT] = CAP( 1, 0, 0, 0),
179 [GEN6_FORMAT_R32G32B32X32_FLOAT] = CAP( 1, 5, 0, 0),
180 [GEN6_FORMAT_R32G32B32_FLOAT] = CAP( 1, 5, 0, 0),
181 [GEN6_FORMAT_R32G32B32_SINT] = CAP( 1, 0, 0, 0),
182 [GEN6_FORMAT_R32G32B32_UINT] = CAP( 1, 0, 0, 0),
183 [GEN6_FORMAT_R16G16B16A16_UNORM] = CAP( 1, 1, 0, 0),
184 [GEN6_FORMAT_R16G16B16A16_SNORM] = CAP( 1, 1, 0, 0),
185 [GEN6_FORMAT_R16G16B16A16_SINT] = CAP( 1, 0, 0, 0),
186 [GEN6_FORMAT_R16G16B16A16_UINT] = CAP( 1, 0, 0, 0),
187 [GEN6_FORMAT_R16G16B16A16_FLOAT] = CAP( 1, 1, 0, 0),
188 [GEN6_FORMAT_R32G32_FLOAT] = CAP( 1, 5, 0, 0),
189 [GEN6_FORMAT_R32G32_SINT] = CAP( 1, 0, 0, 0),
190 [GEN6_FORMAT_R32G32_UINT] = CAP( 1, 0, 0, 0),
191 [GEN6_FORMAT_R32_FLOAT_X8X24_TYPELESS] = CAP( 1, 5, 1, 0),
192 [GEN6_FORMAT_X32_TYPELESS_G8X24_UINT] = CAP( 1, 0, 0, 0),
193 [GEN6_FORMAT_L32A32_FLOAT] = CAP( 1, 5, 0, 0),
194 [GEN6_FORMAT_R16G16B16X16_UNORM] = CAP( 1, 1, 0, 0),
195 [GEN6_FORMAT_R16G16B16X16_FLOAT] = CAP( 1, 1, 0, 0),
196 [GEN6_FORMAT_A32X32_FLOAT] = CAP( 1, 5, 0, 0),
197 [GEN6_FORMAT_L32X32_FLOAT] = CAP( 1, 5, 0, 0),
198 [GEN6_FORMAT_I32X32_FLOAT] = CAP( 1, 5, 0, 0),
199 [GEN6_FORMAT_B8G8R8A8_UNORM] = CAP( 1, 1, 0, 1),
200 [GEN6_FORMAT_B8G8R8A8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
201 [GEN6_FORMAT_R10G10B10A2_UNORM] = CAP( 1, 1, 0, 0),
202 [GEN6_FORMAT_R10G10B10A2_UNORM_SRGB] = CAP( 1, 1, 0, 0),
203 [GEN6_FORMAT_R10G10B10A2_UINT] = CAP( 1, 0, 0, 0),
204 [GEN6_FORMAT_R10G10B10_SNORM_A2_UNORM] = CAP( 1, 1, 0, 0),
205 [GEN6_FORMAT_R8G8B8A8_UNORM] = CAP( 1, 1, 0, 0),
206 [GEN6_FORMAT_R8G8B8A8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
207 [GEN6_FORMAT_R8G8B8A8_SNORM] = CAP( 1, 1, 0, 0),
208 [GEN6_FORMAT_R8G8B8A8_SINT] = CAP( 1, 0, 0, 0),
209 [GEN6_FORMAT_R8G8B8A8_UINT] = CAP( 1, 0, 0, 0),
210 [GEN6_FORMAT_R16G16_UNORM] = CAP( 1, 1, 0, 0),
211 [GEN6_FORMAT_R16G16_SNORM] = CAP( 1, 1, 0, 0),
212 [GEN6_FORMAT_R16G16_SINT] = CAP( 1, 0, 0, 0),
213 [GEN6_FORMAT_R16G16_UINT] = CAP( 1, 0, 0, 0),
214 [GEN6_FORMAT_R16G16_FLOAT] = CAP( 1, 1, 0, 0),
215 [GEN6_FORMAT_B10G10R10A2_UNORM] = CAP( 1, 1, 0, 0),
216 [GEN6_FORMAT_B10G10R10A2_UNORM_SRGB] = CAP( 1, 1, 0, 0),
217 [GEN6_FORMAT_R11G11B10_FLOAT] = CAP( 1, 1, 0, 0),
218 [GEN6_FORMAT_R32_SINT] = CAP( 1, 0, 0, 0),
219 [GEN6_FORMAT_R32_UINT] = CAP( 1, 0, 0, 0),
220 [GEN6_FORMAT_R32_FLOAT] = CAP( 1, 5, 1, 0),
221 [GEN6_FORMAT_R24_UNORM_X8_TYPELESS] = CAP( 1, 5, 1, 0),
222 [GEN6_FORMAT_X24_TYPELESS_G8_UINT] = CAP( 1, 0, 0, 0),
223 [GEN6_FORMAT_L16A16_UNORM] = CAP( 1, 1, 0, 0),
224 [GEN6_FORMAT_I24X8_UNORM] = CAP( 1, 5, 1, 0),
225 [GEN6_FORMAT_L24X8_UNORM] = CAP( 1, 5, 1, 0),
226 [GEN6_FORMAT_A24X8_UNORM] = CAP( 1, 5, 1, 0),
227 [GEN6_FORMAT_I32_FLOAT] = CAP( 1, 5, 1, 0),
228 [GEN6_FORMAT_L32_FLOAT] = CAP( 1, 5, 1, 0),
229 [GEN6_FORMAT_A32_FLOAT] = CAP( 1, 5, 1, 0),
230 [GEN6_FORMAT_B8G8R8X8_UNORM] = CAP( 1, 1, 0, 1),
231 [GEN6_FORMAT_B8G8R8X8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
232 [GEN6_FORMAT_R8G8B8X8_UNORM] = CAP( 1, 1, 0, 0),
233 [GEN6_FORMAT_R8G8B8X8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
234 [GEN6_FORMAT_R9G9B9E5_SHAREDEXP] = CAP( 1, 1, 0, 0),
235 [GEN6_FORMAT_B10G10R10X2_UNORM] = CAP( 1, 1, 0, 0),
236 [GEN6_FORMAT_L16A16_FLOAT] = CAP( 1, 1, 0, 0),
237 [GEN6_FORMAT_B5G6R5_UNORM] = CAP( 1, 1, 0, 1),
238 [GEN6_FORMAT_B5G6R5_UNORM_SRGB] = CAP( 1, 1, 0, 0),
239 [GEN6_FORMAT_B5G5R5A1_UNORM] = CAP( 1, 1, 0, 1),
240 [GEN6_FORMAT_B5G5R5A1_UNORM_SRGB] = CAP( 1, 1, 0, 0),
241 [GEN6_FORMAT_B4G4R4A4_UNORM] = CAP( 1, 1, 0, 1),
242 [GEN6_FORMAT_B4G4R4A4_UNORM_SRGB] = CAP( 1, 1, 0, 0),
243 [GEN6_FORMAT_R8G8_UNORM] = CAP( 1, 1, 0, 0),
244 [GEN6_FORMAT_R8G8_SNORM] = CAP( 1, 1, 0, 1),
245 [GEN6_FORMAT_R8G8_SINT] = CAP( 1, 0, 0, 0),
246 [GEN6_FORMAT_R8G8_UINT] = CAP( 1, 0, 0, 0),
247 [GEN6_FORMAT_R16_UNORM] = CAP( 1, 1, 1, 0),
248 [GEN6_FORMAT_R16_SNORM] = CAP( 1, 1, 0, 0),
249 [GEN6_FORMAT_R16_SINT] = CAP( 1, 0, 0, 0),
250 [GEN6_FORMAT_R16_UINT] = CAP( 1, 0, 0, 0),
251 [GEN6_FORMAT_R16_FLOAT] = CAP( 1, 1, 0, 0),
252 [GEN6_FORMAT_A8P8_UNORM_PALETTE0] = CAP( 5, 5, 0, 0),
253 [GEN6_FORMAT_A8P8_UNORM_PALETTE1] = CAP( 5, 5, 0, 0),
254 [GEN6_FORMAT_I16_UNORM] = CAP( 1, 1, 1, 0),
255 [GEN6_FORMAT_L16_UNORM] = CAP( 1, 1, 1, 0),
256 [GEN6_FORMAT_A16_UNORM] = CAP( 1, 1, 1, 0),
257 [GEN6_FORMAT_L8A8_UNORM] = CAP( 1, 1, 0, 1),
258 [GEN6_FORMAT_I16_FLOAT] = CAP( 1, 1, 1, 0),
259 [GEN6_FORMAT_L16_FLOAT] = CAP( 1, 1, 1, 0),
260 [GEN6_FORMAT_A16_FLOAT] = CAP( 1, 1, 1, 0),
261 [GEN6_FORMAT_L8A8_UNORM_SRGB] = CAP(4.5, 4.5, 0, 0),
262 [GEN6_FORMAT_R5G5_SNORM_B6_UNORM] = CAP( 1, 1, 0, 1),
263 [GEN6_FORMAT_P8A8_UNORM_PALETTE0] = CAP( 5, 5, 0, 0),
264 [GEN6_FORMAT_P8A8_UNORM_PALETTE1] = CAP( 5, 5, 0, 0),
265 [GEN6_FORMAT_R8_UNORM] = CAP( 1, 1, 0, 4.5),
266 [GEN6_FORMAT_R8_SNORM] = CAP( 1, 1, 0, 0),
267 [GEN6_FORMAT_R8_SINT] = CAP( 1, 0, 0, 0),
268 [GEN6_FORMAT_R8_UINT] = CAP( 1, 0, 0, 0),
269 [GEN6_FORMAT_A8_UNORM] = CAP( 1, 1, 0, 1),
270 [GEN6_FORMAT_I8_UNORM] = CAP( 1, 1, 0, 0),
271 [GEN6_FORMAT_L8_UNORM] = CAP( 1, 1, 0, 1),
272 [GEN6_FORMAT_P4A4_UNORM_PALETTE0] = CAP( 1, 1, 0, 0),
273 [GEN6_FORMAT_A4P4_UNORM_PALETTE0] = CAP( 1, 1, 0, 0),
274 [GEN6_FORMAT_P8_UNORM_PALETTE0] = CAP(4.5, 4.5, 0, 0),
275 [GEN6_FORMAT_L8_UNORM_SRGB] = CAP(4.5, 4.5, 0, 0),
276 [GEN6_FORMAT_P8_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0),
277 [GEN6_FORMAT_P4A4_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0),
278 [GEN6_FORMAT_A4P4_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0),
279 [GEN6_FORMAT_DXT1_RGB_SRGB] = CAP(4.5, 4.5, 0, 0),
280 [GEN6_FORMAT_R1_UNORM] = CAP( 1, 1, 0, 0),
281 [GEN6_FORMAT_YCRCB_NORMAL] = CAP( 1, 1, 0, 1),
282 [GEN6_FORMAT_YCRCB_SWAPUVY] = CAP( 1, 1, 0, 1),
283 [GEN6_FORMAT_P2_UNORM_PALETTE0] = CAP(4.5, 4.5, 0, 0),
284 [GEN6_FORMAT_P2_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0),
285 [GEN6_FORMAT_BC1_UNORM] = CAP( 1, 1, 0, 1),
286 [GEN6_FORMAT_BC2_UNORM] = CAP( 1, 1, 0, 1),
287 [GEN6_FORMAT_BC3_UNORM] = CAP( 1, 1, 0, 1),
288 [GEN6_FORMAT_BC4_UNORM] = CAP( 1, 1, 0, 0),
289 [GEN6_FORMAT_BC5_UNORM] = CAP( 1, 1, 0, 0),
290 [GEN6_FORMAT_BC1_UNORM_SRGB] = CAP( 1, 1, 0, 0),
291 [GEN6_FORMAT_BC2_UNORM_SRGB] = CAP( 1, 1, 0, 0),
292 [GEN6_FORMAT_BC3_UNORM_SRGB] = CAP( 1, 1, 0, 0),
293 [GEN6_FORMAT_MONO8] = CAP( 1, 0, 0, 0),
294 [GEN6_FORMAT_YCRCB_SWAPUV] = CAP( 1, 1, 0, 0),
295 [GEN6_FORMAT_YCRCB_SWAPY] = CAP( 1, 1, 0, 0),
296 [GEN6_FORMAT_DXT1_RGB] = CAP( 1, 1, 0, 0),
297 [GEN6_FORMAT_FXT1] = CAP( 1, 1, 0, 0),
298 [GEN6_FORMAT_BC4_SNORM] = CAP( 1, 1, 0, 0),
299 [GEN6_FORMAT_BC5_SNORM] = CAP( 1, 1, 0, 0),
300 [GEN6_FORMAT_R16G16B16_FLOAT] = CAP( 5, 5, 0, 0),
301 [GEN6_FORMAT_BC6H_SF16] = CAP( 7, 7, 0, 0),
302 [GEN6_FORMAT_BC7_UNORM] = CAP( 7, 7, 0, 0),
303 [GEN6_FORMAT_BC7_UNORM_SRGB] = CAP( 7, 7, 0, 0),
304 [GEN6_FORMAT_BC6H_UF16] = CAP( 7, 7, 0, 0),
305#undef CAP
306};
307
308/*
309 * This table is based on:
310 *
311 * - the Sandy Bridge PRM, volume 4 part 1, page 88-97
312 * - the Ivy Bridge PRM, volume 4 part 1, page 172, 252-253, and 277-278
313 * - the Haswell PRM, volume 7, page 262-264
314 */
315static const struct intel_dp_cap intel_dp_caps[] = {
316#define CAP(rt_write, rt_write_blending, typed_write, media_color_processing) \
317 { INTEL_GEN(rt_write), INTEL_GEN(rt_write_blending), INTEL_GEN(typed_write), INTEL_GEN(media_color_processing) }
318 [GEN6_FORMAT_R32G32B32A32_FLOAT] = CAP( 1, 1, 7, 0),
319 [GEN6_FORMAT_R32G32B32A32_SINT] = CAP( 1, 0, 7, 0),
320 [GEN6_FORMAT_R32G32B32A32_UINT] = CAP( 1, 0, 7, 0),
321 [GEN6_FORMAT_R16G16B16A16_UNORM] = CAP( 1, 4.5, 7, 6),
322 [GEN6_FORMAT_R16G16B16A16_SNORM] = CAP( 1, 6, 7, 0),
323 [GEN6_FORMAT_R16G16B16A16_SINT] = CAP( 1, 0, 7, 0),
324 [GEN6_FORMAT_R16G16B16A16_UINT] = CAP( 1, 0, 7, 0),
325 [GEN6_FORMAT_R16G16B16A16_FLOAT] = CAP( 1, 1, 7, 0),
326 [GEN6_FORMAT_R32G32_FLOAT] = CAP( 1, 1, 7, 0),
327 [GEN6_FORMAT_R32G32_SINT] = CAP( 1, 0, 7, 0),
328 [GEN6_FORMAT_R32G32_UINT] = CAP( 1, 0, 7, 0),
329 [GEN6_FORMAT_B8G8R8A8_UNORM] = CAP( 1, 1, 7, 6),
330 [GEN6_FORMAT_B8G8R8A8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
331 [GEN6_FORMAT_R10G10B10A2_UNORM] = CAP( 1, 1, 7, 6),
332 [GEN6_FORMAT_R10G10B10A2_UNORM_SRGB] = CAP( 0, 0, 0, 6),
333 [GEN6_FORMAT_R10G10B10A2_UINT] = CAP( 1, 0, 7, 0),
334 [GEN6_FORMAT_R8G8B8A8_UNORM] = CAP( 1, 1, 7, 6),
335 [GEN6_FORMAT_R8G8B8A8_UNORM_SRGB] = CAP( 1, 1, 0, 6),
336 [GEN6_FORMAT_R8G8B8A8_SNORM] = CAP( 1, 6, 7, 0),
337 [GEN6_FORMAT_R8G8B8A8_SINT] = CAP( 1, 0, 7, 0),
338 [GEN6_FORMAT_R8G8B8A8_UINT] = CAP( 1, 0, 7, 0),
339 [GEN6_FORMAT_R16G16_UNORM] = CAP( 1, 4.5, 7, 0),
340 [GEN6_FORMAT_R16G16_SNORM] = CAP( 1, 6, 7, 0),
341 [GEN6_FORMAT_R16G16_SINT] = CAP( 1, 0, 7, 0),
342 [GEN6_FORMAT_R16G16_UINT] = CAP( 1, 0, 7, 0),
343 [GEN6_FORMAT_R16G16_FLOAT] = CAP( 1, 1, 7, 0),
344 [GEN6_FORMAT_B10G10R10A2_UNORM] = CAP( 1, 1, 7, 6),
345 [GEN6_FORMAT_B10G10R10A2_UNORM_SRGB] = CAP( 1, 1, 0, 6),
346 [GEN6_FORMAT_R11G11B10_FLOAT] = CAP( 1, 1, 7, 0),
347 [GEN6_FORMAT_R32_SINT] = CAP( 1, 0, 7, 0),
348 [GEN6_FORMAT_R32_UINT] = CAP( 1, 0, 7, 0),
349 [GEN6_FORMAT_R32_FLOAT] = CAP( 1, 1, 7, 0),
350 [GEN6_FORMAT_B8G8R8X8_UNORM] = CAP( 0, 0, 0, 6),
351 [GEN6_FORMAT_B5G6R5_UNORM] = CAP( 1, 1, 7, 0),
352 [GEN6_FORMAT_B5G6R5_UNORM_SRGB] = CAP( 1, 1, 0, 0),
353 [GEN6_FORMAT_B5G5R5A1_UNORM] = CAP( 1, 1, 7, 0),
354 [GEN6_FORMAT_B5G5R5A1_UNORM_SRGB] = CAP( 1, 1, 0, 0),
355 [GEN6_FORMAT_B4G4R4A4_UNORM] = CAP( 1, 1, 7, 0),
356 [GEN6_FORMAT_B4G4R4A4_UNORM_SRGB] = CAP( 1, 1, 0, 0),
357 [GEN6_FORMAT_R8G8_UNORM] = CAP( 1, 1, 7, 0),
358 [GEN6_FORMAT_R8G8_SNORM] = CAP( 1, 6, 7, 0),
359 [GEN6_FORMAT_R8G8_SINT] = CAP( 1, 0, 7, 0),
360 [GEN6_FORMAT_R8G8_UINT] = CAP( 1, 0, 7, 0),
361 [GEN6_FORMAT_R16_UNORM] = CAP( 1, 4.5, 7, 7),
362 [GEN6_FORMAT_R16_SNORM] = CAP( 1, 6, 7, 0),
363 [GEN6_FORMAT_R16_SINT] = CAP( 1, 0, 7, 0),
364 [GEN6_FORMAT_R16_UINT] = CAP( 1, 0, 7, 0),
365 [GEN6_FORMAT_R16_FLOAT] = CAP( 1, 1, 7, 0),
366 [GEN6_FORMAT_B5G5R5X1_UNORM] = CAP( 1, 1, 7, 0),
367 [GEN6_FORMAT_B5G5R5X1_UNORM_SRGB] = CAP( 1, 1, 0, 0),
368 [GEN6_FORMAT_R8_UNORM] = CAP( 1, 1, 7, 0),
369 [GEN6_FORMAT_R8_SNORM] = CAP( 1, 6, 7, 0),
370 [GEN6_FORMAT_R8_SINT] = CAP( 1, 0, 7, 0),
371 [GEN6_FORMAT_R8_UINT] = CAP( 1, 0, 7, 0),
372 [GEN6_FORMAT_A8_UNORM] = CAP( 1, 1, 7, 0),
373 [GEN6_FORMAT_YCRCB_NORMAL] = CAP( 1, 0, 0, 6),
374 [GEN6_FORMAT_YCRCB_SWAPUVY] = CAP( 1, 0, 0, 6),
375 [GEN6_FORMAT_YCRCB_SWAPUV] = CAP( 1, 0, 0, 6),
376 [GEN6_FORMAT_YCRCB_SWAPY] = CAP( 1, 0, 0, 6),
377#undef CAP
378};
379
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]380static const int intel_color_mapping[XGL_MAX_CH_FMT + 1][9] = {
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]381 [XGL_CH_FMT_B5G6R5] = { GEN6_FORMAT_B5G6R5_UNORM,
382 0,
383 0,
384 0,
385 0,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]386 GEN6_FORMAT_B5G6R5_UNORM_SRGB,
387 0,
388 0,
389 0, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]390 [XGL_CH_FMT_R8] = { GEN6_FORMAT_R8_UNORM,
391 GEN6_FORMAT_R8_SNORM,
392 GEN6_FORMAT_R8_UINT,
393 GEN6_FORMAT_R8_SINT,
394 0,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]395 0,
396 0,
397 GEN6_FORMAT_R8_USCALED,
398 GEN6_FORMAT_R8_SSCALED, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]399 [XGL_CH_FMT_R8G8] = { GEN6_FORMAT_R8G8_UNORM,
400 GEN6_FORMAT_R8G8_SNORM,
401 GEN6_FORMAT_R8G8_UINT,
402 GEN6_FORMAT_R8G8_SINT,
403 0,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]404 0,
405 0,
406 GEN6_FORMAT_R8G8_USCALED,
407 GEN6_FORMAT_R8G8_SSCALED, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]408 [XGL_CH_FMT_R8G8B8A8] = { GEN6_FORMAT_R8G8B8A8_UNORM,
409 GEN6_FORMAT_R8G8B8A8_SNORM,
410 GEN6_FORMAT_R8G8B8A8_UINT,
411 GEN6_FORMAT_R8G8B8A8_SINT,
412 0,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]413 GEN6_FORMAT_R8G8B8A8_UNORM_SRGB,
414 0,
415 GEN6_FORMAT_R8G8B8A8_USCALED,
416 GEN6_FORMAT_R8G8B8A8_SSCALED, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]417 [XGL_CH_FMT_B8G8R8A8] = { GEN6_FORMAT_B8G8R8A8_UNORM,
418 0,
419 0,
420 0,
421 0,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]422 GEN6_FORMAT_B8G8R8A8_UNORM_SRGB,
423 0,
424 0,
425 0, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]426 [XGL_CH_FMT_R11G11B10] = { 0,
427 0,
428 0,
429 0,
430 GEN6_FORMAT_R11G11B10_FLOAT,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]431 0,
432 0,
433 0,
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]434 0, },
435 [XGL_CH_FMT_R10G10B10A2] = { GEN6_FORMAT_R10G10B10A2_UNORM,
436 GEN6_FORMAT_R10G10B10A2_SNORM,
437 GEN6_FORMAT_R10G10B10A2_UINT,
438 GEN6_FORMAT_R10G10B10A2_SINT,
439 0,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]440 0,
441 0,
442 GEN6_FORMAT_R10G10B10A2_USCALED,
443 GEN6_FORMAT_R10G10B10A2_SSCALED, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]444 [XGL_CH_FMT_R16] = { GEN6_FORMAT_R16_UNORM,
445 GEN6_FORMAT_R16_SNORM,
446 GEN6_FORMAT_R16_UINT,
447 GEN6_FORMAT_R16_SINT,
448 GEN6_FORMAT_R16_FLOAT,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]449 0,
450 0,
451 GEN6_FORMAT_R16_USCALED,
452 GEN6_FORMAT_R16_SSCALED, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]453 [XGL_CH_FMT_R16G16] = { GEN6_FORMAT_R16G16_UNORM,
454 GEN6_FORMAT_R16G16_SNORM,
455 GEN6_FORMAT_R16G16_UINT,
456 GEN6_FORMAT_R16G16_SINT,
457 GEN6_FORMAT_R16G16_FLOAT,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]458 0,
459 0,
460 GEN6_FORMAT_R16G16_USCALED,
461 GEN6_FORMAT_R16G16_SSCALED, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]462 [XGL_CH_FMT_R16G16B16A16] = { GEN6_FORMAT_R16G16B16A16_UNORM,
463 GEN6_FORMAT_R16G16B16A16_SNORM,
464 GEN6_FORMAT_R16G16B16A16_UINT,
465 GEN6_FORMAT_R16G16B16A16_SINT,
466 GEN6_FORMAT_R16G16B16A16_FLOAT,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]467 0,
468 0,
469 GEN6_FORMAT_R16G16B16A16_USCALED,
470 GEN6_FORMAT_R16G16B16A16_SSCALED, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]471 [XGL_CH_FMT_R32] = { GEN6_FORMAT_R32_UNORM,
472 GEN6_FORMAT_R32_SNORM,
473 GEN6_FORMAT_R32_UINT,
474 GEN6_FORMAT_R32_SINT,
475 GEN6_FORMAT_R32_FLOAT,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]476 0,
477 0,
478 GEN6_FORMAT_R32_USCALED,
479 GEN6_FORMAT_R32_SSCALED, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]480 [XGL_CH_FMT_R32G32] = { GEN6_FORMAT_R32G32_UNORM,
481 GEN6_FORMAT_R32G32_SNORM,
482 GEN6_FORMAT_R32G32_UINT,
483 GEN6_FORMAT_R32G32_SINT,
484 GEN6_FORMAT_R32G32_FLOAT,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]485 0,
486 0,
487 GEN6_FORMAT_R32G32_USCALED,
488 GEN6_FORMAT_R32G32_SSCALED, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]489 [XGL_CH_FMT_R32G32B32] = { GEN6_FORMAT_R32G32B32_UNORM,
490 GEN6_FORMAT_R32G32B32_SNORM,
491 GEN6_FORMAT_R32G32B32_UINT,
492 GEN6_FORMAT_R32G32B32_SINT,
493 GEN6_FORMAT_R32G32B32_FLOAT,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]494 0,
495 0,
496 GEN6_FORMAT_R32G32B32_USCALED,
497 GEN6_FORMAT_R32G32B32_SSCALED, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]498 [XGL_CH_FMT_R32G32B32A32] = { GEN6_FORMAT_R32G32B32A32_UNORM,
499 GEN6_FORMAT_R32G32B32A32_SNORM,
500 GEN6_FORMAT_R32G32B32A32_UINT,
501 GEN6_FORMAT_R32G32B32A32_SINT,
502 GEN6_FORMAT_R32G32B32A32_FLOAT,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]503 0,
504 0,
505 GEN6_FORMAT_R32G32B32A32_USCALED,
506 GEN6_FORMAT_R32G32B32A32_SSCALED, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]507 [XGL_CH_FMT_R9G9B9E5] = { 0,
508 0,
509 0,
510 0,
511 GEN6_FORMAT_R9G9B9E5_SHAREDEXP,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]512 0,
513 0,
514 0,
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]515 0, },
516 [XGL_CH_FMT_BC1] = { GEN6_FORMAT_BC1_UNORM,
517 0,
518 0,
519 0,
520 0,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]521 GEN6_FORMAT_BC1_UNORM_SRGB,
522 0,
523 0,
524 0, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]525 [XGL_CH_FMT_BC2] = { GEN6_FORMAT_BC2_UNORM,
526 0,
527 0,
528 0,
529 0,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]530 GEN6_FORMAT_BC2_UNORM_SRGB,
531 0,
532 0,
533 0, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]534 [XGL_CH_FMT_BC3] = { GEN6_FORMAT_BC3_UNORM,
535 0,
536 0,
537 0,
538 0,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]539 GEN6_FORMAT_BC3_UNORM_SRGB,
540 0,
541 0,
542 0, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]543 [XGL_CH_FMT_BC4] = { GEN6_FORMAT_BC4_UNORM,
544 GEN6_FORMAT_BC4_SNORM,
545 0,
546 0,
547 0,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]548 0,
549 0,
550 0,
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]551 0, },
552 [XGL_CH_FMT_BC5] = { GEN6_FORMAT_BC5_UNORM,
553 GEN6_FORMAT_BC5_SNORM,
554 0,
555 0,
556 0,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]557 0,
558 0,
559 0,
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]560 0, },
561 [XGL_CH_FMT_BC6U] = { GEN6_FORMAT_BC6H_UF16,
562 0,
563 0,
564 0,
565 0,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]566 0,
567 0,
568 0,
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]569 0, },
570 [XGL_CH_FMT_BC6S] = { GEN6_FORMAT_BC6H_SF16,
571 0,
572 0,
573 0,
574 0,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]575 0,
576 0,
577 0,
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]578 0, },
579 [XGL_CH_FMT_BC7] = { GEN6_FORMAT_BC7_UNORM,
580 0,
581 0,
582 0,
583 0,
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]584 GEN6_FORMAT_BC7_UNORM_SRGB,
585 0,
586 0,
587 0, },
588 [XGL_CH_FMT_R8G8B8] = { GEN6_FORMAT_R8G8B8_UNORM,
589 GEN6_FORMAT_R8G8B8_SNORM,
590 GEN6_FORMAT_R8G8B8_UINT,
591 GEN6_FORMAT_R8G8B8_SINT,
592 0,
593 GEN6_FORMAT_R8G8B8_UNORM_SRGB,
594 0,
595 GEN6_FORMAT_R8G8B8_USCALED,
596 GEN6_FORMAT_R8G8B8_SSCALED, },
597 [XGL_CH_FMT_R16G16B16] = { GEN6_FORMAT_R16G16B16_UNORM,
598 GEN6_FORMAT_R16G16B16_SNORM,
599 GEN6_FORMAT_R16G16B16_UINT,
600 GEN6_FORMAT_R16G16B16_SINT,
601 0,
602 0,
603 0,
604 GEN6_FORMAT_R16G16B16_USCALED,
605 GEN6_FORMAT_R16G16B16_SSCALED, },
606 [XGL_CH_FMT_B10G10R10A2] = { GEN6_FORMAT_B10G10R10A2_UNORM,
607 GEN6_FORMAT_B10G10R10A2_SNORM,
608 GEN6_FORMAT_B10G10R10A2_UINT,
609 GEN6_FORMAT_B10G10R10A2_SINT,
610 0,
611 GEN6_FORMAT_B10G10R10A2_UNORM_SRGB,
612 0,
613 GEN6_FORMAT_B10G10R10A2_USCALED,
614 GEN6_FORMAT_B10G10R10A2_SSCALED, },
615 [XGL_CH_FMT_R64] = { 0,
616 0,
617 0,
618 0,
619 GEN6_FORMAT_R64_FLOAT,
620 0,
621 0,
622 0,
623 0, },
624 [XGL_CH_FMT_R64G64] = { 0,
625 0,
626 0,
627 0,
628 GEN6_FORMAT_R64G64_FLOAT,
629 0,
630 0,
631 0,
632 0, },
633 [XGL_CH_FMT_R64G64B64] = { 0,
634 0,
635 0,
636 0,
637 GEN6_FORMAT_R64G64B64_FLOAT,
638 0,
639 0,
640 0,
641 0, },
642 [XGL_CH_FMT_R64G64B64A64] = { 0,
643 0,
644 0,
645 0,
646 GEN6_FORMAT_R64G64B64A64_FLOAT,
647 0,
648 0,
649 0,
650 0, },
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]651};
652
Chia-I Wufb240262014-08-16 13:26:06 +0800[diff] [blame]653int intel_format_translate_color(const struct intel_gpu *gpu,
654 XGL_FORMAT format)
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]655{
656 int fmt;
657
658 assert(format.numericFormat != XGL_NUM_FMT_UNDEFINED &&
659 format.numericFormat != XGL_NUM_FMT_DS);
660
661 fmt = intel_color_mapping[format.channelFormat][format.numericFormat - 1];
662
663 /* GEN6_FORMAT_R32G32B32A32_FLOAT happens to be 0 */
664 if (format.channelFormat == XGL_CH_FMT_R32G32B32A32 &&
665 format.numericFormat == XGL_NUM_FMT_FLOAT)
666 assert(fmt == 0);
667 else if (!fmt)
668 fmt = -1;
669
670 return fmt;
671}
672
673static XGL_FLAGS intel_format_get_color_features(const struct intel_dev *dev,
674 XGL_FORMAT format)
675{
Chia-I Wufb240262014-08-16 13:26:06 +0800[diff] [blame]676 const int fmt = intel_format_translate_color(dev->gpu, format);
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]677 const struct intel_vf_cap *vf;
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]678 const struct intel_sampler_cap *sampler;
679 const struct intel_dp_cap *dp;
680 XGL_FLAGS features;
681
682 if (fmt < 0)
683 return 0;
684
685 sampler = (fmt < ARRAY_SIZE(intel_sampler_caps)) ?
686 &intel_sampler_caps[fmt] : NULL;
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]687 vf = (fmt < ARRAY_SIZE(intel_vf_caps)) ? &intel_vf_caps[fmt] : NULL;
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]688 dp = (fmt < ARRAY_SIZE(intel_dp_caps)) ? &intel_dp_caps[fmt] : NULL;
689
690 features = XGL_FORMAT_MEMORY_SHADER_ACCESS_BIT;
691
Chia-I Wu94192892014-08-08 21:27:45 +0800[diff] [blame]692#define TEST(dev, func, cap) ((func) && (func)->cap && \
693 intel_gpu_gen((dev)->gpu) >= (func)->cap)
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]694 if (TEST(dev, vf, vertex_element)) {
695 /* no feature bit to set */
696 }
697
Chia-I Wu94192892014-08-08 21:27:45 +0800[diff] [blame]698 if (TEST(dev, sampler, sampling)) {
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]699 if (format.numericFormat == XGL_NUM_FMT_UINT ||
700 format.numericFormat == XGL_NUM_FMT_SINT ||
Chia-I Wu94192892014-08-08 21:27:45 +0800[diff] [blame]701 TEST(dev, sampler, filtering))
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]702 features |= XGL_FORMAT_IMAGE_SHADER_READ_BIT;
703 }
704
Chia-I Wu94192892014-08-08 21:27:45 +0800[diff] [blame]705 if (TEST(dev, dp, typed_write))
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]706 features |= XGL_FORMAT_IMAGE_SHADER_WRITE_BIT;
707
Chia-I Wu94192892014-08-08 21:27:45 +0800[diff] [blame]708 if (TEST(dev, dp, rt_write)) {
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]709 features |= XGL_FORMAT_COLOR_ATTACHMENT_WRITE_BIT;
710
Chia-I Wu94192892014-08-08 21:27:45 +0800[diff] [blame]711 if (TEST(dev, dp, rt_write_blending))
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]712 features |= XGL_FORMAT_COLOR_ATTACHMENT_BLEND_BIT;
713
714 if (features & XGL_FORMAT_IMAGE_SHADER_READ_BIT) {
715 features |= XGL_FORMAT_IMAGE_COPY_BIT |
716 XGL_FORMAT_CONVERSION_BIT;
717 }
718 }
719#undef TEST
720
721 return features;
722}
723
724static XGL_FLAGS intel_format_get_ds_features(const struct intel_dev *dev,
725 XGL_FORMAT format)
726{
727 XGL_FLAGS features;
728
729 assert(format.numericFormat == XGL_NUM_FMT_DS);
730
731 switch (format.channelFormat) {
732 case XGL_CH_FMT_R8:
733 features = XGL_FORMAT_STENCIL_ATTACHMENT_BIT;;
734 break;
735 case XGL_CH_FMT_R16:
736 case XGL_CH_FMT_R32:
737 features = XGL_FORMAT_DEPTH_ATTACHMENT_BIT;
738 break;
739 case XGL_CH_FMT_R32G8:
740 features = XGL_FORMAT_DEPTH_ATTACHMENT_BIT |
741 XGL_FORMAT_STENCIL_ATTACHMENT_BIT;
742 break;
743 default:
744 features = 0;
745 break;
746 }
747
748 return features;
749}
750
751static XGL_FLAGS intel_format_get_raw_features(const struct intel_dev *dev,
752 XGL_FORMAT format)
753{
754 assert(format.numericFormat == XGL_NUM_FMT_UNDEFINED);
755
756 return (format.channelFormat == XGL_CH_FMT_UNDEFINED) ?
757 XGL_FORMAT_MEMORY_SHADER_ACCESS_BIT : 0;
758}
759
760static void intel_format_get_props(const struct intel_dev *dev,
761 XGL_FORMAT format,
762 XGL_FORMAT_PROPERTIES *props)
763{
764 switch (format.numericFormat) {
765 case XGL_NUM_FMT_UNDEFINED:
766 props->linearTilingFeatures =
767 intel_format_get_raw_features(dev, format);
768 props->optimalTilingFeatures = 0;
769 break;
770 case XGL_NUM_FMT_UNORM:
771 case XGL_NUM_FMT_SNORM:
772 case XGL_NUM_FMT_UINT:
773 case XGL_NUM_FMT_SINT:
774 case XGL_NUM_FMT_FLOAT:
775 case XGL_NUM_FMT_SRGB:
Chia-I Wuc581bd52015-01-18 14:51:02 +0800[diff] [blame]776 case XGL_NUM_FMT_USCALED:
777 case XGL_NUM_FMT_SSCALED:
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]778 props->linearTilingFeatures =
779 intel_format_get_color_features(dev, format);
780 props->optimalTilingFeatures = props->linearTilingFeatures;
781 break;
782 case XGL_NUM_FMT_DS:
783 props->linearTilingFeatures = 0;
784 props->optimalTilingFeatures =
785 intel_format_get_ds_features(dev, format);
786 break;
787 default:
788 props->linearTilingFeatures = 0;
789 props->optimalTilingFeatures = 0;
790 break;
791 }
792}
793
Chia-I Wu96177272015-01-03 15:27:41 +0800[diff] [blame]794ICD_EXPORT XGL_RESULT XGLAPI xglGetFormatInfo(
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]795 XGL_DEVICE device,
796 XGL_FORMAT format,
797 XGL_FORMAT_INFO_TYPE infoType,
798 XGL_SIZE* pDataSize,
799 XGL_VOID* pData)
800{
801 const struct intel_dev *dev = intel_dev(device);
802 XGL_RESULT ret = XGL_SUCCESS;
803
804 switch (infoType) {
805 case XGL_INFO_TYPE_FORMAT_PROPERTIES:
806 *pDataSize = sizeof(XGL_FORMAT_PROPERTIES);
Jon Ashburn408daec2014-12-05 09:23:52 -0700[diff] [blame]807 if (pData == NULL)
808 return ret;
Chia-I Wuac6ba132014-08-07 14:21:43 +0800[diff] [blame]809 intel_format_get_props(dev, format, pData);
810 break;
811 default:
812 ret = XGL_ERROR_INVALID_VALUE;
813 break;
814 }
815
816 return ret;
817}