blob: 2e86ba96ae2efe3427401a90f049f05cae53d671 [file] [log] [blame]
Chia-I Wue6073342014-11-30 09:43:42 +08001#ifndef GEN_RENDER_XML
2#define GEN_RENDER_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7https://github.com/olvaffe/envytools/
8git clone https://github.com/olvaffe/envytools.git
9
Chia-I Wu97aa4de2015-03-05 15:43:16 -070010Copyright (C) 2014-2015 by the following authors:
Chia-I Wue6073342014-11-30 09:43:42 +080011- Chia-I Wu <olvaffe@gmail.com> (olv)
12
13Permission is hereby granted, free of charge, to any person obtaining
14a copy of this software and associated documentation files (the
15"Software"), to deal in the Software without restriction, including
16without limitation the rights to use, copy, modify, merge, publish,
17distribute, sublicense, and/or sell copies of the Software, and to
18permit persons to whom the Software is furnished to do so, subject to
19the following conditions:
20
21The above copyright notice and this permission notice (including the
22next paragraph) shall be included in all copies or substantial
23portions of the Software.
24
25THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
28IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
29LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
30OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
31WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32*/
33
34
35#define GEN6_RENDER_TYPE__MASK 0xe0000000
36#define GEN6_RENDER_TYPE__SHIFT 29
37#define GEN6_RENDER_TYPE_RENDER (0x3 << 29)
38#define GEN6_RENDER_SUBTYPE__MASK 0x18000000
39#define GEN6_RENDER_SUBTYPE__SHIFT 27
40#define GEN6_RENDER_SUBTYPE_COMMON (0x0 << 27)
41#define GEN6_RENDER_SUBTYPE_SINGLE_DW (0x1 << 27)
42#define GEN6_RENDER_SUBTYPE_MEDIA (0x2 << 27)
43#define GEN6_RENDER_SUBTYPE_3D (0x3 << 27)
44#define GEN6_RENDER_OPCODE__MASK 0x07ff0000
45#define GEN6_RENDER_OPCODE__SHIFT 16
46#define GEN6_RENDER_OPCODE_STATE_BASE_ADDRESS (0x101 << 16)
47#define GEN6_RENDER_OPCODE_STATE_SIP (0x102 << 16)
48#define GEN6_RENDER_OPCODE_3DSTATE_VF_STATISTICS (0xb << 16)
49#define GEN6_RENDER_OPCODE_PIPELINE_SELECT (0x104 << 16)
50#define GEN6_RENDER_OPCODE_MEDIA_VFE_STATE (0x0 << 16)
51#define GEN6_RENDER_OPCODE_MEDIA_CURBE_LOAD (0x1 << 16)
52#define GEN6_RENDER_OPCODE_MEDIA_INTERFACE_DESCRIPTOR_LOAD (0x2 << 16)
53#define GEN6_RENDER_OPCODE_MEDIA_STATE_FLUSH (0x4 << 16)
54#define GEN7_RENDER_OPCODE_GPGPU_WALKER (0x105 << 16)
55#define GEN6_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS (0x1 << 16)
56#define GEN6_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS (0x2 << 16)
57#define GEN7_RENDER_OPCODE_3DSTATE_CLEAR_PARAMS (0x4 << 16)
58#define GEN6_RENDER_OPCODE_3DSTATE_URB (0x5 << 16)
59#define GEN7_RENDER_OPCODE_3DSTATE_DEPTH_BUFFER (0x5 << 16)
60#define GEN7_RENDER_OPCODE_3DSTATE_STENCIL_BUFFER (0x6 << 16)
61#define GEN7_RENDER_OPCODE_3DSTATE_HIER_DEPTH_BUFFER (0x7 << 16)
62#define GEN6_RENDER_OPCODE_3DSTATE_VERTEX_BUFFERS (0x8 << 16)
63#define GEN6_RENDER_OPCODE_3DSTATE_VERTEX_ELEMENTS (0x9 << 16)
64#define GEN6_RENDER_OPCODE_3DSTATE_INDEX_BUFFER (0xa << 16)
65#define GEN75_RENDER_OPCODE_3DSTATE_VF (0xc << 16)
66#define GEN6_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS (0xd << 16)
Chia-I Wu97aa4de2015-03-05 15:43:16 -070067#define GEN8_RENDER_OPCODE_3DSTATE_MULTISAMPLE (0xd << 16)
Chia-I Wue6073342014-11-30 09:43:42 +080068#define GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS (0xe << 16)
69#define GEN6_RENDER_OPCODE_3DSTATE_SCISSOR_STATE_POINTERS (0xf << 16)
70#define GEN6_RENDER_OPCODE_3DSTATE_VS (0x10 << 16)
71#define GEN6_RENDER_OPCODE_3DSTATE_GS (0x11 << 16)
72#define GEN6_RENDER_OPCODE_3DSTATE_CLIP (0x12 << 16)
73#define GEN6_RENDER_OPCODE_3DSTATE_SF (0x13 << 16)
74#define GEN6_RENDER_OPCODE_3DSTATE_WM (0x14 << 16)
75#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS (0x15 << 16)
76#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_GS (0x16 << 16)
77#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS (0x17 << 16)
78#define GEN6_RENDER_OPCODE_3DSTATE_SAMPLE_MASK (0x18 << 16)
79#define GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_HS (0x19 << 16)
80#define GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_DS (0x1a << 16)
81#define GEN7_RENDER_OPCODE_3DSTATE_HS (0x1b << 16)
82#define GEN7_RENDER_OPCODE_3DSTATE_TE (0x1c << 16)
83#define GEN7_RENDER_OPCODE_3DSTATE_DS (0x1d << 16)
84#define GEN7_RENDER_OPCODE_3DSTATE_STREAMOUT (0x1e << 16)
85#define GEN7_RENDER_OPCODE_3DSTATE_SBE (0x1f << 16)
86#define GEN7_RENDER_OPCODE_3DSTATE_PS (0x20 << 16)
87#define GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP (0x21 << 16)
88#define GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC (0x23 << 16)
89#define GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS (0x24 << 16)
90#define GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS (0x25 << 16)
91#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_VS (0x26 << 16)
92#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_HS (0x27 << 16)
93#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_DS (0x28 << 16)
94#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_GS (0x29 << 16)
95#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_PS (0x2a << 16)
96#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_VS (0x2b << 16)
97#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_HS (0x2c << 16)
98#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_DS (0x2d << 16)
99#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_GS (0x2e << 16)
100#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_PS (0x2f << 16)
101#define GEN7_RENDER_OPCODE_3DSTATE_URB_VS (0x30 << 16)
102#define GEN7_RENDER_OPCODE_3DSTATE_URB_HS (0x31 << 16)
103#define GEN7_RENDER_OPCODE_3DSTATE_URB_DS (0x32 << 16)
104#define GEN7_RENDER_OPCODE_3DSTATE_URB_GS (0x33 << 16)
Chia-I Wu97aa4de2015-03-05 15:43:16 -0700105#define GEN8_RENDER_OPCODE_3DSTATE_VF_INSTANCING (0x49 << 16)
106#define GEN8_RENDER_OPCODE_3DSTATE_VF_SGVS (0x4a << 16)
107#define GEN8_RENDER_OPCODE_3DSTATE_VF_TOPOLOGY (0x4b << 16)
108#define GEN8_RENDER_OPCODE_3DSTATE_WM_CHROMAKEY (0x4c << 16)
109#define GEN8_RENDER_OPCODE_3DSTATE_PS_BLEND (0x4d << 16)
110#define GEN8_RENDER_OPCODE_3DSTATE_WM_DEPTH_STENCIL (0x4e << 16)
111#define GEN8_RENDER_OPCODE_3DSTATE_PS_EXTRA (0x4f << 16)
112#define GEN8_RENDER_OPCODE_3DSTATE_RASTER (0x50 << 16)
113#define GEN8_RENDER_OPCODE_3DSTATE_SBE_SWIZ (0x51 << 16)
114#define GEN8_RENDER_OPCODE_3DSTATE_WM_HZ_OP (0x52 << 16)
Chia-I Wue6073342014-11-30 09:43:42 +0800115#define GEN6_RENDER_OPCODE_3DSTATE_DRAWING_RECTANGLE (0x100 << 16)
116#define GEN6_RENDER_OPCODE_3DSTATE_DEPTH_BUFFER (0x105 << 16)
117#define GEN6_RENDER_OPCODE_3DSTATE_POLY_STIPPLE_OFFSET (0x106 << 16)
118#define GEN6_RENDER_OPCODE_3DSTATE_POLY_STIPPLE_PATTERN (0x107 << 16)
119#define GEN6_RENDER_OPCODE_3DSTATE_LINE_STIPPLE (0x108 << 16)
120#define GEN6_RENDER_OPCODE_3DSTATE_AA_LINE_PARAMETERS (0x10a << 16)
121#define GEN6_RENDER_OPCODE_3DSTATE_GS_SVB_INDEX (0x10b << 16)
122#define GEN6_RENDER_OPCODE_3DSTATE_MULTISAMPLE (0x10d << 16)
123#define GEN6_RENDER_OPCODE_3DSTATE_STENCIL_BUFFER (0x10e << 16)
124#define GEN6_RENDER_OPCODE_3DSTATE_HIER_DEPTH_BUFFER (0x10f << 16)
125#define GEN6_RENDER_OPCODE_3DSTATE_CLEAR_PARAMS (0x110 << 16)
126#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_VS (0x112 << 16)
127#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_HS (0x113 << 16)
128#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_DS (0x114 << 16)
129#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_GS (0x115 << 16)
130#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_PS (0x116 << 16)
131#define GEN7_RENDER_OPCODE_3DSTATE_SO_DECL_LIST (0x117 << 16)
132#define GEN7_RENDER_OPCODE_3DSTATE_SO_BUFFER (0x118 << 16)
Chia-I Wu97aa4de2015-03-05 15:43:16 -0700133#define GEN8_RENDER_OPCODE_3DSTATE_SAMPLE_PATTERN (0x11c << 16)
Chia-I Wue6073342014-11-30 09:43:42 +0800134#define GEN6_RENDER_OPCODE_PIPE_CONTROL (0x200 << 16)
135#define GEN6_RENDER_OPCODE_3DPRIMITIVE (0x300 << 16)
136#define GEN6_RENDER_LENGTH__MASK 0x000000ff
137#define GEN6_RENDER_LENGTH__SHIFT 0
138#define GEN6_MOCS_LLC__MASK 0x00000003
139#define GEN6_MOCS_LLC__SHIFT 0
140#define GEN6_MOCS_LLC_PTE 0x0
141#define GEN6_MOCS_LLC_UC 0x1
Chia-I Wu97aa4de2015-03-05 15:43:16 -0700142#define GEN6_MOCS_LLC_WB 0x2
Chia-I Wue6073342014-11-30 09:43:42 +0800143#define GEN7_MOCS_LLC__MASK 0x00000002
144#define GEN7_MOCS_LLC__SHIFT 1
145#define GEN7_MOCS_LLC_PTE (0x0 << 1)
Chia-I Wu97aa4de2015-03-05 15:43:16 -0700146#define GEN7_MOCS_LLC_WB (0x1 << 1)
Chia-I Wue6073342014-11-30 09:43:42 +0800147#define GEN75_MOCS_LLC__MASK 0x00000006
148#define GEN75_MOCS_LLC__SHIFT 1
149#define GEN75_MOCS_LLC_PTE (0x0 << 1)
150#define GEN75_MOCS_LLC_UC (0x1 << 1)
Chia-I Wu97aa4de2015-03-05 15:43:16 -0700151#define GEN75_MOCS_LLC_WB (0x2 << 1)
Chia-I Wue6073342014-11-30 09:43:42 +0800152#define GEN75_MOCS_LLC_ELLC (0x3 << 1)
153#define GEN7_MOCS_L3__MASK 0x00000001
154#define GEN7_MOCS_L3__SHIFT 0
155#define GEN7_MOCS_L3_UC 0x0
Chia-I Wu97aa4de2015-03-05 15:43:16 -0700156#define GEN7_MOCS_L3_WB 0x1
157#define GEN8_MOCS_MT__MASK 0x00000060
158#define GEN8_MOCS_MT__SHIFT 5
159#define GEN8_MOCS_MT_PTE (0x0 << 5)
160#define GEN8_MOCS_MT_UC (0x1 << 5)
161#define GEN8_MOCS_MT_WT (0x2 << 5)
162#define GEN8_MOCS_MT_WB (0x3 << 5)
163#define GEN8_MOCS_CT__MASK 0x00000018
164#define GEN8_MOCS_CT__SHIFT 3
165#define GEN8_MOCS_CT_ELLC (0x0 << 3)
166#define GEN8_MOCS_CT_LLC_ONLY (0x1 << 3)
167#define GEN8_MOCS_CT_LLC (0x2 << 3)
168#define GEN8_MOCS_CT_L3 (0x3 << 3)
169#define GEN9_MOCS__MASK 0x0000007f
170#define GEN9_MOCS__SHIFT 0
171#define GEN9_MOCS_MT_WT_CT_L3 0x5
172#define GEN9_MOCS_MT_WB_CT_L3 0x9
173#define GEN6_SBA_ADDR__MASK 0xfffff000
174#define GEN6_SBA_ADDR__SHIFT 12
175#define GEN6_SBA_ADDR__SHR 12
176#define GEN6_SBA_MOCS__MASK 0x00000f00
177#define GEN6_SBA_MOCS__SHIFT 8
178#define GEN8_SBA_MOCS__MASK 0x000007f0
179#define GEN8_SBA_MOCS__SHIFT 4
180#define GEN6_SBA_ADDR_MODIFIED (0x1 << 0)
181#define GEN6_BINDING_TABLE_ADDR__MASK 0x0000ffe0
182#define GEN6_BINDING_TABLE_ADDR__SHIFT 5
183#define GEN6_BINDING_TABLE_ADDR__SHR 5
184#define GEN6_STATE_BASE_ADDRESS__SIZE 19
Chia-I Wue6073342014-11-30 09:43:42 +0800185
186
Chia-I Wu97aa4de2015-03-05 15:43:16 -0700187#define GEN6_SBA_DW1_GENERAL_STATELESS_MOCS__MASK 0x000000f0
188#define GEN6_SBA_DW1_GENERAL_STATELESS_MOCS__SHIFT 4
189#define GEN6_SBA_DW1_GENERAL_STATELESS_FORCE_WRITE_THRU (0x1 << 3)
Chia-I Wue6073342014-11-30 09:43:42 +0800190
191
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Chia-I Wu97aa4de2015-03-05 15:43:16 -0700199
200
201
202
203#define GEN8_SBA_DW3_STATELESS_MOCS__MASK 0x007f0000
204#define GEN8_SBA_DW3_STATELESS_MOCS__SHIFT 16
205
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220
221#define GEN6_STATE_SIP__SIZE 3
Chia-I Wue6073342014-11-30 09:43:42 +0800222
223
224#define GEN6_SIP_DW1_KERNEL_ADDR__MASK 0xfffffff0
225#define GEN6_SIP_DW1_KERNEL_ADDR__SHIFT 4
226#define GEN6_SIP_DW1_KERNEL_ADDR__SHR 4
227
Chia-I Wu97aa4de2015-03-05 15:43:16 -0700228
Chia-I Wue6073342014-11-30 09:43:42 +0800229#define GEN6_PIPELINE_SELECT__SIZE 1
230
231#define GEN6_PIPELINE_SELECT_DW0_SELECT__MASK 0x00000003
232#define GEN6_PIPELINE_SELECT_DW0_SELECT__SHIFT 0
233#define GEN6_PIPELINE_SELECT_DW0_SELECT_3D 0x0
234#define GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA 0x1
235#define GEN7_PIPELINE_SELECT_DW0_SELECT_GPGPU 0x2
Chia-I Wu97aa4de2015-03-05 15:43:16 -0700236#define GEN9_PIPELINE_SELECT_DW0_SELECT__MASK 0x00000700
237#define GEN9_PIPELINE_SELECT_DW0_SELECT__SHIFT 8
238#define GEN9_PIPELINE_SELECT_DW0_SELECT_3D (0x3 << 8)
239
240#define GEN6_PIPE_CONTROL__SIZE 6
241
242
243#define GEN7_PIPE_CONTROL_USE_GGTT (0x1 << 24)
244#define GEN7_PIPE_CONTROL_LRI_WRITE__MASK 0x00800000
245#define GEN7_PIPE_CONTROL_LRI_WRITE__SHIFT 23
246#define GEN7_PIPE_CONTROL_LRI_WRITE_NONE (0x0 << 23)
247#define GEN7_PIPE_CONTROL_LRI_WRITE_IMM (0x1 << 23)
248#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_ENABLE (0x1 << 22)
249#define GEN6_PIPE_CONTROL_STORE_DATA_INDEX (0x1 << 21)
250#define GEN6_PIPE_CONTROL_CS_STALL (0x1 << 20)
251#define GEN6_PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (0x1 << 19)
252#define GEN6_PIPE_CONTROL_TLB_INVALIDATE (0x1 << 18)
253#define GEN6_PIPE_CONTROL_SYNC_GFDT_SURFACE (0x1 << 17)
254#define GEN6_PIPE_CONTROL_GENERIC_MEDIA_STATE_CLEAR (0x1 << 16)
255#define GEN6_PIPE_CONTROL_WRITE__MASK 0x0000c000
256#define GEN6_PIPE_CONTROL_WRITE__SHIFT 14
257#define GEN6_PIPE_CONTROL_WRITE_NONE (0x0 << 14)
258#define GEN6_PIPE_CONTROL_WRITE_IMM (0x1 << 14)
259#define GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT (0x2 << 14)
260#define GEN6_PIPE_CONTROL_WRITE_TIMESTAMP (0x3 << 14)
261#define GEN6_PIPE_CONTROL_DEPTH_STALL (0x1 << 13)
262#define GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH (0x1 << 12)
263#define GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (0x1 << 11)
264#define GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (0x1 << 10)
265#define GEN6_PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE (0x1 << 9)
266#define GEN6_PIPE_CONTROL_NOTIFY_ENABLE (0x1 << 8)
267#define GEN7_PIPE_CONTROL_WRITE_IMM_FLUSH (0x1 << 7)
268#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_APP_ID__MASK 0x00000040
269#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_APP_ID__SHIFT 6
270#define GEN7_PIPE_CONTROL_DC_FLUSH (0x1 << 5)
271#define GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE (0x1 << 4)
272#define GEN6_PIPE_CONTROL_CONSTANT_CACHE_INVALIDATE (0x1 << 3)
273#define GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE (0x1 << 2)
274#define GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL (0x1 << 1)
275#define GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH (0x1 << 0)
276
277#define GEN6_PIPE_CONTROL_DW2_USE_GGTT (0x1 << 2)
278#define GEN6_PIPE_CONTROL_DW2_ADDR__MASK 0xfffffff8
279#define GEN6_PIPE_CONTROL_DW2_ADDR__SHIFT 3
280#define GEN6_PIPE_CONTROL_DW2_ADDR__SHR 3
281
282#define GEN7_PIPE_CONTROL_DW2_ADDR__MASK 0xfffffffc
283#define GEN7_PIPE_CONTROL_DW2_ADDR__SHIFT 2
284#define GEN7_PIPE_CONTROL_DW2_ADDR__SHR 2
285
286#define GEN8_PIPE_CONTROL_DW2_ADDR__MASK 0xfffffffc
287#define GEN8_PIPE_CONTROL_DW2_ADDR__SHIFT 2
288#define GEN8_PIPE_CONTROL_DW2_ADDR__SHR 2
289
290
291
Chia-I Wue6073342014-11-30 09:43:42 +0800292
293
294#endif /* GEN_RENDER_XML */