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Chia-I Wu6464ff22014-08-05 11:59:54 +08001/*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2012-2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28#ifndef INTEL_WINSYS_H
29#define INTEL_WINSYS_H
30
Chia-I Wu32a22462014-08-26 14:13:46 +080031#include <stddef.h>
Chia-I Wu770b3092014-08-05 14:22:03 +080032#include <stdint.h>
33#include <stdbool.h>
Chia-I Wu6464ff22014-08-05 11:59:54 +080034
35/* this is compatible with i915_drm.h's definitions */
36enum intel_ring_type {
37 INTEL_RING_RENDER = 1,
38 INTEL_RING_BSD = 2,
39 INTEL_RING_BLT = 3,
40 INTEL_RING_VEBOX = 4,
41};
42
43/* this is compatible with i915_drm.h's definitions */
44enum intel_exec_flag {
45 INTEL_EXEC_GEN7_SOL_RESET = 1 << 8,
46};
47
48/* this is compatible with i915_drm.h's definitions */
Chia-I Wu32a22462014-08-26 14:13:46 +080049enum intel_reloc_flag {
50 INTEL_RELOC_FENCE = 1 << 0,
51 INTEL_RELOC_GGTT = 1 << 1,
52 INTEL_RELOC_WRITE = 1 << 2,
Chia-I Wu6464ff22014-08-05 11:59:54 +080053};
54
55/* this is compatible with i915_drm.h's definitions */
56enum intel_tiling_mode {
57 INTEL_TILING_NONE = 0,
58 INTEL_TILING_X = 1,
59 INTEL_TILING_Y = 2,
60};
61
Chia-I Wu770b3092014-08-05 14:22:03 +080062enum intel_winsys_handle_type {
63 INTEL_WINSYS_HANDLE_SHARED,
64 INTEL_WINSYS_HANDLE_KMS,
65 INTEL_WINSYS_HANDLE_FD,
66};
67
Chia-I Wuf13ed3c2015-02-22 14:09:00 +080068struct icd_instance;
Chia-I Wu6464ff22014-08-05 11:59:54 +080069struct intel_winsys;
Chia-I Wu6464ff22014-08-05 11:59:54 +080070struct intel_bo;
71
72struct intel_winsys_info {
73 int devid;
74
Chia-I Wu32a22462014-08-26 14:13:46 +080075 /* the sizes of the aperture in bytes */
76 size_t aperture_total;
77 size_t aperture_mappable;
78
Chia-I Wu6464ff22014-08-05 11:59:54 +080079 bool has_llc;
80 bool has_address_swizzling;
81 bool has_logical_context;
82 bool has_ppgtt;
83
84 /* valid registers for intel_winsys_read_reg() */
85 bool has_timestamp;
86
87 /* valid flags for intel_winsys_submit_bo() */
88 bool has_gen7_sol_reset;
89};
90
Chia-I Wu770b3092014-08-05 14:22:03 +080091struct intel_winsys_handle {
92 enum intel_winsys_handle_type type;
93 unsigned handle;
94 unsigned stride;
95};
96
Chia-I Wu6464ff22014-08-05 11:59:54 +080097struct intel_winsys *
Chia-I Wuf13ed3c2015-02-22 14:09:00 +080098intel_winsys_create_for_fd(const struct icd_instance *instance, int fd);
Chia-I Wu6464ff22014-08-05 11:59:54 +080099
100void
101intel_winsys_destroy(struct intel_winsys *winsys);
102
103const struct intel_winsys_info *
104intel_winsys_get_info(const struct intel_winsys *winsys);
105
106/**
Chia-I Wu6464ff22014-08-05 11:59:54 +0800107 * Read a register. Only registers that are considered safe, such as
108 *
109 * TIMESTAMP (0x2358)
110 *
111 * can be read.
112 */
113int
114intel_winsys_read_reg(struct intel_winsys *winsys,
115 uint32_t reg, uint64_t *val);
116
117/**
Chia-I Wucb2dc0d2015-03-05 16:19:42 -0700118 * Return the numbers of submissions lost due to GPU reset.
119 *
120 * \param active_lost Number of lost active/guilty submissions
121 * \param pending_lost Number of lost pending/innocent submissions
122 */
123int
124intel_winsys_get_reset_stats(struct intel_winsys *winsys,
125 uint32_t *active_lost,
126 uint32_t *pending_lost);
127/**
Chia-I Wu6464ff22014-08-05 11:59:54 +0800128 * Allocate a buffer object.
129 *
130 * \param name Informative description of the bo.
Chia-I Wucb2dc0d2015-03-05 16:19:42 -0700131 * \param size Size of the bo.
Chia-I Wu32a22462014-08-26 14:13:46 +0800132 * \param cpu_init Will be initialized by CPU.
Chia-I Wu6464ff22014-08-05 11:59:54 +0800133 */
134struct intel_bo *
135intel_winsys_alloc_bo(struct intel_winsys *winsys,
136 const char *name,
Chia-I Wucb2dc0d2015-03-05 16:19:42 -0700137 unsigned long size,
Chia-I Wu32a22462014-08-26 14:13:46 +0800138 bool cpu_init);
Chia-I Wu6464ff22014-08-05 11:59:54 +0800139
140/**
Chia-I Wu6464ff22014-08-05 11:59:54 +0800141 * Create a bo from a winsys handle.
142 */
143struct intel_bo *
144intel_winsys_import_handle(struct intel_winsys *winsys,
145 const char *name,
Chia-I Wu770b3092014-08-05 14:22:03 +0800146 const struct intel_winsys_handle *handle,
Chia-I Wu6464ff22014-08-05 11:59:54 +0800147 unsigned long height,
148 enum intel_tiling_mode *tiling,
149 unsigned long *pitch);
150
151/**
Chia-I Wucb2dc0d2015-03-05 16:19:42 -0700152 * Export \p bo as a winsys handle for inter-process sharing. \p tiling and
153 * \p pitch must match those set by \p intel_bo_set_tiling().
Chia-I Wu6464ff22014-08-05 11:59:54 +0800154 */
155int
156intel_winsys_export_handle(struct intel_winsys *winsys,
157 struct intel_bo *bo,
158 enum intel_tiling_mode tiling,
159 unsigned long pitch,
160 unsigned long height,
Chia-I Wu770b3092014-08-05 14:22:03 +0800161 struct intel_winsys_handle *handle);
Chia-I Wu6464ff22014-08-05 11:59:54 +0800162
163/**
164 * Return true when buffer objects directly specified in \p bo_array, and
165 * those indirectly referenced by them, can fit in the aperture space.
166 */
167bool
168intel_winsys_can_submit_bo(struct intel_winsys *winsys,
169 struct intel_bo **bo_array,
170 int count);
171
172/**
173 * Submit \p bo for execution.
174 *
175 * \p bo and all bos referenced by \p bo will be considered busy until all
176 * commands are parsed and executed. \p ctx is ignored when the bo is not
177 * submitted to the render ring.
178 */
179int
180intel_winsys_submit_bo(struct intel_winsys *winsys,
181 enum intel_ring_type ring,
182 struct intel_bo *bo, int used,
Chia-I Wu6464ff22014-08-05 11:59:54 +0800183 unsigned long flags);
184
185/**
186 * Decode the commands contained in \p bo. For debugging.
187 *
188 * \param bo Batch buffer to decode.
189 * \param used Size of the commands in bytes.
190 */
191void
192intel_winsys_decode_bo(struct intel_winsys *winsys,
193 struct intel_bo *bo, int used);
194
195/**
Chia-I Wucb2dc0d2015-03-05 16:19:42 -0700196 * Increase the reference count of \p bo. No-op when \p bo is NULL.
Chia-I Wu6464ff22014-08-05 11:59:54 +0800197 */
Chia-I Wucb2dc0d2015-03-05 16:19:42 -0700198struct intel_bo *
199intel_bo_ref(struct intel_bo *bo);
Chia-I Wu6464ff22014-08-05 11:59:54 +0800200
201/**
202 * Decrease the reference count of \p bo. When the reference count reaches
Chia-I Wucb2dc0d2015-03-05 16:19:42 -0700203 * zero, \p bo is destroyed. No-op when \p bo is NULL.
Chia-I Wu6464ff22014-08-05 11:59:54 +0800204 */
205void
Chia-I Wucb2dc0d2015-03-05 16:19:42 -0700206intel_bo_unref(struct intel_bo *bo);
207
208/**
209 * Set the tiling of \p bo. The info is used by GTT mapping and bo export.
210 */
211int
212intel_bo_set_tiling(struct intel_bo *bo,
213 enum intel_tiling_mode tiling,
214 unsigned long pitch);
Chia-I Wu6464ff22014-08-05 11:59:54 +0800215
216/**
217 * Map \p bo for CPU access. Recursive mapping is allowed.
218 *
219 * map() maps the backing store into CPU address space, cached. It will block
220 * if the bo is busy. This variant allows fastest random reads and writes,
221 * but the caller needs to handle tiling or swizzling manually if the bo is
222 * tiled or swizzled. If write is enabled and there is no shared last-level
223 * cache (LLC), the CPU cache will be flushed, which is expensive.
224 *
225 * map_gtt() maps the bo for MMIO access, uncached but write-combined. It
226 * will block if the bo is busy. This variant promises a reasonable speed for
227 * sequential writes, but reads would be very slow. Callers always have a
228 * linear view of the bo.
229 *
Chia-I Wucb2dc0d2015-03-05 16:19:42 -0700230 * map_async() and map_gtt_async() work similar to map() and map_gtt()
231 * respectively, except that they do not block.
Chia-I Wu6464ff22014-08-05 11:59:54 +0800232 */
233void *
234intel_bo_map(struct intel_bo *bo, bool write_enable);
235
236void *
Chia-I Wu6702e972015-02-25 09:47:10 -0700237intel_bo_map_async(struct intel_bo *bo);
238
239void *
Chia-I Wu6464ff22014-08-05 11:59:54 +0800240intel_bo_map_gtt(struct intel_bo *bo);
241
242void *
Chia-I Wu32a22462014-08-26 14:13:46 +0800243intel_bo_map_gtt_async(struct intel_bo *bo);
Chia-I Wu6464ff22014-08-05 11:59:54 +0800244
245/**
246 * Unmap \p bo.
247 */
248void
249intel_bo_unmap(struct intel_bo *bo);
250
251/**
252 * Write data to \p bo.
253 */
254int
255intel_bo_pwrite(struct intel_bo *bo, unsigned long offset,
256 unsigned long size, const void *data);
257
258/**
259 * Read data from the bo.
260 */
261int
262intel_bo_pread(struct intel_bo *bo, unsigned long offset,
263 unsigned long size, void *data);
264
265/**
266 * Add \p target_bo to the relocation list.
267 *
268 * When \p bo is submitted for execution, and if \p target_bo has moved,
269 * the kernel will patch \p bo at \p offset to \p target_bo->offset plus
270 * \p target_offset.
271 *
272 * \p presumed_offset should be written to \p bo at \p offset.
273 */
274int
275intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset,
276 struct intel_bo *target_bo, uint32_t target_offset,
Chia-I Wu32a22462014-08-26 14:13:46 +0800277 uint32_t flags, uint64_t *presumed_offset);
Chia-I Wu6464ff22014-08-05 11:59:54 +0800278
279/**
280 * Return the current number of relocations.
281 */
282int
283intel_bo_get_reloc_count(struct intel_bo *bo);
284
285/**
286 * Truncate all relocations except the first \p start ones.
287 *
288 * Combined with \p intel_bo_get_reloc_count(), they can be used to undo the
289 * \p intel_bo_add_reloc() calls that were just made.
290 */
291void
292intel_bo_truncate_relocs(struct intel_bo *bo, int start);
293
294/**
295 * Return true if \p target_bo is on the relocation list of \p bo, or on
296 * the relocation list of some bo that is referenced by \p bo.
297 */
298bool
299intel_bo_has_reloc(struct intel_bo *bo, struct intel_bo *target_bo);
300
301/**
302 * Wait until \bo is idle, or \p timeout nanoseconds have passed. A
303 * negative timeout means to wait indefinitely.
304 *
305 * \return 0 only when \p bo is idle
306 */
307int
308intel_bo_wait(struct intel_bo *bo, int64_t timeout);
309
310/**
311 * Return true if \p bo is busy.
312 */
313static inline bool
314intel_bo_is_busy(struct intel_bo *bo)
315{
316 return (intel_bo_wait(bo, 0) != 0);
317}
318
319#endif /* INTEL_WINSYS_H */