blob: 93333e948fbedcdaf9898f04eed91aabbe2f2889 [file] [log] [blame]
Chia-I Wu214dac62014-08-05 11:07:40 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wu214dac62014-08-05 11:07:40 +080026 */
27
28#include <stdio.h>
29#include <sys/types.h>
30#include <sys/stat.h>
31#include <fcntl.h>
32#include <unistd.h>
33
34#include "genhw/genhw.h"
Chia-I Wude2bb862014-08-19 14:32:47 +080035#include "dispatch.h"
Chia-I Wuec841722014-08-25 22:36:01 +080036#include "queue.h"
Chia-I Wu214dac62014-08-05 11:07:40 +080037#include "gpu.h"
38
Chia-I Wuf07865e2014-09-15 13:52:21 +080039static int gpu_open_primary_node(struct intel_gpu *gpu)
40{
41 /* cannot not open gpu->primary_node directly */
42 return gpu->primary_fd_internal;
43}
44
45static void gpu_close_primary_node(struct intel_gpu *gpu)
46{
47 if (gpu->primary_fd_internal >= 0) {
48 close(gpu->primary_fd_internal);
49 gpu->primary_fd_internal = -1;
50 }
51}
52
53static int gpu_open_render_node(struct intel_gpu *gpu)
54{
55 if (gpu->render_fd_internal < 0 && gpu->render_node) {
56 gpu->render_fd_internal = open(gpu->render_node, O_RDWR);
57 if (gpu->render_fd_internal < 0) {
58 icd_log(XGL_DBG_MSG_ERROR, XGL_VALIDATION_LEVEL_0, NULL, 0,
59 0, "failed to open %s", gpu->render_node);
60 }
61 }
62
63 return gpu->render_fd_internal;
64}
65
66static void gpu_close_render_node(struct intel_gpu *gpu)
67{
68 if (gpu->render_fd_internal >= 0) {
69 close(gpu->render_fd_internal);
70 gpu->render_fd_internal = -1;
71 }
72}
73
Chia-I Wu214dac62014-08-05 11:07:40 +080074static const char *gpu_get_name(const struct intel_gpu *gpu)
75{
76 const char *name = NULL;
77
78 if (gen_is_hsw(gpu->devid)) {
79 if (gen_is_desktop(gpu->devid))
80 name = "Intel(R) Haswell Desktop";
81 else if (gen_is_mobile(gpu->devid))
82 name = "Intel(R) Haswell Mobile";
83 else if (gen_is_server(gpu->devid))
84 name = "Intel(R) Haswell Server";
85 }
86 else if (gen_is_ivb(gpu->devid)) {
87 if (gen_is_desktop(gpu->devid))
88 name = "Intel(R) Ivybridge Desktop";
89 else if (gen_is_mobile(gpu->devid))
90 name = "Intel(R) Ivybridge Mobile";
91 else if (gen_is_server(gpu->devid))
92 name = "Intel(R) Ivybridge Server";
93 }
94 else if (gen_is_snb(gpu->devid)) {
95 if (gen_is_desktop(gpu->devid))
96 name = "Intel(R) Sandybridge Desktop";
97 else if (gen_is_mobile(gpu->devid))
98 name = "Intel(R) Sandybridge Mobile";
99 else if (gen_is_server(gpu->devid))
100 name = "Intel(R) Sandybridge Server";
101 }
102
103 if (!name)
104 name = "Unknown Intel Chipset";
105
106 return name;
107}
108
Chia-I Wuf07865e2014-09-15 13:52:21 +0800109static struct intel_gpu *gpu_create(int gen, int devid,
110 const char *primary_node,
111 const char *render_node)
Chia-I Wu214dac62014-08-05 11:07:40 +0800112{
113 struct intel_gpu *gpu;
Chia-I Wuf07865e2014-09-15 13:52:21 +0800114 size_t primary_len, render_len;
Chia-I Wu214dac62014-08-05 11:07:40 +0800115
116 gpu = icd_alloc(sizeof(*gpu), 0, XGL_SYSTEM_ALLOC_API_OBJECT);
117 if (!gpu)
118 return NULL;
119
120 memset(gpu, 0, sizeof(*gpu));
121
122 /* debug layer is always enabled for intel_gpu */
Chia-I Wu6a42c2a2014-08-19 14:36:47 +0800123 gpu->dispatch = intel_dispatch_get(true);
Chia-I Wu214dac62014-08-05 11:07:40 +0800124
125 gpu->devid = devid;
126
Chia-I Wuf07865e2014-09-15 13:52:21 +0800127 primary_len = strlen(primary_node);
128 render_len = (render_node) ? strlen(render_node) : 0;
129
130 gpu->primary_node = icd_alloc(primary_len + 1 +
131 ((render_len) ? (render_len + 1) : 0), 0, XGL_SYSTEM_ALLOC_INTERNAL);
132 if (!gpu->primary_node) {
Chia-I Wu214dac62014-08-05 11:07:40 +0800133 icd_free(gpu);
134 return NULL;
135 }
Chia-I Wuf07865e2014-09-15 13:52:21 +0800136
137 memcpy(gpu->primary_node, primary_node, primary_len + 1);
138
139 if (render_node) {
140 gpu->render_node = gpu->primary_node + primary_len + 1;
141 memcpy(gpu->render_node, render_node, render_len + 1);
142 }
Chia-I Wu214dac62014-08-05 11:07:40 +0800143
144 gpu->gen_opaque = gen;
145
Chia-I Wu960f1952014-08-28 23:27:10 +0800146 switch (intel_gpu_gen(gpu)) {
147 case INTEL_GEN(7.5):
148 gpu->gt = gen_get_hsw_gt(devid);
149 break;
150 case INTEL_GEN(7):
151 gpu->gt = gen_get_ivb_gt(devid);
152 break;
153 case INTEL_GEN(6):
154 gpu->gt = gen_get_snb_gt(devid);
155 break;
156 }
157
Chia-I Wu214dac62014-08-05 11:07:40 +0800158 /* 8192 dwords */
Chia-I Wud6109bb2014-08-21 09:12:19 +0800159 gpu->max_batch_buffer_size = sizeof(uint32_t) * 8192;
160
161 /* the winsys is prepared for one reloc every two dwords, then minus 2 */
162 gpu->batch_buffer_reloc_count =
163 gpu->max_batch_buffer_size / sizeof(uint32_t) / 2 - 2;
Chia-I Wu214dac62014-08-05 11:07:40 +0800164
Chia-I Wuf07865e2014-09-15 13:52:21 +0800165 gpu->primary_fd_internal = -1;
166 gpu->render_fd_internal = -1;
167
168 gpu->device_fd = -1;
Chia-I Wu214dac62014-08-05 11:07:40 +0800169
170 return gpu;
171}
172
173static void gpu_destroy(struct intel_gpu *gpu)
174{
Chia-I Wuf07865e2014-09-15 13:52:21 +0800175 intel_gpu_close(gpu);
176 icd_free(gpu->primary_node);
Chia-I Wu214dac62014-08-05 11:07:40 +0800177 icd_free(gpu);
178}
179
180static struct intel_gpu *intel_gpus;
181
182/**
183 * Return true if \p gpu is a valid intel_gpu.
184 */
185bool intel_gpu_is_valid(const struct intel_gpu *gpu)
186{
187 const struct intel_gpu *iter = intel_gpus;
188
189 while (iter) {
190 if (iter == gpu)
191 return true;
192 iter = iter->next;
193 }
194
195 return false;
196}
197
198static int devid_to_gen(int devid)
199{
200 int gen;
201
202 if (gen_is_hsw(devid))
203 gen = INTEL_GEN(7.5);
204 else if (gen_is_ivb(devid))
205 gen = INTEL_GEN(7);
206 else if (gen_is_snb(devid))
207 gen = INTEL_GEN(6);
208 else
209 gen = -1;
210
Chia-I Wubfce58e2014-08-28 23:23:33 +0800211#ifdef INTEL_GEN_SPECIALIZED
212 if (gen != INTEL_GEN(INTEL_GEN_SPECIALIZED))
213 gen = -1;
214#endif
215
Chia-I Wu214dac62014-08-05 11:07:40 +0800216 return gen;
217}
218
Chia-I Wuf07865e2014-09-15 13:52:21 +0800219XGL_RESULT intel_gpu_add(int devid, const char *primary_node,
220 const char *render_node, struct intel_gpu **gpu_ret)
Chia-I Wu214dac62014-08-05 11:07:40 +0800221{
222 const int gen = devid_to_gen(devid);
223 struct intel_gpu *gpu;
224
225 if (gen < 0) {
226 icd_log(XGL_DBG_MSG_WARNING, XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE,
227 0, 0, "unsupported device id 0x%04x", devid);
228 return XGL_ERROR_INITIALIZATION_FAILED;
229 }
230
Chia-I Wuf07865e2014-09-15 13:52:21 +0800231 gpu = gpu_create(gen, devid, primary_node, render_node);
Chia-I Wu214dac62014-08-05 11:07:40 +0800232 if (!gpu)
233 return XGL_ERROR_OUT_OF_MEMORY;
234
235 gpu->next = intel_gpus;
236 intel_gpus = gpu;
237
238 *gpu_ret = gpu;
239
240 return XGL_SUCCESS;
241}
242
243void intel_gpu_remove_all(void)
244{
245 struct intel_gpu *gpu = intel_gpus;
246
247 while (gpu) {
248 struct intel_gpu *next = gpu->next;
249
250 gpu_destroy(gpu);
251 gpu = next;
252 }
253
254 intel_gpus = NULL;
255}
256
257struct intel_gpu *intel_gpu_get_list(void)
258{
259 return intel_gpus;
260}
261
262void intel_gpu_get_props(const struct intel_gpu *gpu,
263 XGL_PHYSICAL_GPU_PROPERTIES *props)
264{
265 const char *name;
266 size_t name_len;
267
268 props->structSize = sizeof(*props);
269
270 props->apiVersion = INTEL_API_VERSION;
271 props->driverVersion = INTEL_DRIVER_VERSION;
272
273 props->vendorId = 0x8086;
274 props->deviceId = gpu->devid;
275
276 props->gpuType = XGL_GPU_TYPE_INTEGRATED;
277
278 /* copy GPU name */
279 name = gpu_get_name(gpu);
280 name_len = strlen(name);
281 if (name_len > sizeof(props->gpuName) - 1)
282 name_len = sizeof(props->gpuName) - 1;
283 memcpy(props->gpuName, name, name_len);
284 props->gpuName[name_len] = '\0';
285
Chia-I Wud6109bb2014-08-21 09:12:19 +0800286 props->maxMemRefsPerSubmission = gpu->batch_buffer_reloc_count;
Chia-I Wu214dac62014-08-05 11:07:40 +0800287
288 props->virtualMemPageSize = 4096;
289
290 /* no size limit, but no bounded buffer could exceed 2GB */
291 props->maxInlineMemoryUpdateSize = 2u << 30;
292
293 props->maxBoundDescriptorSets = 1;
294 props->maxThreadGroupSize = 512;
295
296 /* incremented every 80ns */
297 props->timestampFrequency = 1000 * 1000 * 1000 / 80;
298
299 props->multiColorAttachmentClears = false;
300}
301
302void intel_gpu_get_perf(const struct intel_gpu *gpu,
303 XGL_PHYSICAL_GPU_PERFORMANCE *perf)
304{
305 /* TODO */
306 perf->maxGpuClock = 1.0f;
307 perf->aluPerClock = 1.0f;
308 perf->texPerClock = 1.0f;
309 perf->primsPerClock = 1.0f;
310 perf->pixelsPerClock = 1.0f;
311}
312
313void intel_gpu_get_queue_props(const struct intel_gpu *gpu,
314 enum intel_gpu_engine_type engine,
315 XGL_PHYSICAL_GPU_QUEUE_PROPERTIES *props)
316{
317 props->structSize = sizeof(*props);
318
319 switch (engine) {
320 case INTEL_GPU_ENGINE_3D:
321 props->queueFlags = XGL_QUEUE_GRAPHICS_BIT | XGL_QUEUE_COMPUTE_BIT;
322 props->queueCount = 1;
Chia-I Wuec841722014-08-25 22:36:01 +0800323 props->maxAtomicCounters = INTEL_QUEUE_ATOMIC_COUNTER_COUNT;
Chia-I Wu214dac62014-08-05 11:07:40 +0800324 props->supportsTimestamps = true;
325 break;
326 default:
327 assert(!"unknown engine type");
328 return;
329 }
330}
331
332void intel_gpu_get_memory_props(const struct intel_gpu *gpu,
333 XGL_PHYSICAL_GPU_MEMORY_PROPERTIES *props)
334{
335 props->structSize = sizeof(*props);
336
337 props->supportsMigration = false;
338
339 /* no kernel support yet */
340 props->supportsVirtualMemoryRemapping = false;
341
Chia-I Wu54c0c4b2014-08-06 13:48:25 +0800342 /* no winsys support for DRM_I915_GEM_USERPTR yet */
343 props->supportsPinning = false;
Chia-I Wu214dac62014-08-05 11:07:40 +0800344}
345
346XGL_RESULT intel_gpu_open(struct intel_gpu *gpu)
347{
Chia-I Wuf07865e2014-09-15 13:52:21 +0800348 gpu->device_fd = gpu_open_primary_node(gpu);
349 if (gpu->device_fd < 0)
350 gpu->device_fd = gpu_open_render_node(gpu);
Chia-I Wu214dac62014-08-05 11:07:40 +0800351
Chia-I Wuf07865e2014-09-15 13:52:21 +0800352 return (gpu->device_fd >= 0) ? XGL_SUCCESS : XGL_ERROR_UNKNOWN;
Chia-I Wu214dac62014-08-05 11:07:40 +0800353}
354
355void intel_gpu_close(struct intel_gpu *gpu)
356{
Chia-I Wuf07865e2014-09-15 13:52:21 +0800357 gpu_close_primary_node(gpu);
358 gpu_close_render_node(gpu);
359 gpu->device_fd = -1;
Chia-I Wu214dac62014-08-05 11:07:40 +0800360}
361
362bool intel_gpu_has_extension(const struct intel_gpu *gpu, const char *ext)
363{
364 return false;
365}
Chia-I Wubec90a02014-08-06 12:33:03 +0800366
367XGL_RESULT XGLAPI intelGetGpuInfo(
368 XGL_PHYSICAL_GPU gpu_,
369 XGL_PHYSICAL_GPU_INFO_TYPE infoType,
370 XGL_SIZE* pDataSize,
371 XGL_VOID* pData)
372{
373 const struct intel_gpu *gpu = intel_gpu(gpu_);
374 XGL_RESULT ret = XGL_SUCCESS;
375
376 switch (infoType) {
377 case XGL_INFO_TYPE_PHYSICAL_GPU_PROPERTIES:
378 if (pData == NULL) {
379 return XGL_ERROR_INVALID_POINTER;
380 }
381 *pDataSize = sizeof(XGL_PHYSICAL_GPU_PROPERTIES);
382 intel_gpu_get_props(gpu, pData);
383 break;
384
385 case XGL_INFO_TYPE_PHYSICAL_GPU_PERFORMANCE:
386 if (pData == NULL) {
387 return XGL_ERROR_INVALID_POINTER;
388 }
389 *pDataSize = sizeof(XGL_PHYSICAL_GPU_PERFORMANCE);
390 intel_gpu_get_perf(gpu, pData);
391 break;
392
393 case XGL_INFO_TYPE_PHYSICAL_GPU_QUEUE_PROPERTIES:
394 /*
395 * XGL Programmers guide, page 33:
396 * to determine the data size an application calls
397 * xglGetGpuInfo() with a NULL data pointer. The
398 * expected data size for all queue property structures
399 * is returned in pDataSize
400 */
401 *pDataSize = sizeof(XGL_PHYSICAL_GPU_QUEUE_PROPERTIES) *
402 INTEL_GPU_ENGINE_COUNT;
403 if (pData != NULL) {
404 XGL_PHYSICAL_GPU_QUEUE_PROPERTIES *dst = pData;
405 int engine;
406
407 for (engine = 0; engine < INTEL_GPU_ENGINE_COUNT; engine++) {
408 intel_gpu_get_queue_props(gpu, engine, dst);
409 dst++;
410 }
411 }
412 break;
413
414 case XGL_INFO_TYPE_PHYSICAL_GPU_MEMORY_PROPERTIES:
415 if (pData == NULL) {
416 return XGL_ERROR_INVALID_POINTER;
417 }
418 *pDataSize = sizeof(XGL_PHYSICAL_GPU_MEMORY_PROPERTIES);
419 intel_gpu_get_memory_props(gpu, pData);
420 break;
421
422 default:
423 ret = XGL_ERROR_INVALID_VALUE;
424 }
425
426 return ret;
427}
428
429XGL_RESULT XGLAPI intelGetExtensionSupport(
430 XGL_PHYSICAL_GPU gpu_,
431 const XGL_CHAR* pExtName)
432{
433 struct intel_gpu *gpu = intel_gpu(gpu_);
434
435 return (intel_gpu_has_extension(gpu, (const char *) pExtName)) ?
436 XGL_SUCCESS : XGL_ERROR_INVALID_EXTENSION;
437}
Chia-I Wu251e7d92014-08-19 13:35:42 +0800438
439XGL_RESULT XGLAPI intelGetMultiGpuCompatibility(
Chia-I Wu452f5e82014-08-31 12:39:05 +0800440 XGL_PHYSICAL_GPU gpu0_,
441 XGL_PHYSICAL_GPU gpu1_,
Chia-I Wu251e7d92014-08-19 13:35:42 +0800442 XGL_GPU_COMPATIBILITY_INFO* pInfo)
443{
Chia-I Wu452f5e82014-08-31 12:39:05 +0800444 const struct intel_gpu *gpu0 = intel_gpu(gpu0_);
445 const struct intel_gpu *gpu1 = intel_gpu(gpu1_);
446 XGL_FLAGS compat = XGL_GPU_COMPAT_IQ_MATCH_BIT |
447 XGL_GPU_COMPAT_PEER_TRANSFER_BIT |
448 XGL_GPU_COMPAT_SHARED_MEMORY_BIT |
449 XGL_GPU_COMPAT_SHARED_GPU0_DISPLAY_BIT |
450 XGL_GPU_COMPAT_SHARED_GPU1_DISPLAY_BIT;
451
452 if (intel_gpu_gen(gpu0) == intel_gpu_gen(gpu1))
453 compat |= XGL_GPU_COMPAT_ASIC_FEATURES_BIT;
454
455 pInfo->compatibilityFlags = compat;
456
457 return XGL_SUCCESS;
Chia-I Wu251e7d92014-08-19 13:35:42 +0800458}