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Zonr Changc72c4dd2012-04-12 15:38:53 +08001#ifndef BCC_CONFIG_CONFIG_H
2#define BCC_CONFIG_CONFIG_H
Logan35849002011-01-15 07:30:43 +08003
4//---------------------------------------------------------------------------
Logan Chien4885cf82011-07-20 10:18:05 +08005// Configuration for Disassembler
Logan1dc63142011-02-25 17:14:51 +08006//---------------------------------------------------------------------------
Logan35849002011-01-15 07:30:43 +08007
Stephen Hines36999622012-03-11 19:15:51 -07008#if DEBUG_MC_DISASSEMBLER
Logan Chien4885cf82011-07-20 10:18:05 +08009#define USE_DISASSEMBLER 1
10#else
11#define USE_DISASSEMBLER 0
12#endif
13
Andrew Hsieh1704c742011-11-20 20:43:36 -080014#if defined(__HOST__)
Shih-wei Liaod7f1bd62012-07-23 23:14:34 -070015#define DEBUG_DISASSEMBLER_FILE "/tmp/mc-dis.s"
Andrew Hsieh1704c742011-11-20 20:43:36 -080016#else
Shih-wei Liaod7f1bd62012-07-23 23:14:34 -070017#define DEBUG_DISASSEMBLER_FILE "/data/local/tmp/mc-dis.s"
Andrew Hsieh1704c742011-11-20 20:43:36 -080018#endif // defined(__HOST__)
Logan35849002011-01-15 07:30:43 +080019
Logan35849002011-01-15 07:30:43 +080020//---------------------------------------------------------------------------
Logan1dc63142011-02-25 17:14:51 +080021// Configuration for CodeGen and CompilerRT
22//---------------------------------------------------------------------------
Logan35849002011-01-15 07:30:43 +080023
Logan35849002011-01-15 07:30:43 +080024#if defined(FORCE_ARM_CODEGEN)
Victor Khimenko53f9a6d2018-03-21 20:03:32 +010025 #define PROVIDE_ARM_CODEGEN 1
26 #define DEFAULT_ARM_CODEGEN 1
Logan Chien3bb77072011-09-17 16:53:53 +080027
Tim Murrayc2074ca2014-04-08 15:39:08 -070028#elif defined(FORCE_ARM64_CODEGEN)
Victor Khimenko53f9a6d2018-03-21 20:03:32 +010029 #define PROVIDE_ARM_CODEGEN 1
30 #define PROVIDE_ARM64_CODEGEN 1
31 #define DEFAULT_ARM64_CODEGEN 1
Tim Murrayc2074ca2014-04-08 15:39:08 -070032
Logan Chien21392f02011-11-26 20:32:01 +080033#elif defined(FORCE_MIPS_CODEGEN)
Victor Khimenko53f9a6d2018-03-21 20:03:32 +010034 #define PROVIDE_MIPS_CODEGEN 1
35 #define DEFAULT_MIPS_CODEGEN 1
Logan Chien21392f02011-11-26 20:32:01 +080036
Dragoslav Sicarovd5a42042014-05-22 15:00:18 +000037#elif defined(FORCE_MIPS64_CODEGEN)
Victor Khimenko53f9a6d2018-03-21 20:03:32 +010038 #define PROVIDE_MIPS_CODEGEN 1
39 #define PROVIDE_MIPS64_CODEGEN 1
40 #define DEFAULT_MIPS64_CODEGEN 1
Dragoslav Sicarovd5a42042014-05-22 15:00:18 +000041
Logan35849002011-01-15 07:30:43 +080042#elif defined(FORCE_X86_CODEGEN)
Victor Khimenko53f9a6d2018-03-21 20:03:32 +010043 #define PROVIDE_X86_CODEGEN 1
44 #define DEFAULT_X86_CODEGEN 1
Logan Chien3bb77072011-09-17 16:53:53 +080045
Stephen Hines0467bc42014-05-05 15:11:12 -070046#elif defined(FORCE_X86_64_CODEGEN)
47 // There is no separate X86_64 code generation target. It is all part of X86.
Victor Khimenko53f9a6d2018-03-21 20:03:32 +010048 #define PROVIDE_X86_CODEGEN 1
49 #define DEFAULT_X86_64_CODEGEN 1
Logan Chien3bb77072011-09-17 16:53:53 +080050
51#else
Victor Khimenko53f9a6d2018-03-21 20:03:32 +010052 #define PROVIDE_ARM_CODEGEN 1
53 #define PROVIDE_ARM64_CODEGEN 1
54 #define PROVIDE_MIPS_CODEGEN 1
55 #define PROVIDE_MIPS64_CODEGEN 1
56 #define PROVIDE_X86_CODEGEN 1
57 #define PROVIDE_X86_64_CODEGEN 1
Logan Chien3bb77072011-09-17 16:53:53 +080058
59 #if defined(__arm__)
Victor Khimenko53f9a6d2018-03-21 20:03:32 +010060 #define DEFAULT_ARM_CODEGEN 1
Logan Chien867e8dd2014-09-03 23:16:11 +080061 #elif defined(__aarch64__)
Victor Khimenko53f9a6d2018-03-21 20:03:32 +010062 #define DEFAULT_ARM64_CODEGEN 1
Logan Chien21392f02011-11-26 20:32:01 +080063 #elif defined(__mips__)
Dragoslav Sicarovd5a42042014-05-22 15:00:18 +000064 #if defined(__LP64__)
Victor Khimenko53f9a6d2018-03-21 20:03:32 +010065 #define DEFAULT_MIPS64_CODEGEN 1
Dragoslav Sicarovd5a42042014-05-22 15:00:18 +000066 #else
Victor Khimenko53f9a6d2018-03-21 20:03:32 +010067 #define DEFAULT_MIPS_CODEGEN 1
Dragoslav Sicarovd5a42042014-05-22 15:00:18 +000068 #endif
Logan Chien3bb77072011-09-17 16:53:53 +080069 #elif defined(__i386__)
Victor Khimenko53f9a6d2018-03-21 20:03:32 +010070 #define DEFAULT_X86_CODEGEN 1
Logan Chien3bb77072011-09-17 16:53:53 +080071 #elif defined(__x86_64__)
Victor Khimenko53f9a6d2018-03-21 20:03:32 +010072 #define DEFAULT_X86_64_CODEGEN 1
Logan Chien3bb77072011-09-17 16:53:53 +080073 #endif
Logan35849002011-01-15 07:30:43 +080074#endif
75
Zonr Changf74ee192012-04-12 15:34:58 +080076#define DEFAULT_ARM_TRIPLE_STRING "armv7-none-linux-gnueabi"
Shih-wei Liao99c8a6b2012-08-16 01:55:50 -070077#define DEFAULT_THUMB_TRIPLE_STRING "thumbv7-none-linux-gnueabi"
Tim Murrayc2074ca2014-04-08 15:39:08 -070078#define DEFAULT_ARM64_TRIPLE_STRING "aarch64-none-linux-gnueabi"
Zonr Changf74ee192012-04-12 15:34:58 +080079#define DEFAULT_MIPS_TRIPLE_STRING "mipsel-none-linux-gnueabi"
Dragoslav Sicarovd5a42042014-05-22 15:00:18 +000080#define DEFAULT_MIPS64_TRIPLE_STRING "mips64el-none-linux-gnueabi"
Zonr Changf74ee192012-04-12 15:34:58 +080081#define DEFAULT_X86_TRIPLE_STRING "i686-unknown-linux"
82#define DEFAULT_X86_64_TRIPLE_STRING "x86_64-unknown-linux"
83
Yong Chenf039d982015-10-21 13:28:09 +080084// Custom DataLayout string for X86 with i64 and f64 set to match the ARM32
85// alignment requirement of 64-bits.
86#define X86_CUSTOM_DL_STRING "e-m:e-p:32:32-i64:64-f64:64:64-f80:32-n8:16:32-S128"
Pirama Arumuga Nainard2d5ee32016-04-12 14:04:50 -070087// Default DataLayout string for X86. Present to detect future LLVM datalayout
88// changes so X86_CUSTOM_DL_STRING above can be modified appropriately.
89#define X86_DEFAULT_DL_STRING "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
Yong Chenf039d982015-10-21 13:28:09 +080090
Logan35849002011-01-15 07:30:43 +080091#if defined(DEFAULT_ARM_CODEGEN)
Zonr Changf74ee192012-04-12 15:34:58 +080092 #define DEFAULT_TARGET_TRIPLE_STRING DEFAULT_ARM_TRIPLE_STRING
Tim Murrayc2074ca2014-04-08 15:39:08 -070093#elif defined(DEFAULT_ARM64_CODEGEN)
94 #define DEFAULT_TARGET_TRIPLE_STRING DEFAULT_ARM64_TRIPLE_STRING
Logan Chien21392f02011-11-26 20:32:01 +080095#elif defined(DEFAULT_MIPS_CODEGEN)
Zonr Changf74ee192012-04-12 15:34:58 +080096 #define DEFAULT_TARGET_TRIPLE_STRING DEFAULT_MIPS_TRIPLE_STRING
Dragoslav Sicarovd5a42042014-05-22 15:00:18 +000097#elif defined(DEFAULT_MIPS64_CODEGEN)
98 #define DEFAULT_TARGET_TRIPLE_STRING DEFAULT_MIPS64_TRIPLE_STRING
Logan35849002011-01-15 07:30:43 +080099#elif defined(DEFAULT_X86_CODEGEN)
Zonr Changf74ee192012-04-12 15:34:58 +0800100 #define DEFAULT_TARGET_TRIPLE_STRING DEFAULT_X86_TRIPLE_STRING
Logan Chien3bb77072011-09-17 16:53:53 +0800101#elif defined(DEFAULT_X86_64_CODEGEN)
Zonr Changf74ee192012-04-12 15:34:58 +0800102 #define DEFAULT_TARGET_TRIPLE_STRING DEFAULT_X86_64_TRIPLE_STRING
Logan35849002011-01-15 07:30:43 +0800103#endif
104
105#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
106 #define ARM_USE_VFP
107#endif
108
109//---------------------------------------------------------------------------
110
Zonr Changc72c4dd2012-04-12 15:38:53 +0800111#endif // BCC_CONFIG_CONFIG_H