Colin Cross | 07a5832 | 2022-02-08 19:45:27 -0800 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | **************************************************************************** |
| 3 | *** |
| 4 | *** This header was automatically generated from a Linux kernel header |
| 5 | *** of the same name, to make information necessary for userspace to |
| 6 | *** call into the kernel available to libc. It contains only constants, |
| 7 | *** structures, and macros generated from the original header, and thus, |
| 8 | *** contains no copyrightable information. |
| 9 | *** |
| 10 | *** To edit the content of this header, modify the corresponding |
| 11 | *** source file (e.g. under external/kernel-headers/original/) then |
| 12 | *** run bionic/libc/kernel/tools/update_all.py |
| 13 | *** |
| 14 | *** Any manual change here will be lost the next time this script will |
| 15 | *** be run. You've been warned! |
| 16 | *** |
| 17 | **************************************************************************** |
| 18 | ****************************************************************************/ |
| 19 | #ifndef __AMDGPU_DRM_H__ |
| 20 | #define __AMDGPU_DRM_H__ |
| 21 | #include "drm.h" |
| 22 | #ifdef __cplusplus |
| 23 | extern "C" { |
| 24 | #endif |
| 25 | #define DRM_AMDGPU_GEM_CREATE 0x00 |
| 26 | #define DRM_AMDGPU_GEM_MMAP 0x01 |
| 27 | #define DRM_AMDGPU_CTX 0x02 |
| 28 | #define DRM_AMDGPU_BO_LIST 0x03 |
| 29 | #define DRM_AMDGPU_CS 0x04 |
| 30 | #define DRM_AMDGPU_INFO 0x05 |
| 31 | #define DRM_AMDGPU_GEM_METADATA 0x06 |
| 32 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 |
| 33 | #define DRM_AMDGPU_GEM_VA 0x08 |
| 34 | #define DRM_AMDGPU_WAIT_CS 0x09 |
| 35 | #define DRM_AMDGPU_GEM_OP 0x10 |
| 36 | #define DRM_AMDGPU_GEM_USERPTR 0x11 |
| 37 | #define DRM_AMDGPU_WAIT_FENCES 0x12 |
| 38 | #define DRM_AMDGPU_VM 0x13 |
| 39 | #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 |
| 40 | #define DRM_AMDGPU_SCHED 0x15 |
| 41 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) |
| 42 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) |
| 43 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) |
| 44 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) |
| 45 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) |
| 46 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) |
| 47 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) |
| 48 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) |
| 49 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
| 50 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
| 51 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) |
| 52 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) |
| 53 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) |
| 54 | #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) |
| 55 | #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) |
| 56 | #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) |
| 57 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 |
| 58 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 |
| 59 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 |
| 60 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 |
| 61 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 |
| 62 | #define AMDGPU_GEM_DOMAIN_OA 0x20 |
| 63 | #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA) |
| 64 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) |
| 65 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) |
| 66 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
| 67 | #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) |
| 68 | #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) |
| 69 | #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) |
| 70 | #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) |
| 71 | #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) |
| 72 | #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) |
| 73 | #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) |
| 74 | #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) |
| 75 | struct drm_amdgpu_gem_create_in { |
| 76 | __u64 bo_size; |
| 77 | __u64 alignment; |
| 78 | __u64 domains; |
| 79 | __u64 domain_flags; |
| 80 | }; |
| 81 | struct drm_amdgpu_gem_create_out { |
| 82 | __u32 handle; |
| 83 | __u32 _pad; |
| 84 | }; |
| 85 | union drm_amdgpu_gem_create { |
| 86 | struct drm_amdgpu_gem_create_in in; |
| 87 | struct drm_amdgpu_gem_create_out out; |
| 88 | }; |
| 89 | #define AMDGPU_BO_LIST_OP_CREATE 0 |
| 90 | #define AMDGPU_BO_LIST_OP_DESTROY 1 |
| 91 | #define AMDGPU_BO_LIST_OP_UPDATE 2 |
| 92 | struct drm_amdgpu_bo_list_in { |
| 93 | __u32 operation; |
| 94 | __u32 list_handle; |
| 95 | __u32 bo_number; |
| 96 | __u32 bo_info_size; |
| 97 | __u64 bo_info_ptr; |
| 98 | }; |
| 99 | struct drm_amdgpu_bo_list_entry { |
| 100 | __u32 bo_handle; |
| 101 | __u32 bo_priority; |
| 102 | }; |
| 103 | struct drm_amdgpu_bo_list_out { |
| 104 | __u32 list_handle; |
| 105 | __u32 _pad; |
| 106 | }; |
| 107 | union drm_amdgpu_bo_list { |
| 108 | struct drm_amdgpu_bo_list_in in; |
| 109 | struct drm_amdgpu_bo_list_out out; |
| 110 | }; |
| 111 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 |
| 112 | #define AMDGPU_CTX_OP_FREE_CTX 2 |
| 113 | #define AMDGPU_CTX_OP_QUERY_STATE 3 |
| 114 | #define AMDGPU_CTX_OP_QUERY_STATE2 4 |
Jordan Demeulenaere | 2d50582 | 2022-08-11 17:20:14 +0200 | [diff] [blame] | 115 | #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 |
| 116 | #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 |
Colin Cross | 07a5832 | 2022-02-08 19:45:27 -0800 | [diff] [blame] | 117 | #define AMDGPU_CTX_NO_RESET 0 |
| 118 | #define AMDGPU_CTX_GUILTY_RESET 1 |
| 119 | #define AMDGPU_CTX_INNOCENT_RESET 2 |
| 120 | #define AMDGPU_CTX_UNKNOWN_RESET 3 |
| 121 | #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1 << 0) |
| 122 | #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1 << 1) |
| 123 | #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1 << 2) |
| 124 | #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1 << 3) |
| 125 | #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1 << 4) |
| 126 | #define AMDGPU_CTX_PRIORITY_UNSET - 2048 |
| 127 | #define AMDGPU_CTX_PRIORITY_VERY_LOW - 1023 |
| 128 | #define AMDGPU_CTX_PRIORITY_LOW - 512 |
| 129 | #define AMDGPU_CTX_PRIORITY_NORMAL 0 |
| 130 | #define AMDGPU_CTX_PRIORITY_HIGH 512 |
| 131 | #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 |
Jordan Demeulenaere | 2d50582 | 2022-08-11 17:20:14 +0200 | [diff] [blame] | 132 | #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf |
| 133 | #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 |
| 134 | #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 |
| 135 | #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 |
| 136 | #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 |
| 137 | #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 |
Colin Cross | 07a5832 | 2022-02-08 19:45:27 -0800 | [diff] [blame] | 138 | struct drm_amdgpu_ctx_in { |
| 139 | __u32 op; |
| 140 | __u32 flags; |
| 141 | __u32 ctx_id; |
| 142 | __s32 priority; |
| 143 | }; |
| 144 | union drm_amdgpu_ctx_out { |
| 145 | struct { |
| 146 | __u32 ctx_id; |
| 147 | __u32 _pad; |
| 148 | } alloc; |
| 149 | struct { |
| 150 | __u64 flags; |
| 151 | __u32 hangs; |
| 152 | __u32 reset_status; |
| 153 | } state; |
Jordan Demeulenaere | 2d50582 | 2022-08-11 17:20:14 +0200 | [diff] [blame] | 154 | struct { |
| 155 | __u32 flags; |
| 156 | __u32 _pad; |
| 157 | } pstate; |
Colin Cross | 07a5832 | 2022-02-08 19:45:27 -0800 | [diff] [blame] | 158 | }; |
| 159 | union drm_amdgpu_ctx { |
| 160 | struct drm_amdgpu_ctx_in in; |
| 161 | union drm_amdgpu_ctx_out out; |
| 162 | }; |
| 163 | #define AMDGPU_VM_OP_RESERVE_VMID 1 |
| 164 | #define AMDGPU_VM_OP_UNRESERVE_VMID 2 |
| 165 | struct drm_amdgpu_vm_in { |
| 166 | __u32 op; |
| 167 | __u32 flags; |
| 168 | }; |
| 169 | struct drm_amdgpu_vm_out { |
| 170 | __u64 flags; |
| 171 | }; |
| 172 | union drm_amdgpu_vm { |
| 173 | struct drm_amdgpu_vm_in in; |
| 174 | struct drm_amdgpu_vm_out out; |
| 175 | }; |
| 176 | #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 |
| 177 | #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 |
| 178 | struct drm_amdgpu_sched_in { |
| 179 | __u32 op; |
| 180 | __u32 fd; |
| 181 | __s32 priority; |
| 182 | __u32 ctx_id; |
| 183 | }; |
| 184 | union drm_amdgpu_sched { |
| 185 | struct drm_amdgpu_sched_in in; |
| 186 | }; |
| 187 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) |
| 188 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) |
| 189 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) |
| 190 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) |
| 191 | struct drm_amdgpu_gem_userptr { |
| 192 | __u64 addr; |
| 193 | __u64 size; |
| 194 | __u32 flags; |
| 195 | __u32 handle; |
| 196 | }; |
| 197 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 |
| 198 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf |
| 199 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 |
| 200 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f |
| 201 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 |
| 202 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 |
| 203 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 |
| 204 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 |
| 205 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 |
| 206 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 |
| 207 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 |
| 208 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 |
| 209 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 |
| 210 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 |
| 211 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 |
| 212 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 |
| 213 | #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 |
| 214 | #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f |
| 215 | #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 |
| 216 | #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF |
| 217 | #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 |
| 218 | #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF |
| 219 | #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 |
| 220 | #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 |
| 221 | #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 |
| 222 | #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 |
| 223 | #define AMDGPU_TILING_SCANOUT_SHIFT 63 |
| 224 | #define AMDGPU_TILING_SCANOUT_MASK 0x1 |
| 225 | #define AMDGPU_TILING_SET(field,value) (((__u64) (value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT) |
| 226 | #define AMDGPU_TILING_GET(value,field) (((__u64) (value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK) |
| 227 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 |
| 228 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 |
| 229 | struct drm_amdgpu_gem_metadata { |
| 230 | __u32 handle; |
| 231 | __u32 op; |
| 232 | struct { |
| 233 | __u64 flags; |
| 234 | __u64 tiling_info; |
| 235 | __u32 data_size_bytes; |
| 236 | __u32 data[64]; |
| 237 | } data; |
| 238 | }; |
| 239 | struct drm_amdgpu_gem_mmap_in { |
| 240 | __u32 handle; |
| 241 | __u32 _pad; |
| 242 | }; |
| 243 | struct drm_amdgpu_gem_mmap_out { |
| 244 | __u64 addr_ptr; |
| 245 | }; |
| 246 | union drm_amdgpu_gem_mmap { |
| 247 | struct drm_amdgpu_gem_mmap_in in; |
| 248 | struct drm_amdgpu_gem_mmap_out out; |
| 249 | }; |
| 250 | struct drm_amdgpu_gem_wait_idle_in { |
| 251 | __u32 handle; |
| 252 | __u32 flags; |
| 253 | __u64 timeout; |
| 254 | }; |
| 255 | struct drm_amdgpu_gem_wait_idle_out { |
| 256 | __u32 status; |
| 257 | __u32 domain; |
| 258 | }; |
| 259 | union drm_amdgpu_gem_wait_idle { |
| 260 | struct drm_amdgpu_gem_wait_idle_in in; |
| 261 | struct drm_amdgpu_gem_wait_idle_out out; |
| 262 | }; |
| 263 | struct drm_amdgpu_wait_cs_in { |
| 264 | __u64 handle; |
| 265 | __u64 timeout; |
| 266 | __u32 ip_type; |
| 267 | __u32 ip_instance; |
| 268 | __u32 ring; |
| 269 | __u32 ctx_id; |
| 270 | }; |
| 271 | struct drm_amdgpu_wait_cs_out { |
| 272 | __u64 status; |
| 273 | }; |
| 274 | union drm_amdgpu_wait_cs { |
| 275 | struct drm_amdgpu_wait_cs_in in; |
| 276 | struct drm_amdgpu_wait_cs_out out; |
| 277 | }; |
| 278 | struct drm_amdgpu_fence { |
| 279 | __u32 ctx_id; |
| 280 | __u32 ip_type; |
| 281 | __u32 ip_instance; |
| 282 | __u32 ring; |
| 283 | __u64 seq_no; |
| 284 | }; |
| 285 | struct drm_amdgpu_wait_fences_in { |
| 286 | __u64 fences; |
| 287 | __u32 fence_count; |
| 288 | __u32 wait_all; |
| 289 | __u64 timeout_ns; |
| 290 | }; |
| 291 | struct drm_amdgpu_wait_fences_out { |
| 292 | __u32 status; |
| 293 | __u32 first_signaled; |
| 294 | }; |
| 295 | union drm_amdgpu_wait_fences { |
| 296 | struct drm_amdgpu_wait_fences_in in; |
| 297 | struct drm_amdgpu_wait_fences_out out; |
| 298 | }; |
| 299 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
| 300 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 |
| 301 | struct drm_amdgpu_gem_op { |
| 302 | __u32 handle; |
| 303 | __u32 op; |
| 304 | __u64 value; |
| 305 | }; |
| 306 | #define AMDGPU_VA_OP_MAP 1 |
| 307 | #define AMDGPU_VA_OP_UNMAP 2 |
| 308 | #define AMDGPU_VA_OP_CLEAR 3 |
| 309 | #define AMDGPU_VA_OP_REPLACE 4 |
| 310 | #define AMDGPU_VM_DELAY_UPDATE (1 << 0) |
| 311 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) |
| 312 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) |
| 313 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) |
| 314 | #define AMDGPU_VM_PAGE_PRT (1 << 4) |
| 315 | #define AMDGPU_VM_MTYPE_MASK (0xf << 5) |
| 316 | #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) |
| 317 | #define AMDGPU_VM_MTYPE_NC (1 << 5) |
| 318 | #define AMDGPU_VM_MTYPE_WC (2 << 5) |
| 319 | #define AMDGPU_VM_MTYPE_CC (3 << 5) |
| 320 | #define AMDGPU_VM_MTYPE_UC (4 << 5) |
| 321 | #define AMDGPU_VM_MTYPE_RW (5 << 5) |
| 322 | struct drm_amdgpu_gem_va { |
| 323 | __u32 handle; |
| 324 | __u32 _pad; |
| 325 | __u32 operation; |
| 326 | __u32 flags; |
| 327 | __u64 va_address; |
| 328 | __u64 offset_in_bo; |
| 329 | __u64 map_size; |
| 330 | }; |
| 331 | #define AMDGPU_HW_IP_GFX 0 |
| 332 | #define AMDGPU_HW_IP_COMPUTE 1 |
| 333 | #define AMDGPU_HW_IP_DMA 2 |
| 334 | #define AMDGPU_HW_IP_UVD 3 |
| 335 | #define AMDGPU_HW_IP_VCE 4 |
| 336 | #define AMDGPU_HW_IP_UVD_ENC 5 |
| 337 | #define AMDGPU_HW_IP_VCN_DEC 6 |
| 338 | #define AMDGPU_HW_IP_VCN_ENC 7 |
| 339 | #define AMDGPU_HW_IP_VCN_JPEG 8 |
| 340 | #define AMDGPU_HW_IP_NUM 9 |
| 341 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 |
| 342 | #define AMDGPU_CHUNK_ID_IB 0x01 |
| 343 | #define AMDGPU_CHUNK_ID_FENCE 0x02 |
| 344 | #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 |
| 345 | #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 |
| 346 | #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 |
| 347 | #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 |
| 348 | #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 |
| 349 | #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 |
| 350 | #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 |
| 351 | struct drm_amdgpu_cs_chunk { |
| 352 | __u32 chunk_id; |
| 353 | __u32 length_dw; |
| 354 | __u64 chunk_data; |
| 355 | }; |
| 356 | struct drm_amdgpu_cs_in { |
| 357 | __u32 ctx_id; |
| 358 | __u32 bo_list_handle; |
| 359 | __u32 num_chunks; |
| 360 | __u32 flags; |
| 361 | __u64 chunks; |
| 362 | }; |
| 363 | struct drm_amdgpu_cs_out { |
| 364 | __u64 handle; |
| 365 | }; |
| 366 | union drm_amdgpu_cs { |
| 367 | struct drm_amdgpu_cs_in in; |
| 368 | struct drm_amdgpu_cs_out out; |
| 369 | }; |
| 370 | #define AMDGPU_IB_FLAG_CE (1 << 0) |
| 371 | #define AMDGPU_IB_FLAG_PREAMBLE (1 << 1) |
| 372 | #define AMDGPU_IB_FLAG_PREEMPT (1 << 2) |
| 373 | #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) |
| 374 | #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) |
| 375 | #define AMDGPU_IB_FLAGS_SECURE (1 << 5) |
| 376 | #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) |
| 377 | struct drm_amdgpu_cs_chunk_ib { |
| 378 | __u32 _pad; |
| 379 | __u32 flags; |
| 380 | __u64 va_start; |
| 381 | __u32 ib_bytes; |
| 382 | __u32 ip_type; |
| 383 | __u32 ip_instance; |
| 384 | __u32 ring; |
| 385 | }; |
| 386 | struct drm_amdgpu_cs_chunk_dep { |
| 387 | __u32 ip_type; |
| 388 | __u32 ip_instance; |
| 389 | __u32 ring; |
| 390 | __u32 ctx_id; |
| 391 | __u64 handle; |
| 392 | }; |
| 393 | struct drm_amdgpu_cs_chunk_fence { |
| 394 | __u32 handle; |
| 395 | __u32 offset; |
| 396 | }; |
| 397 | struct drm_amdgpu_cs_chunk_sem { |
| 398 | __u32 handle; |
| 399 | }; |
| 400 | struct drm_amdgpu_cs_chunk_syncobj { |
| 401 | __u32 handle; |
| 402 | __u32 flags; |
| 403 | __u64 point; |
| 404 | }; |
| 405 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 |
| 406 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 |
| 407 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 |
| 408 | union drm_amdgpu_fence_to_handle { |
| 409 | struct { |
| 410 | struct drm_amdgpu_fence fence; |
| 411 | __u32 what; |
| 412 | __u32 pad; |
| 413 | } in; |
| 414 | struct { |
| 415 | __u32 handle; |
| 416 | } out; |
| 417 | }; |
| 418 | struct drm_amdgpu_cs_chunk_data { |
| 419 | union { |
| 420 | struct drm_amdgpu_cs_chunk_ib ib_data; |
| 421 | struct drm_amdgpu_cs_chunk_fence fence_data; |
| 422 | }; |
| 423 | }; |
| 424 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 |
| 425 | #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 |
| 426 | #define AMDGPU_IDS_FLAGS_TMZ 0x4 |
| 427 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 |
| 428 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 |
| 429 | #define AMDGPU_INFO_HW_IP_INFO 0x02 |
| 430 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 |
| 431 | #define AMDGPU_INFO_TIMESTAMP 0x05 |
| 432 | #define AMDGPU_INFO_FW_VERSION 0x0e |
| 433 | #define AMDGPU_INFO_FW_VCE 0x1 |
| 434 | #define AMDGPU_INFO_FW_UVD 0x2 |
| 435 | #define AMDGPU_INFO_FW_GMC 0x03 |
| 436 | #define AMDGPU_INFO_FW_GFX_ME 0x04 |
| 437 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 |
| 438 | #define AMDGPU_INFO_FW_GFX_CE 0x06 |
| 439 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 |
| 440 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 |
| 441 | #define AMDGPU_INFO_FW_SMC 0x0a |
| 442 | #define AMDGPU_INFO_FW_SDMA 0x0b |
| 443 | #define AMDGPU_INFO_FW_SOS 0x0c |
| 444 | #define AMDGPU_INFO_FW_ASD 0x0d |
| 445 | #define AMDGPU_INFO_FW_VCN 0x0e |
| 446 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f |
| 447 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 |
| 448 | #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 |
| 449 | #define AMDGPU_INFO_FW_DMCU 0x12 |
| 450 | #define AMDGPU_INFO_FW_TA 0x13 |
| 451 | #define AMDGPU_INFO_FW_DMCUB 0x14 |
| 452 | #define AMDGPU_INFO_FW_TOC 0x15 |
Jordan Demeulenaere | 2d50582 | 2022-08-11 17:20:14 +0200 | [diff] [blame] | 453 | #define AMDGPU_INFO_FW_CAP 0x16 |
Colin Cross | 07a5832 | 2022-02-08 19:45:27 -0800 | [diff] [blame] | 454 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f |
| 455 | #define AMDGPU_INFO_VRAM_USAGE 0x10 |
| 456 | #define AMDGPU_INFO_GTT_USAGE 0x11 |
| 457 | #define AMDGPU_INFO_GDS_CONFIG 0x13 |
| 458 | #define AMDGPU_INFO_VRAM_GTT 0x14 |
| 459 | #define AMDGPU_INFO_READ_MMR_REG 0x15 |
| 460 | #define AMDGPU_INFO_DEV_INFO 0x16 |
| 461 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 |
| 462 | #define AMDGPU_INFO_NUM_EVICTIONS 0x18 |
| 463 | #define AMDGPU_INFO_MEMORY 0x19 |
| 464 | #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A |
| 465 | #define AMDGPU_INFO_VBIOS 0x1B |
| 466 | #define AMDGPU_INFO_VBIOS_SIZE 0x1 |
| 467 | #define AMDGPU_INFO_VBIOS_IMAGE 0x2 |
| 468 | #define AMDGPU_INFO_VBIOS_INFO 0x3 |
| 469 | #define AMDGPU_INFO_NUM_HANDLES 0x1C |
| 470 | #define AMDGPU_INFO_SENSOR 0x1D |
| 471 | #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 |
| 472 | #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 |
| 473 | #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 |
| 474 | #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 |
| 475 | #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 |
| 476 | #define AMDGPU_INFO_SENSOR_VDDNB 0x6 |
| 477 | #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 |
| 478 | #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 |
| 479 | #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 |
| 480 | #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E |
| 481 | #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F |
| 482 | #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 |
| 483 | #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) |
| 484 | #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) |
| 485 | #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) |
| 486 | #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) |
| 487 | #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) |
| 488 | #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) |
| 489 | #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) |
| 490 | #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) |
| 491 | #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) |
| 492 | #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) |
| 493 | #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) |
| 494 | #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) |
| 495 | #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) |
| 496 | #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) |
| 497 | #define AMDGPU_INFO_VIDEO_CAPS 0x21 |
| 498 | #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 |
| 499 | #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 |
| 500 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 |
| 501 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff |
| 502 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 |
| 503 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff |
| 504 | struct drm_amdgpu_query_fw { |
| 505 | __u32 fw_type; |
| 506 | __u32 ip_instance; |
| 507 | __u32 index; |
| 508 | __u32 _pad; |
| 509 | }; |
| 510 | struct drm_amdgpu_info { |
| 511 | __u64 return_pointer; |
| 512 | __u32 return_size; |
| 513 | __u32 query; |
| 514 | union { |
| 515 | struct { |
| 516 | __u32 id; |
| 517 | __u32 _pad; |
| 518 | } mode_crtc; |
| 519 | struct { |
| 520 | __u32 type; |
| 521 | __u32 ip_instance; |
| 522 | } query_hw_ip; |
| 523 | struct { |
| 524 | __u32 dword_offset; |
| 525 | __u32 count; |
| 526 | __u32 instance; |
| 527 | __u32 flags; |
| 528 | } read_mmr_reg; |
| 529 | struct drm_amdgpu_query_fw query_fw; |
| 530 | struct { |
| 531 | __u32 type; |
| 532 | __u32 offset; |
| 533 | } vbios_info; |
| 534 | struct { |
| 535 | __u32 type; |
| 536 | } sensor_info; |
| 537 | struct { |
| 538 | __u32 type; |
| 539 | } video_cap; |
| 540 | }; |
| 541 | }; |
| 542 | struct drm_amdgpu_info_gds { |
| 543 | __u32 gds_gfx_partition_size; |
| 544 | __u32 compute_partition_size; |
| 545 | __u32 gds_total_size; |
| 546 | __u32 gws_per_gfx_partition; |
| 547 | __u32 gws_per_compute_partition; |
| 548 | __u32 oa_per_gfx_partition; |
| 549 | __u32 oa_per_compute_partition; |
| 550 | __u32 _pad; |
| 551 | }; |
| 552 | struct drm_amdgpu_info_vram_gtt { |
| 553 | __u64 vram_size; |
| 554 | __u64 vram_cpu_accessible_size; |
| 555 | __u64 gtt_size; |
| 556 | }; |
| 557 | struct drm_amdgpu_heap_info { |
| 558 | __u64 total_heap_size; |
| 559 | __u64 usable_heap_size; |
| 560 | __u64 heap_usage; |
| 561 | __u64 max_allocation; |
| 562 | }; |
| 563 | struct drm_amdgpu_memory_info { |
| 564 | struct drm_amdgpu_heap_info vram; |
| 565 | struct drm_amdgpu_heap_info cpu_accessible_vram; |
| 566 | struct drm_amdgpu_heap_info gtt; |
| 567 | }; |
| 568 | struct drm_amdgpu_info_firmware { |
| 569 | __u32 ver; |
| 570 | __u32 feature; |
| 571 | }; |
| 572 | struct drm_amdgpu_info_vbios { |
| 573 | __u8 name[64]; |
| 574 | __u8 vbios_pn[64]; |
| 575 | __u32 version; |
| 576 | __u32 pad; |
| 577 | __u8 vbios_ver_str[32]; |
| 578 | __u8 date[32]; |
| 579 | }; |
| 580 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
| 581 | #define AMDGPU_VRAM_TYPE_GDDR1 1 |
| 582 | #define AMDGPU_VRAM_TYPE_DDR2 2 |
| 583 | #define AMDGPU_VRAM_TYPE_GDDR3 3 |
| 584 | #define AMDGPU_VRAM_TYPE_GDDR4 4 |
| 585 | #define AMDGPU_VRAM_TYPE_GDDR5 5 |
| 586 | #define AMDGPU_VRAM_TYPE_HBM 6 |
| 587 | #define AMDGPU_VRAM_TYPE_DDR3 7 |
| 588 | #define AMDGPU_VRAM_TYPE_DDR4 8 |
| 589 | #define AMDGPU_VRAM_TYPE_GDDR6 9 |
| 590 | #define AMDGPU_VRAM_TYPE_DDR5 10 |
| 591 | struct drm_amdgpu_info_device { |
| 592 | __u32 device_id; |
| 593 | __u32 chip_rev; |
| 594 | __u32 external_rev; |
| 595 | __u32 pci_rev; |
| 596 | __u32 family; |
| 597 | __u32 num_shader_engines; |
| 598 | __u32 num_shader_arrays_per_engine; |
| 599 | __u32 gpu_counter_freq; |
| 600 | __u64 max_engine_clock; |
| 601 | __u64 max_memory_clock; |
| 602 | __u32 cu_active_number; |
| 603 | __u32 cu_ao_mask; |
| 604 | __u32 cu_bitmap[4][4]; |
| 605 | __u32 enabled_rb_pipes_mask; |
| 606 | __u32 num_rb_pipes; |
| 607 | __u32 num_hw_gfx_contexts; |
| 608 | __u32 _pad; |
| 609 | __u64 ids_flags; |
| 610 | __u64 virtual_address_offset; |
| 611 | __u64 virtual_address_max; |
| 612 | __u32 virtual_address_alignment; |
| 613 | __u32 pte_fragment_size; |
| 614 | __u32 gart_page_size; |
| 615 | __u32 ce_ram_size; |
| 616 | __u32 vram_type; |
| 617 | __u32 vram_bit_width; |
| 618 | __u32 vce_harvest_config; |
| 619 | __u32 gc_double_offchip_lds_buf; |
| 620 | __u64 prim_buf_gpu_addr; |
| 621 | __u64 pos_buf_gpu_addr; |
| 622 | __u64 cntl_sb_buf_gpu_addr; |
| 623 | __u64 param_buf_gpu_addr; |
| 624 | __u32 prim_buf_size; |
| 625 | __u32 pos_buf_size; |
| 626 | __u32 cntl_sb_buf_size; |
| 627 | __u32 param_buf_size; |
| 628 | __u32 wave_front_size; |
| 629 | __u32 num_shader_visible_vgprs; |
| 630 | __u32 num_cu_per_sh; |
| 631 | __u32 num_tcc_blocks; |
| 632 | __u32 gs_vgt_table_depth; |
| 633 | __u32 gs_prim_buffer_depth; |
| 634 | __u32 max_gs_waves_per_vgt; |
| 635 | __u32 _pad1; |
| 636 | __u32 cu_ao_bitmap[4][4]; |
| 637 | __u64 high_va_offset; |
| 638 | __u64 high_va_max; |
| 639 | __u32 pa_sc_tile_steering_override; |
| 640 | __u64 tcc_disabled_mask; |
| 641 | }; |
| 642 | struct drm_amdgpu_info_hw_ip { |
| 643 | __u32 hw_ip_version_major; |
| 644 | __u32 hw_ip_version_minor; |
| 645 | __u64 capabilities_flags; |
| 646 | __u32 ib_start_alignment; |
| 647 | __u32 ib_size_alignment; |
| 648 | __u32 available_rings; |
| 649 | __u32 _pad; |
| 650 | }; |
| 651 | struct drm_amdgpu_info_num_handles { |
| 652 | __u32 uvd_max_handles; |
| 653 | __u32 uvd_used_handles; |
| 654 | }; |
| 655 | #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 |
| 656 | struct drm_amdgpu_info_vce_clock_table_entry { |
| 657 | __u32 sclk; |
| 658 | __u32 mclk; |
| 659 | __u32 eclk; |
| 660 | __u32 pad; |
| 661 | }; |
| 662 | struct drm_amdgpu_info_vce_clock_table { |
| 663 | struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; |
| 664 | __u32 num_valid_entries; |
| 665 | __u32 pad; |
| 666 | }; |
| 667 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 |
| 668 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 |
| 669 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 |
| 670 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 |
| 671 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 |
| 672 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 |
| 673 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 |
| 674 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 |
| 675 | #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 |
| 676 | struct drm_amdgpu_info_video_codec_info { |
| 677 | __u32 valid; |
| 678 | __u32 max_width; |
| 679 | __u32 max_height; |
| 680 | __u32 max_pixels_per_frame; |
| 681 | __u32 max_level; |
| 682 | __u32 pad; |
| 683 | }; |
| 684 | struct drm_amdgpu_info_video_caps { |
| 685 | struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; |
| 686 | }; |
| 687 | #define AMDGPU_FAMILY_UNKNOWN 0 |
| 688 | #define AMDGPU_FAMILY_SI 110 |
| 689 | #define AMDGPU_FAMILY_CI 120 |
| 690 | #define AMDGPU_FAMILY_KV 125 |
| 691 | #define AMDGPU_FAMILY_VI 130 |
| 692 | #define AMDGPU_FAMILY_CZ 135 |
| 693 | #define AMDGPU_FAMILY_AI 141 |
| 694 | #define AMDGPU_FAMILY_RV 142 |
| 695 | #define AMDGPU_FAMILY_NV 143 |
| 696 | #define AMDGPU_FAMILY_VGH 144 |
| 697 | #define AMDGPU_FAMILY_YC 146 |
Jordan Demeulenaere | 2d50582 | 2022-08-11 17:20:14 +0200 | [diff] [blame] | 698 | #define AMDGPU_FAMILY_GC_10_3_6 149 |
| 699 | #define AMDGPU_FAMILY_GC_10_3_7 151 |
Colin Cross | 07a5832 | 2022-02-08 19:45:27 -0800 | [diff] [blame] | 700 | #ifdef __cplusplus |
| 701 | } |
| 702 | #endif |
| 703 | #endif |