blob: 0caf698ea3466b0a2b9c905e62db8d1db939e0bb [file] [log] [blame]
Colin Cross07a58322022-02-08 19:45:27 -08001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPILINUX_SERIAL_CORE_H
20#define _UAPILINUX_SERIAL_CORE_H
21#include <linux/serial.h>
22#define PORT_NS16550A 14
23#define PORT_XSCALE 15
24#define PORT_RM9000 16
25#define PORT_OCTEON 17
26#define PORT_AR7 18
27#define PORT_U6_16550A 19
28#define PORT_TEGRA 20
29#define PORT_XR17D15X 21
30#define PORT_LPC3220 22
31#define PORT_8250_CIR 23
32#define PORT_XR17V35X 24
33#define PORT_BRCM_TRUMANAGE 25
34#define PORT_ALTR_16550_F32 26
35#define PORT_ALTR_16550_F64 27
36#define PORT_ALTR_16550_F128 28
37#define PORT_RT2880 29
38#define PORT_16550A_FSL64 30
39#define PORT_PXA 31
40#define PORT_AMBA 32
41#define PORT_CLPS711X 33
42#define PORT_SA1100 34
43#define PORT_UART00 35
44#define PORT_OWL 36
45#define PORT_21285 37
46#define PORT_SUNZILOG 38
47#define PORT_SUNSAB 39
48#define PORT_NPCM 40
49#define PORT_TEGRA_TCU 41
50#define PORT_PCH_8LINE 44
51#define PORT_PCH_2LINE 45
52#define PORT_DZ 46
53#define PORT_ZS 47
54#define PORT_MUX 48
55#define PORT_ATMEL 49
56#define PORT_MAC_ZILOG 50
57#define PORT_PMAC_ZILOG 51
58#define PORT_SCI 52
59#define PORT_SCIF 53
60#define PORT_IRDA 54
61#define PORT_S3C2410 55
62#define PORT_IP22ZILOG 56
63#define PORT_LH7A40X 57
64#define PORT_CPM 58
65#define PORT_MPC52xx 59
66#define PORT_ICOM 60
67#define PORT_S3C2440 61
68#define PORT_IMX 62
69#define PORT_MPSC 63
70#define PORT_TXX9 64
71#define PORT_VR41XX_SIU 65
72#define PORT_VR41XX_DSIU 66
73#define PORT_S3C2400 67
74#define PORT_M32R_SIO 68
75#define PORT_JSM 69
76#define PORT_SUNHV 72
77#define PORT_S3C2412 73
78#define PORT_UARTLITE 74
79#define PORT_BFIN 75
80#define PORT_SB1250_DUART 77
81#define PORT_MCF 78
82#define PORT_BFIN_SPORT 79
83#define PORT_MN10300 80
84#define PORT_MN10300_CTS 81
85#define PORT_SC26XX 82
86#define PORT_SCIFA 83
87#define PORT_S3C6400 84
88#define PORT_NWPSERIAL 85
89#define PORT_MAX3100 86
90#define PORT_TIMBUART 87
91#define PORT_MSM 88
92#define PORT_BCM63XX 89
93#define PORT_APBUART 90
94#define PORT_ALTERA_JTAGUART 91
95#define PORT_ALTERA_UART 92
96#define PORT_SCIFB 93
97#define PORT_MAX310X 94
98#define PORT_DA830 95
99#define PORT_OMAP 96
100#define PORT_VT8500 97
101#define PORT_XUARTPS 98
102#define PORT_AR933X 99
103#define PORT_ARC 101
104#define PORT_RP2 102
105#define PORT_LPUART 103
106#define PORT_HSCIF 104
107#define PORT_ASC 105
108#define PORT_TILEGX 106
109#define PORT_MEN_Z135 107
110#define PORT_SC16IS7XX 108
111#define PORT_MESON 109
112#define PORT_DIGICOLOR 110
113#define PORT_SPRD 111
114#define PORT_CRIS 112
115#define PORT_STM32 113
116#define PORT_MVEBU 114
117#define PORT_PIC32 115
118#define PORT_MPS2UART 116
119#define PORT_MTK_BTIF 117
120#define PORT_RDA 118
121#define PORT_MLB_USIO 119
122#define PORT_SIFIVE_V0 120
123#define PORT_SUNIX 121
124#define PORT_LINFLEXUART 122
125#endif