Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 1 | /*===------------- avx512vlvbmi2intrin.h - VBMI2 intrinsics -----------------=== |
| 2 | * |
| 3 | * |
Logan Chien | df4f766 | 2019-09-04 16:45:23 -0700 | [diff] [blame] | 4 | * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 5 | * See https://llvm.org/LICENSE.txt for license information. |
| 6 | * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 7 | * |
| 8 | *===-----------------------------------------------------------------------=== |
| 9 | */ |
| 10 | #ifndef __IMMINTRIN_H |
| 11 | #error "Never use <avx512vlvbmi2intrin.h> directly; include <immintrin.h> instead." |
| 12 | #endif |
| 13 | |
| 14 | #ifndef __AVX512VLVBMI2INTRIN_H |
| 15 | #define __AVX512VLVBMI2INTRIN_H |
| 16 | |
| 17 | /* Define the default attributes for the functions in this file. */ |
| 18 | #define __DEFAULT_FN_ATTRS128 __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vbmi2"), __min_vector_width__(128))) |
| 19 | #define __DEFAULT_FN_ATTRS256 __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vbmi2"), __min_vector_width__(256))) |
| 20 | |
| 21 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 22 | _mm_mask_compress_epi16(__m128i __S, __mmask8 __U, __m128i __D) |
| 23 | { |
| 24 | return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D, |
| 25 | (__v8hi) __S, |
| 26 | __U); |
| 27 | } |
| 28 | |
| 29 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 30 | _mm_maskz_compress_epi16(__mmask8 __U, __m128i __D) |
| 31 | { |
| 32 | return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D, |
| 33 | (__v8hi) _mm_setzero_si128(), |
| 34 | __U); |
| 35 | } |
| 36 | |
| 37 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 38 | _mm_mask_compress_epi8(__m128i __S, __mmask16 __U, __m128i __D) |
| 39 | { |
| 40 | return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D, |
| 41 | (__v16qi) __S, |
| 42 | __U); |
| 43 | } |
| 44 | |
| 45 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 46 | _mm_maskz_compress_epi8(__mmask16 __U, __m128i __D) |
| 47 | { |
| 48 | return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D, |
| 49 | (__v16qi) _mm_setzero_si128(), |
| 50 | __U); |
| 51 | } |
| 52 | |
| 53 | static __inline__ void __DEFAULT_FN_ATTRS128 |
| 54 | _mm_mask_compressstoreu_epi16(void *__P, __mmask8 __U, __m128i __D) |
| 55 | { |
| 56 | __builtin_ia32_compressstorehi128_mask ((__v8hi *) __P, (__v8hi) __D, |
| 57 | __U); |
| 58 | } |
| 59 | |
| 60 | static __inline__ void __DEFAULT_FN_ATTRS128 |
| 61 | _mm_mask_compressstoreu_epi8(void *__P, __mmask16 __U, __m128i __D) |
| 62 | { |
| 63 | __builtin_ia32_compressstoreqi128_mask ((__v16qi *) __P, (__v16qi) __D, |
| 64 | __U); |
| 65 | } |
| 66 | |
| 67 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 68 | _mm_mask_expand_epi16(__m128i __S, __mmask8 __U, __m128i __D) |
| 69 | { |
| 70 | return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D, |
| 71 | (__v8hi) __S, |
| 72 | __U); |
| 73 | } |
| 74 | |
| 75 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 76 | _mm_maskz_expand_epi16(__mmask8 __U, __m128i __D) |
| 77 | { |
| 78 | return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D, |
| 79 | (__v8hi) _mm_setzero_si128(), |
| 80 | __U); |
| 81 | } |
| 82 | |
| 83 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 84 | _mm_mask_expand_epi8(__m128i __S, __mmask16 __U, __m128i __D) |
| 85 | { |
| 86 | return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D, |
| 87 | (__v16qi) __S, |
| 88 | __U); |
| 89 | } |
| 90 | |
| 91 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 92 | _mm_maskz_expand_epi8(__mmask16 __U, __m128i __D) |
| 93 | { |
| 94 | return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D, |
| 95 | (__v16qi) _mm_setzero_si128(), |
| 96 | __U); |
| 97 | } |
| 98 | |
| 99 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 100 | _mm_mask_expandloadu_epi16(__m128i __S, __mmask8 __U, void const *__P) |
| 101 | { |
| 102 | return (__m128i) __builtin_ia32_expandloadhi128_mask ((const __v8hi *)__P, |
| 103 | (__v8hi) __S, |
| 104 | __U); |
| 105 | } |
| 106 | |
| 107 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 108 | _mm_maskz_expandloadu_epi16(__mmask8 __U, void const *__P) |
| 109 | { |
| 110 | return (__m128i) __builtin_ia32_expandloadhi128_mask ((const __v8hi *)__P, |
| 111 | (__v8hi) _mm_setzero_si128(), |
| 112 | __U); |
| 113 | } |
| 114 | |
| 115 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 116 | _mm_mask_expandloadu_epi8(__m128i __S, __mmask16 __U, void const *__P) |
| 117 | { |
| 118 | return (__m128i) __builtin_ia32_expandloadqi128_mask ((const __v16qi *)__P, |
| 119 | (__v16qi) __S, |
| 120 | __U); |
| 121 | } |
| 122 | |
| 123 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 124 | _mm_maskz_expandloadu_epi8(__mmask16 __U, void const *__P) |
| 125 | { |
| 126 | return (__m128i) __builtin_ia32_expandloadqi128_mask ((const __v16qi *)__P, |
| 127 | (__v16qi) _mm_setzero_si128(), |
| 128 | __U); |
| 129 | } |
| 130 | |
| 131 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 132 | _mm256_mask_compress_epi16(__m256i __S, __mmask16 __U, __m256i __D) |
| 133 | { |
| 134 | return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __D, |
| 135 | (__v16hi) __S, |
| 136 | __U); |
| 137 | } |
| 138 | |
| 139 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 140 | _mm256_maskz_compress_epi16(__mmask16 __U, __m256i __D) |
| 141 | { |
| 142 | return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __D, |
| 143 | (__v16hi) _mm256_setzero_si256(), |
| 144 | __U); |
| 145 | } |
| 146 | |
| 147 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 148 | _mm256_mask_compress_epi8(__m256i __S, __mmask32 __U, __m256i __D) |
| 149 | { |
| 150 | return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __D, |
| 151 | (__v32qi) __S, |
| 152 | __U); |
| 153 | } |
| 154 | |
| 155 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 156 | _mm256_maskz_compress_epi8(__mmask32 __U, __m256i __D) |
| 157 | { |
| 158 | return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __D, |
| 159 | (__v32qi) _mm256_setzero_si256(), |
| 160 | __U); |
| 161 | } |
| 162 | |
| 163 | static __inline__ void __DEFAULT_FN_ATTRS256 |
| 164 | _mm256_mask_compressstoreu_epi16(void *__P, __mmask16 __U, __m256i __D) |
| 165 | { |
| 166 | __builtin_ia32_compressstorehi256_mask ((__v16hi *) __P, (__v16hi) __D, |
| 167 | __U); |
| 168 | } |
| 169 | |
| 170 | static __inline__ void __DEFAULT_FN_ATTRS256 |
| 171 | _mm256_mask_compressstoreu_epi8(void *__P, __mmask32 __U, __m256i __D) |
| 172 | { |
| 173 | __builtin_ia32_compressstoreqi256_mask ((__v32qi *) __P, (__v32qi) __D, |
| 174 | __U); |
| 175 | } |
| 176 | |
| 177 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 178 | _mm256_mask_expand_epi16(__m256i __S, __mmask16 __U, __m256i __D) |
| 179 | { |
| 180 | return (__m256i) __builtin_ia32_expandhi256_mask ((__v16hi) __D, |
| 181 | (__v16hi) __S, |
| 182 | __U); |
| 183 | } |
| 184 | |
| 185 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 186 | _mm256_maskz_expand_epi16(__mmask16 __U, __m256i __D) |
| 187 | { |
| 188 | return (__m256i) __builtin_ia32_expandhi256_mask ((__v16hi) __D, |
| 189 | (__v16hi) _mm256_setzero_si256(), |
| 190 | __U); |
| 191 | } |
| 192 | |
| 193 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 194 | _mm256_mask_expand_epi8(__m256i __S, __mmask32 __U, __m256i __D) |
| 195 | { |
| 196 | return (__m256i) __builtin_ia32_expandqi256_mask ((__v32qi) __D, |
| 197 | (__v32qi) __S, |
| 198 | __U); |
| 199 | } |
| 200 | |
| 201 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 202 | _mm256_maskz_expand_epi8(__mmask32 __U, __m256i __D) |
| 203 | { |
| 204 | return (__m256i) __builtin_ia32_expandqi256_mask ((__v32qi) __D, |
| 205 | (__v32qi) _mm256_setzero_si256(), |
| 206 | __U); |
| 207 | } |
| 208 | |
| 209 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 210 | _mm256_mask_expandloadu_epi16(__m256i __S, __mmask16 __U, void const *__P) |
| 211 | { |
| 212 | return (__m256i) __builtin_ia32_expandloadhi256_mask ((const __v16hi *)__P, |
| 213 | (__v16hi) __S, |
| 214 | __U); |
| 215 | } |
| 216 | |
| 217 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 218 | _mm256_maskz_expandloadu_epi16(__mmask16 __U, void const *__P) |
| 219 | { |
| 220 | return (__m256i) __builtin_ia32_expandloadhi256_mask ((const __v16hi *)__P, |
| 221 | (__v16hi) _mm256_setzero_si256(), |
| 222 | __U); |
| 223 | } |
| 224 | |
| 225 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 226 | _mm256_mask_expandloadu_epi8(__m256i __S, __mmask32 __U, void const *__P) |
| 227 | { |
| 228 | return (__m256i) __builtin_ia32_expandloadqi256_mask ((const __v32qi *)__P, |
| 229 | (__v32qi) __S, |
| 230 | __U); |
| 231 | } |
| 232 | |
| 233 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 234 | _mm256_maskz_expandloadu_epi8(__mmask32 __U, void const *__P) |
| 235 | { |
| 236 | return (__m256i) __builtin_ia32_expandloadqi256_mask ((const __v32qi *)__P, |
| 237 | (__v32qi) _mm256_setzero_si256(), |
| 238 | __U); |
| 239 | } |
| 240 | |
| 241 | #define _mm256_shldi_epi64(A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 242 | ((__m256i)__builtin_ia32_vpshldq256((__v4di)(__m256i)(A), \ |
| 243 | (__v4di)(__m256i)(B), (int)(I))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 244 | |
| 245 | #define _mm256_mask_shldi_epi64(S, U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 246 | ((__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \ |
| 247 | (__v4di)_mm256_shldi_epi64((A), (B), (I)), \ |
| 248 | (__v4di)(__m256i)(S))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 249 | |
| 250 | #define _mm256_maskz_shldi_epi64(U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 251 | ((__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \ |
| 252 | (__v4di)_mm256_shldi_epi64((A), (B), (I)), \ |
| 253 | (__v4di)_mm256_setzero_si256())) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 254 | |
| 255 | #define _mm_shldi_epi64(A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 256 | ((__m128i)__builtin_ia32_vpshldq128((__v2di)(__m128i)(A), \ |
| 257 | (__v2di)(__m128i)(B), (int)(I))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 258 | |
| 259 | #define _mm_mask_shldi_epi64(S, U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 260 | ((__m128i)__builtin_ia32_selectq_128((__mmask8)(U), \ |
| 261 | (__v2di)_mm_shldi_epi64((A), (B), (I)), \ |
| 262 | (__v2di)(__m128i)(S))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 263 | |
| 264 | #define _mm_maskz_shldi_epi64(U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 265 | ((__m128i)__builtin_ia32_selectq_128((__mmask8)(U), \ |
| 266 | (__v2di)_mm_shldi_epi64((A), (B), (I)), \ |
| 267 | (__v2di)_mm_setzero_si128())) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 268 | |
| 269 | #define _mm256_shldi_epi32(A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 270 | ((__m256i)__builtin_ia32_vpshldd256((__v8si)(__m256i)(A), \ |
| 271 | (__v8si)(__m256i)(B), (int)(I))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 272 | |
| 273 | #define _mm256_mask_shldi_epi32(S, U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 274 | ((__m256i)__builtin_ia32_selectd_256((__mmask8)(U), \ |
| 275 | (__v8si)_mm256_shldi_epi32((A), (B), (I)), \ |
| 276 | (__v8si)(__m256i)(S))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 277 | |
| 278 | #define _mm256_maskz_shldi_epi32(U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 279 | ((__m256i)__builtin_ia32_selectd_256((__mmask8)(U), \ |
| 280 | (__v8si)_mm256_shldi_epi32((A), (B), (I)), \ |
| 281 | (__v8si)_mm256_setzero_si256())) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 282 | |
| 283 | #define _mm_shldi_epi32(A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 284 | ((__m128i)__builtin_ia32_vpshldd128((__v4si)(__m128i)(A), \ |
| 285 | (__v4si)(__m128i)(B), (int)(I))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 286 | |
| 287 | #define _mm_mask_shldi_epi32(S, U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 288 | ((__m128i)__builtin_ia32_selectd_128((__mmask8)(U), \ |
| 289 | (__v4si)_mm_shldi_epi32((A), (B), (I)), \ |
| 290 | (__v4si)(__m128i)(S))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 291 | |
| 292 | #define _mm_maskz_shldi_epi32(U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 293 | ((__m128i)__builtin_ia32_selectd_128((__mmask8)(U), \ |
| 294 | (__v4si)_mm_shldi_epi32((A), (B), (I)), \ |
| 295 | (__v4si)_mm_setzero_si128())) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 296 | |
| 297 | #define _mm256_shldi_epi16(A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 298 | ((__m256i)__builtin_ia32_vpshldw256((__v16hi)(__m256i)(A), \ |
| 299 | (__v16hi)(__m256i)(B), (int)(I))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 300 | |
| 301 | #define _mm256_mask_shldi_epi16(S, U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 302 | ((__m256i)__builtin_ia32_selectw_256((__mmask16)(U), \ |
| 303 | (__v16hi)_mm256_shldi_epi16((A), (B), (I)), \ |
| 304 | (__v16hi)(__m256i)(S))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 305 | |
| 306 | #define _mm256_maskz_shldi_epi16(U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 307 | ((__m256i)__builtin_ia32_selectw_256((__mmask16)(U), \ |
| 308 | (__v16hi)_mm256_shldi_epi16((A), (B), (I)), \ |
| 309 | (__v16hi)_mm256_setzero_si256())) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 310 | |
| 311 | #define _mm_shldi_epi16(A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 312 | ((__m128i)__builtin_ia32_vpshldw128((__v8hi)(__m128i)(A), \ |
| 313 | (__v8hi)(__m128i)(B), (int)(I))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 314 | |
| 315 | #define _mm_mask_shldi_epi16(S, U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 316 | ((__m128i)__builtin_ia32_selectw_128((__mmask8)(U), \ |
| 317 | (__v8hi)_mm_shldi_epi16((A), (B), (I)), \ |
| 318 | (__v8hi)(__m128i)(S))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 319 | |
| 320 | #define _mm_maskz_shldi_epi16(U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 321 | ((__m128i)__builtin_ia32_selectw_128((__mmask8)(U), \ |
| 322 | (__v8hi)_mm_shldi_epi16((A), (B), (I)), \ |
| 323 | (__v8hi)_mm_setzero_si128())) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 324 | |
| 325 | #define _mm256_shrdi_epi64(A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 326 | ((__m256i)__builtin_ia32_vpshrdq256((__v4di)(__m256i)(A), \ |
| 327 | (__v4di)(__m256i)(B), (int)(I))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 328 | |
| 329 | #define _mm256_mask_shrdi_epi64(S, U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 330 | ((__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \ |
| 331 | (__v4di)_mm256_shrdi_epi64((A), (B), (I)), \ |
| 332 | (__v4di)(__m256i)(S))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 333 | |
| 334 | #define _mm256_maskz_shrdi_epi64(U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 335 | ((__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \ |
| 336 | (__v4di)_mm256_shrdi_epi64((A), (B), (I)), \ |
| 337 | (__v4di)_mm256_setzero_si256())) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 338 | |
| 339 | #define _mm_shrdi_epi64(A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 340 | ((__m128i)__builtin_ia32_vpshrdq128((__v2di)(__m128i)(A), \ |
| 341 | (__v2di)(__m128i)(B), (int)(I))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 342 | |
| 343 | #define _mm_mask_shrdi_epi64(S, U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 344 | ((__m128i)__builtin_ia32_selectq_128((__mmask8)(U), \ |
| 345 | (__v2di)_mm_shrdi_epi64((A), (B), (I)), \ |
| 346 | (__v2di)(__m128i)(S))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 347 | |
| 348 | #define _mm_maskz_shrdi_epi64(U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 349 | ((__m128i)__builtin_ia32_selectq_128((__mmask8)(U), \ |
| 350 | (__v2di)_mm_shrdi_epi64((A), (B), (I)), \ |
| 351 | (__v2di)_mm_setzero_si128())) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 352 | |
| 353 | #define _mm256_shrdi_epi32(A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 354 | ((__m256i)__builtin_ia32_vpshrdd256((__v8si)(__m256i)(A), \ |
| 355 | (__v8si)(__m256i)(B), (int)(I))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 356 | |
| 357 | #define _mm256_mask_shrdi_epi32(S, U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 358 | ((__m256i)__builtin_ia32_selectd_256((__mmask8)(U), \ |
| 359 | (__v8si)_mm256_shrdi_epi32((A), (B), (I)), \ |
| 360 | (__v8si)(__m256i)(S))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 361 | |
| 362 | #define _mm256_maskz_shrdi_epi32(U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 363 | ((__m256i)__builtin_ia32_selectd_256((__mmask8)(U), \ |
| 364 | (__v8si)_mm256_shrdi_epi32((A), (B), (I)), \ |
| 365 | (__v8si)_mm256_setzero_si256())) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 366 | |
| 367 | #define _mm_shrdi_epi32(A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 368 | ((__m128i)__builtin_ia32_vpshrdd128((__v4si)(__m128i)(A), \ |
| 369 | (__v4si)(__m128i)(B), (int)(I))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 370 | |
| 371 | #define _mm_mask_shrdi_epi32(S, U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 372 | ((__m128i)__builtin_ia32_selectd_128((__mmask8)(U), \ |
| 373 | (__v4si)_mm_shrdi_epi32((A), (B), (I)), \ |
| 374 | (__v4si)(__m128i)(S))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 375 | |
| 376 | #define _mm_maskz_shrdi_epi32(U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 377 | ((__m128i)__builtin_ia32_selectd_128((__mmask8)(U), \ |
| 378 | (__v4si)_mm_shrdi_epi32((A), (B), (I)), \ |
| 379 | (__v4si)_mm_setzero_si128())) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 380 | |
| 381 | #define _mm256_shrdi_epi16(A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 382 | ((__m256i)__builtin_ia32_vpshrdw256((__v16hi)(__m256i)(A), \ |
| 383 | (__v16hi)(__m256i)(B), (int)(I))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 384 | |
| 385 | #define _mm256_mask_shrdi_epi16(S, U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 386 | ((__m256i)__builtin_ia32_selectw_256((__mmask16)(U), \ |
| 387 | (__v16hi)_mm256_shrdi_epi16((A), (B), (I)), \ |
| 388 | (__v16hi)(__m256i)(S))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 389 | |
| 390 | #define _mm256_maskz_shrdi_epi16(U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 391 | ((__m256i)__builtin_ia32_selectw_256((__mmask16)(U), \ |
| 392 | (__v16hi)_mm256_shrdi_epi16((A), (B), (I)), \ |
| 393 | (__v16hi)_mm256_setzero_si256())) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 394 | |
| 395 | #define _mm_shrdi_epi16(A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 396 | ((__m128i)__builtin_ia32_vpshrdw128((__v8hi)(__m128i)(A), \ |
| 397 | (__v8hi)(__m128i)(B), (int)(I))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 398 | |
| 399 | #define _mm_mask_shrdi_epi16(S, U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 400 | ((__m128i)__builtin_ia32_selectw_128((__mmask8)(U), \ |
| 401 | (__v8hi)_mm_shrdi_epi16((A), (B), (I)), \ |
| 402 | (__v8hi)(__m128i)(S))) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 403 | |
| 404 | #define _mm_maskz_shrdi_epi16(U, A, B, I) \ |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 405 | ((__m128i)__builtin_ia32_selectw_128((__mmask8)(U), \ |
| 406 | (__v8hi)_mm_shrdi_epi16((A), (B), (I)), \ |
| 407 | (__v8hi)_mm_setzero_si128())) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 408 | |
| 409 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 410 | _mm256_shldv_epi64(__m256i __A, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 411 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 412 | return (__m256i)__builtin_ia32_vpshldvq256((__v4di)__A, (__v4di)__B, |
| 413 | (__v4di)__C); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 414 | } |
| 415 | |
| 416 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 417 | _mm256_mask_shldv_epi64(__m256i __A, __mmask8 __U, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 418 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 419 | return (__m256i)__builtin_ia32_selectq_256(__U, |
| 420 | (__v4di)_mm256_shldv_epi64(__A, __B, __C), |
| 421 | (__v4di)__A); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 422 | } |
| 423 | |
| 424 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 425 | _mm256_maskz_shldv_epi64(__mmask8 __U, __m256i __A, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 426 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 427 | return (__m256i)__builtin_ia32_selectq_256(__U, |
| 428 | (__v4di)_mm256_shldv_epi64(__A, __B, __C), |
| 429 | (__v4di)_mm256_setzero_si256()); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 430 | } |
| 431 | |
| 432 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 433 | _mm_shldv_epi64(__m128i __A, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 434 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 435 | return (__m128i)__builtin_ia32_vpshldvq128((__v2di)__A, (__v2di)__B, |
| 436 | (__v2di)__C); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 437 | } |
| 438 | |
| 439 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 440 | _mm_mask_shldv_epi64(__m128i __A, __mmask8 __U, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 441 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 442 | return (__m128i)__builtin_ia32_selectq_128(__U, |
| 443 | (__v2di)_mm_shldv_epi64(__A, __B, __C), |
| 444 | (__v2di)__A); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 445 | } |
| 446 | |
| 447 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 448 | _mm_maskz_shldv_epi64(__mmask8 __U, __m128i __A, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 449 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 450 | return (__m128i)__builtin_ia32_selectq_128(__U, |
| 451 | (__v2di)_mm_shldv_epi64(__A, __B, __C), |
| 452 | (__v2di)_mm_setzero_si128()); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 453 | } |
| 454 | |
| 455 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 456 | _mm256_shldv_epi32(__m256i __A, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 457 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 458 | return (__m256i)__builtin_ia32_vpshldvd256((__v8si)__A, (__v8si)__B, |
| 459 | (__v8si)__C); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 460 | } |
| 461 | |
| 462 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 463 | _mm256_mask_shldv_epi32(__m256i __A, __mmask8 __U, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 464 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 465 | return (__m256i)__builtin_ia32_selectd_256(__U, |
| 466 | (__v8si)_mm256_shldv_epi32(__A, __B, __C), |
| 467 | (__v8si)__A); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 468 | } |
| 469 | |
| 470 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 471 | _mm256_maskz_shldv_epi32(__mmask8 __U, __m256i __A, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 472 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 473 | return (__m256i)__builtin_ia32_selectd_256(__U, |
| 474 | (__v8si)_mm256_shldv_epi32(__A, __B, __C), |
| 475 | (__v8si)_mm256_setzero_si256()); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 476 | } |
| 477 | |
| 478 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 479 | _mm_shldv_epi32(__m128i __A, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 480 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 481 | return (__m128i)__builtin_ia32_vpshldvd128((__v4si)__A, (__v4si)__B, |
| 482 | (__v4si)__C); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 483 | } |
| 484 | |
| 485 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 486 | _mm_mask_shldv_epi32(__m128i __A, __mmask8 __U, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 487 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 488 | return (__m128i)__builtin_ia32_selectd_128(__U, |
| 489 | (__v4si)_mm_shldv_epi32(__A, __B, __C), |
| 490 | (__v4si)__A); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 491 | } |
| 492 | |
| 493 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 494 | _mm_maskz_shldv_epi32(__mmask8 __U, __m128i __A, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 495 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 496 | return (__m128i)__builtin_ia32_selectd_128(__U, |
| 497 | (__v4si)_mm_shldv_epi32(__A, __B, __C), |
| 498 | (__v4si)_mm_setzero_si128()); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 499 | } |
| 500 | |
| 501 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 502 | _mm256_shldv_epi16(__m256i __A, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 503 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 504 | return (__m256i)__builtin_ia32_vpshldvw256((__v16hi)__A, (__v16hi)__B, |
| 505 | (__v16hi)__C); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 506 | } |
| 507 | |
| 508 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 509 | _mm256_mask_shldv_epi16(__m256i __A, __mmask16 __U, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 510 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 511 | return (__m256i)__builtin_ia32_selectw_256(__U, |
| 512 | (__v16hi)_mm256_shldv_epi16(__A, __B, __C), |
| 513 | (__v16hi)__A); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 514 | } |
| 515 | |
| 516 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 517 | _mm256_maskz_shldv_epi16(__mmask16 __U, __m256i __A, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 518 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 519 | return (__m256i)__builtin_ia32_selectw_256(__U, |
| 520 | (__v16hi)_mm256_shldv_epi16(__A, __B, __C), |
| 521 | (__v16hi)_mm256_setzero_si256()); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 522 | } |
| 523 | |
| 524 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 525 | _mm_shldv_epi16(__m128i __A, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 526 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 527 | return (__m128i)__builtin_ia32_vpshldvw128((__v8hi)__A, (__v8hi)__B, |
| 528 | (__v8hi)__C); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 529 | } |
| 530 | |
| 531 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 532 | _mm_mask_shldv_epi16(__m128i __A, __mmask8 __U, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 533 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 534 | return (__m128i)__builtin_ia32_selectw_128(__U, |
| 535 | (__v8hi)_mm_shldv_epi16(__A, __B, __C), |
| 536 | (__v8hi)__A); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 537 | } |
| 538 | |
| 539 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 540 | _mm_maskz_shldv_epi16(__mmask8 __U, __m128i __A, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 541 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 542 | return (__m128i)__builtin_ia32_selectw_128(__U, |
| 543 | (__v8hi)_mm_shldv_epi16(__A, __B, __C), |
| 544 | (__v8hi)_mm_setzero_si128()); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 545 | } |
| 546 | |
| 547 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 548 | _mm256_shrdv_epi64(__m256i __A, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 549 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 550 | return (__m256i)__builtin_ia32_vpshrdvq256((__v4di)__A, (__v4di)__B, |
| 551 | (__v4di)__C); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 552 | } |
| 553 | |
| 554 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 555 | _mm256_mask_shrdv_epi64(__m256i __A, __mmask8 __U, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 556 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 557 | return (__m256i)__builtin_ia32_selectq_256(__U, |
| 558 | (__v4di)_mm256_shrdv_epi64(__A, __B, __C), |
| 559 | (__v4di)__A); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 560 | } |
| 561 | |
| 562 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 563 | _mm256_maskz_shrdv_epi64(__mmask8 __U, __m256i __A, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 564 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 565 | return (__m256i)__builtin_ia32_selectq_256(__U, |
| 566 | (__v4di)_mm256_shrdv_epi64(__A, __B, __C), |
| 567 | (__v4di)_mm256_setzero_si256()); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 568 | } |
| 569 | |
| 570 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 571 | _mm_shrdv_epi64(__m128i __A, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 572 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 573 | return (__m128i)__builtin_ia32_vpshrdvq128((__v2di)__A, (__v2di)__B, |
| 574 | (__v2di)__C); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 575 | } |
| 576 | |
| 577 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 578 | _mm_mask_shrdv_epi64(__m128i __A, __mmask8 __U, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 579 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 580 | return (__m128i)__builtin_ia32_selectq_128(__U, |
| 581 | (__v2di)_mm_shrdv_epi64(__A, __B, __C), |
| 582 | (__v2di)__A); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 583 | } |
| 584 | |
| 585 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 586 | _mm_maskz_shrdv_epi64(__mmask8 __U, __m128i __A, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 587 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 588 | return (__m128i)__builtin_ia32_selectq_128(__U, |
| 589 | (__v2di)_mm_shrdv_epi64(__A, __B, __C), |
| 590 | (__v2di)_mm_setzero_si128()); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 591 | } |
| 592 | |
| 593 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 594 | _mm256_shrdv_epi32(__m256i __A, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 595 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 596 | return (__m256i)__builtin_ia32_vpshrdvd256((__v8si)__A, (__v8si)__B, |
| 597 | (__v8si)__C); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 598 | } |
| 599 | |
| 600 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 601 | _mm256_mask_shrdv_epi32(__m256i __A, __mmask8 __U, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 602 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 603 | return (__m256i)__builtin_ia32_selectd_256(__U, |
| 604 | (__v8si)_mm256_shrdv_epi32(__A, __B, __C), |
| 605 | (__v8si)__A); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 606 | } |
| 607 | |
| 608 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 609 | _mm256_maskz_shrdv_epi32(__mmask8 __U, __m256i __A, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 610 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 611 | return (__m256i)__builtin_ia32_selectd_256(__U, |
| 612 | (__v8si)_mm256_shrdv_epi32(__A, __B, __C), |
| 613 | (__v8si)_mm256_setzero_si256()); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 614 | } |
| 615 | |
| 616 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 617 | _mm_shrdv_epi32(__m128i __A, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 618 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 619 | return (__m128i)__builtin_ia32_vpshrdvd128((__v4si)__A, (__v4si)__B, |
| 620 | (__v4si)__C); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 621 | } |
| 622 | |
| 623 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 624 | _mm_mask_shrdv_epi32(__m128i __A, __mmask8 __U, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 625 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 626 | return (__m128i)__builtin_ia32_selectd_128(__U, |
| 627 | (__v4si)_mm_shrdv_epi32(__A, __B, __C), |
| 628 | (__v4si)__A); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 629 | } |
| 630 | |
| 631 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 632 | _mm_maskz_shrdv_epi32(__mmask8 __U, __m128i __A, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 633 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 634 | return (__m128i)__builtin_ia32_selectd_128(__U, |
| 635 | (__v4si)_mm_shrdv_epi32(__A, __B, __C), |
| 636 | (__v4si)_mm_setzero_si128()); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 637 | } |
| 638 | |
| 639 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 640 | _mm256_shrdv_epi16(__m256i __A, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 641 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 642 | return (__m256i)__builtin_ia32_vpshrdvw256((__v16hi)__A, (__v16hi)__B, |
| 643 | (__v16hi)__C); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 644 | } |
| 645 | |
| 646 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 647 | _mm256_mask_shrdv_epi16(__m256i __A, __mmask16 __U, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 648 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 649 | return (__m256i)__builtin_ia32_selectw_256(__U, |
| 650 | (__v16hi)_mm256_shrdv_epi16(__A, __B, __C), |
| 651 | (__v16hi)__A); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 652 | } |
| 653 | |
| 654 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 655 | _mm256_maskz_shrdv_epi16(__mmask16 __U, __m256i __A, __m256i __B, __m256i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 656 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 657 | return (__m256i)__builtin_ia32_selectw_256(__U, |
| 658 | (__v16hi)_mm256_shrdv_epi16(__A, __B, __C), |
| 659 | (__v16hi)_mm256_setzero_si256()); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 660 | } |
| 661 | |
| 662 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 663 | _mm_shrdv_epi16(__m128i __A, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 664 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 665 | return (__m128i)__builtin_ia32_vpshrdvw128((__v8hi)__A, (__v8hi)__B, |
| 666 | (__v8hi)__C); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 667 | } |
| 668 | |
| 669 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 670 | _mm_mask_shrdv_epi16(__m128i __A, __mmask8 __U, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 671 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 672 | return (__m128i)__builtin_ia32_selectw_128(__U, |
| 673 | (__v8hi)_mm_shrdv_epi16(__A, __B, __C), |
| 674 | (__v8hi)__A); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 675 | } |
| 676 | |
| 677 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 678 | _mm_maskz_shrdv_epi16(__mmask8 __U, __m128i __A, __m128i __B, __m128i __C) |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 679 | { |
Logan Chien | dbcf412 | 2019-03-21 10:50:25 +0800 | [diff] [blame] | 680 | return (__m128i)__builtin_ia32_selectw_128(__U, |
| 681 | (__v8hi)_mm_shrdv_epi16(__A, __B, __C), |
| 682 | (__v8hi)_mm_setzero_si128()); |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 683 | } |
| 684 | |
| 685 | |
| 686 | #undef __DEFAULT_FN_ATTRS128 |
| 687 | #undef __DEFAULT_FN_ATTRS256 |
| 688 | |
| 689 | #endif |