Logan Chien | 2833ffb | 2018-10-09 10:03:24 +0800 | [diff] [blame] | 1 | /*===---- prfchwintrin.h - PREFETCHW intrinsic -----------------------------=== |
| 2 | * |
Logan Chien | df4f766 | 2019-09-04 16:45:23 -0700 | [diff] [blame] | 3 | * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | * See https://llvm.org/LICENSE.txt for license information. |
| 5 | * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
Logan Chien | 2833ffb | 2018-10-09 10:03:24 +0800 | [diff] [blame] | 6 | * |
| 7 | *===-----------------------------------------------------------------------=== |
| 8 | */ |
| 9 | |
| 10 | #if !defined(__X86INTRIN_H) && !defined(_MM3DNOW_H_INCLUDED) |
| 11 | #error "Never use <prfchwintrin.h> directly; include <x86intrin.h> or <mm3dnow.h> instead." |
| 12 | #endif |
| 13 | |
| 14 | #ifndef __PRFCHWINTRIN_H |
| 15 | #define __PRFCHWINTRIN_H |
| 16 | |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 17 | /// Loads a memory sequence containing the specified memory address into |
| 18 | /// all data cache levels. The cache-coherency state is set to exclusive. |
| 19 | /// Data can be read from and written to the cache line without additional |
| 20 | /// delay. |
| 21 | /// |
| 22 | /// \headerfile <x86intrin.h> |
| 23 | /// |
| 24 | /// This intrinsic corresponds to the \c PREFETCHT0 instruction. |
| 25 | /// |
| 26 | /// \param __P |
| 27 | /// A pointer specifying the memory address to be prefetched. |
Logan Chien | 2833ffb | 2018-10-09 10:03:24 +0800 | [diff] [blame] | 28 | static __inline__ void __attribute__((__always_inline__, __nodebug__)) |
| 29 | _m_prefetch(void *__P) |
| 30 | { |
| 31 | __builtin_prefetch (__P, 0, 3 /* _MM_HINT_T0 */); |
| 32 | } |
| 33 | |
Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 34 | /// Loads a memory sequence containing the specified memory address into |
| 35 | /// the L1 data cache and sets the cache-coherency to modified. This |
| 36 | /// provides a hint to the processor that the cache line will be modified. |
| 37 | /// It is intended for use when the cache line will be written to shortly |
| 38 | /// after the prefetch is performed. |
| 39 | /// |
| 40 | /// Note that the effect of this intrinsic is dependent on the processor |
| 41 | /// implementation. |
| 42 | /// |
| 43 | /// \headerfile <x86intrin.h> |
| 44 | /// |
| 45 | /// This intrinsic corresponds to the \c PREFETCHW instruction. |
| 46 | /// |
| 47 | /// \param __P |
| 48 | /// A pointer specifying the memory address to be prefetched. |
Logan Chien | 2833ffb | 2018-10-09 10:03:24 +0800 | [diff] [blame] | 49 | static __inline__ void __attribute__((__always_inline__, __nodebug__)) |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 50 | _m_prefetchw(volatile const void *__P) |
Logan Chien | 2833ffb | 2018-10-09 10:03:24 +0800 | [diff] [blame] | 51 | { |
Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 52 | #pragma clang diagnostic push |
| 53 | #pragma clang diagnostic ignored "-Wcast-qual" |
| 54 | __builtin_prefetch ((const void*)__P, 1, 3 /* _MM_HINT_T0 */); |
| 55 | #pragma clang diagnostic pop |
Logan Chien | 2833ffb | 2018-10-09 10:03:24 +0800 | [diff] [blame] | 56 | } |
Logan Chien | 2833ffb | 2018-10-09 10:03:24 +0800 | [diff] [blame] | 57 | |
| 58 | #endif /* __PRFCHWINTRIN_H */ |