Logan Chien | 55afb0a | 2018-10-15 10:42:14 +0800 | [diff] [blame] | 1 | /*===------------- avx512vlvbmi2intrin.h - VBMI2 intrinsics -----------------=== |
| 2 | * |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 5 | * of this software and associated documentation files (the "Software"), to deal |
| 6 | * in the Software without restriction, including without limitation the rights |
| 7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 8 | * copies of the Software, and to permit persons to whom the Software is |
| 9 | * furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 17 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 20 | * THE SOFTWARE. |
| 21 | * |
| 22 | *===-----------------------------------------------------------------------=== |
| 23 | */ |
| 24 | #ifndef __IMMINTRIN_H |
| 25 | #error "Never use <avx512vlvbmi2intrin.h> directly; include <immintrin.h> instead." |
| 26 | #endif |
| 27 | |
| 28 | #ifndef __AVX512VLVBMI2INTRIN_H |
| 29 | #define __AVX512VLVBMI2INTRIN_H |
| 30 | |
| 31 | /* Define the default attributes for the functions in this file. */ |
| 32 | #define __DEFAULT_FN_ATTRS128 __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vbmi2"), __min_vector_width__(128))) |
| 33 | #define __DEFAULT_FN_ATTRS256 __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vbmi2"), __min_vector_width__(256))) |
| 34 | |
| 35 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 36 | _mm_mask_compress_epi16(__m128i __S, __mmask8 __U, __m128i __D) |
| 37 | { |
| 38 | return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D, |
| 39 | (__v8hi) __S, |
| 40 | __U); |
| 41 | } |
| 42 | |
| 43 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 44 | _mm_maskz_compress_epi16(__mmask8 __U, __m128i __D) |
| 45 | { |
| 46 | return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D, |
| 47 | (__v8hi) _mm_setzero_si128(), |
| 48 | __U); |
| 49 | } |
| 50 | |
| 51 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 52 | _mm_mask_compress_epi8(__m128i __S, __mmask16 __U, __m128i __D) |
| 53 | { |
| 54 | return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D, |
| 55 | (__v16qi) __S, |
| 56 | __U); |
| 57 | } |
| 58 | |
| 59 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 60 | _mm_maskz_compress_epi8(__mmask16 __U, __m128i __D) |
| 61 | { |
| 62 | return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D, |
| 63 | (__v16qi) _mm_setzero_si128(), |
| 64 | __U); |
| 65 | } |
| 66 | |
| 67 | static __inline__ void __DEFAULT_FN_ATTRS128 |
| 68 | _mm_mask_compressstoreu_epi16(void *__P, __mmask8 __U, __m128i __D) |
| 69 | { |
| 70 | __builtin_ia32_compressstorehi128_mask ((__v8hi *) __P, (__v8hi) __D, |
| 71 | __U); |
| 72 | } |
| 73 | |
| 74 | static __inline__ void __DEFAULT_FN_ATTRS128 |
| 75 | _mm_mask_compressstoreu_epi8(void *__P, __mmask16 __U, __m128i __D) |
| 76 | { |
| 77 | __builtin_ia32_compressstoreqi128_mask ((__v16qi *) __P, (__v16qi) __D, |
| 78 | __U); |
| 79 | } |
| 80 | |
| 81 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 82 | _mm_mask_expand_epi16(__m128i __S, __mmask8 __U, __m128i __D) |
| 83 | { |
| 84 | return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D, |
| 85 | (__v8hi) __S, |
| 86 | __U); |
| 87 | } |
| 88 | |
| 89 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 90 | _mm_maskz_expand_epi16(__mmask8 __U, __m128i __D) |
| 91 | { |
| 92 | return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D, |
| 93 | (__v8hi) _mm_setzero_si128(), |
| 94 | __U); |
| 95 | } |
| 96 | |
| 97 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 98 | _mm_mask_expand_epi8(__m128i __S, __mmask16 __U, __m128i __D) |
| 99 | { |
| 100 | return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D, |
| 101 | (__v16qi) __S, |
| 102 | __U); |
| 103 | } |
| 104 | |
| 105 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 106 | _mm_maskz_expand_epi8(__mmask16 __U, __m128i __D) |
| 107 | { |
| 108 | return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D, |
| 109 | (__v16qi) _mm_setzero_si128(), |
| 110 | __U); |
| 111 | } |
| 112 | |
| 113 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 114 | _mm_mask_expandloadu_epi16(__m128i __S, __mmask8 __U, void const *__P) |
| 115 | { |
| 116 | return (__m128i) __builtin_ia32_expandloadhi128_mask ((const __v8hi *)__P, |
| 117 | (__v8hi) __S, |
| 118 | __U); |
| 119 | } |
| 120 | |
| 121 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 122 | _mm_maskz_expandloadu_epi16(__mmask8 __U, void const *__P) |
| 123 | { |
| 124 | return (__m128i) __builtin_ia32_expandloadhi128_mask ((const __v8hi *)__P, |
| 125 | (__v8hi) _mm_setzero_si128(), |
| 126 | __U); |
| 127 | } |
| 128 | |
| 129 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 130 | _mm_mask_expandloadu_epi8(__m128i __S, __mmask16 __U, void const *__P) |
| 131 | { |
| 132 | return (__m128i) __builtin_ia32_expandloadqi128_mask ((const __v16qi *)__P, |
| 133 | (__v16qi) __S, |
| 134 | __U); |
| 135 | } |
| 136 | |
| 137 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 138 | _mm_maskz_expandloadu_epi8(__mmask16 __U, void const *__P) |
| 139 | { |
| 140 | return (__m128i) __builtin_ia32_expandloadqi128_mask ((const __v16qi *)__P, |
| 141 | (__v16qi) _mm_setzero_si128(), |
| 142 | __U); |
| 143 | } |
| 144 | |
| 145 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 146 | _mm256_mask_compress_epi16(__m256i __S, __mmask16 __U, __m256i __D) |
| 147 | { |
| 148 | return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __D, |
| 149 | (__v16hi) __S, |
| 150 | __U); |
| 151 | } |
| 152 | |
| 153 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 154 | _mm256_maskz_compress_epi16(__mmask16 __U, __m256i __D) |
| 155 | { |
| 156 | return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __D, |
| 157 | (__v16hi) _mm256_setzero_si256(), |
| 158 | __U); |
| 159 | } |
| 160 | |
| 161 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 162 | _mm256_mask_compress_epi8(__m256i __S, __mmask32 __U, __m256i __D) |
| 163 | { |
| 164 | return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __D, |
| 165 | (__v32qi) __S, |
| 166 | __U); |
| 167 | } |
| 168 | |
| 169 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 170 | _mm256_maskz_compress_epi8(__mmask32 __U, __m256i __D) |
| 171 | { |
| 172 | return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __D, |
| 173 | (__v32qi) _mm256_setzero_si256(), |
| 174 | __U); |
| 175 | } |
| 176 | |
| 177 | static __inline__ void __DEFAULT_FN_ATTRS256 |
| 178 | _mm256_mask_compressstoreu_epi16(void *__P, __mmask16 __U, __m256i __D) |
| 179 | { |
| 180 | __builtin_ia32_compressstorehi256_mask ((__v16hi *) __P, (__v16hi) __D, |
| 181 | __U); |
| 182 | } |
| 183 | |
| 184 | static __inline__ void __DEFAULT_FN_ATTRS256 |
| 185 | _mm256_mask_compressstoreu_epi8(void *__P, __mmask32 __U, __m256i __D) |
| 186 | { |
| 187 | __builtin_ia32_compressstoreqi256_mask ((__v32qi *) __P, (__v32qi) __D, |
| 188 | __U); |
| 189 | } |
| 190 | |
| 191 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 192 | _mm256_mask_expand_epi16(__m256i __S, __mmask16 __U, __m256i __D) |
| 193 | { |
| 194 | return (__m256i) __builtin_ia32_expandhi256_mask ((__v16hi) __D, |
| 195 | (__v16hi) __S, |
| 196 | __U); |
| 197 | } |
| 198 | |
| 199 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 200 | _mm256_maskz_expand_epi16(__mmask16 __U, __m256i __D) |
| 201 | { |
| 202 | return (__m256i) __builtin_ia32_expandhi256_mask ((__v16hi) __D, |
| 203 | (__v16hi) _mm256_setzero_si256(), |
| 204 | __U); |
| 205 | } |
| 206 | |
| 207 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 208 | _mm256_mask_expand_epi8(__m256i __S, __mmask32 __U, __m256i __D) |
| 209 | { |
| 210 | return (__m256i) __builtin_ia32_expandqi256_mask ((__v32qi) __D, |
| 211 | (__v32qi) __S, |
| 212 | __U); |
| 213 | } |
| 214 | |
| 215 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 216 | _mm256_maskz_expand_epi8(__mmask32 __U, __m256i __D) |
| 217 | { |
| 218 | return (__m256i) __builtin_ia32_expandqi256_mask ((__v32qi) __D, |
| 219 | (__v32qi) _mm256_setzero_si256(), |
| 220 | __U); |
| 221 | } |
| 222 | |
| 223 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 224 | _mm256_mask_expandloadu_epi16(__m256i __S, __mmask16 __U, void const *__P) |
| 225 | { |
| 226 | return (__m256i) __builtin_ia32_expandloadhi256_mask ((const __v16hi *)__P, |
| 227 | (__v16hi) __S, |
| 228 | __U); |
| 229 | } |
| 230 | |
| 231 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 232 | _mm256_maskz_expandloadu_epi16(__mmask16 __U, void const *__P) |
| 233 | { |
| 234 | return (__m256i) __builtin_ia32_expandloadhi256_mask ((const __v16hi *)__P, |
| 235 | (__v16hi) _mm256_setzero_si256(), |
| 236 | __U); |
| 237 | } |
| 238 | |
| 239 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 240 | _mm256_mask_expandloadu_epi8(__m256i __S, __mmask32 __U, void const *__P) |
| 241 | { |
| 242 | return (__m256i) __builtin_ia32_expandloadqi256_mask ((const __v32qi *)__P, |
| 243 | (__v32qi) __S, |
| 244 | __U); |
| 245 | } |
| 246 | |
| 247 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 248 | _mm256_maskz_expandloadu_epi8(__mmask32 __U, void const *__P) |
| 249 | { |
| 250 | return (__m256i) __builtin_ia32_expandloadqi256_mask ((const __v32qi *)__P, |
| 251 | (__v32qi) _mm256_setzero_si256(), |
| 252 | __U); |
| 253 | } |
| 254 | |
| 255 | #define _mm256_shldi_epi64(A, B, I) \ |
| 256 | (__m256i)__builtin_ia32_vpshldq256((__v4di)(__m256i)(A), \ |
| 257 | (__v4di)(__m256i)(B), (int)(I)) |
| 258 | |
| 259 | #define _mm256_mask_shldi_epi64(S, U, A, B, I) \ |
| 260 | (__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \ |
| 261 | (__v4di)_mm256_shldi_epi64((A), (B), (I)), \ |
| 262 | (__v4di)(__m256i)(S)) |
| 263 | |
| 264 | #define _mm256_maskz_shldi_epi64(U, A, B, I) \ |
| 265 | (__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \ |
| 266 | (__v4di)_mm256_shldi_epi64((A), (B), (I)), \ |
| 267 | (__v4di)_mm256_setzero_si256()) |
| 268 | |
| 269 | #define _mm_shldi_epi64(A, B, I) \ |
| 270 | (__m128i)__builtin_ia32_vpshldq128((__v2di)(__m128i)(A), \ |
| 271 | (__v2di)(__m128i)(B), (int)(I)) |
| 272 | |
| 273 | #define _mm_mask_shldi_epi64(S, U, A, B, I) \ |
| 274 | (__m128i)__builtin_ia32_selectq_128((__mmask8)(U), \ |
| 275 | (__v2di)_mm_shldi_epi64((A), (B), (I)), \ |
| 276 | (__v2di)(__m128i)(S)) |
| 277 | |
| 278 | #define _mm_maskz_shldi_epi64(U, A, B, I) \ |
| 279 | (__m128i)__builtin_ia32_selectq_128((__mmask8)(U), \ |
| 280 | (__v2di)_mm_shldi_epi64((A), (B), (I)), \ |
| 281 | (__v2di)_mm_setzero_si128()) |
| 282 | |
| 283 | #define _mm256_shldi_epi32(A, B, I) \ |
| 284 | (__m256i)__builtin_ia32_vpshldd256((__v8si)(__m256i)(A), \ |
| 285 | (__v8si)(__m256i)(B), (int)(I)) |
| 286 | |
| 287 | #define _mm256_mask_shldi_epi32(S, U, A, B, I) \ |
| 288 | (__m256i)__builtin_ia32_selectd_256((__mmask8)(U), \ |
| 289 | (__v8si)_mm256_shldi_epi32((A), (B), (I)), \ |
| 290 | (__v8si)(__m256i)(S)) |
| 291 | |
| 292 | #define _mm256_maskz_shldi_epi32(U, A, B, I) \ |
| 293 | (__m256i)__builtin_ia32_selectd_256((__mmask8)(U), \ |
| 294 | (__v8si)_mm256_shldi_epi32((A), (B), (I)), \ |
| 295 | (__v8si)_mm256_setzero_si256()) |
| 296 | |
| 297 | #define _mm_shldi_epi32(A, B, I) \ |
| 298 | (__m128i)__builtin_ia32_vpshldd128((__v4si)(__m128i)(A), \ |
| 299 | (__v4si)(__m128i)(B), (int)(I)) |
| 300 | |
| 301 | #define _mm_mask_shldi_epi32(S, U, A, B, I) \ |
| 302 | (__m128i)__builtin_ia32_selectd_128((__mmask8)(U), \ |
| 303 | (__v4si)_mm_shldi_epi32((A), (B), (I)), \ |
| 304 | (__v4si)(__m128i)(S)) |
| 305 | |
| 306 | #define _mm_maskz_shldi_epi32(U, A, B, I) \ |
| 307 | (__m128i)__builtin_ia32_selectd_128((__mmask8)(U), \ |
| 308 | (__v4si)_mm_shldi_epi32((A), (B), (I)), \ |
| 309 | (__v4si)_mm_setzero_si128()) |
| 310 | |
| 311 | #define _mm256_shldi_epi16(A, B, I) \ |
| 312 | (__m256i)__builtin_ia32_vpshldw256((__v16hi)(__m256i)(A), \ |
| 313 | (__v16hi)(__m256i)(B), (int)(I)) |
| 314 | |
| 315 | #define _mm256_mask_shldi_epi16(S, U, A, B, I) \ |
| 316 | (__m256i)__builtin_ia32_selectw_256((__mmask16)(U), \ |
| 317 | (__v16hi)_mm256_shldi_epi16((A), (B), (I)), \ |
| 318 | (__v16hi)(__m256i)(S)) |
| 319 | |
| 320 | #define _mm256_maskz_shldi_epi16(U, A, B, I) \ |
| 321 | (__m256i)__builtin_ia32_selectw_256((__mmask16)(U), \ |
| 322 | (__v16hi)_mm256_shldi_epi16((A), (B), (I)), \ |
| 323 | (__v16hi)_mm256_setzero_si256()) |
| 324 | |
| 325 | #define _mm_shldi_epi16(A, B, I) \ |
| 326 | (__m128i)__builtin_ia32_vpshldw128((__v8hi)(__m128i)(A), \ |
| 327 | (__v8hi)(__m128i)(B), (int)(I)) |
| 328 | |
| 329 | #define _mm_mask_shldi_epi16(S, U, A, B, I) \ |
| 330 | (__m128i)__builtin_ia32_selectw_128((__mmask8)(U), \ |
| 331 | (__v8hi)_mm_shldi_epi16((A), (B), (I)), \ |
| 332 | (__v8hi)(__m128i)(S)) |
| 333 | |
| 334 | #define _mm_maskz_shldi_epi16(U, A, B, I) \ |
| 335 | (__m128i)__builtin_ia32_selectw_128((__mmask8)(U), \ |
| 336 | (__v8hi)_mm_shldi_epi16((A), (B), (I)), \ |
| 337 | (__v8hi)_mm_setzero_si128()) |
| 338 | |
| 339 | #define _mm256_shrdi_epi64(A, B, I) \ |
| 340 | (__m256i)__builtin_ia32_vpshrdq256((__v4di)(__m256i)(A), \ |
| 341 | (__v4di)(__m256i)(B), (int)(I)) |
| 342 | |
| 343 | #define _mm256_mask_shrdi_epi64(S, U, A, B, I) \ |
| 344 | (__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \ |
| 345 | (__v4di)_mm256_shrdi_epi64((A), (B), (I)), \ |
| 346 | (__v4di)(__m256i)(S)) |
| 347 | |
| 348 | #define _mm256_maskz_shrdi_epi64(U, A, B, I) \ |
| 349 | (__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \ |
| 350 | (__v4di)_mm256_shrdi_epi64((A), (B), (I)), \ |
| 351 | (__v4di)_mm256_setzero_si256()) |
| 352 | |
| 353 | #define _mm_shrdi_epi64(A, B, I) \ |
| 354 | (__m128i)__builtin_ia32_vpshrdq128((__v2di)(__m128i)(A), \ |
| 355 | (__v2di)(__m128i)(B), (int)(I)) |
| 356 | |
| 357 | #define _mm_mask_shrdi_epi64(S, U, A, B, I) \ |
| 358 | (__m128i)__builtin_ia32_selectq_128((__mmask8)(U), \ |
| 359 | (__v2di)_mm_shrdi_epi64((A), (B), (I)), \ |
| 360 | (__v2di)(__m128i)(S)) |
| 361 | |
| 362 | #define _mm_maskz_shrdi_epi64(U, A, B, I) \ |
| 363 | (__m128i)__builtin_ia32_selectq_128((__mmask8)(U), \ |
| 364 | (__v2di)_mm_shrdi_epi64((A), (B), (I)), \ |
| 365 | (__v2di)_mm_setzero_si128()) |
| 366 | |
| 367 | #define _mm256_shrdi_epi32(A, B, I) \ |
| 368 | (__m256i)__builtin_ia32_vpshrdd256((__v8si)(__m256i)(A), \ |
| 369 | (__v8si)(__m256i)(B), (int)(I)) |
| 370 | |
| 371 | #define _mm256_mask_shrdi_epi32(S, U, A, B, I) \ |
| 372 | (__m256i)__builtin_ia32_selectd_256((__mmask8)(U), \ |
| 373 | (__v8si)_mm256_shrdi_epi32((A), (B), (I)), \ |
| 374 | (__v8si)(__m256i)(S)) |
| 375 | |
| 376 | #define _mm256_maskz_shrdi_epi32(U, A, B, I) \ |
| 377 | (__m256i)__builtin_ia32_selectd_256((__mmask8)(U), \ |
| 378 | (__v8si)_mm256_shrdi_epi32((A), (B), (I)), \ |
| 379 | (__v8si)_mm256_setzero_si256()) |
| 380 | |
| 381 | #define _mm_shrdi_epi32(A, B, I) \ |
| 382 | (__m128i)__builtin_ia32_vpshrdd128((__v4si)(__m128i)(A), \ |
| 383 | (__v4si)(__m128i)(B), (int)(I)) |
| 384 | |
| 385 | #define _mm_mask_shrdi_epi32(S, U, A, B, I) \ |
| 386 | (__m128i)__builtin_ia32_selectd_128((__mmask8)(U), \ |
| 387 | (__v4si)_mm_shrdi_epi32((A), (B), (I)), \ |
| 388 | (__v4si)(__m128i)(S)) |
| 389 | |
| 390 | #define _mm_maskz_shrdi_epi32(U, A, B, I) \ |
| 391 | (__m128i)__builtin_ia32_selectd_128((__mmask8)(U), \ |
| 392 | (__v4si)_mm_shrdi_epi32((A), (B), (I)), \ |
| 393 | (__v4si)_mm_setzero_si128()) |
| 394 | |
| 395 | #define _mm256_shrdi_epi16(A, B, I) \ |
| 396 | (__m256i)__builtin_ia32_vpshrdw256((__v16hi)(__m256i)(A), \ |
| 397 | (__v16hi)(__m256i)(B), (int)(I)) |
| 398 | |
| 399 | #define _mm256_mask_shrdi_epi16(S, U, A, B, I) \ |
| 400 | (__m256i)__builtin_ia32_selectw_256((__mmask16)(U), \ |
| 401 | (__v16hi)_mm256_shrdi_epi16((A), (B), (I)), \ |
| 402 | (__v16hi)(__m256i)(S)) |
| 403 | |
| 404 | #define _mm256_maskz_shrdi_epi16(U, A, B, I) \ |
| 405 | (__m256i)__builtin_ia32_selectw_256((__mmask16)(U), \ |
| 406 | (__v16hi)_mm256_shrdi_epi16((A), (B), (I)), \ |
| 407 | (__v16hi)_mm256_setzero_si256()) |
| 408 | |
| 409 | #define _mm_shrdi_epi16(A, B, I) \ |
| 410 | (__m128i)__builtin_ia32_vpshrdw128((__v8hi)(__m128i)(A), \ |
| 411 | (__v8hi)(__m128i)(B), (int)(I)) |
| 412 | |
| 413 | #define _mm_mask_shrdi_epi16(S, U, A, B, I) \ |
| 414 | (__m128i)__builtin_ia32_selectw_128((__mmask8)(U), \ |
| 415 | (__v8hi)_mm_shrdi_epi16((A), (B), (I)), \ |
| 416 | (__v8hi)(__m128i)(S)) |
| 417 | |
| 418 | #define _mm_maskz_shrdi_epi16(U, A, B, I) \ |
| 419 | (__m128i)__builtin_ia32_selectw_128((__mmask8)(U), \ |
| 420 | (__v8hi)_mm_shrdi_epi16((A), (B), (I)), \ |
| 421 | (__v8hi)_mm_setzero_si128()) |
| 422 | |
| 423 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 424 | _mm256_mask_shldv_epi64(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B) |
| 425 | { |
| 426 | return (__m256i) __builtin_ia32_vpshldvq256_mask ((__v4di) __S, |
| 427 | (__v4di) __A, |
| 428 | (__v4di) __B, |
| 429 | __U); |
| 430 | } |
| 431 | |
| 432 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 433 | _mm256_maskz_shldv_epi64(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B) |
| 434 | { |
| 435 | return (__m256i) __builtin_ia32_vpshldvq256_maskz ((__v4di) __S, |
| 436 | (__v4di) __A, |
| 437 | (__v4di) __B, |
| 438 | __U); |
| 439 | } |
| 440 | |
| 441 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 442 | _mm256_shldv_epi64(__m256i __S, __m256i __A, __m256i __B) |
| 443 | { |
| 444 | return (__m256i) __builtin_ia32_vpshldvq256_mask ((__v4di) __S, |
| 445 | (__v4di) __A, |
| 446 | (__v4di) __B, |
| 447 | (__mmask8) -1); |
| 448 | } |
| 449 | |
| 450 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 451 | _mm_mask_shldv_epi64(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B) |
| 452 | { |
| 453 | return (__m128i) __builtin_ia32_vpshldvq128_mask ((__v2di) __S, |
| 454 | (__v2di) __A, |
| 455 | (__v2di) __B, |
| 456 | __U); |
| 457 | } |
| 458 | |
| 459 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 460 | _mm_maskz_shldv_epi64(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B) |
| 461 | { |
| 462 | return (__m128i) __builtin_ia32_vpshldvq128_maskz ((__v2di) __S, |
| 463 | (__v2di) __A, |
| 464 | (__v2di) __B, |
| 465 | __U); |
| 466 | } |
| 467 | |
| 468 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 469 | _mm_shldv_epi64(__m128i __S, __m128i __A, __m128i __B) |
| 470 | { |
| 471 | return (__m128i) __builtin_ia32_vpshldvq128_mask ((__v2di) __S, |
| 472 | (__v2di) __A, |
| 473 | (__v2di) __B, |
| 474 | (__mmask8) -1); |
| 475 | } |
| 476 | |
| 477 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 478 | _mm256_mask_shldv_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B) |
| 479 | { |
| 480 | return (__m256i) __builtin_ia32_vpshldvd256_mask ((__v8si) __S, |
| 481 | (__v8si) __A, |
| 482 | (__v8si) __B, |
| 483 | __U); |
| 484 | } |
| 485 | |
| 486 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 487 | _mm256_maskz_shldv_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B) |
| 488 | { |
| 489 | return (__m256i) __builtin_ia32_vpshldvd256_maskz ((__v8si) __S, |
| 490 | (__v8si) __A, |
| 491 | (__v8si) __B, |
| 492 | __U); |
| 493 | } |
| 494 | |
| 495 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 496 | _mm256_shldv_epi32(__m256i __S, __m256i __A, __m256i __B) |
| 497 | { |
| 498 | return (__m256i) __builtin_ia32_vpshldvd256_mask ((__v8si) __S, |
| 499 | (__v8si) __A, |
| 500 | (__v8si) __B, |
| 501 | (__mmask8) -1); |
| 502 | } |
| 503 | |
| 504 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 505 | _mm_mask_shldv_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B) |
| 506 | { |
| 507 | return (__m128i) __builtin_ia32_vpshldvd128_mask ((__v4si) __S, |
| 508 | (__v4si) __A, |
| 509 | (__v4si) __B, |
| 510 | __U); |
| 511 | } |
| 512 | |
| 513 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 514 | _mm_maskz_shldv_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B) |
| 515 | { |
| 516 | return (__m128i) __builtin_ia32_vpshldvd128_maskz ((__v4si) __S, |
| 517 | (__v4si) __A, |
| 518 | (__v4si) __B, |
| 519 | __U); |
| 520 | } |
| 521 | |
| 522 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 523 | _mm_shldv_epi32(__m128i __S, __m128i __A, __m128i __B) |
| 524 | { |
| 525 | return (__m128i) __builtin_ia32_vpshldvd128_mask ((__v4si) __S, |
| 526 | (__v4si) __A, |
| 527 | (__v4si) __B, |
| 528 | (__mmask8) -1); |
| 529 | } |
| 530 | |
| 531 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 532 | _mm256_mask_shldv_epi16(__m256i __S, __mmask16 __U, __m256i __A, __m256i __B) |
| 533 | { |
| 534 | return (__m256i) __builtin_ia32_vpshldvw256_mask ((__v16hi) __S, |
| 535 | (__v16hi) __A, |
| 536 | (__v16hi) __B, |
| 537 | __U); |
| 538 | } |
| 539 | |
| 540 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 541 | _mm256_maskz_shldv_epi16(__mmask16 __U, __m256i __S, __m256i __A, __m256i __B) |
| 542 | { |
| 543 | return (__m256i) __builtin_ia32_vpshldvw256_maskz ((__v16hi) __S, |
| 544 | (__v16hi) __A, |
| 545 | (__v16hi) __B, |
| 546 | __U); |
| 547 | } |
| 548 | |
| 549 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 550 | _mm256_shldv_epi16(__m256i __S, __m256i __A, __m256i __B) |
| 551 | { |
| 552 | return (__m256i) __builtin_ia32_vpshldvw256_mask ((__v16hi) __S, |
| 553 | (__v16hi) __A, |
| 554 | (__v16hi) __B, |
| 555 | (__mmask16) -1); |
| 556 | } |
| 557 | |
| 558 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 559 | _mm_mask_shldv_epi16(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B) |
| 560 | { |
| 561 | return (__m128i) __builtin_ia32_vpshldvw128_mask ((__v8hi) __S, |
| 562 | (__v8hi) __A, |
| 563 | (__v8hi) __B, |
| 564 | __U); |
| 565 | } |
| 566 | |
| 567 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 568 | _mm_maskz_shldv_epi16(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B) |
| 569 | { |
| 570 | return (__m128i) __builtin_ia32_vpshldvw128_maskz ((__v8hi) __S, |
| 571 | (__v8hi) __A, |
| 572 | (__v8hi) __B, |
| 573 | __U); |
| 574 | } |
| 575 | |
| 576 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 577 | _mm_shldv_epi16(__m128i __S, __m128i __A, __m128i __B) |
| 578 | { |
| 579 | return (__m128i) __builtin_ia32_vpshldvw128_mask ((__v8hi) __S, |
| 580 | (__v8hi) __A, |
| 581 | (__v8hi) __B, |
| 582 | (__mmask8) -1); |
| 583 | } |
| 584 | |
| 585 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 586 | _mm256_mask_shrdv_epi64(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B) |
| 587 | { |
| 588 | return (__m256i) __builtin_ia32_vpshrdvq256_mask ((__v4di) __S, |
| 589 | (__v4di) __A, |
| 590 | (__v4di) __B, |
| 591 | __U); |
| 592 | } |
| 593 | |
| 594 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 595 | _mm256_maskz_shrdv_epi64(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B) |
| 596 | { |
| 597 | return (__m256i) __builtin_ia32_vpshrdvq256_maskz ((__v4di) __S, |
| 598 | (__v4di) __A, |
| 599 | (__v4di) __B, |
| 600 | __U); |
| 601 | } |
| 602 | |
| 603 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 604 | _mm256_shrdv_epi64(__m256i __S, __m256i __A, __m256i __B) |
| 605 | { |
| 606 | return (__m256i) __builtin_ia32_vpshrdvq256_mask ((__v4di) __S, |
| 607 | (__v4di) __A, |
| 608 | (__v4di) __B, |
| 609 | (__mmask8) -1); |
| 610 | } |
| 611 | |
| 612 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 613 | _mm_mask_shrdv_epi64(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B) |
| 614 | { |
| 615 | return (__m128i) __builtin_ia32_vpshrdvq128_mask ((__v2di) __S, |
| 616 | (__v2di) __A, |
| 617 | (__v2di) __B, |
| 618 | __U); |
| 619 | } |
| 620 | |
| 621 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 622 | _mm_maskz_shrdv_epi64(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B) |
| 623 | { |
| 624 | return (__m128i) __builtin_ia32_vpshrdvq128_maskz ((__v2di) __S, |
| 625 | (__v2di) __A, |
| 626 | (__v2di) __B, |
| 627 | __U); |
| 628 | } |
| 629 | |
| 630 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 631 | _mm_shrdv_epi64(__m128i __S, __m128i __A, __m128i __B) |
| 632 | { |
| 633 | return (__m128i) __builtin_ia32_vpshrdvq128_mask ((__v2di) __S, |
| 634 | (__v2di) __A, |
| 635 | (__v2di) __B, |
| 636 | (__mmask8) -1); |
| 637 | } |
| 638 | |
| 639 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 640 | _mm256_mask_shrdv_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B) |
| 641 | { |
| 642 | return (__m256i) __builtin_ia32_vpshrdvd256_mask ((__v8si) __S, |
| 643 | (__v8si) __A, |
| 644 | (__v8si) __B, |
| 645 | __U); |
| 646 | } |
| 647 | |
| 648 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 649 | _mm256_maskz_shrdv_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B) |
| 650 | { |
| 651 | return (__m256i) __builtin_ia32_vpshrdvd256_maskz ((__v8si) __S, |
| 652 | (__v8si) __A, |
| 653 | (__v8si) __B, |
| 654 | __U); |
| 655 | } |
| 656 | |
| 657 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 658 | _mm256_shrdv_epi32(__m256i __S, __m256i __A, __m256i __B) |
| 659 | { |
| 660 | return (__m256i) __builtin_ia32_vpshrdvd256_mask ((__v8si) __S, |
| 661 | (__v8si) __A, |
| 662 | (__v8si) __B, |
| 663 | (__mmask8) -1); |
| 664 | } |
| 665 | |
| 666 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 667 | _mm_mask_shrdv_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B) |
| 668 | { |
| 669 | return (__m128i) __builtin_ia32_vpshrdvd128_mask ((__v4si) __S, |
| 670 | (__v4si) __A, |
| 671 | (__v4si) __B, |
| 672 | __U); |
| 673 | } |
| 674 | |
| 675 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 676 | _mm_maskz_shrdv_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B) |
| 677 | { |
| 678 | return (__m128i) __builtin_ia32_vpshrdvd128_maskz ((__v4si) __S, |
| 679 | (__v4si) __A, |
| 680 | (__v4si) __B, |
| 681 | __U); |
| 682 | } |
| 683 | |
| 684 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 685 | _mm_shrdv_epi32(__m128i __S, __m128i __A, __m128i __B) |
| 686 | { |
| 687 | return (__m128i) __builtin_ia32_vpshrdvd128_mask ((__v4si) __S, |
| 688 | (__v4si) __A, |
| 689 | (__v4si) __B, |
| 690 | (__mmask8) -1); |
| 691 | } |
| 692 | |
| 693 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 694 | _mm256_mask_shrdv_epi16(__m256i __S, __mmask16 __U, __m256i __A, __m256i __B) |
| 695 | { |
| 696 | return (__m256i) __builtin_ia32_vpshrdvw256_mask ((__v16hi) __S, |
| 697 | (__v16hi) __A, |
| 698 | (__v16hi) __B, |
| 699 | __U); |
| 700 | } |
| 701 | |
| 702 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 703 | _mm256_maskz_shrdv_epi16(__mmask16 __U, __m256i __S, __m256i __A, __m256i __B) |
| 704 | { |
| 705 | return (__m256i) __builtin_ia32_vpshrdvw256_maskz ((__v16hi) __S, |
| 706 | (__v16hi) __A, |
| 707 | (__v16hi) __B, |
| 708 | __U); |
| 709 | } |
| 710 | |
| 711 | static __inline__ __m256i __DEFAULT_FN_ATTRS256 |
| 712 | _mm256_shrdv_epi16(__m256i __S, __m256i __A, __m256i __B) |
| 713 | { |
| 714 | return (__m256i) __builtin_ia32_vpshrdvw256_mask ((__v16hi) __S, |
| 715 | (__v16hi) __A, |
| 716 | (__v16hi) __B, |
| 717 | (__mmask16) -1); |
| 718 | } |
| 719 | |
| 720 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 721 | _mm_mask_shrdv_epi16(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B) |
| 722 | { |
| 723 | return (__m128i) __builtin_ia32_vpshrdvw128_mask ((__v8hi) __S, |
| 724 | (__v8hi) __A, |
| 725 | (__v8hi) __B, |
| 726 | __U); |
| 727 | } |
| 728 | |
| 729 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 730 | _mm_maskz_shrdv_epi16(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B) |
| 731 | { |
| 732 | return (__m128i) __builtin_ia32_vpshrdvw128_maskz ((__v8hi) __S, |
| 733 | (__v8hi) __A, |
| 734 | (__v8hi) __B, |
| 735 | __U); |
| 736 | } |
| 737 | |
| 738 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 |
| 739 | _mm_shrdv_epi16(__m128i __S, __m128i __A, __m128i __B) |
| 740 | { |
| 741 | return (__m128i) __builtin_ia32_vpshrdvw128_mask ((__v8hi) __S, |
| 742 | (__v8hi) __A, |
| 743 | (__v8hi) __B, |
| 744 | (__mmask8) -1); |
| 745 | } |
| 746 | |
| 747 | |
| 748 | #undef __DEFAULT_FN_ATTRS128 |
| 749 | #undef __DEFAULT_FN_ATTRS256 |
| 750 | |
| 751 | #endif |